scsi: lpfc: Fix list corruption detected in lpfc_put_sgl_per_hdwq
[linux-2.6-block.git] / drivers / scsi / lpfc / lpfc_init.c
CommitLineData
dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
0d041215 4 * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term *
3e21d1cb 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
50611577 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
c44ce173 7 * EMULEX and SLI are trademarks of Emulex. *
d080abe0 8 * www.broadcom.com *
c44ce173 9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e 10 * *
11 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC
12 * modify it under the terms of version 2 of the GNU General *
13 * Public License as published by the Free Software Foundation. *
14 * This program is distributed in the hope that it will be useful. *
15 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
16 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
18 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
19 * TO BE LEGALLY INVALID. See the GNU General Public License for *
20 * more details, a copy of which can be found in the file COPYING *
21 * included with this package. *
dea3101e 22 *******************************************************************/
23
dea3101e 24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/idr.h>
28#include <linux/interrupt.h>
acf3368f 29#include <linux/module.h>
dea3101e 30#include <linux/kthread.h>
31#include <linux/pci.h>
32#include <linux/spinlock.h>
92d7f7b0 33#include <linux/ctype.h>
0d878419 34#include <linux/aer.h>
5a0e3ad6 35#include <linux/slab.h>
52d52440 36#include <linux/firmware.h>
3ef6d24c 37#include <linux/miscdevice.h>
7bb03bbf 38#include <linux/percpu.h>
895427bd 39#include <linux/msi.h>
6a828b0f 40#include <linux/irq.h>
286871a6 41#include <linux/bitops.h>
31f06d2e 42#include <linux/crash_dump.h>
dea3101e 43
91886523 44#include <scsi/scsi.h>
dea3101e 45#include <scsi/scsi_device.h>
46#include <scsi/scsi_host.h>
47#include <scsi/scsi_transport_fc.h>
86c67379
JS
48#include <scsi/scsi_tcq.h>
49#include <scsi/fc/fc_fs.h>
50
51#include <linux/nvme-fc-driver.h>
dea3101e 52
da0436e9 53#include "lpfc_hw4.h"
dea3101e 54#include "lpfc_hw.h"
55#include "lpfc_sli.h"
da0436e9 56#include "lpfc_sli4.h"
ea2151b4 57#include "lpfc_nl.h"
dea3101e 58#include "lpfc_disc.h"
dea3101e 59#include "lpfc.h"
895427bd
JS
60#include "lpfc_scsi.h"
61#include "lpfc_nvme.h"
86c67379 62#include "lpfc_nvmet.h"
dea3101e 63#include "lpfc_logmsg.h"
64#include "lpfc_crtn.h"
92d7f7b0 65#include "lpfc_vport.h"
dea3101e 66#include "lpfc_version.h"
12f44457 67#include "lpfc_ids.h"
dea3101e 68
7bb03bbf 69/* Used when mapping IRQ vectors in a driver centric manner */
d7b761b0 70static uint32_t lpfc_present_cpu;
7bb03bbf 71
dea3101e 72static void lpfc_get_hba_model_desc(struct lpfc_hba *, uint8_t *, uint8_t *);
73static int lpfc_post_rcv_buf(struct lpfc_hba *);
5350d872 74static int lpfc_sli4_queue_verify(struct lpfc_hba *);
da0436e9
JS
75static int lpfc_create_bootstrap_mbox(struct lpfc_hba *);
76static int lpfc_setup_endian_order(struct lpfc_hba *);
da0436e9 77static void lpfc_destroy_bootstrap_mbox(struct lpfc_hba *);
8a9d2e80 78static void lpfc_free_els_sgl_list(struct lpfc_hba *);
f358dd0c 79static void lpfc_free_nvmet_sgl_list(struct lpfc_hba *);
8a9d2e80 80static void lpfc_init_sgl_list(struct lpfc_hba *);
da0436e9
JS
81static int lpfc_init_active_sgl_array(struct lpfc_hba *);
82static void lpfc_free_active_sgl(struct lpfc_hba *);
83static int lpfc_hba_down_post_s3(struct lpfc_hba *phba);
84static int lpfc_hba_down_post_s4(struct lpfc_hba *phba);
85static int lpfc_sli4_cq_event_pool_create(struct lpfc_hba *);
86static void lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *);
87static void lpfc_sli4_cq_event_release_all(struct lpfc_hba *);
618a5230
JS
88static void lpfc_sli4_disable_intr(struct lpfc_hba *);
89static uint32_t lpfc_sli4_enable_intr(struct lpfc_hba *, uint32_t);
1ba981fd 90static void lpfc_sli4_oas_verify(struct lpfc_hba *phba);
6a828b0f 91static uint16_t lpfc_find_cpu_handle(struct lpfc_hba *, uint16_t, int);
aa6ff309 92static void lpfc_setup_bg(struct lpfc_hba *, struct Scsi_Host *);
dea3101e 93
94static struct scsi_transport_template *lpfc_transport_template = NULL;
92d7f7b0 95static struct scsi_transport_template *lpfc_vport_transport_template = NULL;
dea3101e 96static DEFINE_IDR(lpfc_hba_index);
f358dd0c 97#define LPFC_NVMET_BUF_POST 254
dea3101e 98
e59058c4 99/**
3621a710 100 * lpfc_config_port_prep - Perform lpfc initialization prior to config port
e59058c4
JS
101 * @phba: pointer to lpfc hba data structure.
102 *
103 * This routine will do LPFC initialization prior to issuing the CONFIG_PORT
104 * mailbox command. It retrieves the revision information from the HBA and
105 * collects the Vital Product Data (VPD) about the HBA for preparing the
106 * configuration of the HBA.
107 *
108 * Return codes:
109 * 0 - success.
110 * -ERESTART - requests the SLI layer to reset the HBA and try again.
111 * Any other value - indicates an error.
112 **/
dea3101e 113int
2e0fef85 114lpfc_config_port_prep(struct lpfc_hba *phba)
dea3101e 115{
116 lpfc_vpd_t *vp = &phba->vpd;
117 int i = 0, rc;
118 LPFC_MBOXQ_t *pmb;
119 MAILBOX_t *mb;
120 char *lpfc_vpd_data = NULL;
121 uint16_t offset = 0;
122 static char licensed[56] =
123 "key unlock for use with gnu public licensed code only\0";
65a29c16 124 static int init_key = 1;
dea3101e 125
126 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
127 if (!pmb) {
2e0fef85 128 phba->link_state = LPFC_HBA_ERROR;
dea3101e 129 return -ENOMEM;
130 }
131
04c68496 132 mb = &pmb->u.mb;
2e0fef85 133 phba->link_state = LPFC_INIT_MBX_CMDS;
dea3101e 134
135 if (lpfc_is_LC_HBA(phba->pcidev->device)) {
65a29c16
JS
136 if (init_key) {
137 uint32_t *ptext = (uint32_t *) licensed;
dea3101e 138
65a29c16
JS
139 for (i = 0; i < 56; i += sizeof (uint32_t), ptext++)
140 *ptext = cpu_to_be32(*ptext);
141 init_key = 0;
142 }
dea3101e 143
144 lpfc_read_nv(phba, pmb);
145 memset((char*)mb->un.varRDnvp.rsvd3, 0,
146 sizeof (mb->un.varRDnvp.rsvd3));
147 memcpy((char*)mb->un.varRDnvp.rsvd3, licensed,
148 sizeof (licensed));
149
150 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
151
152 if (rc != MBX_SUCCESS) {
ed957684 153 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
e8b62011 154 "0324 Config Port initialization "
dea3101e 155 "error, mbxCmd x%x READ_NVPARM, "
156 "mbxStatus x%x\n",
dea3101e 157 mb->mbxCommand, mb->mbxStatus);
158 mempool_free(pmb, phba->mbox_mem_pool);
159 return -ERESTART;
160 }
161 memcpy(phba->wwnn, (char *)mb->un.varRDnvp.nodename,
2e0fef85
JS
162 sizeof(phba->wwnn));
163 memcpy(phba->wwpn, (char *)mb->un.varRDnvp.portname,
164 sizeof(phba->wwpn));
dea3101e 165 }
166
dfb75133
MW
167 /*
168 * Clear all option bits except LPFC_SLI3_BG_ENABLED,
169 * which was already set in lpfc_get_cfgparam()
170 */
171 phba->sli3_options &= (uint32_t)LPFC_SLI3_BG_ENABLED;
92d7f7b0 172
dea3101e 173 /* Setup and issue mailbox READ REV command */
174 lpfc_read_rev(phba, pmb);
175 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
176 if (rc != MBX_SUCCESS) {
ed957684 177 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011 178 "0439 Adapter failed to init, mbxCmd x%x "
dea3101e 179 "READ_REV, mbxStatus x%x\n",
dea3101e 180 mb->mbxCommand, mb->mbxStatus);
181 mempool_free( pmb, phba->mbox_mem_pool);
182 return -ERESTART;
183 }
184
92d7f7b0 185
1de933f3
JSEC
186 /*
187 * The value of rr must be 1 since the driver set the cv field to 1.
188 * This setting requires the FW to set all revision fields.
dea3101e 189 */
1de933f3 190 if (mb->un.varRdRev.rr == 0) {
dea3101e 191 vp->rev.rBit = 0;
1de933f3 192 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011
JS
193 "0440 Adapter failed to init, READ_REV has "
194 "missing revision information.\n");
dea3101e 195 mempool_free(pmb, phba->mbox_mem_pool);
196 return -ERESTART;
dea3101e 197 }
198
495a714c
JS
199 if (phba->sli_rev == 3 && !mb->un.varRdRev.v3rsp) {
200 mempool_free(pmb, phba->mbox_mem_pool);
ed957684 201 return -EINVAL;
495a714c 202 }
ed957684 203
dea3101e 204 /* Save information as VPD data */
1de933f3 205 vp->rev.rBit = 1;
92d7f7b0 206 memcpy(&vp->sli3Feat, &mb->un.varRdRev.sli3Feat, sizeof(uint32_t));
1de933f3
JSEC
207 vp->rev.sli1FwRev = mb->un.varRdRev.sli1FwRev;
208 memcpy(vp->rev.sli1FwName, (char*) mb->un.varRdRev.sli1FwName, 16);
209 vp->rev.sli2FwRev = mb->un.varRdRev.sli2FwRev;
210 memcpy(vp->rev.sli2FwName, (char *) mb->un.varRdRev.sli2FwName, 16);
dea3101e 211 vp->rev.biuRev = mb->un.varRdRev.biuRev;
212 vp->rev.smRev = mb->un.varRdRev.smRev;
213 vp->rev.smFwRev = mb->un.varRdRev.un.smFwRev;
214 vp->rev.endecRev = mb->un.varRdRev.endecRev;
215 vp->rev.fcphHigh = mb->un.varRdRev.fcphHigh;
216 vp->rev.fcphLow = mb->un.varRdRev.fcphLow;
217 vp->rev.feaLevelHigh = mb->un.varRdRev.feaLevelHigh;
218 vp->rev.feaLevelLow = mb->un.varRdRev.feaLevelLow;
219 vp->rev.postKernRev = mb->un.varRdRev.postKernRev;
220 vp->rev.opFwRev = mb->un.varRdRev.opFwRev;
221
92d7f7b0
JS
222 /* If the sli feature level is less then 9, we must
223 * tear down all RPIs and VPIs on link down if NPIV
224 * is enabled.
225 */
226 if (vp->rev.feaLevelHigh < 9)
227 phba->sli3_options |= LPFC_SLI3_VPORT_TEARDOWN;
228
dea3101e 229 if (lpfc_is_LC_HBA(phba->pcidev->device))
230 memcpy(phba->RandomData, (char *)&mb->un.varWords[24],
231 sizeof (phba->RandomData));
232
dea3101e 233 /* Get adapter VPD information */
dea3101e 234 lpfc_vpd_data = kmalloc(DMP_VPD_SIZE, GFP_KERNEL);
235 if (!lpfc_vpd_data)
d7c255b2 236 goto out_free_mbox;
dea3101e 237 do {
a0c87cbd 238 lpfc_dump_mem(phba, pmb, offset, DMP_REGION_VPD);
dea3101e 239 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
240
241 if (rc != MBX_SUCCESS) {
242 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011 243 "0441 VPD not present on adapter, "
dea3101e 244 "mbxCmd x%x DUMP VPD, mbxStatus x%x\n",
dea3101e 245 mb->mbxCommand, mb->mbxStatus);
74b72a59 246 mb->un.varDmp.word_cnt = 0;
dea3101e 247 }
04c68496
JS
248 /* dump mem may return a zero when finished or we got a
249 * mailbox error, either way we are done.
250 */
251 if (mb->un.varDmp.word_cnt == 0)
252 break;
74b72a59
JW
253 if (mb->un.varDmp.word_cnt > DMP_VPD_SIZE - offset)
254 mb->un.varDmp.word_cnt = DMP_VPD_SIZE - offset;
d7c255b2
JS
255 lpfc_sli_pcimem_bcopy(((uint8_t *)mb) + DMP_RSP_OFFSET,
256 lpfc_vpd_data + offset,
92d7f7b0 257 mb->un.varDmp.word_cnt);
dea3101e 258 offset += mb->un.varDmp.word_cnt;
74b72a59
JW
259 } while (mb->un.varDmp.word_cnt && offset < DMP_VPD_SIZE);
260 lpfc_parse_vpd(phba, lpfc_vpd_data, offset);
dea3101e 261
262 kfree(lpfc_vpd_data);
dea3101e 263out_free_mbox:
264 mempool_free(pmb, phba->mbox_mem_pool);
265 return 0;
266}
267
e59058c4 268/**
3621a710 269 * lpfc_config_async_cmpl - Completion handler for config async event mbox cmd
e59058c4
JS
270 * @phba: pointer to lpfc hba data structure.
271 * @pmboxq: pointer to the driver internal queue element for mailbox command.
272 *
273 * This is the completion handler for driver's configuring asynchronous event
274 * mailbox command to the device. If the mailbox command returns successfully,
275 * it will set internal async event support flag to 1; otherwise, it will
276 * set internal async event support flag to 0.
277 **/
57127f15
JS
278static void
279lpfc_config_async_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
280{
04c68496 281 if (pmboxq->u.mb.mbxStatus == MBX_SUCCESS)
57127f15
JS
282 phba->temp_sensor_support = 1;
283 else
284 phba->temp_sensor_support = 0;
285 mempool_free(pmboxq, phba->mbox_mem_pool);
286 return;
287}
288
97207482 289/**
3621a710 290 * lpfc_dump_wakeup_param_cmpl - dump memory mailbox command completion handler
97207482
JS
291 * @phba: pointer to lpfc hba data structure.
292 * @pmboxq: pointer to the driver internal queue element for mailbox command.
293 *
294 * This is the completion handler for dump mailbox command for getting
295 * wake up parameters. When this command complete, the response contain
296 * Option rom version of the HBA. This function translate the version number
297 * into a human readable string and store it in OptionROMVersion.
298 **/
299static void
300lpfc_dump_wakeup_param_cmpl(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmboxq)
301{
302 struct prog_id *prg;
303 uint32_t prog_id_word;
304 char dist = ' ';
305 /* character array used for decoding dist type. */
306 char dist_char[] = "nabx";
307
04c68496 308 if (pmboxq->u.mb.mbxStatus != MBX_SUCCESS) {
9f1e1b50 309 mempool_free(pmboxq, phba->mbox_mem_pool);
97207482 310 return;
9f1e1b50 311 }
97207482
JS
312
313 prg = (struct prog_id *) &prog_id_word;
314
315 /* word 7 contain option rom version */
04c68496 316 prog_id_word = pmboxq->u.mb.un.varWords[7];
97207482
JS
317
318 /* Decode the Option rom version word to a readable string */
319 if (prg->dist < 4)
320 dist = dist_char[prg->dist];
321
322 if ((prg->dist == 3) && (prg->num == 0))
a2fc4aef 323 snprintf(phba->OptionROMVersion, 32, "%d.%d%d",
97207482
JS
324 prg->ver, prg->rev, prg->lev);
325 else
a2fc4aef 326 snprintf(phba->OptionROMVersion, 32, "%d.%d%d%c%d",
97207482
JS
327 prg->ver, prg->rev, prg->lev,
328 dist, prg->num);
9f1e1b50 329 mempool_free(pmboxq, phba->mbox_mem_pool);
97207482
JS
330 return;
331}
332
0558056c
JS
333/**
334 * lpfc_update_vport_wwn - Updates the fc_nodename, fc_portname,
335 * cfg_soft_wwnn, cfg_soft_wwpn
336 * @vport: pointer to lpfc vport data structure.
337 *
338 *
339 * Return codes
340 * None.
341 **/
342void
343lpfc_update_vport_wwn(struct lpfc_vport *vport)
344{
aeb3c817
JS
345 uint8_t vvvl = vport->fc_sparam.cmn.valid_vendor_ver_level;
346 u32 *fawwpn_key = (u32 *)&vport->fc_sparam.un.vendorVersion[0];
347
0558056c
JS
348 /* If the soft name exists then update it using the service params */
349 if (vport->phba->cfg_soft_wwnn)
350 u64_to_wwn(vport->phba->cfg_soft_wwnn,
351 vport->fc_sparam.nodeName.u.wwn);
352 if (vport->phba->cfg_soft_wwpn)
353 u64_to_wwn(vport->phba->cfg_soft_wwpn,
354 vport->fc_sparam.portName.u.wwn);
355
356 /*
357 * If the name is empty or there exists a soft name
358 * then copy the service params name, otherwise use the fc name
359 */
360 if (vport->fc_nodename.u.wwn[0] == 0 || vport->phba->cfg_soft_wwnn)
361 memcpy(&vport->fc_nodename, &vport->fc_sparam.nodeName,
362 sizeof(struct lpfc_name));
363 else
364 memcpy(&vport->fc_sparam.nodeName, &vport->fc_nodename,
365 sizeof(struct lpfc_name));
366
aeb3c817
JS
367 /*
368 * If the port name has changed, then set the Param changes flag
369 * to unreg the login
370 */
371 if (vport->fc_portname.u.wwn[0] != 0 &&
372 memcmp(&vport->fc_portname, &vport->fc_sparam.portName,
373 sizeof(struct lpfc_name)))
374 vport->vport_flag |= FAWWPN_PARAM_CHG;
375
376 if (vport->fc_portname.u.wwn[0] == 0 ||
377 vport->phba->cfg_soft_wwpn ||
378 (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR) ||
379 vport->vport_flag & FAWWPN_SET) {
0558056c
JS
380 memcpy(&vport->fc_portname, &vport->fc_sparam.portName,
381 sizeof(struct lpfc_name));
aeb3c817
JS
382 vport->vport_flag &= ~FAWWPN_SET;
383 if (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR)
384 vport->vport_flag |= FAWWPN_SET;
385 }
0558056c
JS
386 else
387 memcpy(&vport->fc_sparam.portName, &vport->fc_portname,
388 sizeof(struct lpfc_name));
389}
390
e59058c4 391/**
3621a710 392 * lpfc_config_port_post - Perform lpfc initialization after config port
e59058c4
JS
393 * @phba: pointer to lpfc hba data structure.
394 *
395 * This routine will do LPFC initialization after the CONFIG_PORT mailbox
396 * command call. It performs all internal resource and state setups on the
397 * port: post IOCB buffers, enable appropriate host interrupt attentions,
398 * ELS ring timers, etc.
399 *
400 * Return codes
401 * 0 - success.
402 * Any other value - error.
403 **/
dea3101e 404int
2e0fef85 405lpfc_config_port_post(struct lpfc_hba *phba)
dea3101e 406{
2e0fef85 407 struct lpfc_vport *vport = phba->pport;
a257bf90 408 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
dea3101e 409 LPFC_MBOXQ_t *pmb;
410 MAILBOX_t *mb;
411 struct lpfc_dmabuf *mp;
412 struct lpfc_sli *psli = &phba->sli;
413 uint32_t status, timeout;
2e0fef85
JS
414 int i, j;
415 int rc;
dea3101e 416
7af67051
JS
417 spin_lock_irq(&phba->hbalock);
418 /*
419 * If the Config port completed correctly the HBA is not
420 * over heated any more.
421 */
422 if (phba->over_temp_state == HBA_OVER_TEMP)
423 phba->over_temp_state = HBA_NORMAL_TEMP;
424 spin_unlock_irq(&phba->hbalock);
425
dea3101e 426 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
427 if (!pmb) {
2e0fef85 428 phba->link_state = LPFC_HBA_ERROR;
dea3101e 429 return -ENOMEM;
430 }
04c68496 431 mb = &pmb->u.mb;
dea3101e 432
dea3101e 433 /* Get login parameters for NID. */
9f1177a3
JS
434 rc = lpfc_read_sparam(phba, pmb, 0);
435 if (rc) {
436 mempool_free(pmb, phba->mbox_mem_pool);
437 return -ENOMEM;
438 }
439
ed957684 440 pmb->vport = vport;
dea3101e 441 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
ed957684 442 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011 443 "0448 Adapter failed init, mbxCmd x%x "
dea3101e 444 "READ_SPARM mbxStatus x%x\n",
dea3101e 445 mb->mbxCommand, mb->mbxStatus);
2e0fef85 446 phba->link_state = LPFC_HBA_ERROR;
3e1f0718 447 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
9f1177a3 448 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 449 lpfc_mbuf_free(phba, mp->virt, mp->phys);
450 kfree(mp);
451 return -EIO;
452 }
453
3e1f0718 454 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
dea3101e 455
2e0fef85 456 memcpy(&vport->fc_sparam, mp->virt, sizeof (struct serv_parm));
dea3101e 457 lpfc_mbuf_free(phba, mp->virt, mp->phys);
458 kfree(mp);
3e1f0718 459 pmb->ctx_buf = NULL;
0558056c 460 lpfc_update_vport_wwn(vport);
a257bf90
JS
461
462 /* Update the fc_host data structures with new wwn. */
463 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
464 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
21e9a0a5 465 fc_host_max_npiv_vports(shost) = phba->max_vpi;
a257bf90 466
dea3101e 467 /* If no serial number in VPD data, use low 6 bytes of WWNN */
468 /* This should be consolidated into parse_vpd ? - mr */
469 if (phba->SerialNumber[0] == 0) {
470 uint8_t *outptr;
471
2e0fef85 472 outptr = &vport->fc_nodename.u.s.IEEE[0];
dea3101e 473 for (i = 0; i < 12; i++) {
474 status = *outptr++;
475 j = ((status & 0xf0) >> 4);
476 if (j <= 9)
477 phba->SerialNumber[i] =
478 (char)((uint8_t) 0x30 + (uint8_t) j);
479 else
480 phba->SerialNumber[i] =
481 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
482 i++;
483 j = (status & 0xf);
484 if (j <= 9)
485 phba->SerialNumber[i] =
486 (char)((uint8_t) 0x30 + (uint8_t) j);
487 else
488 phba->SerialNumber[i] =
489 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
490 }
491 }
492
dea3101e 493 lpfc_read_config(phba, pmb);
ed957684 494 pmb->vport = vport;
dea3101e 495 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
ed957684 496 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011 497 "0453 Adapter failed to init, mbxCmd x%x "
dea3101e 498 "READ_CONFIG, mbxStatus x%x\n",
dea3101e 499 mb->mbxCommand, mb->mbxStatus);
2e0fef85 500 phba->link_state = LPFC_HBA_ERROR;
dea3101e 501 mempool_free( pmb, phba->mbox_mem_pool);
502 return -EIO;
503 }
504
a0c87cbd
JS
505 /* Check if the port is disabled */
506 lpfc_sli_read_link_ste(phba);
507
dea3101e 508 /* Reset the DFT_HBA_Q_DEPTH to the max xri */
572709e2
JS
509 i = (mb->un.varRdConfig.max_xri + 1);
510 if (phba->cfg_hba_queue_depth > i) {
511 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
512 "3359 HBA queue depth changed from %d to %d\n",
513 phba->cfg_hba_queue_depth, i);
514 phba->cfg_hba_queue_depth = i;
515 }
516
517 /* Reset the DFT_LUN_Q_DEPTH to (max xri >> 3) */
518 i = (mb->un.varRdConfig.max_xri >> 3);
519 if (phba->pport->cfg_lun_queue_depth > i) {
520 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
521 "3360 LUN queue depth changed from %d to %d\n",
522 phba->pport->cfg_lun_queue_depth, i);
523 phba->pport->cfg_lun_queue_depth = i;
524 }
dea3101e 525
526 phba->lmt = mb->un.varRdConfig.lmt;
74b72a59
JW
527
528 /* Get the default values for Model Name and Description */
529 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
530
2e0fef85 531 phba->link_state = LPFC_LINK_DOWN;
dea3101e 532
0b727fea 533 /* Only process IOCBs on ELS ring till hba_state is READY */
895427bd
JS
534 if (psli->sli3_ring[LPFC_EXTRA_RING].sli.sli3.cmdringaddr)
535 psli->sli3_ring[LPFC_EXTRA_RING].flag |= LPFC_STOP_IOCB_EVENT;
536 if (psli->sli3_ring[LPFC_FCP_RING].sli.sli3.cmdringaddr)
537 psli->sli3_ring[LPFC_FCP_RING].flag |= LPFC_STOP_IOCB_EVENT;
dea3101e 538
539 /* Post receive buffers for desired rings */
ed957684
JS
540 if (phba->sli_rev != 3)
541 lpfc_post_rcv_buf(phba);
dea3101e 542
9399627f
JS
543 /*
544 * Configure HBA MSI-X attention conditions to messages if MSI-X mode
545 */
546 if (phba->intr_type == MSIX) {
547 rc = lpfc_config_msi(phba, pmb);
548 if (rc) {
549 mempool_free(pmb, phba->mbox_mem_pool);
550 return -EIO;
551 }
552 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
553 if (rc != MBX_SUCCESS) {
554 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
555 "0352 Config MSI mailbox command "
556 "failed, mbxCmd x%x, mbxStatus x%x\n",
04c68496
JS
557 pmb->u.mb.mbxCommand,
558 pmb->u.mb.mbxStatus);
9399627f
JS
559 mempool_free(pmb, phba->mbox_mem_pool);
560 return -EIO;
561 }
562 }
563
04c68496 564 spin_lock_irq(&phba->hbalock);
9399627f
JS
565 /* Initialize ERATT handling flag */
566 phba->hba_flag &= ~HBA_ERATT_HANDLED;
567
dea3101e 568 /* Enable appropriate host interrupts */
9940b97b
JS
569 if (lpfc_readl(phba->HCregaddr, &status)) {
570 spin_unlock_irq(&phba->hbalock);
571 return -EIO;
572 }
dea3101e 573 status |= HC_MBINT_ENA | HC_ERINT_ENA | HC_LAINT_ENA;
574 if (psli->num_rings > 0)
575 status |= HC_R0INT_ENA;
576 if (psli->num_rings > 1)
577 status |= HC_R1INT_ENA;
578 if (psli->num_rings > 2)
579 status |= HC_R2INT_ENA;
580 if (psli->num_rings > 3)
581 status |= HC_R3INT_ENA;
582
875fbdfe
JSEC
583 if ((phba->cfg_poll & ENABLE_FCP_RING_POLLING) &&
584 (phba->cfg_poll & DISABLE_FCP_RING_INT))
9399627f 585 status &= ~(HC_R0INT_ENA);
875fbdfe 586
dea3101e 587 writel(status, phba->HCregaddr);
588 readl(phba->HCregaddr); /* flush */
2e0fef85 589 spin_unlock_irq(&phba->hbalock);
dea3101e 590
9399627f
JS
591 /* Set up ring-0 (ELS) timer */
592 timeout = phba->fc_ratov * 2;
256ec0d0
JS
593 mod_timer(&vport->els_tmofunc,
594 jiffies + msecs_to_jiffies(1000 * timeout));
9399627f 595 /* Set up heart beat (HB) timer */
256ec0d0
JS
596 mod_timer(&phba->hb_tmofunc,
597 jiffies + msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
598 phba->hb_outstanding = 0;
599 phba->last_completion_time = jiffies;
9399627f 600 /* Set up error attention (ERATT) polling timer */
256ec0d0 601 mod_timer(&phba->eratt_poll,
65791f1f 602 jiffies + msecs_to_jiffies(1000 * phba->eratt_poll_interval));
dea3101e 603
a0c87cbd
JS
604 if (phba->hba_flag & LINK_DISABLED) {
605 lpfc_printf_log(phba,
606 KERN_ERR, LOG_INIT,
607 "2598 Adapter Link is disabled.\n");
608 lpfc_down_link(phba, pmb);
609 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
610 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
611 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
612 lpfc_printf_log(phba,
613 KERN_ERR, LOG_INIT,
614 "2599 Adapter failed to issue DOWN_LINK"
615 " mbox command rc 0x%x\n", rc);
616
617 mempool_free(pmb, phba->mbox_mem_pool);
618 return -EIO;
619 }
e40a02c1 620 } else if (phba->cfg_suppress_link_up == LPFC_INITIALIZE_LINK) {
026abb87
JS
621 mempool_free(pmb, phba->mbox_mem_pool);
622 rc = phba->lpfc_hba_init_link(phba, MBX_NOWAIT);
623 if (rc)
624 return rc;
dea3101e 625 }
626 /* MBOX buffer will be freed in mbox compl */
57127f15 627 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9f1177a3
JS
628 if (!pmb) {
629 phba->link_state = LPFC_HBA_ERROR;
630 return -ENOMEM;
631 }
632
57127f15
JS
633 lpfc_config_async(phba, pmb, LPFC_ELS_RING);
634 pmb->mbox_cmpl = lpfc_config_async_cmpl;
635 pmb->vport = phba->pport;
636 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
dea3101e 637
57127f15
JS
638 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
639 lpfc_printf_log(phba,
640 KERN_ERR,
641 LOG_INIT,
642 "0456 Adapter failed to issue "
e4e74273 643 "ASYNCEVT_ENABLE mbox status x%x\n",
57127f15
JS
644 rc);
645 mempool_free(pmb, phba->mbox_mem_pool);
646 }
97207482
JS
647
648 /* Get Option rom version */
649 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9f1177a3
JS
650 if (!pmb) {
651 phba->link_state = LPFC_HBA_ERROR;
652 return -ENOMEM;
653 }
654
97207482
JS
655 lpfc_dump_wakeup_param(phba, pmb);
656 pmb->mbox_cmpl = lpfc_dump_wakeup_param_cmpl;
657 pmb->vport = phba->pport;
658 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
659
660 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
661 lpfc_printf_log(phba, KERN_ERR, LOG_INIT, "0435 Adapter failed "
e4e74273 662 "to get Option ROM version status x%x\n", rc);
97207482
JS
663 mempool_free(pmb, phba->mbox_mem_pool);
664 }
665
d7c255b2 666 return 0;
ce8b3ce5
JS
667}
668
84d1b006
JS
669/**
670 * lpfc_hba_init_link - Initialize the FC link
671 * @phba: pointer to lpfc hba data structure.
6e7288d9 672 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
84d1b006
JS
673 *
674 * This routine will issue the INIT_LINK mailbox command call.
675 * It is available to other drivers through the lpfc_hba data
676 * structure for use as a delayed link up mechanism with the
677 * module parameter lpfc_suppress_link_up.
678 *
679 * Return code
680 * 0 - success
681 * Any other value - error
682 **/
e399b228 683static int
6e7288d9 684lpfc_hba_init_link(struct lpfc_hba *phba, uint32_t flag)
1b51197d
JS
685{
686 return lpfc_hba_init_link_fc_topology(phba, phba->cfg_topology, flag);
687}
688
689/**
690 * lpfc_hba_init_link_fc_topology - Initialize FC link with desired topology
691 * @phba: pointer to lpfc hba data structure.
692 * @fc_topology: desired fc topology.
693 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
694 *
695 * This routine will issue the INIT_LINK mailbox command call.
696 * It is available to other drivers through the lpfc_hba data
697 * structure for use as a delayed link up mechanism with the
698 * module parameter lpfc_suppress_link_up.
699 *
700 * Return code
701 * 0 - success
702 * Any other value - error
703 **/
704int
705lpfc_hba_init_link_fc_topology(struct lpfc_hba *phba, uint32_t fc_topology,
706 uint32_t flag)
84d1b006
JS
707{
708 struct lpfc_vport *vport = phba->pport;
709 LPFC_MBOXQ_t *pmb;
710 MAILBOX_t *mb;
711 int rc;
712
713 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
714 if (!pmb) {
715 phba->link_state = LPFC_HBA_ERROR;
716 return -ENOMEM;
717 }
718 mb = &pmb->u.mb;
719 pmb->vport = vport;
720
026abb87
JS
721 if ((phba->cfg_link_speed > LPFC_USER_LINK_SPEED_MAX) ||
722 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_1G) &&
723 !(phba->lmt & LMT_1Gb)) ||
724 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_2G) &&
725 !(phba->lmt & LMT_2Gb)) ||
726 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_4G) &&
727 !(phba->lmt & LMT_4Gb)) ||
728 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_8G) &&
729 !(phba->lmt & LMT_8Gb)) ||
730 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_10G) &&
731 !(phba->lmt & LMT_10Gb)) ||
732 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_16G) &&
d38dd52c
JS
733 !(phba->lmt & LMT_16Gb)) ||
734 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_32G) &&
fbd8a6ba
JS
735 !(phba->lmt & LMT_32Gb)) ||
736 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_64G) &&
737 !(phba->lmt & LMT_64Gb))) {
026abb87
JS
738 /* Reset link speed to auto */
739 lpfc_printf_log(phba, KERN_ERR, LOG_LINK_EVENT,
740 "1302 Invalid speed for this board:%d "
741 "Reset link speed to auto.\n",
742 phba->cfg_link_speed);
743 phba->cfg_link_speed = LPFC_USER_LINK_SPEED_AUTO;
744 }
1b51197d 745 lpfc_init_link(phba, pmb, fc_topology, phba->cfg_link_speed);
84d1b006 746 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
1b51197d
JS
747 if (phba->sli_rev < LPFC_SLI_REV4)
748 lpfc_set_loopback_flag(phba);
6e7288d9 749 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
76a95d75 750 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
84d1b006
JS
751 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
752 "0498 Adapter failed to init, mbxCmd x%x "
753 "INIT_LINK, mbxStatus x%x\n",
754 mb->mbxCommand, mb->mbxStatus);
76a95d75
JS
755 if (phba->sli_rev <= LPFC_SLI_REV3) {
756 /* Clear all interrupt enable conditions */
757 writel(0, phba->HCregaddr);
758 readl(phba->HCregaddr); /* flush */
759 /* Clear all pending interrupts */
760 writel(0xffffffff, phba->HAregaddr);
761 readl(phba->HAregaddr); /* flush */
762 }
84d1b006 763 phba->link_state = LPFC_HBA_ERROR;
6e7288d9 764 if (rc != MBX_BUSY || flag == MBX_POLL)
84d1b006
JS
765 mempool_free(pmb, phba->mbox_mem_pool);
766 return -EIO;
767 }
e40a02c1 768 phba->cfg_suppress_link_up = LPFC_INITIALIZE_LINK;
6e7288d9
JS
769 if (flag == MBX_POLL)
770 mempool_free(pmb, phba->mbox_mem_pool);
84d1b006
JS
771
772 return 0;
773}
774
775/**
776 * lpfc_hba_down_link - this routine downs the FC link
6e7288d9
JS
777 * @phba: pointer to lpfc hba data structure.
778 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
84d1b006
JS
779 *
780 * This routine will issue the DOWN_LINK mailbox command call.
781 * It is available to other drivers through the lpfc_hba data
782 * structure for use to stop the link.
783 *
784 * Return code
785 * 0 - success
786 * Any other value - error
787 **/
e399b228 788static int
6e7288d9 789lpfc_hba_down_link(struct lpfc_hba *phba, uint32_t flag)
84d1b006
JS
790{
791 LPFC_MBOXQ_t *pmb;
792 int rc;
793
794 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
795 if (!pmb) {
796 phba->link_state = LPFC_HBA_ERROR;
797 return -ENOMEM;
798 }
799
800 lpfc_printf_log(phba,
801 KERN_ERR, LOG_INIT,
802 "0491 Adapter Link is disabled.\n");
803 lpfc_down_link(phba, pmb);
804 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
6e7288d9 805 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
84d1b006
JS
806 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
807 lpfc_printf_log(phba,
808 KERN_ERR, LOG_INIT,
809 "2522 Adapter failed to issue DOWN_LINK"
810 " mbox command rc 0x%x\n", rc);
811
812 mempool_free(pmb, phba->mbox_mem_pool);
813 return -EIO;
814 }
6e7288d9
JS
815 if (flag == MBX_POLL)
816 mempool_free(pmb, phba->mbox_mem_pool);
817
84d1b006
JS
818 return 0;
819}
820
e59058c4 821/**
3621a710 822 * lpfc_hba_down_prep - Perform lpfc uninitialization prior to HBA reset
e59058c4
JS
823 * @phba: pointer to lpfc HBA data structure.
824 *
825 * This routine will do LPFC uninitialization before the HBA is reset when
826 * bringing down the SLI Layer.
827 *
828 * Return codes
829 * 0 - success.
830 * Any other value - error.
831 **/
dea3101e 832int
2e0fef85 833lpfc_hba_down_prep(struct lpfc_hba *phba)
dea3101e 834{
1b32f6aa
JS
835 struct lpfc_vport **vports;
836 int i;
3772a991
JS
837
838 if (phba->sli_rev <= LPFC_SLI_REV3) {
839 /* Disable interrupts */
840 writel(0, phba->HCregaddr);
841 readl(phba->HCregaddr); /* flush */
842 }
dea3101e 843
1b32f6aa
JS
844 if (phba->pport->load_flag & FC_UNLOADING)
845 lpfc_cleanup_discovery_resources(phba->pport);
846 else {
847 vports = lpfc_create_vport_work_array(phba);
848 if (vports != NULL)
3772a991
JS
849 for (i = 0; i <= phba->max_vports &&
850 vports[i] != NULL; i++)
1b32f6aa
JS
851 lpfc_cleanup_discovery_resources(vports[i]);
852 lpfc_destroy_vport_work_array(phba, vports);
7f5f3d0d
JS
853 }
854 return 0;
dea3101e 855}
856
68e814f5
JS
857/**
858 * lpfc_sli4_free_sp_events - Cleanup sp_queue_events to free
859 * rspiocb which got deferred
860 *
861 * @phba: pointer to lpfc HBA data structure.
862 *
863 * This routine will cleanup completed slow path events after HBA is reset
864 * when bringing down the SLI Layer.
865 *
866 *
867 * Return codes
868 * void.
869 **/
870static void
871lpfc_sli4_free_sp_events(struct lpfc_hba *phba)
872{
873 struct lpfc_iocbq *rspiocbq;
874 struct hbq_dmabuf *dmabuf;
875 struct lpfc_cq_event *cq_event;
876
877 spin_lock_irq(&phba->hbalock);
878 phba->hba_flag &= ~HBA_SP_QUEUE_EVT;
879 spin_unlock_irq(&phba->hbalock);
880
881 while (!list_empty(&phba->sli4_hba.sp_queue_event)) {
882 /* Get the response iocb from the head of work queue */
883 spin_lock_irq(&phba->hbalock);
884 list_remove_head(&phba->sli4_hba.sp_queue_event,
885 cq_event, struct lpfc_cq_event, list);
886 spin_unlock_irq(&phba->hbalock);
887
888 switch (bf_get(lpfc_wcqe_c_code, &cq_event->cqe.wcqe_cmpl)) {
889 case CQE_CODE_COMPL_WQE:
890 rspiocbq = container_of(cq_event, struct lpfc_iocbq,
891 cq_event);
892 lpfc_sli_release_iocbq(phba, rspiocbq);
893 break;
894 case CQE_CODE_RECEIVE:
895 case CQE_CODE_RECEIVE_V1:
896 dmabuf = container_of(cq_event, struct hbq_dmabuf,
897 cq_event);
898 lpfc_in_buf_free(phba, &dmabuf->dbuf);
899 }
900 }
901}
902
e59058c4 903/**
bcece5f5 904 * lpfc_hba_free_post_buf - Perform lpfc uninitialization after HBA reset
e59058c4
JS
905 * @phba: pointer to lpfc HBA data structure.
906 *
bcece5f5
JS
907 * This routine will cleanup posted ELS buffers after the HBA is reset
908 * when bringing down the SLI Layer.
909 *
e59058c4
JS
910 *
911 * Return codes
bcece5f5 912 * void.
e59058c4 913 **/
bcece5f5
JS
914static void
915lpfc_hba_free_post_buf(struct lpfc_hba *phba)
41415862
JW
916{
917 struct lpfc_sli *psli = &phba->sli;
918 struct lpfc_sli_ring *pring;
919 struct lpfc_dmabuf *mp, *next_mp;
07eab624
JS
920 LIST_HEAD(buflist);
921 int count;
41415862 922
92d7f7b0
JS
923 if (phba->sli3_options & LPFC_SLI3_HBQ_ENABLED)
924 lpfc_sli_hbqbuf_free_all(phba);
925 else {
926 /* Cleanup preposted buffers on the ELS ring */
895427bd 927 pring = &psli->sli3_ring[LPFC_ELS_RING];
07eab624
JS
928 spin_lock_irq(&phba->hbalock);
929 list_splice_init(&pring->postbufq, &buflist);
930 spin_unlock_irq(&phba->hbalock);
931
932 count = 0;
933 list_for_each_entry_safe(mp, next_mp, &buflist, list) {
92d7f7b0 934 list_del(&mp->list);
07eab624 935 count++;
92d7f7b0
JS
936 lpfc_mbuf_free(phba, mp->virt, mp->phys);
937 kfree(mp);
938 }
07eab624
JS
939
940 spin_lock_irq(&phba->hbalock);
941 pring->postbufq_cnt -= count;
bcece5f5 942 spin_unlock_irq(&phba->hbalock);
41415862 943 }
bcece5f5
JS
944}
945
946/**
947 * lpfc_hba_clean_txcmplq - Perform lpfc uninitialization after HBA reset
948 * @phba: pointer to lpfc HBA data structure.
949 *
950 * This routine will cleanup the txcmplq after the HBA is reset when bringing
951 * down the SLI Layer.
952 *
953 * Return codes
954 * void
955 **/
956static void
957lpfc_hba_clean_txcmplq(struct lpfc_hba *phba)
958{
959 struct lpfc_sli *psli = &phba->sli;
895427bd 960 struct lpfc_queue *qp = NULL;
bcece5f5
JS
961 struct lpfc_sli_ring *pring;
962 LIST_HEAD(completions);
963 int i;
c1dd9111 964 struct lpfc_iocbq *piocb, *next_iocb;
bcece5f5 965
895427bd
JS
966 if (phba->sli_rev != LPFC_SLI_REV4) {
967 for (i = 0; i < psli->num_rings; i++) {
968 pring = &psli->sli3_ring[i];
bcece5f5 969 spin_lock_irq(&phba->hbalock);
895427bd
JS
970 /* At this point in time the HBA is either reset or DOA
971 * Nothing should be on txcmplq as it will
972 * NEVER complete.
973 */
974 list_splice_init(&pring->txcmplq, &completions);
975 pring->txcmplq_cnt = 0;
bcece5f5 976 spin_unlock_irq(&phba->hbalock);
09372820 977
895427bd
JS
978 lpfc_sli_abort_iocb_ring(phba, pring);
979 }
a257bf90 980 /* Cancel all the IOCBs from the completions list */
895427bd
JS
981 lpfc_sli_cancel_iocbs(phba, &completions,
982 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
983 return;
984 }
985 list_for_each_entry(qp, &phba->sli4_hba.lpfc_wq_list, wq_list) {
986 pring = qp->pring;
987 if (!pring)
988 continue;
989 spin_lock_irq(&pring->ring_lock);
c1dd9111
JS
990 list_for_each_entry_safe(piocb, next_iocb,
991 &pring->txcmplq, list)
992 piocb->iocb_flag &= ~LPFC_IO_ON_TXCMPLQ;
895427bd
JS
993 list_splice_init(&pring->txcmplq, &completions);
994 pring->txcmplq_cnt = 0;
995 spin_unlock_irq(&pring->ring_lock);
41415862
JW
996 lpfc_sli_abort_iocb_ring(phba, pring);
997 }
895427bd
JS
998 /* Cancel all the IOCBs from the completions list */
999 lpfc_sli_cancel_iocbs(phba, &completions,
1000 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
bcece5f5 1001}
41415862 1002
bcece5f5
JS
1003/**
1004 * lpfc_hba_down_post_s3 - Perform lpfc uninitialization after HBA reset
1005 int i;
1006 * @phba: pointer to lpfc HBA data structure.
1007 *
1008 * This routine will do uninitialization after the HBA is reset when bring
1009 * down the SLI Layer.
1010 *
1011 * Return codes
1012 * 0 - success.
1013 * Any other value - error.
1014 **/
1015static int
1016lpfc_hba_down_post_s3(struct lpfc_hba *phba)
1017{
1018 lpfc_hba_free_post_buf(phba);
1019 lpfc_hba_clean_txcmplq(phba);
41415862
JW
1020 return 0;
1021}
5af5eee7 1022
da0436e9
JS
1023/**
1024 * lpfc_hba_down_post_s4 - Perform lpfc uninitialization after HBA reset
1025 * @phba: pointer to lpfc HBA data structure.
1026 *
1027 * This routine will do uninitialization after the HBA is reset when bring
1028 * down the SLI Layer.
1029 *
1030 * Return codes
af901ca1 1031 * 0 - success.
da0436e9
JS
1032 * Any other value - error.
1033 **/
1034static int
1035lpfc_hba_down_post_s4(struct lpfc_hba *phba)
1036{
c490850a 1037 struct lpfc_io_buf *psb, *psb_next;
86c67379 1038 struct lpfc_nvmet_rcv_ctx *ctxp, *ctxp_next;
5e5b511d 1039 struct lpfc_sli4_hdw_queue *qp;
da0436e9 1040 LIST_HEAD(aborts);
895427bd 1041 LIST_HEAD(nvme_aborts);
86c67379 1042 LIST_HEAD(nvmet_aborts);
0f65ff68 1043 struct lpfc_sglq *sglq_entry = NULL;
5e5b511d 1044 int cnt, idx;
0f65ff68 1045
895427bd
JS
1046
1047 lpfc_sli_hbqbuf_free_all(phba);
bcece5f5
JS
1048 lpfc_hba_clean_txcmplq(phba);
1049
da0436e9
JS
1050 /* At this point in time the HBA is either reset or DOA. Either
1051 * way, nothing should be on lpfc_abts_els_sgl_list, it needs to be
895427bd 1052 * on the lpfc_els_sgl_list so that it can either be freed if the
da0436e9
JS
1053 * driver is unloading or reposted if the driver is restarting
1054 * the port.
1055 */
895427bd 1056 spin_lock_irq(&phba->hbalock); /* required for lpfc_els_sgl_list and */
da0436e9 1057 /* scsl_buf_list */
895427bd 1058 /* sgl_list_lock required because worker thread uses this
da0436e9
JS
1059 * list.
1060 */
895427bd 1061 spin_lock(&phba->sli4_hba.sgl_list_lock);
0f65ff68
JS
1062 list_for_each_entry(sglq_entry,
1063 &phba->sli4_hba.lpfc_abts_els_sgl_list, list)
1064 sglq_entry->state = SGL_FREED;
1065
da0436e9 1066 list_splice_init(&phba->sli4_hba.lpfc_abts_els_sgl_list,
895427bd
JS
1067 &phba->sli4_hba.lpfc_els_sgl_list);
1068
f358dd0c 1069
895427bd 1070 spin_unlock(&phba->sli4_hba.sgl_list_lock);
5e5b511d
JS
1071
1072 /* abts_xxxx_buf_list_lock required because worker thread uses this
da0436e9
JS
1073 * list.
1074 */
5e5b511d
JS
1075 cnt = 0;
1076 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
1077 qp = &phba->sli4_hba.hdwq[idx];
da0436e9 1078
c00f62e6
JS
1079 spin_lock(&qp->abts_io_buf_list_lock);
1080 list_splice_init(&qp->lpfc_abts_io_buf_list,
5e5b511d 1081 &aborts);
68e814f5 1082
0794d601 1083 list_for_each_entry_safe(psb, psb_next, &aborts, list) {
86c67379
JS
1084 psb->pCmd = NULL;
1085 psb->status = IOSTAT_SUCCESS;
cf1a1d3e 1086 cnt++;
86c67379 1087 }
5e5b511d
JS
1088 spin_lock(&qp->io_buf_list_put_lock);
1089 list_splice_init(&aborts, &qp->lpfc_io_buf_list_put);
1090 qp->put_io_bufs += qp->abts_scsi_io_bufs;
c00f62e6 1091 qp->put_io_bufs += qp->abts_nvme_io_bufs;
5e5b511d 1092 qp->abts_scsi_io_bufs = 0;
c00f62e6 1093 qp->abts_nvme_io_bufs = 0;
5e5b511d 1094 spin_unlock(&qp->io_buf_list_put_lock);
c00f62e6 1095 spin_unlock(&qp->abts_io_buf_list_lock);
5e5b511d 1096 }
731eedcb 1097 spin_unlock_irq(&phba->hbalock);
86c67379 1098
5e5b511d 1099 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
731eedcb 1100 spin_lock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
5e5b511d
JS
1101 list_splice_init(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list,
1102 &nvmet_aborts);
731eedcb 1103 spin_unlock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
86c67379
JS
1104 list_for_each_entry_safe(ctxp, ctxp_next, &nvmet_aborts, list) {
1105 ctxp->flag &= ~(LPFC_NVMET_XBUSY | LPFC_NVMET_ABORT_OP);
6c621a22 1106 lpfc_nvmet_ctxbuf_post(phba, ctxp->ctxbuf);
86c67379 1107 }
895427bd 1108 }
895427bd 1109
68e814f5 1110 lpfc_sli4_free_sp_events(phba);
5e5b511d 1111 return cnt;
da0436e9
JS
1112}
1113
1114/**
1115 * lpfc_hba_down_post - Wrapper func for hba down post routine
1116 * @phba: pointer to lpfc HBA data structure.
1117 *
1118 * This routine wraps the actual SLI3 or SLI4 routine for performing
1119 * uninitialization after the HBA is reset when bring down the SLI Layer.
1120 *
1121 * Return codes
af901ca1 1122 * 0 - success.
da0436e9
JS
1123 * Any other value - error.
1124 **/
1125int
1126lpfc_hba_down_post(struct lpfc_hba *phba)
1127{
1128 return (*phba->lpfc_hba_down_post)(phba);
1129}
41415862 1130
e59058c4 1131/**
3621a710 1132 * lpfc_hb_timeout - The HBA-timer timeout handler
e59058c4
JS
1133 * @ptr: unsigned long holds the pointer to lpfc hba data structure.
1134 *
1135 * This is the HBA-timer timeout handler registered to the lpfc driver. When
1136 * this timer fires, a HBA timeout event shall be posted to the lpfc driver
1137 * work-port-events bitmap and the worker thread is notified. This timeout
1138 * event will be used by the worker thread to invoke the actual timeout
1139 * handler routine, lpfc_hb_timeout_handler. Any periodical operations will
1140 * be performed in the timeout handler and the HBA timeout event bit shall
1141 * be cleared by the worker thread after it has taken the event bitmap out.
1142 **/
a6ababd2 1143static void
f22eb4d3 1144lpfc_hb_timeout(struct timer_list *t)
858c9f6c
JS
1145{
1146 struct lpfc_hba *phba;
5e9d9b82 1147 uint32_t tmo_posted;
858c9f6c
JS
1148 unsigned long iflag;
1149
f22eb4d3 1150 phba = from_timer(phba, t, hb_tmofunc);
9399627f
JS
1151
1152 /* Check for heart beat timeout conditions */
858c9f6c 1153 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
5e9d9b82
JS
1154 tmo_posted = phba->pport->work_port_events & WORKER_HB_TMO;
1155 if (!tmo_posted)
858c9f6c
JS
1156 phba->pport->work_port_events |= WORKER_HB_TMO;
1157 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
1158
9399627f 1159 /* Tell the worker thread there is work to do */
5e9d9b82
JS
1160 if (!tmo_posted)
1161 lpfc_worker_wake_up(phba);
858c9f6c
JS
1162 return;
1163}
1164
19ca7609
JS
1165/**
1166 * lpfc_rrq_timeout - The RRQ-timer timeout handler
1167 * @ptr: unsigned long holds the pointer to lpfc hba data structure.
1168 *
1169 * This is the RRQ-timer timeout handler registered to the lpfc driver. When
1170 * this timer fires, a RRQ timeout event shall be posted to the lpfc driver
1171 * work-port-events bitmap and the worker thread is notified. This timeout
1172 * event will be used by the worker thread to invoke the actual timeout
1173 * handler routine, lpfc_rrq_handler. Any periodical operations will
1174 * be performed in the timeout handler and the RRQ timeout event bit shall
1175 * be cleared by the worker thread after it has taken the event bitmap out.
1176 **/
1177static void
f22eb4d3 1178lpfc_rrq_timeout(struct timer_list *t)
19ca7609
JS
1179{
1180 struct lpfc_hba *phba;
19ca7609
JS
1181 unsigned long iflag;
1182
f22eb4d3 1183 phba = from_timer(phba, t, rrq_tmr);
19ca7609 1184 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
06918ac5
JS
1185 if (!(phba->pport->load_flag & FC_UNLOADING))
1186 phba->hba_flag |= HBA_RRQ_ACTIVE;
1187 else
1188 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
19ca7609 1189 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
06918ac5
JS
1190
1191 if (!(phba->pport->load_flag & FC_UNLOADING))
1192 lpfc_worker_wake_up(phba);
19ca7609
JS
1193}
1194
e59058c4 1195/**
3621a710 1196 * lpfc_hb_mbox_cmpl - The lpfc heart-beat mailbox command callback function
e59058c4
JS
1197 * @phba: pointer to lpfc hba data structure.
1198 * @pmboxq: pointer to the driver internal queue element for mailbox command.
1199 *
1200 * This is the callback function to the lpfc heart-beat mailbox command.
1201 * If configured, the lpfc driver issues the heart-beat mailbox command to
1202 * the HBA every LPFC_HB_MBOX_INTERVAL (current 5) seconds. At the time the
1203 * heart-beat mailbox command is issued, the driver shall set up heart-beat
1204 * timeout timer to LPFC_HB_MBOX_TIMEOUT (current 30) seconds and marks
1205 * heart-beat outstanding state. Once the mailbox command comes back and
1206 * no error conditions detected, the heart-beat mailbox command timer is
1207 * reset to LPFC_HB_MBOX_INTERVAL seconds and the heart-beat outstanding
1208 * state is cleared for the next heart-beat. If the timer expired with the
1209 * heart-beat outstanding state set, the driver will put the HBA offline.
1210 **/
858c9f6c
JS
1211static void
1212lpfc_hb_mbox_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
1213{
1214 unsigned long drvr_flag;
1215
1216 spin_lock_irqsave(&phba->hbalock, drvr_flag);
1217 phba->hb_outstanding = 0;
1218 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
1219
9399627f 1220 /* Check and reset heart-beat timer is necessary */
858c9f6c
JS
1221 mempool_free(pmboxq, phba->mbox_mem_pool);
1222 if (!(phba->pport->fc_flag & FC_OFFLINE_MODE) &&
1223 !(phba->link_state == LPFC_HBA_ERROR) &&
51ef4c26 1224 !(phba->pport->load_flag & FC_UNLOADING))
858c9f6c 1225 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1226 jiffies +
1227 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1228 return;
1229}
1230
32517fc0
JS
1231static void
1232lpfc_hb_eq_delay_work(struct work_struct *work)
1233{
1234 struct lpfc_hba *phba = container_of(to_delayed_work(work),
1235 struct lpfc_hba, eq_delay_work);
1236 struct lpfc_eq_intr_info *eqi, *eqi_new;
1237 struct lpfc_queue *eq, *eq_next;
1238 unsigned char *eqcnt = NULL;
1239 uint32_t usdelay;
1240 int i;
8d34a59c 1241 bool update = false;
32517fc0
JS
1242
1243 if (!phba->cfg_auto_imax || phba->pport->load_flag & FC_UNLOADING)
1244 return;
1245
1246 if (phba->link_state == LPFC_HBA_ERROR ||
1247 phba->pport->fc_flag & FC_OFFLINE_MODE)
1248 goto requeue;
1249
1250 eqcnt = kcalloc(num_possible_cpus(), sizeof(unsigned char),
1251 GFP_KERNEL);
1252 if (!eqcnt)
1253 goto requeue;
1254
8d34a59c
JS
1255 if (phba->cfg_irq_chann > 1) {
1256 /* Loop thru all IRQ vectors */
1257 for (i = 0; i < phba->cfg_irq_chann; i++) {
1258 /* Get the EQ corresponding to the IRQ vector */
1259 eq = phba->sli4_hba.hba_eq_hdl[i].eq;
1260 if (!eq)
1261 continue;
1262 if (eq->q_mode) {
1263 update = true;
1264 break;
1265 }
1266 if (eqcnt[eq->last_cpu] < 2)
1267 eqcnt[eq->last_cpu]++;
1268 }
1269 } else
1270 update = true;
32517fc0
JS
1271
1272 for_each_present_cpu(i) {
32517fc0 1273 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, i);
8d34a59c
JS
1274 if (!update && eqcnt[i] < 2) {
1275 eqi->icnt = 0;
1276 continue;
1277 }
32517fc0
JS
1278
1279 usdelay = (eqi->icnt / LPFC_IMAX_THRESHOLD) *
1280 LPFC_EQ_DELAY_STEP;
1281 if (usdelay > LPFC_MAX_AUTO_EQ_DELAY)
1282 usdelay = LPFC_MAX_AUTO_EQ_DELAY;
1283
1284 eqi->icnt = 0;
1285
1286 list_for_each_entry_safe(eq, eq_next, &eqi->list, cpu_list) {
1287 if (eq->last_cpu != i) {
1288 eqi_new = per_cpu_ptr(phba->sli4_hba.eq_info,
1289 eq->last_cpu);
1290 list_move_tail(&eq->cpu_list, &eqi_new->list);
1291 continue;
1292 }
1293 if (usdelay != eq->q_mode)
1294 lpfc_modify_hba_eq_delay(phba, eq->hdwq, 1,
1295 usdelay);
1296 }
1297 }
1298
1299 kfree(eqcnt);
1300
1301requeue:
1302 queue_delayed_work(phba->wq, &phba->eq_delay_work,
1303 msecs_to_jiffies(LPFC_EQ_DELAY_MSECS));
1304}
1305
c490850a
JS
1306/**
1307 * lpfc_hb_mxp_handler - Multi-XRI pools handler to adjust XRI distribution
1308 * @phba: pointer to lpfc hba data structure.
1309 *
1310 * For each heartbeat, this routine does some heuristic methods to adjust
1311 * XRI distribution. The goal is to fully utilize free XRIs.
1312 **/
1313static void lpfc_hb_mxp_handler(struct lpfc_hba *phba)
1314{
1315 u32 i;
1316 u32 hwq_count;
1317
1318 hwq_count = phba->cfg_hdw_queue;
1319 for (i = 0; i < hwq_count; i++) {
1320 /* Adjust XRIs in private pool */
1321 lpfc_adjust_pvt_pool_count(phba, i);
1322
1323 /* Adjust high watermark */
1324 lpfc_adjust_high_watermark(phba, i);
1325
1326#ifdef LPFC_MXP_STAT
1327 /* Snapshot pbl, pvt and busy count */
1328 lpfc_snapshot_mxp(phba, i);
1329#endif
1330 }
1331}
1332
e59058c4 1333/**
3621a710 1334 * lpfc_hb_timeout_handler - The HBA-timer timeout handler
e59058c4
JS
1335 * @phba: pointer to lpfc hba data structure.
1336 *
1337 * This is the actual HBA-timer timeout handler to be invoked by the worker
1338 * thread whenever the HBA timer fired and HBA-timeout event posted. This
1339 * handler performs any periodic operations needed for the device. If such
1340 * periodic event has already been attended to either in the interrupt handler
1341 * or by processing slow-ring or fast-ring events within the HBA-timer
1342 * timeout window (LPFC_HB_MBOX_INTERVAL), this handler just simply resets
1343 * the timer for the next timeout period. If lpfc heart-beat mailbox command
1344 * is configured and there is no heart-beat mailbox command outstanding, a
1345 * heart-beat mailbox is issued and timer set properly. Otherwise, if there
1346 * has been a heart-beat mailbox command outstanding, the HBA shall be put
1347 * to offline.
1348 **/
858c9f6c
JS
1349void
1350lpfc_hb_timeout_handler(struct lpfc_hba *phba)
1351{
45ed1190 1352 struct lpfc_vport **vports;
858c9f6c 1353 LPFC_MBOXQ_t *pmboxq;
0ff10d46 1354 struct lpfc_dmabuf *buf_ptr;
45ed1190 1355 int retval, i;
858c9f6c 1356 struct lpfc_sli *psli = &phba->sli;
0ff10d46 1357 LIST_HEAD(completions);
858c9f6c 1358
c490850a
JS
1359 if (phba->cfg_xri_rebalancing) {
1360 /* Multi-XRI pools handler */
1361 lpfc_hb_mxp_handler(phba);
1362 }
858c9f6c 1363
45ed1190
JS
1364 vports = lpfc_create_vport_work_array(phba);
1365 if (vports != NULL)
4258e98e 1366 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
45ed1190 1367 lpfc_rcv_seq_check_edtov(vports[i]);
4258e98e
JS
1368 lpfc_fdmi_num_disc_check(vports[i]);
1369 }
45ed1190
JS
1370 lpfc_destroy_vport_work_array(phba, vports);
1371
858c9f6c 1372 if ((phba->link_state == LPFC_HBA_ERROR) ||
51ef4c26 1373 (phba->pport->load_flag & FC_UNLOADING) ||
858c9f6c
JS
1374 (phba->pport->fc_flag & FC_OFFLINE_MODE))
1375 return;
1376
1377 spin_lock_irq(&phba->pport->work_port_lock);
858c9f6c 1378
256ec0d0
JS
1379 if (time_after(phba->last_completion_time +
1380 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL),
1381 jiffies)) {
858c9f6c
JS
1382 spin_unlock_irq(&phba->pport->work_port_lock);
1383 if (!phba->hb_outstanding)
1384 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1385 jiffies +
1386 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1387 else
1388 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1389 jiffies +
1390 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c
JS
1391 return;
1392 }
1393 spin_unlock_irq(&phba->pport->work_port_lock);
1394
0ff10d46
JS
1395 if (phba->elsbuf_cnt &&
1396 (phba->elsbuf_cnt == phba->elsbuf_prev_cnt)) {
1397 spin_lock_irq(&phba->hbalock);
1398 list_splice_init(&phba->elsbuf, &completions);
1399 phba->elsbuf_cnt = 0;
1400 phba->elsbuf_prev_cnt = 0;
1401 spin_unlock_irq(&phba->hbalock);
1402
1403 while (!list_empty(&completions)) {
1404 list_remove_head(&completions, buf_ptr,
1405 struct lpfc_dmabuf, list);
1406 lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
1407 kfree(buf_ptr);
1408 }
1409 }
1410 phba->elsbuf_prev_cnt = phba->elsbuf_cnt;
1411
858c9f6c 1412 /* If there is no heart beat outstanding, issue a heartbeat command */
13815c83
JS
1413 if (phba->cfg_enable_hba_heartbeat) {
1414 if (!phba->hb_outstanding) {
bc73905a
JS
1415 if ((!(psli->sli_flag & LPFC_SLI_MBOX_ACTIVE)) &&
1416 (list_empty(&psli->mboxq))) {
1417 pmboxq = mempool_alloc(phba->mbox_mem_pool,
1418 GFP_KERNEL);
1419 if (!pmboxq) {
1420 mod_timer(&phba->hb_tmofunc,
1421 jiffies +
256ec0d0
JS
1422 msecs_to_jiffies(1000 *
1423 LPFC_HB_MBOX_INTERVAL));
bc73905a
JS
1424 return;
1425 }
1426
1427 lpfc_heart_beat(phba, pmboxq);
1428 pmboxq->mbox_cmpl = lpfc_hb_mbox_cmpl;
1429 pmboxq->vport = phba->pport;
1430 retval = lpfc_sli_issue_mbox(phba, pmboxq,
1431 MBX_NOWAIT);
1432
1433 if (retval != MBX_BUSY &&
1434 retval != MBX_SUCCESS) {
1435 mempool_free(pmboxq,
1436 phba->mbox_mem_pool);
1437 mod_timer(&phba->hb_tmofunc,
1438 jiffies +
256ec0d0
JS
1439 msecs_to_jiffies(1000 *
1440 LPFC_HB_MBOX_INTERVAL));
bc73905a
JS
1441 return;
1442 }
1443 phba->skipped_hb = 0;
1444 phba->hb_outstanding = 1;
1445 } else if (time_before_eq(phba->last_completion_time,
1446 phba->skipped_hb)) {
1447 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
1448 "2857 Last completion time not "
1449 " updated in %d ms\n",
1450 jiffies_to_msecs(jiffies
1451 - phba->last_completion_time));
1452 } else
1453 phba->skipped_hb = jiffies;
1454
858c9f6c 1455 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1456 jiffies +
1457 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c 1458 return;
13815c83
JS
1459 } else {
1460 /*
1461 * If heart beat timeout called with hb_outstanding set
dcf2a4e0
JS
1462 * we need to give the hb mailbox cmd a chance to
1463 * complete or TMO.
13815c83 1464 */
dcf2a4e0
JS
1465 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1466 "0459 Adapter heartbeat still out"
1467 "standing:last compl time was %d ms.\n",
1468 jiffies_to_msecs(jiffies
1469 - phba->last_completion_time));
1470 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1471 jiffies +
1472 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c 1473 }
4258e98e
JS
1474 } else {
1475 mod_timer(&phba->hb_tmofunc,
1476 jiffies +
1477 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1478 }
1479}
1480
e59058c4 1481/**
3621a710 1482 * lpfc_offline_eratt - Bring lpfc offline on hardware error attention
e59058c4
JS
1483 * @phba: pointer to lpfc hba data structure.
1484 *
1485 * This routine is called to bring the HBA offline when HBA hardware error
1486 * other than Port Error 6 has been detected.
1487 **/
09372820
JS
1488static void
1489lpfc_offline_eratt(struct lpfc_hba *phba)
1490{
1491 struct lpfc_sli *psli = &phba->sli;
1492
1493 spin_lock_irq(&phba->hbalock);
f4b4c68f 1494 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
09372820 1495 spin_unlock_irq(&phba->hbalock);
618a5230 1496 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
09372820
JS
1497
1498 lpfc_offline(phba);
1499 lpfc_reset_barrier(phba);
f4b4c68f 1500 spin_lock_irq(&phba->hbalock);
09372820 1501 lpfc_sli_brdreset(phba);
f4b4c68f 1502 spin_unlock_irq(&phba->hbalock);
09372820
JS
1503 lpfc_hba_down_post(phba);
1504 lpfc_sli_brdready(phba, HS_MBRDY);
1505 lpfc_unblock_mgmt_io(phba);
1506 phba->link_state = LPFC_HBA_ERROR;
1507 return;
1508}
1509
da0436e9
JS
1510/**
1511 * lpfc_sli4_offline_eratt - Bring lpfc offline on SLI4 hardware error attention
1512 * @phba: pointer to lpfc hba data structure.
1513 *
1514 * This routine is called to bring a SLI4 HBA offline when HBA hardware error
1515 * other than Port Error 6 has been detected.
1516 **/
a88dbb6a 1517void
da0436e9
JS
1518lpfc_sli4_offline_eratt(struct lpfc_hba *phba)
1519{
946727dc
JS
1520 spin_lock_irq(&phba->hbalock);
1521 phba->link_state = LPFC_HBA_ERROR;
1522 spin_unlock_irq(&phba->hbalock);
1523
618a5230 1524 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
c00f62e6 1525 lpfc_sli_flush_io_rings(phba);
da0436e9 1526 lpfc_offline(phba);
da0436e9 1527 lpfc_hba_down_post(phba);
da0436e9 1528 lpfc_unblock_mgmt_io(phba);
da0436e9
JS
1529}
1530
a257bf90
JS
1531/**
1532 * lpfc_handle_deferred_eratt - The HBA hardware deferred error handler
1533 * @phba: pointer to lpfc hba data structure.
1534 *
1535 * This routine is invoked to handle the deferred HBA hardware error
1536 * conditions. This type of error is indicated by HBA by setting ER1
1537 * and another ER bit in the host status register. The driver will
1538 * wait until the ER1 bit clears before handling the error condition.
1539 **/
1540static void
1541lpfc_handle_deferred_eratt(struct lpfc_hba *phba)
1542{
1543 uint32_t old_host_status = phba->work_hs;
a257bf90
JS
1544 struct lpfc_sli *psli = &phba->sli;
1545
f4b4c68f
JS
1546 /* If the pci channel is offline, ignore possible errors,
1547 * since we cannot communicate with the pci card anyway.
1548 */
1549 if (pci_channel_offline(phba->pcidev)) {
1550 spin_lock_irq(&phba->hbalock);
1551 phba->hba_flag &= ~DEFER_ERATT;
1552 spin_unlock_irq(&phba->hbalock);
1553 return;
1554 }
1555
a257bf90
JS
1556 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1557 "0479 Deferred Adapter Hardware Error "
1558 "Data: x%x x%x x%x\n",
1559 phba->work_hs,
1560 phba->work_status[0], phba->work_status[1]);
1561
1562 spin_lock_irq(&phba->hbalock);
f4b4c68f 1563 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
a257bf90
JS
1564 spin_unlock_irq(&phba->hbalock);
1565
1566
1567 /*
1568 * Firmware stops when it triggred erratt. That could cause the I/Os
1569 * dropped by the firmware. Error iocb (I/O) on txcmplq and let the
1570 * SCSI layer retry it after re-establishing link.
1571 */
db55fba8 1572 lpfc_sli_abort_fcp_rings(phba);
a257bf90
JS
1573
1574 /*
1575 * There was a firmware error. Take the hba offline and then
1576 * attempt to restart it.
1577 */
618a5230 1578 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
a257bf90
JS
1579 lpfc_offline(phba);
1580
1581 /* Wait for the ER1 bit to clear.*/
1582 while (phba->work_hs & HS_FFER1) {
1583 msleep(100);
9940b97b
JS
1584 if (lpfc_readl(phba->HSregaddr, &phba->work_hs)) {
1585 phba->work_hs = UNPLUG_ERR ;
1586 break;
1587 }
a257bf90
JS
1588 /* If driver is unloading let the worker thread continue */
1589 if (phba->pport->load_flag & FC_UNLOADING) {
1590 phba->work_hs = 0;
1591 break;
1592 }
1593 }
1594
1595 /*
1596 * This is to ptrotect against a race condition in which
1597 * first write to the host attention register clear the
1598 * host status register.
1599 */
1600 if ((!phba->work_hs) && (!(phba->pport->load_flag & FC_UNLOADING)))
1601 phba->work_hs = old_host_status & ~HS_FFER1;
1602
3772a991 1603 spin_lock_irq(&phba->hbalock);
a257bf90 1604 phba->hba_flag &= ~DEFER_ERATT;
3772a991 1605 spin_unlock_irq(&phba->hbalock);
a257bf90
JS
1606 phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
1607 phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
1608}
1609
3772a991
JS
1610static void
1611lpfc_board_errevt_to_mgmt(struct lpfc_hba *phba)
1612{
1613 struct lpfc_board_event_header board_event;
1614 struct Scsi_Host *shost;
1615
1616 board_event.event_type = FC_REG_BOARD_EVENT;
1617 board_event.subcategory = LPFC_EVENT_PORTINTERR;
1618 shost = lpfc_shost_from_vport(phba->pport);
1619 fc_host_post_vendor_event(shost, fc_get_event_number(),
1620 sizeof(board_event),
1621 (char *) &board_event,
1622 LPFC_NL_VENDOR_ID);
1623}
1624
e59058c4 1625/**
3772a991 1626 * lpfc_handle_eratt_s3 - The SLI3 HBA hardware error handler
e59058c4
JS
1627 * @phba: pointer to lpfc hba data structure.
1628 *
1629 * This routine is invoked to handle the following HBA hardware error
1630 * conditions:
1631 * 1 - HBA error attention interrupt
1632 * 2 - DMA ring index out of range
1633 * 3 - Mailbox command came back as unknown
1634 **/
3772a991
JS
1635static void
1636lpfc_handle_eratt_s3(struct lpfc_hba *phba)
dea3101e 1637{
2e0fef85 1638 struct lpfc_vport *vport = phba->pport;
2e0fef85 1639 struct lpfc_sli *psli = &phba->sli;
d2873e4c 1640 uint32_t event_data;
57127f15
JS
1641 unsigned long temperature;
1642 struct temp_event temp_event_data;
92d7f7b0 1643 struct Scsi_Host *shost;
2e0fef85 1644
8d63f375 1645 /* If the pci channel is offline, ignore possible errors,
3772a991
JS
1646 * since we cannot communicate with the pci card anyway.
1647 */
1648 if (pci_channel_offline(phba->pcidev)) {
1649 spin_lock_irq(&phba->hbalock);
1650 phba->hba_flag &= ~DEFER_ERATT;
1651 spin_unlock_irq(&phba->hbalock);
8d63f375 1652 return;
3772a991
JS
1653 }
1654
13815c83
JS
1655 /* If resets are disabled then leave the HBA alone and return */
1656 if (!phba->cfg_enable_hba_reset)
1657 return;
dea3101e 1658
ea2151b4 1659 /* Send an internal error event to mgmt application */
3772a991 1660 lpfc_board_errevt_to_mgmt(phba);
ea2151b4 1661
a257bf90
JS
1662 if (phba->hba_flag & DEFER_ERATT)
1663 lpfc_handle_deferred_eratt(phba);
1664
dcf2a4e0
JS
1665 if ((phba->work_hs & HS_FFER6) || (phba->work_hs & HS_FFER8)) {
1666 if (phba->work_hs & HS_FFER6)
1667 /* Re-establishing Link */
1668 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1669 "1301 Re-establishing Link "
1670 "Data: x%x x%x x%x\n",
1671 phba->work_hs, phba->work_status[0],
1672 phba->work_status[1]);
1673 if (phba->work_hs & HS_FFER8)
1674 /* Device Zeroization */
1675 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1676 "2861 Host Authentication device "
1677 "zeroization Data:x%x x%x x%x\n",
1678 phba->work_hs, phba->work_status[0],
1679 phba->work_status[1]);
58da1ffb 1680
92d7f7b0 1681 spin_lock_irq(&phba->hbalock);
f4b4c68f 1682 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
92d7f7b0 1683 spin_unlock_irq(&phba->hbalock);
dea3101e 1684
1685 /*
1686 * Firmware stops when it triggled erratt with HS_FFER6.
1687 * That could cause the I/Os dropped by the firmware.
1688 * Error iocb (I/O) on txcmplq and let the SCSI layer
1689 * retry it after re-establishing link.
1690 */
db55fba8 1691 lpfc_sli_abort_fcp_rings(phba);
dea3101e 1692
dea3101e 1693 /*
1694 * There was a firmware error. Take the hba offline and then
1695 * attempt to restart it.
1696 */
618a5230 1697 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
dea3101e 1698 lpfc_offline(phba);
41415862 1699 lpfc_sli_brdrestart(phba);
dea3101e 1700 if (lpfc_online(phba) == 0) { /* Initialize the HBA */
46fa311e 1701 lpfc_unblock_mgmt_io(phba);
dea3101e 1702 return;
1703 }
46fa311e 1704 lpfc_unblock_mgmt_io(phba);
57127f15
JS
1705 } else if (phba->work_hs & HS_CRIT_TEMP) {
1706 temperature = readl(phba->MBslimaddr + TEMPERATURE_OFFSET);
1707 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1708 temp_event_data.event_code = LPFC_CRIT_TEMP;
1709 temp_event_data.data = (uint32_t)temperature;
1710
1711 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
d7c255b2 1712 "0406 Adapter maximum temperature exceeded "
57127f15
JS
1713 "(%ld), taking this port offline "
1714 "Data: x%x x%x x%x\n",
1715 temperature, phba->work_hs,
1716 phba->work_status[0], phba->work_status[1]);
1717
1718 shost = lpfc_shost_from_vport(phba->pport);
1719 fc_host_post_vendor_event(shost, fc_get_event_number(),
1720 sizeof(temp_event_data),
1721 (char *) &temp_event_data,
1722 SCSI_NL_VID_TYPE_PCI
1723 | PCI_VENDOR_ID_EMULEX);
1724
7af67051 1725 spin_lock_irq(&phba->hbalock);
7af67051
JS
1726 phba->over_temp_state = HBA_OVER_TEMP;
1727 spin_unlock_irq(&phba->hbalock);
09372820 1728 lpfc_offline_eratt(phba);
57127f15 1729
dea3101e 1730 } else {
1731 /* The if clause above forces this code path when the status
9399627f
JS
1732 * failure is a value other than FFER6. Do not call the offline
1733 * twice. This is the adapter hardware error path.
dea3101e 1734 */
1735 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011 1736 "0457 Adapter Hardware Error "
dea3101e 1737 "Data: x%x x%x x%x\n",
e8b62011 1738 phba->work_hs,
dea3101e 1739 phba->work_status[0], phba->work_status[1]);
1740
d2873e4c 1741 event_data = FC_REG_DUMP_EVENT;
92d7f7b0 1742 shost = lpfc_shost_from_vport(vport);
2e0fef85 1743 fc_host_post_vendor_event(shost, fc_get_event_number(),
d2873e4c
JS
1744 sizeof(event_data), (char *) &event_data,
1745 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1746
09372820 1747 lpfc_offline_eratt(phba);
dea3101e 1748 }
9399627f 1749 return;
dea3101e 1750}
1751
618a5230
JS
1752/**
1753 * lpfc_sli4_port_sta_fn_reset - The SLI4 function reset due to port status reg
1754 * @phba: pointer to lpfc hba data structure.
1755 * @mbx_action: flag for mailbox shutdown action.
1756 *
1757 * This routine is invoked to perform an SLI4 port PCI function reset in
1758 * response to port status register polling attention. It waits for port
1759 * status register (ERR, RDY, RN) bits before proceeding with function reset.
1760 * During this process, interrupt vectors are freed and later requested
1761 * for handling possible port resource change.
1762 **/
1763static int
e10b2022
JS
1764lpfc_sli4_port_sta_fn_reset(struct lpfc_hba *phba, int mbx_action,
1765 bool en_rn_msg)
618a5230
JS
1766{
1767 int rc;
1768 uint32_t intr_mode;
1769
27d6ac0a 1770 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
65791f1f
JS
1771 LPFC_SLI_INTF_IF_TYPE_2) {
1772 /*
1773 * On error status condition, driver need to wait for port
1774 * ready before performing reset.
1775 */
1776 rc = lpfc_sli4_pdev_status_reg_wait(phba);
0e916ee7 1777 if (rc)
65791f1f
JS
1778 return rc;
1779 }
0e916ee7 1780
65791f1f
JS
1781 /* need reset: attempt for port recovery */
1782 if (en_rn_msg)
1783 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1784 "2887 Reset Needed: Attempting Port "
1785 "Recovery...\n");
1786 lpfc_offline_prep(phba, mbx_action);
c00f62e6 1787 lpfc_sli_flush_io_rings(phba);
65791f1f
JS
1788 lpfc_offline(phba);
1789 /* release interrupt for possible resource change */
1790 lpfc_sli4_disable_intr(phba);
5a9eeff5
JS
1791 rc = lpfc_sli_brdrestart(phba);
1792 if (rc) {
1793 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1794 "6309 Failed to restart board\n");
1795 return rc;
1796 }
65791f1f
JS
1797 /* request and enable interrupt */
1798 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
1799 if (intr_mode == LPFC_INTR_ERROR) {
1800 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1801 "3175 Failed to enable interrupt\n");
1802 return -EIO;
618a5230 1803 }
65791f1f
JS
1804 phba->intr_mode = intr_mode;
1805 rc = lpfc_online(phba);
1806 if (rc == 0)
1807 lpfc_unblock_mgmt_io(phba);
1808
618a5230
JS
1809 return rc;
1810}
1811
da0436e9
JS
1812/**
1813 * lpfc_handle_eratt_s4 - The SLI4 HBA hardware error handler
1814 * @phba: pointer to lpfc hba data structure.
1815 *
1816 * This routine is invoked to handle the SLI4 HBA hardware error attention
1817 * conditions.
1818 **/
1819static void
1820lpfc_handle_eratt_s4(struct lpfc_hba *phba)
1821{
1822 struct lpfc_vport *vport = phba->pport;
1823 uint32_t event_data;
1824 struct Scsi_Host *shost;
2fcee4bf 1825 uint32_t if_type;
2e90f4b5
JS
1826 struct lpfc_register portstat_reg = {0};
1827 uint32_t reg_err1, reg_err2;
1828 uint32_t uerrlo_reg, uemasklo_reg;
65791f1f 1829 uint32_t smphr_port_status = 0, pci_rd_rc1, pci_rd_rc2;
e10b2022 1830 bool en_rn_msg = true;
946727dc 1831 struct temp_event temp_event_data;
65791f1f
JS
1832 struct lpfc_register portsmphr_reg;
1833 int rc, i;
da0436e9
JS
1834
1835 /* If the pci channel is offline, ignore possible errors, since
1836 * we cannot communicate with the pci card anyway.
1837 */
32a93100
JS
1838 if (pci_channel_offline(phba->pcidev)) {
1839 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1840 "3166 pci channel is offline\n");
1841 lpfc_sli4_offline_eratt(phba);
da0436e9 1842 return;
32a93100 1843 }
da0436e9 1844
65791f1f 1845 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
2fcee4bf
JS
1846 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
1847 switch (if_type) {
1848 case LPFC_SLI_INTF_IF_TYPE_0:
2e90f4b5
JS
1849 pci_rd_rc1 = lpfc_readl(
1850 phba->sli4_hba.u.if_type0.UERRLOregaddr,
1851 &uerrlo_reg);
1852 pci_rd_rc2 = lpfc_readl(
1853 phba->sli4_hba.u.if_type0.UEMASKLOregaddr,
1854 &uemasklo_reg);
1855 /* consider PCI bus read error as pci_channel_offline */
1856 if (pci_rd_rc1 == -EIO && pci_rd_rc2 == -EIO)
1857 return;
65791f1f
JS
1858 if (!(phba->hba_flag & HBA_RECOVERABLE_UE)) {
1859 lpfc_sli4_offline_eratt(phba);
1860 return;
1861 }
1862 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1863 "7623 Checking UE recoverable");
1864
1865 for (i = 0; i < phba->sli4_hba.ue_to_sr / 1000; i++) {
1866 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1867 &portsmphr_reg.word0))
1868 continue;
1869
1870 smphr_port_status = bf_get(lpfc_port_smphr_port_status,
1871 &portsmphr_reg);
1872 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1873 LPFC_PORT_SEM_UE_RECOVERABLE)
1874 break;
1875 /*Sleep for 1Sec, before checking SEMAPHORE */
1876 msleep(1000);
1877 }
1878
1879 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1880 "4827 smphr_port_status x%x : Waited %dSec",
1881 smphr_port_status, i);
1882
1883 /* Recoverable UE, reset the HBA device */
1884 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1885 LPFC_PORT_SEM_UE_RECOVERABLE) {
1886 for (i = 0; i < 20; i++) {
1887 msleep(1000);
1888 if (!lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1889 &portsmphr_reg.word0) &&
1890 (LPFC_POST_STAGE_PORT_READY ==
1891 bf_get(lpfc_port_smphr_port_status,
1892 &portsmphr_reg))) {
1893 rc = lpfc_sli4_port_sta_fn_reset(phba,
1894 LPFC_MBX_NO_WAIT, en_rn_msg);
1895 if (rc == 0)
1896 return;
1897 lpfc_printf_log(phba,
1898 KERN_ERR, LOG_INIT,
1899 "4215 Failed to recover UE");
1900 break;
1901 }
1902 }
1903 }
1904 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1905 "7624 Firmware not ready: Failing UE recovery,"
1906 " waited %dSec", i);
8c24a4f6 1907 phba->link_state = LPFC_HBA_ERROR;
2fcee4bf 1908 break;
946727dc 1909
2fcee4bf 1910 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 1911 case LPFC_SLI_INTF_IF_TYPE_6:
2e90f4b5
JS
1912 pci_rd_rc1 = lpfc_readl(
1913 phba->sli4_hba.u.if_type2.STATUSregaddr,
1914 &portstat_reg.word0);
1915 /* consider PCI bus read error as pci_channel_offline */
6b5151fd
JS
1916 if (pci_rd_rc1 == -EIO) {
1917 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1918 "3151 PCI bus read access failure: x%x\n",
1919 readl(phba->sli4_hba.u.if_type2.STATUSregaddr));
32a93100 1920 lpfc_sli4_offline_eratt(phba);
2e90f4b5 1921 return;
6b5151fd 1922 }
2e90f4b5
JS
1923 reg_err1 = readl(phba->sli4_hba.u.if_type2.ERR1regaddr);
1924 reg_err2 = readl(phba->sli4_hba.u.if_type2.ERR2regaddr);
2fcee4bf 1925 if (bf_get(lpfc_sliport_status_oti, &portstat_reg)) {
2fcee4bf
JS
1926 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1927 "2889 Port Overtemperature event, "
946727dc
JS
1928 "taking port offline Data: x%x x%x\n",
1929 reg_err1, reg_err2);
1930
310429ef 1931 phba->sfp_alarm |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
946727dc
JS
1932 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1933 temp_event_data.event_code = LPFC_CRIT_TEMP;
1934 temp_event_data.data = 0xFFFFFFFF;
1935
1936 shost = lpfc_shost_from_vport(phba->pport);
1937 fc_host_post_vendor_event(shost, fc_get_event_number(),
1938 sizeof(temp_event_data),
1939 (char *)&temp_event_data,
1940 SCSI_NL_VID_TYPE_PCI
1941 | PCI_VENDOR_ID_EMULEX);
1942
2fcee4bf
JS
1943 spin_lock_irq(&phba->hbalock);
1944 phba->over_temp_state = HBA_OVER_TEMP;
1945 spin_unlock_irq(&phba->hbalock);
1946 lpfc_sli4_offline_eratt(phba);
946727dc 1947 return;
2fcee4bf 1948 }
2e90f4b5 1949 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
e10b2022 1950 reg_err2 == SLIPORT_ERR2_REG_FW_RESTART) {
2e90f4b5 1951 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e10b2022
JS
1952 "3143 Port Down: Firmware Update "
1953 "Detected\n");
1954 en_rn_msg = false;
1955 } else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2e90f4b5
JS
1956 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
1957 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1958 "3144 Port Down: Debug Dump\n");
1959 else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1960 reg_err2 == SLIPORT_ERR2_REG_FUNC_PROVISON)
1961 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1962 "3145 Port Down: Provisioning\n");
618a5230 1963
946727dc
JS
1964 /* If resets are disabled then leave the HBA alone and return */
1965 if (!phba->cfg_enable_hba_reset)
1966 return;
1967
618a5230 1968 /* Check port status register for function reset */
e10b2022
JS
1969 rc = lpfc_sli4_port_sta_fn_reset(phba, LPFC_MBX_NO_WAIT,
1970 en_rn_msg);
618a5230
JS
1971 if (rc == 0) {
1972 /* don't report event on forced debug dump */
1973 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1974 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
1975 return;
1976 else
1977 break;
2fcee4bf 1978 }
618a5230 1979 /* fall through for not able to recover */
6b5151fd 1980 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8c24a4f6
JS
1981 "3152 Unrecoverable error\n");
1982 phba->link_state = LPFC_HBA_ERROR;
2fcee4bf
JS
1983 break;
1984 case LPFC_SLI_INTF_IF_TYPE_1:
1985 default:
1986 break;
1987 }
2e90f4b5
JS
1988 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1989 "3123 Report dump event to upper layer\n");
1990 /* Send an internal error event to mgmt application */
1991 lpfc_board_errevt_to_mgmt(phba);
1992
1993 event_data = FC_REG_DUMP_EVENT;
1994 shost = lpfc_shost_from_vport(vport);
1995 fc_host_post_vendor_event(shost, fc_get_event_number(),
1996 sizeof(event_data), (char *) &event_data,
1997 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
da0436e9
JS
1998}
1999
2000/**
2001 * lpfc_handle_eratt - Wrapper func for handling hba error attention
2002 * @phba: pointer to lpfc HBA data structure.
2003 *
2004 * This routine wraps the actual SLI3 or SLI4 hba error attention handling
2005 * routine from the API jump table function pointer from the lpfc_hba struct.
2006 *
2007 * Return codes
af901ca1 2008 * 0 - success.
da0436e9
JS
2009 * Any other value - error.
2010 **/
2011void
2012lpfc_handle_eratt(struct lpfc_hba *phba)
2013{
2014 (*phba->lpfc_handle_eratt)(phba);
2015}
2016
e59058c4 2017/**
3621a710 2018 * lpfc_handle_latt - The HBA link event handler
e59058c4
JS
2019 * @phba: pointer to lpfc hba data structure.
2020 *
2021 * This routine is invoked from the worker thread to handle a HBA host
895427bd 2022 * attention link event. SLI3 only.
e59058c4 2023 **/
dea3101e 2024void
2e0fef85 2025lpfc_handle_latt(struct lpfc_hba *phba)
dea3101e 2026{
2e0fef85
JS
2027 struct lpfc_vport *vport = phba->pport;
2028 struct lpfc_sli *psli = &phba->sli;
dea3101e 2029 LPFC_MBOXQ_t *pmb;
2030 volatile uint32_t control;
2031 struct lpfc_dmabuf *mp;
09372820 2032 int rc = 0;
dea3101e 2033
2034 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
09372820
JS
2035 if (!pmb) {
2036 rc = 1;
dea3101e 2037 goto lpfc_handle_latt_err_exit;
09372820 2038 }
dea3101e 2039
2040 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
09372820
JS
2041 if (!mp) {
2042 rc = 2;
dea3101e 2043 goto lpfc_handle_latt_free_pmb;
09372820 2044 }
dea3101e 2045
2046 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
09372820
JS
2047 if (!mp->virt) {
2048 rc = 3;
dea3101e 2049 goto lpfc_handle_latt_free_mp;
09372820 2050 }
dea3101e 2051
6281bfe0 2052 /* Cleanup any outstanding ELS commands */
549e55cd 2053 lpfc_els_flush_all_cmd(phba);
dea3101e 2054
2055 psli->slistat.link_event++;
76a95d75
JS
2056 lpfc_read_topology(phba, pmb, mp);
2057 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
2e0fef85 2058 pmb->vport = vport;
0d2b6b83 2059 /* Block ELS IOCBs until we have processed this mbox command */
895427bd 2060 phba->sli.sli3_ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
0b727fea 2061 rc = lpfc_sli_issue_mbox (phba, pmb, MBX_NOWAIT);
09372820
JS
2062 if (rc == MBX_NOT_FINISHED) {
2063 rc = 4;
14691150 2064 goto lpfc_handle_latt_free_mbuf;
09372820 2065 }
dea3101e 2066
2067 /* Clear Link Attention in HA REG */
2e0fef85 2068 spin_lock_irq(&phba->hbalock);
dea3101e 2069 writel(HA_LATT, phba->HAregaddr);
2070 readl(phba->HAregaddr); /* flush */
2e0fef85 2071 spin_unlock_irq(&phba->hbalock);
dea3101e 2072
2073 return;
2074
14691150 2075lpfc_handle_latt_free_mbuf:
895427bd 2076 phba->sli.sli3_ring[LPFC_ELS_RING].flag &= ~LPFC_STOP_IOCB_EVENT;
14691150 2077 lpfc_mbuf_free(phba, mp->virt, mp->phys);
dea3101e 2078lpfc_handle_latt_free_mp:
2079 kfree(mp);
2080lpfc_handle_latt_free_pmb:
1dcb58e5 2081 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 2082lpfc_handle_latt_err_exit:
2083 /* Enable Link attention interrupts */
2e0fef85 2084 spin_lock_irq(&phba->hbalock);
dea3101e 2085 psli->sli_flag |= LPFC_PROCESS_LA;
2086 control = readl(phba->HCregaddr);
2087 control |= HC_LAINT_ENA;
2088 writel(control, phba->HCregaddr);
2089 readl(phba->HCregaddr); /* flush */
2090
2091 /* Clear Link Attention in HA REG */
2092 writel(HA_LATT, phba->HAregaddr);
2093 readl(phba->HAregaddr); /* flush */
2e0fef85 2094 spin_unlock_irq(&phba->hbalock);
dea3101e 2095 lpfc_linkdown(phba);
2e0fef85 2096 phba->link_state = LPFC_HBA_ERROR;
dea3101e 2097
09372820
JS
2098 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
2099 "0300 LATT: Cannot issue READ_LA: Data:%d\n", rc);
dea3101e 2100
2101 return;
2102}
2103
e59058c4 2104/**
3621a710 2105 * lpfc_parse_vpd - Parse VPD (Vital Product Data)
e59058c4
JS
2106 * @phba: pointer to lpfc hba data structure.
2107 * @vpd: pointer to the vital product data.
2108 * @len: length of the vital product data in bytes.
2109 *
2110 * This routine parses the Vital Product Data (VPD). The VPD is treated as
2111 * an array of characters. In this routine, the ModelName, ProgramType, and
2112 * ModelDesc, etc. fields of the phba data structure will be populated.
2113 *
2114 * Return codes
2115 * 0 - pointer to the VPD passed in is NULL
2116 * 1 - success
2117 **/
3772a991 2118int
2e0fef85 2119lpfc_parse_vpd(struct lpfc_hba *phba, uint8_t *vpd, int len)
dea3101e 2120{
2121 uint8_t lenlo, lenhi;
07da60c1 2122 int Length;
dea3101e 2123 int i, j;
2124 int finished = 0;
2125 int index = 0;
2126
2127 if (!vpd)
2128 return 0;
2129
2130 /* Vital Product */
ed957684 2131 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011 2132 "0455 Vital Product Data: x%x x%x x%x x%x\n",
dea3101e 2133 (uint32_t) vpd[0], (uint32_t) vpd[1], (uint32_t) vpd[2],
2134 (uint32_t) vpd[3]);
74b72a59 2135 while (!finished && (index < (len - 4))) {
dea3101e 2136 switch (vpd[index]) {
2137 case 0x82:
74b72a59 2138 case 0x91:
dea3101e 2139 index += 1;
2140 lenlo = vpd[index];
2141 index += 1;
2142 lenhi = vpd[index];
2143 index += 1;
2144 i = ((((unsigned short)lenhi) << 8) + lenlo);
2145 index += i;
2146 break;
2147 case 0x90:
2148 index += 1;
2149 lenlo = vpd[index];
2150 index += 1;
2151 lenhi = vpd[index];
2152 index += 1;
2153 Length = ((((unsigned short)lenhi) << 8) + lenlo);
74b72a59
JW
2154 if (Length > len - index)
2155 Length = len - index;
dea3101e 2156 while (Length > 0) {
2157 /* Look for Serial Number */
2158 if ((vpd[index] == 'S') && (vpd[index+1] == 'N')) {
2159 index += 2;
2160 i = vpd[index];
2161 index += 1;
2162 j = 0;
2163 Length -= (3+i);
2164 while(i--) {
2165 phba->SerialNumber[j++] = vpd[index++];
2166 if (j == 31)
2167 break;
2168 }
2169 phba->SerialNumber[j] = 0;
2170 continue;
2171 }
2172 else if ((vpd[index] == 'V') && (vpd[index+1] == '1')) {
2173 phba->vpd_flag |= VPD_MODEL_DESC;
2174 index += 2;
2175 i = vpd[index];
2176 index += 1;
2177 j = 0;
2178 Length -= (3+i);
2179 while(i--) {
2180 phba->ModelDesc[j++] = vpd[index++];
2181 if (j == 255)
2182 break;
2183 }
2184 phba->ModelDesc[j] = 0;
2185 continue;
2186 }
2187 else if ((vpd[index] == 'V') && (vpd[index+1] == '2')) {
2188 phba->vpd_flag |= VPD_MODEL_NAME;
2189 index += 2;
2190 i = vpd[index];
2191 index += 1;
2192 j = 0;
2193 Length -= (3+i);
2194 while(i--) {
2195 phba->ModelName[j++] = vpd[index++];
2196 if (j == 79)
2197 break;
2198 }
2199 phba->ModelName[j] = 0;
2200 continue;
2201 }
2202 else if ((vpd[index] == 'V') && (vpd[index+1] == '3')) {
2203 phba->vpd_flag |= VPD_PROGRAM_TYPE;
2204 index += 2;
2205 i = vpd[index];
2206 index += 1;
2207 j = 0;
2208 Length -= (3+i);
2209 while(i--) {
2210 phba->ProgramType[j++] = vpd[index++];
2211 if (j == 255)
2212 break;
2213 }
2214 phba->ProgramType[j] = 0;
2215 continue;
2216 }
2217 else if ((vpd[index] == 'V') && (vpd[index+1] == '4')) {
2218 phba->vpd_flag |= VPD_PORT;
2219 index += 2;
2220 i = vpd[index];
2221 index += 1;
2222 j = 0;
2223 Length -= (3+i);
2224 while(i--) {
cd1c8301
JS
2225 if ((phba->sli_rev == LPFC_SLI_REV4) &&
2226 (phba->sli4_hba.pport_name_sta ==
2227 LPFC_SLI4_PPNAME_GET)) {
2228 j++;
2229 index++;
2230 } else
2231 phba->Port[j++] = vpd[index++];
2232 if (j == 19)
2233 break;
dea3101e 2234 }
cd1c8301
JS
2235 if ((phba->sli_rev != LPFC_SLI_REV4) ||
2236 (phba->sli4_hba.pport_name_sta ==
2237 LPFC_SLI4_PPNAME_NON))
2238 phba->Port[j] = 0;
dea3101e 2239 continue;
2240 }
2241 else {
2242 index += 2;
2243 i = vpd[index];
2244 index += 1;
2245 index += i;
2246 Length -= (3 + i);
2247 }
2248 }
2249 finished = 0;
2250 break;
2251 case 0x78:
2252 finished = 1;
2253 break;
2254 default:
2255 index ++;
2256 break;
2257 }
74b72a59 2258 }
dea3101e 2259
2260 return(1);
2261}
2262
e59058c4 2263/**
3621a710 2264 * lpfc_get_hba_model_desc - Retrieve HBA device model name and description
e59058c4
JS
2265 * @phba: pointer to lpfc hba data structure.
2266 * @mdp: pointer to the data structure to hold the derived model name.
2267 * @descp: pointer to the data structure to hold the derived description.
2268 *
2269 * This routine retrieves HBA's description based on its registered PCI device
2270 * ID. The @descp passed into this function points to an array of 256 chars. It
2271 * shall be returned with the model name, maximum speed, and the host bus type.
2272 * The @mdp passed into this function points to an array of 80 chars. When the
2273 * function returns, the @mdp will be filled with the model name.
2274 **/
dea3101e 2275static void
2e0fef85 2276lpfc_get_hba_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)
dea3101e 2277{
2278 lpfc_vpd_t *vp;
fefcb2b6 2279 uint16_t dev_id = phba->pcidev->device;
74b72a59 2280 int max_speed;
84774a4d 2281 int GE = 0;
da0436e9 2282 int oneConnect = 0; /* default is not a oneConnect */
74b72a59 2283 struct {
a747c9ce
JS
2284 char *name;
2285 char *bus;
2286 char *function;
2287 } m = {"<Unknown>", "", ""};
74b72a59
JW
2288
2289 if (mdp && mdp[0] != '\0'
2290 && descp && descp[0] != '\0')
2291 return;
2292
fbd8a6ba
JS
2293 if (phba->lmt & LMT_64Gb)
2294 max_speed = 64;
2295 else if (phba->lmt & LMT_32Gb)
d38dd52c
JS
2296 max_speed = 32;
2297 else if (phba->lmt & LMT_16Gb)
c0c11512
JS
2298 max_speed = 16;
2299 else if (phba->lmt & LMT_10Gb)
74b72a59
JW
2300 max_speed = 10;
2301 else if (phba->lmt & LMT_8Gb)
2302 max_speed = 8;
2303 else if (phba->lmt & LMT_4Gb)
2304 max_speed = 4;
2305 else if (phba->lmt & LMT_2Gb)
2306 max_speed = 2;
4169d868 2307 else if (phba->lmt & LMT_1Gb)
74b72a59 2308 max_speed = 1;
4169d868
JS
2309 else
2310 max_speed = 0;
dea3101e 2311
2312 vp = &phba->vpd;
dea3101e 2313
e4adb204 2314 switch (dev_id) {
06325e74 2315 case PCI_DEVICE_ID_FIREFLY:
12222f4f
JS
2316 m = (typeof(m)){"LP6000", "PCI",
2317 "Obsolete, Unsupported Fibre Channel Adapter"};
06325e74 2318 break;
dea3101e 2319 case PCI_DEVICE_ID_SUPERFLY:
2320 if (vp->rev.biuRev >= 1 && vp->rev.biuRev <= 3)
12222f4f 2321 m = (typeof(m)){"LP7000", "PCI", ""};
dea3101e 2322 else
12222f4f
JS
2323 m = (typeof(m)){"LP7000E", "PCI", ""};
2324 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
dea3101e 2325 break;
2326 case PCI_DEVICE_ID_DRAGONFLY:
a747c9ce 2327 m = (typeof(m)){"LP8000", "PCI",
12222f4f 2328 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2329 break;
2330 case PCI_DEVICE_ID_CENTAUR:
2331 if (FC_JEDEC_ID(vp->rev.biuRev) == CENTAUR_2G_JEDEC_ID)
12222f4f 2332 m = (typeof(m)){"LP9002", "PCI", ""};
dea3101e 2333 else
12222f4f
JS
2334 m = (typeof(m)){"LP9000", "PCI", ""};
2335 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
dea3101e 2336 break;
2337 case PCI_DEVICE_ID_RFLY:
a747c9ce 2338 m = (typeof(m)){"LP952", "PCI",
12222f4f 2339 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2340 break;
2341 case PCI_DEVICE_ID_PEGASUS:
a747c9ce 2342 m = (typeof(m)){"LP9802", "PCI-X",
12222f4f 2343 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2344 break;
2345 case PCI_DEVICE_ID_THOR:
a747c9ce 2346 m = (typeof(m)){"LP10000", "PCI-X",
12222f4f 2347 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2348 break;
2349 case PCI_DEVICE_ID_VIPER:
a747c9ce 2350 m = (typeof(m)){"LPX1000", "PCI-X",
12222f4f 2351 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2352 break;
2353 case PCI_DEVICE_ID_PFLY:
a747c9ce 2354 m = (typeof(m)){"LP982", "PCI-X",
12222f4f 2355 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2356 break;
2357 case PCI_DEVICE_ID_TFLY:
a747c9ce 2358 m = (typeof(m)){"LP1050", "PCI-X",
12222f4f 2359 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2360 break;
2361 case PCI_DEVICE_ID_HELIOS:
a747c9ce 2362 m = (typeof(m)){"LP11000", "PCI-X2",
12222f4f 2363 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2364 break;
e4adb204 2365 case PCI_DEVICE_ID_HELIOS_SCSP:
a747c9ce 2366 m = (typeof(m)){"LP11000-SP", "PCI-X2",
12222f4f 2367 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2368 break;
2369 case PCI_DEVICE_ID_HELIOS_DCSP:
a747c9ce 2370 m = (typeof(m)){"LP11002-SP", "PCI-X2",
12222f4f 2371 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2372 break;
2373 case PCI_DEVICE_ID_NEPTUNE:
12222f4f
JS
2374 m = (typeof(m)){"LPe1000", "PCIe",
2375 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2376 break;
2377 case PCI_DEVICE_ID_NEPTUNE_SCSP:
12222f4f
JS
2378 m = (typeof(m)){"LPe1000-SP", "PCIe",
2379 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2380 break;
2381 case PCI_DEVICE_ID_NEPTUNE_DCSP:
12222f4f
JS
2382 m = (typeof(m)){"LPe1002-SP", "PCIe",
2383 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204 2384 break;
dea3101e 2385 case PCI_DEVICE_ID_BMID:
a747c9ce 2386 m = (typeof(m)){"LP1150", "PCI-X2", "Fibre Channel Adapter"};
dea3101e 2387 break;
2388 case PCI_DEVICE_ID_BSMB:
12222f4f
JS
2389 m = (typeof(m)){"LP111", "PCI-X2",
2390 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2391 break;
2392 case PCI_DEVICE_ID_ZEPHYR:
a747c9ce 2393 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
dea3101e 2394 break;
e4adb204 2395 case PCI_DEVICE_ID_ZEPHYR_SCSP:
a747c9ce 2396 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
e4adb204
JSEC
2397 break;
2398 case PCI_DEVICE_ID_ZEPHYR_DCSP:
a747c9ce 2399 m = (typeof(m)){"LP2105", "PCIe", "FCoE Adapter"};
a257bf90 2400 GE = 1;
e4adb204 2401 break;
dea3101e 2402 case PCI_DEVICE_ID_ZMID:
a747c9ce 2403 m = (typeof(m)){"LPe1150", "PCIe", "Fibre Channel Adapter"};
dea3101e 2404 break;
2405 case PCI_DEVICE_ID_ZSMB:
a747c9ce 2406 m = (typeof(m)){"LPe111", "PCIe", "Fibre Channel Adapter"};
dea3101e 2407 break;
2408 case PCI_DEVICE_ID_LP101:
12222f4f
JS
2409 m = (typeof(m)){"LP101", "PCI-X",
2410 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2411 break;
2412 case PCI_DEVICE_ID_LP10000S:
12222f4f
JS
2413 m = (typeof(m)){"LP10000-S", "PCI",
2414 "Obsolete, Unsupported Fibre Channel Adapter"};
06325e74 2415 break;
e4adb204 2416 case PCI_DEVICE_ID_LP11000S:
12222f4f
JS
2417 m = (typeof(m)){"LP11000-S", "PCI-X2",
2418 "Obsolete, Unsupported Fibre Channel Adapter"};
18a3b596 2419 break;
e4adb204 2420 case PCI_DEVICE_ID_LPE11000S:
12222f4f
JS
2421 m = (typeof(m)){"LPe11000-S", "PCIe",
2422 "Obsolete, Unsupported Fibre Channel Adapter"};
5cc36b3c 2423 break;
b87eab38 2424 case PCI_DEVICE_ID_SAT:
a747c9ce 2425 m = (typeof(m)){"LPe12000", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2426 break;
2427 case PCI_DEVICE_ID_SAT_MID:
a747c9ce 2428 m = (typeof(m)){"LPe1250", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2429 break;
2430 case PCI_DEVICE_ID_SAT_SMB:
a747c9ce 2431 m = (typeof(m)){"LPe121", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2432 break;
2433 case PCI_DEVICE_ID_SAT_DCSP:
a747c9ce 2434 m = (typeof(m)){"LPe12002-SP", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2435 break;
2436 case PCI_DEVICE_ID_SAT_SCSP:
a747c9ce 2437 m = (typeof(m)){"LPe12000-SP", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2438 break;
2439 case PCI_DEVICE_ID_SAT_S:
a747c9ce 2440 m = (typeof(m)){"LPe12000-S", "PCIe", "Fibre Channel Adapter"};
b87eab38 2441 break;
84774a4d 2442 case PCI_DEVICE_ID_HORNET:
12222f4f
JS
2443 m = (typeof(m)){"LP21000", "PCIe",
2444 "Obsolete, Unsupported FCoE Adapter"};
84774a4d
JS
2445 GE = 1;
2446 break;
2447 case PCI_DEVICE_ID_PROTEUS_VF:
a747c9ce 2448 m = (typeof(m)){"LPev12000", "PCIe IOV",
12222f4f 2449 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d
JS
2450 break;
2451 case PCI_DEVICE_ID_PROTEUS_PF:
a747c9ce 2452 m = (typeof(m)){"LPev12000", "PCIe IOV",
12222f4f 2453 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d
JS
2454 break;
2455 case PCI_DEVICE_ID_PROTEUS_S:
a747c9ce 2456 m = (typeof(m)){"LPemv12002-S", "PCIe IOV",
12222f4f 2457 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d 2458 break;
da0436e9
JS
2459 case PCI_DEVICE_ID_TIGERSHARK:
2460 oneConnect = 1;
a747c9ce 2461 m = (typeof(m)){"OCe10100", "PCIe", "FCoE"};
da0436e9 2462 break;
a747c9ce 2463 case PCI_DEVICE_ID_TOMCAT:
6669f9bb 2464 oneConnect = 1;
a747c9ce
JS
2465 m = (typeof(m)){"OCe11100", "PCIe", "FCoE"};
2466 break;
2467 case PCI_DEVICE_ID_FALCON:
2468 m = (typeof(m)){"LPSe12002-ML1-E", "PCIe",
2469 "EmulexSecure Fibre"};
6669f9bb 2470 break;
98fc5dd9
JS
2471 case PCI_DEVICE_ID_BALIUS:
2472 m = (typeof(m)){"LPVe12002", "PCIe Shared I/O",
12222f4f 2473 "Obsolete, Unsupported Fibre Channel Adapter"};
98fc5dd9 2474 break;
085c647c 2475 case PCI_DEVICE_ID_LANCER_FC:
c0c11512 2476 m = (typeof(m)){"LPe16000", "PCIe", "Fibre Channel Adapter"};
085c647c 2477 break;
12222f4f
JS
2478 case PCI_DEVICE_ID_LANCER_FC_VF:
2479 m = (typeof(m)){"LPe16000", "PCIe",
2480 "Obsolete, Unsupported Fibre Channel Adapter"};
2481 break;
085c647c
JS
2482 case PCI_DEVICE_ID_LANCER_FCOE:
2483 oneConnect = 1;
079b5c91 2484 m = (typeof(m)){"OCe15100", "PCIe", "FCoE"};
085c647c 2485 break;
12222f4f
JS
2486 case PCI_DEVICE_ID_LANCER_FCOE_VF:
2487 oneConnect = 1;
2488 m = (typeof(m)){"OCe15100", "PCIe",
2489 "Obsolete, Unsupported FCoE"};
2490 break;
d38dd52c
JS
2491 case PCI_DEVICE_ID_LANCER_G6_FC:
2492 m = (typeof(m)){"LPe32000", "PCIe", "Fibre Channel Adapter"};
2493 break;
c238b9b6
JS
2494 case PCI_DEVICE_ID_LANCER_G7_FC:
2495 m = (typeof(m)){"LPe36000", "PCIe", "Fibre Channel Adapter"};
2496 break;
f8cafd38
JS
2497 case PCI_DEVICE_ID_SKYHAWK:
2498 case PCI_DEVICE_ID_SKYHAWK_VF:
2499 oneConnect = 1;
2500 m = (typeof(m)){"OCe14000", "PCIe", "FCoE"};
2501 break;
5cc36b3c 2502 default:
a747c9ce 2503 m = (typeof(m)){"Unknown", "", ""};
e4adb204 2504 break;
dea3101e 2505 }
74b72a59
JW
2506
2507 if (mdp && mdp[0] == '\0')
2508 snprintf(mdp, 79,"%s", m.name);
c0c11512
JS
2509 /*
2510 * oneConnect hba requires special processing, they are all initiators
da0436e9
JS
2511 * and we put the port number on the end
2512 */
2513 if (descp && descp[0] == '\0') {
2514 if (oneConnect)
2515 snprintf(descp, 255,
4169d868 2516 "Emulex OneConnect %s, %s Initiator %s",
a747c9ce 2517 m.name, m.function,
da0436e9 2518 phba->Port);
4169d868
JS
2519 else if (max_speed == 0)
2520 snprintf(descp, 255,
290237d2 2521 "Emulex %s %s %s",
4169d868 2522 m.name, m.bus, m.function);
da0436e9
JS
2523 else
2524 snprintf(descp, 255,
2525 "Emulex %s %d%s %s %s",
a747c9ce
JS
2526 m.name, max_speed, (GE) ? "GE" : "Gb",
2527 m.bus, m.function);
da0436e9 2528 }
dea3101e 2529}
2530
e59058c4 2531/**
3621a710 2532 * lpfc_post_buffer - Post IOCB(s) with DMA buffer descriptor(s) to a IOCB ring
e59058c4
JS
2533 * @phba: pointer to lpfc hba data structure.
2534 * @pring: pointer to a IOCB ring.
2535 * @cnt: the number of IOCBs to be posted to the IOCB ring.
2536 *
2537 * This routine posts a given number of IOCBs with the associated DMA buffer
2538 * descriptors specified by the cnt argument to the given IOCB ring.
2539 *
2540 * Return codes
2541 * The number of IOCBs NOT able to be posted to the IOCB ring.
2542 **/
dea3101e 2543int
495a714c 2544lpfc_post_buffer(struct lpfc_hba *phba, struct lpfc_sli_ring *pring, int cnt)
dea3101e 2545{
2546 IOCB_t *icmd;
0bd4ca25 2547 struct lpfc_iocbq *iocb;
dea3101e 2548 struct lpfc_dmabuf *mp1, *mp2;
2549
2550 cnt += pring->missbufcnt;
2551
2552 /* While there are buffers to post */
2553 while (cnt > 0) {
2554 /* Allocate buffer for command iocb */
0bd4ca25 2555 iocb = lpfc_sli_get_iocbq(phba);
dea3101e 2556 if (iocb == NULL) {
2557 pring->missbufcnt = cnt;
2558 return cnt;
2559 }
dea3101e 2560 icmd = &iocb->iocb;
2561
2562 /* 2 buffers can be posted per command */
2563 /* Allocate buffer to post */
2564 mp1 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2565 if (mp1)
98c9ea5c
JS
2566 mp1->virt = lpfc_mbuf_alloc(phba, MEM_PRI, &mp1->phys);
2567 if (!mp1 || !mp1->virt) {
c9475cb0 2568 kfree(mp1);
604a3e30 2569 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2570 pring->missbufcnt = cnt;
2571 return cnt;
2572 }
2573
2574 INIT_LIST_HEAD(&mp1->list);
2575 /* Allocate buffer to post */
2576 if (cnt > 1) {
2577 mp2 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2578 if (mp2)
2579 mp2->virt = lpfc_mbuf_alloc(phba, MEM_PRI,
2580 &mp2->phys);
98c9ea5c 2581 if (!mp2 || !mp2->virt) {
c9475cb0 2582 kfree(mp2);
dea3101e 2583 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2584 kfree(mp1);
604a3e30 2585 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2586 pring->missbufcnt = cnt;
2587 return cnt;
2588 }
2589
2590 INIT_LIST_HEAD(&mp2->list);
2591 } else {
2592 mp2 = NULL;
2593 }
2594
2595 icmd->un.cont64[0].addrHigh = putPaddrHigh(mp1->phys);
2596 icmd->un.cont64[0].addrLow = putPaddrLow(mp1->phys);
2597 icmd->un.cont64[0].tus.f.bdeSize = FCELSSIZE;
2598 icmd->ulpBdeCount = 1;
2599 cnt--;
2600 if (mp2) {
2601 icmd->un.cont64[1].addrHigh = putPaddrHigh(mp2->phys);
2602 icmd->un.cont64[1].addrLow = putPaddrLow(mp2->phys);
2603 icmd->un.cont64[1].tus.f.bdeSize = FCELSSIZE;
2604 cnt--;
2605 icmd->ulpBdeCount = 2;
2606 }
2607
2608 icmd->ulpCommand = CMD_QUE_RING_BUF64_CN;
2609 icmd->ulpLe = 1;
2610
3772a991
JS
2611 if (lpfc_sli_issue_iocb(phba, pring->ringno, iocb, 0) ==
2612 IOCB_ERROR) {
dea3101e 2613 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2614 kfree(mp1);
2615 cnt++;
2616 if (mp2) {
2617 lpfc_mbuf_free(phba, mp2->virt, mp2->phys);
2618 kfree(mp2);
2619 cnt++;
2620 }
604a3e30 2621 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2622 pring->missbufcnt = cnt;
dea3101e 2623 return cnt;
2624 }
dea3101e 2625 lpfc_sli_ringpostbuf_put(phba, pring, mp1);
92d7f7b0 2626 if (mp2)
dea3101e 2627 lpfc_sli_ringpostbuf_put(phba, pring, mp2);
dea3101e 2628 }
2629 pring->missbufcnt = 0;
2630 return 0;
2631}
2632
e59058c4 2633/**
3621a710 2634 * lpfc_post_rcv_buf - Post the initial receive IOCB buffers to ELS ring
e59058c4
JS
2635 * @phba: pointer to lpfc hba data structure.
2636 *
2637 * This routine posts initial receive IOCB buffers to the ELS ring. The
2638 * current number of initial IOCB buffers specified by LPFC_BUF_RING0 is
895427bd 2639 * set to 64 IOCBs. SLI3 only.
e59058c4
JS
2640 *
2641 * Return codes
2642 * 0 - success (currently always success)
2643 **/
dea3101e 2644static int
2e0fef85 2645lpfc_post_rcv_buf(struct lpfc_hba *phba)
dea3101e 2646{
2647 struct lpfc_sli *psli = &phba->sli;
2648
2649 /* Ring 0, ELS / CT buffers */
895427bd 2650 lpfc_post_buffer(phba, &psli->sli3_ring[LPFC_ELS_RING], LPFC_BUF_RING0);
dea3101e 2651 /* Ring 2 - FCP no buffers needed */
2652
2653 return 0;
2654}
2655
2656#define S(N,V) (((V)<<(N))|((V)>>(32-(N))))
2657
e59058c4 2658/**
3621a710 2659 * lpfc_sha_init - Set up initial array of hash table entries
e59058c4
JS
2660 * @HashResultPointer: pointer to an array as hash table.
2661 *
2662 * This routine sets up the initial values to the array of hash table entries
2663 * for the LC HBAs.
2664 **/
dea3101e 2665static void
2666lpfc_sha_init(uint32_t * HashResultPointer)
2667{
2668 HashResultPointer[0] = 0x67452301;
2669 HashResultPointer[1] = 0xEFCDAB89;
2670 HashResultPointer[2] = 0x98BADCFE;
2671 HashResultPointer[3] = 0x10325476;
2672 HashResultPointer[4] = 0xC3D2E1F0;
2673}
2674
e59058c4 2675/**
3621a710 2676 * lpfc_sha_iterate - Iterate initial hash table with the working hash table
e59058c4
JS
2677 * @HashResultPointer: pointer to an initial/result hash table.
2678 * @HashWorkingPointer: pointer to an working hash table.
2679 *
2680 * This routine iterates an initial hash table pointed by @HashResultPointer
2681 * with the values from the working hash table pointeed by @HashWorkingPointer.
2682 * The results are putting back to the initial hash table, returned through
2683 * the @HashResultPointer as the result hash table.
2684 **/
dea3101e 2685static void
2686lpfc_sha_iterate(uint32_t * HashResultPointer, uint32_t * HashWorkingPointer)
2687{
2688 int t;
2689 uint32_t TEMP;
2690 uint32_t A, B, C, D, E;
2691 t = 16;
2692 do {
2693 HashWorkingPointer[t] =
2694 S(1,
2695 HashWorkingPointer[t - 3] ^ HashWorkingPointer[t -
2696 8] ^
2697 HashWorkingPointer[t - 14] ^ HashWorkingPointer[t - 16]);
2698 } while (++t <= 79);
2699 t = 0;
2700 A = HashResultPointer[0];
2701 B = HashResultPointer[1];
2702 C = HashResultPointer[2];
2703 D = HashResultPointer[3];
2704 E = HashResultPointer[4];
2705
2706 do {
2707 if (t < 20) {
2708 TEMP = ((B & C) | ((~B) & D)) + 0x5A827999;
2709 } else if (t < 40) {
2710 TEMP = (B ^ C ^ D) + 0x6ED9EBA1;
2711 } else if (t < 60) {
2712 TEMP = ((B & C) | (B & D) | (C & D)) + 0x8F1BBCDC;
2713 } else {
2714 TEMP = (B ^ C ^ D) + 0xCA62C1D6;
2715 }
2716 TEMP += S(5, A) + E + HashWorkingPointer[t];
2717 E = D;
2718 D = C;
2719 C = S(30, B);
2720 B = A;
2721 A = TEMP;
2722 } while (++t <= 79);
2723
2724 HashResultPointer[0] += A;
2725 HashResultPointer[1] += B;
2726 HashResultPointer[2] += C;
2727 HashResultPointer[3] += D;
2728 HashResultPointer[4] += E;
2729
2730}
2731
e59058c4 2732/**
3621a710 2733 * lpfc_challenge_key - Create challenge key based on WWPN of the HBA
e59058c4
JS
2734 * @RandomChallenge: pointer to the entry of host challenge random number array.
2735 * @HashWorking: pointer to the entry of the working hash array.
2736 *
2737 * This routine calculates the working hash array referred by @HashWorking
2738 * from the challenge random numbers associated with the host, referred by
2739 * @RandomChallenge. The result is put into the entry of the working hash
2740 * array and returned by reference through @HashWorking.
2741 **/
dea3101e 2742static void
2743lpfc_challenge_key(uint32_t * RandomChallenge, uint32_t * HashWorking)
2744{
2745 *HashWorking = (*RandomChallenge ^ *HashWorking);
2746}
2747
e59058c4 2748/**
3621a710 2749 * lpfc_hba_init - Perform special handling for LC HBA initialization
e59058c4
JS
2750 * @phba: pointer to lpfc hba data structure.
2751 * @hbainit: pointer to an array of unsigned 32-bit integers.
2752 *
2753 * This routine performs the special handling for LC HBA initialization.
2754 **/
dea3101e 2755void
2756lpfc_hba_init(struct lpfc_hba *phba, uint32_t *hbainit)
2757{
2758 int t;
2759 uint32_t *HashWorking;
2e0fef85 2760 uint32_t *pwwnn = (uint32_t *) phba->wwnn;
dea3101e 2761
bbfbbbc1 2762 HashWorking = kcalloc(80, sizeof(uint32_t), GFP_KERNEL);
dea3101e 2763 if (!HashWorking)
2764 return;
2765
dea3101e 2766 HashWorking[0] = HashWorking[78] = *pwwnn++;
2767 HashWorking[1] = HashWorking[79] = *pwwnn;
2768
2769 for (t = 0; t < 7; t++)
2770 lpfc_challenge_key(phba->RandomData + t, HashWorking + t);
2771
2772 lpfc_sha_init(hbainit);
2773 lpfc_sha_iterate(hbainit, HashWorking);
2774 kfree(HashWorking);
2775}
2776
e59058c4 2777/**
3621a710 2778 * lpfc_cleanup - Performs vport cleanups before deleting a vport
e59058c4
JS
2779 * @vport: pointer to a virtual N_Port data structure.
2780 *
2781 * This routine performs the necessary cleanups before deleting the @vport.
2782 * It invokes the discovery state machine to perform necessary state
2783 * transitions and to release the ndlps associated with the @vport. Note,
2784 * the physical port is treated as @vport 0.
2785 **/
87af33fe 2786void
2e0fef85 2787lpfc_cleanup(struct lpfc_vport *vport)
dea3101e 2788{
87af33fe 2789 struct lpfc_hba *phba = vport->phba;
dea3101e 2790 struct lpfc_nodelist *ndlp, *next_ndlp;
a8adb832 2791 int i = 0;
dea3101e 2792
87af33fe
JS
2793 if (phba->link_state > LPFC_LINK_DOWN)
2794 lpfc_port_link_failure(vport);
2795
2796 list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
e47c9093
JS
2797 if (!NLP_CHK_NODE_ACT(ndlp)) {
2798 ndlp = lpfc_enable_node(vport, ndlp,
2799 NLP_STE_UNUSED_NODE);
2800 if (!ndlp)
2801 continue;
2802 spin_lock_irq(&phba->ndlp_lock);
2803 NLP_SET_FREE_REQ(ndlp);
2804 spin_unlock_irq(&phba->ndlp_lock);
2805 /* Trigger the release of the ndlp memory */
2806 lpfc_nlp_put(ndlp);
2807 continue;
2808 }
2809 spin_lock_irq(&phba->ndlp_lock);
2810 if (NLP_CHK_FREE_REQ(ndlp)) {
2811 /* The ndlp should not be in memory free mode already */
2812 spin_unlock_irq(&phba->ndlp_lock);
2813 continue;
2814 } else
2815 /* Indicate request for freeing ndlp memory */
2816 NLP_SET_FREE_REQ(ndlp);
2817 spin_unlock_irq(&phba->ndlp_lock);
2818
58da1ffb
JS
2819 if (vport->port_type != LPFC_PHYSICAL_PORT &&
2820 ndlp->nlp_DID == Fabric_DID) {
2821 /* Just free up ndlp with Fabric_DID for vports */
2822 lpfc_nlp_put(ndlp);
2823 continue;
2824 }
2825
eff4a01b
JS
2826 /* take care of nodes in unused state before the state
2827 * machine taking action.
2828 */
2829 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
2830 lpfc_nlp_put(ndlp);
2831 continue;
2832 }
2833
87af33fe
JS
2834 if (ndlp->nlp_type & NLP_FABRIC)
2835 lpfc_disc_state_machine(vport, ndlp, NULL,
2836 NLP_EVT_DEVICE_RECOVERY);
e47c9093 2837
87af33fe
JS
2838 lpfc_disc_state_machine(vport, ndlp, NULL,
2839 NLP_EVT_DEVICE_RM);
2840 }
2841
a8adb832
JS
2842 /* At this point, ALL ndlp's should be gone
2843 * because of the previous NLP_EVT_DEVICE_RM.
2844 * Lets wait for this to happen, if needed.
2845 */
87af33fe 2846 while (!list_empty(&vport->fc_nodes)) {
a8adb832 2847 if (i++ > 3000) {
87af33fe 2848 lpfc_printf_vlog(vport, KERN_ERR, LOG_DISCOVERY,
a8adb832 2849 "0233 Nodelist not empty\n");
e47c9093
JS
2850 list_for_each_entry_safe(ndlp, next_ndlp,
2851 &vport->fc_nodes, nlp_listp) {
2852 lpfc_printf_vlog(ndlp->vport, KERN_ERR,
2853 LOG_NODE,
32350664 2854 "0282 did:x%x ndlp:x%px "
e47c9093
JS
2855 "usgmap:x%x refcnt:%d\n",
2856 ndlp->nlp_DID, (void *)ndlp,
2857 ndlp->nlp_usg_map,
2c935bc5 2858 kref_read(&ndlp->kref));
e47c9093 2859 }
a8adb832 2860 break;
87af33fe 2861 }
a8adb832
JS
2862
2863 /* Wait for any activity on ndlps to settle */
2864 msleep(10);
87af33fe 2865 }
1151e3ec 2866 lpfc_cleanup_vports_rrqs(vport, NULL);
dea3101e 2867}
2868
e59058c4 2869/**
3621a710 2870 * lpfc_stop_vport_timers - Stop all the timers associated with a vport
e59058c4
JS
2871 * @vport: pointer to a virtual N_Port data structure.
2872 *
2873 * This routine stops all the timers associated with a @vport. This function
2874 * is invoked before disabling or deleting a @vport. Note that the physical
2875 * port is treated as @vport 0.
2876 **/
92d7f7b0
JS
2877void
2878lpfc_stop_vport_timers(struct lpfc_vport *vport)
dea3101e 2879{
92d7f7b0 2880 del_timer_sync(&vport->els_tmofunc);
92494144 2881 del_timer_sync(&vport->delayed_disc_tmo);
92d7f7b0
JS
2882 lpfc_can_disctmo(vport);
2883 return;
dea3101e 2884}
2885
ecfd03c6
JS
2886/**
2887 * __lpfc_sli4_stop_fcf_redisc_wait_timer - Stop FCF rediscovery wait timer
2888 * @phba: pointer to lpfc hba data structure.
2889 *
2890 * This routine stops the SLI4 FCF rediscover wait timer if it's on. The
2891 * caller of this routine should already hold the host lock.
2892 **/
2893void
2894__lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2895{
5ac6b303
JS
2896 /* Clear pending FCF rediscovery wait flag */
2897 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
2898
ecfd03c6
JS
2899 /* Now, try to stop the timer */
2900 del_timer(&phba->fcf.redisc_wait);
2901}
2902
2903/**
2904 * lpfc_sli4_stop_fcf_redisc_wait_timer - Stop FCF rediscovery wait timer
2905 * @phba: pointer to lpfc hba data structure.
2906 *
2907 * This routine stops the SLI4 FCF rediscover wait timer if it's on. It
2908 * checks whether the FCF rediscovery wait timer is pending with the host
2909 * lock held before proceeding with disabling the timer and clearing the
2910 * wait timer pendig flag.
2911 **/
2912void
2913lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2914{
2915 spin_lock_irq(&phba->hbalock);
2916 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
2917 /* FCF rediscovery timer already fired or stopped */
2918 spin_unlock_irq(&phba->hbalock);
2919 return;
2920 }
2921 __lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
5ac6b303
JS
2922 /* Clear failover in progress flags */
2923 phba->fcf.fcf_flag &= ~(FCF_DEAD_DISC | FCF_ACVL_DISC);
ecfd03c6
JS
2924 spin_unlock_irq(&phba->hbalock);
2925}
2926
e59058c4 2927/**
3772a991 2928 * lpfc_stop_hba_timers - Stop all the timers associated with an HBA
e59058c4
JS
2929 * @phba: pointer to lpfc hba data structure.
2930 *
2931 * This routine stops all the timers associated with a HBA. This function is
2932 * invoked before either putting a HBA offline or unloading the driver.
2933 **/
3772a991
JS
2934void
2935lpfc_stop_hba_timers(struct lpfc_hba *phba)
dea3101e 2936{
cdb42bec
JS
2937 if (phba->pport)
2938 lpfc_stop_vport_timers(phba->pport);
32517fc0 2939 cancel_delayed_work_sync(&phba->eq_delay_work);
2e0fef85 2940 del_timer_sync(&phba->sli.mbox_tmo);
92d7f7b0 2941 del_timer_sync(&phba->fabric_block_timer);
9399627f 2942 del_timer_sync(&phba->eratt_poll);
3772a991 2943 del_timer_sync(&phba->hb_tmofunc);
1151e3ec
JS
2944 if (phba->sli_rev == LPFC_SLI_REV4) {
2945 del_timer_sync(&phba->rrq_tmr);
2946 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
2947 }
3772a991
JS
2948 phba->hb_outstanding = 0;
2949
2950 switch (phba->pci_dev_grp) {
2951 case LPFC_PCI_DEV_LP:
2952 /* Stop any LightPulse device specific driver timers */
2953 del_timer_sync(&phba->fcp_poll_timer);
2954 break;
2955 case LPFC_PCI_DEV_OC:
cc0e5f1c 2956 /* Stop any OneConnect device specific driver timers */
ecfd03c6 2957 lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
3772a991
JS
2958 break;
2959 default:
2960 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2961 "0297 Invalid device group (x%x)\n",
2962 phba->pci_dev_grp);
2963 break;
2964 }
2e0fef85 2965 return;
dea3101e 2966}
2967
e59058c4 2968/**
3621a710 2969 * lpfc_block_mgmt_io - Mark a HBA's management interface as blocked
e59058c4
JS
2970 * @phba: pointer to lpfc hba data structure.
2971 *
2972 * This routine marks a HBA's management interface as blocked. Once the HBA's
2973 * management interface is marked as blocked, all the user space access to
2974 * the HBA, whether they are from sysfs interface or libdfc interface will
2975 * all be blocked. The HBA is set to block the management interface when the
2976 * driver prepares the HBA interface for online or offline.
2977 **/
a6ababd2 2978static void
618a5230 2979lpfc_block_mgmt_io(struct lpfc_hba *phba, int mbx_action)
a6ababd2
AB
2980{
2981 unsigned long iflag;
6e7288d9
JS
2982 uint8_t actcmd = MBX_HEARTBEAT;
2983 unsigned long timeout;
2984
a6ababd2
AB
2985 spin_lock_irqsave(&phba->hbalock, iflag);
2986 phba->sli.sli_flag |= LPFC_BLOCK_MGMT_IO;
618a5230
JS
2987 spin_unlock_irqrestore(&phba->hbalock, iflag);
2988 if (mbx_action == LPFC_MBX_NO_WAIT)
2989 return;
2990 timeout = msecs_to_jiffies(LPFC_MBOX_TMO * 1000) + jiffies;
2991 spin_lock_irqsave(&phba->hbalock, iflag);
a183a15f 2992 if (phba->sli.mbox_active) {
6e7288d9 2993 actcmd = phba->sli.mbox_active->u.mb.mbxCommand;
a183a15f
JS
2994 /* Determine how long we might wait for the active mailbox
2995 * command to be gracefully completed by firmware.
2996 */
2997 timeout = msecs_to_jiffies(lpfc_mbox_tmo_val(phba,
2998 phba->sli.mbox_active) * 1000) + jiffies;
2999 }
a6ababd2 3000 spin_unlock_irqrestore(&phba->hbalock, iflag);
a183a15f 3001
6e7288d9
JS
3002 /* Wait for the outstnading mailbox command to complete */
3003 while (phba->sli.mbox_active) {
3004 /* Check active mailbox complete status every 2ms */
3005 msleep(2);
3006 if (time_after(jiffies, timeout)) {
3007 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3008 "2813 Mgmt IO is Blocked %x "
3009 "- mbox cmd %x still active\n",
3010 phba->sli.sli_flag, actcmd);
3011 break;
3012 }
3013 }
a6ababd2
AB
3014}
3015
6b5151fd
JS
3016/**
3017 * lpfc_sli4_node_prep - Assign RPIs for active nodes.
3018 * @phba: pointer to lpfc hba data structure.
3019 *
3020 * Allocate RPIs for all active remote nodes. This is needed whenever
3021 * an SLI4 adapter is reset and the driver is not unloading. Its purpose
3022 * is to fixup the temporary rpi assignments.
3023 **/
3024void
3025lpfc_sli4_node_prep(struct lpfc_hba *phba)
3026{
3027 struct lpfc_nodelist *ndlp, *next_ndlp;
3028 struct lpfc_vport **vports;
9d3d340d
JS
3029 int i, rpi;
3030 unsigned long flags;
6b5151fd
JS
3031
3032 if (phba->sli_rev != LPFC_SLI_REV4)
3033 return;
3034
3035 vports = lpfc_create_vport_work_array(phba);
9d3d340d
JS
3036 if (vports == NULL)
3037 return;
6b5151fd 3038
9d3d340d
JS
3039 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3040 if (vports[i]->load_flag & FC_UNLOADING)
3041 continue;
3042
3043 list_for_each_entry_safe(ndlp, next_ndlp,
3044 &vports[i]->fc_nodes,
3045 nlp_listp) {
3046 if (!NLP_CHK_NODE_ACT(ndlp))
3047 continue;
3048 rpi = lpfc_sli4_alloc_rpi(phba);
3049 if (rpi == LPFC_RPI_ALLOC_ERROR) {
3050 spin_lock_irqsave(&phba->ndlp_lock, flags);
3051 NLP_CLR_NODE_ACT(ndlp);
3052 spin_unlock_irqrestore(&phba->ndlp_lock, flags);
3053 continue;
6b5151fd 3054 }
9d3d340d 3055 ndlp->nlp_rpi = rpi;
0f154226
JS
3056 lpfc_printf_vlog(ndlp->vport, KERN_INFO,
3057 LOG_NODE | LOG_DISCOVERY,
3058 "0009 Assign RPI x%x to ndlp x%px "
3059 "DID:x%06x flg:x%x map:x%x\n",
3060 ndlp->nlp_rpi, ndlp, ndlp->nlp_DID,
3061 ndlp->nlp_flag, ndlp->nlp_usg_map);
6b5151fd
JS
3062 }
3063 }
3064 lpfc_destroy_vport_work_array(phba, vports);
3065}
3066
c490850a
JS
3067/**
3068 * lpfc_create_expedite_pool - create expedite pool
3069 * @phba: pointer to lpfc hba data structure.
3070 *
3071 * This routine moves a batch of XRIs from lpfc_io_buf_list_put of HWQ 0
3072 * to expedite pool. Mark them as expedite.
3073 **/
3999df75 3074static void lpfc_create_expedite_pool(struct lpfc_hba *phba)
c490850a
JS
3075{
3076 struct lpfc_sli4_hdw_queue *qp;
3077 struct lpfc_io_buf *lpfc_ncmd;
3078 struct lpfc_io_buf *lpfc_ncmd_next;
3079 struct lpfc_epd_pool *epd_pool;
3080 unsigned long iflag;
3081
3082 epd_pool = &phba->epd_pool;
3083 qp = &phba->sli4_hba.hdwq[0];
3084
3085 spin_lock_init(&epd_pool->lock);
3086 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3087 spin_lock(&epd_pool->lock);
3088 INIT_LIST_HEAD(&epd_pool->list);
3089 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3090 &qp->lpfc_io_buf_list_put, list) {
3091 list_move_tail(&lpfc_ncmd->list, &epd_pool->list);
3092 lpfc_ncmd->expedite = true;
3093 qp->put_io_bufs--;
3094 epd_pool->count++;
3095 if (epd_pool->count >= XRI_BATCH)
3096 break;
3097 }
3098 spin_unlock(&epd_pool->lock);
3099 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3100}
3101
3102/**
3103 * lpfc_destroy_expedite_pool - destroy expedite pool
3104 * @phba: pointer to lpfc hba data structure.
3105 *
3106 * This routine returns XRIs from expedite pool to lpfc_io_buf_list_put
3107 * of HWQ 0. Clear the mark.
3108 **/
3999df75 3109static void lpfc_destroy_expedite_pool(struct lpfc_hba *phba)
c490850a
JS
3110{
3111 struct lpfc_sli4_hdw_queue *qp;
3112 struct lpfc_io_buf *lpfc_ncmd;
3113 struct lpfc_io_buf *lpfc_ncmd_next;
3114 struct lpfc_epd_pool *epd_pool;
3115 unsigned long iflag;
3116
3117 epd_pool = &phba->epd_pool;
3118 qp = &phba->sli4_hba.hdwq[0];
3119
3120 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3121 spin_lock(&epd_pool->lock);
3122 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3123 &epd_pool->list, list) {
3124 list_move_tail(&lpfc_ncmd->list,
3125 &qp->lpfc_io_buf_list_put);
3126 lpfc_ncmd->flags = false;
3127 qp->put_io_bufs++;
3128 epd_pool->count--;
3129 }
3130 spin_unlock(&epd_pool->lock);
3131 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3132}
3133
3134/**
3135 * lpfc_create_multixri_pools - create multi-XRI pools
3136 * @phba: pointer to lpfc hba data structure.
3137 *
3138 * This routine initialize public, private per HWQ. Then, move XRIs from
3139 * lpfc_io_buf_list_put to public pool. High and low watermark are also
3140 * Initialized.
3141 **/
3142void lpfc_create_multixri_pools(struct lpfc_hba *phba)
3143{
3144 u32 i, j;
3145 u32 hwq_count;
3146 u32 count_per_hwq;
3147 struct lpfc_io_buf *lpfc_ncmd;
3148 struct lpfc_io_buf *lpfc_ncmd_next;
3149 unsigned long iflag;
3150 struct lpfc_sli4_hdw_queue *qp;
3151 struct lpfc_multixri_pool *multixri_pool;
3152 struct lpfc_pbl_pool *pbl_pool;
3153 struct lpfc_pvt_pool *pvt_pool;
3154
3155 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3156 "1234 num_hdw_queue=%d num_present_cpu=%d common_xri_cnt=%d\n",
3157 phba->cfg_hdw_queue, phba->sli4_hba.num_present_cpu,
3158 phba->sli4_hba.io_xri_cnt);
3159
3160 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3161 lpfc_create_expedite_pool(phba);
3162
3163 hwq_count = phba->cfg_hdw_queue;
3164 count_per_hwq = phba->sli4_hba.io_xri_cnt / hwq_count;
3165
3166 for (i = 0; i < hwq_count; i++) {
3167 multixri_pool = kzalloc(sizeof(*multixri_pool), GFP_KERNEL);
3168
3169 if (!multixri_pool) {
3170 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3171 "1238 Failed to allocate memory for "
3172 "multixri_pool\n");
3173
3174 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3175 lpfc_destroy_expedite_pool(phba);
3176
3177 j = 0;
3178 while (j < i) {
3179 qp = &phba->sli4_hba.hdwq[j];
3180 kfree(qp->p_multixri_pool);
3181 j++;
3182 }
3183 phba->cfg_xri_rebalancing = 0;
3184 return;
3185 }
3186
3187 qp = &phba->sli4_hba.hdwq[i];
3188 qp->p_multixri_pool = multixri_pool;
3189
3190 multixri_pool->xri_limit = count_per_hwq;
3191 multixri_pool->rrb_next_hwqid = i;
3192
3193 /* Deal with public free xri pool */
3194 pbl_pool = &multixri_pool->pbl_pool;
3195 spin_lock_init(&pbl_pool->lock);
3196 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3197 spin_lock(&pbl_pool->lock);
3198 INIT_LIST_HEAD(&pbl_pool->list);
3199 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3200 &qp->lpfc_io_buf_list_put, list) {
3201 list_move_tail(&lpfc_ncmd->list, &pbl_pool->list);
3202 qp->put_io_bufs--;
3203 pbl_pool->count++;
3204 }
3205 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3206 "1235 Moved %d buffers from PUT list over to pbl_pool[%d]\n",
3207 pbl_pool->count, i);
3208 spin_unlock(&pbl_pool->lock);
3209 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3210
3211 /* Deal with private free xri pool */
3212 pvt_pool = &multixri_pool->pvt_pool;
3213 pvt_pool->high_watermark = multixri_pool->xri_limit / 2;
3214 pvt_pool->low_watermark = XRI_BATCH;
3215 spin_lock_init(&pvt_pool->lock);
3216 spin_lock_irqsave(&pvt_pool->lock, iflag);
3217 INIT_LIST_HEAD(&pvt_pool->list);
3218 pvt_pool->count = 0;
3219 spin_unlock_irqrestore(&pvt_pool->lock, iflag);
3220 }
3221}
3222
3223/**
3224 * lpfc_destroy_multixri_pools - destroy multi-XRI pools
3225 * @phba: pointer to lpfc hba data structure.
3226 *
3227 * This routine returns XRIs from public/private to lpfc_io_buf_list_put.
3228 **/
3999df75 3229static void lpfc_destroy_multixri_pools(struct lpfc_hba *phba)
c490850a
JS
3230{
3231 u32 i;
3232 u32 hwq_count;
3233 struct lpfc_io_buf *lpfc_ncmd;
3234 struct lpfc_io_buf *lpfc_ncmd_next;
3235 unsigned long iflag;
3236 struct lpfc_sli4_hdw_queue *qp;
3237 struct lpfc_multixri_pool *multixri_pool;
3238 struct lpfc_pbl_pool *pbl_pool;
3239 struct lpfc_pvt_pool *pvt_pool;
3240
3241 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3242 lpfc_destroy_expedite_pool(phba);
3243
c00f62e6
JS
3244 if (!(phba->pport->load_flag & FC_UNLOADING))
3245 lpfc_sli_flush_io_rings(phba);
c66a9197 3246
c490850a
JS
3247 hwq_count = phba->cfg_hdw_queue;
3248
3249 for (i = 0; i < hwq_count; i++) {
3250 qp = &phba->sli4_hba.hdwq[i];
3251 multixri_pool = qp->p_multixri_pool;
3252 if (!multixri_pool)
3253 continue;
3254
3255 qp->p_multixri_pool = NULL;
3256
3257 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3258
3259 /* Deal with public free xri pool */
3260 pbl_pool = &multixri_pool->pbl_pool;
3261 spin_lock(&pbl_pool->lock);
3262
3263 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3264 "1236 Moving %d buffers from pbl_pool[%d] TO PUT list\n",
3265 pbl_pool->count, i);
3266
3267 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3268 &pbl_pool->list, list) {
3269 list_move_tail(&lpfc_ncmd->list,
3270 &qp->lpfc_io_buf_list_put);
3271 qp->put_io_bufs++;
3272 pbl_pool->count--;
3273 }
3274
3275 INIT_LIST_HEAD(&pbl_pool->list);
3276 pbl_pool->count = 0;
3277
3278 spin_unlock(&pbl_pool->lock);
3279
3280 /* Deal with private free xri pool */
3281 pvt_pool = &multixri_pool->pvt_pool;
3282 spin_lock(&pvt_pool->lock);
3283
3284 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3285 "1237 Moving %d buffers from pvt_pool[%d] TO PUT list\n",
3286 pvt_pool->count, i);
3287
3288 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3289 &pvt_pool->list, list) {
3290 list_move_tail(&lpfc_ncmd->list,
3291 &qp->lpfc_io_buf_list_put);
3292 qp->put_io_bufs++;
3293 pvt_pool->count--;
3294 }
3295
3296 INIT_LIST_HEAD(&pvt_pool->list);
3297 pvt_pool->count = 0;
3298
3299 spin_unlock(&pvt_pool->lock);
3300 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3301
3302 kfree(multixri_pool);
3303 }
3304}
3305
e59058c4 3306/**
3621a710 3307 * lpfc_online - Initialize and bring a HBA online
e59058c4
JS
3308 * @phba: pointer to lpfc hba data structure.
3309 *
3310 * This routine initializes the HBA and brings a HBA online. During this
3311 * process, the management interface is blocked to prevent user space access
3312 * to the HBA interfering with the driver initialization.
3313 *
3314 * Return codes
3315 * 0 - successful
3316 * 1 - failed
3317 **/
dea3101e 3318int
2e0fef85 3319lpfc_online(struct lpfc_hba *phba)
dea3101e 3320{
372bd282 3321 struct lpfc_vport *vport;
549e55cd 3322 struct lpfc_vport **vports;
a145fda3 3323 int i, error = 0;
16a3a208 3324 bool vpis_cleared = false;
2e0fef85 3325
dea3101e 3326 if (!phba)
3327 return 0;
372bd282 3328 vport = phba->pport;
dea3101e 3329
2e0fef85 3330 if (!(vport->fc_flag & FC_OFFLINE_MODE))
dea3101e 3331 return 0;
3332
ed957684 3333 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
e8b62011 3334 "0458 Bring Adapter online\n");
dea3101e 3335
618a5230 3336 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
46fa311e 3337
da0436e9
JS
3338 if (phba->sli_rev == LPFC_SLI_REV4) {
3339 if (lpfc_sli4_hba_setup(phba)) { /* Initialize SLI4 HBA */
3340 lpfc_unblock_mgmt_io(phba);
3341 return 1;
3342 }
16a3a208
JS
3343 spin_lock_irq(&phba->hbalock);
3344 if (!phba->sli4_hba.max_cfg_param.vpi_used)
3345 vpis_cleared = true;
3346 spin_unlock_irq(&phba->hbalock);
a145fda3
DK
3347
3348 /* Reestablish the local initiator port.
3349 * The offline process destroyed the previous lport.
3350 */
3351 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME &&
3352 !phba->nvmet_support) {
3353 error = lpfc_nvme_create_localport(phba->pport);
3354 if (error)
3355 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
3356 "6132 NVME restore reg failed "
3357 "on nvmei error x%x\n", error);
3358 }
da0436e9 3359 } else {
895427bd 3360 lpfc_sli_queue_init(phba);
da0436e9
JS
3361 if (lpfc_sli_hba_setup(phba)) { /* Initialize SLI2/SLI3 HBA */
3362 lpfc_unblock_mgmt_io(phba);
3363 return 1;
3364 }
46fa311e 3365 }
dea3101e 3366
549e55cd 3367 vports = lpfc_create_vport_work_array(phba);
aeb6641f 3368 if (vports != NULL) {
da0436e9 3369 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
549e55cd
JS
3370 struct Scsi_Host *shost;
3371 shost = lpfc_shost_from_vport(vports[i]);
3372 spin_lock_irq(shost->host_lock);
3373 vports[i]->fc_flag &= ~FC_OFFLINE_MODE;
3374 if (phba->sli3_options & LPFC_SLI3_NPIV_ENABLED)
3375 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
16a3a208 3376 if (phba->sli_rev == LPFC_SLI_REV4) {
1c6834a7 3377 vports[i]->fc_flag |= FC_VPORT_NEEDS_INIT_VPI;
16a3a208
JS
3378 if ((vpis_cleared) &&
3379 (vports[i]->port_type !=
3380 LPFC_PHYSICAL_PORT))
3381 vports[i]->vpi = 0;
3382 }
549e55cd
JS
3383 spin_unlock_irq(shost->host_lock);
3384 }
aeb6641f
AB
3385 }
3386 lpfc_destroy_vport_work_array(phba, vports);
dea3101e 3387
c490850a
JS
3388 if (phba->cfg_xri_rebalancing)
3389 lpfc_create_multixri_pools(phba);
3390
46fa311e 3391 lpfc_unblock_mgmt_io(phba);
dea3101e 3392 return 0;
3393}
3394
e59058c4 3395/**
3621a710 3396 * lpfc_unblock_mgmt_io - Mark a HBA's management interface to be not blocked
e59058c4
JS
3397 * @phba: pointer to lpfc hba data structure.
3398 *
3399 * This routine marks a HBA's management interface as not blocked. Once the
3400 * HBA's management interface is marked as not blocked, all the user space
3401 * access to the HBA, whether they are from sysfs interface or libdfc
3402 * interface will be allowed. The HBA is set to block the management interface
3403 * when the driver prepares the HBA interface for online or offline and then
3404 * set to unblock the management interface afterwards.
3405 **/
46fa311e
JS
3406void
3407lpfc_unblock_mgmt_io(struct lpfc_hba * phba)
3408{
3409 unsigned long iflag;
3410
2e0fef85
JS
3411 spin_lock_irqsave(&phba->hbalock, iflag);
3412 phba->sli.sli_flag &= ~LPFC_BLOCK_MGMT_IO;
3413 spin_unlock_irqrestore(&phba->hbalock, iflag);
46fa311e
JS
3414}
3415
e59058c4 3416/**
3621a710 3417 * lpfc_offline_prep - Prepare a HBA to be brought offline
e59058c4
JS
3418 * @phba: pointer to lpfc hba data structure.
3419 *
3420 * This routine is invoked to prepare a HBA to be brought offline. It performs
3421 * unregistration login to all the nodes on all vports and flushes the mailbox
3422 * queue to make it ready to be brought offline.
3423 **/
46fa311e 3424void
618a5230 3425lpfc_offline_prep(struct lpfc_hba *phba, int mbx_action)
46fa311e 3426{
2e0fef85 3427 struct lpfc_vport *vport = phba->pport;
46fa311e 3428 struct lpfc_nodelist *ndlp, *next_ndlp;
87af33fe 3429 struct lpfc_vport **vports;
72100cc4 3430 struct Scsi_Host *shost;
87af33fe 3431 int i;
dea3101e 3432
2e0fef85 3433 if (vport->fc_flag & FC_OFFLINE_MODE)
46fa311e 3434 return;
dea3101e 3435
618a5230 3436 lpfc_block_mgmt_io(phba, mbx_action);
dea3101e 3437
3438 lpfc_linkdown(phba);
3439
87af33fe
JS
3440 /* Issue an unreg_login to all nodes on all vports */
3441 vports = lpfc_create_vport_work_array(phba);
3442 if (vports != NULL) {
da0436e9 3443 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
a8adb832
JS
3444 if (vports[i]->load_flag & FC_UNLOADING)
3445 continue;
72100cc4
JS
3446 shost = lpfc_shost_from_vport(vports[i]);
3447 spin_lock_irq(shost->host_lock);
c868595d 3448 vports[i]->vpi_state &= ~LPFC_VPI_REGISTERED;
695a814e
JS
3449 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
3450 vports[i]->fc_flag &= ~FC_VFI_REGISTERED;
72100cc4 3451 spin_unlock_irq(shost->host_lock);
695a814e 3452
87af33fe
JS
3453 shost = lpfc_shost_from_vport(vports[i]);
3454 list_for_each_entry_safe(ndlp, next_ndlp,
3455 &vports[i]->fc_nodes,
3456 nlp_listp) {
0f154226
JS
3457 if ((!NLP_CHK_NODE_ACT(ndlp)) ||
3458 ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
3459 /* Driver must assume RPI is invalid for
3460 * any unused or inactive node.
3461 */
3462 ndlp->nlp_rpi = LPFC_RPI_ALLOC_ERROR;
87af33fe 3463 continue;
0f154226
JS
3464 }
3465
87af33fe
JS
3466 if (ndlp->nlp_type & NLP_FABRIC) {
3467 lpfc_disc_state_machine(vports[i], ndlp,
3468 NULL, NLP_EVT_DEVICE_RECOVERY);
3469 lpfc_disc_state_machine(vports[i], ndlp,
3470 NULL, NLP_EVT_DEVICE_RM);
3471 }
3472 spin_lock_irq(shost->host_lock);
3473 ndlp->nlp_flag &= ~NLP_NPR_ADISC;
401ee0c1 3474 spin_unlock_irq(shost->host_lock);
6b5151fd
JS
3475 /*
3476 * Whenever an SLI4 port goes offline, free the
401ee0c1
JS
3477 * RPI. Get a new RPI when the adapter port
3478 * comes back online.
6b5151fd 3479 */
be6bb941 3480 if (phba->sli_rev == LPFC_SLI_REV4) {
0f154226
JS
3481 lpfc_printf_vlog(ndlp->vport, KERN_INFO,
3482 LOG_NODE | LOG_DISCOVERY,
3483 "0011 Free RPI x%x on "
3484 "ndlp:x%px did x%x "
3485 "usgmap:x%x\n",
3486 ndlp->nlp_rpi, ndlp,
3487 ndlp->nlp_DID,
3488 ndlp->nlp_usg_map);
6b5151fd 3489 lpfc_sli4_free_rpi(phba, ndlp->nlp_rpi);
0f154226 3490 ndlp->nlp_rpi = LPFC_RPI_ALLOC_ERROR;
be6bb941 3491 }
87af33fe
JS
3492 lpfc_unreg_rpi(vports[i], ndlp);
3493 }
3494 }
3495 }
09372820 3496 lpfc_destroy_vport_work_array(phba, vports);
dea3101e 3497
618a5230 3498 lpfc_sli_mbox_sys_shutdown(phba, mbx_action);
f485c18d
DK
3499
3500 if (phba->wq)
3501 flush_workqueue(phba->wq);
46fa311e
JS
3502}
3503
e59058c4 3504/**
3621a710 3505 * lpfc_offline - Bring a HBA offline
e59058c4
JS
3506 * @phba: pointer to lpfc hba data structure.
3507 *
3508 * This routine actually brings a HBA offline. It stops all the timers
3509 * associated with the HBA, brings down the SLI layer, and eventually
3510 * marks the HBA as in offline state for the upper layer protocol.
3511 **/
46fa311e 3512void
2e0fef85 3513lpfc_offline(struct lpfc_hba *phba)
46fa311e 3514{
549e55cd
JS
3515 struct Scsi_Host *shost;
3516 struct lpfc_vport **vports;
3517 int i;
46fa311e 3518
549e55cd 3519 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
46fa311e 3520 return;
688a8863 3521
da0436e9
JS
3522 /* stop port and all timers associated with this hba */
3523 lpfc_stop_port(phba);
4b40d02b
DK
3524
3525 /* Tear down the local and target port registrations. The
3526 * nvme transports need to cleanup.
3527 */
3528 lpfc_nvmet_destroy_targetport(phba);
3529 lpfc_nvme_destroy_localport(phba->pport);
3530
51ef4c26
JS
3531 vports = lpfc_create_vport_work_array(phba);
3532 if (vports != NULL)
da0436e9 3533 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
51ef4c26 3534 lpfc_stop_vport_timers(vports[i]);
09372820 3535 lpfc_destroy_vport_work_array(phba, vports);
92d7f7b0 3536 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
e8b62011 3537 "0460 Bring Adapter offline\n");
dea3101e 3538 /* Bring down the SLI Layer and cleanup. The HBA is offline
3539 now. */
3540 lpfc_sli_hba_down(phba);
92d7f7b0 3541 spin_lock_irq(&phba->hbalock);
7054a606 3542 phba->work_ha = 0;
92d7f7b0 3543 spin_unlock_irq(&phba->hbalock);
549e55cd
JS
3544 vports = lpfc_create_vport_work_array(phba);
3545 if (vports != NULL)
da0436e9 3546 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
549e55cd 3547 shost = lpfc_shost_from_vport(vports[i]);
549e55cd
JS
3548 spin_lock_irq(shost->host_lock);
3549 vports[i]->work_port_events = 0;
3550 vports[i]->fc_flag |= FC_OFFLINE_MODE;
3551 spin_unlock_irq(shost->host_lock);
3552 }
09372820 3553 lpfc_destroy_vport_work_array(phba, vports);
c490850a
JS
3554
3555 if (phba->cfg_xri_rebalancing)
3556 lpfc_destroy_multixri_pools(phba);
dea3101e 3557}
3558
e59058c4 3559/**
3621a710 3560 * lpfc_scsi_free - Free all the SCSI buffers and IOCBs from driver lists
e59058c4
JS
3561 * @phba: pointer to lpfc hba data structure.
3562 *
3563 * This routine is to free all the SCSI buffers and IOCBs from the driver
3564 * list back to kernel. It is called from lpfc_pci_remove_one to free
3565 * the internal resources before the device is removed from the system.
e59058c4 3566 **/
8a9d2e80 3567static void
2e0fef85 3568lpfc_scsi_free(struct lpfc_hba *phba)
dea3101e 3569{
c490850a 3570 struct lpfc_io_buf *sb, *sb_next;
dea3101e 3571
895427bd
JS
3572 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
3573 return;
3574
2e0fef85 3575 spin_lock_irq(&phba->hbalock);
a40fc5f0 3576
dea3101e 3577 /* Release all the lpfc_scsi_bufs maintained by this host. */
a40fc5f0
JS
3578
3579 spin_lock(&phba->scsi_buf_list_put_lock);
3580 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_put,
3581 list) {
dea3101e 3582 list_del(&sb->list);
771db5c0 3583 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
92d7f7b0 3584 sb->dma_handle);
dea3101e 3585 kfree(sb);
3586 phba->total_scsi_bufs--;
3587 }
a40fc5f0
JS
3588 spin_unlock(&phba->scsi_buf_list_put_lock);
3589
3590 spin_lock(&phba->scsi_buf_list_get_lock);
3591 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_get,
3592 list) {
dea3101e 3593 list_del(&sb->list);
771db5c0 3594 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
92d7f7b0 3595 sb->dma_handle);
dea3101e 3596 kfree(sb);
3597 phba->total_scsi_bufs--;
3598 }
a40fc5f0 3599 spin_unlock(&phba->scsi_buf_list_get_lock);
2e0fef85 3600 spin_unlock_irq(&phba->hbalock);
8a9d2e80 3601}
0794d601 3602
895427bd 3603/**
5e5b511d 3604 * lpfc_io_free - Free all the IO buffers and IOCBs from driver lists
895427bd
JS
3605 * @phba: pointer to lpfc hba data structure.
3606 *
0794d601 3607 * This routine is to free all the IO buffers and IOCBs from the driver
895427bd
JS
3608 * list back to kernel. It is called from lpfc_pci_remove_one to free
3609 * the internal resources before the device is removed from the system.
3610 **/
c490850a 3611void
5e5b511d 3612lpfc_io_free(struct lpfc_hba *phba)
895427bd 3613{
c490850a 3614 struct lpfc_io_buf *lpfc_ncmd, *lpfc_ncmd_next;
5e5b511d
JS
3615 struct lpfc_sli4_hdw_queue *qp;
3616 int idx;
895427bd 3617
5e5b511d
JS
3618 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3619 qp = &phba->sli4_hba.hdwq[idx];
3620 /* Release all the lpfc_nvme_bufs maintained by this host. */
3621 spin_lock(&qp->io_buf_list_put_lock);
3622 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3623 &qp->lpfc_io_buf_list_put,
3624 list) {
3625 list_del(&lpfc_ncmd->list);
3626 qp->put_io_bufs--;
3627 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3628 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
d79c9e9d
JS
3629 if (phba->cfg_xpsgl && !phba->nvmet_support)
3630 lpfc_put_sgl_per_hdwq(phba, lpfc_ncmd);
3631 lpfc_put_cmd_rsp_buf_per_hdwq(phba, lpfc_ncmd);
5e5b511d
JS
3632 kfree(lpfc_ncmd);
3633 qp->total_io_bufs--;
3634 }
3635 spin_unlock(&qp->io_buf_list_put_lock);
3636
3637 spin_lock(&qp->io_buf_list_get_lock);
3638 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3639 &qp->lpfc_io_buf_list_get,
3640 list) {
3641 list_del(&lpfc_ncmd->list);
3642 qp->get_io_bufs--;
3643 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3644 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
d79c9e9d
JS
3645 if (phba->cfg_xpsgl && !phba->nvmet_support)
3646 lpfc_put_sgl_per_hdwq(phba, lpfc_ncmd);
3647 lpfc_put_cmd_rsp_buf_per_hdwq(phba, lpfc_ncmd);
5e5b511d
JS
3648 kfree(lpfc_ncmd);
3649 qp->total_io_bufs--;
3650 }
3651 spin_unlock(&qp->io_buf_list_get_lock);
895427bd 3652 }
895427bd 3653}
0794d601 3654
8a9d2e80 3655/**
895427bd 3656 * lpfc_sli4_els_sgl_update - update ELS xri-sgl sizing and mapping
8a9d2e80
JS
3657 * @phba: pointer to lpfc hba data structure.
3658 *
3659 * This routine first calculates the sizes of the current els and allocated
3660 * scsi sgl lists, and then goes through all sgls to updates the physical
3661 * XRIs assigned due to port function reset. During port initialization, the
3662 * current els and allocated scsi sgl lists are 0s.
3663 *
3664 * Return codes
3665 * 0 - successful (for now, it always returns 0)
3666 **/
3667int
895427bd 3668lpfc_sli4_els_sgl_update(struct lpfc_hba *phba)
8a9d2e80
JS
3669{
3670 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
895427bd 3671 uint16_t i, lxri, xri_cnt, els_xri_cnt;
8a9d2e80 3672 LIST_HEAD(els_sgl_list);
8a9d2e80
JS
3673 int rc;
3674
3675 /*
3676 * update on pci function's els xri-sgl list
3677 */
3678 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
895427bd 3679
8a9d2e80
JS
3680 if (els_xri_cnt > phba->sli4_hba.els_xri_cnt) {
3681 /* els xri-sgl expanded */
3682 xri_cnt = els_xri_cnt - phba->sli4_hba.els_xri_cnt;
3683 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3684 "3157 ELS xri-sgl count increased from "
3685 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3686 els_xri_cnt);
3687 /* allocate the additional els sgls */
3688 for (i = 0; i < xri_cnt; i++) {
3689 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3690 GFP_KERNEL);
3691 if (sglq_entry == NULL) {
3692 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3693 "2562 Failure to allocate an "
3694 "ELS sgl entry:%d\n", i);
3695 rc = -ENOMEM;
3696 goto out_free_mem;
3697 }
3698 sglq_entry->buff_type = GEN_BUFF_TYPE;
3699 sglq_entry->virt = lpfc_mbuf_alloc(phba, 0,
3700 &sglq_entry->phys);
3701 if (sglq_entry->virt == NULL) {
3702 kfree(sglq_entry);
3703 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3704 "2563 Failure to allocate an "
3705 "ELS mbuf:%d\n", i);
3706 rc = -ENOMEM;
3707 goto out_free_mem;
3708 }
3709 sglq_entry->sgl = sglq_entry->virt;
3710 memset(sglq_entry->sgl, 0, LPFC_BPL_SIZE);
3711 sglq_entry->state = SGL_FREED;
3712 list_add_tail(&sglq_entry->list, &els_sgl_list);
3713 }
38c20673 3714 spin_lock_irq(&phba->hbalock);
895427bd
JS
3715 spin_lock(&phba->sli4_hba.sgl_list_lock);
3716 list_splice_init(&els_sgl_list,
3717 &phba->sli4_hba.lpfc_els_sgl_list);
3718 spin_unlock(&phba->sli4_hba.sgl_list_lock);
38c20673 3719 spin_unlock_irq(&phba->hbalock);
8a9d2e80
JS
3720 } else if (els_xri_cnt < phba->sli4_hba.els_xri_cnt) {
3721 /* els xri-sgl shrinked */
3722 xri_cnt = phba->sli4_hba.els_xri_cnt - els_xri_cnt;
3723 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3724 "3158 ELS xri-sgl count decreased from "
3725 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3726 els_xri_cnt);
3727 spin_lock_irq(&phba->hbalock);
895427bd
JS
3728 spin_lock(&phba->sli4_hba.sgl_list_lock);
3729 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list,
3730 &els_sgl_list);
8a9d2e80
JS
3731 /* release extra els sgls from list */
3732 for (i = 0; i < xri_cnt; i++) {
3733 list_remove_head(&els_sgl_list,
3734 sglq_entry, struct lpfc_sglq, list);
3735 if (sglq_entry) {
895427bd
JS
3736 __lpfc_mbuf_free(phba, sglq_entry->virt,
3737 sglq_entry->phys);
8a9d2e80
JS
3738 kfree(sglq_entry);
3739 }
3740 }
895427bd
JS
3741 list_splice_init(&els_sgl_list,
3742 &phba->sli4_hba.lpfc_els_sgl_list);
3743 spin_unlock(&phba->sli4_hba.sgl_list_lock);
8a9d2e80
JS
3744 spin_unlock_irq(&phba->hbalock);
3745 } else
3746 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3747 "3163 ELS xri-sgl count unchanged: %d\n",
3748 els_xri_cnt);
3749 phba->sli4_hba.els_xri_cnt = els_xri_cnt;
3750
3751 /* update xris to els sgls on the list */
3752 sglq_entry = NULL;
3753 sglq_entry_next = NULL;
3754 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
895427bd 3755 &phba->sli4_hba.lpfc_els_sgl_list, list) {
8a9d2e80
JS
3756 lxri = lpfc_sli4_next_xritag(phba);
3757 if (lxri == NO_XRI) {
3758 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3759 "2400 Failed to allocate xri for "
3760 "ELS sgl\n");
3761 rc = -ENOMEM;
3762 goto out_free_mem;
3763 }
3764 sglq_entry->sli4_lxritag = lxri;
3765 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3766 }
895427bd
JS
3767 return 0;
3768
3769out_free_mem:
3770 lpfc_free_els_sgl_list(phba);
3771 return rc;
3772}
3773
f358dd0c
JS
3774/**
3775 * lpfc_sli4_nvmet_sgl_update - update xri-sgl sizing and mapping
3776 * @phba: pointer to lpfc hba data structure.
3777 *
3778 * This routine first calculates the sizes of the current els and allocated
3779 * scsi sgl lists, and then goes through all sgls to updates the physical
3780 * XRIs assigned due to port function reset. During port initialization, the
3781 * current els and allocated scsi sgl lists are 0s.
3782 *
3783 * Return codes
3784 * 0 - successful (for now, it always returns 0)
3785 **/
3786int
3787lpfc_sli4_nvmet_sgl_update(struct lpfc_hba *phba)
3788{
3789 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
3790 uint16_t i, lxri, xri_cnt, els_xri_cnt;
6c621a22 3791 uint16_t nvmet_xri_cnt;
f358dd0c
JS
3792 LIST_HEAD(nvmet_sgl_list);
3793 int rc;
3794
3795 /*
3796 * update on pci function's nvmet xri-sgl list
3797 */
3798 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
61f3d4bf 3799
6c621a22
JS
3800 /* For NVMET, ALL remaining XRIs are dedicated for IO processing */
3801 nvmet_xri_cnt = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
f358dd0c
JS
3802 if (nvmet_xri_cnt > phba->sli4_hba.nvmet_xri_cnt) {
3803 /* els xri-sgl expanded */
3804 xri_cnt = nvmet_xri_cnt - phba->sli4_hba.nvmet_xri_cnt;
3805 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3806 "6302 NVMET xri-sgl cnt grew from %d to %d\n",
3807 phba->sli4_hba.nvmet_xri_cnt, nvmet_xri_cnt);
3808 /* allocate the additional nvmet sgls */
3809 for (i = 0; i < xri_cnt; i++) {
3810 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3811 GFP_KERNEL);
3812 if (sglq_entry == NULL) {
3813 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3814 "6303 Failure to allocate an "
3815 "NVMET sgl entry:%d\n", i);
3816 rc = -ENOMEM;
3817 goto out_free_mem;
3818 }
3819 sglq_entry->buff_type = NVMET_BUFF_TYPE;
3820 sglq_entry->virt = lpfc_nvmet_buf_alloc(phba, 0,
3821 &sglq_entry->phys);
3822 if (sglq_entry->virt == NULL) {
3823 kfree(sglq_entry);
3824 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3825 "6304 Failure to allocate an "
3826 "NVMET buf:%d\n", i);
3827 rc = -ENOMEM;
3828 goto out_free_mem;
3829 }
3830 sglq_entry->sgl = sglq_entry->virt;
3831 memset(sglq_entry->sgl, 0,
3832 phba->cfg_sg_dma_buf_size);
3833 sglq_entry->state = SGL_FREED;
3834 list_add_tail(&sglq_entry->list, &nvmet_sgl_list);
3835 }
3836 spin_lock_irq(&phba->hbalock);
3837 spin_lock(&phba->sli4_hba.sgl_list_lock);
3838 list_splice_init(&nvmet_sgl_list,
3839 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3840 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3841 spin_unlock_irq(&phba->hbalock);
3842 } else if (nvmet_xri_cnt < phba->sli4_hba.nvmet_xri_cnt) {
3843 /* nvmet xri-sgl shrunk */
3844 xri_cnt = phba->sli4_hba.nvmet_xri_cnt - nvmet_xri_cnt;
3845 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3846 "6305 NVMET xri-sgl count decreased from "
3847 "%d to %d\n", phba->sli4_hba.nvmet_xri_cnt,
3848 nvmet_xri_cnt);
3849 spin_lock_irq(&phba->hbalock);
3850 spin_lock(&phba->sli4_hba.sgl_list_lock);
3851 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list,
3852 &nvmet_sgl_list);
3853 /* release extra nvmet sgls from list */
3854 for (i = 0; i < xri_cnt; i++) {
3855 list_remove_head(&nvmet_sgl_list,
3856 sglq_entry, struct lpfc_sglq, list);
3857 if (sglq_entry) {
3858 lpfc_nvmet_buf_free(phba, sglq_entry->virt,
3859 sglq_entry->phys);
3860 kfree(sglq_entry);
3861 }
3862 }
3863 list_splice_init(&nvmet_sgl_list,
3864 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3865 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3866 spin_unlock_irq(&phba->hbalock);
3867 } else
3868 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3869 "6306 NVMET xri-sgl count unchanged: %d\n",
3870 nvmet_xri_cnt);
3871 phba->sli4_hba.nvmet_xri_cnt = nvmet_xri_cnt;
3872
3873 /* update xris to nvmet sgls on the list */
3874 sglq_entry = NULL;
3875 sglq_entry_next = NULL;
3876 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
3877 &phba->sli4_hba.lpfc_nvmet_sgl_list, list) {
3878 lxri = lpfc_sli4_next_xritag(phba);
3879 if (lxri == NO_XRI) {
3880 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3881 "6307 Failed to allocate xri for "
3882 "NVMET sgl\n");
3883 rc = -ENOMEM;
3884 goto out_free_mem;
3885 }
3886 sglq_entry->sli4_lxritag = lxri;
3887 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3888 }
3889 return 0;
3890
3891out_free_mem:
3892 lpfc_free_nvmet_sgl_list(phba);
3893 return rc;
3894}
3895
5e5b511d
JS
3896int
3897lpfc_io_buf_flush(struct lpfc_hba *phba, struct list_head *cbuf)
3898{
3899 LIST_HEAD(blist);
3900 struct lpfc_sli4_hdw_queue *qp;
c490850a
JS
3901 struct lpfc_io_buf *lpfc_cmd;
3902 struct lpfc_io_buf *iobufp, *prev_iobufp;
5e5b511d
JS
3903 int idx, cnt, xri, inserted;
3904
3905 cnt = 0;
3906 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3907 qp = &phba->sli4_hba.hdwq[idx];
3908 spin_lock_irq(&qp->io_buf_list_get_lock);
3909 spin_lock(&qp->io_buf_list_put_lock);
3910
3911 /* Take everything off the get and put lists */
3912 list_splice_init(&qp->lpfc_io_buf_list_get, &blist);
3913 list_splice(&qp->lpfc_io_buf_list_put, &blist);
3914 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
3915 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
3916 cnt += qp->get_io_bufs + qp->put_io_bufs;
3917 qp->get_io_bufs = 0;
3918 qp->put_io_bufs = 0;
3919 qp->total_io_bufs = 0;
3920 spin_unlock(&qp->io_buf_list_put_lock);
3921 spin_unlock_irq(&qp->io_buf_list_get_lock);
3922 }
3923
3924 /*
3925 * Take IO buffers off blist and put on cbuf sorted by XRI.
3926 * This is because POST_SGL takes a sequential range of XRIs
3927 * to post to the firmware.
3928 */
3929 for (idx = 0; idx < cnt; idx++) {
c490850a 3930 list_remove_head(&blist, lpfc_cmd, struct lpfc_io_buf, list);
5e5b511d
JS
3931 if (!lpfc_cmd)
3932 return cnt;
3933 if (idx == 0) {
3934 list_add_tail(&lpfc_cmd->list, cbuf);
3935 continue;
3936 }
3937 xri = lpfc_cmd->cur_iocbq.sli4_xritag;
3938 inserted = 0;
3939 prev_iobufp = NULL;
3940 list_for_each_entry(iobufp, cbuf, list) {
3941 if (xri < iobufp->cur_iocbq.sli4_xritag) {
3942 if (prev_iobufp)
3943 list_add(&lpfc_cmd->list,
3944 &prev_iobufp->list);
3945 else
3946 list_add(&lpfc_cmd->list, cbuf);
3947 inserted = 1;
3948 break;
3949 }
3950 prev_iobufp = iobufp;
3951 }
3952 if (!inserted)
3953 list_add_tail(&lpfc_cmd->list, cbuf);
3954 }
3955 return cnt;
3956}
3957
3958int
3959lpfc_io_buf_replenish(struct lpfc_hba *phba, struct list_head *cbuf)
3960{
3961 struct lpfc_sli4_hdw_queue *qp;
c490850a 3962 struct lpfc_io_buf *lpfc_cmd;
5e5b511d
JS
3963 int idx, cnt;
3964
3965 qp = phba->sli4_hba.hdwq;
3966 cnt = 0;
3967 while (!list_empty(cbuf)) {
3968 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3969 list_remove_head(cbuf, lpfc_cmd,
c490850a 3970 struct lpfc_io_buf, list);
5e5b511d
JS
3971 if (!lpfc_cmd)
3972 return cnt;
3973 cnt++;
3974 qp = &phba->sli4_hba.hdwq[idx];
1fbf9742
JS
3975 lpfc_cmd->hdwq_no = idx;
3976 lpfc_cmd->hdwq = qp;
5e5b511d
JS
3977 lpfc_cmd->cur_iocbq.wqe_cmpl = NULL;
3978 lpfc_cmd->cur_iocbq.iocb_cmpl = NULL;
3979 spin_lock(&qp->io_buf_list_put_lock);
3980 list_add_tail(&lpfc_cmd->list,
3981 &qp->lpfc_io_buf_list_put);
3982 qp->put_io_bufs++;
3983 qp->total_io_bufs++;
3984 spin_unlock(&qp->io_buf_list_put_lock);
3985 }
3986 }
3987 return cnt;
3988}
3989
895427bd 3990/**
5e5b511d 3991 * lpfc_sli4_io_sgl_update - update xri-sgl sizing and mapping
895427bd
JS
3992 * @phba: pointer to lpfc hba data structure.
3993 *
3994 * This routine first calculates the sizes of the current els and allocated
3995 * scsi sgl lists, and then goes through all sgls to updates the physical
3996 * XRIs assigned due to port function reset. During port initialization, the
3997 * current els and allocated scsi sgl lists are 0s.
3998 *
3999 * Return codes
4000 * 0 - successful (for now, it always returns 0)
4001 **/
4002int
5e5b511d 4003lpfc_sli4_io_sgl_update(struct lpfc_hba *phba)
895427bd 4004{
c490850a 4005 struct lpfc_io_buf *lpfc_ncmd = NULL, *lpfc_ncmd_next = NULL;
0794d601 4006 uint16_t i, lxri, els_xri_cnt;
5e5b511d
JS
4007 uint16_t io_xri_cnt, io_xri_max;
4008 LIST_HEAD(io_sgl_list);
0794d601 4009 int rc, cnt;
8a9d2e80 4010
895427bd 4011 /*
0794d601 4012 * update on pci function's allocated nvme xri-sgl list
895427bd 4013 */
8a9d2e80 4014
0794d601
JS
4015 /* maximum number of xris available for nvme buffers */
4016 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
5e5b511d
JS
4017 io_xri_max = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
4018 phba->sli4_hba.io_xri_max = io_xri_max;
895427bd 4019
e8c0a779 4020 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
0794d601
JS
4021 "6074 Current allocated XRI sgl count:%d, "
4022 "maximum XRI count:%d\n",
5e5b511d
JS
4023 phba->sli4_hba.io_xri_cnt,
4024 phba->sli4_hba.io_xri_max);
8a9d2e80 4025
5e5b511d 4026 cnt = lpfc_io_buf_flush(phba, &io_sgl_list);
8a9d2e80 4027
5e5b511d 4028 if (phba->sli4_hba.io_xri_cnt > phba->sli4_hba.io_xri_max) {
0794d601 4029 /* max nvme xri shrunk below the allocated nvme buffers */
5e5b511d
JS
4030 io_xri_cnt = phba->sli4_hba.io_xri_cnt -
4031 phba->sli4_hba.io_xri_max;
0794d601 4032 /* release the extra allocated nvme buffers */
5e5b511d
JS
4033 for (i = 0; i < io_xri_cnt; i++) {
4034 list_remove_head(&io_sgl_list, lpfc_ncmd,
c490850a 4035 struct lpfc_io_buf, list);
0794d601 4036 if (lpfc_ncmd) {
771db5c0 4037 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
0794d601
JS
4038 lpfc_ncmd->data,
4039 lpfc_ncmd->dma_handle);
4040 kfree(lpfc_ncmd);
a2fc4aef 4041 }
8a9d2e80 4042 }
5e5b511d 4043 phba->sli4_hba.io_xri_cnt -= io_xri_cnt;
8a9d2e80
JS
4044 }
4045
0794d601
JS
4046 /* update xris associated to remaining allocated nvme buffers */
4047 lpfc_ncmd = NULL;
4048 lpfc_ncmd_next = NULL;
5e5b511d 4049 phba->sli4_hba.io_xri_cnt = cnt;
0794d601 4050 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
5e5b511d 4051 &io_sgl_list, list) {
8a9d2e80
JS
4052 lxri = lpfc_sli4_next_xritag(phba);
4053 if (lxri == NO_XRI) {
4054 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
0794d601
JS
4055 "6075 Failed to allocate xri for "
4056 "nvme buffer\n");
8a9d2e80
JS
4057 rc = -ENOMEM;
4058 goto out_free_mem;
4059 }
0794d601
JS
4060 lpfc_ncmd->cur_iocbq.sli4_lxritag = lxri;
4061 lpfc_ncmd->cur_iocbq.sli4_xritag = phba->sli4_hba.xri_ids[lxri];
8a9d2e80 4062 }
5e5b511d 4063 cnt = lpfc_io_buf_replenish(phba, &io_sgl_list);
dea3101e 4064 return 0;
8a9d2e80
JS
4065
4066out_free_mem:
5e5b511d 4067 lpfc_io_free(phba);
8a9d2e80 4068 return rc;
dea3101e 4069}
4070
0794d601 4071/**
5e5b511d 4072 * lpfc_new_io_buf - IO buffer allocator for HBA with SLI4 IF spec
0794d601
JS
4073 * @vport: The virtual port for which this call being executed.
4074 * @num_to_allocate: The requested number of buffers to allocate.
4075 *
4076 * This routine allocates nvme buffers for device with SLI-4 interface spec,
4077 * the nvme buffer contains all the necessary information needed to initiate
4078 * an I/O. After allocating up to @num_to_allocate IO buffers and put
4079 * them on a list, it post them to the port by using SGL block post.
4080 *
4081 * Return codes:
5e5b511d 4082 * int - number of IO buffers that were allocated and posted.
0794d601
JS
4083 * 0 = failure, less than num_to_alloc is a partial failure.
4084 **/
4085int
5e5b511d 4086lpfc_new_io_buf(struct lpfc_hba *phba, int num_to_alloc)
0794d601 4087{
c490850a 4088 struct lpfc_io_buf *lpfc_ncmd;
0794d601
JS
4089 struct lpfc_iocbq *pwqeq;
4090 uint16_t iotag, lxri = 0;
4091 int bcnt, num_posted;
4092 LIST_HEAD(prep_nblist);
4093 LIST_HEAD(post_nblist);
4094 LIST_HEAD(nvme_nblist);
4095
5e5b511d 4096 phba->sli4_hba.io_xri_cnt = 0;
0794d601 4097 for (bcnt = 0; bcnt < num_to_alloc; bcnt++) {
7f9989ba 4098 lpfc_ncmd = kzalloc(sizeof(*lpfc_ncmd), GFP_KERNEL);
0794d601
JS
4099 if (!lpfc_ncmd)
4100 break;
4101 /*
4102 * Get memory from the pci pool to map the virt space to
4103 * pci bus space for an I/O. The DMA buffer includes the
4104 * number of SGE's necessary to support the sg_tablesize.
4105 */
a5c990ee
TM
4106 lpfc_ncmd->data = dma_pool_zalloc(phba->lpfc_sg_dma_buf_pool,
4107 GFP_KERNEL,
4108 &lpfc_ncmd->dma_handle);
0794d601
JS
4109 if (!lpfc_ncmd->data) {
4110 kfree(lpfc_ncmd);
4111 break;
4112 }
0794d601 4113
d79c9e9d
JS
4114 if (phba->cfg_xpsgl && !phba->nvmet_support) {
4115 INIT_LIST_HEAD(&lpfc_ncmd->dma_sgl_xtra_list);
4116 } else {
4117 /*
4118 * 4K Page alignment is CRITICAL to BlockGuard, double
4119 * check to be sure.
4120 */
4121 if ((phba->sli3_options & LPFC_SLI3_BG_ENABLED) &&
4122 (((unsigned long)(lpfc_ncmd->data) &
4123 (unsigned long)(SLI4_PAGE_SIZE - 1)) != 0)) {
4124 lpfc_printf_log(phba, KERN_ERR, LOG_FCP,
4125 "3369 Memory alignment err: "
4126 "addr=%lx\n",
4127 (unsigned long)lpfc_ncmd->data);
4128 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4129 lpfc_ncmd->data,
4130 lpfc_ncmd->dma_handle);
4131 kfree(lpfc_ncmd);
4132 break;
4133 }
0794d601
JS
4134 }
4135
d79c9e9d
JS
4136 INIT_LIST_HEAD(&lpfc_ncmd->dma_cmd_rsp_list);
4137
0794d601
JS
4138 lxri = lpfc_sli4_next_xritag(phba);
4139 if (lxri == NO_XRI) {
4140 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4141 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4142 kfree(lpfc_ncmd);
4143 break;
4144 }
4145 pwqeq = &lpfc_ncmd->cur_iocbq;
4146
4147 /* Allocate iotag for lpfc_ncmd->cur_iocbq. */
4148 iotag = lpfc_sli_next_iotag(phba, pwqeq);
4149 if (iotag == 0) {
4150 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4151 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4152 kfree(lpfc_ncmd);
4153 lpfc_printf_log(phba, KERN_ERR, LOG_NVME_IOERR,
4154 "6121 Failed to allocate IOTAG for"
4155 " XRI:0x%x\n", lxri);
4156 lpfc_sli4_free_xri(phba, lxri);
4157 break;
4158 }
4159 pwqeq->sli4_lxritag = lxri;
4160 pwqeq->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
4161 pwqeq->context1 = lpfc_ncmd;
4162
4163 /* Initialize local short-hand pointers. */
4164 lpfc_ncmd->dma_sgl = lpfc_ncmd->data;
4165 lpfc_ncmd->dma_phys_sgl = lpfc_ncmd->dma_handle;
4166 lpfc_ncmd->cur_iocbq.context1 = lpfc_ncmd;
c2017260 4167 spin_lock_init(&lpfc_ncmd->buf_lock);
0794d601
JS
4168
4169 /* add the nvme buffer to a post list */
4170 list_add_tail(&lpfc_ncmd->list, &post_nblist);
5e5b511d 4171 phba->sli4_hba.io_xri_cnt++;
0794d601
JS
4172 }
4173 lpfc_printf_log(phba, KERN_INFO, LOG_NVME,
4174 "6114 Allocate %d out of %d requested new NVME "
4175 "buffers\n", bcnt, num_to_alloc);
4176
4177 /* post the list of nvme buffer sgls to port if available */
4178 if (!list_empty(&post_nblist))
5e5b511d 4179 num_posted = lpfc_sli4_post_io_sgl_list(
0794d601
JS
4180 phba, &post_nblist, bcnt);
4181 else
4182 num_posted = 0;
4183
4184 return num_posted;
4185}
4186
96418b5e
JS
4187static uint64_t
4188lpfc_get_wwpn(struct lpfc_hba *phba)
4189{
4190 uint64_t wwn;
4191 int rc;
4192 LPFC_MBOXQ_t *mboxq;
4193 MAILBOX_t *mb;
4194
96418b5e
JS
4195 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
4196 GFP_KERNEL);
4197 if (!mboxq)
4198 return (uint64_t)-1;
4199
4200 /* First get WWN of HBA instance */
4201 lpfc_read_nv(phba, mboxq);
4202 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
4203 if (rc != MBX_SUCCESS) {
4204 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4205 "6019 Mailbox failed , mbxCmd x%x "
4206 "READ_NV, mbxStatus x%x\n",
4207 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
4208 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
4209 mempool_free(mboxq, phba->mbox_mem_pool);
4210 return (uint64_t) -1;
4211 }
4212 mb = &mboxq->u.mb;
4213 memcpy(&wwn, (char *)mb->un.varRDnvp.portname, sizeof(uint64_t));
4214 /* wwn is WWPN of HBA instance */
4215 mempool_free(mboxq, phba->mbox_mem_pool);
4216 if (phba->sli_rev == LPFC_SLI_REV4)
4217 return be64_to_cpu(wwn);
4218 else
286871a6 4219 return rol64(wwn, 32);
96418b5e
JS
4220}
4221
e59058c4 4222/**
3621a710 4223 * lpfc_create_port - Create an FC port
e59058c4
JS
4224 * @phba: pointer to lpfc hba data structure.
4225 * @instance: a unique integer ID to this FC port.
4226 * @dev: pointer to the device data structure.
4227 *
4228 * This routine creates a FC port for the upper layer protocol. The FC port
4229 * can be created on top of either a physical port or a virtual port provided
4230 * by the HBA. This routine also allocates a SCSI host data structure (shost)
4231 * and associates the FC port created before adding the shost into the SCSI
4232 * layer.
4233 *
4234 * Return codes
4235 * @vport - pointer to the virtual N_Port data structure.
4236 * NULL - port create failed.
4237 **/
2e0fef85 4238struct lpfc_vport *
3de2a653 4239lpfc_create_port(struct lpfc_hba *phba, int instance, struct device *dev)
47a8617c 4240{
2e0fef85 4241 struct lpfc_vport *vport;
895427bd 4242 struct Scsi_Host *shost = NULL;
2e0fef85 4243 int error = 0;
96418b5e
JS
4244 int i;
4245 uint64_t wwn;
4246 bool use_no_reset_hba = false;
56bc8028 4247 int rc;
96418b5e 4248
56bc8028
JS
4249 if (lpfc_no_hba_reset_cnt) {
4250 if (phba->sli_rev < LPFC_SLI_REV4 &&
4251 dev == &phba->pcidev->dev) {
4252 /* Reset the port first */
4253 lpfc_sli_brdrestart(phba);
4254 rc = lpfc_sli_chipset_init(phba);
4255 if (rc)
4256 return NULL;
4257 }
4258 wwn = lpfc_get_wwpn(phba);
4259 }
96418b5e
JS
4260
4261 for (i = 0; i < lpfc_no_hba_reset_cnt; i++) {
4262 if (wwn == lpfc_no_hba_reset[i]) {
4263 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4264 "6020 Setting use_no_reset port=%llx\n",
4265 wwn);
4266 use_no_reset_hba = true;
4267 break;
4268 }
4269 }
47a8617c 4270
895427bd
JS
4271 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
4272 if (dev != &phba->pcidev->dev) {
4273 shost = scsi_host_alloc(&lpfc_vport_template,
4274 sizeof(struct lpfc_vport));
4275 } else {
96418b5e 4276 if (!use_no_reset_hba)
895427bd
JS
4277 shost = scsi_host_alloc(&lpfc_template,
4278 sizeof(struct lpfc_vport));
4279 else
96418b5e 4280 shost = scsi_host_alloc(&lpfc_template_no_hr,
895427bd
JS
4281 sizeof(struct lpfc_vport));
4282 }
4283 } else if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
4284 shost = scsi_host_alloc(&lpfc_template_nvme,
ea4142f6
JS
4285 sizeof(struct lpfc_vport));
4286 }
2e0fef85
JS
4287 if (!shost)
4288 goto out;
47a8617c 4289
2e0fef85
JS
4290 vport = (struct lpfc_vport *) shost->hostdata;
4291 vport->phba = phba;
2e0fef85 4292 vport->load_flag |= FC_LOADING;
92d7f7b0 4293 vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
7f5f3d0d 4294 vport->fc_rscn_flush = 0;
3de2a653 4295 lpfc_get_vport_cfgparam(vport);
895427bd 4296
f6e84790
JS
4297 /* Adjust value in vport */
4298 vport->cfg_enable_fc4_type = phba->cfg_enable_fc4_type;
4299
2e0fef85
JS
4300 shost->unique_id = instance;
4301 shost->max_id = LPFC_MAX_TARGET;
3de2a653 4302 shost->max_lun = vport->cfg_max_luns;
2e0fef85
JS
4303 shost->this_id = -1;
4304 shost->max_cmd_len = 16;
6a828b0f 4305
da0436e9 4306 if (phba->sli_rev == LPFC_SLI_REV4) {
77ffd346
JS
4307 if (!phba->cfg_fcp_mq_threshold ||
4308 phba->cfg_fcp_mq_threshold > phba->cfg_hdw_queue)
4309 phba->cfg_fcp_mq_threshold = phba->cfg_hdw_queue;
4310
4311 shost->nr_hw_queues = min_t(int, 2 * num_possible_nodes(),
4312 phba->cfg_fcp_mq_threshold);
6a828b0f 4313
28baac74 4314 shost->dma_boundary =
cb5172ea 4315 phba->sli4_hba.pc_sli4_params.sge_supp_len-1;
d79c9e9d
JS
4316
4317 if (phba->cfg_xpsgl && !phba->nvmet_support)
4318 shost->sg_tablesize = LPFC_MAX_SG_TABLESIZE;
4319 else
4320 shost->sg_tablesize = phba->cfg_scsi_seg_cnt;
ace44e48
JS
4321 } else
4322 /* SLI-3 has a limited number of hardware queues (3),
4323 * thus there is only one for FCP processing.
4324 */
4325 shost->nr_hw_queues = 1;
81301a9b 4326
47a8617c 4327 /*
2e0fef85
JS
4328 * Set initial can_queue value since 0 is no longer supported and
4329 * scsi_add_host will fail. This will be adjusted later based on the
4330 * max xri value determined in hba setup.
47a8617c 4331 */
2e0fef85 4332 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3de2a653 4333 if (dev != &phba->pcidev->dev) {
92d7f7b0
JS
4334 shost->transportt = lpfc_vport_transport_template;
4335 vport->port_type = LPFC_NPIV_PORT;
4336 } else {
4337 shost->transportt = lpfc_transport_template;
4338 vport->port_type = LPFC_PHYSICAL_PORT;
4339 }
47a8617c 4340
2e0fef85
JS
4341 /* Initialize all internally managed lists. */
4342 INIT_LIST_HEAD(&vport->fc_nodes);
da0436e9 4343 INIT_LIST_HEAD(&vport->rcv_buffer_list);
2e0fef85 4344 spin_lock_init(&vport->work_port_lock);
47a8617c 4345
f22eb4d3 4346 timer_setup(&vport->fc_disctmo, lpfc_disc_timeout, 0);
47a8617c 4347
f22eb4d3 4348 timer_setup(&vport->els_tmofunc, lpfc_els_timeout, 0);
92494144 4349
f22eb4d3 4350 timer_setup(&vport->delayed_disc_tmo, lpfc_delayed_disc_tmo, 0);
92494144 4351
aa6ff309
JS
4352 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED)
4353 lpfc_setup_bg(phba, shost);
4354
d139b9bd 4355 error = scsi_add_host_with_dma(shost, dev, &phba->pcidev->dev);
2e0fef85
JS
4356 if (error)
4357 goto out_put_shost;
47a8617c 4358
523128e5 4359 spin_lock_irq(&phba->port_list_lock);
2e0fef85 4360 list_add_tail(&vport->listentry, &phba->port_list);
523128e5 4361 spin_unlock_irq(&phba->port_list_lock);
2e0fef85 4362 return vport;
47a8617c 4363
2e0fef85
JS
4364out_put_shost:
4365 scsi_host_put(shost);
4366out:
4367 return NULL;
47a8617c
JS
4368}
4369
e59058c4 4370/**
3621a710 4371 * destroy_port - destroy an FC port
e59058c4
JS
4372 * @vport: pointer to an lpfc virtual N_Port data structure.
4373 *
4374 * This routine destroys a FC port from the upper layer protocol. All the
4375 * resources associated with the port are released.
4376 **/
2e0fef85
JS
4377void
4378destroy_port(struct lpfc_vport *vport)
47a8617c 4379{
92d7f7b0
JS
4380 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
4381 struct lpfc_hba *phba = vport->phba;
47a8617c 4382
858c9f6c 4383 lpfc_debugfs_terminate(vport);
92d7f7b0
JS
4384 fc_remove_host(shost);
4385 scsi_remove_host(shost);
47a8617c 4386
523128e5 4387 spin_lock_irq(&phba->port_list_lock);
92d7f7b0 4388 list_del_init(&vport->listentry);
523128e5 4389 spin_unlock_irq(&phba->port_list_lock);
47a8617c 4390
92d7f7b0 4391 lpfc_cleanup(vport);
47a8617c 4392 return;
47a8617c
JS
4393}
4394
e59058c4 4395/**
3621a710 4396 * lpfc_get_instance - Get a unique integer ID
e59058c4
JS
4397 *
4398 * This routine allocates a unique integer ID from lpfc_hba_index pool. It
4399 * uses the kernel idr facility to perform the task.
4400 *
4401 * Return codes:
4402 * instance - a unique integer ID allocated as the new instance.
4403 * -1 - lpfc get instance failed.
4404 **/
92d7f7b0
JS
4405int
4406lpfc_get_instance(void)
4407{
ab516036
TH
4408 int ret;
4409
4410 ret = idr_alloc(&lpfc_hba_index, NULL, 0, 0, GFP_KERNEL);
4411 return ret < 0 ? -1 : ret;
47a8617c
JS
4412}
4413
e59058c4 4414/**
3621a710 4415 * lpfc_scan_finished - method for SCSI layer to detect whether scan is done
e59058c4
JS
4416 * @shost: pointer to SCSI host data structure.
4417 * @time: elapsed time of the scan in jiffies.
4418 *
4419 * This routine is called by the SCSI layer with a SCSI host to determine
4420 * whether the scan host is finished.
4421 *
4422 * Note: there is no scan_start function as adapter initialization will have
4423 * asynchronously kicked off the link initialization.
4424 *
4425 * Return codes
4426 * 0 - SCSI host scan is not over yet.
4427 * 1 - SCSI host scan is over.
4428 **/
47a8617c
JS
4429int lpfc_scan_finished(struct Scsi_Host *shost, unsigned long time)
4430{
2e0fef85
JS
4431 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4432 struct lpfc_hba *phba = vport->phba;
858c9f6c 4433 int stat = 0;
47a8617c 4434
858c9f6c
JS
4435 spin_lock_irq(shost->host_lock);
4436
51ef4c26 4437 if (vport->load_flag & FC_UNLOADING) {
858c9f6c
JS
4438 stat = 1;
4439 goto finished;
4440 }
256ec0d0 4441 if (time >= msecs_to_jiffies(30 * 1000)) {
2e0fef85 4442 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011
JS
4443 "0461 Scanning longer than 30 "
4444 "seconds. Continuing initialization\n");
858c9f6c 4445 stat = 1;
47a8617c 4446 goto finished;
2e0fef85 4447 }
256ec0d0
JS
4448 if (time >= msecs_to_jiffies(15 * 1000) &&
4449 phba->link_state <= LPFC_LINK_DOWN) {
2e0fef85 4450 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011
JS
4451 "0465 Link down longer than 15 "
4452 "seconds. Continuing initialization\n");
858c9f6c 4453 stat = 1;
47a8617c 4454 goto finished;
2e0fef85 4455 }
47a8617c 4456
2e0fef85 4457 if (vport->port_state != LPFC_VPORT_READY)
858c9f6c 4458 goto finished;
2e0fef85 4459 if (vport->num_disc_nodes || vport->fc_prli_sent)
858c9f6c 4460 goto finished;
256ec0d0 4461 if (vport->fc_map_cnt == 0 && time < msecs_to_jiffies(2 * 1000))
858c9f6c 4462 goto finished;
2e0fef85 4463 if ((phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) != 0)
858c9f6c
JS
4464 goto finished;
4465
4466 stat = 1;
47a8617c
JS
4467
4468finished:
858c9f6c
JS
4469 spin_unlock_irq(shost->host_lock);
4470 return stat;
92d7f7b0 4471}
47a8617c 4472
3999df75 4473static void lpfc_host_supported_speeds_set(struct Scsi_Host *shost)
cd71348a
JS
4474{
4475 struct lpfc_vport *vport = (struct lpfc_vport *)shost->hostdata;
4476 struct lpfc_hba *phba = vport->phba;
4477
4478 fc_host_supported_speeds(shost) = 0;
1dc5ec24
JS
4479 if (phba->lmt & LMT_128Gb)
4480 fc_host_supported_speeds(shost) |= FC_PORTSPEED_128GBIT;
cd71348a
JS
4481 if (phba->lmt & LMT_64Gb)
4482 fc_host_supported_speeds(shost) |= FC_PORTSPEED_64GBIT;
4483 if (phba->lmt & LMT_32Gb)
4484 fc_host_supported_speeds(shost) |= FC_PORTSPEED_32GBIT;
4485 if (phba->lmt & LMT_16Gb)
4486 fc_host_supported_speeds(shost) |= FC_PORTSPEED_16GBIT;
4487 if (phba->lmt & LMT_10Gb)
4488 fc_host_supported_speeds(shost) |= FC_PORTSPEED_10GBIT;
4489 if (phba->lmt & LMT_8Gb)
4490 fc_host_supported_speeds(shost) |= FC_PORTSPEED_8GBIT;
4491 if (phba->lmt & LMT_4Gb)
4492 fc_host_supported_speeds(shost) |= FC_PORTSPEED_4GBIT;
4493 if (phba->lmt & LMT_2Gb)
4494 fc_host_supported_speeds(shost) |= FC_PORTSPEED_2GBIT;
4495 if (phba->lmt & LMT_1Gb)
4496 fc_host_supported_speeds(shost) |= FC_PORTSPEED_1GBIT;
4497}
4498
e59058c4 4499/**
3621a710 4500 * lpfc_host_attrib_init - Initialize SCSI host attributes on a FC port
e59058c4
JS
4501 * @shost: pointer to SCSI host data structure.
4502 *
4503 * This routine initializes a given SCSI host attributes on a FC port. The
4504 * SCSI host can be either on top of a physical port or a virtual port.
4505 **/
92d7f7b0
JS
4506void lpfc_host_attrib_init(struct Scsi_Host *shost)
4507{
4508 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4509 struct lpfc_hba *phba = vport->phba;
47a8617c 4510 /*
2e0fef85 4511 * Set fixed host attributes. Must done after lpfc_sli_hba_setup().
47a8617c
JS
4512 */
4513
2e0fef85
JS
4514 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
4515 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
47a8617c
JS
4516 fc_host_supported_classes(shost) = FC_COS_CLASS3;
4517
4518 memset(fc_host_supported_fc4s(shost), 0,
2e0fef85 4519 sizeof(fc_host_supported_fc4s(shost)));
47a8617c
JS
4520 fc_host_supported_fc4s(shost)[2] = 1;
4521 fc_host_supported_fc4s(shost)[7] = 1;
4522
92d7f7b0
JS
4523 lpfc_vport_symbolic_node_name(vport, fc_host_symbolic_name(shost),
4524 sizeof fc_host_symbolic_name(shost));
47a8617c 4525
cd71348a 4526 lpfc_host_supported_speeds_set(shost);
47a8617c
JS
4527
4528 fc_host_maxframe_size(shost) =
2e0fef85
JS
4529 (((uint32_t) vport->fc_sparam.cmn.bbRcvSizeMsb & 0x0F) << 8) |
4530 (uint32_t) vport->fc_sparam.cmn.bbRcvSizeLsb;
47a8617c 4531
0af5d708
MC
4532 fc_host_dev_loss_tmo(shost) = vport->cfg_devloss_tmo;
4533
47a8617c
JS
4534 /* This value is also unchanging */
4535 memset(fc_host_active_fc4s(shost), 0,
2e0fef85 4536 sizeof(fc_host_active_fc4s(shost)));
47a8617c
JS
4537 fc_host_active_fc4s(shost)[2] = 1;
4538 fc_host_active_fc4s(shost)[7] = 1;
4539
92d7f7b0 4540 fc_host_max_npiv_vports(shost) = phba->max_vpi;
47a8617c 4541 spin_lock_irq(shost->host_lock);
51ef4c26 4542 vport->load_flag &= ~FC_LOADING;
47a8617c 4543 spin_unlock_irq(shost->host_lock);
47a8617c 4544}
dea3101e 4545
e59058c4 4546/**
da0436e9 4547 * lpfc_stop_port_s3 - Stop SLI3 device port
e59058c4
JS
4548 * @phba: pointer to lpfc hba data structure.
4549 *
da0436e9
JS
4550 * This routine is invoked to stop an SLI3 device port, it stops the device
4551 * from generating interrupts and stops the device driver's timers for the
4552 * device.
e59058c4 4553 **/
da0436e9
JS
4554static void
4555lpfc_stop_port_s3(struct lpfc_hba *phba)
db2378e0 4556{
da0436e9
JS
4557 /* Clear all interrupt enable conditions */
4558 writel(0, phba->HCregaddr);
4559 readl(phba->HCregaddr); /* flush */
4560 /* Clear all pending interrupts */
4561 writel(0xffffffff, phba->HAregaddr);
4562 readl(phba->HAregaddr); /* flush */
db2378e0 4563
da0436e9
JS
4564 /* Reset some HBA SLI setup states */
4565 lpfc_stop_hba_timers(phba);
4566 phba->pport->work_port_events = 0;
4567}
db2378e0 4568
da0436e9
JS
4569/**
4570 * lpfc_stop_port_s4 - Stop SLI4 device port
4571 * @phba: pointer to lpfc hba data structure.
4572 *
4573 * This routine is invoked to stop an SLI4 device port, it stops the device
4574 * from generating interrupts and stops the device driver's timers for the
4575 * device.
4576 **/
4577static void
4578lpfc_stop_port_s4(struct lpfc_hba *phba)
4579{
4580 /* Reset some HBA SLI4 setup states */
4581 lpfc_stop_hba_timers(phba);
cdb42bec
JS
4582 if (phba->pport)
4583 phba->pport->work_port_events = 0;
da0436e9 4584 phba->sli4_hba.intr_enable = 0;
da0436e9 4585}
9399627f 4586
da0436e9
JS
4587/**
4588 * lpfc_stop_port - Wrapper function for stopping hba port
4589 * @phba: Pointer to HBA context object.
4590 *
4591 * This routine wraps the actual SLI3 or SLI4 hba stop port routine from
4592 * the API jump table function pointer from the lpfc_hba struct.
4593 **/
4594void
4595lpfc_stop_port(struct lpfc_hba *phba)
4596{
4597 phba->lpfc_stop_port(phba);
f485c18d
DK
4598
4599 if (phba->wq)
4600 flush_workqueue(phba->wq);
da0436e9 4601}
db2378e0 4602
ecfd03c6
JS
4603/**
4604 * lpfc_fcf_redisc_wait_start_timer - Start fcf rediscover wait timer
4605 * @phba: Pointer to hba for which this call is being executed.
4606 *
4607 * This routine starts the timer waiting for the FCF rediscovery to complete.
4608 **/
4609void
4610lpfc_fcf_redisc_wait_start_timer(struct lpfc_hba *phba)
4611{
4612 unsigned long fcf_redisc_wait_tmo =
4613 (jiffies + msecs_to_jiffies(LPFC_FCF_REDISCOVER_WAIT_TMO));
4614 /* Start fcf rediscovery wait period timer */
4615 mod_timer(&phba->fcf.redisc_wait, fcf_redisc_wait_tmo);
4616 spin_lock_irq(&phba->hbalock);
4617 /* Allow action to new fcf asynchronous event */
4618 phba->fcf.fcf_flag &= ~(FCF_AVAILABLE | FCF_SCAN_DONE);
4619 /* Mark the FCF rediscovery pending state */
4620 phba->fcf.fcf_flag |= FCF_REDISC_PEND;
4621 spin_unlock_irq(&phba->hbalock);
4622}
4623
4624/**
4625 * lpfc_sli4_fcf_redisc_wait_tmo - FCF table rediscover wait timeout
4626 * @ptr: Map to lpfc_hba data structure pointer.
4627 *
4628 * This routine is invoked when waiting for FCF table rediscover has been
4629 * timed out. If new FCF record(s) has (have) been discovered during the
4630 * wait period, a new FCF event shall be added to the FCOE async event
4631 * list, and then worker thread shall be waked up for processing from the
4632 * worker thread context.
4633 **/
e399b228 4634static void
f22eb4d3 4635lpfc_sli4_fcf_redisc_wait_tmo(struct timer_list *t)
ecfd03c6 4636{
f22eb4d3 4637 struct lpfc_hba *phba = from_timer(phba, t, fcf.redisc_wait);
ecfd03c6
JS
4638
4639 /* Don't send FCF rediscovery event if timer cancelled */
4640 spin_lock_irq(&phba->hbalock);
4641 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
4642 spin_unlock_irq(&phba->hbalock);
4643 return;
4644 }
4645 /* Clear FCF rediscovery timer pending flag */
4646 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
4647 /* FCF rediscovery event to worker thread */
4648 phba->fcf.fcf_flag |= FCF_REDISC_EVT;
4649 spin_unlock_irq(&phba->hbalock);
0c9ab6f5 4650 lpfc_printf_log(phba, KERN_INFO, LOG_FIP,
a93ff37a 4651 "2776 FCF rediscover quiescent timer expired\n");
ecfd03c6
JS
4652 /* wake up worker thread */
4653 lpfc_worker_wake_up(phba);
4654}
4655
e59058c4 4656/**
da0436e9 4657 * lpfc_sli4_parse_latt_fault - Parse sli4 link-attention link fault code
e59058c4 4658 * @phba: pointer to lpfc hba data structure.
da0436e9 4659 * @acqe_link: pointer to the async link completion queue entry.
e59058c4 4660 *
23288b78 4661 * This routine is to parse the SLI4 link-attention link fault code.
e59058c4 4662 **/
23288b78 4663static void
da0436e9
JS
4664lpfc_sli4_parse_latt_fault(struct lpfc_hba *phba,
4665 struct lpfc_acqe_link *acqe_link)
db2378e0 4666{
da0436e9
JS
4667 switch (bf_get(lpfc_acqe_link_fault, acqe_link)) {
4668 case LPFC_ASYNC_LINK_FAULT_NONE:
4669 case LPFC_ASYNC_LINK_FAULT_LOCAL:
4670 case LPFC_ASYNC_LINK_FAULT_REMOTE:
23288b78 4671 case LPFC_ASYNC_LINK_FAULT_LR_LRR:
da0436e9
JS
4672 break;
4673 default:
4674 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
23288b78 4675 "0398 Unknown link fault code: x%x\n",
da0436e9 4676 bf_get(lpfc_acqe_link_fault, acqe_link));
da0436e9
JS
4677 break;
4678 }
db2378e0
JS
4679}
4680
5b75da2f 4681/**
da0436e9 4682 * lpfc_sli4_parse_latt_type - Parse sli4 link attention type
5b75da2f 4683 * @phba: pointer to lpfc hba data structure.
da0436e9 4684 * @acqe_link: pointer to the async link completion queue entry.
5b75da2f 4685 *
da0436e9
JS
4686 * This routine is to parse the SLI4 link attention type and translate it
4687 * into the base driver's link attention type coding.
5b75da2f 4688 *
da0436e9
JS
4689 * Return: Link attention type in terms of base driver's coding.
4690 **/
4691static uint8_t
4692lpfc_sli4_parse_latt_type(struct lpfc_hba *phba,
4693 struct lpfc_acqe_link *acqe_link)
5b75da2f 4694{
da0436e9 4695 uint8_t att_type;
5b75da2f 4696
da0436e9
JS
4697 switch (bf_get(lpfc_acqe_link_status, acqe_link)) {
4698 case LPFC_ASYNC_LINK_STATUS_DOWN:
4699 case LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN:
76a95d75 4700 att_type = LPFC_ATT_LINK_DOWN;
da0436e9
JS
4701 break;
4702 case LPFC_ASYNC_LINK_STATUS_UP:
4703 /* Ignore physical link up events - wait for logical link up */
76a95d75 4704 att_type = LPFC_ATT_RESERVED;
da0436e9
JS
4705 break;
4706 case LPFC_ASYNC_LINK_STATUS_LOGICAL_UP:
76a95d75 4707 att_type = LPFC_ATT_LINK_UP;
da0436e9
JS
4708 break;
4709 default:
4710 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
4711 "0399 Invalid link attention type: x%x\n",
4712 bf_get(lpfc_acqe_link_status, acqe_link));
76a95d75 4713 att_type = LPFC_ATT_RESERVED;
da0436e9 4714 break;
5b75da2f 4715 }
da0436e9 4716 return att_type;
5b75da2f
JS
4717}
4718
8b68cd52
JS
4719/**
4720 * lpfc_sli_port_speed_get - Get sli3 link speed code to link speed
4721 * @phba: pointer to lpfc hba data structure.
4722 *
4723 * This routine is to get an SLI3 FC port's link speed in Mbps.
4724 *
4725 * Return: link speed in terms of Mbps.
4726 **/
4727uint32_t
4728lpfc_sli_port_speed_get(struct lpfc_hba *phba)
4729{
4730 uint32_t link_speed;
4731
4732 if (!lpfc_is_link_up(phba))
4733 return 0;
4734
a085e87c
JS
4735 if (phba->sli_rev <= LPFC_SLI_REV3) {
4736 switch (phba->fc_linkspeed) {
4737 case LPFC_LINK_SPEED_1GHZ:
4738 link_speed = 1000;
4739 break;
4740 case LPFC_LINK_SPEED_2GHZ:
4741 link_speed = 2000;
4742 break;
4743 case LPFC_LINK_SPEED_4GHZ:
4744 link_speed = 4000;
4745 break;
4746 case LPFC_LINK_SPEED_8GHZ:
4747 link_speed = 8000;
4748 break;
4749 case LPFC_LINK_SPEED_10GHZ:
4750 link_speed = 10000;
4751 break;
4752 case LPFC_LINK_SPEED_16GHZ:
4753 link_speed = 16000;
4754 break;
4755 default:
4756 link_speed = 0;
4757 }
4758 } else {
4759 if (phba->sli4_hba.link_state.logical_speed)
4760 link_speed =
4761 phba->sli4_hba.link_state.logical_speed;
4762 else
4763 link_speed = phba->sli4_hba.link_state.speed;
8b68cd52
JS
4764 }
4765 return link_speed;
4766}
4767
4768/**
4769 * lpfc_sli4_port_speed_parse - Parse async evt link speed code to link speed
4770 * @phba: pointer to lpfc hba data structure.
4771 * @evt_code: asynchronous event code.
4772 * @speed_code: asynchronous event link speed code.
4773 *
4774 * This routine is to parse the giving SLI4 async event link speed code into
4775 * value of Mbps for the link speed.
4776 *
4777 * Return: link speed in terms of Mbps.
4778 **/
4779static uint32_t
4780lpfc_sli4_port_speed_parse(struct lpfc_hba *phba, uint32_t evt_code,
4781 uint8_t speed_code)
4782{
4783 uint32_t port_speed;
4784
4785 switch (evt_code) {
4786 case LPFC_TRAILER_CODE_LINK:
4787 switch (speed_code) {
26d830ec 4788 case LPFC_ASYNC_LINK_SPEED_ZERO:
8b68cd52
JS
4789 port_speed = 0;
4790 break;
26d830ec 4791 case LPFC_ASYNC_LINK_SPEED_10MBPS:
8b68cd52
JS
4792 port_speed = 10;
4793 break;
26d830ec 4794 case LPFC_ASYNC_LINK_SPEED_100MBPS:
8b68cd52
JS
4795 port_speed = 100;
4796 break;
26d830ec 4797 case LPFC_ASYNC_LINK_SPEED_1GBPS:
8b68cd52
JS
4798 port_speed = 1000;
4799 break;
26d830ec 4800 case LPFC_ASYNC_LINK_SPEED_10GBPS:
8b68cd52
JS
4801 port_speed = 10000;
4802 break;
26d830ec
JS
4803 case LPFC_ASYNC_LINK_SPEED_20GBPS:
4804 port_speed = 20000;
4805 break;
4806 case LPFC_ASYNC_LINK_SPEED_25GBPS:
4807 port_speed = 25000;
4808 break;
4809 case LPFC_ASYNC_LINK_SPEED_40GBPS:
4810 port_speed = 40000;
4811 break;
8b68cd52
JS
4812 default:
4813 port_speed = 0;
4814 }
4815 break;
4816 case LPFC_TRAILER_CODE_FC:
4817 switch (speed_code) {
26d830ec 4818 case LPFC_FC_LA_SPEED_UNKNOWN:
8b68cd52
JS
4819 port_speed = 0;
4820 break;
26d830ec 4821 case LPFC_FC_LA_SPEED_1G:
8b68cd52
JS
4822 port_speed = 1000;
4823 break;
26d830ec 4824 case LPFC_FC_LA_SPEED_2G:
8b68cd52
JS
4825 port_speed = 2000;
4826 break;
26d830ec 4827 case LPFC_FC_LA_SPEED_4G:
8b68cd52
JS
4828 port_speed = 4000;
4829 break;
26d830ec 4830 case LPFC_FC_LA_SPEED_8G:
8b68cd52
JS
4831 port_speed = 8000;
4832 break;
26d830ec 4833 case LPFC_FC_LA_SPEED_10G:
8b68cd52
JS
4834 port_speed = 10000;
4835 break;
26d830ec 4836 case LPFC_FC_LA_SPEED_16G:
8b68cd52
JS
4837 port_speed = 16000;
4838 break;
d38dd52c
JS
4839 case LPFC_FC_LA_SPEED_32G:
4840 port_speed = 32000;
4841 break;
fbd8a6ba
JS
4842 case LPFC_FC_LA_SPEED_64G:
4843 port_speed = 64000;
4844 break;
1dc5ec24
JS
4845 case LPFC_FC_LA_SPEED_128G:
4846 port_speed = 128000;
4847 break;
8b68cd52
JS
4848 default:
4849 port_speed = 0;
4850 }
4851 break;
4852 default:
4853 port_speed = 0;
4854 }
4855 return port_speed;
4856}
4857
da0436e9 4858/**
70f3c073 4859 * lpfc_sli4_async_link_evt - Process the asynchronous FCoE link event
da0436e9
JS
4860 * @phba: pointer to lpfc hba data structure.
4861 * @acqe_link: pointer to the async link completion queue entry.
4862 *
70f3c073 4863 * This routine is to handle the SLI4 asynchronous FCoE link event.
da0436e9
JS
4864 **/
4865static void
4866lpfc_sli4_async_link_evt(struct lpfc_hba *phba,
4867 struct lpfc_acqe_link *acqe_link)
4868{
4869 struct lpfc_dmabuf *mp;
4870 LPFC_MBOXQ_t *pmb;
4871 MAILBOX_t *mb;
76a95d75 4872 struct lpfc_mbx_read_top *la;
da0436e9 4873 uint8_t att_type;
76a95d75 4874 int rc;
da0436e9
JS
4875
4876 att_type = lpfc_sli4_parse_latt_type(phba, acqe_link);
76a95d75 4877 if (att_type != LPFC_ATT_LINK_DOWN && att_type != LPFC_ATT_LINK_UP)
da0436e9 4878 return;
32b9793f 4879 phba->fcoe_eventtag = acqe_link->event_tag;
da0436e9
JS
4880 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
4881 if (!pmb) {
4882 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4883 "0395 The mboxq allocation failed\n");
4884 return;
4885 }
4886 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
4887 if (!mp) {
4888 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4889 "0396 The lpfc_dmabuf allocation failed\n");
4890 goto out_free_pmb;
4891 }
4892 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
4893 if (!mp->virt) {
4894 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4895 "0397 The mbuf allocation failed\n");
4896 goto out_free_dmabuf;
4897 }
4898
4899 /* Cleanup any outstanding ELS commands */
4900 lpfc_els_flush_all_cmd(phba);
4901
4902 /* Block ELS IOCBs until we have done process link event */
895427bd 4903 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
da0436e9
JS
4904
4905 /* Update link event statistics */
4906 phba->sli.slistat.link_event++;
4907
76a95d75
JS
4908 /* Create lpfc_handle_latt mailbox command from link ACQE */
4909 lpfc_read_topology(phba, pmb, mp);
4910 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
da0436e9
JS
4911 pmb->vport = phba->pport;
4912
da0436e9
JS
4913 /* Keep the link status for extra SLI4 state machine reference */
4914 phba->sli4_hba.link_state.speed =
8b68cd52
JS
4915 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_LINK,
4916 bf_get(lpfc_acqe_link_speed, acqe_link));
da0436e9
JS
4917 phba->sli4_hba.link_state.duplex =
4918 bf_get(lpfc_acqe_link_duplex, acqe_link);
4919 phba->sli4_hba.link_state.status =
4920 bf_get(lpfc_acqe_link_status, acqe_link);
70f3c073
JS
4921 phba->sli4_hba.link_state.type =
4922 bf_get(lpfc_acqe_link_type, acqe_link);
4923 phba->sli4_hba.link_state.number =
4924 bf_get(lpfc_acqe_link_number, acqe_link);
da0436e9
JS
4925 phba->sli4_hba.link_state.fault =
4926 bf_get(lpfc_acqe_link_fault, acqe_link);
65467b6b 4927 phba->sli4_hba.link_state.logical_speed =
8b68cd52
JS
4928 bf_get(lpfc_acqe_logical_link_speed, acqe_link) * 10;
4929
70f3c073 4930 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
c31098ce
JS
4931 "2900 Async FC/FCoE Link event - Speed:%dGBit "
4932 "duplex:x%x LA Type:x%x Port Type:%d Port Number:%d "
4933 "Logical speed:%dMbps Fault:%d\n",
70f3c073
JS
4934 phba->sli4_hba.link_state.speed,
4935 phba->sli4_hba.link_state.topology,
4936 phba->sli4_hba.link_state.status,
4937 phba->sli4_hba.link_state.type,
4938 phba->sli4_hba.link_state.number,
8b68cd52 4939 phba->sli4_hba.link_state.logical_speed,
70f3c073 4940 phba->sli4_hba.link_state.fault);
76a95d75
JS
4941 /*
4942 * For FC Mode: issue the READ_TOPOLOGY mailbox command to fetch
4943 * topology info. Note: Optional for non FC-AL ports.
4944 */
4945 if (!(phba->hba_flag & HBA_FCOE_MODE)) {
4946 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
4947 if (rc == MBX_NOT_FINISHED)
4948 goto out_free_dmabuf;
4949 return;
4950 }
4951 /*
4952 * For FCoE Mode: fill in all the topology information we need and call
4953 * the READ_TOPOLOGY completion routine to continue without actually
4954 * sending the READ_TOPOLOGY mailbox command to the port.
4955 */
23288b78 4956 /* Initialize completion status */
76a95d75 4957 mb = &pmb->u.mb;
23288b78
JS
4958 mb->mbxStatus = MBX_SUCCESS;
4959
4960 /* Parse port fault information field */
4961 lpfc_sli4_parse_latt_fault(phba, acqe_link);
76a95d75
JS
4962
4963 /* Parse and translate link attention fields */
4964 la = (struct lpfc_mbx_read_top *) &pmb->u.mb.un.varReadTop;
4965 la->eventTag = acqe_link->event_tag;
4966 bf_set(lpfc_mbx_read_top_att_type, la, att_type);
4967 bf_set(lpfc_mbx_read_top_link_spd, la,
a085e87c 4968 (bf_get(lpfc_acqe_link_speed, acqe_link)));
76a95d75
JS
4969
4970 /* Fake the the following irrelvant fields */
4971 bf_set(lpfc_mbx_read_top_topology, la, LPFC_TOPOLOGY_PT_PT);
4972 bf_set(lpfc_mbx_read_top_alpa_granted, la, 0);
4973 bf_set(lpfc_mbx_read_top_il, la, 0);
4974 bf_set(lpfc_mbx_read_top_pb, la, 0);
4975 bf_set(lpfc_mbx_read_top_fa, la, 0);
4976 bf_set(lpfc_mbx_read_top_mm, la, 0);
da0436e9
JS
4977
4978 /* Invoke the lpfc_handle_latt mailbox command callback function */
76a95d75 4979 lpfc_mbx_cmpl_read_topology(phba, pmb);
da0436e9 4980
5b75da2f 4981 return;
da0436e9
JS
4982
4983out_free_dmabuf:
4984 kfree(mp);
4985out_free_pmb:
4986 mempool_free(pmb, phba->mbox_mem_pool);
4987}
4988
1dc5ec24
JS
4989/**
4990 * lpfc_async_link_speed_to_read_top - Parse async evt link speed code to read
4991 * topology.
4992 * @phba: pointer to lpfc hba data structure.
4993 * @evt_code: asynchronous event code.
4994 * @speed_code: asynchronous event link speed code.
4995 *
4996 * This routine is to parse the giving SLI4 async event link speed code into
4997 * value of Read topology link speed.
4998 *
4999 * Return: link speed in terms of Read topology.
5000 **/
5001static uint8_t
5002lpfc_async_link_speed_to_read_top(struct lpfc_hba *phba, uint8_t speed_code)
5003{
5004 uint8_t port_speed;
5005
5006 switch (speed_code) {
5007 case LPFC_FC_LA_SPEED_1G:
5008 port_speed = LPFC_LINK_SPEED_1GHZ;
5009 break;
5010 case LPFC_FC_LA_SPEED_2G:
5011 port_speed = LPFC_LINK_SPEED_2GHZ;
5012 break;
5013 case LPFC_FC_LA_SPEED_4G:
5014 port_speed = LPFC_LINK_SPEED_4GHZ;
5015 break;
5016 case LPFC_FC_LA_SPEED_8G:
5017 port_speed = LPFC_LINK_SPEED_8GHZ;
5018 break;
5019 case LPFC_FC_LA_SPEED_16G:
5020 port_speed = LPFC_LINK_SPEED_16GHZ;
5021 break;
5022 case LPFC_FC_LA_SPEED_32G:
5023 port_speed = LPFC_LINK_SPEED_32GHZ;
5024 break;
5025 case LPFC_FC_LA_SPEED_64G:
5026 port_speed = LPFC_LINK_SPEED_64GHZ;
5027 break;
5028 case LPFC_FC_LA_SPEED_128G:
5029 port_speed = LPFC_LINK_SPEED_128GHZ;
5030 break;
5031 case LPFC_FC_LA_SPEED_256G:
5032 port_speed = LPFC_LINK_SPEED_256GHZ;
5033 break;
5034 default:
5035 port_speed = 0;
5036 break;
5037 }
5038
5039 return port_speed;
5040}
5041
5042#define trunk_link_status(__idx)\
5043 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
5044 ((phba->trunk_link.link##__idx.state == LPFC_LINK_UP) ?\
5045 "Link up" : "Link down") : "NA"
5046/* Did port __idx reported an error */
5047#define trunk_port_fault(__idx)\
5048 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
5049 (port_fault & (1 << __idx) ? "YES" : "NO") : "NA"
5050
5051static void
5052lpfc_update_trunk_link_status(struct lpfc_hba *phba,
5053 struct lpfc_acqe_fc_la *acqe_fc)
5054{
5055 uint8_t port_fault = bf_get(lpfc_acqe_fc_la_trunk_linkmask, acqe_fc);
5056 uint8_t err = bf_get(lpfc_acqe_fc_la_trunk_fault, acqe_fc);
5057
5058 phba->sli4_hba.link_state.speed =
5059 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
5060 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5061
5062 phba->sli4_hba.link_state.logical_speed =
b8e6f136 5063 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
1dc5ec24
JS
5064 /* We got FC link speed, convert to fc_linkspeed (READ_TOPOLOGY) */
5065 phba->fc_linkspeed =
5066 lpfc_async_link_speed_to_read_top(
5067 phba,
5068 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5069
5070 if (bf_get(lpfc_acqe_fc_la_trunk_config_port0, acqe_fc)) {
5071 phba->trunk_link.link0.state =
5072 bf_get(lpfc_acqe_fc_la_trunk_link_status_port0, acqe_fc)
5073 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5074 phba->trunk_link.link0.fault = port_fault & 0x1 ? err : 0;
1dc5ec24
JS
5075 }
5076 if (bf_get(lpfc_acqe_fc_la_trunk_config_port1, acqe_fc)) {
5077 phba->trunk_link.link1.state =
5078 bf_get(lpfc_acqe_fc_la_trunk_link_status_port1, acqe_fc)
5079 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5080 phba->trunk_link.link1.fault = port_fault & 0x2 ? err : 0;
1dc5ec24
JS
5081 }
5082 if (bf_get(lpfc_acqe_fc_la_trunk_config_port2, acqe_fc)) {
5083 phba->trunk_link.link2.state =
5084 bf_get(lpfc_acqe_fc_la_trunk_link_status_port2, acqe_fc)
5085 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5086 phba->trunk_link.link2.fault = port_fault & 0x4 ? err : 0;
1dc5ec24
JS
5087 }
5088 if (bf_get(lpfc_acqe_fc_la_trunk_config_port3, acqe_fc)) {
5089 phba->trunk_link.link3.state =
5090 bf_get(lpfc_acqe_fc_la_trunk_link_status_port3, acqe_fc)
5091 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5092 phba->trunk_link.link3.fault = port_fault & 0x8 ? err : 0;
1dc5ec24
JS
5093 }
5094
5095 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5096 "2910 Async FC Trunking Event - Speed:%d\n"
5097 "\tLogical speed:%d "
5098 "port0: %s port1: %s port2: %s port3: %s\n",
5099 phba->sli4_hba.link_state.speed,
5100 phba->sli4_hba.link_state.logical_speed,
5101 trunk_link_status(0), trunk_link_status(1),
5102 trunk_link_status(2), trunk_link_status(3));
5103
5104 if (port_fault)
5105 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5106 "3202 trunk error:0x%x (%s) seen on port0:%s "
5107 /*
5108 * SLI-4: We have only 0xA error codes
5109 * defined as of now. print an appropriate
5110 * message in case driver needs to be updated.
5111 */
5112 "port1:%s port2:%s port3:%s\n", err, err > 0xA ?
5113 "UNDEFINED. update driver." : trunk_errmsg[err],
5114 trunk_port_fault(0), trunk_port_fault(1),
5115 trunk_port_fault(2), trunk_port_fault(3));
5116}
5117
5118
70f3c073
JS
5119/**
5120 * lpfc_sli4_async_fc_evt - Process the asynchronous FC link event
5121 * @phba: pointer to lpfc hba data structure.
5122 * @acqe_fc: pointer to the async fc completion queue entry.
5123 *
5124 * This routine is to handle the SLI4 asynchronous FC event. It will simply log
5125 * that the event was received and then issue a read_topology mailbox command so
5126 * that the rest of the driver will treat it the same as SLI3.
5127 **/
5128static void
5129lpfc_sli4_async_fc_evt(struct lpfc_hba *phba, struct lpfc_acqe_fc_la *acqe_fc)
5130{
5131 struct lpfc_dmabuf *mp;
5132 LPFC_MBOXQ_t *pmb;
7bdedb34
JS
5133 MAILBOX_t *mb;
5134 struct lpfc_mbx_read_top *la;
70f3c073
JS
5135 int rc;
5136
5137 if (bf_get(lpfc_trailer_type, acqe_fc) !=
5138 LPFC_FC_LA_EVENT_TYPE_FC_LINK) {
5139 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5140 "2895 Non FC link Event detected.(%d)\n",
5141 bf_get(lpfc_trailer_type, acqe_fc));
5142 return;
5143 }
1dc5ec24
JS
5144
5145 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
5146 LPFC_FC_LA_TYPE_TRUNKING_EVENT) {
5147 lpfc_update_trunk_link_status(phba, acqe_fc);
5148 return;
5149 }
5150
70f3c073
JS
5151 /* Keep the link status for extra SLI4 state machine reference */
5152 phba->sli4_hba.link_state.speed =
8b68cd52
JS
5153 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
5154 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
70f3c073
JS
5155 phba->sli4_hba.link_state.duplex = LPFC_ASYNC_LINK_DUPLEX_FULL;
5156 phba->sli4_hba.link_state.topology =
5157 bf_get(lpfc_acqe_fc_la_topology, acqe_fc);
5158 phba->sli4_hba.link_state.status =
5159 bf_get(lpfc_acqe_fc_la_att_type, acqe_fc);
5160 phba->sli4_hba.link_state.type =
5161 bf_get(lpfc_acqe_fc_la_port_type, acqe_fc);
5162 phba->sli4_hba.link_state.number =
5163 bf_get(lpfc_acqe_fc_la_port_number, acqe_fc);
5164 phba->sli4_hba.link_state.fault =
5165 bf_get(lpfc_acqe_link_fault, acqe_fc);
b8e6f136
JS
5166
5167 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
5168 LPFC_FC_LA_TYPE_LINK_DOWN)
5169 phba->sli4_hba.link_state.logical_speed = 0;
5170 else if (!phba->sli4_hba.conf_trunk)
5171 phba->sli4_hba.link_state.logical_speed =
8b68cd52 5172 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
b8e6f136 5173
70f3c073
JS
5174 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5175 "2896 Async FC event - Speed:%dGBaud Topology:x%x "
5176 "LA Type:x%x Port Type:%d Port Number:%d Logical speed:"
5177 "%dMbps Fault:%d\n",
5178 phba->sli4_hba.link_state.speed,
5179 phba->sli4_hba.link_state.topology,
5180 phba->sli4_hba.link_state.status,
5181 phba->sli4_hba.link_state.type,
5182 phba->sli4_hba.link_state.number,
8b68cd52 5183 phba->sli4_hba.link_state.logical_speed,
70f3c073
JS
5184 phba->sli4_hba.link_state.fault);
5185 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
5186 if (!pmb) {
5187 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5188 "2897 The mboxq allocation failed\n");
5189 return;
5190 }
5191 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
5192 if (!mp) {
5193 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5194 "2898 The lpfc_dmabuf allocation failed\n");
5195 goto out_free_pmb;
5196 }
5197 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
5198 if (!mp->virt) {
5199 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5200 "2899 The mbuf allocation failed\n");
5201 goto out_free_dmabuf;
5202 }
5203
5204 /* Cleanup any outstanding ELS commands */
5205 lpfc_els_flush_all_cmd(phba);
5206
5207 /* Block ELS IOCBs until we have done process link event */
895427bd 5208 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
70f3c073
JS
5209
5210 /* Update link event statistics */
5211 phba->sli.slistat.link_event++;
5212
5213 /* Create lpfc_handle_latt mailbox command from link ACQE */
5214 lpfc_read_topology(phba, pmb, mp);
5215 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
5216 pmb->vport = phba->pport;
5217
7bdedb34 5218 if (phba->sli4_hba.link_state.status != LPFC_FC_LA_TYPE_LINK_UP) {
ae9e28f3
JS
5219 phba->link_flag &= ~(LS_MDS_LINK_DOWN | LS_MDS_LOOPBACK);
5220
5221 switch (phba->sli4_hba.link_state.status) {
5222 case LPFC_FC_LA_TYPE_MDS_LINK_DOWN:
5223 phba->link_flag |= LS_MDS_LINK_DOWN;
5224 break;
5225 case LPFC_FC_LA_TYPE_MDS_LOOPBACK:
5226 phba->link_flag |= LS_MDS_LOOPBACK;
5227 break;
5228 default:
5229 break;
5230 }
5231
23288b78 5232 /* Initialize completion status */
7bdedb34 5233 mb = &pmb->u.mb;
23288b78
JS
5234 mb->mbxStatus = MBX_SUCCESS;
5235
5236 /* Parse port fault information field */
5237 lpfc_sli4_parse_latt_fault(phba, (void *)acqe_fc);
7bdedb34
JS
5238
5239 /* Parse and translate link attention fields */
5240 la = (struct lpfc_mbx_read_top *)&pmb->u.mb.un.varReadTop;
5241 la->eventTag = acqe_fc->event_tag;
7bdedb34 5242
aeb3c817
JS
5243 if (phba->sli4_hba.link_state.status ==
5244 LPFC_FC_LA_TYPE_UNEXP_WWPN) {
5245 bf_set(lpfc_mbx_read_top_att_type, la,
5246 LPFC_FC_LA_TYPE_UNEXP_WWPN);
5247 } else {
5248 bf_set(lpfc_mbx_read_top_att_type, la,
5249 LPFC_FC_LA_TYPE_LINK_DOWN);
5250 }
7bdedb34
JS
5251 /* Invoke the mailbox command callback function */
5252 lpfc_mbx_cmpl_read_topology(phba, pmb);
5253
5254 return;
5255 }
5256
70f3c073
JS
5257 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
5258 if (rc == MBX_NOT_FINISHED)
5259 goto out_free_dmabuf;
5260 return;
5261
5262out_free_dmabuf:
5263 kfree(mp);
5264out_free_pmb:
5265 mempool_free(pmb, phba->mbox_mem_pool);
5266}
5267
5268/**
5269 * lpfc_sli4_async_sli_evt - Process the asynchronous SLI link event
5270 * @phba: pointer to lpfc hba data structure.
5271 * @acqe_fc: pointer to the async SLI completion queue entry.
5272 *
5273 * This routine is to handle the SLI4 asynchronous SLI events.
5274 **/
5275static void
5276lpfc_sli4_async_sli_evt(struct lpfc_hba *phba, struct lpfc_acqe_sli *acqe_sli)
5277{
4b8bae08 5278 char port_name;
8c1312e1 5279 char message[128];
4b8bae08 5280 uint8_t status;
946727dc 5281 uint8_t evt_type;
448193b5 5282 uint8_t operational = 0;
946727dc 5283 struct temp_event temp_event_data;
4b8bae08 5284 struct lpfc_acqe_misconfigured_event *misconfigured;
946727dc 5285 struct Scsi_Host *shost;
cd71348a
JS
5286 struct lpfc_vport **vports;
5287 int rc, i;
946727dc
JS
5288
5289 evt_type = bf_get(lpfc_trailer_type, acqe_sli);
4b8bae08 5290
448193b5
JS
5291 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5292 "2901 Async SLI event - Event Data1:x%08x Event Data2:"
5293 "x%08x SLI Event Type:%d\n",
5294 acqe_sli->event_data1, acqe_sli->event_data2,
5295 evt_type);
4b8bae08
JS
5296
5297 port_name = phba->Port[0];
5298 if (port_name == 0x00)
5299 port_name = '?'; /* get port name is empty */
5300
946727dc
JS
5301 switch (evt_type) {
5302 case LPFC_SLI_EVENT_TYPE_OVER_TEMP:
5303 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
5304 temp_event_data.event_code = LPFC_THRESHOLD_TEMP;
5305 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
5306
5307 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
5308 "3190 Over Temperature:%d Celsius- Port Name %c\n",
5309 acqe_sli->event_data1, port_name);
5310
310429ef 5311 phba->sfp_warning |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
946727dc
JS
5312 shost = lpfc_shost_from_vport(phba->pport);
5313 fc_host_post_vendor_event(shost, fc_get_event_number(),
5314 sizeof(temp_event_data),
5315 (char *)&temp_event_data,
5316 SCSI_NL_VID_TYPE_PCI
5317 | PCI_VENDOR_ID_EMULEX);
5318 break;
5319 case LPFC_SLI_EVENT_TYPE_NORM_TEMP:
5320 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
5321 temp_event_data.event_code = LPFC_NORMAL_TEMP;
5322 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
5323
5324 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5325 "3191 Normal Temperature:%d Celsius - Port Name %c\n",
5326 acqe_sli->event_data1, port_name);
5327
5328 shost = lpfc_shost_from_vport(phba->pport);
5329 fc_host_post_vendor_event(shost, fc_get_event_number(),
5330 sizeof(temp_event_data),
5331 (char *)&temp_event_data,
5332 SCSI_NL_VID_TYPE_PCI
5333 | PCI_VENDOR_ID_EMULEX);
5334 break;
5335 case LPFC_SLI_EVENT_TYPE_MISCONFIGURED:
5336 misconfigured = (struct lpfc_acqe_misconfigured_event *)
4b8bae08
JS
5337 &acqe_sli->event_data1;
5338
946727dc
JS
5339 /* fetch the status for this port */
5340 switch (phba->sli4_hba.lnk_info.lnk_no) {
5341 case LPFC_LINK_NUMBER_0:
448193b5
JS
5342 status = bf_get(lpfc_sli_misconfigured_port0_state,
5343 &misconfigured->theEvent);
5344 operational = bf_get(lpfc_sli_misconfigured_port0_op,
4b8bae08 5345 &misconfigured->theEvent);
946727dc
JS
5346 break;
5347 case LPFC_LINK_NUMBER_1:
448193b5
JS
5348 status = bf_get(lpfc_sli_misconfigured_port1_state,
5349 &misconfigured->theEvent);
5350 operational = bf_get(lpfc_sli_misconfigured_port1_op,
4b8bae08 5351 &misconfigured->theEvent);
946727dc
JS
5352 break;
5353 case LPFC_LINK_NUMBER_2:
448193b5
JS
5354 status = bf_get(lpfc_sli_misconfigured_port2_state,
5355 &misconfigured->theEvent);
5356 operational = bf_get(lpfc_sli_misconfigured_port2_op,
4b8bae08 5357 &misconfigured->theEvent);
946727dc
JS
5358 break;
5359 case LPFC_LINK_NUMBER_3:
448193b5
JS
5360 status = bf_get(lpfc_sli_misconfigured_port3_state,
5361 &misconfigured->theEvent);
5362 operational = bf_get(lpfc_sli_misconfigured_port3_op,
4b8bae08 5363 &misconfigured->theEvent);
946727dc
JS
5364 break;
5365 default:
448193b5
JS
5366 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5367 "3296 "
5368 "LPFC_SLI_EVENT_TYPE_MISCONFIGURED "
5369 "event: Invalid link %d",
5370 phba->sli4_hba.lnk_info.lnk_no);
5371 return;
946727dc 5372 }
4b8bae08 5373
448193b5
JS
5374 /* Skip if optic state unchanged */
5375 if (phba->sli4_hba.lnk_info.optic_state == status)
5376 return;
5377
946727dc
JS
5378 switch (status) {
5379 case LPFC_SLI_EVENT_STATUS_VALID:
448193b5
JS
5380 sprintf(message, "Physical Link is functional");
5381 break;
946727dc
JS
5382 case LPFC_SLI_EVENT_STATUS_NOT_PRESENT:
5383 sprintf(message, "Optics faulted/incorrectly "
5384 "installed/not installed - Reseat optics, "
5385 "if issue not resolved, replace.");
5386 break;
5387 case LPFC_SLI_EVENT_STATUS_WRONG_TYPE:
5388 sprintf(message,
5389 "Optics of two types installed - Remove one "
5390 "optic or install matching pair of optics.");
5391 break;
5392 case LPFC_SLI_EVENT_STATUS_UNSUPPORTED:
5393 sprintf(message, "Incompatible optics - Replace with "
292098be 5394 "compatible optics for card to function.");
946727dc 5395 break;
448193b5
JS
5396 case LPFC_SLI_EVENT_STATUS_UNQUALIFIED:
5397 sprintf(message, "Unqualified optics - Replace with "
5398 "Avago optics for Warranty and Technical "
5399 "Support - Link is%s operational",
2ea259ee 5400 (operational) ? " not" : "");
448193b5
JS
5401 break;
5402 case LPFC_SLI_EVENT_STATUS_UNCERTIFIED:
5403 sprintf(message, "Uncertified optics - Replace with "
5404 "Avago-certified optics to enable link "
5405 "operation - Link is%s operational",
2ea259ee 5406 (operational) ? " not" : "");
448193b5 5407 break;
946727dc
JS
5408 default:
5409 /* firmware is reporting a status we don't know about */
5410 sprintf(message, "Unknown event status x%02x", status);
5411 break;
5412 }
cd71348a
JS
5413
5414 /* Issue READ_CONFIG mbox command to refresh supported speeds */
5415 rc = lpfc_sli4_read_config(phba);
3952e91f 5416 if (rc) {
cd71348a
JS
5417 phba->lmt = 0;
5418 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5419 "3194 Unable to retrieve supported "
3952e91f 5420 "speeds, rc = 0x%x\n", rc);
cd71348a
JS
5421 }
5422 vports = lpfc_create_vport_work_array(phba);
5423 if (vports != NULL) {
5424 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5425 i++) {
5426 shost = lpfc_shost_from_vport(vports[i]);
5427 lpfc_host_supported_speeds_set(shost);
5428 }
5429 }
5430 lpfc_destroy_vport_work_array(phba, vports);
5431
448193b5 5432 phba->sli4_hba.lnk_info.optic_state = status;
946727dc 5433 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
448193b5 5434 "3176 Port Name %c %s\n", port_name, message);
946727dc
JS
5435 break;
5436 case LPFC_SLI_EVENT_TYPE_REMOTE_DPORT:
5437 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5438 "3192 Remote DPort Test Initiated - "
5439 "Event Data1:x%08x Event Data2: x%08x\n",
5440 acqe_sli->event_data1, acqe_sli->event_data2);
4b8bae08
JS
5441 break;
5442 default:
946727dc
JS
5443 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5444 "3193 Async SLI event - Event Data1:x%08x Event Data2:"
5445 "x%08x SLI Event Type:%d\n",
5446 acqe_sli->event_data1, acqe_sli->event_data2,
5447 evt_type);
4b8bae08
JS
5448 break;
5449 }
70f3c073
JS
5450}
5451
fc2b989b
JS
5452/**
5453 * lpfc_sli4_perform_vport_cvl - Perform clear virtual link on a vport
5454 * @vport: pointer to vport data structure.
5455 *
5456 * This routine is to perform Clear Virtual Link (CVL) on a vport in
5457 * response to a CVL event.
5458 *
5459 * Return the pointer to the ndlp with the vport if successful, otherwise
5460 * return NULL.
5461 **/
5462static struct lpfc_nodelist *
5463lpfc_sli4_perform_vport_cvl(struct lpfc_vport *vport)
5464{
5465 struct lpfc_nodelist *ndlp;
5466 struct Scsi_Host *shost;
5467 struct lpfc_hba *phba;
5468
5469 if (!vport)
5470 return NULL;
fc2b989b
JS
5471 phba = vport->phba;
5472 if (!phba)
5473 return NULL;
78730cfe
JS
5474 ndlp = lpfc_findnode_did(vport, Fabric_DID);
5475 if (!ndlp) {
5476 /* Cannot find existing Fabric ndlp, so allocate a new one */
9d3d340d 5477 ndlp = lpfc_nlp_init(vport, Fabric_DID);
78730cfe
JS
5478 if (!ndlp)
5479 return 0;
78730cfe
JS
5480 /* Set the node type */
5481 ndlp->nlp_type |= NLP_FABRIC;
5482 /* Put ndlp onto node list */
5483 lpfc_enqueue_node(vport, ndlp);
5484 } else if (!NLP_CHK_NODE_ACT(ndlp)) {
5485 /* re-setup ndlp without removing from node list */
5486 ndlp = lpfc_enable_node(vport, ndlp, NLP_STE_UNUSED_NODE);
5487 if (!ndlp)
5488 return 0;
5489 }
63e801ce
JS
5490 if ((phba->pport->port_state < LPFC_FLOGI) &&
5491 (phba->pport->port_state != LPFC_VPORT_FAILED))
fc2b989b
JS
5492 return NULL;
5493 /* If virtual link is not yet instantiated ignore CVL */
63e801ce
JS
5494 if ((vport != phba->pport) && (vport->port_state < LPFC_FDISC)
5495 && (vport->port_state != LPFC_VPORT_FAILED))
fc2b989b
JS
5496 return NULL;
5497 shost = lpfc_shost_from_vport(vport);
5498 if (!shost)
5499 return NULL;
5500 lpfc_linkdown_port(vport);
5501 lpfc_cleanup_pending_mbox(vport);
5502 spin_lock_irq(shost->host_lock);
5503 vport->fc_flag |= FC_VPORT_CVL_RCVD;
5504 spin_unlock_irq(shost->host_lock);
5505
5506 return ndlp;
5507}
5508
5509/**
5510 * lpfc_sli4_perform_all_vport_cvl - Perform clear virtual link on all vports
5511 * @vport: pointer to lpfc hba data structure.
5512 *
5513 * This routine is to perform Clear Virtual Link (CVL) on all vports in
5514 * response to a FCF dead event.
5515 **/
5516static void
5517lpfc_sli4_perform_all_vport_cvl(struct lpfc_hba *phba)
5518{
5519 struct lpfc_vport **vports;
5520 int i;
5521
5522 vports = lpfc_create_vport_work_array(phba);
5523 if (vports)
5524 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
5525 lpfc_sli4_perform_vport_cvl(vports[i]);
5526 lpfc_destroy_vport_work_array(phba, vports);
5527}
5528
da0436e9 5529/**
76a95d75 5530 * lpfc_sli4_async_fip_evt - Process the asynchronous FCoE FIP event
da0436e9
JS
5531 * @phba: pointer to lpfc hba data structure.
5532 * @acqe_link: pointer to the async fcoe completion queue entry.
5533 *
5534 * This routine is to handle the SLI4 asynchronous fcoe event.
5535 **/
5536static void
76a95d75 5537lpfc_sli4_async_fip_evt(struct lpfc_hba *phba,
70f3c073 5538 struct lpfc_acqe_fip *acqe_fip)
da0436e9 5539{
70f3c073 5540 uint8_t event_type = bf_get(lpfc_trailer_type, acqe_fip);
da0436e9 5541 int rc;
6669f9bb
JS
5542 struct lpfc_vport *vport;
5543 struct lpfc_nodelist *ndlp;
5544 struct Scsi_Host *shost;
695a814e
JS
5545 int active_vlink_present;
5546 struct lpfc_vport **vports;
5547 int i;
da0436e9 5548
70f3c073
JS
5549 phba->fc_eventTag = acqe_fip->event_tag;
5550 phba->fcoe_eventtag = acqe_fip->event_tag;
da0436e9 5551 switch (event_type) {
70f3c073
JS
5552 case LPFC_FIP_EVENT_TYPE_NEW_FCF:
5553 case LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD:
5554 if (event_type == LPFC_FIP_EVENT_TYPE_NEW_FCF)
999d813f
JS
5555 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
5556 LOG_DISCOVERY,
a93ff37a
JS
5557 "2546 New FCF event, evt_tag:x%x, "
5558 "index:x%x\n",
70f3c073
JS
5559 acqe_fip->event_tag,
5560 acqe_fip->index);
999d813f
JS
5561 else
5562 lpfc_printf_log(phba, KERN_WARNING, LOG_FIP |
5563 LOG_DISCOVERY,
a93ff37a
JS
5564 "2788 FCF param modified event, "
5565 "evt_tag:x%x, index:x%x\n",
70f3c073
JS
5566 acqe_fip->event_tag,
5567 acqe_fip->index);
38b92ef8 5568 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
0c9ab6f5
JS
5569 /*
5570 * During period of FCF discovery, read the FCF
5571 * table record indexed by the event to update
a93ff37a 5572 * FCF roundrobin failover eligible FCF bmask.
0c9ab6f5
JS
5573 */
5574 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5575 LOG_DISCOVERY,
a93ff37a
JS
5576 "2779 Read FCF (x%x) for updating "
5577 "roundrobin FCF failover bmask\n",
70f3c073
JS
5578 acqe_fip->index);
5579 rc = lpfc_sli4_read_fcf_rec(phba, acqe_fip->index);
0c9ab6f5 5580 }
38b92ef8
JS
5581
5582 /* If the FCF discovery is in progress, do nothing. */
3804dc84 5583 spin_lock_irq(&phba->hbalock);
a93ff37a 5584 if (phba->hba_flag & FCF_TS_INPROG) {
38b92ef8
JS
5585 spin_unlock_irq(&phba->hbalock);
5586 break;
5587 }
5588 /* If fast FCF failover rescan event is pending, do nothing */
036cad1f 5589 if (phba->fcf.fcf_flag & (FCF_REDISC_EVT | FCF_REDISC_PEND)) {
38b92ef8
JS
5590 spin_unlock_irq(&phba->hbalock);
5591 break;
5592 }
5593
c2b9712e
JS
5594 /* If the FCF has been in discovered state, do nothing. */
5595 if (phba->fcf.fcf_flag & FCF_SCAN_DONE) {
3804dc84
JS
5596 spin_unlock_irq(&phba->hbalock);
5597 break;
5598 }
5599 spin_unlock_irq(&phba->hbalock);
38b92ef8 5600
0c9ab6f5
JS
5601 /* Otherwise, scan the entire FCF table and re-discover SAN */
5602 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
a93ff37a
JS
5603 "2770 Start FCF table scan per async FCF "
5604 "event, evt_tag:x%x, index:x%x\n",
70f3c073 5605 acqe_fip->event_tag, acqe_fip->index);
0c9ab6f5
JS
5606 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba,
5607 LPFC_FCOE_FCF_GET_FIRST);
da0436e9 5608 if (rc)
0c9ab6f5
JS
5609 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
5610 "2547 Issue FCF scan read FCF mailbox "
a93ff37a 5611 "command failed (x%x)\n", rc);
da0436e9
JS
5612 break;
5613
70f3c073 5614 case LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL:
da0436e9 5615 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
e4e74273 5616 "2548 FCF Table full count 0x%x tag 0x%x\n",
70f3c073
JS
5617 bf_get(lpfc_acqe_fip_fcf_count, acqe_fip),
5618 acqe_fip->event_tag);
da0436e9
JS
5619 break;
5620
70f3c073 5621 case LPFC_FIP_EVENT_TYPE_FCF_DEAD:
80c17849 5622 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
0c9ab6f5 5623 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
a93ff37a 5624 "2549 FCF (x%x) disconnected from network, "
70f3c073 5625 "tag:x%x\n", acqe_fip->index, acqe_fip->event_tag);
38b92ef8
JS
5626 /*
5627 * If we are in the middle of FCF failover process, clear
5628 * the corresponding FCF bit in the roundrobin bitmap.
da0436e9 5629 */
fc2b989b 5630 spin_lock_irq(&phba->hbalock);
a1cadfef
JS
5631 if ((phba->fcf.fcf_flag & FCF_DISCOVERY) &&
5632 (phba->fcf.current_rec.fcf_indx != acqe_fip->index)) {
fc2b989b 5633 spin_unlock_irq(&phba->hbalock);
0c9ab6f5 5634 /* Update FLOGI FCF failover eligible FCF bmask */
70f3c073 5635 lpfc_sli4_fcf_rr_index_clear(phba, acqe_fip->index);
fc2b989b
JS
5636 break;
5637 }
38b92ef8
JS
5638 spin_unlock_irq(&phba->hbalock);
5639
5640 /* If the event is not for currently used fcf do nothing */
70f3c073 5641 if (phba->fcf.current_rec.fcf_indx != acqe_fip->index)
38b92ef8
JS
5642 break;
5643
5644 /*
5645 * Otherwise, request the port to rediscover the entire FCF
5646 * table for a fast recovery from case that the current FCF
5647 * is no longer valid as we are not in the middle of FCF
5648 * failover process already.
5649 */
c2b9712e
JS
5650 spin_lock_irq(&phba->hbalock);
5651 /* Mark the fast failover process in progress */
5652 phba->fcf.fcf_flag |= FCF_DEAD_DISC;
5653 spin_unlock_irq(&phba->hbalock);
5654
5655 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
5656 "2771 Start FCF fast failover process due to "
5657 "FCF DEAD event: evt_tag:x%x, fcf_index:x%x "
5658 "\n", acqe_fip->event_tag, acqe_fip->index);
5659 rc = lpfc_sli4_redisc_fcf_table(phba);
5660 if (rc) {
5661 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
5662 LOG_DISCOVERY,
7afc0ce9 5663 "2772 Issue FCF rediscover mailbox "
c2b9712e
JS
5664 "command failed, fail through to FCF "
5665 "dead event\n");
5666 spin_lock_irq(&phba->hbalock);
5667 phba->fcf.fcf_flag &= ~FCF_DEAD_DISC;
5668 spin_unlock_irq(&phba->hbalock);
5669 /*
5670 * Last resort will fail over by treating this
5671 * as a link down to FCF registration.
5672 */
5673 lpfc_sli4_fcf_dead_failthrough(phba);
5674 } else {
5675 /* Reset FCF roundrobin bmask for new discovery */
5676 lpfc_sli4_clear_fcf_rr_bmask(phba);
5677 /*
5678 * Handling fast FCF failover to a DEAD FCF event is
5679 * considered equalivant to receiving CVL to all vports.
5680 */
5681 lpfc_sli4_perform_all_vport_cvl(phba);
5682 }
da0436e9 5683 break;
70f3c073 5684 case LPFC_FIP_EVENT_TYPE_CVL:
80c17849 5685 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
0c9ab6f5 5686 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
6669f9bb 5687 "2718 Clear Virtual Link Received for VPI 0x%x"
70f3c073 5688 " tag 0x%x\n", acqe_fip->index, acqe_fip->event_tag);
6d368e53 5689
6669f9bb 5690 vport = lpfc_find_vport_by_vpid(phba,
5248a749 5691 acqe_fip->index);
fc2b989b 5692 ndlp = lpfc_sli4_perform_vport_cvl(vport);
6669f9bb
JS
5693 if (!ndlp)
5694 break;
695a814e
JS
5695 active_vlink_present = 0;
5696
5697 vports = lpfc_create_vport_work_array(phba);
5698 if (vports) {
5699 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5700 i++) {
5701 if ((!(vports[i]->fc_flag &
5702 FC_VPORT_CVL_RCVD)) &&
5703 (vports[i]->port_state > LPFC_FDISC)) {
5704 active_vlink_present = 1;
5705 break;
5706 }
5707 }
5708 lpfc_destroy_vport_work_array(phba, vports);
5709 }
5710
cc82355a
JS
5711 /*
5712 * Don't re-instantiate if vport is marked for deletion.
5713 * If we are here first then vport_delete is going to wait
5714 * for discovery to complete.
5715 */
5716 if (!(vport->load_flag & FC_UNLOADING) &&
5717 active_vlink_present) {
695a814e
JS
5718 /*
5719 * If there are other active VLinks present,
5720 * re-instantiate the Vlink using FDISC.
5721 */
256ec0d0
JS
5722 mod_timer(&ndlp->nlp_delayfunc,
5723 jiffies + msecs_to_jiffies(1000));
fc2b989b 5724 shost = lpfc_shost_from_vport(vport);
6669f9bb
JS
5725 spin_lock_irq(shost->host_lock);
5726 ndlp->nlp_flag |= NLP_DELAY_TMO;
5727 spin_unlock_irq(shost->host_lock);
695a814e
JS
5728 ndlp->nlp_last_elscmd = ELS_CMD_FDISC;
5729 vport->port_state = LPFC_FDISC;
5730 } else {
ecfd03c6
JS
5731 /*
5732 * Otherwise, we request port to rediscover
5733 * the entire FCF table for a fast recovery
5734 * from possible case that the current FCF
0c9ab6f5
JS
5735 * is no longer valid if we are not already
5736 * in the FCF failover process.
ecfd03c6 5737 */
fc2b989b 5738 spin_lock_irq(&phba->hbalock);
0c9ab6f5 5739 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
fc2b989b
JS
5740 spin_unlock_irq(&phba->hbalock);
5741 break;
5742 }
5743 /* Mark the fast failover process in progress */
0c9ab6f5 5744 phba->fcf.fcf_flag |= FCF_ACVL_DISC;
fc2b989b 5745 spin_unlock_irq(&phba->hbalock);
0c9ab6f5
JS
5746 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5747 LOG_DISCOVERY,
a93ff37a 5748 "2773 Start FCF failover per CVL, "
70f3c073 5749 "evt_tag:x%x\n", acqe_fip->event_tag);
ecfd03c6 5750 rc = lpfc_sli4_redisc_fcf_table(phba);
fc2b989b 5751 if (rc) {
0c9ab6f5
JS
5752 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
5753 LOG_DISCOVERY,
5754 "2774 Issue FCF rediscover "
7afc0ce9 5755 "mailbox command failed, "
0c9ab6f5 5756 "through to CVL event\n");
fc2b989b 5757 spin_lock_irq(&phba->hbalock);
0c9ab6f5 5758 phba->fcf.fcf_flag &= ~FCF_ACVL_DISC;
fc2b989b 5759 spin_unlock_irq(&phba->hbalock);
ecfd03c6
JS
5760 /*
5761 * Last resort will be re-try on the
5762 * the current registered FCF entry.
5763 */
5764 lpfc_retry_pport_discovery(phba);
38b92ef8
JS
5765 } else
5766 /*
5767 * Reset FCF roundrobin bmask for new
5768 * discovery.
5769 */
7d791df7 5770 lpfc_sli4_clear_fcf_rr_bmask(phba);
6669f9bb
JS
5771 }
5772 break;
da0436e9
JS
5773 default:
5774 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5775 "0288 Unknown FCoE event type 0x%x event tag "
70f3c073 5776 "0x%x\n", event_type, acqe_fip->event_tag);
da0436e9
JS
5777 break;
5778 }
5779}
5780
5781/**
5782 * lpfc_sli4_async_dcbx_evt - Process the asynchronous dcbx event
5783 * @phba: pointer to lpfc hba data structure.
5784 * @acqe_link: pointer to the async dcbx completion queue entry.
5785 *
5786 * This routine is to handle the SLI4 asynchronous dcbx event.
5787 **/
5788static void
5789lpfc_sli4_async_dcbx_evt(struct lpfc_hba *phba,
5790 struct lpfc_acqe_dcbx *acqe_dcbx)
5791{
4d9ab994 5792 phba->fc_eventTag = acqe_dcbx->event_tag;
da0436e9
JS
5793 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5794 "0290 The SLI4 DCBX asynchronous event is not "
5795 "handled yet\n");
5796}
5797
b19a061a
JS
5798/**
5799 * lpfc_sli4_async_grp5_evt - Process the asynchronous group5 event
5800 * @phba: pointer to lpfc hba data structure.
5801 * @acqe_link: pointer to the async grp5 completion queue entry.
5802 *
5803 * This routine is to handle the SLI4 asynchronous grp5 event. A grp5 event
5804 * is an asynchronous notified of a logical link speed change. The Port
5805 * reports the logical link speed in units of 10Mbps.
5806 **/
5807static void
5808lpfc_sli4_async_grp5_evt(struct lpfc_hba *phba,
5809 struct lpfc_acqe_grp5 *acqe_grp5)
5810{
5811 uint16_t prev_ll_spd;
5812
5813 phba->fc_eventTag = acqe_grp5->event_tag;
5814 phba->fcoe_eventtag = acqe_grp5->event_tag;
5815 prev_ll_spd = phba->sli4_hba.link_state.logical_speed;
5816 phba->sli4_hba.link_state.logical_speed =
8b68cd52 5817 (bf_get(lpfc_acqe_grp5_llink_spd, acqe_grp5)) * 10;
b19a061a
JS
5818 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5819 "2789 GRP5 Async Event: Updating logical link speed "
8b68cd52
JS
5820 "from %dMbps to %dMbps\n", prev_ll_spd,
5821 phba->sli4_hba.link_state.logical_speed);
b19a061a
JS
5822}
5823
da0436e9
JS
5824/**
5825 * lpfc_sli4_async_event_proc - Process all the pending asynchronous event
5826 * @phba: pointer to lpfc hba data structure.
5827 *
5828 * This routine is invoked by the worker thread to process all the pending
5829 * SLI4 asynchronous events.
5830 **/
5831void lpfc_sli4_async_event_proc(struct lpfc_hba *phba)
5832{
5833 struct lpfc_cq_event *cq_event;
5834
5835 /* First, declare the async event has been handled */
5836 spin_lock_irq(&phba->hbalock);
5837 phba->hba_flag &= ~ASYNC_EVENT;
5838 spin_unlock_irq(&phba->hbalock);
5839 /* Now, handle all the async events */
5840 while (!list_empty(&phba->sli4_hba.sp_asynce_work_queue)) {
5841 /* Get the first event from the head of the event queue */
5842 spin_lock_irq(&phba->hbalock);
5843 list_remove_head(&phba->sli4_hba.sp_asynce_work_queue,
5844 cq_event, struct lpfc_cq_event, list);
5845 spin_unlock_irq(&phba->hbalock);
5846 /* Process the asynchronous event */
5847 switch (bf_get(lpfc_trailer_code, &cq_event->cqe.mcqe_cmpl)) {
5848 case LPFC_TRAILER_CODE_LINK:
5849 lpfc_sli4_async_link_evt(phba,
5850 &cq_event->cqe.acqe_link);
5851 break;
5852 case LPFC_TRAILER_CODE_FCOE:
70f3c073 5853 lpfc_sli4_async_fip_evt(phba, &cq_event->cqe.acqe_fip);
da0436e9
JS
5854 break;
5855 case LPFC_TRAILER_CODE_DCBX:
5856 lpfc_sli4_async_dcbx_evt(phba,
5857 &cq_event->cqe.acqe_dcbx);
5858 break;
b19a061a
JS
5859 case LPFC_TRAILER_CODE_GRP5:
5860 lpfc_sli4_async_grp5_evt(phba,
5861 &cq_event->cqe.acqe_grp5);
5862 break;
70f3c073
JS
5863 case LPFC_TRAILER_CODE_FC:
5864 lpfc_sli4_async_fc_evt(phba, &cq_event->cqe.acqe_fc);
5865 break;
5866 case LPFC_TRAILER_CODE_SLI:
5867 lpfc_sli4_async_sli_evt(phba, &cq_event->cqe.acqe_sli);
5868 break;
da0436e9
JS
5869 default:
5870 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5871 "1804 Invalid asynchrous event code: "
5872 "x%x\n", bf_get(lpfc_trailer_code,
5873 &cq_event->cqe.mcqe_cmpl));
5874 break;
5875 }
5876 /* Free the completion event processed to the free pool */
5877 lpfc_sli4_cq_event_release(phba, cq_event);
5878 }
5879}
5880
ecfd03c6
JS
5881/**
5882 * lpfc_sli4_fcf_redisc_event_proc - Process fcf table rediscovery event
5883 * @phba: pointer to lpfc hba data structure.
5884 *
5885 * This routine is invoked by the worker thread to process FCF table
5886 * rediscovery pending completion event.
5887 **/
5888void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *phba)
5889{
5890 int rc;
5891
5892 spin_lock_irq(&phba->hbalock);
5893 /* Clear FCF rediscovery timeout event */
5894 phba->fcf.fcf_flag &= ~FCF_REDISC_EVT;
5895 /* Clear driver fast failover FCF record flag */
5896 phba->fcf.failover_rec.flag = 0;
5897 /* Set state for FCF fast failover */
5898 phba->fcf.fcf_flag |= FCF_REDISC_FOV;
5899 spin_unlock_irq(&phba->hbalock);
5900
5901 /* Scan FCF table from the first entry to re-discover SAN */
0c9ab6f5 5902 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
a93ff37a 5903 "2777 Start post-quiescent FCF table scan\n");
0c9ab6f5 5904 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST);
ecfd03c6 5905 if (rc)
0c9ab6f5
JS
5906 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
5907 "2747 Issue FCF scan read FCF mailbox "
5908 "command failed 0x%x\n", rc);
ecfd03c6
JS
5909}
5910
da0436e9
JS
5911/**
5912 * lpfc_api_table_setup - Set up per hba pci-device group func api jump table
5913 * @phba: pointer to lpfc hba data structure.
5914 * @dev_grp: The HBA PCI-Device group number.
5915 *
5916 * This routine is invoked to set up the per HBA PCI-Device group function
5917 * API jump table entries.
5918 *
5919 * Return: 0 if success, otherwise -ENODEV
5920 **/
5921int
5922lpfc_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
5923{
5924 int rc;
5925
5926 /* Set up lpfc PCI-device group */
5927 phba->pci_dev_grp = dev_grp;
5928
5929 /* The LPFC_PCI_DEV_OC uses SLI4 */
5930 if (dev_grp == LPFC_PCI_DEV_OC)
5931 phba->sli_rev = LPFC_SLI_REV4;
5932
5933 /* Set up device INIT API function jump table */
5934 rc = lpfc_init_api_table_setup(phba, dev_grp);
5935 if (rc)
5936 return -ENODEV;
5937 /* Set up SCSI API function jump table */
5938 rc = lpfc_scsi_api_table_setup(phba, dev_grp);
5939 if (rc)
5940 return -ENODEV;
5941 /* Set up SLI API function jump table */
5942 rc = lpfc_sli_api_table_setup(phba, dev_grp);
5943 if (rc)
5944 return -ENODEV;
5945 /* Set up MBOX API function jump table */
5946 rc = lpfc_mbox_api_table_setup(phba, dev_grp);
5947 if (rc)
5948 return -ENODEV;
5949
5950 return 0;
5b75da2f
JS
5951}
5952
5953/**
3621a710 5954 * lpfc_log_intr_mode - Log the active interrupt mode
5b75da2f
JS
5955 * @phba: pointer to lpfc hba data structure.
5956 * @intr_mode: active interrupt mode adopted.
5957 *
5958 * This routine it invoked to log the currently used active interrupt mode
5959 * to the device.
3772a991
JS
5960 **/
5961static void lpfc_log_intr_mode(struct lpfc_hba *phba, uint32_t intr_mode)
5b75da2f
JS
5962{
5963 switch (intr_mode) {
5964 case 0:
5965 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5966 "0470 Enable INTx interrupt mode.\n");
5967 break;
5968 case 1:
5969 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5970 "0481 Enabled MSI interrupt mode.\n");
5971 break;
5972 case 2:
5973 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5974 "0480 Enabled MSI-X interrupt mode.\n");
5975 break;
5976 default:
5977 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5978 "0482 Illegal interrupt mode.\n");
5979 break;
5980 }
5981 return;
5982}
5983
5b75da2f 5984/**
3772a991 5985 * lpfc_enable_pci_dev - Enable a generic PCI device.
5b75da2f
JS
5986 * @phba: pointer to lpfc hba data structure.
5987 *
3772a991
JS
5988 * This routine is invoked to enable the PCI device that is common to all
5989 * PCI devices.
5b75da2f
JS
5990 *
5991 * Return codes
af901ca1 5992 * 0 - successful
3772a991 5993 * other values - error
5b75da2f 5994 **/
3772a991
JS
5995static int
5996lpfc_enable_pci_dev(struct lpfc_hba *phba)
5b75da2f 5997{
3772a991 5998 struct pci_dev *pdev;
5b75da2f 5999
3772a991
JS
6000 /* Obtain PCI device reference */
6001 if (!phba->pcidev)
6002 goto out_error;
6003 else
6004 pdev = phba->pcidev;
3772a991
JS
6005 /* Enable PCI device */
6006 if (pci_enable_device_mem(pdev))
6007 goto out_error;
6008 /* Request PCI resource for the device */
e0c0483c 6009 if (pci_request_mem_regions(pdev, LPFC_DRIVER_NAME))
3772a991
JS
6010 goto out_disable_device;
6011 /* Set up device as PCI master and save state for EEH */
6012 pci_set_master(pdev);
6013 pci_try_set_mwi(pdev);
6014 pci_save_state(pdev);
5b75da2f 6015
0558056c 6016 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
453193e0 6017 if (pci_is_pcie(pdev))
0558056c
JS
6018 pdev->needs_freset = 1;
6019
3772a991 6020 return 0;
5b75da2f 6021
3772a991
JS
6022out_disable_device:
6023 pci_disable_device(pdev);
6024out_error:
079b5c91 6025 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e0c0483c 6026 "1401 Failed to enable pci device\n");
3772a991 6027 return -ENODEV;
5b75da2f
JS
6028}
6029
6030/**
3772a991 6031 * lpfc_disable_pci_dev - Disable a generic PCI device.
5b75da2f
JS
6032 * @phba: pointer to lpfc hba data structure.
6033 *
3772a991
JS
6034 * This routine is invoked to disable the PCI device that is common to all
6035 * PCI devices.
5b75da2f
JS
6036 **/
6037static void
3772a991 6038lpfc_disable_pci_dev(struct lpfc_hba *phba)
5b75da2f 6039{
3772a991 6040 struct pci_dev *pdev;
5b75da2f 6041
3772a991
JS
6042 /* Obtain PCI device reference */
6043 if (!phba->pcidev)
6044 return;
6045 else
6046 pdev = phba->pcidev;
3772a991 6047 /* Release PCI resource and disable PCI device */
e0c0483c 6048 pci_release_mem_regions(pdev);
3772a991 6049 pci_disable_device(pdev);
5b75da2f
JS
6050
6051 return;
6052}
6053
e59058c4 6054/**
3772a991
JS
6055 * lpfc_reset_hba - Reset a hba
6056 * @phba: pointer to lpfc hba data structure.
e59058c4 6057 *
3772a991
JS
6058 * This routine is invoked to reset a hba device. It brings the HBA
6059 * offline, performs a board restart, and then brings the board back
6060 * online. The lpfc_offline calls lpfc_sli_hba_down which will clean up
6061 * on outstanding mailbox commands.
e59058c4 6062 **/
3772a991
JS
6063void
6064lpfc_reset_hba(struct lpfc_hba *phba)
dea3101e 6065{
3772a991
JS
6066 /* If resets are disabled then set error state and return. */
6067 if (!phba->cfg_enable_hba_reset) {
6068 phba->link_state = LPFC_HBA_ERROR;
6069 return;
6070 }
ee62021a
JS
6071 if (phba->sli.sli_flag & LPFC_SLI_ACTIVE)
6072 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
6073 else
6074 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
3772a991
JS
6075 lpfc_offline(phba);
6076 lpfc_sli_brdrestart(phba);
6077 lpfc_online(phba);
6078 lpfc_unblock_mgmt_io(phba);
6079}
dea3101e 6080
0a96e975
JS
6081/**
6082 * lpfc_sli_sriov_nr_virtfn_get - Get the number of sr-iov virtual functions
6083 * @phba: pointer to lpfc hba data structure.
6084 *
6085 * This function enables the PCI SR-IOV virtual functions to a physical
6086 * function. It invokes the PCI SR-IOV api with the @nr_vfn provided to
6087 * enable the number of virtual functions to the physical function. As
6088 * not all devices support SR-IOV, the return code from the pci_enable_sriov()
6089 * API call does not considered as an error condition for most of the device.
6090 **/
6091uint16_t
6092lpfc_sli_sriov_nr_virtfn_get(struct lpfc_hba *phba)
6093{
6094 struct pci_dev *pdev = phba->pcidev;
6095 uint16_t nr_virtfn;
6096 int pos;
6097
0a96e975
JS
6098 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6099 if (pos == 0)
6100 return 0;
6101
6102 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, &nr_virtfn);
6103 return nr_virtfn;
6104}
6105
912e3acd
JS
6106/**
6107 * lpfc_sli_probe_sriov_nr_virtfn - Enable a number of sr-iov virtual functions
6108 * @phba: pointer to lpfc hba data structure.
6109 * @nr_vfn: number of virtual functions to be enabled.
6110 *
6111 * This function enables the PCI SR-IOV virtual functions to a physical
6112 * function. It invokes the PCI SR-IOV api with the @nr_vfn provided to
6113 * enable the number of virtual functions to the physical function. As
6114 * not all devices support SR-IOV, the return code from the pci_enable_sriov()
6115 * API call does not considered as an error condition for most of the device.
6116 **/
6117int
6118lpfc_sli_probe_sriov_nr_virtfn(struct lpfc_hba *phba, int nr_vfn)
6119{
6120 struct pci_dev *pdev = phba->pcidev;
0a96e975 6121 uint16_t max_nr_vfn;
912e3acd
JS
6122 int rc;
6123
0a96e975
JS
6124 max_nr_vfn = lpfc_sli_sriov_nr_virtfn_get(phba);
6125 if (nr_vfn > max_nr_vfn) {
6126 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6127 "3057 Requested vfs (%d) greater than "
6128 "supported vfs (%d)", nr_vfn, max_nr_vfn);
6129 return -EINVAL;
6130 }
6131
912e3acd
JS
6132 rc = pci_enable_sriov(pdev, nr_vfn);
6133 if (rc) {
6134 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6135 "2806 Failed to enable sriov on this device "
6136 "with vfn number nr_vf:%d, rc:%d\n",
6137 nr_vfn, rc);
6138 } else
6139 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6140 "2807 Successful enable sriov on this device "
6141 "with vfn number nr_vf:%d\n", nr_vfn);
6142 return rc;
6143}
6144
3772a991 6145/**
895427bd 6146 * lpfc_setup_driver_resource_phase1 - Phase1 etup driver internal resources.
3772a991
JS
6147 * @phba: pointer to lpfc hba data structure.
6148 *
895427bd
JS
6149 * This routine is invoked to set up the driver internal resources before the
6150 * device specific resource setup to support the HBA device it attached to.
3772a991
JS
6151 *
6152 * Return codes
895427bd
JS
6153 * 0 - successful
6154 * other values - error
3772a991
JS
6155 **/
6156static int
895427bd 6157lpfc_setup_driver_resource_phase1(struct lpfc_hba *phba)
3772a991 6158{
895427bd 6159 struct lpfc_sli *psli = &phba->sli;
dea3101e 6160
2e0fef85 6161 /*
895427bd 6162 * Driver resources common to all SLI revisions
2e0fef85 6163 */
895427bd
JS
6164 atomic_set(&phba->fast_event_count, 0);
6165 spin_lock_init(&phba->hbalock);
dea3101e 6166
895427bd
JS
6167 /* Initialize ndlp management spinlock */
6168 spin_lock_init(&phba->ndlp_lock);
6169
523128e5
JS
6170 /* Initialize port_list spinlock */
6171 spin_lock_init(&phba->port_list_lock);
895427bd 6172 INIT_LIST_HEAD(&phba->port_list);
523128e5 6173
895427bd
JS
6174 INIT_LIST_HEAD(&phba->work_list);
6175 init_waitqueue_head(&phba->wait_4_mlo_m_q);
6176
6177 /* Initialize the wait queue head for the kernel thread */
6178 init_waitqueue_head(&phba->work_waitq);
6179
6180 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
f358dd0c 6181 "1403 Protocols supported %s %s %s\n",
895427bd
JS
6182 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) ?
6183 "SCSI" : " "),
6184 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) ?
f358dd0c
JS
6185 "NVME" : " "),
6186 (phba->nvmet_support ? "NVMET" : " "));
895427bd 6187
0794d601
JS
6188 /* Initialize the IO buffer list used by driver for SLI3 SCSI */
6189 spin_lock_init(&phba->scsi_buf_list_get_lock);
6190 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_get);
6191 spin_lock_init(&phba->scsi_buf_list_put_lock);
6192 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_put);
895427bd
JS
6193
6194 /* Initialize the fabric iocb list */
6195 INIT_LIST_HEAD(&phba->fabric_iocb_list);
6196
6197 /* Initialize list to save ELS buffers */
6198 INIT_LIST_HEAD(&phba->elsbuf);
6199
6200 /* Initialize FCF connection rec list */
6201 INIT_LIST_HEAD(&phba->fcf_conn_rec_list);
6202
6203 /* Initialize OAS configuration list */
6204 spin_lock_init(&phba->devicelock);
6205 INIT_LIST_HEAD(&phba->luns);
858c9f6c 6206
3772a991 6207 /* MBOX heartbeat timer */
f22eb4d3 6208 timer_setup(&psli->mbox_tmo, lpfc_mbox_timeout, 0);
3772a991 6209 /* Fabric block timer */
f22eb4d3 6210 timer_setup(&phba->fabric_block_timer, lpfc_fabric_block_timeout, 0);
3772a991 6211 /* EA polling mode timer */
f22eb4d3 6212 timer_setup(&phba->eratt_poll, lpfc_poll_eratt, 0);
895427bd 6213 /* Heartbeat timer */
f22eb4d3 6214 timer_setup(&phba->hb_tmofunc, lpfc_hb_timeout, 0);
895427bd 6215
32517fc0
JS
6216 INIT_DELAYED_WORK(&phba->eq_delay_work, lpfc_hb_eq_delay_work);
6217
895427bd
JS
6218 return 0;
6219}
6220
6221/**
6222 * lpfc_sli_driver_resource_setup - Setup driver internal resources for SLI3 dev
6223 * @phba: pointer to lpfc hba data structure.
6224 *
6225 * This routine is invoked to set up the driver internal resources specific to
6226 * support the SLI-3 HBA device it attached to.
6227 *
6228 * Return codes
6229 * 0 - successful
6230 * other values - error
6231 **/
6232static int
6233lpfc_sli_driver_resource_setup(struct lpfc_hba *phba)
6234{
0794d601 6235 int rc, entry_sz;
895427bd
JS
6236
6237 /*
6238 * Initialize timers used by driver
6239 */
6240
6241 /* FCP polling mode timer */
f22eb4d3 6242 timer_setup(&phba->fcp_poll_timer, lpfc_poll_timeout, 0);
dea3101e 6243
3772a991
JS
6244 /* Host attention work mask setup */
6245 phba->work_ha_mask = (HA_ERATT | HA_MBATT | HA_LATT);
6246 phba->work_ha_mask |= (HA_RXMASK << (LPFC_ELS_RING * 4));
dea3101e 6247
3772a991
JS
6248 /* Get all the module params for configuring this host */
6249 lpfc_get_cfgparam(phba);
895427bd
JS
6250 /* Set up phase-1 common device driver resources */
6251
6252 rc = lpfc_setup_driver_resource_phase1(phba);
6253 if (rc)
6254 return -ENODEV;
6255
49198b37
JS
6256 if (phba->pcidev->device == PCI_DEVICE_ID_HORNET) {
6257 phba->menlo_flag |= HBA_MENLO_SUPPORT;
6258 /* check for menlo minimum sg count */
6259 if (phba->cfg_sg_seg_cnt < LPFC_DEFAULT_MENLO_SG_SEG_CNT)
6260 phba->cfg_sg_seg_cnt = LPFC_DEFAULT_MENLO_SG_SEG_CNT;
6261 }
6262
895427bd 6263 if (!phba->sli.sli3_ring)
6396bb22
KC
6264 phba->sli.sli3_ring = kcalloc(LPFC_SLI3_MAX_RING,
6265 sizeof(struct lpfc_sli_ring),
6266 GFP_KERNEL);
895427bd 6267 if (!phba->sli.sli3_ring)
2a76a283
JS
6268 return -ENOMEM;
6269
dea3101e 6270 /*
96f7077f 6271 * Since lpfc_sg_seg_cnt is module parameter, the sg_dma_buf_size
3772a991 6272 * used to create the sg_dma_buf_pool must be dynamically calculated.
dea3101e 6273 */
3772a991 6274
96f7077f
JS
6275 /* Initialize the host templates the configured values. */
6276 lpfc_vport_template.sg_tablesize = phba->cfg_sg_seg_cnt;
96418b5e
JS
6277 lpfc_template_no_hr.sg_tablesize = phba->cfg_sg_seg_cnt;
6278 lpfc_template.sg_tablesize = phba->cfg_sg_seg_cnt;
96f7077f 6279
0794d601
JS
6280 if (phba->sli_rev == LPFC_SLI_REV4)
6281 entry_sz = sizeof(struct sli4_sge);
6282 else
6283 entry_sz = sizeof(struct ulp_bde64);
6284
96f7077f 6285 /* There are going to be 2 reserved BDEs: 1 FCP cmnd + 1 FCP rsp */
3772a991 6286 if (phba->cfg_enable_bg) {
96f7077f
JS
6287 /*
6288 * The scsi_buf for a T10-DIF I/O will hold the FCP cmnd,
6289 * the FCP rsp, and a BDE for each. Sice we have no control
6290 * over how many protection data segments the SCSI Layer
6291 * will hand us (ie: there could be one for every block
6292 * in the IO), we just allocate enough BDEs to accomidate
6293 * our max amount and we need to limit lpfc_sg_seg_cnt to
6294 * minimize the risk of running out.
6295 */
6296 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6297 sizeof(struct fcp_rsp) +
0794d601 6298 (LPFC_MAX_SG_SEG_CNT * entry_sz);
96f7077f
JS
6299
6300 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SG_SEG_CNT_DIF)
6301 phba->cfg_sg_seg_cnt = LPFC_MAX_SG_SEG_CNT_DIF;
6302
6303 /* Total BDEs in BPL for scsi_sg_list and scsi_sg_prot_list */
6304 phba->cfg_total_seg_cnt = LPFC_MAX_SG_SEG_CNT;
6305 } else {
6306 /*
6307 * The scsi_buf for a regular I/O will hold the FCP cmnd,
6308 * the FCP rsp, a BDE for each, and a BDE for up to
6309 * cfg_sg_seg_cnt data segments.
6310 */
6311 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6312 sizeof(struct fcp_rsp) +
0794d601 6313 ((phba->cfg_sg_seg_cnt + 2) * entry_sz);
96f7077f
JS
6314
6315 /* Total BDEs in BPL for scsi_sg_list */
6316 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + 2;
901a920f 6317 }
dea3101e 6318
96f7077f
JS
6319 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
6320 "9088 sg_tablesize:%d dmabuf_size:%d total_bde:%d\n",
6321 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
6322 phba->cfg_total_seg_cnt);
dea3101e 6323
3772a991
JS
6324 phba->max_vpi = LPFC_MAX_VPI;
6325 /* This will be set to correct value after config_port mbox */
6326 phba->max_vports = 0;
dea3101e 6327
3772a991
JS
6328 /*
6329 * Initialize the SLI Layer to run with lpfc HBAs.
6330 */
6331 lpfc_sli_setup(phba);
895427bd 6332 lpfc_sli_queue_init(phba);
ed957684 6333
3772a991
JS
6334 /* Allocate device driver memory */
6335 if (lpfc_mem_alloc(phba, BPL_ALIGN_SZ))
6336 return -ENOMEM;
51ef4c26 6337
d79c9e9d
JS
6338 phba->lpfc_sg_dma_buf_pool =
6339 dma_pool_create("lpfc_sg_dma_buf_pool",
6340 &phba->pcidev->dev, phba->cfg_sg_dma_buf_size,
6341 BPL_ALIGN_SZ, 0);
6342
6343 if (!phba->lpfc_sg_dma_buf_pool)
6344 goto fail_free_mem;
6345
6346 phba->lpfc_cmd_rsp_buf_pool =
6347 dma_pool_create("lpfc_cmd_rsp_buf_pool",
6348 &phba->pcidev->dev,
6349 sizeof(struct fcp_cmnd) +
6350 sizeof(struct fcp_rsp),
6351 BPL_ALIGN_SZ, 0);
6352
6353 if (!phba->lpfc_cmd_rsp_buf_pool)
6354 goto fail_free_dma_buf_pool;
6355
912e3acd
JS
6356 /*
6357 * Enable sr-iov virtual functions if supported and configured
6358 * through the module parameter.
6359 */
6360 if (phba->cfg_sriov_nr_virtfn > 0) {
6361 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
6362 phba->cfg_sriov_nr_virtfn);
6363 if (rc) {
6364 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6365 "2808 Requested number of SR-IOV "
6366 "virtual functions (%d) is not "
6367 "supported\n",
6368 phba->cfg_sriov_nr_virtfn);
6369 phba->cfg_sriov_nr_virtfn = 0;
6370 }
6371 }
6372
3772a991 6373 return 0;
d79c9e9d
JS
6374
6375fail_free_dma_buf_pool:
6376 dma_pool_destroy(phba->lpfc_sg_dma_buf_pool);
6377 phba->lpfc_sg_dma_buf_pool = NULL;
6378fail_free_mem:
6379 lpfc_mem_free(phba);
6380 return -ENOMEM;
3772a991 6381}
ed957684 6382
3772a991
JS
6383/**
6384 * lpfc_sli_driver_resource_unset - Unset drvr internal resources for SLI3 dev
6385 * @phba: pointer to lpfc hba data structure.
6386 *
6387 * This routine is invoked to unset the driver internal resources set up
6388 * specific for supporting the SLI-3 HBA device it attached to.
6389 **/
6390static void
6391lpfc_sli_driver_resource_unset(struct lpfc_hba *phba)
6392{
6393 /* Free device driver memory allocated */
6394 lpfc_mem_free_all(phba);
3163f725 6395
3772a991
JS
6396 return;
6397}
dea3101e 6398
3772a991 6399/**
da0436e9 6400 * lpfc_sli4_driver_resource_setup - Setup drvr internal resources for SLI4 dev
3772a991
JS
6401 * @phba: pointer to lpfc hba data structure.
6402 *
da0436e9
JS
6403 * This routine is invoked to set up the driver internal resources specific to
6404 * support the SLI-4 HBA device it attached to.
3772a991
JS
6405 *
6406 * Return codes
af901ca1 6407 * 0 - successful
da0436e9 6408 * other values - error
3772a991
JS
6409 **/
6410static int
da0436e9 6411lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
3772a991 6412{
28baac74 6413 LPFC_MBOXQ_t *mboxq;
f358dd0c 6414 MAILBOX_t *mb;
895427bd 6415 int rc, i, max_buf_size;
28baac74
JS
6416 uint8_t pn_page[LPFC_MAX_SUPPORTED_PAGES] = {0};
6417 struct lpfc_mqe *mqe;
09294d46 6418 int longs;
81e6a637 6419 int extra;
f358dd0c 6420 uint64_t wwn;
b92dc72d
JS
6421 u32 if_type;
6422 u32 if_fam;
da0436e9 6423
895427bd 6424 phba->sli4_hba.num_present_cpu = lpfc_present_cpu;
222e9239 6425 phba->sli4_hba.num_possible_cpu = num_possible_cpus();
895427bd
JS
6426 phba->sli4_hba.curr_disp_cpu = 0;
6427
716d3bc5
JS
6428 /* Get all the module params for configuring this host */
6429 lpfc_get_cfgparam(phba);
6430
895427bd
JS
6431 /* Set up phase-1 common device driver resources */
6432 rc = lpfc_setup_driver_resource_phase1(phba);
6433 if (rc)
6434 return -ENODEV;
6435
da0436e9
JS
6436 /* Before proceed, wait for POST done and device ready */
6437 rc = lpfc_sli4_post_status_check(phba);
6438 if (rc)
6439 return -ENODEV;
6440
3cee98db
JS
6441 /* Allocate all driver workqueues here */
6442
6443 /* The lpfc_wq workqueue for deferred irq use */
6444 phba->wq = alloc_workqueue("lpfc_wq", WQ_MEM_RECLAIM, 0);
6445
3772a991 6446 /*
da0436e9 6447 * Initialize timers used by driver
3772a991 6448 */
3772a991 6449
f22eb4d3 6450 timer_setup(&phba->rrq_tmr, lpfc_rrq_timeout, 0);
3772a991 6451
ecfd03c6 6452 /* FCF rediscover timer */
f22eb4d3 6453 timer_setup(&phba->fcf.redisc_wait, lpfc_sli4_fcf_redisc_wait_tmo, 0);
ecfd03c6 6454
7ad20aa9
JS
6455 /*
6456 * Control structure for handling external multi-buffer mailbox
6457 * command pass-through.
6458 */
6459 memset((uint8_t *)&phba->mbox_ext_buf_ctx, 0,
6460 sizeof(struct lpfc_mbox_ext_buf_ctx));
6461 INIT_LIST_HEAD(&phba->mbox_ext_buf_ctx.ext_dmabuf_list);
6462
da0436e9 6463 phba->max_vpi = LPFC_MAX_VPI;
67d12733 6464
da0436e9
JS
6465 /* This will be set to correct value after the read_config mbox */
6466 phba->max_vports = 0;
3772a991 6467
da0436e9
JS
6468 /* Program the default value of vlan_id and fc_map */
6469 phba->valid_vlan = 0;
6470 phba->fc_map[0] = LPFC_FCOE_FCF_MAP0;
6471 phba->fc_map[1] = LPFC_FCOE_FCF_MAP1;
6472 phba->fc_map[2] = LPFC_FCOE_FCF_MAP2;
3772a991 6473
2a76a283
JS
6474 /*
6475 * For SLI4, instead of using ring 0 (LPFC_FCP_RING) for FCP commands
895427bd
JS
6476 * we will associate a new ring, for each EQ/CQ/WQ tuple.
6477 * The WQ create will allocate the ring.
2a76a283 6478 */
09294d46 6479
da0436e9 6480 /* Initialize buffer queue management fields */
895427bd 6481 INIT_LIST_HEAD(&phba->hbqs[LPFC_ELS_HBQ].hbq_buffer_list);
da0436e9
JS
6482 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_sli4_rb_alloc;
6483 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_sli4_rb_free;
3772a991 6484
da0436e9
JS
6485 /*
6486 * Initialize the SLI Layer to run with lpfc SLI4 HBAs.
6487 */
c00f62e6
JS
6488 /* Initialize the Abort buffer list used by driver */
6489 spin_lock_init(&phba->sli4_hba.abts_io_buf_list_lock);
6490 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_io_buf_list);
895427bd
JS
6491
6492 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6493 /* Initialize the Abort nvme buffer list used by driver */
5e5b511d 6494 spin_lock_init(&phba->sli4_hba.abts_nvmet_buf_list_lock);
86c67379 6495 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
a8cf5dfe 6496 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_io_wait_list);
79d8c4ce
JS
6497 spin_lock_init(&phba->sli4_hba.t_active_list_lock);
6498 INIT_LIST_HEAD(&phba->sli4_hba.t_active_ctx_list);
895427bd
JS
6499 }
6500
da0436e9 6501 /* This abort list used by worker thread */
895427bd 6502 spin_lock_init(&phba->sli4_hba.sgl_list_lock);
a8cf5dfe 6503 spin_lock_init(&phba->sli4_hba.nvmet_io_wait_lock);
3772a991 6504
da0436e9 6505 /*
6d368e53 6506 * Initialize driver internal slow-path work queues
da0436e9 6507 */
3772a991 6508
da0436e9
JS
6509 /* Driver internel slow-path CQ Event pool */
6510 INIT_LIST_HEAD(&phba->sli4_hba.sp_cqe_event_pool);
6511 /* Response IOCB work queue list */
45ed1190 6512 INIT_LIST_HEAD(&phba->sli4_hba.sp_queue_event);
da0436e9
JS
6513 /* Asynchronous event CQ Event work queue list */
6514 INIT_LIST_HEAD(&phba->sli4_hba.sp_asynce_work_queue);
6515 /* Fast-path XRI aborted CQ Event work queue list */
6516 INIT_LIST_HEAD(&phba->sli4_hba.sp_fcp_xri_aborted_work_queue);
6517 /* Slow-path XRI aborted CQ Event work queue list */
6518 INIT_LIST_HEAD(&phba->sli4_hba.sp_els_xri_aborted_work_queue);
6519 /* Receive queue CQ Event work queue list */
6520 INIT_LIST_HEAD(&phba->sli4_hba.sp_unsol_work_queue);
6521
6d368e53
JS
6522 /* Initialize extent block lists. */
6523 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_blk_list);
6524 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_xri_blk_list);
6525 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_vfi_blk_list);
6526 INIT_LIST_HEAD(&phba->lpfc_vpi_blk_list);
6527
d1f525aa
JS
6528 /* Initialize mboxq lists. If the early init routines fail
6529 * these lists need to be correctly initialized.
6530 */
6531 INIT_LIST_HEAD(&phba->sli.mboxq);
6532 INIT_LIST_HEAD(&phba->sli.mboxq_cmpl);
6533
448193b5
JS
6534 /* initialize optic_state to 0xFF */
6535 phba->sli4_hba.lnk_info.optic_state = 0xff;
6536
da0436e9
JS
6537 /* Allocate device driver memory */
6538 rc = lpfc_mem_alloc(phba, SGL_ALIGN_SZ);
6539 if (rc)
6540 return -ENOMEM;
6541
2fcee4bf 6542 /* IF Type 2 ports get initialized now. */
27d6ac0a 6543 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
2fcee4bf
JS
6544 LPFC_SLI_INTF_IF_TYPE_2) {
6545 rc = lpfc_pci_function_reset(phba);
895427bd
JS
6546 if (unlikely(rc)) {
6547 rc = -ENODEV;
6548 goto out_free_mem;
6549 }
946727dc 6550 phba->temp_sensor_support = 1;
2fcee4bf
JS
6551 }
6552
da0436e9
JS
6553 /* Create the bootstrap mailbox command */
6554 rc = lpfc_create_bootstrap_mbox(phba);
6555 if (unlikely(rc))
6556 goto out_free_mem;
6557
6558 /* Set up the host's endian order with the device. */
6559 rc = lpfc_setup_endian_order(phba);
6560 if (unlikely(rc))
6561 goto out_free_bsmbx;
6562
6563 /* Set up the hba's configuration parameters. */
6564 rc = lpfc_sli4_read_config(phba);
cff261f6
JS
6565 if (unlikely(rc))
6566 goto out_free_bsmbx;
6567 rc = lpfc_mem_alloc_active_rrq_pool_s4(phba);
da0436e9
JS
6568 if (unlikely(rc))
6569 goto out_free_bsmbx;
6570
2fcee4bf
JS
6571 /* IF Type 0 ports get initialized now. */
6572 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
6573 LPFC_SLI_INTF_IF_TYPE_0) {
6574 rc = lpfc_pci_function_reset(phba);
6575 if (unlikely(rc))
6576 goto out_free_bsmbx;
6577 }
da0436e9 6578
cb5172ea
JS
6579 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
6580 GFP_KERNEL);
6581 if (!mboxq) {
6582 rc = -ENOMEM;
6583 goto out_free_bsmbx;
6584 }
6585
f358dd0c 6586 /* Check for NVMET being configured */
895427bd 6587 phba->nvmet_support = 0;
f358dd0c
JS
6588 if (lpfc_enable_nvmet_cnt) {
6589
6590 /* First get WWN of HBA instance */
6591 lpfc_read_nv(phba, mboxq);
6592 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
6593 if (rc != MBX_SUCCESS) {
6594 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
6595 "6016 Mailbox failed , mbxCmd x%x "
6596 "READ_NV, mbxStatus x%x\n",
6597 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
6598 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
d1f525aa 6599 mempool_free(mboxq, phba->mbox_mem_pool);
f358dd0c
JS
6600 rc = -EIO;
6601 goto out_free_bsmbx;
6602 }
6603 mb = &mboxq->u.mb;
6604 memcpy(&wwn, (char *)mb->un.varRDnvp.nodename,
6605 sizeof(uint64_t));
6606 wwn = cpu_to_be64(wwn);
6607 phba->sli4_hba.wwnn.u.name = wwn;
6608 memcpy(&wwn, (char *)mb->un.varRDnvp.portname,
6609 sizeof(uint64_t));
6610 /* wwn is WWPN of HBA instance */
6611 wwn = cpu_to_be64(wwn);
6612 phba->sli4_hba.wwpn.u.name = wwn;
6613
6614 /* Check to see if it matches any module parameter */
6615 for (i = 0; i < lpfc_enable_nvmet_cnt; i++) {
6616 if (wwn == lpfc_enable_nvmet[i]) {
7d708033 6617#if (IS_ENABLED(CONFIG_NVME_TARGET_FC))
3c603be9
JS
6618 if (lpfc_nvmet_mem_alloc(phba))
6619 break;
6620
6621 phba->nvmet_support = 1; /* a match */
6622
f358dd0c
JS
6623 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6624 "6017 NVME Target %016llx\n",
6625 wwn);
7d708033
JS
6626#else
6627 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6628 "6021 Can't enable NVME Target."
6629 " NVME_TARGET_FC infrastructure"
6630 " is not in kernel\n");
6631#endif
c490850a
JS
6632 /* Not supported for NVMET */
6633 phba->cfg_xri_rebalancing = 0;
3c603be9 6634 break;
f358dd0c
JS
6635 }
6636 }
6637 }
895427bd
JS
6638
6639 lpfc_nvme_mod_param_dep(phba);
6640
fedd3b7b 6641 /* Get the Supported Pages if PORT_CAPABILITIES is supported by port. */
cb5172ea
JS
6642 lpfc_supported_pages(mboxq);
6643 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
fedd3b7b
JS
6644 if (!rc) {
6645 mqe = &mboxq->u.mqe;
6646 memcpy(&pn_page[0], ((uint8_t *)&mqe->un.supp_pages.word3),
6647 LPFC_MAX_SUPPORTED_PAGES);
6648 for (i = 0; i < LPFC_MAX_SUPPORTED_PAGES; i++) {
6649 switch (pn_page[i]) {
6650 case LPFC_SLI4_PARAMETERS:
6651 phba->sli4_hba.pc_sli4_params.supported = 1;
6652 break;
6653 default:
6654 break;
6655 }
6656 }
6657 /* Read the port's SLI4 Parameters capabilities if supported. */
6658 if (phba->sli4_hba.pc_sli4_params.supported)
6659 rc = lpfc_pc_sli4_params_get(phba, mboxq);
6660 if (rc) {
6661 mempool_free(mboxq, phba->mbox_mem_pool);
6662 rc = -EIO;
6663 goto out_free_bsmbx;
cb5172ea
JS
6664 }
6665 }
65791f1f 6666
fedd3b7b
JS
6667 /*
6668 * Get sli4 parameters that override parameters from Port capabilities.
6d368e53
JS
6669 * If this call fails, it isn't critical unless the SLI4 parameters come
6670 * back in conflict.
fedd3b7b 6671 */
6d368e53
JS
6672 rc = lpfc_get_sli4_parameters(phba, mboxq);
6673 if (rc) {
b92dc72d
JS
6674 if_type = bf_get(lpfc_sli_intf_if_type,
6675 &phba->sli4_hba.sli_intf);
6676 if_fam = bf_get(lpfc_sli_intf_sli_family,
6677 &phba->sli4_hba.sli_intf);
6d368e53
JS
6678 if (phba->sli4_hba.extents_in_use &&
6679 phba->sli4_hba.rpi_hdrs_in_use) {
6680 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6681 "2999 Unsupported SLI4 Parameters "
6682 "Extents and RPI headers enabled.\n");
b92dc72d
JS
6683 if (if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
6684 if_fam == LPFC_SLI_INTF_FAMILY_BE2) {
6685 mempool_free(mboxq, phba->mbox_mem_pool);
6686 rc = -EIO;
6687 goto out_free_bsmbx;
6688 }
6689 }
6690 if (!(if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
6691 if_fam == LPFC_SLI_INTF_FAMILY_BE2)) {
6692 mempool_free(mboxq, phba->mbox_mem_pool);
6693 rc = -EIO;
6694 goto out_free_bsmbx;
6d368e53
JS
6695 }
6696 }
895427bd 6697
d79c9e9d
JS
6698 /*
6699 * 1 for cmd, 1 for rsp, NVME adds an extra one
6700 * for boundary conditions in its max_sgl_segment template.
6701 */
6702 extra = 2;
6703 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
6704 extra++;
6705
6706 /*
6707 * It doesn't matter what family our adapter is in, we are
6708 * limited to 2 Pages, 512 SGEs, for our SGL.
6709 * There are going to be 2 reserved SGEs: 1 FCP cmnd + 1 FCP rsp
6710 */
6711 max_buf_size = (2 * SLI4_PAGE_SIZE);
6712
6713 /*
6714 * Since lpfc_sg_seg_cnt is module param, the sg_dma_buf_size
6715 * used to create the sg_dma_buf_pool must be calculated.
6716 */
6717 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED) {
6718 /* Both cfg_enable_bg and cfg_external_dif code paths */
6719
6720 /*
6721 * The scsi_buf for a T10-DIF I/O holds the FCP cmnd,
6722 * the FCP rsp, and a SGE. Sice we have no control
6723 * over how many protection segments the SCSI Layer
6724 * will hand us (ie: there could be one for every block
6725 * in the IO), just allocate enough SGEs to accomidate
6726 * our max amount and we need to limit lpfc_sg_seg_cnt
6727 * to minimize the risk of running out.
6728 */
6729 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6730 sizeof(struct fcp_rsp) + max_buf_size;
6731
6732 /* Total SGEs for scsi_sg_list and scsi_sg_prot_list */
6733 phba->cfg_total_seg_cnt = LPFC_MAX_SGL_SEG_CNT;
6734
6735 /*
6736 * If supporting DIF, reduce the seg count for scsi to
6737 * allow room for the DIF sges.
6738 */
6739 if (phba->cfg_enable_bg &&
6740 phba->cfg_sg_seg_cnt > LPFC_MAX_BG_SLI4_SEG_CNT_DIF)
6741 phba->cfg_scsi_seg_cnt = LPFC_MAX_BG_SLI4_SEG_CNT_DIF;
6742 else
6743 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
6744
6745 } else {
6746 /*
6747 * The scsi_buf for a regular I/O holds the FCP cmnd,
6748 * the FCP rsp, a SGE for each, and a SGE for up to
6749 * cfg_sg_seg_cnt data segments.
6750 */
6751 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6752 sizeof(struct fcp_rsp) +
6753 ((phba->cfg_sg_seg_cnt + extra) *
6754 sizeof(struct sli4_sge));
6755
6756 /* Total SGEs for scsi_sg_list */
6757 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + extra;
6758 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
6759
6760 /*
6761 * NOTE: if (phba->cfg_sg_seg_cnt + extra) <= 256 we only
6762 * need to post 1 page for the SGL.
6763 */
6764 }
6765
6766 if (phba->cfg_xpsgl && !phba->nvmet_support)
6767 phba->cfg_sg_dma_buf_size = LPFC_DEFAULT_XPSGL_SIZE;
6768 else if (phba->cfg_sg_dma_buf_size <= LPFC_MIN_SG_SLI4_BUF_SZ)
6769 phba->cfg_sg_dma_buf_size = LPFC_MIN_SG_SLI4_BUF_SZ;
6770 else
6771 phba->cfg_sg_dma_buf_size =
6772 SLI4_PAGE_ALIGN(phba->cfg_sg_dma_buf_size);
6773
6774 phba->border_sge_num = phba->cfg_sg_dma_buf_size /
6775 sizeof(struct sli4_sge);
6776
6777 /* Limit to LPFC_MAX_NVME_SEG_CNT for NVME. */
6778 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6779 if (phba->cfg_sg_seg_cnt > LPFC_MAX_NVME_SEG_CNT) {
6780 lpfc_printf_log(phba, KERN_INFO, LOG_NVME | LOG_INIT,
6781 "6300 Reducing NVME sg segment "
6782 "cnt to %d\n",
6783 LPFC_MAX_NVME_SEG_CNT);
6784 phba->cfg_nvme_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
6785 } else
6786 phba->cfg_nvme_seg_cnt = phba->cfg_sg_seg_cnt;
6787 }
6788
6789 /* Initialize the host templates with the updated values. */
6790 lpfc_vport_template.sg_tablesize = phba->cfg_scsi_seg_cnt;
6791 lpfc_template.sg_tablesize = phba->cfg_scsi_seg_cnt;
6792 lpfc_template_no_hr.sg_tablesize = phba->cfg_scsi_seg_cnt;
6793
6794 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
6795 "9087 sg_seg_cnt:%d dmabuf_size:%d "
6796 "total:%d scsi:%d nvme:%d\n",
6797 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
6798 phba->cfg_total_seg_cnt, phba->cfg_scsi_seg_cnt,
6799 phba->cfg_nvme_seg_cnt);
6800
6801 if (phba->cfg_sg_dma_buf_size < SLI4_PAGE_SIZE)
6802 i = phba->cfg_sg_dma_buf_size;
6803 else
6804 i = SLI4_PAGE_SIZE;
6805
6806 phba->lpfc_sg_dma_buf_pool =
6807 dma_pool_create("lpfc_sg_dma_buf_pool",
6808 &phba->pcidev->dev,
6809 phba->cfg_sg_dma_buf_size,
6810 i, 0);
6811 if (!phba->lpfc_sg_dma_buf_pool)
6812 goto out_free_bsmbx;
6813
6814 phba->lpfc_cmd_rsp_buf_pool =
6815 dma_pool_create("lpfc_cmd_rsp_buf_pool",
6816 &phba->pcidev->dev,
6817 sizeof(struct fcp_cmnd) +
6818 sizeof(struct fcp_rsp),
6819 i, 0);
6820 if (!phba->lpfc_cmd_rsp_buf_pool)
6821 goto out_free_sg_dma_buf;
6822
cb5172ea 6823 mempool_free(mboxq, phba->mbox_mem_pool);
1ba981fd
JS
6824
6825 /* Verify OAS is supported */
6826 lpfc_sli4_oas_verify(phba);
1ba981fd 6827
d2cc9bcd
JS
6828 /* Verify RAS support on adapter */
6829 lpfc_sli4_ras_init(phba);
6830
5350d872
JS
6831 /* Verify all the SLI4 queues */
6832 rc = lpfc_sli4_queue_verify(phba);
da0436e9 6833 if (rc)
d79c9e9d 6834 goto out_free_cmd_rsp_buf;
da0436e9
JS
6835
6836 /* Create driver internal CQE event pool */
6837 rc = lpfc_sli4_cq_event_pool_create(phba);
6838 if (rc)
d79c9e9d 6839 goto out_free_cmd_rsp_buf;
da0436e9 6840
8a9d2e80
JS
6841 /* Initialize sgl lists per host */
6842 lpfc_init_sgl_list(phba);
6843
6844 /* Allocate and initialize active sgl array */
da0436e9
JS
6845 rc = lpfc_init_active_sgl_array(phba);
6846 if (rc) {
6847 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6848 "1430 Failed to initialize sgl list.\n");
8a9d2e80 6849 goto out_destroy_cq_event_pool;
da0436e9 6850 }
da0436e9
JS
6851 rc = lpfc_sli4_init_rpi_hdrs(phba);
6852 if (rc) {
6853 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6854 "1432 Failed to initialize rpi headers.\n");
6855 goto out_free_active_sgl;
6856 }
6857
a93ff37a 6858 /* Allocate eligible FCF bmask memory for FCF roundrobin failover */
0c9ab6f5 6859 longs = (LPFC_SLI4_FCF_TBL_INDX_MAX + BITS_PER_LONG - 1)/BITS_PER_LONG;
6396bb22 6860 phba->fcf.fcf_rr_bmask = kcalloc(longs, sizeof(unsigned long),
0c9ab6f5
JS
6861 GFP_KERNEL);
6862 if (!phba->fcf.fcf_rr_bmask) {
6863 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6864 "2759 Failed allocate memory for FCF round "
6865 "robin failover bmask\n");
0558056c 6866 rc = -ENOMEM;
0c9ab6f5
JS
6867 goto out_remove_rpi_hdrs;
6868 }
6869
6a828b0f 6870 phba->sli4_hba.hba_eq_hdl = kcalloc(phba->cfg_irq_chann,
cdb42bec
JS
6871 sizeof(struct lpfc_hba_eq_hdl),
6872 GFP_KERNEL);
895427bd 6873 if (!phba->sli4_hba.hba_eq_hdl) {
67d12733
JS
6874 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6875 "2572 Failed allocate memory for "
6876 "fast-path per-EQ handle array\n");
6877 rc = -ENOMEM;
6878 goto out_free_fcf_rr_bmask;
da0436e9
JS
6879 }
6880
222e9239 6881 phba->sli4_hba.cpu_map = kcalloc(phba->sli4_hba.num_possible_cpu,
895427bd
JS
6882 sizeof(struct lpfc_vector_map_info),
6883 GFP_KERNEL);
7bb03bbf
JS
6884 if (!phba->sli4_hba.cpu_map) {
6885 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6886 "3327 Failed allocate memory for msi-x "
6887 "interrupt vector mapping\n");
6888 rc = -ENOMEM;
895427bd 6889 goto out_free_hba_eq_hdl;
7bb03bbf 6890 }
b246de17 6891
32517fc0
JS
6892 phba->sli4_hba.eq_info = alloc_percpu(struct lpfc_eq_intr_info);
6893 if (!phba->sli4_hba.eq_info) {
6894 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6895 "3321 Failed allocation for per_cpu stats\n");
6896 rc = -ENOMEM;
6897 goto out_free_hba_cpu_map;
6898 }
912e3acd
JS
6899 /*
6900 * Enable sr-iov virtual functions if supported and configured
6901 * through the module parameter.
6902 */
6903 if (phba->cfg_sriov_nr_virtfn > 0) {
6904 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
6905 phba->cfg_sriov_nr_virtfn);
6906 if (rc) {
6907 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6908 "3020 Requested number of SR-IOV "
6909 "virtual functions (%d) is not "
6910 "supported\n",
6911 phba->cfg_sriov_nr_virtfn);
6912 phba->cfg_sriov_nr_virtfn = 0;
6913 }
6914 }
6915
5248a749 6916 return 0;
da0436e9 6917
32517fc0
JS
6918out_free_hba_cpu_map:
6919 kfree(phba->sli4_hba.cpu_map);
895427bd
JS
6920out_free_hba_eq_hdl:
6921 kfree(phba->sli4_hba.hba_eq_hdl);
0c9ab6f5
JS
6922out_free_fcf_rr_bmask:
6923 kfree(phba->fcf.fcf_rr_bmask);
da0436e9
JS
6924out_remove_rpi_hdrs:
6925 lpfc_sli4_remove_rpi_hdrs(phba);
6926out_free_active_sgl:
6927 lpfc_free_active_sgl(phba);
da0436e9
JS
6928out_destroy_cq_event_pool:
6929 lpfc_sli4_cq_event_pool_destroy(phba);
d79c9e9d
JS
6930out_free_cmd_rsp_buf:
6931 dma_pool_destroy(phba->lpfc_cmd_rsp_buf_pool);
6932 phba->lpfc_cmd_rsp_buf_pool = NULL;
6933out_free_sg_dma_buf:
6934 dma_pool_destroy(phba->lpfc_sg_dma_buf_pool);
6935 phba->lpfc_sg_dma_buf_pool = NULL;
da0436e9
JS
6936out_free_bsmbx:
6937 lpfc_destroy_bootstrap_mbox(phba);
6938out_free_mem:
6939 lpfc_mem_free(phba);
6940 return rc;
6941}
6942
6943/**
6944 * lpfc_sli4_driver_resource_unset - Unset drvr internal resources for SLI4 dev
6945 * @phba: pointer to lpfc hba data structure.
6946 *
6947 * This routine is invoked to unset the driver internal resources set up
6948 * specific for supporting the SLI-4 HBA device it attached to.
6949 **/
6950static void
6951lpfc_sli4_driver_resource_unset(struct lpfc_hba *phba)
6952{
6953 struct lpfc_fcf_conn_entry *conn_entry, *next_conn_entry;
6954
32517fc0
JS
6955 free_percpu(phba->sli4_hba.eq_info);
6956
7bb03bbf
JS
6957 /* Free memory allocated for msi-x interrupt vector to CPU mapping */
6958 kfree(phba->sli4_hba.cpu_map);
222e9239 6959 phba->sli4_hba.num_possible_cpu = 0;
7bb03bbf 6960 phba->sli4_hba.num_present_cpu = 0;
76fd07a6 6961 phba->sli4_hba.curr_disp_cpu = 0;
7bb03bbf 6962
da0436e9 6963 /* Free memory allocated for fast-path work queue handles */
895427bd 6964 kfree(phba->sli4_hba.hba_eq_hdl);
da0436e9
JS
6965
6966 /* Free the allocated rpi headers. */
6967 lpfc_sli4_remove_rpi_hdrs(phba);
d11e31dd 6968 lpfc_sli4_remove_rpis(phba);
da0436e9 6969
0c9ab6f5
JS
6970 /* Free eligible FCF index bmask */
6971 kfree(phba->fcf.fcf_rr_bmask);
6972
da0436e9
JS
6973 /* Free the ELS sgl list */
6974 lpfc_free_active_sgl(phba);
8a9d2e80 6975 lpfc_free_els_sgl_list(phba);
f358dd0c 6976 lpfc_free_nvmet_sgl_list(phba);
da0436e9 6977
da0436e9
JS
6978 /* Free the completion queue EQ event pool */
6979 lpfc_sli4_cq_event_release_all(phba);
6980 lpfc_sli4_cq_event_pool_destroy(phba);
6981
6d368e53
JS
6982 /* Release resource identifiers. */
6983 lpfc_sli4_dealloc_resource_identifiers(phba);
6984
da0436e9
JS
6985 /* Free the bsmbx region. */
6986 lpfc_destroy_bootstrap_mbox(phba);
6987
6988 /* Free the SLI Layer memory with SLI4 HBAs */
6989 lpfc_mem_free_all(phba);
6990
6991 /* Free the current connect table */
6992 list_for_each_entry_safe(conn_entry, next_conn_entry,
4d9ab994
JS
6993 &phba->fcf_conn_rec_list, list) {
6994 list_del_init(&conn_entry->list);
da0436e9 6995 kfree(conn_entry);
4d9ab994 6996 }
da0436e9
JS
6997
6998 return;
6999}
7000
7001/**
25985edc 7002 * lpfc_init_api_table_setup - Set up init api function jump table
da0436e9
JS
7003 * @phba: The hba struct for which this call is being executed.
7004 * @dev_grp: The HBA PCI-Device group number.
7005 *
7006 * This routine sets up the device INIT interface API function jump table
7007 * in @phba struct.
7008 *
7009 * Returns: 0 - success, -ENODEV - failure.
7010 **/
7011int
7012lpfc_init_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
7013{
84d1b006
JS
7014 phba->lpfc_hba_init_link = lpfc_hba_init_link;
7015 phba->lpfc_hba_down_link = lpfc_hba_down_link;
7f86059a 7016 phba->lpfc_selective_reset = lpfc_selective_reset;
da0436e9
JS
7017 switch (dev_grp) {
7018 case LPFC_PCI_DEV_LP:
7019 phba->lpfc_hba_down_post = lpfc_hba_down_post_s3;
7020 phba->lpfc_handle_eratt = lpfc_handle_eratt_s3;
7021 phba->lpfc_stop_port = lpfc_stop_port_s3;
7022 break;
7023 case LPFC_PCI_DEV_OC:
7024 phba->lpfc_hba_down_post = lpfc_hba_down_post_s4;
7025 phba->lpfc_handle_eratt = lpfc_handle_eratt_s4;
7026 phba->lpfc_stop_port = lpfc_stop_port_s4;
7027 break;
7028 default:
7029 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7030 "1431 Invalid HBA PCI-device group: 0x%x\n",
7031 dev_grp);
7032 return -ENODEV;
7033 break;
7034 }
7035 return 0;
7036}
7037
da0436e9
JS
7038/**
7039 * lpfc_setup_driver_resource_phase2 - Phase2 setup driver internal resources.
7040 * @phba: pointer to lpfc hba data structure.
7041 *
7042 * This routine is invoked to set up the driver internal resources after the
7043 * device specific resource setup to support the HBA device it attached to.
7044 *
7045 * Return codes
af901ca1 7046 * 0 - successful
da0436e9
JS
7047 * other values - error
7048 **/
7049static int
7050lpfc_setup_driver_resource_phase2(struct lpfc_hba *phba)
7051{
7052 int error;
7053
7054 /* Startup the kernel thread for this host adapter. */
7055 phba->worker_thread = kthread_run(lpfc_do_work, phba,
7056 "lpfc_worker_%d", phba->brd_no);
7057 if (IS_ERR(phba->worker_thread)) {
7058 error = PTR_ERR(phba->worker_thread);
7059 return error;
3772a991
JS
7060 }
7061
7062 return 0;
7063}
7064
7065/**
7066 * lpfc_unset_driver_resource_phase2 - Phase2 unset driver internal resources.
7067 * @phba: pointer to lpfc hba data structure.
7068 *
7069 * This routine is invoked to unset the driver internal resources set up after
7070 * the device specific resource setup for supporting the HBA device it
7071 * attached to.
7072 **/
7073static void
7074lpfc_unset_driver_resource_phase2(struct lpfc_hba *phba)
7075{
f485c18d
DK
7076 if (phba->wq) {
7077 flush_workqueue(phba->wq);
7078 destroy_workqueue(phba->wq);
7079 phba->wq = NULL;
7080 }
7081
3772a991 7082 /* Stop kernel worker thread */
0cdb84ec
JS
7083 if (phba->worker_thread)
7084 kthread_stop(phba->worker_thread);
3772a991
JS
7085}
7086
7087/**
7088 * lpfc_free_iocb_list - Free iocb list.
7089 * @phba: pointer to lpfc hba data structure.
7090 *
7091 * This routine is invoked to free the driver's IOCB list and memory.
7092 **/
6c621a22 7093void
3772a991
JS
7094lpfc_free_iocb_list(struct lpfc_hba *phba)
7095{
7096 struct lpfc_iocbq *iocbq_entry = NULL, *iocbq_next = NULL;
7097
7098 spin_lock_irq(&phba->hbalock);
7099 list_for_each_entry_safe(iocbq_entry, iocbq_next,
7100 &phba->lpfc_iocb_list, list) {
7101 list_del(&iocbq_entry->list);
7102 kfree(iocbq_entry);
7103 phba->total_iocbq_bufs--;
98c9ea5c 7104 }
3772a991
JS
7105 spin_unlock_irq(&phba->hbalock);
7106
7107 return;
7108}
7109
7110/**
7111 * lpfc_init_iocb_list - Allocate and initialize iocb list.
7112 * @phba: pointer to lpfc hba data structure.
7113 *
7114 * This routine is invoked to allocate and initizlize the driver's IOCB
7115 * list and set up the IOCB tag array accordingly.
7116 *
7117 * Return codes
af901ca1 7118 * 0 - successful
3772a991
JS
7119 * other values - error
7120 **/
6c621a22 7121int
3772a991
JS
7122lpfc_init_iocb_list(struct lpfc_hba *phba, int iocb_count)
7123{
7124 struct lpfc_iocbq *iocbq_entry = NULL;
7125 uint16_t iotag;
7126 int i;
dea3101e 7127
7128 /* Initialize and populate the iocb list per host. */
7129 INIT_LIST_HEAD(&phba->lpfc_iocb_list);
3772a991 7130 for (i = 0; i < iocb_count; i++) {
dd00cc48 7131 iocbq_entry = kzalloc(sizeof(struct lpfc_iocbq), GFP_KERNEL);
dea3101e 7132 if (iocbq_entry == NULL) {
7133 printk(KERN_ERR "%s: only allocated %d iocbs of "
7134 "expected %d count. Unloading driver.\n",
a5f7337f 7135 __func__, i, iocb_count);
dea3101e 7136 goto out_free_iocbq;
7137 }
7138
604a3e30
JB
7139 iotag = lpfc_sli_next_iotag(phba, iocbq_entry);
7140 if (iotag == 0) {
3772a991 7141 kfree(iocbq_entry);
604a3e30 7142 printk(KERN_ERR "%s: failed to allocate IOTAG. "
3772a991 7143 "Unloading driver.\n", __func__);
604a3e30
JB
7144 goto out_free_iocbq;
7145 }
6d368e53 7146 iocbq_entry->sli4_lxritag = NO_XRI;
3772a991 7147 iocbq_entry->sli4_xritag = NO_XRI;
2e0fef85
JS
7148
7149 spin_lock_irq(&phba->hbalock);
dea3101e 7150 list_add(&iocbq_entry->list, &phba->lpfc_iocb_list);
7151 phba->total_iocbq_bufs++;
2e0fef85 7152 spin_unlock_irq(&phba->hbalock);
dea3101e 7153 }
7154
3772a991 7155 return 0;
dea3101e 7156
3772a991
JS
7157out_free_iocbq:
7158 lpfc_free_iocb_list(phba);
dea3101e 7159
3772a991
JS
7160 return -ENOMEM;
7161}
5e9d9b82 7162
3772a991 7163/**
8a9d2e80 7164 * lpfc_free_sgl_list - Free a given sgl list.
da0436e9 7165 * @phba: pointer to lpfc hba data structure.
8a9d2e80 7166 * @sglq_list: pointer to the head of sgl list.
3772a991 7167 *
8a9d2e80 7168 * This routine is invoked to free a give sgl list and memory.
3772a991 7169 **/
8a9d2e80
JS
7170void
7171lpfc_free_sgl_list(struct lpfc_hba *phba, struct list_head *sglq_list)
3772a991 7172{
da0436e9 7173 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
8a9d2e80
JS
7174
7175 list_for_each_entry_safe(sglq_entry, sglq_next, sglq_list, list) {
7176 list_del(&sglq_entry->list);
7177 lpfc_mbuf_free(phba, sglq_entry->virt, sglq_entry->phys);
7178 kfree(sglq_entry);
7179 }
7180}
7181
7182/**
7183 * lpfc_free_els_sgl_list - Free els sgl list.
7184 * @phba: pointer to lpfc hba data structure.
7185 *
7186 * This routine is invoked to free the driver's els sgl list and memory.
7187 **/
7188static void
7189lpfc_free_els_sgl_list(struct lpfc_hba *phba)
7190{
da0436e9 7191 LIST_HEAD(sglq_list);
dea3101e 7192
8a9d2e80 7193 /* Retrieve all els sgls from driver list */
da0436e9 7194 spin_lock_irq(&phba->hbalock);
895427bd
JS
7195 spin_lock(&phba->sli4_hba.sgl_list_lock);
7196 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list, &sglq_list);
7197 spin_unlock(&phba->sli4_hba.sgl_list_lock);
da0436e9 7198 spin_unlock_irq(&phba->hbalock);
dea3101e 7199
8a9d2e80
JS
7200 /* Now free the sgl list */
7201 lpfc_free_sgl_list(phba, &sglq_list);
da0436e9 7202}
92d7f7b0 7203
f358dd0c
JS
7204/**
7205 * lpfc_free_nvmet_sgl_list - Free nvmet sgl list.
7206 * @phba: pointer to lpfc hba data structure.
7207 *
7208 * This routine is invoked to free the driver's nvmet sgl list and memory.
7209 **/
7210static void
7211lpfc_free_nvmet_sgl_list(struct lpfc_hba *phba)
7212{
7213 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
7214 LIST_HEAD(sglq_list);
7215
7216 /* Retrieve all nvmet sgls from driver list */
7217 spin_lock_irq(&phba->hbalock);
7218 spin_lock(&phba->sli4_hba.sgl_list_lock);
7219 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list, &sglq_list);
7220 spin_unlock(&phba->sli4_hba.sgl_list_lock);
7221 spin_unlock_irq(&phba->hbalock);
7222
7223 /* Now free the sgl list */
7224 list_for_each_entry_safe(sglq_entry, sglq_next, &sglq_list, list) {
7225 list_del(&sglq_entry->list);
7226 lpfc_nvmet_buf_free(phba, sglq_entry->virt, sglq_entry->phys);
7227 kfree(sglq_entry);
7228 }
4b40d02b
DK
7229
7230 /* Update the nvmet_xri_cnt to reflect no current sgls.
7231 * The next initialization cycle sets the count and allocates
7232 * the sgls over again.
7233 */
7234 phba->sli4_hba.nvmet_xri_cnt = 0;
f358dd0c
JS
7235}
7236
da0436e9
JS
7237/**
7238 * lpfc_init_active_sgl_array - Allocate the buf to track active ELS XRIs.
7239 * @phba: pointer to lpfc hba data structure.
7240 *
7241 * This routine is invoked to allocate the driver's active sgl memory.
7242 * This array will hold the sglq_entry's for active IOs.
7243 **/
7244static int
7245lpfc_init_active_sgl_array(struct lpfc_hba *phba)
7246{
7247 int size;
7248 size = sizeof(struct lpfc_sglq *);
7249 size *= phba->sli4_hba.max_cfg_param.max_xri;
7250
7251 phba->sli4_hba.lpfc_sglq_active_list =
7252 kzalloc(size, GFP_KERNEL);
7253 if (!phba->sli4_hba.lpfc_sglq_active_list)
7254 return -ENOMEM;
7255 return 0;
3772a991
JS
7256}
7257
7258/**
da0436e9 7259 * lpfc_free_active_sgl - Free the buf that tracks active ELS XRIs.
3772a991
JS
7260 * @phba: pointer to lpfc hba data structure.
7261 *
da0436e9
JS
7262 * This routine is invoked to walk through the array of active sglq entries
7263 * and free all of the resources.
7264 * This is just a place holder for now.
3772a991
JS
7265 **/
7266static void
da0436e9 7267lpfc_free_active_sgl(struct lpfc_hba *phba)
3772a991 7268{
da0436e9 7269 kfree(phba->sli4_hba.lpfc_sglq_active_list);
3772a991
JS
7270}
7271
7272/**
da0436e9 7273 * lpfc_init_sgl_list - Allocate and initialize sgl list.
3772a991
JS
7274 * @phba: pointer to lpfc hba data structure.
7275 *
da0436e9
JS
7276 * This routine is invoked to allocate and initizlize the driver's sgl
7277 * list and set up the sgl xritag tag array accordingly.
3772a991 7278 *
3772a991 7279 **/
8a9d2e80 7280static void
da0436e9 7281lpfc_init_sgl_list(struct lpfc_hba *phba)
3772a991 7282{
da0436e9 7283 /* Initialize and populate the sglq list per host/VF. */
895427bd 7284 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_els_sgl_list);
da0436e9 7285 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_els_sgl_list);
f358dd0c 7286 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_sgl_list);
86c67379 7287 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
da0436e9 7288
8a9d2e80
JS
7289 /* els xri-sgl book keeping */
7290 phba->sli4_hba.els_xri_cnt = 0;
0ff10d46 7291
895427bd 7292 /* nvme xri-buffer book keeping */
5e5b511d 7293 phba->sli4_hba.io_xri_cnt = 0;
da0436e9
JS
7294}
7295
7296/**
7297 * lpfc_sli4_init_rpi_hdrs - Post the rpi header memory region to the port
7298 * @phba: pointer to lpfc hba data structure.
7299 *
7300 * This routine is invoked to post rpi header templates to the
88a2cfbb 7301 * port for those SLI4 ports that do not support extents. This routine
da0436e9 7302 * posts a PAGE_SIZE memory region to the port to hold up to
88a2cfbb
JS
7303 * PAGE_SIZE modulo 64 rpi context headers. This is an initialization routine
7304 * and should be called only when interrupts are disabled.
da0436e9
JS
7305 *
7306 * Return codes
af901ca1 7307 * 0 - successful
88a2cfbb 7308 * -ERROR - otherwise.
da0436e9
JS
7309 **/
7310int
7311lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *phba)
7312{
7313 int rc = 0;
da0436e9
JS
7314 struct lpfc_rpi_hdr *rpi_hdr;
7315
7316 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_hdr_list);
ff78d8f9 7317 if (!phba->sli4_hba.rpi_hdrs_in_use)
6d368e53 7318 return rc;
6d368e53
JS
7319 if (phba->sli4_hba.extents_in_use)
7320 return -EIO;
da0436e9
JS
7321
7322 rpi_hdr = lpfc_sli4_create_rpi_hdr(phba);
7323 if (!rpi_hdr) {
7324 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI,
7325 "0391 Error during rpi post operation\n");
7326 lpfc_sli4_remove_rpis(phba);
7327 rc = -ENODEV;
7328 }
7329
7330 return rc;
7331}
7332
7333/**
7334 * lpfc_sli4_create_rpi_hdr - Allocate an rpi header memory region
7335 * @phba: pointer to lpfc hba data structure.
7336 *
7337 * This routine is invoked to allocate a single 4KB memory region to
7338 * support rpis and stores them in the phba. This single region
7339 * provides support for up to 64 rpis. The region is used globally
7340 * by the device.
7341 *
7342 * Returns:
7343 * A valid rpi hdr on success.
7344 * A NULL pointer on any failure.
7345 **/
7346struct lpfc_rpi_hdr *
7347lpfc_sli4_create_rpi_hdr(struct lpfc_hba *phba)
7348{
7349 uint16_t rpi_limit, curr_rpi_range;
7350 struct lpfc_dmabuf *dmabuf;
7351 struct lpfc_rpi_hdr *rpi_hdr;
7352
6d368e53
JS
7353 /*
7354 * If the SLI4 port supports extents, posting the rpi header isn't
7355 * required. Set the expected maximum count and let the actual value
7356 * get set when extents are fully allocated.
7357 */
7358 if (!phba->sli4_hba.rpi_hdrs_in_use)
7359 return NULL;
7360 if (phba->sli4_hba.extents_in_use)
7361 return NULL;
7362
7363 /* The limit on the logical index is just the max_rpi count. */
845d9e8d 7364 rpi_limit = phba->sli4_hba.max_cfg_param.max_rpi;
da0436e9
JS
7365
7366 spin_lock_irq(&phba->hbalock);
6d368e53
JS
7367 /*
7368 * Establish the starting RPI in this header block. The starting
7369 * rpi is normalized to a zero base because the physical rpi is
7370 * port based.
7371 */
97f2ecf1 7372 curr_rpi_range = phba->sli4_hba.next_rpi;
da0436e9
JS
7373 spin_unlock_irq(&phba->hbalock);
7374
845d9e8d
JS
7375 /* Reached full RPI range */
7376 if (curr_rpi_range == rpi_limit)
6d368e53 7377 return NULL;
845d9e8d 7378
da0436e9
JS
7379 /*
7380 * First allocate the protocol header region for the port. The
7381 * port expects a 4KB DMA-mapped memory region that is 4K aligned.
7382 */
7383 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
7384 if (!dmabuf)
7385 return NULL;
7386
750afb08
LC
7387 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
7388 LPFC_HDR_TEMPLATE_SIZE,
7389 &dmabuf->phys, GFP_KERNEL);
da0436e9
JS
7390 if (!dmabuf->virt) {
7391 rpi_hdr = NULL;
7392 goto err_free_dmabuf;
7393 }
7394
da0436e9
JS
7395 if (!IS_ALIGNED(dmabuf->phys, LPFC_HDR_TEMPLATE_SIZE)) {
7396 rpi_hdr = NULL;
7397 goto err_free_coherent;
7398 }
7399
7400 /* Save the rpi header data for cleanup later. */
7401 rpi_hdr = kzalloc(sizeof(struct lpfc_rpi_hdr), GFP_KERNEL);
7402 if (!rpi_hdr)
7403 goto err_free_coherent;
7404
7405 rpi_hdr->dmabuf = dmabuf;
7406 rpi_hdr->len = LPFC_HDR_TEMPLATE_SIZE;
7407 rpi_hdr->page_count = 1;
7408 spin_lock_irq(&phba->hbalock);
6d368e53
JS
7409
7410 /* The rpi_hdr stores the logical index only. */
7411 rpi_hdr->start_rpi = curr_rpi_range;
845d9e8d 7412 rpi_hdr->next_rpi = phba->sli4_hba.next_rpi + LPFC_RPI_HDR_COUNT;
da0436e9
JS
7413 list_add_tail(&rpi_hdr->list, &phba->sli4_hba.lpfc_rpi_hdr_list);
7414
da0436e9
JS
7415 spin_unlock_irq(&phba->hbalock);
7416 return rpi_hdr;
7417
7418 err_free_coherent:
7419 dma_free_coherent(&phba->pcidev->dev, LPFC_HDR_TEMPLATE_SIZE,
7420 dmabuf->virt, dmabuf->phys);
7421 err_free_dmabuf:
7422 kfree(dmabuf);
7423 return NULL;
7424}
7425
7426/**
7427 * lpfc_sli4_remove_rpi_hdrs - Remove all rpi header memory regions
7428 * @phba: pointer to lpfc hba data structure.
7429 *
7430 * This routine is invoked to remove all memory resources allocated
6d368e53
JS
7431 * to support rpis for SLI4 ports not supporting extents. This routine
7432 * presumes the caller has released all rpis consumed by fabric or port
7433 * logins and is prepared to have the header pages removed.
da0436e9
JS
7434 **/
7435void
7436lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *phba)
7437{
7438 struct lpfc_rpi_hdr *rpi_hdr, *next_rpi_hdr;
7439
6d368e53
JS
7440 if (!phba->sli4_hba.rpi_hdrs_in_use)
7441 goto exit;
7442
da0436e9
JS
7443 list_for_each_entry_safe(rpi_hdr, next_rpi_hdr,
7444 &phba->sli4_hba.lpfc_rpi_hdr_list, list) {
7445 list_del(&rpi_hdr->list);
7446 dma_free_coherent(&phba->pcidev->dev, rpi_hdr->len,
7447 rpi_hdr->dmabuf->virt, rpi_hdr->dmabuf->phys);
7448 kfree(rpi_hdr->dmabuf);
7449 kfree(rpi_hdr);
7450 }
6d368e53
JS
7451 exit:
7452 /* There are no rpis available to the port now. */
7453 phba->sli4_hba.next_rpi = 0;
da0436e9
JS
7454}
7455
7456/**
7457 * lpfc_hba_alloc - Allocate driver hba data structure for a device.
7458 * @pdev: pointer to pci device data structure.
7459 *
7460 * This routine is invoked to allocate the driver hba data structure for an
7461 * HBA device. If the allocation is successful, the phba reference to the
7462 * PCI device data structure is set.
7463 *
7464 * Return codes
af901ca1 7465 * pointer to @phba - successful
da0436e9
JS
7466 * NULL - error
7467 **/
7468static struct lpfc_hba *
7469lpfc_hba_alloc(struct pci_dev *pdev)
7470{
7471 struct lpfc_hba *phba;
7472
7473 /* Allocate memory for HBA structure */
7474 phba = kzalloc(sizeof(struct lpfc_hba), GFP_KERNEL);
7475 if (!phba) {
e34ccdfe 7476 dev_err(&pdev->dev, "failed to allocate hba struct\n");
da0436e9
JS
7477 return NULL;
7478 }
7479
7480 /* Set reference to PCI device in HBA structure */
7481 phba->pcidev = pdev;
7482
7483 /* Assign an unused board number */
7484 phba->brd_no = lpfc_get_instance();
7485 if (phba->brd_no < 0) {
7486 kfree(phba);
7487 return NULL;
7488 }
65791f1f 7489 phba->eratt_poll_interval = LPFC_ERATT_POLL_INTERVAL;
da0436e9 7490
4fede78f 7491 spin_lock_init(&phba->ct_ev_lock);
f1c3b0fc
JS
7492 INIT_LIST_HEAD(&phba->ct_ev_waiters);
7493
da0436e9
JS
7494 return phba;
7495}
7496
7497/**
7498 * lpfc_hba_free - Free driver hba data structure with a device.
7499 * @phba: pointer to lpfc hba data structure.
7500 *
7501 * This routine is invoked to free the driver hba data structure with an
7502 * HBA device.
7503 **/
7504static void
7505lpfc_hba_free(struct lpfc_hba *phba)
7506{
5e5b511d
JS
7507 if (phba->sli_rev == LPFC_SLI_REV4)
7508 kfree(phba->sli4_hba.hdwq);
7509
da0436e9
JS
7510 /* Release the driver assigned board number */
7511 idr_remove(&lpfc_hba_index, phba->brd_no);
7512
895427bd
JS
7513 /* Free memory allocated with sli3 rings */
7514 kfree(phba->sli.sli3_ring);
7515 phba->sli.sli3_ring = NULL;
2a76a283 7516
da0436e9
JS
7517 kfree(phba);
7518 return;
7519}
7520
7521/**
7522 * lpfc_create_shost - Create hba physical port with associated scsi host.
7523 * @phba: pointer to lpfc hba data structure.
7524 *
7525 * This routine is invoked to create HBA physical port and associate a SCSI
7526 * host with it.
7527 *
7528 * Return codes
af901ca1 7529 * 0 - successful
da0436e9
JS
7530 * other values - error
7531 **/
7532static int
7533lpfc_create_shost(struct lpfc_hba *phba)
7534{
7535 struct lpfc_vport *vport;
7536 struct Scsi_Host *shost;
7537
7538 /* Initialize HBA FC structure */
7539 phba->fc_edtov = FF_DEF_EDTOV;
7540 phba->fc_ratov = FF_DEF_RATOV;
7541 phba->fc_altov = FF_DEF_ALTOV;
7542 phba->fc_arbtov = FF_DEF_ARBTOV;
7543
d7c47992 7544 atomic_set(&phba->sdev_cnt, 0);
da0436e9
JS
7545 vport = lpfc_create_port(phba, phba->brd_no, &phba->pcidev->dev);
7546 if (!vport)
7547 return -ENODEV;
7548
7549 shost = lpfc_shost_from_vport(vport);
7550 phba->pport = vport;
2ea259ee 7551
f358dd0c
JS
7552 if (phba->nvmet_support) {
7553 /* Only 1 vport (pport) will support NVME target */
7554 if (phba->txrdy_payload_pool == NULL) {
771db5c0
RP
7555 phba->txrdy_payload_pool = dma_pool_create(
7556 "txrdy_pool", &phba->pcidev->dev,
f358dd0c
JS
7557 TXRDY_PAYLOAD_LEN, 16, 0);
7558 if (phba->txrdy_payload_pool) {
7559 phba->targetport = NULL;
7560 phba->cfg_enable_fc4_type = LPFC_ENABLE_NVME;
7561 lpfc_printf_log(phba, KERN_INFO,
7562 LOG_INIT | LOG_NVME_DISC,
7563 "6076 NVME Target Found\n");
7564 }
7565 }
7566 }
7567
da0436e9
JS
7568 lpfc_debugfs_initialize(vport);
7569 /* Put reference to SCSI host to driver's device private data */
7570 pci_set_drvdata(phba->pcidev, shost);
2e0fef85 7571
4258e98e
JS
7572 /*
7573 * At this point we are fully registered with PSA. In addition,
7574 * any initial discovery should be completed.
7575 */
7576 vport->load_flag |= FC_ALLOW_FDMI;
8663cbbe
JS
7577 if (phba->cfg_enable_SmartSAN ||
7578 (phba->cfg_fdmi_on == LPFC_FDMI_SUPPORT)) {
4258e98e
JS
7579
7580 /* Setup appropriate attribute masks */
7581 vport->fdmi_hba_mask = LPFC_FDMI2_HBA_ATTR;
8663cbbe 7582 if (phba->cfg_enable_SmartSAN)
4258e98e
JS
7583 vport->fdmi_port_mask = LPFC_FDMI2_SMART_ATTR;
7584 else
7585 vport->fdmi_port_mask = LPFC_FDMI2_PORT_ATTR;
7586 }
3772a991
JS
7587 return 0;
7588}
db2378e0 7589
3772a991
JS
7590/**
7591 * lpfc_destroy_shost - Destroy hba physical port with associated scsi host.
7592 * @phba: pointer to lpfc hba data structure.
7593 *
7594 * This routine is invoked to destroy HBA physical port and the associated
7595 * SCSI host.
7596 **/
7597static void
7598lpfc_destroy_shost(struct lpfc_hba *phba)
7599{
7600 struct lpfc_vport *vport = phba->pport;
7601
7602 /* Destroy physical port that associated with the SCSI host */
7603 destroy_port(vport);
7604
7605 return;
7606}
7607
7608/**
7609 * lpfc_setup_bg - Setup Block guard structures and debug areas.
7610 * @phba: pointer to lpfc hba data structure.
7611 * @shost: the shost to be used to detect Block guard settings.
7612 *
7613 * This routine sets up the local Block guard protocol settings for @shost.
7614 * This routine also allocates memory for debugging bg buffers.
7615 **/
7616static void
7617lpfc_setup_bg(struct lpfc_hba *phba, struct Scsi_Host *shost)
7618{
bbeb79b9
JS
7619 uint32_t old_mask;
7620 uint32_t old_guard;
7621
b3b98b74 7622 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
3772a991
JS
7623 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7624 "1478 Registering BlockGuard with the "
7625 "SCSI layer\n");
bbeb79b9 7626
b3b98b74
JS
7627 old_mask = phba->cfg_prot_mask;
7628 old_guard = phba->cfg_prot_guard;
bbeb79b9
JS
7629
7630 /* Only allow supported values */
b3b98b74 7631 phba->cfg_prot_mask &= (SHOST_DIF_TYPE1_PROTECTION |
bbeb79b9
JS
7632 SHOST_DIX_TYPE0_PROTECTION |
7633 SHOST_DIX_TYPE1_PROTECTION);
b3b98b74
JS
7634 phba->cfg_prot_guard &= (SHOST_DIX_GUARD_IP |
7635 SHOST_DIX_GUARD_CRC);
bbeb79b9
JS
7636
7637 /* DIF Type 1 protection for profiles AST1/C1 is end to end */
b3b98b74
JS
7638 if (phba->cfg_prot_mask == SHOST_DIX_TYPE1_PROTECTION)
7639 phba->cfg_prot_mask |= SHOST_DIF_TYPE1_PROTECTION;
bbeb79b9 7640
b3b98b74
JS
7641 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
7642 if ((old_mask != phba->cfg_prot_mask) ||
7643 (old_guard != phba->cfg_prot_guard))
bbeb79b9
JS
7644 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7645 "1475 Registering BlockGuard with the "
7646 "SCSI layer: mask %d guard %d\n",
b3b98b74
JS
7647 phba->cfg_prot_mask,
7648 phba->cfg_prot_guard);
bbeb79b9 7649
b3b98b74
JS
7650 scsi_host_set_prot(shost, phba->cfg_prot_mask);
7651 scsi_host_set_guard(shost, phba->cfg_prot_guard);
bbeb79b9
JS
7652 } else
7653 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7654 "1479 Not Registering BlockGuard with the SCSI "
7655 "layer, Bad protection parameters: %d %d\n",
7656 old_mask, old_guard);
3772a991 7657 }
3772a991
JS
7658}
7659
7660/**
7661 * lpfc_post_init_setup - Perform necessary device post initialization setup.
7662 * @phba: pointer to lpfc hba data structure.
7663 *
7664 * This routine is invoked to perform all the necessary post initialization
7665 * setup for the device.
7666 **/
7667static void
7668lpfc_post_init_setup(struct lpfc_hba *phba)
7669{
7670 struct Scsi_Host *shost;
7671 struct lpfc_adapter_event_header adapter_event;
7672
7673 /* Get the default values for Model Name and Description */
7674 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
7675
7676 /*
7677 * hba setup may have changed the hba_queue_depth so we need to
7678 * adjust the value of can_queue.
7679 */
7680 shost = pci_get_drvdata(phba->pcidev);
7681 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3772a991
JS
7682
7683 lpfc_host_attrib_init(shost);
7684
7685 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
7686 spin_lock_irq(shost->host_lock);
7687 lpfc_poll_start_timer(phba);
7688 spin_unlock_irq(shost->host_lock);
7689 }
7690
7691 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7692 "0428 Perform SCSI scan\n");
7693 /* Send board arrival event to upper layer */
7694 adapter_event.event_type = FC_REG_ADAPTER_EVENT;
7695 adapter_event.subcategory = LPFC_EVENT_ARRIVAL;
7696 fc_host_post_vendor_event(shost, fc_get_event_number(),
7697 sizeof(adapter_event),
7698 (char *) &adapter_event,
7699 LPFC_NL_VENDOR_ID);
7700 return;
7701}
7702
7703/**
7704 * lpfc_sli_pci_mem_setup - Setup SLI3 HBA PCI memory space.
7705 * @phba: pointer to lpfc hba data structure.
7706 *
7707 * This routine is invoked to set up the PCI device memory space for device
7708 * with SLI-3 interface spec.
7709 *
7710 * Return codes
af901ca1 7711 * 0 - successful
3772a991
JS
7712 * other values - error
7713 **/
7714static int
7715lpfc_sli_pci_mem_setup(struct lpfc_hba *phba)
7716{
f30e1bfd 7717 struct pci_dev *pdev = phba->pcidev;
3772a991
JS
7718 unsigned long bar0map_len, bar2map_len;
7719 int i, hbq_count;
7720 void *ptr;
56de8357 7721 int error;
3772a991 7722
f30e1bfd 7723 if (!pdev)
56de8357 7724 return -ENODEV;
3772a991
JS
7725
7726 /* Set the device DMA mask size */
56de8357
HR
7727 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7728 if (error)
7729 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7730 if (error)
f30e1bfd 7731 return error;
56de8357 7732 error = -ENODEV;
3772a991
JS
7733
7734 /* Get the bus address of Bar0 and Bar2 and the number of bytes
7735 * required by each mapping.
7736 */
7737 phba->pci_bar0_map = pci_resource_start(pdev, 0);
7738 bar0map_len = pci_resource_len(pdev, 0);
7739
7740 phba->pci_bar2_map = pci_resource_start(pdev, 2);
7741 bar2map_len = pci_resource_len(pdev, 2);
7742
7743 /* Map HBA SLIM to a kernel virtual address. */
7744 phba->slim_memmap_p = ioremap(phba->pci_bar0_map, bar0map_len);
7745 if (!phba->slim_memmap_p) {
7746 dev_printk(KERN_ERR, &pdev->dev,
7747 "ioremap failed for SLIM memory.\n");
7748 goto out;
7749 }
7750
7751 /* Map HBA Control Registers to a kernel virtual address. */
7752 phba->ctrl_regs_memmap_p = ioremap(phba->pci_bar2_map, bar2map_len);
7753 if (!phba->ctrl_regs_memmap_p) {
7754 dev_printk(KERN_ERR, &pdev->dev,
7755 "ioremap failed for HBA control registers.\n");
7756 goto out_iounmap_slim;
7757 }
7758
7759 /* Allocate memory for SLI-2 structures */
750afb08
LC
7760 phba->slim2p.virt = dma_alloc_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7761 &phba->slim2p.phys, GFP_KERNEL);
3772a991
JS
7762 if (!phba->slim2p.virt)
7763 goto out_iounmap;
7764
3772a991 7765 phba->mbox = phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, mbx);
7a470277
JS
7766 phba->mbox_ext = (phba->slim2p.virt +
7767 offsetof(struct lpfc_sli2_slim, mbx_ext_words));
3772a991
JS
7768 phba->pcb = (phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, pcb));
7769 phba->IOCBs = (phba->slim2p.virt +
7770 offsetof(struct lpfc_sli2_slim, IOCBs));
7771
7772 phba->hbqslimp.virt = dma_alloc_coherent(&pdev->dev,
7773 lpfc_sli_hbq_size(),
7774 &phba->hbqslimp.phys,
7775 GFP_KERNEL);
7776 if (!phba->hbqslimp.virt)
7777 goto out_free_slim;
7778
7779 hbq_count = lpfc_sli_hbq_count();
7780 ptr = phba->hbqslimp.virt;
7781 for (i = 0; i < hbq_count; ++i) {
7782 phba->hbqs[i].hbq_virt = ptr;
7783 INIT_LIST_HEAD(&phba->hbqs[i].hbq_buffer_list);
7784 ptr += (lpfc_hbq_defs[i]->entry_count *
7785 sizeof(struct lpfc_hbq_entry));
7786 }
7787 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_els_hbq_alloc;
7788 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_els_hbq_free;
7789
7790 memset(phba->hbqslimp.virt, 0, lpfc_sli_hbq_size());
7791
3772a991
JS
7792 phba->MBslimaddr = phba->slim_memmap_p;
7793 phba->HAregaddr = phba->ctrl_regs_memmap_p + HA_REG_OFFSET;
7794 phba->CAregaddr = phba->ctrl_regs_memmap_p + CA_REG_OFFSET;
7795 phba->HSregaddr = phba->ctrl_regs_memmap_p + HS_REG_OFFSET;
7796 phba->HCregaddr = phba->ctrl_regs_memmap_p + HC_REG_OFFSET;
7797
7798 return 0;
7799
7800out_free_slim:
7801 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7802 phba->slim2p.virt, phba->slim2p.phys);
7803out_iounmap:
7804 iounmap(phba->ctrl_regs_memmap_p);
7805out_iounmap_slim:
7806 iounmap(phba->slim_memmap_p);
7807out:
7808 return error;
7809}
7810
7811/**
7812 * lpfc_sli_pci_mem_unset - Unset SLI3 HBA PCI memory space.
7813 * @phba: pointer to lpfc hba data structure.
7814 *
7815 * This routine is invoked to unset the PCI device memory space for device
7816 * with SLI-3 interface spec.
7817 **/
7818static void
7819lpfc_sli_pci_mem_unset(struct lpfc_hba *phba)
7820{
7821 struct pci_dev *pdev;
7822
7823 /* Obtain PCI device reference */
7824 if (!phba->pcidev)
7825 return;
7826 else
7827 pdev = phba->pcidev;
7828
7829 /* Free coherent DMA memory allocated */
7830 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
7831 phba->hbqslimp.virt, phba->hbqslimp.phys);
7832 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7833 phba->slim2p.virt, phba->slim2p.phys);
7834
7835 /* I/O memory unmap */
7836 iounmap(phba->ctrl_regs_memmap_p);
7837 iounmap(phba->slim_memmap_p);
7838
7839 return;
7840}
7841
7842/**
da0436e9 7843 * lpfc_sli4_post_status_check - Wait for SLI4 POST done and check status
3772a991
JS
7844 * @phba: pointer to lpfc hba data structure.
7845 *
da0436e9
JS
7846 * This routine is invoked to wait for SLI4 device Power On Self Test (POST)
7847 * done and check status.
3772a991 7848 *
da0436e9 7849 * Return 0 if successful, otherwise -ENODEV.
3772a991 7850 **/
da0436e9
JS
7851int
7852lpfc_sli4_post_status_check(struct lpfc_hba *phba)
3772a991 7853{
2fcee4bf
JS
7854 struct lpfc_register portsmphr_reg, uerrlo_reg, uerrhi_reg;
7855 struct lpfc_register reg_data;
7856 int i, port_error = 0;
7857 uint32_t if_type;
3772a991 7858
9940b97b
JS
7859 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
7860 memset(&reg_data, 0, sizeof(reg_data));
2fcee4bf 7861 if (!phba->sli4_hba.PSMPHRregaddr)
da0436e9 7862 return -ENODEV;
3772a991 7863
da0436e9
JS
7864 /* Wait up to 30 seconds for the SLI Port POST done and ready */
7865 for (i = 0; i < 3000; i++) {
9940b97b
JS
7866 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
7867 &portsmphr_reg.word0) ||
7868 (bf_get(lpfc_port_smphr_perr, &portsmphr_reg))) {
2fcee4bf 7869 /* Port has a fatal POST error, break out */
da0436e9
JS
7870 port_error = -ENODEV;
7871 break;
7872 }
2fcee4bf
JS
7873 if (LPFC_POST_STAGE_PORT_READY ==
7874 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg))
da0436e9 7875 break;
da0436e9 7876 msleep(10);
3772a991
JS
7877 }
7878
2fcee4bf
JS
7879 /*
7880 * If there was a port error during POST, then don't proceed with
7881 * other register reads as the data may not be valid. Just exit.
7882 */
7883 if (port_error) {
da0436e9 7884 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2fcee4bf
JS
7885 "1408 Port Failed POST - portsmphr=0x%x, "
7886 "perr=x%x, sfi=x%x, nip=x%x, ipc=x%x, scr1=x%x, "
7887 "scr2=x%x, hscratch=x%x, pstatus=x%x\n",
7888 portsmphr_reg.word0,
7889 bf_get(lpfc_port_smphr_perr, &portsmphr_reg),
7890 bf_get(lpfc_port_smphr_sfi, &portsmphr_reg),
7891 bf_get(lpfc_port_smphr_nip, &portsmphr_reg),
7892 bf_get(lpfc_port_smphr_ipc, &portsmphr_reg),
7893 bf_get(lpfc_port_smphr_scr1, &portsmphr_reg),
7894 bf_get(lpfc_port_smphr_scr2, &portsmphr_reg),
7895 bf_get(lpfc_port_smphr_host_scratch, &portsmphr_reg),
7896 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg));
7897 } else {
28baac74 7898 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
2fcee4bf
JS
7899 "2534 Device Info: SLIFamily=0x%x, "
7900 "SLIRev=0x%x, IFType=0x%x, SLIHint_1=0x%x, "
7901 "SLIHint_2=0x%x, FT=0x%x\n",
28baac74
JS
7902 bf_get(lpfc_sli_intf_sli_family,
7903 &phba->sli4_hba.sli_intf),
7904 bf_get(lpfc_sli_intf_slirev,
7905 &phba->sli4_hba.sli_intf),
085c647c
JS
7906 bf_get(lpfc_sli_intf_if_type,
7907 &phba->sli4_hba.sli_intf),
7908 bf_get(lpfc_sli_intf_sli_hint1,
28baac74 7909 &phba->sli4_hba.sli_intf),
085c647c
JS
7910 bf_get(lpfc_sli_intf_sli_hint2,
7911 &phba->sli4_hba.sli_intf),
7912 bf_get(lpfc_sli_intf_func_type,
28baac74 7913 &phba->sli4_hba.sli_intf));
2fcee4bf
JS
7914 /*
7915 * Check for other Port errors during the initialization
7916 * process. Fail the load if the port did not come up
7917 * correctly.
7918 */
7919 if_type = bf_get(lpfc_sli_intf_if_type,
7920 &phba->sli4_hba.sli_intf);
7921 switch (if_type) {
7922 case LPFC_SLI_INTF_IF_TYPE_0:
7923 phba->sli4_hba.ue_mask_lo =
7924 readl(phba->sli4_hba.u.if_type0.UEMASKLOregaddr);
7925 phba->sli4_hba.ue_mask_hi =
7926 readl(phba->sli4_hba.u.if_type0.UEMASKHIregaddr);
7927 uerrlo_reg.word0 =
7928 readl(phba->sli4_hba.u.if_type0.UERRLOregaddr);
7929 uerrhi_reg.word0 =
7930 readl(phba->sli4_hba.u.if_type0.UERRHIregaddr);
7931 if ((~phba->sli4_hba.ue_mask_lo & uerrlo_reg.word0) ||
7932 (~phba->sli4_hba.ue_mask_hi & uerrhi_reg.word0)) {
7933 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7934 "1422 Unrecoverable Error "
7935 "Detected during POST "
7936 "uerr_lo_reg=0x%x, "
7937 "uerr_hi_reg=0x%x, "
7938 "ue_mask_lo_reg=0x%x, "
7939 "ue_mask_hi_reg=0x%x\n",
7940 uerrlo_reg.word0,
7941 uerrhi_reg.word0,
7942 phba->sli4_hba.ue_mask_lo,
7943 phba->sli4_hba.ue_mask_hi);
7944 port_error = -ENODEV;
7945 }
7946 break;
7947 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 7948 case LPFC_SLI_INTF_IF_TYPE_6:
2fcee4bf 7949 /* Final checks. The port status should be clean. */
9940b97b
JS
7950 if (lpfc_readl(phba->sli4_hba.u.if_type2.STATUSregaddr,
7951 &reg_data.word0) ||
0558056c
JS
7952 (bf_get(lpfc_sliport_status_err, &reg_data) &&
7953 !bf_get(lpfc_sliport_status_rn, &reg_data))) {
2fcee4bf
JS
7954 phba->work_status[0] =
7955 readl(phba->sli4_hba.u.if_type2.
7956 ERR1regaddr);
7957 phba->work_status[1] =
7958 readl(phba->sli4_hba.u.if_type2.
7959 ERR2regaddr);
7960 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8fcb8acd
JS
7961 "2888 Unrecoverable port error "
7962 "following POST: port status reg "
7963 "0x%x, port_smphr reg 0x%x, "
2fcee4bf
JS
7964 "error 1=0x%x, error 2=0x%x\n",
7965 reg_data.word0,
7966 portsmphr_reg.word0,
7967 phba->work_status[0],
7968 phba->work_status[1]);
7969 port_error = -ENODEV;
7970 }
7971 break;
7972 case LPFC_SLI_INTF_IF_TYPE_1:
7973 default:
7974 break;
7975 }
28baac74 7976 }
da0436e9
JS
7977 return port_error;
7978}
3772a991 7979
da0436e9
JS
7980/**
7981 * lpfc_sli4_bar0_register_memmap - Set up SLI4 BAR0 register memory map.
7982 * @phba: pointer to lpfc hba data structure.
2fcee4bf 7983 * @if_type: The SLI4 interface type getting configured.
da0436e9
JS
7984 *
7985 * This routine is invoked to set up SLI4 BAR0 PCI config space register
7986 * memory map.
7987 **/
7988static void
2fcee4bf
JS
7989lpfc_sli4_bar0_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
7990{
7991 switch (if_type) {
7992 case LPFC_SLI_INTF_IF_TYPE_0:
7993 phba->sli4_hba.u.if_type0.UERRLOregaddr =
7994 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_LO;
7995 phba->sli4_hba.u.if_type0.UERRHIregaddr =
7996 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_HI;
7997 phba->sli4_hba.u.if_type0.UEMASKLOregaddr =
7998 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_LO;
7999 phba->sli4_hba.u.if_type0.UEMASKHIregaddr =
8000 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_HI;
8001 phba->sli4_hba.SLIINTFregaddr =
8002 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
8003 break;
8004 case LPFC_SLI_INTF_IF_TYPE_2:
0cf07f84
JS
8005 phba->sli4_hba.u.if_type2.EQDregaddr =
8006 phba->sli4_hba.conf_regs_memmap_p +
8007 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
2fcee4bf 8008 phba->sli4_hba.u.if_type2.ERR1regaddr =
88a2cfbb
JS
8009 phba->sli4_hba.conf_regs_memmap_p +
8010 LPFC_CTL_PORT_ER1_OFFSET;
2fcee4bf 8011 phba->sli4_hba.u.if_type2.ERR2regaddr =
88a2cfbb
JS
8012 phba->sli4_hba.conf_regs_memmap_p +
8013 LPFC_CTL_PORT_ER2_OFFSET;
2fcee4bf 8014 phba->sli4_hba.u.if_type2.CTRLregaddr =
88a2cfbb
JS
8015 phba->sli4_hba.conf_regs_memmap_p +
8016 LPFC_CTL_PORT_CTL_OFFSET;
2fcee4bf 8017 phba->sli4_hba.u.if_type2.STATUSregaddr =
88a2cfbb
JS
8018 phba->sli4_hba.conf_regs_memmap_p +
8019 LPFC_CTL_PORT_STA_OFFSET;
2fcee4bf
JS
8020 phba->sli4_hba.SLIINTFregaddr =
8021 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
8022 phba->sli4_hba.PSMPHRregaddr =
88a2cfbb
JS
8023 phba->sli4_hba.conf_regs_memmap_p +
8024 LPFC_CTL_PORT_SEM_OFFSET;
2fcee4bf 8025 phba->sli4_hba.RQDBregaddr =
962bc51b
JS
8026 phba->sli4_hba.conf_regs_memmap_p +
8027 LPFC_ULP0_RQ_DOORBELL;
2fcee4bf 8028 phba->sli4_hba.WQDBregaddr =
962bc51b
JS
8029 phba->sli4_hba.conf_regs_memmap_p +
8030 LPFC_ULP0_WQ_DOORBELL;
9dd35425 8031 phba->sli4_hba.CQDBregaddr =
2fcee4bf 8032 phba->sli4_hba.conf_regs_memmap_p + LPFC_EQCQ_DOORBELL;
9dd35425 8033 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
2fcee4bf
JS
8034 phba->sli4_hba.MQDBregaddr =
8035 phba->sli4_hba.conf_regs_memmap_p + LPFC_MQ_DOORBELL;
8036 phba->sli4_hba.BMBXregaddr =
8037 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
8038 break;
27d6ac0a
JS
8039 case LPFC_SLI_INTF_IF_TYPE_6:
8040 phba->sli4_hba.u.if_type2.EQDregaddr =
8041 phba->sli4_hba.conf_regs_memmap_p +
8042 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
8043 phba->sli4_hba.u.if_type2.ERR1regaddr =
8044 phba->sli4_hba.conf_regs_memmap_p +
8045 LPFC_CTL_PORT_ER1_OFFSET;
8046 phba->sli4_hba.u.if_type2.ERR2regaddr =
8047 phba->sli4_hba.conf_regs_memmap_p +
8048 LPFC_CTL_PORT_ER2_OFFSET;
8049 phba->sli4_hba.u.if_type2.CTRLregaddr =
8050 phba->sli4_hba.conf_regs_memmap_p +
8051 LPFC_CTL_PORT_CTL_OFFSET;
8052 phba->sli4_hba.u.if_type2.STATUSregaddr =
8053 phba->sli4_hba.conf_regs_memmap_p +
8054 LPFC_CTL_PORT_STA_OFFSET;
8055 phba->sli4_hba.PSMPHRregaddr =
8056 phba->sli4_hba.conf_regs_memmap_p +
8057 LPFC_CTL_PORT_SEM_OFFSET;
8058 phba->sli4_hba.BMBXregaddr =
8059 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
8060 break;
2fcee4bf
JS
8061 case LPFC_SLI_INTF_IF_TYPE_1:
8062 default:
8063 dev_printk(KERN_ERR, &phba->pcidev->dev,
8064 "FATAL - unsupported SLI4 interface type - %d\n",
8065 if_type);
8066 break;
8067 }
da0436e9 8068}
3772a991 8069
da0436e9
JS
8070/**
8071 * lpfc_sli4_bar1_register_memmap - Set up SLI4 BAR1 register memory map.
8072 * @phba: pointer to lpfc hba data structure.
8073 *
27d6ac0a 8074 * This routine is invoked to set up SLI4 BAR1 register memory map.
da0436e9
JS
8075 **/
8076static void
27d6ac0a 8077lpfc_sli4_bar1_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
da0436e9 8078{
27d6ac0a
JS
8079 switch (if_type) {
8080 case LPFC_SLI_INTF_IF_TYPE_0:
8081 phba->sli4_hba.PSMPHRregaddr =
8082 phba->sli4_hba.ctrl_regs_memmap_p +
8083 LPFC_SLIPORT_IF0_SMPHR;
8084 phba->sli4_hba.ISRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8085 LPFC_HST_ISR0;
8086 phba->sli4_hba.IMRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8087 LPFC_HST_IMR0;
8088 phba->sli4_hba.ISCRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8089 LPFC_HST_ISCR0;
8090 break;
8091 case LPFC_SLI_INTF_IF_TYPE_6:
8092 phba->sli4_hba.RQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8093 LPFC_IF6_RQ_DOORBELL;
8094 phba->sli4_hba.WQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8095 LPFC_IF6_WQ_DOORBELL;
8096 phba->sli4_hba.CQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8097 LPFC_IF6_CQ_DOORBELL;
8098 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8099 LPFC_IF6_EQ_DOORBELL;
8100 phba->sli4_hba.MQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8101 LPFC_IF6_MQ_DOORBELL;
8102 break;
8103 case LPFC_SLI_INTF_IF_TYPE_2:
8104 case LPFC_SLI_INTF_IF_TYPE_1:
8105 default:
8106 dev_err(&phba->pcidev->dev,
8107 "FATAL - unsupported SLI4 interface type - %d\n",
8108 if_type);
8109 break;
8110 }
3772a991
JS
8111}
8112
8113/**
da0436e9 8114 * lpfc_sli4_bar2_register_memmap - Set up SLI4 BAR2 register memory map.
3772a991 8115 * @phba: pointer to lpfc hba data structure.
da0436e9 8116 * @vf: virtual function number
3772a991 8117 *
da0436e9
JS
8118 * This routine is invoked to set up SLI4 BAR2 doorbell register memory map
8119 * based on the given viftual function number, @vf.
8120 *
8121 * Return 0 if successful, otherwise -ENODEV.
3772a991 8122 **/
da0436e9
JS
8123static int
8124lpfc_sli4_bar2_register_memmap(struct lpfc_hba *phba, uint32_t vf)
3772a991 8125{
da0436e9
JS
8126 if (vf > LPFC_VIR_FUNC_MAX)
8127 return -ENODEV;
3772a991 8128
da0436e9 8129 phba->sli4_hba.RQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
962bc51b
JS
8130 vf * LPFC_VFR_PAGE_SIZE +
8131 LPFC_ULP0_RQ_DOORBELL);
da0436e9 8132 phba->sli4_hba.WQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
962bc51b
JS
8133 vf * LPFC_VFR_PAGE_SIZE +
8134 LPFC_ULP0_WQ_DOORBELL);
9dd35425
JS
8135 phba->sli4_hba.CQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8136 vf * LPFC_VFR_PAGE_SIZE +
8137 LPFC_EQCQ_DOORBELL);
8138 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
da0436e9
JS
8139 phba->sli4_hba.MQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8140 vf * LPFC_VFR_PAGE_SIZE + LPFC_MQ_DOORBELL);
8141 phba->sli4_hba.BMBXregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8142 vf * LPFC_VFR_PAGE_SIZE + LPFC_BMBX);
8143 return 0;
3772a991
JS
8144}
8145
8146/**
da0436e9 8147 * lpfc_create_bootstrap_mbox - Create the bootstrap mailbox
3772a991
JS
8148 * @phba: pointer to lpfc hba data structure.
8149 *
da0436e9
JS
8150 * This routine is invoked to create the bootstrap mailbox
8151 * region consistent with the SLI-4 interface spec. This
8152 * routine allocates all memory necessary to communicate
8153 * mailbox commands to the port and sets up all alignment
8154 * needs. No locks are expected to be held when calling
8155 * this routine.
3772a991
JS
8156 *
8157 * Return codes
af901ca1 8158 * 0 - successful
d439d286 8159 * -ENOMEM - could not allocated memory.
da0436e9 8160 **/
3772a991 8161static int
da0436e9 8162lpfc_create_bootstrap_mbox(struct lpfc_hba *phba)
3772a991 8163{
da0436e9
JS
8164 uint32_t bmbx_size;
8165 struct lpfc_dmabuf *dmabuf;
8166 struct dma_address *dma_address;
8167 uint32_t pa_addr;
8168 uint64_t phys_addr;
8169
8170 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
8171 if (!dmabuf)
8172 return -ENOMEM;
3772a991 8173
da0436e9
JS
8174 /*
8175 * The bootstrap mailbox region is comprised of 2 parts
8176 * plus an alignment restriction of 16 bytes.
8177 */
8178 bmbx_size = sizeof(struct lpfc_bmbx_create) + (LPFC_ALIGN_16_BYTE - 1);
750afb08
LC
8179 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev, bmbx_size,
8180 &dmabuf->phys, GFP_KERNEL);
da0436e9
JS
8181 if (!dmabuf->virt) {
8182 kfree(dmabuf);
8183 return -ENOMEM;
3772a991
JS
8184 }
8185
da0436e9
JS
8186 /*
8187 * Initialize the bootstrap mailbox pointers now so that the register
8188 * operations are simple later. The mailbox dma address is required
8189 * to be 16-byte aligned. Also align the virtual memory as each
8190 * maibox is copied into the bmbx mailbox region before issuing the
8191 * command to the port.
8192 */
8193 phba->sli4_hba.bmbx.dmabuf = dmabuf;
8194 phba->sli4_hba.bmbx.bmbx_size = bmbx_size;
8195
8196 phba->sli4_hba.bmbx.avirt = PTR_ALIGN(dmabuf->virt,
8197 LPFC_ALIGN_16_BYTE);
8198 phba->sli4_hba.bmbx.aphys = ALIGN(dmabuf->phys,
8199 LPFC_ALIGN_16_BYTE);
8200
8201 /*
8202 * Set the high and low physical addresses now. The SLI4 alignment
8203 * requirement is 16 bytes and the mailbox is posted to the port
8204 * as two 30-bit addresses. The other data is a bit marking whether
8205 * the 30-bit address is the high or low address.
8206 * Upcast bmbx aphys to 64bits so shift instruction compiles
8207 * clean on 32 bit machines.
8208 */
8209 dma_address = &phba->sli4_hba.bmbx.dma_address;
8210 phys_addr = (uint64_t)phba->sli4_hba.bmbx.aphys;
8211 pa_addr = (uint32_t) ((phys_addr >> 34) & 0x3fffffff);
8212 dma_address->addr_hi = (uint32_t) ((pa_addr << 2) |
8213 LPFC_BMBX_BIT1_ADDR_HI);
8214
8215 pa_addr = (uint32_t) ((phba->sli4_hba.bmbx.aphys >> 4) & 0x3fffffff);
8216 dma_address->addr_lo = (uint32_t) ((pa_addr << 2) |
8217 LPFC_BMBX_BIT1_ADDR_LO);
8218 return 0;
3772a991
JS
8219}
8220
8221/**
da0436e9 8222 * lpfc_destroy_bootstrap_mbox - Destroy all bootstrap mailbox resources
3772a991
JS
8223 * @phba: pointer to lpfc hba data structure.
8224 *
da0436e9
JS
8225 * This routine is invoked to teardown the bootstrap mailbox
8226 * region and release all host resources. This routine requires
8227 * the caller to ensure all mailbox commands recovered, no
8228 * additional mailbox comands are sent, and interrupts are disabled
8229 * before calling this routine.
8230 *
8231 **/
3772a991 8232static void
da0436e9 8233lpfc_destroy_bootstrap_mbox(struct lpfc_hba *phba)
3772a991 8234{
da0436e9
JS
8235 dma_free_coherent(&phba->pcidev->dev,
8236 phba->sli4_hba.bmbx.bmbx_size,
8237 phba->sli4_hba.bmbx.dmabuf->virt,
8238 phba->sli4_hba.bmbx.dmabuf->phys);
8239
8240 kfree(phba->sli4_hba.bmbx.dmabuf);
8241 memset(&phba->sli4_hba.bmbx, 0, sizeof(struct lpfc_bmbx));
3772a991
JS
8242}
8243
8244/**
da0436e9 8245 * lpfc_sli4_read_config - Get the config parameters.
3772a991
JS
8246 * @phba: pointer to lpfc hba data structure.
8247 *
da0436e9
JS
8248 * This routine is invoked to read the configuration parameters from the HBA.
8249 * The configuration parameters are used to set the base and maximum values
8250 * for RPI's XRI's VPI's VFI's and FCFIs. These values also affect the resource
8251 * allocation for the port.
3772a991
JS
8252 *
8253 * Return codes
af901ca1 8254 * 0 - successful
25985edc 8255 * -ENOMEM - No available memory
d439d286 8256 * -EIO - The mailbox failed to complete successfully.
3772a991 8257 **/
ff78d8f9 8258int
da0436e9 8259lpfc_sli4_read_config(struct lpfc_hba *phba)
3772a991 8260{
da0436e9
JS
8261 LPFC_MBOXQ_t *pmb;
8262 struct lpfc_mbx_read_config *rd_config;
912e3acd
JS
8263 union lpfc_sli4_cfg_shdr *shdr;
8264 uint32_t shdr_status, shdr_add_status;
8265 struct lpfc_mbx_get_func_cfg *get_func_cfg;
8266 struct lpfc_rsrc_desc_fcfcoe *desc;
8aa134a8 8267 char *pdesc_0;
c691816e 8268 uint16_t forced_link_speed;
6a828b0f 8269 uint32_t if_type, qmin;
8aa134a8 8270 int length, i, rc = 0, rc2;
3772a991 8271
da0436e9
JS
8272 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
8273 if (!pmb) {
8274 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8275 "2011 Unable to allocate memory for issuing "
8276 "SLI_CONFIG_SPECIAL mailbox command\n");
8277 return -ENOMEM;
3772a991
JS
8278 }
8279
da0436e9 8280 lpfc_read_config(phba, pmb);
3772a991 8281
da0436e9
JS
8282 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
8283 if (rc != MBX_SUCCESS) {
8284 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8285 "2012 Mailbox failed , mbxCmd x%x "
8286 "READ_CONFIG, mbxStatus x%x\n",
8287 bf_get(lpfc_mqe_command, &pmb->u.mqe),
8288 bf_get(lpfc_mqe_status, &pmb->u.mqe));
8289 rc = -EIO;
8290 } else {
8291 rd_config = &pmb->u.mqe.un.rd_config;
ff78d8f9
JS
8292 if (bf_get(lpfc_mbx_rd_conf_lnk_ldv, rd_config)) {
8293 phba->sli4_hba.lnk_info.lnk_dv = LPFC_LNK_DAT_VAL;
8294 phba->sli4_hba.lnk_info.lnk_tp =
8295 bf_get(lpfc_mbx_rd_conf_lnk_type, rd_config);
8296 phba->sli4_hba.lnk_info.lnk_no =
8297 bf_get(lpfc_mbx_rd_conf_lnk_numb, rd_config);
8298 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8299 "3081 lnk_type:%d, lnk_numb:%d\n",
8300 phba->sli4_hba.lnk_info.lnk_tp,
8301 phba->sli4_hba.lnk_info.lnk_no);
8302 } else
8303 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
8304 "3082 Mailbox (x%x) returned ldv:x0\n",
8305 bf_get(lpfc_mqe_command, &pmb->u.mqe));
44fd7fe3
JS
8306 if (bf_get(lpfc_mbx_rd_conf_bbscn_def, rd_config)) {
8307 phba->bbcredit_support = 1;
8308 phba->sli4_hba.bbscn_params.word0 = rd_config->word8;
8309 }
8310
1dc5ec24
JS
8311 phba->sli4_hba.conf_trunk =
8312 bf_get(lpfc_mbx_rd_conf_trunk, rd_config);
6d368e53
JS
8313 phba->sli4_hba.extents_in_use =
8314 bf_get(lpfc_mbx_rd_conf_extnts_inuse, rd_config);
da0436e9
JS
8315 phba->sli4_hba.max_cfg_param.max_xri =
8316 bf_get(lpfc_mbx_rd_conf_xri_count, rd_config);
31f06d2e
JS
8317 /* Reduce resource usage in kdump environment */
8318 if (is_kdump_kernel() &&
8319 phba->sli4_hba.max_cfg_param.max_xri > 512)
8320 phba->sli4_hba.max_cfg_param.max_xri = 512;
da0436e9
JS
8321 phba->sli4_hba.max_cfg_param.xri_base =
8322 bf_get(lpfc_mbx_rd_conf_xri_base, rd_config);
8323 phba->sli4_hba.max_cfg_param.max_vpi =
8324 bf_get(lpfc_mbx_rd_conf_vpi_count, rd_config);
8b47ae69
JS
8325 /* Limit the max we support */
8326 if (phba->sli4_hba.max_cfg_param.max_vpi > LPFC_MAX_VPORTS)
8327 phba->sli4_hba.max_cfg_param.max_vpi = LPFC_MAX_VPORTS;
da0436e9
JS
8328 phba->sli4_hba.max_cfg_param.vpi_base =
8329 bf_get(lpfc_mbx_rd_conf_vpi_base, rd_config);
8330 phba->sli4_hba.max_cfg_param.max_rpi =
8331 bf_get(lpfc_mbx_rd_conf_rpi_count, rd_config);
8332 phba->sli4_hba.max_cfg_param.rpi_base =
8333 bf_get(lpfc_mbx_rd_conf_rpi_base, rd_config);
8334 phba->sli4_hba.max_cfg_param.max_vfi =
8335 bf_get(lpfc_mbx_rd_conf_vfi_count, rd_config);
8336 phba->sli4_hba.max_cfg_param.vfi_base =
8337 bf_get(lpfc_mbx_rd_conf_vfi_base, rd_config);
8338 phba->sli4_hba.max_cfg_param.max_fcfi =
8339 bf_get(lpfc_mbx_rd_conf_fcfi_count, rd_config);
da0436e9
JS
8340 phba->sli4_hba.max_cfg_param.max_eq =
8341 bf_get(lpfc_mbx_rd_conf_eq_count, rd_config);
8342 phba->sli4_hba.max_cfg_param.max_rq =
8343 bf_get(lpfc_mbx_rd_conf_rq_count, rd_config);
8344 phba->sli4_hba.max_cfg_param.max_wq =
8345 bf_get(lpfc_mbx_rd_conf_wq_count, rd_config);
8346 phba->sli4_hba.max_cfg_param.max_cq =
8347 bf_get(lpfc_mbx_rd_conf_cq_count, rd_config);
8348 phba->lmt = bf_get(lpfc_mbx_rd_conf_lmt, rd_config);
8349 phba->sli4_hba.next_xri = phba->sli4_hba.max_cfg_param.xri_base;
8350 phba->vpi_base = phba->sli4_hba.max_cfg_param.vpi_base;
8351 phba->vfi_base = phba->sli4_hba.max_cfg_param.vfi_base;
5ffc266e
JS
8352 phba->max_vpi = (phba->sli4_hba.max_cfg_param.max_vpi > 0) ?
8353 (phba->sli4_hba.max_cfg_param.max_vpi - 1) : 0;
da0436e9
JS
8354 phba->max_vports = phba->max_vpi;
8355 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6d368e53
JS
8356 "2003 cfg params Extents? %d "
8357 "XRI(B:%d M:%d), "
da0436e9
JS
8358 "VPI(B:%d M:%d) "
8359 "VFI(B:%d M:%d) "
8360 "RPI(B:%d M:%d) "
2ea259ee 8361 "FCFI:%d EQ:%d CQ:%d WQ:%d RQ:%d\n",
6d368e53 8362 phba->sli4_hba.extents_in_use,
da0436e9
JS
8363 phba->sli4_hba.max_cfg_param.xri_base,
8364 phba->sli4_hba.max_cfg_param.max_xri,
8365 phba->sli4_hba.max_cfg_param.vpi_base,
8366 phba->sli4_hba.max_cfg_param.max_vpi,
8367 phba->sli4_hba.max_cfg_param.vfi_base,
8368 phba->sli4_hba.max_cfg_param.max_vfi,
8369 phba->sli4_hba.max_cfg_param.rpi_base,
8370 phba->sli4_hba.max_cfg_param.max_rpi,
2ea259ee
JS
8371 phba->sli4_hba.max_cfg_param.max_fcfi,
8372 phba->sli4_hba.max_cfg_param.max_eq,
8373 phba->sli4_hba.max_cfg_param.max_cq,
8374 phba->sli4_hba.max_cfg_param.max_wq,
8375 phba->sli4_hba.max_cfg_param.max_rq);
8376
d38f33b3 8377 /*
6a828b0f
JS
8378 * Calculate queue resources based on how
8379 * many WQ/CQ/EQs are available.
d38f33b3 8380 */
6a828b0f
JS
8381 qmin = phba->sli4_hba.max_cfg_param.max_wq;
8382 if (phba->sli4_hba.max_cfg_param.max_cq < qmin)
8383 qmin = phba->sli4_hba.max_cfg_param.max_cq;
8384 if (phba->sli4_hba.max_cfg_param.max_eq < qmin)
8385 qmin = phba->sli4_hba.max_cfg_param.max_eq;
8386 /*
8387 * Whats left after this can go toward NVME / FCP.
8388 * The minus 4 accounts for ELS, NVME LS, MBOX
8389 * plus one extra. When configured for
8390 * NVMET, FCP io channel WQs are not created.
8391 */
8392 qmin -= 4;
d38f33b3 8393
6a828b0f
JS
8394 /* Check to see if there is enough for NVME */
8395 if ((phba->cfg_irq_chann > qmin) ||
8396 (phba->cfg_hdw_queue > qmin)) {
8397 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8398 "2005 Reducing Queues: "
8399 "WQ %d CQ %d EQ %d: min %d: "
8400 "IRQ %d HDWQ %d\n",
d38f33b3
JS
8401 phba->sli4_hba.max_cfg_param.max_wq,
8402 phba->sli4_hba.max_cfg_param.max_cq,
6a828b0f
JS
8403 phba->sli4_hba.max_cfg_param.max_eq,
8404 qmin, phba->cfg_irq_chann,
cdb42bec 8405 phba->cfg_hdw_queue);
d38f33b3 8406
6a828b0f
JS
8407 if (phba->cfg_irq_chann > qmin)
8408 phba->cfg_irq_chann = qmin;
8409 if (phba->cfg_hdw_queue > qmin)
8410 phba->cfg_hdw_queue = qmin;
d38f33b3 8411 }
3772a991 8412 }
912e3acd
JS
8413
8414 if (rc)
8415 goto read_cfg_out;
da0436e9 8416
c691816e
JS
8417 /* Update link speed if forced link speed is supported */
8418 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
27d6ac0a 8419 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
c691816e
JS
8420 forced_link_speed =
8421 bf_get(lpfc_mbx_rd_conf_link_speed, rd_config);
8422 if (forced_link_speed) {
8423 phba->hba_flag |= HBA_FORCED_LINK_SPEED;
8424
8425 switch (forced_link_speed) {
8426 case LINK_SPEED_1G:
8427 phba->cfg_link_speed =
8428 LPFC_USER_LINK_SPEED_1G;
8429 break;
8430 case LINK_SPEED_2G:
8431 phba->cfg_link_speed =
8432 LPFC_USER_LINK_SPEED_2G;
8433 break;
8434 case LINK_SPEED_4G:
8435 phba->cfg_link_speed =
8436 LPFC_USER_LINK_SPEED_4G;
8437 break;
8438 case LINK_SPEED_8G:
8439 phba->cfg_link_speed =
8440 LPFC_USER_LINK_SPEED_8G;
8441 break;
8442 case LINK_SPEED_10G:
8443 phba->cfg_link_speed =
8444 LPFC_USER_LINK_SPEED_10G;
8445 break;
8446 case LINK_SPEED_16G:
8447 phba->cfg_link_speed =
8448 LPFC_USER_LINK_SPEED_16G;
8449 break;
8450 case LINK_SPEED_32G:
8451 phba->cfg_link_speed =
8452 LPFC_USER_LINK_SPEED_32G;
8453 break;
fbd8a6ba
JS
8454 case LINK_SPEED_64G:
8455 phba->cfg_link_speed =
8456 LPFC_USER_LINK_SPEED_64G;
8457 break;
c691816e
JS
8458 case 0xffff:
8459 phba->cfg_link_speed =
8460 LPFC_USER_LINK_SPEED_AUTO;
8461 break;
8462 default:
8463 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8464 "0047 Unrecognized link "
8465 "speed : %d\n",
8466 forced_link_speed);
8467 phba->cfg_link_speed =
8468 LPFC_USER_LINK_SPEED_AUTO;
8469 }
8470 }
8471 }
8472
da0436e9 8473 /* Reset the DFT_HBA_Q_DEPTH to the max xri */
572709e2
JS
8474 length = phba->sli4_hba.max_cfg_param.max_xri -
8475 lpfc_sli4_get_els_iocb_cnt(phba);
8476 if (phba->cfg_hba_queue_depth > length) {
8477 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8478 "3361 HBA queue depth changed from %d to %d\n",
8479 phba->cfg_hba_queue_depth, length);
8480 phba->cfg_hba_queue_depth = length;
8481 }
912e3acd 8482
27d6ac0a 8483 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
912e3acd
JS
8484 LPFC_SLI_INTF_IF_TYPE_2)
8485 goto read_cfg_out;
8486
8487 /* get the pf# and vf# for SLI4 if_type 2 port */
8488 length = (sizeof(struct lpfc_mbx_get_func_cfg) -
8489 sizeof(struct lpfc_sli4_cfg_mhdr));
8490 lpfc_sli4_config(phba, pmb, LPFC_MBOX_SUBSYSTEM_COMMON,
8491 LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG,
8492 length, LPFC_SLI4_MBX_EMBED);
8493
8aa134a8 8494 rc2 = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
912e3acd
JS
8495 shdr = (union lpfc_sli4_cfg_shdr *)
8496 &pmb->u.mqe.un.sli4_config.header.cfg_shdr;
8497 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
8498 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
8aa134a8 8499 if (rc2 || shdr_status || shdr_add_status) {
912e3acd
JS
8500 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8501 "3026 Mailbox failed , mbxCmd x%x "
8502 "GET_FUNCTION_CONFIG, mbxStatus x%x\n",
8503 bf_get(lpfc_mqe_command, &pmb->u.mqe),
8504 bf_get(lpfc_mqe_status, &pmb->u.mqe));
912e3acd
JS
8505 goto read_cfg_out;
8506 }
8507
8508 /* search for fc_fcoe resrouce descriptor */
8509 get_func_cfg = &pmb->u.mqe.un.get_func_cfg;
912e3acd 8510
8aa134a8
JS
8511 pdesc_0 = (char *)&get_func_cfg->func_cfg.desc[0];
8512 desc = (struct lpfc_rsrc_desc_fcfcoe *)pdesc_0;
8513 length = bf_get(lpfc_rsrc_desc_fcfcoe_length, desc);
8514 if (length == LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD)
8515 length = LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH;
8516 else if (length != LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH)
8517 goto read_cfg_out;
8518
912e3acd 8519 for (i = 0; i < LPFC_RSRC_DESC_MAX_NUM; i++) {
8aa134a8 8520 desc = (struct lpfc_rsrc_desc_fcfcoe *)(pdesc_0 + length * i);
912e3acd 8521 if (LPFC_RSRC_DESC_TYPE_FCFCOE ==
8aa134a8 8522 bf_get(lpfc_rsrc_desc_fcfcoe_type, desc)) {
912e3acd
JS
8523 phba->sli4_hba.iov.pf_number =
8524 bf_get(lpfc_rsrc_desc_fcfcoe_pfnum, desc);
8525 phba->sli4_hba.iov.vf_number =
8526 bf_get(lpfc_rsrc_desc_fcfcoe_vfnum, desc);
8527 break;
8528 }
8529 }
8530
8531 if (i < LPFC_RSRC_DESC_MAX_NUM)
8532 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8533 "3027 GET_FUNCTION_CONFIG: pf_number:%d, "
8534 "vf_number:%d\n", phba->sli4_hba.iov.pf_number,
8535 phba->sli4_hba.iov.vf_number);
8aa134a8 8536 else
912e3acd
JS
8537 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8538 "3028 GET_FUNCTION_CONFIG: failed to find "
c4dba187 8539 "Resource Descriptor:x%x\n",
912e3acd 8540 LPFC_RSRC_DESC_TYPE_FCFCOE);
912e3acd
JS
8541
8542read_cfg_out:
8543 mempool_free(pmb, phba->mbox_mem_pool);
da0436e9 8544 return rc;
3772a991
JS
8545}
8546
8547/**
2fcee4bf 8548 * lpfc_setup_endian_order - Write endian order to an SLI4 if_type 0 port.
3772a991
JS
8549 * @phba: pointer to lpfc hba data structure.
8550 *
2fcee4bf
JS
8551 * This routine is invoked to setup the port-side endian order when
8552 * the port if_type is 0. This routine has no function for other
8553 * if_types.
da0436e9
JS
8554 *
8555 * Return codes
af901ca1 8556 * 0 - successful
25985edc 8557 * -ENOMEM - No available memory
d439d286 8558 * -EIO - The mailbox failed to complete successfully.
3772a991 8559 **/
da0436e9
JS
8560static int
8561lpfc_setup_endian_order(struct lpfc_hba *phba)
3772a991 8562{
da0436e9 8563 LPFC_MBOXQ_t *mboxq;
2fcee4bf 8564 uint32_t if_type, rc = 0;
da0436e9
JS
8565 uint32_t endian_mb_data[2] = {HOST_ENDIAN_LOW_WORD0,
8566 HOST_ENDIAN_HIGH_WORD1};
3772a991 8567
2fcee4bf
JS
8568 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
8569 switch (if_type) {
8570 case LPFC_SLI_INTF_IF_TYPE_0:
8571 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
8572 GFP_KERNEL);
8573 if (!mboxq) {
8574 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8575 "0492 Unable to allocate memory for "
8576 "issuing SLI_CONFIG_SPECIAL mailbox "
8577 "command\n");
8578 return -ENOMEM;
8579 }
3772a991 8580
2fcee4bf
JS
8581 /*
8582 * The SLI4_CONFIG_SPECIAL mailbox command requires the first
8583 * two words to contain special data values and no other data.
8584 */
8585 memset(mboxq, 0, sizeof(LPFC_MBOXQ_t));
8586 memcpy(&mboxq->u.mqe, &endian_mb_data, sizeof(endian_mb_data));
8587 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
8588 if (rc != MBX_SUCCESS) {
8589 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8590 "0493 SLI_CONFIG_SPECIAL mailbox "
8591 "failed with status x%x\n",
8592 rc);
8593 rc = -EIO;
8594 }
8595 mempool_free(mboxq, phba->mbox_mem_pool);
8596 break;
27d6ac0a 8597 case LPFC_SLI_INTF_IF_TYPE_6:
2fcee4bf
JS
8598 case LPFC_SLI_INTF_IF_TYPE_2:
8599 case LPFC_SLI_INTF_IF_TYPE_1:
8600 default:
8601 break;
da0436e9 8602 }
da0436e9 8603 return rc;
3772a991
JS
8604}
8605
8606/**
895427bd 8607 * lpfc_sli4_queue_verify - Verify and update EQ counts
3772a991
JS
8608 * @phba: pointer to lpfc hba data structure.
8609 *
895427bd
JS
8610 * This routine is invoked to check the user settable queue counts for EQs.
8611 * After this routine is called the counts will be set to valid values that
5350d872
JS
8612 * adhere to the constraints of the system's interrupt vectors and the port's
8613 * queue resources.
da0436e9
JS
8614 *
8615 * Return codes
af901ca1 8616 * 0 - successful
25985edc 8617 * -ENOMEM - No available memory
3772a991 8618 **/
da0436e9 8619static int
5350d872 8620lpfc_sli4_queue_verify(struct lpfc_hba *phba)
3772a991 8621{
da0436e9 8622 /*
67d12733 8623 * Sanity check for configured queue parameters against the run-time
da0436e9
JS
8624 * device parameters
8625 */
3772a991 8626
bcb24f65 8627 if (phba->nvmet_support) {
6a828b0f
JS
8628 if (phba->cfg_irq_chann < phba->cfg_nvmet_mrq)
8629 phba->cfg_nvmet_mrq = phba->cfg_irq_chann;
982ab128
JS
8630 if (phba->cfg_nvmet_mrq > LPFC_NVMET_MRQ_MAX)
8631 phba->cfg_nvmet_mrq = LPFC_NVMET_MRQ_MAX;
bcb24f65 8632 }
895427bd
JS
8633
8634 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6a828b0f
JS
8635 "2574 IO channels: hdwQ %d IRQ %d MRQ: %d\n",
8636 phba->cfg_hdw_queue, phba->cfg_irq_chann,
8637 phba->cfg_nvmet_mrq);
3772a991 8638
da0436e9
JS
8639 /* Get EQ depth from module parameter, fake the default for now */
8640 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
8641 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
3772a991 8642
5350d872
JS
8643 /* Get CQ depth from module parameter, fake the default for now */
8644 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
8645 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
895427bd
JS
8646 return 0;
8647}
8648
8649static int
c00f62e6 8650lpfc_alloc_io_wq_cq(struct lpfc_hba *phba, int idx)
895427bd
JS
8651{
8652 struct lpfc_queue *qdesc;
c00f62e6 8653 u32 wqesize;
c1a21ebc 8654 int cpu;
895427bd 8655
c00f62e6
JS
8656 cpu = lpfc_find_cpu_handle(phba, idx, LPFC_FIND_BY_HDWQ);
8657 /* Create Fast Path IO CQs */
c176ffa0 8658 if (phba->enab_exp_wqcq_pages)
a51e41b6
JS
8659 /* Increase the CQ size when WQEs contain an embedded cdb */
8660 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
8661 phba->sli4_hba.cq_esize,
c1a21ebc 8662 LPFC_CQE_EXP_COUNT, cpu);
a51e41b6
JS
8663
8664 else
8665 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8666 phba->sli4_hba.cq_esize,
c1a21ebc 8667 phba->sli4_hba.cq_ecount, cpu);
895427bd
JS
8668 if (!qdesc) {
8669 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
c00f62e6 8670 "0499 Failed allocate fast-path IO CQ (%d)\n", idx);
895427bd
JS
8671 return 1;
8672 }
7365f6fd 8673 qdesc->qe_valid = 1;
c00f62e6 8674 qdesc->hdwq = idx;
c1a21ebc 8675 qdesc->chann = cpu;
c00f62e6 8676 phba->sli4_hba.hdwq[idx].io_cq = qdesc;
895427bd 8677
c00f62e6 8678 /* Create Fast Path IO WQs */
c176ffa0 8679 if (phba->enab_exp_wqcq_pages) {
a51e41b6 8680 /* Increase the WQ size when WQEs contain an embedded cdb */
c176ffa0
JS
8681 wqesize = (phba->fcp_embed_io) ?
8682 LPFC_WQE128_SIZE : phba->sli4_hba.wq_esize;
a51e41b6 8683 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
c176ffa0 8684 wqesize,
c1a21ebc 8685 LPFC_WQE_EXP_COUNT, cpu);
c176ffa0 8686 } else
a51e41b6
JS
8687 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8688 phba->sli4_hba.wq_esize,
c1a21ebc 8689 phba->sli4_hba.wq_ecount, cpu);
c176ffa0 8690
895427bd
JS
8691 if (!qdesc) {
8692 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
c00f62e6
JS
8693 "0503 Failed allocate fast-path IO WQ (%d)\n",
8694 idx);
895427bd
JS
8695 return 1;
8696 }
c00f62e6
JS
8697 qdesc->hdwq = idx;
8698 qdesc->chann = cpu;
8699 phba->sli4_hba.hdwq[idx].io_wq = qdesc;
895427bd 8700 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
5350d872 8701 return 0;
5350d872
JS
8702}
8703
8704/**
8705 * lpfc_sli4_queue_create - Create all the SLI4 queues
8706 * @phba: pointer to lpfc hba data structure.
8707 *
8708 * This routine is invoked to allocate all the SLI4 queues for the FCoE HBA
8709 * operation. For each SLI4 queue type, the parameters such as queue entry
8710 * count (queue depth) shall be taken from the module parameter. For now,
8711 * we just use some constant number as place holder.
8712 *
8713 * Return codes
4907cb7b 8714 * 0 - successful
5350d872
JS
8715 * -ENOMEM - No availble memory
8716 * -EIO - The mailbox failed to complete successfully.
8717 **/
8718int
8719lpfc_sli4_queue_create(struct lpfc_hba *phba)
8720{
8721 struct lpfc_queue *qdesc;
657add4e 8722 int idx, cpu, eqcpu;
5e5b511d 8723 struct lpfc_sli4_hdw_queue *qp;
657add4e
JS
8724 struct lpfc_vector_map_info *cpup;
8725 struct lpfc_vector_map_info *eqcpup;
32517fc0 8726 struct lpfc_eq_intr_info *eqi;
5350d872
JS
8727
8728 /*
67d12733 8729 * Create HBA Record arrays.
895427bd 8730 * Both NVME and FCP will share that same vectors / EQs
5350d872 8731 */
67d12733
JS
8732 phba->sli4_hba.mq_esize = LPFC_MQE_SIZE;
8733 phba->sli4_hba.mq_ecount = LPFC_MQE_DEF_COUNT;
8734 phba->sli4_hba.wq_esize = LPFC_WQE_SIZE;
8735 phba->sli4_hba.wq_ecount = LPFC_WQE_DEF_COUNT;
8736 phba->sli4_hba.rq_esize = LPFC_RQE_SIZE;
8737 phba->sli4_hba.rq_ecount = LPFC_RQE_DEF_COUNT;
895427bd
JS
8738 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
8739 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
8740 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
8741 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
67d12733 8742
cdb42bec 8743 if (!phba->sli4_hba.hdwq) {
5e5b511d
JS
8744 phba->sli4_hba.hdwq = kcalloc(
8745 phba->cfg_hdw_queue, sizeof(struct lpfc_sli4_hdw_queue),
8746 GFP_KERNEL);
8747 if (!phba->sli4_hba.hdwq) {
895427bd 8748 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5e5b511d
JS
8749 "6427 Failed allocate memory for "
8750 "fast-path Hardware Queue array\n");
895427bd
JS
8751 goto out_error;
8752 }
5e5b511d
JS
8753 /* Prepare hardware queues to take IO buffers */
8754 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
8755 qp = &phba->sli4_hba.hdwq[idx];
8756 spin_lock_init(&qp->io_buf_list_get_lock);
8757 spin_lock_init(&qp->io_buf_list_put_lock);
8758 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
8759 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
8760 qp->get_io_bufs = 0;
8761 qp->put_io_bufs = 0;
8762 qp->total_io_bufs = 0;
c00f62e6
JS
8763 spin_lock_init(&qp->abts_io_buf_list_lock);
8764 INIT_LIST_HEAD(&qp->lpfc_abts_io_buf_list);
5e5b511d 8765 qp->abts_scsi_io_bufs = 0;
5e5b511d 8766 qp->abts_nvme_io_bufs = 0;
d79c9e9d
JS
8767 INIT_LIST_HEAD(&qp->sgl_list);
8768 INIT_LIST_HEAD(&qp->cmd_rsp_buf_list);
8769 spin_lock_init(&qp->hdwq_lock);
895427bd 8770 }
67d12733
JS
8771 }
8772
cdb42bec 8773 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
2d7dbc4c
JS
8774 if (phba->nvmet_support) {
8775 phba->sli4_hba.nvmet_cqset = kcalloc(
8776 phba->cfg_nvmet_mrq,
8777 sizeof(struct lpfc_queue *),
8778 GFP_KERNEL);
8779 if (!phba->sli4_hba.nvmet_cqset) {
8780 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8781 "3121 Fail allocate memory for "
8782 "fast-path CQ set array\n");
8783 goto out_error;
8784 }
8785 phba->sli4_hba.nvmet_mrq_hdr = kcalloc(
8786 phba->cfg_nvmet_mrq,
8787 sizeof(struct lpfc_queue *),
8788 GFP_KERNEL);
8789 if (!phba->sli4_hba.nvmet_mrq_hdr) {
8790 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8791 "3122 Fail allocate memory for "
8792 "fast-path RQ set hdr array\n");
8793 goto out_error;
8794 }
8795 phba->sli4_hba.nvmet_mrq_data = kcalloc(
8796 phba->cfg_nvmet_mrq,
8797 sizeof(struct lpfc_queue *),
8798 GFP_KERNEL);
8799 if (!phba->sli4_hba.nvmet_mrq_data) {
8800 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8801 "3124 Fail allocate memory for "
8802 "fast-path RQ set data array\n");
8803 goto out_error;
8804 }
8805 }
da0436e9 8806 }
67d12733 8807
895427bd 8808 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
67d12733 8809
895427bd 8810 /* Create HBA Event Queues (EQs) */
657add4e
JS
8811 for_each_present_cpu(cpu) {
8812 /* We only want to create 1 EQ per vector, even though
8813 * multiple CPUs might be using that vector. so only
8814 * selects the CPUs that are LPFC_CPU_FIRST_IRQ.
6a828b0f 8815 */
657add4e
JS
8816 cpup = &phba->sli4_hba.cpu_map[cpu];
8817 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
6a828b0f 8818 continue;
657add4e
JS
8819
8820 /* Get a ptr to the Hardware Queue associated with this CPU */
8821 qp = &phba->sli4_hba.hdwq[cpup->hdwq];
8822
8823 /* Allocate an EQ */
81b96eda
JS
8824 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8825 phba->sli4_hba.eq_esize,
c1a21ebc 8826 phba->sli4_hba.eq_ecount, cpu);
da0436e9
JS
8827 if (!qdesc) {
8828 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
657add4e
JS
8829 "0497 Failed allocate EQ (%d)\n",
8830 cpup->hdwq);
67d12733 8831 goto out_error;
da0436e9 8832 }
7365f6fd 8833 qdesc->qe_valid = 1;
657add4e 8834 qdesc->hdwq = cpup->hdwq;
3ad348d9 8835 qdesc->chann = cpu; /* First CPU this EQ is affinitized to */
32517fc0 8836 qdesc->last_cpu = qdesc->chann;
657add4e
JS
8837
8838 /* Save the allocated EQ in the Hardware Queue */
8839 qp->hba_eq = qdesc;
8840
32517fc0
JS
8841 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, qdesc->last_cpu);
8842 list_add(&qdesc->cpu_list, &eqi->list);
895427bd 8843 }
67d12733 8844
657add4e
JS
8845 /* Now we need to populate the other Hardware Queues, that share
8846 * an IRQ vector, with the associated EQ ptr.
8847 */
8848 for_each_present_cpu(cpu) {
8849 cpup = &phba->sli4_hba.cpu_map[cpu];
8850
8851 /* Check for EQ already allocated in previous loop */
8852 if (cpup->flag & LPFC_CPU_FIRST_IRQ)
8853 continue;
8854
8855 /* Check for multiple CPUs per hdwq */
8856 qp = &phba->sli4_hba.hdwq[cpup->hdwq];
8857 if (qp->hba_eq)
8858 continue;
8859
8860 /* We need to share an EQ for this hdwq */
8861 eqcpu = lpfc_find_cpu_handle(phba, cpup->eq, LPFC_FIND_BY_EQ);
8862 eqcpup = &phba->sli4_hba.cpu_map[eqcpu];
8863 qp->hba_eq = phba->sli4_hba.hdwq[eqcpup->hdwq].hba_eq;
8864 }
67d12733 8865
c00f62e6 8866 /* Allocate IO Path SLI4 CQ/WQs */
6a828b0f 8867 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
c00f62e6 8868 if (lpfc_alloc_io_wq_cq(phba, idx))
67d12733 8869 goto out_error;
6a828b0f 8870 }
da0436e9 8871
c00f62e6
JS
8872 if (phba->nvmet_support) {
8873 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
8874 cpu = lpfc_find_cpu_handle(phba, idx,
8875 LPFC_FIND_BY_HDWQ);
8876 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda
JS
8877 LPFC_DEFAULT_PAGE_SIZE,
8878 phba->sli4_hba.cq_esize,
c1a21ebc
JS
8879 phba->sli4_hba.cq_ecount,
8880 cpu);
c00f62e6
JS
8881 if (!qdesc) {
8882 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
cdb42bec
JS
8883 "3142 Failed allocate NVME "
8884 "CQ Set (%d)\n", idx);
c00f62e6 8885 goto out_error;
2d7dbc4c 8886 }
c00f62e6
JS
8887 qdesc->qe_valid = 1;
8888 qdesc->hdwq = idx;
8889 qdesc->chann = cpu;
8890 phba->sli4_hba.nvmet_cqset[idx] = qdesc;
2d7dbc4c
JS
8891 }
8892 }
8893
da0436e9 8894 /*
67d12733 8895 * Create Slow Path Completion Queues (CQs)
da0436e9
JS
8896 */
8897
c1a21ebc 8898 cpu = lpfc_find_cpu_handle(phba, 0, LPFC_FIND_BY_EQ);
da0436e9 8899 /* Create slow-path Mailbox Command Complete Queue */
81b96eda
JS
8900 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8901 phba->sli4_hba.cq_esize,
c1a21ebc 8902 phba->sli4_hba.cq_ecount, cpu);
da0436e9
JS
8903 if (!qdesc) {
8904 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8905 "0500 Failed allocate slow-path mailbox CQ\n");
67d12733 8906 goto out_error;
da0436e9 8907 }
7365f6fd 8908 qdesc->qe_valid = 1;
da0436e9
JS
8909 phba->sli4_hba.mbx_cq = qdesc;
8910
8911 /* Create slow-path ELS Complete Queue */
81b96eda
JS
8912 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8913 phba->sli4_hba.cq_esize,
c1a21ebc 8914 phba->sli4_hba.cq_ecount, cpu);
da0436e9
JS
8915 if (!qdesc) {
8916 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8917 "0501 Failed allocate slow-path ELS CQ\n");
67d12733 8918 goto out_error;
da0436e9 8919 }
7365f6fd 8920 qdesc->qe_valid = 1;
c00f62e6 8921 qdesc->chann = cpu;
da0436e9
JS
8922 phba->sli4_hba.els_cq = qdesc;
8923
da0436e9 8924
5350d872 8925 /*
67d12733 8926 * Create Slow Path Work Queues (WQs)
5350d872 8927 */
da0436e9
JS
8928
8929 /* Create Mailbox Command Queue */
da0436e9 8930
81b96eda
JS
8931 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8932 phba->sli4_hba.mq_esize,
c1a21ebc 8933 phba->sli4_hba.mq_ecount, cpu);
da0436e9
JS
8934 if (!qdesc) {
8935 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8936 "0505 Failed allocate slow-path MQ\n");
67d12733 8937 goto out_error;
da0436e9 8938 }
c00f62e6 8939 qdesc->chann = cpu;
da0436e9
JS
8940 phba->sli4_hba.mbx_wq = qdesc;
8941
8942 /*
67d12733 8943 * Create ELS Work Queues
da0436e9 8944 */
da0436e9
JS
8945
8946 /* Create slow-path ELS Work Queue */
81b96eda
JS
8947 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8948 phba->sli4_hba.wq_esize,
c1a21ebc 8949 phba->sli4_hba.wq_ecount, cpu);
da0436e9
JS
8950 if (!qdesc) {
8951 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8952 "0504 Failed allocate slow-path ELS WQ\n");
67d12733 8953 goto out_error;
da0436e9 8954 }
c00f62e6 8955 qdesc->chann = cpu;
da0436e9 8956 phba->sli4_hba.els_wq = qdesc;
895427bd
JS
8957 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
8958
8959 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
8960 /* Create NVME LS Complete Queue */
81b96eda
JS
8961 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8962 phba->sli4_hba.cq_esize,
c1a21ebc 8963 phba->sli4_hba.cq_ecount, cpu);
895427bd
JS
8964 if (!qdesc) {
8965 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8966 "6079 Failed allocate NVME LS CQ\n");
8967 goto out_error;
8968 }
c00f62e6 8969 qdesc->chann = cpu;
7365f6fd 8970 qdesc->qe_valid = 1;
895427bd
JS
8971 phba->sli4_hba.nvmels_cq = qdesc;
8972
8973 /* Create NVME LS Work Queue */
81b96eda
JS
8974 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8975 phba->sli4_hba.wq_esize,
c1a21ebc 8976 phba->sli4_hba.wq_ecount, cpu);
895427bd
JS
8977 if (!qdesc) {
8978 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8979 "6080 Failed allocate NVME LS WQ\n");
8980 goto out_error;
8981 }
c00f62e6 8982 qdesc->chann = cpu;
895427bd
JS
8983 phba->sli4_hba.nvmels_wq = qdesc;
8984 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
8985 }
da0436e9 8986
da0436e9
JS
8987 /*
8988 * Create Receive Queue (RQ)
8989 */
da0436e9
JS
8990
8991 /* Create Receive Queue for header */
81b96eda
JS
8992 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8993 phba->sli4_hba.rq_esize,
c1a21ebc 8994 phba->sli4_hba.rq_ecount, cpu);
da0436e9
JS
8995 if (!qdesc) {
8996 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8997 "0506 Failed allocate receive HRQ\n");
67d12733 8998 goto out_error;
da0436e9
JS
8999 }
9000 phba->sli4_hba.hdr_rq = qdesc;
9001
9002 /* Create Receive Queue for data */
81b96eda
JS
9003 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9004 phba->sli4_hba.rq_esize,
c1a21ebc 9005 phba->sli4_hba.rq_ecount, cpu);
da0436e9
JS
9006 if (!qdesc) {
9007 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9008 "0507 Failed allocate receive DRQ\n");
67d12733 9009 goto out_error;
da0436e9
JS
9010 }
9011 phba->sli4_hba.dat_rq = qdesc;
9012
cdb42bec
JS
9013 if ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) &&
9014 phba->nvmet_support) {
2d7dbc4c 9015 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
c1a21ebc
JS
9016 cpu = lpfc_find_cpu_handle(phba, idx,
9017 LPFC_FIND_BY_HDWQ);
2d7dbc4c
JS
9018 /* Create NVMET Receive Queue for header */
9019 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda 9020 LPFC_DEFAULT_PAGE_SIZE,
2d7dbc4c 9021 phba->sli4_hba.rq_esize,
c1a21ebc
JS
9022 LPFC_NVMET_RQE_DEF_COUNT,
9023 cpu);
2d7dbc4c
JS
9024 if (!qdesc) {
9025 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9026 "3146 Failed allocate "
9027 "receive HRQ\n");
9028 goto out_error;
9029 }
5e5b511d 9030 qdesc->hdwq = idx;
2d7dbc4c
JS
9031 phba->sli4_hba.nvmet_mrq_hdr[idx] = qdesc;
9032
9033 /* Only needed for header of RQ pair */
c1a21ebc
JS
9034 qdesc->rqbp = kzalloc_node(sizeof(*qdesc->rqbp),
9035 GFP_KERNEL,
9036 cpu_to_node(cpu));
2d7dbc4c
JS
9037 if (qdesc->rqbp == NULL) {
9038 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9039 "6131 Failed allocate "
9040 "Header RQBP\n");
9041 goto out_error;
9042 }
9043
4b40d02b
DK
9044 /* Put list in known state in case driver load fails. */
9045 INIT_LIST_HEAD(&qdesc->rqbp->rqb_buffer_list);
9046
2d7dbc4c
JS
9047 /* Create NVMET Receive Queue for data */
9048 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda 9049 LPFC_DEFAULT_PAGE_SIZE,
2d7dbc4c 9050 phba->sli4_hba.rq_esize,
c1a21ebc
JS
9051 LPFC_NVMET_RQE_DEF_COUNT,
9052 cpu);
2d7dbc4c
JS
9053 if (!qdesc) {
9054 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9055 "3156 Failed allocate "
9056 "receive DRQ\n");
9057 goto out_error;
9058 }
5e5b511d 9059 qdesc->hdwq = idx;
2d7dbc4c
JS
9060 phba->sli4_hba.nvmet_mrq_data[idx] = qdesc;
9061 }
9062 }
9063
4c47efc1
JS
9064#if defined(BUILD_NVME)
9065 /* Clear NVME stats */
9066 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
9067 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9068 memset(&phba->sli4_hba.hdwq[idx].nvme_cstat, 0,
9069 sizeof(phba->sli4_hba.hdwq[idx].nvme_cstat));
9070 }
9071 }
9072#endif
9073
9074 /* Clear SCSI stats */
9075 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
9076 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9077 memset(&phba->sli4_hba.hdwq[idx].scsi_cstat, 0,
9078 sizeof(phba->sli4_hba.hdwq[idx].scsi_cstat));
9079 }
9080 }
9081
da0436e9
JS
9082 return 0;
9083
da0436e9 9084out_error:
67d12733 9085 lpfc_sli4_queue_destroy(phba);
da0436e9
JS
9086 return -ENOMEM;
9087}
9088
895427bd
JS
9089static inline void
9090__lpfc_sli4_release_queue(struct lpfc_queue **qp)
9091{
9092 if (*qp != NULL) {
9093 lpfc_sli4_queue_free(*qp);
9094 *qp = NULL;
9095 }
9096}
9097
9098static inline void
9099lpfc_sli4_release_queues(struct lpfc_queue ***qs, int max)
9100{
9101 int idx;
9102
9103 if (*qs == NULL)
9104 return;
9105
9106 for (idx = 0; idx < max; idx++)
9107 __lpfc_sli4_release_queue(&(*qs)[idx]);
9108
9109 kfree(*qs);
9110 *qs = NULL;
9111}
9112
9113static inline void
6a828b0f 9114lpfc_sli4_release_hdwq(struct lpfc_hba *phba)
895427bd 9115{
6a828b0f 9116 struct lpfc_sli4_hdw_queue *hdwq;
657add4e 9117 struct lpfc_queue *eq;
cdb42bec
JS
9118 uint32_t idx;
9119
6a828b0f 9120 hdwq = phba->sli4_hba.hdwq;
6a828b0f 9121
657add4e
JS
9122 /* Loop thru all Hardware Queues */
9123 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9124 /* Free the CQ/WQ corresponding to the Hardware Queue */
c00f62e6
JS
9125 lpfc_sli4_queue_free(hdwq[idx].io_cq);
9126 lpfc_sli4_queue_free(hdwq[idx].io_wq);
9127 hdwq[idx].io_cq = NULL;
9128 hdwq[idx].io_wq = NULL;
d79c9e9d
JS
9129 if (phba->cfg_xpsgl && !phba->nvmet_support)
9130 lpfc_free_sgl_per_hdwq(phba, &hdwq[idx]);
9131 lpfc_free_cmd_rsp_buf_per_hdwq(phba, &hdwq[idx]);
895427bd 9132 }
657add4e
JS
9133 /* Loop thru all IRQ vectors */
9134 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
9135 /* Free the EQ corresponding to the IRQ vector */
9136 eq = phba->sli4_hba.hba_eq_hdl[idx].eq;
9137 lpfc_sli4_queue_free(eq);
9138 phba->sli4_hba.hba_eq_hdl[idx].eq = NULL;
9139 }
895427bd
JS
9140}
9141
da0436e9
JS
9142/**
9143 * lpfc_sli4_queue_destroy - Destroy all the SLI4 queues
9144 * @phba: pointer to lpfc hba data structure.
9145 *
9146 * This routine is invoked to release all the SLI4 queues with the FCoE HBA
9147 * operation.
9148 *
9149 * Return codes
af901ca1 9150 * 0 - successful
25985edc 9151 * -ENOMEM - No available memory
d439d286 9152 * -EIO - The mailbox failed to complete successfully.
da0436e9 9153 **/
5350d872 9154void
da0436e9
JS
9155lpfc_sli4_queue_destroy(struct lpfc_hba *phba)
9156{
4645f7b5
JS
9157 /*
9158 * Set FREE_INIT before beginning to free the queues.
9159 * Wait until the users of queues to acknowledge to
9160 * release queues by clearing FREE_WAIT.
9161 */
9162 spin_lock_irq(&phba->hbalock);
9163 phba->sli.sli_flag |= LPFC_QUEUE_FREE_INIT;
9164 while (phba->sli.sli_flag & LPFC_QUEUE_FREE_WAIT) {
9165 spin_unlock_irq(&phba->hbalock);
9166 msleep(20);
9167 spin_lock_irq(&phba->hbalock);
9168 }
9169 spin_unlock_irq(&phba->hbalock);
9170
895427bd 9171 /* Release HBA eqs */
cdb42bec 9172 if (phba->sli4_hba.hdwq)
6a828b0f 9173 lpfc_sli4_release_hdwq(phba);
895427bd 9174
bcb24f65
JS
9175 if (phba->nvmet_support) {
9176 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_cqset,
9177 phba->cfg_nvmet_mrq);
2d7dbc4c 9178
bcb24f65
JS
9179 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_hdr,
9180 phba->cfg_nvmet_mrq);
9181 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_data,
9182 phba->cfg_nvmet_mrq);
9183 }
2d7dbc4c 9184
895427bd
JS
9185 /* Release mailbox command work queue */
9186 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_wq);
9187
9188 /* Release ELS work queue */
9189 __lpfc_sli4_release_queue(&phba->sli4_hba.els_wq);
9190
9191 /* Release ELS work queue */
9192 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_wq);
9193
9194 /* Release unsolicited receive queue */
9195 __lpfc_sli4_release_queue(&phba->sli4_hba.hdr_rq);
9196 __lpfc_sli4_release_queue(&phba->sli4_hba.dat_rq);
9197
9198 /* Release ELS complete queue */
9199 __lpfc_sli4_release_queue(&phba->sli4_hba.els_cq);
9200
9201 /* Release NVME LS complete queue */
9202 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_cq);
9203
9204 /* Release mailbox command complete queue */
9205 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_cq);
9206
9207 /* Everything on this list has been freed */
9208 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
4645f7b5
JS
9209
9210 /* Done with freeing the queues */
9211 spin_lock_irq(&phba->hbalock);
9212 phba->sli.sli_flag &= ~LPFC_QUEUE_FREE_INIT;
9213 spin_unlock_irq(&phba->hbalock);
895427bd
JS
9214}
9215
895427bd
JS
9216int
9217lpfc_free_rq_buffer(struct lpfc_hba *phba, struct lpfc_queue *rq)
9218{
9219 struct lpfc_rqb *rqbp;
9220 struct lpfc_dmabuf *h_buf;
9221 struct rqb_dmabuf *rqb_buffer;
9222
9223 rqbp = rq->rqbp;
9224 while (!list_empty(&rqbp->rqb_buffer_list)) {
9225 list_remove_head(&rqbp->rqb_buffer_list, h_buf,
9226 struct lpfc_dmabuf, list);
9227
9228 rqb_buffer = container_of(h_buf, struct rqb_dmabuf, hbuf);
9229 (rqbp->rqb_free_buffer)(phba, rqb_buffer);
9230 rqbp->buffer_count--;
67d12733 9231 }
895427bd
JS
9232 return 1;
9233}
67d12733 9234
895427bd
JS
9235static int
9236lpfc_create_wq_cq(struct lpfc_hba *phba, struct lpfc_queue *eq,
9237 struct lpfc_queue *cq, struct lpfc_queue *wq, uint16_t *cq_map,
9238 int qidx, uint32_t qtype)
9239{
9240 struct lpfc_sli_ring *pring;
9241 int rc;
9242
9243 if (!eq || !cq || !wq) {
9244 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9245 "6085 Fast-path %s (%d) not allocated\n",
9246 ((eq) ? ((cq) ? "WQ" : "CQ") : "EQ"), qidx);
9247 return -ENOMEM;
9248 }
9249
9250 /* create the Cq first */
9251 rc = lpfc_cq_create(phba, cq, eq,
9252 (qtype == LPFC_MBOX) ? LPFC_MCQ : LPFC_WCQ, qtype);
9253 if (rc) {
9254 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9255 "6086 Failed setup of CQ (%d), rc = 0x%x\n",
9256 qidx, (uint32_t)rc);
9257 return rc;
67d12733
JS
9258 }
9259
895427bd 9260 if (qtype != LPFC_MBOX) {
cdb42bec 9261 /* Setup cq_map for fast lookup */
895427bd
JS
9262 if (cq_map)
9263 *cq_map = cq->queue_id;
da0436e9 9264
895427bd
JS
9265 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9266 "6087 CQ setup: cq[%d]-id=%d, parent eq[%d]-id=%d\n",
9267 qidx, cq->queue_id, qidx, eq->queue_id);
da0436e9 9268
895427bd
JS
9269 /* create the wq */
9270 rc = lpfc_wq_create(phba, wq, cq, qtype);
9271 if (rc) {
9272 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
c835c085 9273 "4618 Fail setup fastpath WQ (%d), rc = 0x%x\n",
895427bd
JS
9274 qidx, (uint32_t)rc);
9275 /* no need to tear down cq - caller will do so */
9276 return rc;
9277 }
da0436e9 9278
895427bd
JS
9279 /* Bind this CQ/WQ to the NVME ring */
9280 pring = wq->pring;
9281 pring->sli.sli4.wqp = (void *)wq;
9282 cq->pring = pring;
da0436e9 9283
895427bd
JS
9284 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9285 "2593 WQ setup: wq[%d]-id=%d assoc=%d, cq[%d]-id=%d\n",
9286 qidx, wq->queue_id, wq->assoc_qid, qidx, cq->queue_id);
9287 } else {
9288 rc = lpfc_mq_create(phba, wq, cq, LPFC_MBOX);
9289 if (rc) {
9290 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9291 "0539 Failed setup of slow-path MQ: "
9292 "rc = 0x%x\n", rc);
9293 /* no need to tear down cq - caller will do so */
9294 return rc;
9295 }
da0436e9 9296
895427bd
JS
9297 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9298 "2589 MBX MQ setup: wq-id=%d, parent cq-id=%d\n",
9299 phba->sli4_hba.mbx_wq->queue_id,
9300 phba->sli4_hba.mbx_cq->queue_id);
67d12733 9301 }
da0436e9 9302
895427bd 9303 return 0;
da0436e9
JS
9304}
9305
6a828b0f
JS
9306/**
9307 * lpfc_setup_cq_lookup - Setup the CQ lookup table
9308 * @phba: pointer to lpfc hba data structure.
9309 *
9310 * This routine will populate the cq_lookup table by all
9311 * available CQ queue_id's.
9312 **/
3999df75 9313static void
6a828b0f
JS
9314lpfc_setup_cq_lookup(struct lpfc_hba *phba)
9315{
9316 struct lpfc_queue *eq, *childq;
6a828b0f
JS
9317 int qidx;
9318
6a828b0f
JS
9319 memset(phba->sli4_hba.cq_lookup, 0,
9320 (sizeof(struct lpfc_queue *) * (phba->sli4_hba.cq_max + 1)));
657add4e 9321 /* Loop thru all IRQ vectors */
6a828b0f 9322 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
657add4e
JS
9323 /* Get the EQ corresponding to the IRQ vector */
9324 eq = phba->sli4_hba.hba_eq_hdl[qidx].eq;
6a828b0f
JS
9325 if (!eq)
9326 continue;
657add4e 9327 /* Loop through all CQs associated with that EQ */
6a828b0f
JS
9328 list_for_each_entry(childq, &eq->child_list, list) {
9329 if (childq->queue_id > phba->sli4_hba.cq_max)
9330 continue;
c00f62e6 9331 if (childq->subtype == LPFC_IO)
6a828b0f
JS
9332 phba->sli4_hba.cq_lookup[childq->queue_id] =
9333 childq;
9334 }
9335 }
9336}
9337
da0436e9
JS
9338/**
9339 * lpfc_sli4_queue_setup - Set up all the SLI4 queues
9340 * @phba: pointer to lpfc hba data structure.
9341 *
9342 * This routine is invoked to set up all the SLI4 queues for the FCoE HBA
9343 * operation.
9344 *
9345 * Return codes
af901ca1 9346 * 0 - successful
25985edc 9347 * -ENOMEM - No available memory
d439d286 9348 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9349 **/
9350int
9351lpfc_sli4_queue_setup(struct lpfc_hba *phba)
9352{
962bc51b
JS
9353 uint32_t shdr_status, shdr_add_status;
9354 union lpfc_sli4_cfg_shdr *shdr;
657add4e 9355 struct lpfc_vector_map_info *cpup;
cdb42bec 9356 struct lpfc_sli4_hdw_queue *qp;
962bc51b 9357 LPFC_MBOXQ_t *mboxq;
657add4e 9358 int qidx, cpu;
cb733e35 9359 uint32_t length, usdelay;
895427bd 9360 int rc = -ENOMEM;
962bc51b
JS
9361
9362 /* Check for dual-ULP support */
9363 mboxq = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9364 if (!mboxq) {
9365 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9366 "3249 Unable to allocate memory for "
9367 "QUERY_FW_CFG mailbox command\n");
9368 return -ENOMEM;
9369 }
9370 length = (sizeof(struct lpfc_mbx_query_fw_config) -
9371 sizeof(struct lpfc_sli4_cfg_mhdr));
9372 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
9373 LPFC_MBOX_OPCODE_QUERY_FW_CFG,
9374 length, LPFC_SLI4_MBX_EMBED);
9375
9376 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9377
9378 shdr = (union lpfc_sli4_cfg_shdr *)
9379 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
9380 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
9381 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
9382 if (shdr_status || shdr_add_status || rc) {
9383 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9384 "3250 QUERY_FW_CFG mailbox failed with status "
9385 "x%x add_status x%x, mbx status x%x\n",
9386 shdr_status, shdr_add_status, rc);
9387 if (rc != MBX_TIMEOUT)
9388 mempool_free(mboxq, phba->mbox_mem_pool);
9389 rc = -ENXIO;
9390 goto out_error;
9391 }
9392
9393 phba->sli4_hba.fw_func_mode =
9394 mboxq->u.mqe.un.query_fw_cfg.rsp.function_mode;
9395 phba->sli4_hba.ulp0_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp0_mode;
9396 phba->sli4_hba.ulp1_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp1_mode;
8b017a30
JS
9397 phba->sli4_hba.physical_port =
9398 mboxq->u.mqe.un.query_fw_cfg.rsp.physical_port;
962bc51b
JS
9399 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9400 "3251 QUERY_FW_CFG: func_mode:x%x, ulp0_mode:x%x, "
9401 "ulp1_mode:x%x\n", phba->sli4_hba.fw_func_mode,
9402 phba->sli4_hba.ulp0_mode, phba->sli4_hba.ulp1_mode);
9403
9404 if (rc != MBX_TIMEOUT)
9405 mempool_free(mboxq, phba->mbox_mem_pool);
da0436e9
JS
9406
9407 /*
67d12733 9408 * Set up HBA Event Queues (EQs)
da0436e9 9409 */
cdb42bec 9410 qp = phba->sli4_hba.hdwq;
da0436e9 9411
67d12733 9412 /* Set up HBA event queue */
cdb42bec 9413 if (!qp) {
2e90f4b5
JS
9414 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9415 "3147 Fast-path EQs not allocated\n");
1b51197d 9416 rc = -ENOMEM;
67d12733 9417 goto out_error;
2e90f4b5 9418 }
657add4e
JS
9419
9420 /* Loop thru all IRQ vectors */
6a828b0f 9421 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
657add4e
JS
9422 /* Create HBA Event Queues (EQs) in order */
9423 for_each_present_cpu(cpu) {
9424 cpup = &phba->sli4_hba.cpu_map[cpu];
9425
9426 /* Look for the CPU thats using that vector with
9427 * LPFC_CPU_FIRST_IRQ set.
9428 */
9429 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
9430 continue;
9431 if (qidx != cpup->eq)
9432 continue;
9433
9434 /* Create an EQ for that vector */
9435 rc = lpfc_eq_create(phba, qp[cpup->hdwq].hba_eq,
9436 phba->cfg_fcp_imax);
9437 if (rc) {
9438 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9439 "0523 Failed setup of fast-path"
9440 " EQ (%d), rc = 0x%x\n",
9441 cpup->eq, (uint32_t)rc);
9442 goto out_destroy;
9443 }
9444
9445 /* Save the EQ for that vector in the hba_eq_hdl */
9446 phba->sli4_hba.hba_eq_hdl[cpup->eq].eq =
9447 qp[cpup->hdwq].hba_eq;
9448
9449 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9450 "2584 HBA EQ setup: queue[%d]-id=%d\n",
9451 cpup->eq,
9452 qp[cpup->hdwq].hba_eq->queue_id);
da0436e9 9453 }
67d12733
JS
9454 }
9455
657add4e 9456 /* Loop thru all Hardware Queues */
cdb42bec 9457 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
657add4e
JS
9458 cpu = lpfc_find_cpu_handle(phba, qidx, LPFC_FIND_BY_HDWQ);
9459 cpup = &phba->sli4_hba.cpu_map[cpu];
9460
9461 /* Create the CQ/WQ corresponding to the Hardware Queue */
cdb42bec 9462 rc = lpfc_create_wq_cq(phba,
657add4e 9463 phba->sli4_hba.hdwq[cpup->hdwq].hba_eq,
c00f62e6
JS
9464 qp[qidx].io_cq,
9465 qp[qidx].io_wq,
9466 &phba->sli4_hba.hdwq[qidx].io_cq_map,
9467 qidx,
9468 LPFC_IO);
cdb42bec 9469 if (rc) {
67d12733 9470 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
895427bd 9471 "0535 Failed to setup fastpath "
c00f62e6 9472 "IO WQ/CQ (%d), rc = 0x%x\n",
895427bd 9473 qidx, (uint32_t)rc);
cdb42bec 9474 goto out_destroy;
895427bd 9475 }
67d12733 9476 }
895427bd 9477
da0436e9 9478 /*
895427bd 9479 * Set up Slow Path Complete Queues (CQs)
da0436e9
JS
9480 */
9481
895427bd 9482 /* Set up slow-path MBOX CQ/MQ */
da0436e9 9483
895427bd 9484 if (!phba->sli4_hba.mbx_cq || !phba->sli4_hba.mbx_wq) {
da0436e9 9485 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
895427bd
JS
9486 "0528 %s not allocated\n",
9487 phba->sli4_hba.mbx_cq ?
d1f525aa 9488 "Mailbox WQ" : "Mailbox CQ");
1b51197d 9489 rc = -ENOMEM;
895427bd 9490 goto out_destroy;
da0436e9 9491 }
da0436e9 9492
cdb42bec 9493 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
d1f525aa
JS
9494 phba->sli4_hba.mbx_cq,
9495 phba->sli4_hba.mbx_wq,
9496 NULL, 0, LPFC_MBOX);
da0436e9
JS
9497 if (rc) {
9498 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
895427bd
JS
9499 "0529 Failed setup of mailbox WQ/CQ: rc = 0x%x\n",
9500 (uint32_t)rc);
9501 goto out_destroy;
da0436e9 9502 }
2d7dbc4c
JS
9503 if (phba->nvmet_support) {
9504 if (!phba->sli4_hba.nvmet_cqset) {
9505 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9506 "3165 Fast-path NVME CQ Set "
9507 "array not allocated\n");
9508 rc = -ENOMEM;
9509 goto out_destroy;
9510 }
9511 if (phba->cfg_nvmet_mrq > 1) {
9512 rc = lpfc_cq_create_set(phba,
9513 phba->sli4_hba.nvmet_cqset,
cdb42bec 9514 qp,
2d7dbc4c
JS
9515 LPFC_WCQ, LPFC_NVMET);
9516 if (rc) {
9517 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9518 "3164 Failed setup of NVME CQ "
9519 "Set, rc = 0x%x\n",
9520 (uint32_t)rc);
9521 goto out_destroy;
9522 }
9523 } else {
9524 /* Set up NVMET Receive Complete Queue */
9525 rc = lpfc_cq_create(phba, phba->sli4_hba.nvmet_cqset[0],
cdb42bec 9526 qp[0].hba_eq,
2d7dbc4c
JS
9527 LPFC_WCQ, LPFC_NVMET);
9528 if (rc) {
9529 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9530 "6089 Failed setup NVMET CQ: "
9531 "rc = 0x%x\n", (uint32_t)rc);
9532 goto out_destroy;
9533 }
81b96eda
JS
9534 phba->sli4_hba.nvmet_cqset[0]->chann = 0;
9535
2d7dbc4c
JS
9536 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9537 "6090 NVMET CQ setup: cq-id=%d, "
9538 "parent eq-id=%d\n",
9539 phba->sli4_hba.nvmet_cqset[0]->queue_id,
cdb42bec 9540 qp[0].hba_eq->queue_id);
2d7dbc4c
JS
9541 }
9542 }
da0436e9 9543
895427bd
JS
9544 /* Set up slow-path ELS WQ/CQ */
9545 if (!phba->sli4_hba.els_cq || !phba->sli4_hba.els_wq) {
da0436e9 9546 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
895427bd
JS
9547 "0530 ELS %s not allocated\n",
9548 phba->sli4_hba.els_cq ? "WQ" : "CQ");
1b51197d 9549 rc = -ENOMEM;
895427bd 9550 goto out_destroy;
da0436e9 9551 }
cdb42bec
JS
9552 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9553 phba->sli4_hba.els_cq,
9554 phba->sli4_hba.els_wq,
9555 NULL, 0, LPFC_ELS);
da0436e9
JS
9556 if (rc) {
9557 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
cdb42bec
JS
9558 "0525 Failed setup of ELS WQ/CQ: rc = 0x%x\n",
9559 (uint32_t)rc);
895427bd 9560 goto out_destroy;
da0436e9
JS
9561 }
9562 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9563 "2590 ELS WQ setup: wq-id=%d, parent cq-id=%d\n",
9564 phba->sli4_hba.els_wq->queue_id,
9565 phba->sli4_hba.els_cq->queue_id);
9566
cdb42bec 9567 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
895427bd
JS
9568 /* Set up NVME LS Complete Queue */
9569 if (!phba->sli4_hba.nvmels_cq || !phba->sli4_hba.nvmels_wq) {
9570 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9571 "6091 LS %s not allocated\n",
9572 phba->sli4_hba.nvmels_cq ? "WQ" : "CQ");
9573 rc = -ENOMEM;
9574 goto out_destroy;
9575 }
cdb42bec
JS
9576 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9577 phba->sli4_hba.nvmels_cq,
9578 phba->sli4_hba.nvmels_wq,
9579 NULL, 0, LPFC_NVME_LS);
895427bd
JS
9580 if (rc) {
9581 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
cdb42bec
JS
9582 "0526 Failed setup of NVVME LS WQ/CQ: "
9583 "rc = 0x%x\n", (uint32_t)rc);
895427bd
JS
9584 goto out_destroy;
9585 }
9586
9587 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9588 "6096 ELS WQ setup: wq-id=%d, "
9589 "parent cq-id=%d\n",
9590 phba->sli4_hba.nvmels_wq->queue_id,
9591 phba->sli4_hba.nvmels_cq->queue_id);
9592 }
9593
2d7dbc4c
JS
9594 /*
9595 * Create NVMET Receive Queue (RQ)
9596 */
9597 if (phba->nvmet_support) {
9598 if ((!phba->sli4_hba.nvmet_cqset) ||
9599 (!phba->sli4_hba.nvmet_mrq_hdr) ||
9600 (!phba->sli4_hba.nvmet_mrq_data)) {
9601 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9602 "6130 MRQ CQ Queues not "
9603 "allocated\n");
9604 rc = -ENOMEM;
9605 goto out_destroy;
9606 }
9607 if (phba->cfg_nvmet_mrq > 1) {
9608 rc = lpfc_mrq_create(phba,
9609 phba->sli4_hba.nvmet_mrq_hdr,
9610 phba->sli4_hba.nvmet_mrq_data,
9611 phba->sli4_hba.nvmet_cqset,
9612 LPFC_NVMET);
9613 if (rc) {
9614 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9615 "6098 Failed setup of NVMET "
9616 "MRQ: rc = 0x%x\n",
9617 (uint32_t)rc);
9618 goto out_destroy;
9619 }
9620
9621 } else {
9622 rc = lpfc_rq_create(phba,
9623 phba->sli4_hba.nvmet_mrq_hdr[0],
9624 phba->sli4_hba.nvmet_mrq_data[0],
9625 phba->sli4_hba.nvmet_cqset[0],
9626 LPFC_NVMET);
9627 if (rc) {
9628 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9629 "6057 Failed setup of NVMET "
9630 "Receive Queue: rc = 0x%x\n",
9631 (uint32_t)rc);
9632 goto out_destroy;
9633 }
9634
9635 lpfc_printf_log(
9636 phba, KERN_INFO, LOG_INIT,
9637 "6099 NVMET RQ setup: hdr-rq-id=%d, "
9638 "dat-rq-id=%d parent cq-id=%d\n",
9639 phba->sli4_hba.nvmet_mrq_hdr[0]->queue_id,
9640 phba->sli4_hba.nvmet_mrq_data[0]->queue_id,
9641 phba->sli4_hba.nvmet_cqset[0]->queue_id);
9642
9643 }
9644 }
9645
da0436e9
JS
9646 if (!phba->sli4_hba.hdr_rq || !phba->sli4_hba.dat_rq) {
9647 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9648 "0540 Receive Queue not allocated\n");
1b51197d 9649 rc = -ENOMEM;
895427bd 9650 goto out_destroy;
da0436e9 9651 }
73d91e50 9652
da0436e9 9653 rc = lpfc_rq_create(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq,
4d9ab994 9654 phba->sli4_hba.els_cq, LPFC_USOL);
da0436e9
JS
9655 if (rc) {
9656 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9657 "0541 Failed setup of Receive Queue: "
a2fc4aef 9658 "rc = 0x%x\n", (uint32_t)rc);
895427bd 9659 goto out_destroy;
da0436e9 9660 }
73d91e50 9661
da0436e9
JS
9662 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9663 "2592 USL RQ setup: hdr-rq-id=%d, dat-rq-id=%d "
9664 "parent cq-id=%d\n",
9665 phba->sli4_hba.hdr_rq->queue_id,
9666 phba->sli4_hba.dat_rq->queue_id,
4d9ab994 9667 phba->sli4_hba.els_cq->queue_id);
1ba981fd 9668
cb733e35
JS
9669 if (phba->cfg_fcp_imax)
9670 usdelay = LPFC_SEC_TO_USEC / phba->cfg_fcp_imax;
9671 else
9672 usdelay = 0;
9673
6a828b0f 9674 for (qidx = 0; qidx < phba->cfg_irq_chann;
cdb42bec 9675 qidx += LPFC_MAX_EQ_DELAY_EQID_CNT)
0cf07f84 9676 lpfc_modify_hba_eq_delay(phba, qidx, LPFC_MAX_EQ_DELAY_EQID_CNT,
cb733e35 9677 usdelay);
43140ca6 9678
6a828b0f
JS
9679 if (phba->sli4_hba.cq_max) {
9680 kfree(phba->sli4_hba.cq_lookup);
9681 phba->sli4_hba.cq_lookup = kcalloc((phba->sli4_hba.cq_max + 1),
9682 sizeof(struct lpfc_queue *), GFP_KERNEL);
9683 if (!phba->sli4_hba.cq_lookup) {
1ba981fd 9684 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6a828b0f
JS
9685 "0549 Failed setup of CQ Lookup table: "
9686 "size 0x%x\n", phba->sli4_hba.cq_max);
fad28e3d 9687 rc = -ENOMEM;
895427bd 9688 goto out_destroy;
1ba981fd 9689 }
6a828b0f 9690 lpfc_setup_cq_lookup(phba);
1ba981fd 9691 }
da0436e9
JS
9692 return 0;
9693
895427bd
JS
9694out_destroy:
9695 lpfc_sli4_queue_unset(phba);
da0436e9
JS
9696out_error:
9697 return rc;
9698}
9699
9700/**
9701 * lpfc_sli4_queue_unset - Unset all the SLI4 queues
9702 * @phba: pointer to lpfc hba data structure.
9703 *
9704 * This routine is invoked to unset all the SLI4 queues with the FCoE HBA
9705 * operation.
9706 *
9707 * Return codes
af901ca1 9708 * 0 - successful
25985edc 9709 * -ENOMEM - No available memory
d439d286 9710 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9711 **/
9712void
9713lpfc_sli4_queue_unset(struct lpfc_hba *phba)
9714{
cdb42bec 9715 struct lpfc_sli4_hdw_queue *qp;
657add4e 9716 struct lpfc_queue *eq;
895427bd 9717 int qidx;
da0436e9
JS
9718
9719 /* Unset mailbox command work queue */
895427bd
JS
9720 if (phba->sli4_hba.mbx_wq)
9721 lpfc_mq_destroy(phba, phba->sli4_hba.mbx_wq);
9722
9723 /* Unset NVME LS work queue */
9724 if (phba->sli4_hba.nvmels_wq)
9725 lpfc_wq_destroy(phba, phba->sli4_hba.nvmels_wq);
9726
da0436e9 9727 /* Unset ELS work queue */
019c0d66 9728 if (phba->sli4_hba.els_wq)
895427bd
JS
9729 lpfc_wq_destroy(phba, phba->sli4_hba.els_wq);
9730
da0436e9 9731 /* Unset unsolicited receive queue */
895427bd
JS
9732 if (phba->sli4_hba.hdr_rq)
9733 lpfc_rq_destroy(phba, phba->sli4_hba.hdr_rq,
9734 phba->sli4_hba.dat_rq);
9735
da0436e9 9736 /* Unset mailbox command complete queue */
895427bd
JS
9737 if (phba->sli4_hba.mbx_cq)
9738 lpfc_cq_destroy(phba, phba->sli4_hba.mbx_cq);
9739
da0436e9 9740 /* Unset ELS complete queue */
895427bd
JS
9741 if (phba->sli4_hba.els_cq)
9742 lpfc_cq_destroy(phba, phba->sli4_hba.els_cq);
9743
9744 /* Unset NVME LS complete queue */
9745 if (phba->sli4_hba.nvmels_cq)
9746 lpfc_cq_destroy(phba, phba->sli4_hba.nvmels_cq);
9747
bcb24f65
JS
9748 if (phba->nvmet_support) {
9749 /* Unset NVMET MRQ queue */
9750 if (phba->sli4_hba.nvmet_mrq_hdr) {
9751 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
9752 lpfc_rq_destroy(
9753 phba,
2d7dbc4c
JS
9754 phba->sli4_hba.nvmet_mrq_hdr[qidx],
9755 phba->sli4_hba.nvmet_mrq_data[qidx]);
bcb24f65 9756 }
2d7dbc4c 9757
bcb24f65
JS
9758 /* Unset NVMET CQ Set complete queue */
9759 if (phba->sli4_hba.nvmet_cqset) {
9760 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
9761 lpfc_cq_destroy(
9762 phba, phba->sli4_hba.nvmet_cqset[qidx]);
9763 }
2d7dbc4c
JS
9764 }
9765
cdb42bec
JS
9766 /* Unset fast-path SLI4 queues */
9767 if (phba->sli4_hba.hdwq) {
657add4e 9768 /* Loop thru all Hardware Queues */
cdb42bec 9769 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
657add4e 9770 /* Destroy the CQ/WQ corresponding to Hardware Queue */
cdb42bec 9771 qp = &phba->sli4_hba.hdwq[qidx];
c00f62e6
JS
9772 lpfc_wq_destroy(phba, qp->io_wq);
9773 lpfc_cq_destroy(phba, qp->io_cq);
657add4e
JS
9774 }
9775 /* Loop thru all IRQ vectors */
9776 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
9777 /* Destroy the EQ corresponding to the IRQ vector */
9778 eq = phba->sli4_hba.hba_eq_hdl[qidx].eq;
9779 lpfc_eq_destroy(phba, eq);
cdb42bec
JS
9780 }
9781 }
895427bd 9782
6a828b0f
JS
9783 kfree(phba->sli4_hba.cq_lookup);
9784 phba->sli4_hba.cq_lookup = NULL;
9785 phba->sli4_hba.cq_max = 0;
da0436e9
JS
9786}
9787
9788/**
9789 * lpfc_sli4_cq_event_pool_create - Create completion-queue event free pool
9790 * @phba: pointer to lpfc hba data structure.
9791 *
9792 * This routine is invoked to allocate and set up a pool of completion queue
9793 * events. The body of the completion queue event is a completion queue entry
9794 * CQE. For now, this pool is used for the interrupt service routine to queue
9795 * the following HBA completion queue events for the worker thread to process:
9796 * - Mailbox asynchronous events
9797 * - Receive queue completion unsolicited events
9798 * Later, this can be used for all the slow-path events.
9799 *
9800 * Return codes
af901ca1 9801 * 0 - successful
25985edc 9802 * -ENOMEM - No available memory
da0436e9
JS
9803 **/
9804static int
9805lpfc_sli4_cq_event_pool_create(struct lpfc_hba *phba)
9806{
9807 struct lpfc_cq_event *cq_event;
9808 int i;
9809
9810 for (i = 0; i < (4 * phba->sli4_hba.cq_ecount); i++) {
9811 cq_event = kmalloc(sizeof(struct lpfc_cq_event), GFP_KERNEL);
9812 if (!cq_event)
9813 goto out_pool_create_fail;
9814 list_add_tail(&cq_event->list,
9815 &phba->sli4_hba.sp_cqe_event_pool);
9816 }
9817 return 0;
9818
9819out_pool_create_fail:
9820 lpfc_sli4_cq_event_pool_destroy(phba);
9821 return -ENOMEM;
9822}
9823
9824/**
9825 * lpfc_sli4_cq_event_pool_destroy - Free completion-queue event free pool
9826 * @phba: pointer to lpfc hba data structure.
9827 *
9828 * This routine is invoked to free the pool of completion queue events at
9829 * driver unload time. Note that, it is the responsibility of the driver
9830 * cleanup routine to free all the outstanding completion-queue events
9831 * allocated from this pool back into the pool before invoking this routine
9832 * to destroy the pool.
9833 **/
9834static void
9835lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *phba)
9836{
9837 struct lpfc_cq_event *cq_event, *next_cq_event;
9838
9839 list_for_each_entry_safe(cq_event, next_cq_event,
9840 &phba->sli4_hba.sp_cqe_event_pool, list) {
9841 list_del(&cq_event->list);
9842 kfree(cq_event);
9843 }
9844}
9845
9846/**
9847 * __lpfc_sli4_cq_event_alloc - Allocate a completion-queue event from free pool
9848 * @phba: pointer to lpfc hba data structure.
9849 *
9850 * This routine is the lock free version of the API invoked to allocate a
9851 * completion-queue event from the free pool.
9852 *
9853 * Return: Pointer to the newly allocated completion-queue event if successful
9854 * NULL otherwise.
9855 **/
9856struct lpfc_cq_event *
9857__lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
9858{
9859 struct lpfc_cq_event *cq_event = NULL;
9860
9861 list_remove_head(&phba->sli4_hba.sp_cqe_event_pool, cq_event,
9862 struct lpfc_cq_event, list);
9863 return cq_event;
9864}
9865
9866/**
9867 * lpfc_sli4_cq_event_alloc - Allocate a completion-queue event from free pool
9868 * @phba: pointer to lpfc hba data structure.
9869 *
9870 * This routine is the lock version of the API invoked to allocate a
9871 * completion-queue event from the free pool.
9872 *
9873 * Return: Pointer to the newly allocated completion-queue event if successful
9874 * NULL otherwise.
9875 **/
9876struct lpfc_cq_event *
9877lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
9878{
9879 struct lpfc_cq_event *cq_event;
9880 unsigned long iflags;
9881
9882 spin_lock_irqsave(&phba->hbalock, iflags);
9883 cq_event = __lpfc_sli4_cq_event_alloc(phba);
9884 spin_unlock_irqrestore(&phba->hbalock, iflags);
9885 return cq_event;
9886}
9887
9888/**
9889 * __lpfc_sli4_cq_event_release - Release a completion-queue event to free pool
9890 * @phba: pointer to lpfc hba data structure.
9891 * @cq_event: pointer to the completion queue event to be freed.
9892 *
9893 * This routine is the lock free version of the API invoked to release a
9894 * completion-queue event back into the free pool.
9895 **/
9896void
9897__lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
9898 struct lpfc_cq_event *cq_event)
9899{
9900 list_add_tail(&cq_event->list, &phba->sli4_hba.sp_cqe_event_pool);
9901}
9902
9903/**
9904 * lpfc_sli4_cq_event_release - Release a completion-queue event to free pool
9905 * @phba: pointer to lpfc hba data structure.
9906 * @cq_event: pointer to the completion queue event to be freed.
9907 *
9908 * This routine is the lock version of the API invoked to release a
9909 * completion-queue event back into the free pool.
9910 **/
9911void
9912lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
9913 struct lpfc_cq_event *cq_event)
9914{
9915 unsigned long iflags;
9916 spin_lock_irqsave(&phba->hbalock, iflags);
9917 __lpfc_sli4_cq_event_release(phba, cq_event);
9918 spin_unlock_irqrestore(&phba->hbalock, iflags);
9919}
9920
9921/**
9922 * lpfc_sli4_cq_event_release_all - Release all cq events to the free pool
9923 * @phba: pointer to lpfc hba data structure.
9924 *
9925 * This routine is to free all the pending completion-queue events to the
9926 * back into the free pool for device reset.
9927 **/
9928static void
9929lpfc_sli4_cq_event_release_all(struct lpfc_hba *phba)
9930{
9931 LIST_HEAD(cqelist);
9932 struct lpfc_cq_event *cqe;
9933 unsigned long iflags;
9934
9935 /* Retrieve all the pending WCQEs from pending WCQE lists */
9936 spin_lock_irqsave(&phba->hbalock, iflags);
9937 /* Pending FCP XRI abort events */
9938 list_splice_init(&phba->sli4_hba.sp_fcp_xri_aborted_work_queue,
9939 &cqelist);
9940 /* Pending ELS XRI abort events */
9941 list_splice_init(&phba->sli4_hba.sp_els_xri_aborted_work_queue,
9942 &cqelist);
9943 /* Pending asynnc events */
9944 list_splice_init(&phba->sli4_hba.sp_asynce_work_queue,
9945 &cqelist);
9946 spin_unlock_irqrestore(&phba->hbalock, iflags);
9947
9948 while (!list_empty(&cqelist)) {
9949 list_remove_head(&cqelist, cqe, struct lpfc_cq_event, list);
9950 lpfc_sli4_cq_event_release(phba, cqe);
9951 }
9952}
9953
9954/**
9955 * lpfc_pci_function_reset - Reset pci function.
9956 * @phba: pointer to lpfc hba data structure.
9957 *
9958 * This routine is invoked to request a PCI function reset. It will destroys
9959 * all resources assigned to the PCI function which originates this request.
9960 *
9961 * Return codes
af901ca1 9962 * 0 - successful
25985edc 9963 * -ENOMEM - No available memory
d439d286 9964 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9965 **/
9966int
9967lpfc_pci_function_reset(struct lpfc_hba *phba)
9968{
9969 LPFC_MBOXQ_t *mboxq;
2fcee4bf 9970 uint32_t rc = 0, if_type;
da0436e9 9971 uint32_t shdr_status, shdr_add_status;
2f6fa2c9
JS
9972 uint32_t rdy_chk;
9973 uint32_t port_reset = 0;
da0436e9 9974 union lpfc_sli4_cfg_shdr *shdr;
2fcee4bf 9975 struct lpfc_register reg_data;
2b81f942 9976 uint16_t devid;
da0436e9 9977
2fcee4bf
JS
9978 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
9979 switch (if_type) {
9980 case LPFC_SLI_INTF_IF_TYPE_0:
9981 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
9982 GFP_KERNEL);
9983 if (!mboxq) {
9984 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9985 "0494 Unable to allocate memory for "
9986 "issuing SLI_FUNCTION_RESET mailbox "
9987 "command\n");
9988 return -ENOMEM;
9989 }
da0436e9 9990
2fcee4bf
JS
9991 /* Setup PCI function reset mailbox-ioctl command */
9992 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
9993 LPFC_MBOX_OPCODE_FUNCTION_RESET, 0,
9994 LPFC_SLI4_MBX_EMBED);
9995 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9996 shdr = (union lpfc_sli4_cfg_shdr *)
9997 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
9998 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
9999 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status,
10000 &shdr->response);
10001 if (rc != MBX_TIMEOUT)
10002 mempool_free(mboxq, phba->mbox_mem_pool);
10003 if (shdr_status || shdr_add_status || rc) {
10004 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10005 "0495 SLI_FUNCTION_RESET mailbox "
10006 "failed with status x%x add_status x%x,"
10007 " mbx status x%x\n",
10008 shdr_status, shdr_add_status, rc);
10009 rc = -ENXIO;
10010 }
10011 break;
10012 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 10013 case LPFC_SLI_INTF_IF_TYPE_6:
2f6fa2c9
JS
10014wait:
10015 /*
10016 * Poll the Port Status Register and wait for RDY for
10017 * up to 30 seconds. If the port doesn't respond, treat
10018 * it as an error.
10019 */
77d093fb 10020 for (rdy_chk = 0; rdy_chk < 1500; rdy_chk++) {
2f6fa2c9
JS
10021 if (lpfc_readl(phba->sli4_hba.u.if_type2.
10022 STATUSregaddr, &reg_data.word0)) {
10023 rc = -ENODEV;
10024 goto out;
10025 }
10026 if (bf_get(lpfc_sliport_status_rdy, &reg_data))
10027 break;
10028 msleep(20);
10029 }
10030
10031 if (!bf_get(lpfc_sliport_status_rdy, &reg_data)) {
10032 phba->work_status[0] = readl(
10033 phba->sli4_hba.u.if_type2.ERR1regaddr);
10034 phba->work_status[1] = readl(
10035 phba->sli4_hba.u.if_type2.ERR2regaddr);
10036 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10037 "2890 Port not ready, port status reg "
10038 "0x%x error 1=0x%x, error 2=0x%x\n",
10039 reg_data.word0,
10040 phba->work_status[0],
10041 phba->work_status[1]);
10042 rc = -ENODEV;
10043 goto out;
10044 }
10045
10046 if (!port_reset) {
10047 /*
10048 * Reset the port now
10049 */
2fcee4bf
JS
10050 reg_data.word0 = 0;
10051 bf_set(lpfc_sliport_ctrl_end, &reg_data,
10052 LPFC_SLIPORT_LITTLE_ENDIAN);
10053 bf_set(lpfc_sliport_ctrl_ip, &reg_data,
10054 LPFC_SLIPORT_INIT_PORT);
10055 writel(reg_data.word0, phba->sli4_hba.u.if_type2.
10056 CTRLregaddr);
8fcb8acd 10057 /* flush */
2b81f942
JS
10058 pci_read_config_word(phba->pcidev,
10059 PCI_DEVICE_ID, &devid);
2fcee4bf 10060
2f6fa2c9
JS
10061 port_reset = 1;
10062 msleep(20);
10063 goto wait;
10064 } else if (bf_get(lpfc_sliport_status_rn, &reg_data)) {
10065 rc = -ENODEV;
10066 goto out;
2fcee4bf
JS
10067 }
10068 break;
2f6fa2c9 10069
2fcee4bf
JS
10070 case LPFC_SLI_INTF_IF_TYPE_1:
10071 default:
10072 break;
da0436e9 10073 }
2fcee4bf 10074
73d91e50 10075out:
2fcee4bf 10076 /* Catch the not-ready port failure after a port reset. */
2f6fa2c9 10077 if (rc) {
229adb0e
JS
10078 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10079 "3317 HBA not functional: IP Reset Failed "
2f6fa2c9 10080 "try: echo fw_reset > board_mode\n");
2fcee4bf 10081 rc = -ENODEV;
229adb0e 10082 }
2fcee4bf 10083
da0436e9
JS
10084 return rc;
10085}
10086
da0436e9
JS
10087/**
10088 * lpfc_sli4_pci_mem_setup - Setup SLI4 HBA PCI memory space.
10089 * @phba: pointer to lpfc hba data structure.
10090 *
10091 * This routine is invoked to set up the PCI device memory space for device
10092 * with SLI-4 interface spec.
10093 *
10094 * Return codes
af901ca1 10095 * 0 - successful
da0436e9
JS
10096 * other values - error
10097 **/
10098static int
10099lpfc_sli4_pci_mem_setup(struct lpfc_hba *phba)
10100{
f30e1bfd 10101 struct pci_dev *pdev = phba->pcidev;
da0436e9 10102 unsigned long bar0map_len, bar1map_len, bar2map_len;
3a487ff7 10103 int error;
2fcee4bf 10104 uint32_t if_type;
da0436e9 10105
f30e1bfd 10106 if (!pdev)
56de8357 10107 return -ENODEV;
da0436e9
JS
10108
10109 /* Set the device DMA mask size */
56de8357
HR
10110 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
10111 if (error)
10112 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10113 if (error)
f30e1bfd 10114 return error;
da0436e9 10115
2fcee4bf
JS
10116 /*
10117 * The BARs and register set definitions and offset locations are
10118 * dependent on the if_type.
10119 */
10120 if (pci_read_config_dword(pdev, LPFC_SLI_INTF,
10121 &phba->sli4_hba.sli_intf.word0)) {
3a487ff7 10122 return -ENODEV;
2fcee4bf
JS
10123 }
10124
10125 /* There is no SLI3 failback for SLI4 devices. */
10126 if (bf_get(lpfc_sli_intf_valid, &phba->sli4_hba.sli_intf) !=
10127 LPFC_SLI_INTF_VALID) {
10128 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10129 "2894 SLI_INTF reg contents invalid "
10130 "sli_intf reg 0x%x\n",
10131 phba->sli4_hba.sli_intf.word0);
3a487ff7 10132 return -ENODEV;
2fcee4bf
JS
10133 }
10134
10135 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
10136 /*
10137 * Get the bus address of SLI4 device Bar regions and the
10138 * number of bytes required by each mapping. The mapping of the
10139 * particular PCI BARs regions is dependent on the type of
10140 * SLI4 device.
da0436e9 10141 */
f5ca6f2e
JS
10142 if (pci_resource_start(pdev, PCI_64BIT_BAR0)) {
10143 phba->pci_bar0_map = pci_resource_start(pdev, PCI_64BIT_BAR0);
10144 bar0map_len = pci_resource_len(pdev, PCI_64BIT_BAR0);
2fcee4bf
JS
10145
10146 /*
10147 * Map SLI4 PCI Config Space Register base to a kernel virtual
10148 * addr
10149 */
10150 phba->sli4_hba.conf_regs_memmap_p =
10151 ioremap(phba->pci_bar0_map, bar0map_len);
10152 if (!phba->sli4_hba.conf_regs_memmap_p) {
10153 dev_printk(KERN_ERR, &pdev->dev,
10154 "ioremap failed for SLI4 PCI config "
10155 "registers.\n");
3a487ff7 10156 return -ENODEV;
2fcee4bf 10157 }
f5ca6f2e 10158 phba->pci_bar0_memmap_p = phba->sli4_hba.conf_regs_memmap_p;
2fcee4bf
JS
10159 /* Set up BAR0 PCI config space register memory map */
10160 lpfc_sli4_bar0_register_memmap(phba, if_type);
1dfb5a47
JS
10161 } else {
10162 phba->pci_bar0_map = pci_resource_start(pdev, 1);
10163 bar0map_len = pci_resource_len(pdev, 1);
27d6ac0a 10164 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
2fcee4bf
JS
10165 dev_printk(KERN_ERR, &pdev->dev,
10166 "FATAL - No BAR0 mapping for SLI4, if_type 2\n");
3a487ff7 10167 return -ENODEV;
2fcee4bf
JS
10168 }
10169 phba->sli4_hba.conf_regs_memmap_p =
da0436e9 10170 ioremap(phba->pci_bar0_map, bar0map_len);
2fcee4bf
JS
10171 if (!phba->sli4_hba.conf_regs_memmap_p) {
10172 dev_printk(KERN_ERR, &pdev->dev,
10173 "ioremap failed for SLI4 PCI config "
10174 "registers.\n");
3a487ff7 10175 return -ENODEV;
2fcee4bf
JS
10176 }
10177 lpfc_sli4_bar0_register_memmap(phba, if_type);
da0436e9
JS
10178 }
10179
e4b9794e
JS
10180 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
10181 if (pci_resource_start(pdev, PCI_64BIT_BAR2)) {
10182 /*
10183 * Map SLI4 if type 0 HBA Control Register base to a
10184 * kernel virtual address and setup the registers.
10185 */
10186 phba->pci_bar1_map = pci_resource_start(pdev,
10187 PCI_64BIT_BAR2);
10188 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
10189 phba->sli4_hba.ctrl_regs_memmap_p =
10190 ioremap(phba->pci_bar1_map,
10191 bar1map_len);
10192 if (!phba->sli4_hba.ctrl_regs_memmap_p) {
10193 dev_err(&pdev->dev,
10194 "ioremap failed for SLI4 HBA "
10195 "control registers.\n");
10196 error = -ENOMEM;
10197 goto out_iounmap_conf;
10198 }
10199 phba->pci_bar2_memmap_p =
10200 phba->sli4_hba.ctrl_regs_memmap_p;
27d6ac0a 10201 lpfc_sli4_bar1_register_memmap(phba, if_type);
e4b9794e
JS
10202 } else {
10203 error = -ENOMEM;
2fcee4bf
JS
10204 goto out_iounmap_conf;
10205 }
da0436e9
JS
10206 }
10207
27d6ac0a
JS
10208 if ((if_type == LPFC_SLI_INTF_IF_TYPE_6) &&
10209 (pci_resource_start(pdev, PCI_64BIT_BAR2))) {
10210 /*
10211 * Map SLI4 if type 6 HBA Doorbell Register base to a kernel
10212 * virtual address and setup the registers.
10213 */
10214 phba->pci_bar1_map = pci_resource_start(pdev, PCI_64BIT_BAR2);
10215 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
10216 phba->sli4_hba.drbl_regs_memmap_p =
10217 ioremap(phba->pci_bar1_map, bar1map_len);
10218 if (!phba->sli4_hba.drbl_regs_memmap_p) {
10219 dev_err(&pdev->dev,
10220 "ioremap failed for SLI4 HBA doorbell registers.\n");
3a487ff7 10221 error = -ENOMEM;
27d6ac0a
JS
10222 goto out_iounmap_conf;
10223 }
10224 phba->pci_bar2_memmap_p = phba->sli4_hba.drbl_regs_memmap_p;
10225 lpfc_sli4_bar1_register_memmap(phba, if_type);
10226 }
10227
e4b9794e
JS
10228 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
10229 if (pci_resource_start(pdev, PCI_64BIT_BAR4)) {
10230 /*
10231 * Map SLI4 if type 0 HBA Doorbell Register base to
10232 * a kernel virtual address and setup the registers.
10233 */
10234 phba->pci_bar2_map = pci_resource_start(pdev,
10235 PCI_64BIT_BAR4);
10236 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
10237 phba->sli4_hba.drbl_regs_memmap_p =
10238 ioremap(phba->pci_bar2_map,
10239 bar2map_len);
10240 if (!phba->sli4_hba.drbl_regs_memmap_p) {
10241 dev_err(&pdev->dev,
10242 "ioremap failed for SLI4 HBA"
10243 " doorbell registers.\n");
10244 error = -ENOMEM;
10245 goto out_iounmap_ctrl;
10246 }
10247 phba->pci_bar4_memmap_p =
10248 phba->sli4_hba.drbl_regs_memmap_p;
10249 error = lpfc_sli4_bar2_register_memmap(phba, LPFC_VF0);
10250 if (error)
10251 goto out_iounmap_all;
10252 } else {
10253 error = -ENOMEM;
2fcee4bf 10254 goto out_iounmap_all;
e4b9794e 10255 }
da0436e9
JS
10256 }
10257
1351e69f
JS
10258 if (if_type == LPFC_SLI_INTF_IF_TYPE_6 &&
10259 pci_resource_start(pdev, PCI_64BIT_BAR4)) {
10260 /*
10261 * Map SLI4 if type 6 HBA DPP Register base to a kernel
10262 * virtual address and setup the registers.
10263 */
10264 phba->pci_bar2_map = pci_resource_start(pdev, PCI_64BIT_BAR4);
10265 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
10266 phba->sli4_hba.dpp_regs_memmap_p =
10267 ioremap(phba->pci_bar2_map, bar2map_len);
10268 if (!phba->sli4_hba.dpp_regs_memmap_p) {
10269 dev_err(&pdev->dev,
10270 "ioremap failed for SLI4 HBA dpp registers.\n");
3a487ff7 10271 error = -ENOMEM;
1351e69f
JS
10272 goto out_iounmap_ctrl;
10273 }
10274 phba->pci_bar4_memmap_p = phba->sli4_hba.dpp_regs_memmap_p;
10275 }
10276
b71413dd 10277 /* Set up the EQ/CQ register handeling functions now */
27d6ac0a
JS
10278 switch (if_type) {
10279 case LPFC_SLI_INTF_IF_TYPE_0:
10280 case LPFC_SLI_INTF_IF_TYPE_2:
b71413dd 10281 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_eq_clr_intr;
32517fc0
JS
10282 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_write_eq_db;
10283 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_write_cq_db;
27d6ac0a
JS
10284 break;
10285 case LPFC_SLI_INTF_IF_TYPE_6:
10286 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_if6_eq_clr_intr;
32517fc0
JS
10287 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_if6_write_eq_db;
10288 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_if6_write_cq_db;
27d6ac0a
JS
10289 break;
10290 default:
10291 break;
b71413dd
JS
10292 }
10293
da0436e9
JS
10294 return 0;
10295
10296out_iounmap_all:
10297 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10298out_iounmap_ctrl:
10299 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
10300out_iounmap_conf:
10301 iounmap(phba->sli4_hba.conf_regs_memmap_p);
3a487ff7 10302
da0436e9
JS
10303 return error;
10304}
10305
10306/**
10307 * lpfc_sli4_pci_mem_unset - Unset SLI4 HBA PCI memory space.
10308 * @phba: pointer to lpfc hba data structure.
10309 *
10310 * This routine is invoked to unset the PCI device memory space for device
10311 * with SLI-4 interface spec.
10312 **/
10313static void
10314lpfc_sli4_pci_mem_unset(struct lpfc_hba *phba)
10315{
2e90f4b5
JS
10316 uint32_t if_type;
10317 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
da0436e9 10318
2e90f4b5
JS
10319 switch (if_type) {
10320 case LPFC_SLI_INTF_IF_TYPE_0:
10321 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10322 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
10323 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10324 break;
10325 case LPFC_SLI_INTF_IF_TYPE_2:
10326 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10327 break;
27d6ac0a
JS
10328 case LPFC_SLI_INTF_IF_TYPE_6:
10329 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10330 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10331 break;
2e90f4b5
JS
10332 case LPFC_SLI_INTF_IF_TYPE_1:
10333 default:
10334 dev_printk(KERN_ERR, &phba->pcidev->dev,
10335 "FATAL - unsupported SLI4 interface type - %d\n",
10336 if_type);
10337 break;
10338 }
da0436e9
JS
10339}
10340
10341/**
10342 * lpfc_sli_enable_msix - Enable MSI-X interrupt mode on SLI-3 device
10343 * @phba: pointer to lpfc hba data structure.
10344 *
10345 * This routine is invoked to enable the MSI-X interrupt vectors to device
45ffac19 10346 * with SLI-3 interface specs.
da0436e9
JS
10347 *
10348 * Return codes
af901ca1 10349 * 0 - successful
da0436e9
JS
10350 * other values - error
10351 **/
10352static int
10353lpfc_sli_enable_msix(struct lpfc_hba *phba)
10354{
45ffac19 10355 int rc;
da0436e9
JS
10356 LPFC_MBOXQ_t *pmb;
10357
10358 /* Set up MSI-X multi-message vectors */
45ffac19
CH
10359 rc = pci_alloc_irq_vectors(phba->pcidev,
10360 LPFC_MSIX_VECTORS, LPFC_MSIX_VECTORS, PCI_IRQ_MSIX);
10361 if (rc < 0) {
da0436e9
JS
10362 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10363 "0420 PCI enable MSI-X failed (%d)\n", rc);
029165ac 10364 goto vec_fail_out;
da0436e9 10365 }
45ffac19 10366
da0436e9
JS
10367 /*
10368 * Assign MSI-X vectors to interrupt handlers
10369 */
10370
10371 /* vector-0 is associated to slow-path handler */
45ffac19 10372 rc = request_irq(pci_irq_vector(phba->pcidev, 0),
ed243d37 10373 &lpfc_sli_sp_intr_handler, 0,
da0436e9
JS
10374 LPFC_SP_DRIVER_HANDLER_NAME, phba);
10375 if (rc) {
10376 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10377 "0421 MSI-X slow-path request_irq failed "
10378 "(%d)\n", rc);
10379 goto msi_fail_out;
10380 }
10381
10382 /* vector-1 is associated to fast-path handler */
45ffac19 10383 rc = request_irq(pci_irq_vector(phba->pcidev, 1),
ed243d37 10384 &lpfc_sli_fp_intr_handler, 0,
da0436e9
JS
10385 LPFC_FP_DRIVER_HANDLER_NAME, phba);
10386
10387 if (rc) {
10388 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10389 "0429 MSI-X fast-path request_irq failed "
10390 "(%d)\n", rc);
10391 goto irq_fail_out;
10392 }
10393
10394 /*
10395 * Configure HBA MSI-X attention conditions to messages
10396 */
10397 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
10398
10399 if (!pmb) {
10400 rc = -ENOMEM;
10401 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10402 "0474 Unable to allocate memory for issuing "
10403 "MBOX_CONFIG_MSI command\n");
10404 goto mem_fail_out;
10405 }
10406 rc = lpfc_config_msi(phba, pmb);
10407 if (rc)
10408 goto mbx_fail_out;
10409 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
10410 if (rc != MBX_SUCCESS) {
10411 lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX,
10412 "0351 Config MSI mailbox command failed, "
10413 "mbxCmd x%x, mbxStatus x%x\n",
10414 pmb->u.mb.mbxCommand, pmb->u.mb.mbxStatus);
10415 goto mbx_fail_out;
10416 }
10417
10418 /* Free memory allocated for mailbox command */
10419 mempool_free(pmb, phba->mbox_mem_pool);
10420 return rc;
10421
10422mbx_fail_out:
10423 /* Free memory allocated for mailbox command */
10424 mempool_free(pmb, phba->mbox_mem_pool);
10425
10426mem_fail_out:
10427 /* free the irq already requested */
45ffac19 10428 free_irq(pci_irq_vector(phba->pcidev, 1), phba);
da0436e9
JS
10429
10430irq_fail_out:
10431 /* free the irq already requested */
45ffac19 10432 free_irq(pci_irq_vector(phba->pcidev, 0), phba);
da0436e9
JS
10433
10434msi_fail_out:
10435 /* Unconfigure MSI-X capability structure */
45ffac19 10436 pci_free_irq_vectors(phba->pcidev);
029165ac
AG
10437
10438vec_fail_out:
da0436e9
JS
10439 return rc;
10440}
10441
da0436e9
JS
10442/**
10443 * lpfc_sli_enable_msi - Enable MSI interrupt mode on SLI-3 device.
10444 * @phba: pointer to lpfc hba data structure.
10445 *
10446 * This routine is invoked to enable the MSI interrupt mode to device with
10447 * SLI-3 interface spec. The kernel function pci_enable_msi() is called to
10448 * enable the MSI vector. The device driver is responsible for calling the
10449 * request_irq() to register MSI vector with a interrupt the handler, which
10450 * is done in this function.
10451 *
10452 * Return codes
af901ca1 10453 * 0 - successful
da0436e9
JS
10454 * other values - error
10455 */
10456static int
10457lpfc_sli_enable_msi(struct lpfc_hba *phba)
10458{
10459 int rc;
10460
10461 rc = pci_enable_msi(phba->pcidev);
10462 if (!rc)
10463 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10464 "0462 PCI enable MSI mode success.\n");
10465 else {
10466 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10467 "0471 PCI enable MSI mode failed (%d)\n", rc);
10468 return rc;
10469 }
10470
10471 rc = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
ed243d37 10472 0, LPFC_DRIVER_NAME, phba);
da0436e9
JS
10473 if (rc) {
10474 pci_disable_msi(phba->pcidev);
10475 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10476 "0478 MSI request_irq failed (%d)\n", rc);
10477 }
10478 return rc;
10479}
10480
da0436e9
JS
10481/**
10482 * lpfc_sli_enable_intr - Enable device interrupt to SLI-3 device.
10483 * @phba: pointer to lpfc hba data structure.
10484 *
10485 * This routine is invoked to enable device interrupt and associate driver's
10486 * interrupt handler(s) to interrupt vector(s) to device with SLI-3 interface
10487 * spec. Depends on the interrupt mode configured to the driver, the driver
10488 * will try to fallback from the configured interrupt mode to an interrupt
10489 * mode which is supported by the platform, kernel, and device in the order
10490 * of:
10491 * MSI-X -> MSI -> IRQ.
10492 *
10493 * Return codes
af901ca1 10494 * 0 - successful
da0436e9
JS
10495 * other values - error
10496 **/
10497static uint32_t
10498lpfc_sli_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
10499{
10500 uint32_t intr_mode = LPFC_INTR_ERROR;
10501 int retval;
10502
10503 if (cfg_mode == 2) {
10504 /* Need to issue conf_port mbox cmd before conf_msi mbox cmd */
10505 retval = lpfc_sli_config_port(phba, LPFC_SLI_REV3);
10506 if (!retval) {
10507 /* Now, try to enable MSI-X interrupt mode */
10508 retval = lpfc_sli_enable_msix(phba);
10509 if (!retval) {
10510 /* Indicate initialization to MSI-X mode */
10511 phba->intr_type = MSIX;
10512 intr_mode = 2;
10513 }
10514 }
10515 }
10516
10517 /* Fallback to MSI if MSI-X initialization failed */
10518 if (cfg_mode >= 1 && phba->intr_type == NONE) {
10519 retval = lpfc_sli_enable_msi(phba);
10520 if (!retval) {
10521 /* Indicate initialization to MSI mode */
10522 phba->intr_type = MSI;
10523 intr_mode = 1;
10524 }
10525 }
10526
10527 /* Fallback to INTx if both MSI-X/MSI initalization failed */
10528 if (phba->intr_type == NONE) {
10529 retval = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
10530 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
10531 if (!retval) {
10532 /* Indicate initialization to INTx mode */
10533 phba->intr_type = INTx;
10534 intr_mode = 0;
10535 }
10536 }
10537 return intr_mode;
10538}
10539
10540/**
10541 * lpfc_sli_disable_intr - Disable device interrupt to SLI-3 device.
10542 * @phba: pointer to lpfc hba data structure.
10543 *
10544 * This routine is invoked to disable device interrupt and disassociate the
10545 * driver's interrupt handler(s) from interrupt vector(s) to device with
10546 * SLI-3 interface spec. Depending on the interrupt mode, the driver will
10547 * release the interrupt vector(s) for the message signaled interrupt.
10548 **/
10549static void
10550lpfc_sli_disable_intr(struct lpfc_hba *phba)
10551{
45ffac19
CH
10552 int nr_irqs, i;
10553
da0436e9 10554 if (phba->intr_type == MSIX)
45ffac19
CH
10555 nr_irqs = LPFC_MSIX_VECTORS;
10556 else
10557 nr_irqs = 1;
10558
10559 for (i = 0; i < nr_irqs; i++)
10560 free_irq(pci_irq_vector(phba->pcidev, i), phba);
10561 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
10562
10563 /* Reset interrupt management states */
10564 phba->intr_type = NONE;
10565 phba->sli.slistat.sli_intr = 0;
da0436e9
JS
10566}
10567
6a828b0f 10568/**
657add4e 10569 * lpfc_find_cpu_handle - Find the CPU that corresponds to the specified Queue
6a828b0f
JS
10570 * @phba: pointer to lpfc hba data structure.
10571 * @id: EQ vector index or Hardware Queue index
10572 * @match: LPFC_FIND_BY_EQ = match by EQ
10573 * LPFC_FIND_BY_HDWQ = match by Hardware Queue
657add4e 10574 * Return the CPU that matches the selection criteria
6a828b0f
JS
10575 */
10576static uint16_t
10577lpfc_find_cpu_handle(struct lpfc_hba *phba, uint16_t id, int match)
10578{
10579 struct lpfc_vector_map_info *cpup;
10580 int cpu;
10581
657add4e 10582 /* Loop through all CPUs */
222e9239
JS
10583 for_each_present_cpu(cpu) {
10584 cpup = &phba->sli4_hba.cpu_map[cpu];
657add4e
JS
10585
10586 /* If we are matching by EQ, there may be multiple CPUs using
10587 * using the same vector, so select the one with
10588 * LPFC_CPU_FIRST_IRQ set.
10589 */
6a828b0f 10590 if ((match == LPFC_FIND_BY_EQ) &&
657add4e 10591 (cpup->flag & LPFC_CPU_FIRST_IRQ) &&
6a828b0f
JS
10592 (cpup->irq != LPFC_VECTOR_MAP_EMPTY) &&
10593 (cpup->eq == id))
10594 return cpu;
657add4e
JS
10595
10596 /* If matching by HDWQ, select the first CPU that matches */
6a828b0f
JS
10597 if ((match == LPFC_FIND_BY_HDWQ) && (cpup->hdwq == id))
10598 return cpu;
6a828b0f
JS
10599 }
10600 return 0;
10601}
10602
6a828b0f
JS
10603#ifdef CONFIG_X86
10604/**
10605 * lpfc_find_hyper - Determine if the CPU map entry is hyper-threaded
10606 * @phba: pointer to lpfc hba data structure.
10607 * @cpu: CPU map index
10608 * @phys_id: CPU package physical id
10609 * @core_id: CPU core id
10610 */
10611static int
10612lpfc_find_hyper(struct lpfc_hba *phba, int cpu,
10613 uint16_t phys_id, uint16_t core_id)
10614{
10615 struct lpfc_vector_map_info *cpup;
10616 int idx;
10617
222e9239
JS
10618 for_each_present_cpu(idx) {
10619 cpup = &phba->sli4_hba.cpu_map[idx];
6a828b0f
JS
10620 /* Does the cpup match the one we are looking for */
10621 if ((cpup->phys_id == phys_id) &&
10622 (cpup->core_id == core_id) &&
222e9239 10623 (cpu != idx))
6a828b0f 10624 return 1;
6a828b0f
JS
10625 }
10626 return 0;
10627}
10628#endif
10629
7bb03bbf 10630/**
895427bd 10631 * lpfc_cpu_affinity_check - Check vector CPU affinity mappings
7bb03bbf 10632 * @phba: pointer to lpfc hba data structure.
895427bd
JS
10633 * @vectors: number of msix vectors allocated.
10634 *
10635 * The routine will figure out the CPU affinity assignment for every
6a828b0f 10636 * MSI-X vector allocated for the HBA.
895427bd
JS
10637 * In addition, the CPU to IO channel mapping will be calculated
10638 * and the phba->sli4_hba.cpu_map array will reflect this.
7bb03bbf 10639 */
895427bd
JS
10640static void
10641lpfc_cpu_affinity_check(struct lpfc_hba *phba, int vectors)
7bb03bbf 10642{
3ad348d9 10643 int i, cpu, idx, next_idx, new_cpu, start_cpu, first_cpu;
6a828b0f
JS
10644 int max_phys_id, min_phys_id;
10645 int max_core_id, min_core_id;
7bb03bbf 10646 struct lpfc_vector_map_info *cpup;
d9954a2d 10647 struct lpfc_vector_map_info *new_cpup;
75508a8b 10648 const struct cpumask *maskp;
7bb03bbf
JS
10649#ifdef CONFIG_X86
10650 struct cpuinfo_x86 *cpuinfo;
10651#endif
7bb03bbf
JS
10652
10653 /* Init cpu_map array */
d9954a2d
JS
10654 for_each_possible_cpu(cpu) {
10655 cpup = &phba->sli4_hba.cpu_map[cpu];
10656 cpup->phys_id = LPFC_VECTOR_MAP_EMPTY;
10657 cpup->core_id = LPFC_VECTOR_MAP_EMPTY;
10658 cpup->hdwq = LPFC_VECTOR_MAP_EMPTY;
10659 cpup->eq = LPFC_VECTOR_MAP_EMPTY;
10660 cpup->irq = LPFC_VECTOR_MAP_EMPTY;
10661 cpup->flag = 0;
10662 }
7bb03bbf 10663
6a828b0f 10664 max_phys_id = 0;
d9954a2d 10665 min_phys_id = LPFC_VECTOR_MAP_EMPTY;
6a828b0f 10666 max_core_id = 0;
d9954a2d 10667 min_core_id = LPFC_VECTOR_MAP_EMPTY;
7bb03bbf
JS
10668
10669 /* Update CPU map with physical id and core id of each CPU */
222e9239
JS
10670 for_each_present_cpu(cpu) {
10671 cpup = &phba->sli4_hba.cpu_map[cpu];
7bb03bbf
JS
10672#ifdef CONFIG_X86
10673 cpuinfo = &cpu_data(cpu);
10674 cpup->phys_id = cpuinfo->phys_proc_id;
10675 cpup->core_id = cpuinfo->cpu_core_id;
d9954a2d
JS
10676 if (lpfc_find_hyper(phba, cpu, cpup->phys_id, cpup->core_id))
10677 cpup->flag |= LPFC_CPU_MAP_HYPER;
7bb03bbf
JS
10678#else
10679 /* No distinction between CPUs for other platforms */
10680 cpup->phys_id = 0;
6a828b0f 10681 cpup->core_id = cpu;
7bb03bbf 10682#endif
6a828b0f 10683
b3295c2a 10684 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3ad348d9
JS
10685 "3328 CPU %d physid %d coreid %d flag x%x\n",
10686 cpu, cpup->phys_id, cpup->core_id, cpup->flag);
6a828b0f
JS
10687
10688 if (cpup->phys_id > max_phys_id)
10689 max_phys_id = cpup->phys_id;
10690 if (cpup->phys_id < min_phys_id)
10691 min_phys_id = cpup->phys_id;
10692
10693 if (cpup->core_id > max_core_id)
10694 max_core_id = cpup->core_id;
10695 if (cpup->core_id < min_core_id)
10696 min_core_id = cpup->core_id;
7bb03bbf 10697 }
7bb03bbf 10698
32517fc0
JS
10699 for_each_possible_cpu(i) {
10700 struct lpfc_eq_intr_info *eqi =
10701 per_cpu_ptr(phba->sli4_hba.eq_info, i);
10702
10703 INIT_LIST_HEAD(&eqi->list);
10704 eqi->icnt = 0;
10705 }
10706
d9954a2d
JS
10707 /* This loop sets up all CPUs that are affinitized with a
10708 * irq vector assigned to the driver. All affinitized CPUs
657add4e 10709 * will get a link to that vectors IRQ and EQ.
a86c71ba
JS
10710 *
10711 * NULL affinity mask handling:
10712 * If irq count is greater than one, log an error message.
10713 * If the null mask is received for the first irq, find the
10714 * first present cpu, and assign the eq index to ensure at
10715 * least one EQ is assigned.
d9954a2d 10716 */
75508a8b 10717 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
657add4e 10718 /* Get a CPU mask for all CPUs affinitized to this vector */
75508a8b 10719 maskp = pci_irq_get_affinity(phba->pcidev, idx);
a86c71ba
JS
10720 if (!maskp) {
10721 if (phba->cfg_irq_chann > 1)
10722 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10723 "3329 No affinity mask found "
10724 "for vector %d (%d)\n",
10725 idx, phba->cfg_irq_chann);
10726 if (!idx) {
10727 cpu = cpumask_first(cpu_present_mask);
10728 cpup = &phba->sli4_hba.cpu_map[cpu];
10729 cpup->eq = idx;
10730 cpup->irq = pci_irq_vector(phba->pcidev, idx);
10731 cpup->flag |= LPFC_CPU_FIRST_IRQ;
10732 }
10733 break;
10734 }
75508a8b 10735
657add4e
JS
10736 i = 0;
10737 /* Loop through all CPUs associated with vector idx */
75508a8b 10738 for_each_cpu_and(cpu, maskp, cpu_present_mask) {
657add4e 10739 /* Set the EQ index and IRQ for that vector */
75508a8b 10740 cpup = &phba->sli4_hba.cpu_map[cpu];
6a828b0f 10741 cpup->eq = idx;
6a828b0f
JS
10742 cpup->irq = pci_irq_vector(phba->pcidev, idx);
10743
657add4e
JS
10744 /* If this is the first CPU thats assigned to this
10745 * vector, set LPFC_CPU_FIRST_IRQ.
10746 */
10747 if (!i)
10748 cpup->flag |= LPFC_CPU_FIRST_IRQ;
10749 i++;
3ad348d9
JS
10750
10751 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10752 "3336 Set Affinity: CPU %d "
10753 "irq %d eq %d flag x%x\n",
10754 cpu, cpup->irq, cpup->eq, cpup->flag);
6a828b0f 10755 }
b3295c2a 10756 }
d9954a2d
JS
10757
10758 /* After looking at each irq vector assigned to this pcidev, its
10759 * possible to see that not ALL CPUs have been accounted for.
657add4e
JS
10760 * Next we will set any unassigned (unaffinitized) cpu map
10761 * entries to a IRQ on the same phys_id.
d9954a2d
JS
10762 */
10763 first_cpu = cpumask_first(cpu_present_mask);
10764 start_cpu = first_cpu;
10765
10766 for_each_present_cpu(cpu) {
10767 cpup = &phba->sli4_hba.cpu_map[cpu];
10768
10769 /* Is this CPU entry unassigned */
10770 if (cpup->eq == LPFC_VECTOR_MAP_EMPTY) {
10771 /* Mark CPU as IRQ not assigned by the kernel */
10772 cpup->flag |= LPFC_CPU_MAP_UNASSIGN;
10773
657add4e 10774 /* If so, find a new_cpup thats on the the SAME
d9954a2d
JS
10775 * phys_id as cpup. start_cpu will start where we
10776 * left off so all unassigned entries don't get assgined
10777 * the IRQ of the first entry.
10778 */
10779 new_cpu = start_cpu;
10780 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
10781 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
10782 if (!(new_cpup->flag & LPFC_CPU_MAP_UNASSIGN) &&
10783 (new_cpup->irq != LPFC_VECTOR_MAP_EMPTY) &&
10784 (new_cpup->phys_id == cpup->phys_id))
10785 goto found_same;
10786 new_cpu = cpumask_next(
10787 new_cpu, cpu_present_mask);
10788 if (new_cpu == nr_cpumask_bits)
10789 new_cpu = first_cpu;
10790 }
10791 /* At this point, we leave the CPU as unassigned */
10792 continue;
10793found_same:
10794 /* We found a matching phys_id, so copy the IRQ info */
10795 cpup->eq = new_cpup->eq;
d9954a2d
JS
10796 cpup->irq = new_cpup->irq;
10797
10798 /* Bump start_cpu to the next slot to minmize the
10799 * chance of having multiple unassigned CPU entries
10800 * selecting the same IRQ.
10801 */
10802 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
10803 if (start_cpu == nr_cpumask_bits)
10804 start_cpu = first_cpu;
10805
657add4e 10806 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
d9954a2d 10807 "3337 Set Affinity: CPU %d "
657add4e 10808 "irq %d from id %d same "
d9954a2d 10809 "phys_id (%d)\n",
657add4e 10810 cpu, cpup->irq, new_cpu, cpup->phys_id);
d9954a2d
JS
10811 }
10812 }
10813
10814 /* Set any unassigned cpu map entries to a IRQ on any phys_id */
10815 start_cpu = first_cpu;
10816
10817 for_each_present_cpu(cpu) {
10818 cpup = &phba->sli4_hba.cpu_map[cpu];
10819
10820 /* Is this entry unassigned */
10821 if (cpup->eq == LPFC_VECTOR_MAP_EMPTY) {
10822 /* Mark it as IRQ not assigned by the kernel */
10823 cpup->flag |= LPFC_CPU_MAP_UNASSIGN;
10824
657add4e 10825 /* If so, find a new_cpup thats on ANY phys_id
d9954a2d
JS
10826 * as the cpup. start_cpu will start where we
10827 * left off so all unassigned entries don't get
10828 * assigned the IRQ of the first entry.
10829 */
10830 new_cpu = start_cpu;
10831 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
10832 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
10833 if (!(new_cpup->flag & LPFC_CPU_MAP_UNASSIGN) &&
10834 (new_cpup->irq != LPFC_VECTOR_MAP_EMPTY))
10835 goto found_any;
10836 new_cpu = cpumask_next(
10837 new_cpu, cpu_present_mask);
10838 if (new_cpu == nr_cpumask_bits)
10839 new_cpu = first_cpu;
10840 }
10841 /* We should never leave an entry unassigned */
10842 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10843 "3339 Set Affinity: CPU %d "
657add4e
JS
10844 "irq %d UNASSIGNED\n",
10845 cpup->hdwq, cpup->irq);
d9954a2d
JS
10846 continue;
10847found_any:
10848 /* We found an available entry, copy the IRQ info */
10849 cpup->eq = new_cpup->eq;
d9954a2d
JS
10850 cpup->irq = new_cpup->irq;
10851
10852 /* Bump start_cpu to the next slot to minmize the
10853 * chance of having multiple unassigned CPU entries
10854 * selecting the same IRQ.
10855 */
10856 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
10857 if (start_cpu == nr_cpumask_bits)
10858 start_cpu = first_cpu;
10859
657add4e 10860 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
d9954a2d 10861 "3338 Set Affinity: CPU %d "
657add4e
JS
10862 "irq %d from id %d (%d/%d)\n",
10863 cpu, cpup->irq, new_cpu,
d9954a2d
JS
10864 new_cpup->phys_id, new_cpup->core_id);
10865 }
10866 }
657add4e 10867
3ad348d9
JS
10868 /* Assign hdwq indices that are unique across all cpus in the map
10869 * that are also FIRST_CPUs.
10870 */
10871 idx = 0;
10872 for_each_present_cpu(cpu) {
10873 cpup = &phba->sli4_hba.cpu_map[cpu];
10874
10875 /* Only FIRST IRQs get a hdwq index assignment. */
10876 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
10877 continue;
10878
10879 /* 1 to 1, the first LPFC_CPU_FIRST_IRQ cpus to a unique hdwq */
10880 cpup->hdwq = idx;
10881 idx++;
10882 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10883 "3333 Set Affinity: CPU %d (phys %d core %d): "
10884 "hdwq %d eq %d irq %d flg x%x\n",
10885 cpu, cpup->phys_id, cpup->core_id,
10886 cpup->hdwq, cpup->eq, cpup->irq, cpup->flag);
10887 }
657add4e
JS
10888 /* Finally we need to associate a hdwq with each cpu_map entry
10889 * This will be 1 to 1 - hdwq to cpu, unless there are less
10890 * hardware queues then CPUs. For that case we will just round-robin
10891 * the available hardware queues as they get assigned to CPUs.
3ad348d9
JS
10892 * The next_idx is the idx from the FIRST_CPU loop above to account
10893 * for irq_chann < hdwq. The idx is used for round-robin assignments
10894 * and needs to start at 0.
657add4e 10895 */
3ad348d9 10896 next_idx = idx;
657add4e 10897 start_cpu = 0;
3ad348d9 10898 idx = 0;
657add4e
JS
10899 for_each_present_cpu(cpu) {
10900 cpup = &phba->sli4_hba.cpu_map[cpu];
657add4e 10901
3ad348d9
JS
10902 /* FIRST cpus are already mapped. */
10903 if (cpup->flag & LPFC_CPU_FIRST_IRQ)
10904 continue;
10905
10906 /* If the cfg_irq_chann < cfg_hdw_queue, set the hdwq
10907 * of the unassigned cpus to the next idx so that all
10908 * hdw queues are fully utilized.
10909 */
10910 if (next_idx < phba->cfg_hdw_queue) {
10911 cpup->hdwq = next_idx;
10912 next_idx++;
10913 continue;
10914 }
10915
10916 /* Not a First CPU and all hdw_queues are used. Reuse a
10917 * Hardware Queue for another CPU, so be smart about it
10918 * and pick one that has its IRQ/EQ mapped to the same phys_id
10919 * (CPU package) and core_id.
10920 */
10921 new_cpu = start_cpu;
10922 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
10923 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
10924 if (new_cpup->hdwq != LPFC_VECTOR_MAP_EMPTY &&
10925 new_cpup->phys_id == cpup->phys_id &&
10926 new_cpup->core_id == cpup->core_id) {
10927 goto found_hdwq;
657add4e 10928 }
3ad348d9
JS
10929 new_cpu = cpumask_next(new_cpu, cpu_present_mask);
10930 if (new_cpu == nr_cpumask_bits)
10931 new_cpu = first_cpu;
10932 }
657add4e 10933
3ad348d9
JS
10934 /* If we can't match both phys_id and core_id,
10935 * settle for just a phys_id match.
10936 */
10937 new_cpu = start_cpu;
10938 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
10939 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
10940 if (new_cpup->hdwq != LPFC_VECTOR_MAP_EMPTY &&
10941 new_cpup->phys_id == cpup->phys_id)
10942 goto found_hdwq;
10943
10944 new_cpu = cpumask_next(new_cpu, cpu_present_mask);
10945 if (new_cpu == nr_cpumask_bits)
10946 new_cpu = first_cpu;
657add4e 10947 }
3ad348d9
JS
10948
10949 /* Otherwise just round robin on cfg_hdw_queue */
10950 cpup->hdwq = idx % phba->cfg_hdw_queue;
10951 idx++;
10952 goto logit;
10953 found_hdwq:
10954 /* We found an available entry, copy the IRQ info */
10955 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
10956 if (start_cpu == nr_cpumask_bits)
10957 start_cpu = first_cpu;
10958 cpup->hdwq = new_cpup->hdwq;
10959 logit:
657add4e
JS
10960 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10961 "3335 Set Affinity: CPU %d (phys %d core %d): "
10962 "hdwq %d eq %d irq %d flg x%x\n",
10963 cpu, cpup->phys_id, cpup->core_id,
10964 cpup->hdwq, cpup->eq, cpup->irq, cpup->flag);
657add4e
JS
10965 }
10966
10967 /* The cpu_map array will be used later during initialization
10968 * when EQ / CQ / WQs are allocated and configured.
10969 */
b3295c2a 10970 return;
7bb03bbf 10971}
7bb03bbf 10972
da0436e9
JS
10973/**
10974 * lpfc_sli4_enable_msix - Enable MSI-X interrupt mode to SLI-4 device
10975 * @phba: pointer to lpfc hba data structure.
10976 *
10977 * This routine is invoked to enable the MSI-X interrupt vectors to device
45ffac19 10978 * with SLI-4 interface spec.
da0436e9
JS
10979 *
10980 * Return codes
af901ca1 10981 * 0 - successful
da0436e9
JS
10982 * other values - error
10983 **/
10984static int
10985lpfc_sli4_enable_msix(struct lpfc_hba *phba)
10986{
75baf696 10987 int vectors, rc, index;
b83d005e 10988 char *name;
da0436e9
JS
10989
10990 /* Set up MSI-X multi-message vectors */
6a828b0f 10991 vectors = phba->cfg_irq_chann;
45ffac19 10992
f358dd0c 10993 rc = pci_alloc_irq_vectors(phba->pcidev,
75508a8b 10994 1,
f358dd0c 10995 vectors, PCI_IRQ_MSIX | PCI_IRQ_AFFINITY);
4f871e1b 10996 if (rc < 0) {
da0436e9
JS
10997 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10998 "0484 PCI enable MSI-X failed (%d)\n", rc);
029165ac 10999 goto vec_fail_out;
da0436e9 11000 }
4f871e1b 11001 vectors = rc;
75baf696 11002
7bb03bbf 11003 /* Assign MSI-X vectors to interrupt handlers */
67d12733 11004 for (index = 0; index < vectors; index++) {
b83d005e
JS
11005 name = phba->sli4_hba.hba_eq_hdl[index].handler_name;
11006 memset(name, 0, LPFC_SLI4_HANDLER_NAME_SZ);
11007 snprintf(name, LPFC_SLI4_HANDLER_NAME_SZ,
4305f183 11008 LPFC_DRIVER_HANDLER_NAME"%d", index);
da0436e9 11009
895427bd
JS
11010 phba->sli4_hba.hba_eq_hdl[index].idx = index;
11011 phba->sli4_hba.hba_eq_hdl[index].phba = phba;
7370d10a
JS
11012 rc = request_irq(pci_irq_vector(phba->pcidev, index),
11013 &lpfc_sli4_hba_intr_handler, 0,
11014 name,
11015 &phba->sli4_hba.hba_eq_hdl[index]);
da0436e9
JS
11016 if (rc) {
11017 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
11018 "0486 MSI-X fast-path (%d) "
11019 "request_irq failed (%d)\n", index, rc);
11020 goto cfg_fail_out;
11021 }
11022 }
11023
6a828b0f 11024 if (vectors != phba->cfg_irq_chann) {
82c3e9ba
JS
11025 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11026 "3238 Reducing IO channels to match number of "
11027 "MSI-X vectors, requested %d got %d\n",
6a828b0f
JS
11028 phba->cfg_irq_chann, vectors);
11029 if (phba->cfg_irq_chann > vectors)
11030 phba->cfg_irq_chann = vectors;
982ab128 11031 if (phba->nvmet_support && (phba->cfg_nvmet_mrq > vectors))
cdb42bec 11032 phba->cfg_nvmet_mrq = vectors;
82c3e9ba 11033 }
7bb03bbf 11034
da0436e9
JS
11035 return rc;
11036
11037cfg_fail_out:
11038 /* free the irq already requested */
895427bd
JS
11039 for (--index; index >= 0; index--)
11040 free_irq(pci_irq_vector(phba->pcidev, index),
11041 &phba->sli4_hba.hba_eq_hdl[index]);
da0436e9 11042
da0436e9 11043 /* Unconfigure MSI-X capability structure */
45ffac19 11044 pci_free_irq_vectors(phba->pcidev);
029165ac
AG
11045
11046vec_fail_out:
da0436e9
JS
11047 return rc;
11048}
11049
da0436e9
JS
11050/**
11051 * lpfc_sli4_enable_msi - Enable MSI interrupt mode to SLI-4 device
11052 * @phba: pointer to lpfc hba data structure.
11053 *
11054 * This routine is invoked to enable the MSI interrupt mode to device with
07b1b914
JS
11055 * SLI-4 interface spec. The kernel function pci_alloc_irq_vectors() is
11056 * called to enable the MSI vector. The device driver is responsible for
11057 * calling the request_irq() to register MSI vector with a interrupt the
11058 * handler, which is done in this function.
da0436e9
JS
11059 *
11060 * Return codes
af901ca1 11061 * 0 - successful
da0436e9
JS
11062 * other values - error
11063 **/
11064static int
11065lpfc_sli4_enable_msi(struct lpfc_hba *phba)
11066{
11067 int rc, index;
11068
07b1b914
JS
11069 rc = pci_alloc_irq_vectors(phba->pcidev, 1, 1,
11070 PCI_IRQ_MSI | PCI_IRQ_AFFINITY);
11071 if (rc > 0)
da0436e9
JS
11072 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11073 "0487 PCI enable MSI mode success.\n");
11074 else {
11075 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11076 "0488 PCI enable MSI mode failed (%d)\n", rc);
07b1b914 11077 return rc ? rc : -1;
da0436e9
JS
11078 }
11079
11080 rc = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
ed243d37 11081 0, LPFC_DRIVER_NAME, phba);
da0436e9 11082 if (rc) {
07b1b914 11083 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
11084 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
11085 "0490 MSI request_irq failed (%d)\n", rc);
75baf696 11086 return rc;
da0436e9
JS
11087 }
11088
6a828b0f 11089 for (index = 0; index < phba->cfg_irq_chann; index++) {
895427bd
JS
11090 phba->sli4_hba.hba_eq_hdl[index].idx = index;
11091 phba->sli4_hba.hba_eq_hdl[index].phba = phba;
da0436e9
JS
11092 }
11093
75baf696 11094 return 0;
da0436e9
JS
11095}
11096
da0436e9
JS
11097/**
11098 * lpfc_sli4_enable_intr - Enable device interrupt to SLI-4 device
11099 * @phba: pointer to lpfc hba data structure.
11100 *
11101 * This routine is invoked to enable device interrupt and associate driver's
11102 * interrupt handler(s) to interrupt vector(s) to device with SLI-4
11103 * interface spec. Depends on the interrupt mode configured to the driver,
11104 * the driver will try to fallback from the configured interrupt mode to an
11105 * interrupt mode which is supported by the platform, kernel, and device in
11106 * the order of:
11107 * MSI-X -> MSI -> IRQ.
11108 *
11109 * Return codes
af901ca1 11110 * 0 - successful
da0436e9
JS
11111 * other values - error
11112 **/
11113static uint32_t
11114lpfc_sli4_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
11115{
11116 uint32_t intr_mode = LPFC_INTR_ERROR;
895427bd 11117 int retval, idx;
da0436e9
JS
11118
11119 if (cfg_mode == 2) {
11120 /* Preparation before conf_msi mbox cmd */
11121 retval = 0;
11122 if (!retval) {
11123 /* Now, try to enable MSI-X interrupt mode */
11124 retval = lpfc_sli4_enable_msix(phba);
11125 if (!retval) {
11126 /* Indicate initialization to MSI-X mode */
11127 phba->intr_type = MSIX;
11128 intr_mode = 2;
11129 }
11130 }
11131 }
11132
11133 /* Fallback to MSI if MSI-X initialization failed */
11134 if (cfg_mode >= 1 && phba->intr_type == NONE) {
11135 retval = lpfc_sli4_enable_msi(phba);
11136 if (!retval) {
11137 /* Indicate initialization to MSI mode */
11138 phba->intr_type = MSI;
11139 intr_mode = 1;
11140 }
11141 }
11142
11143 /* Fallback to INTx if both MSI-X/MSI initalization failed */
11144 if (phba->intr_type == NONE) {
11145 retval = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
11146 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
11147 if (!retval) {
895427bd
JS
11148 struct lpfc_hba_eq_hdl *eqhdl;
11149
da0436e9
JS
11150 /* Indicate initialization to INTx mode */
11151 phba->intr_type = INTx;
11152 intr_mode = 0;
895427bd 11153
6a828b0f 11154 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
895427bd
JS
11155 eqhdl = &phba->sli4_hba.hba_eq_hdl[idx];
11156 eqhdl->idx = idx;
11157 eqhdl->phba = phba;
1ba981fd 11158 }
da0436e9
JS
11159 }
11160 }
11161 return intr_mode;
11162}
11163
11164/**
11165 * lpfc_sli4_disable_intr - Disable device interrupt to SLI-4 device
11166 * @phba: pointer to lpfc hba data structure.
11167 *
11168 * This routine is invoked to disable device interrupt and disassociate
11169 * the driver's interrupt handler(s) from interrupt vector(s) to device
11170 * with SLI-4 interface spec. Depending on the interrupt mode, the driver
11171 * will release the interrupt vector(s) for the message signaled interrupt.
11172 **/
11173static void
11174lpfc_sli4_disable_intr(struct lpfc_hba *phba)
11175{
11176 /* Disable the currently initialized interrupt mode */
45ffac19
CH
11177 if (phba->intr_type == MSIX) {
11178 int index;
11179
11180 /* Free up MSI-X multi-message vectors */
6a828b0f 11181 for (index = 0; index < phba->cfg_irq_chann; index++) {
b3295c2a
JS
11182 irq_set_affinity_hint(
11183 pci_irq_vector(phba->pcidev, index),
11184 NULL);
895427bd
JS
11185 free_irq(pci_irq_vector(phba->pcidev, index),
11186 &phba->sli4_hba.hba_eq_hdl[index]);
b3295c2a 11187 }
45ffac19 11188 } else {
da0436e9 11189 free_irq(phba->pcidev->irq, phba);
45ffac19
CH
11190 }
11191
11192 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
11193
11194 /* Reset interrupt management states */
11195 phba->intr_type = NONE;
11196 phba->sli.slistat.sli_intr = 0;
da0436e9
JS
11197}
11198
11199/**
11200 * lpfc_unset_hba - Unset SLI3 hba device initialization
11201 * @phba: pointer to lpfc hba data structure.
11202 *
11203 * This routine is invoked to unset the HBA device initialization steps to
11204 * a device with SLI-3 interface spec.
11205 **/
11206static void
11207lpfc_unset_hba(struct lpfc_hba *phba)
11208{
11209 struct lpfc_vport *vport = phba->pport;
11210 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
11211
11212 spin_lock_irq(shost->host_lock);
11213 vport->load_flag |= FC_UNLOADING;
11214 spin_unlock_irq(shost->host_lock);
11215
72859909
JS
11216 kfree(phba->vpi_bmask);
11217 kfree(phba->vpi_ids);
11218
da0436e9
JS
11219 lpfc_stop_hba_timers(phba);
11220
11221 phba->pport->work_port_events = 0;
11222
11223 lpfc_sli_hba_down(phba);
11224
11225 lpfc_sli_brdrestart(phba);
11226
11227 lpfc_sli_disable_intr(phba);
11228
11229 return;
11230}
11231
5af5eee7
JS
11232/**
11233 * lpfc_sli4_xri_exchange_busy_wait - Wait for device XRI exchange busy
11234 * @phba: Pointer to HBA context object.
11235 *
11236 * This function is called in the SLI4 code path to wait for completion
11237 * of device's XRIs exchange busy. It will check the XRI exchange busy
11238 * on outstanding FCP and ELS I/Os every 10ms for up to 10 seconds; after
11239 * that, it will check the XRI exchange busy on outstanding FCP and ELS
11240 * I/Os every 30 seconds, log error message, and wait forever. Only when
11241 * all XRI exchange busy complete, the driver unload shall proceed with
11242 * invoking the function reset ioctl mailbox command to the CNA and the
11243 * the rest of the driver unload resource release.
11244 **/
11245static void
11246lpfc_sli4_xri_exchange_busy_wait(struct lpfc_hba *phba)
11247{
5e5b511d 11248 struct lpfc_sli4_hdw_queue *qp;
c00f62e6 11249 int idx, ccnt;
5af5eee7 11250 int wait_time = 0;
5e5b511d 11251 int io_xri_cmpl = 1;
86c67379 11252 int nvmet_xri_cmpl = 1;
5af5eee7
JS
11253 int els_xri_cmpl = list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
11254
c3725bdc
JS
11255 /* Driver just aborted IOs during the hba_unset process. Pause
11256 * here to give the HBA time to complete the IO and get entries
11257 * into the abts lists.
11258 */
11259 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1 * 5);
11260
11261 /* Wait for NVME pending IO to flush back to transport. */
11262 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
11263 lpfc_nvme_wait_for_io_drain(phba);
11264
5e5b511d 11265 ccnt = 0;
5e5b511d
JS
11266 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
11267 qp = &phba->sli4_hba.hdwq[idx];
c00f62e6
JS
11268 io_xri_cmpl = list_empty(&qp->lpfc_abts_io_buf_list);
11269 if (!io_xri_cmpl) /* if list is NOT empty */
11270 ccnt++;
5e5b511d
JS
11271 }
11272 if (ccnt)
11273 io_xri_cmpl = 0;
5e5b511d 11274
86c67379 11275 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
86c67379
JS
11276 nvmet_xri_cmpl =
11277 list_empty(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
11278 }
895427bd 11279
c00f62e6 11280 while (!els_xri_cmpl || !io_xri_cmpl || !nvmet_xri_cmpl) {
5af5eee7 11281 if (wait_time > LPFC_XRI_EXCH_BUSY_WAIT_TMO) {
68c9b55d
JS
11282 if (!nvmet_xri_cmpl)
11283 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11284 "6424 NVMET XRI exchange busy "
11285 "wait time: %d seconds.\n",
11286 wait_time/1000);
5e5b511d 11287 if (!io_xri_cmpl)
895427bd 11288 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
c00f62e6 11289 "6100 IO XRI exchange busy "
5af5eee7
JS
11290 "wait time: %d seconds.\n",
11291 wait_time/1000);
11292 if (!els_xri_cmpl)
11293 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11294 "2878 ELS XRI exchange busy "
11295 "wait time: %d seconds.\n",
11296 wait_time/1000);
11297 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T2);
11298 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T2;
11299 } else {
11300 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1);
11301 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T1;
11302 }
5e5b511d
JS
11303
11304 ccnt = 0;
5e5b511d
JS
11305 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
11306 qp = &phba->sli4_hba.hdwq[idx];
c00f62e6
JS
11307 io_xri_cmpl = list_empty(
11308 &qp->lpfc_abts_io_buf_list);
11309 if (!io_xri_cmpl) /* if list is NOT empty */
11310 ccnt++;
5e5b511d
JS
11311 }
11312 if (ccnt)
11313 io_xri_cmpl = 0;
5e5b511d 11314
86c67379 11315 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
86c67379
JS
11316 nvmet_xri_cmpl = list_empty(
11317 &phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
11318 }
5af5eee7
JS
11319 els_xri_cmpl =
11320 list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
f358dd0c 11321
5af5eee7
JS
11322 }
11323}
11324
da0436e9
JS
11325/**
11326 * lpfc_sli4_hba_unset - Unset the fcoe hba
11327 * @phba: Pointer to HBA context object.
11328 *
11329 * This function is called in the SLI4 code path to reset the HBA's FCoE
11330 * function. The caller is not required to hold any lock. This routine
11331 * issues PCI function reset mailbox command to reset the FCoE function.
11332 * At the end of the function, it calls lpfc_hba_down_post function to
11333 * free any pending commands.
11334 **/
11335static void
11336lpfc_sli4_hba_unset(struct lpfc_hba *phba)
11337{
11338 int wait_cnt = 0;
11339 LPFC_MBOXQ_t *mboxq;
912e3acd 11340 struct pci_dev *pdev = phba->pcidev;
da0436e9
JS
11341
11342 lpfc_stop_hba_timers(phba);
cdb42bec
JS
11343 if (phba->pport)
11344 phba->sli4_hba.intr_enable = 0;
da0436e9
JS
11345
11346 /*
11347 * Gracefully wait out the potential current outstanding asynchronous
11348 * mailbox command.
11349 */
11350
11351 /* First, block any pending async mailbox command from posted */
11352 spin_lock_irq(&phba->hbalock);
11353 phba->sli.sli_flag |= LPFC_SLI_ASYNC_MBX_BLK;
11354 spin_unlock_irq(&phba->hbalock);
11355 /* Now, trying to wait it out if we can */
11356 while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
11357 msleep(10);
11358 if (++wait_cnt > LPFC_ACTIVE_MBOX_WAIT_CNT)
11359 break;
11360 }
11361 /* Forcefully release the outstanding mailbox command if timed out */
11362 if (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
11363 spin_lock_irq(&phba->hbalock);
11364 mboxq = phba->sli.mbox_active;
11365 mboxq->u.mb.mbxStatus = MBX_NOT_FINISHED;
11366 __lpfc_mbox_cmpl_put(phba, mboxq);
11367 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
11368 phba->sli.mbox_active = NULL;
11369 spin_unlock_irq(&phba->hbalock);
11370 }
11371
5af5eee7
JS
11372 /* Abort all iocbs associated with the hba */
11373 lpfc_sli_hba_iocb_abort(phba);
11374
11375 /* Wait for completion of device XRI exchange busy */
11376 lpfc_sli4_xri_exchange_busy_wait(phba);
11377
da0436e9
JS
11378 /* Disable PCI subsystem interrupt */
11379 lpfc_sli4_disable_intr(phba);
11380
912e3acd
JS
11381 /* Disable SR-IOV if enabled */
11382 if (phba->cfg_sriov_nr_virtfn)
11383 pci_disable_sriov(pdev);
11384
da0436e9
JS
11385 /* Stop kthread signal shall trigger work_done one more time */
11386 kthread_stop(phba->worker_thread);
11387
d2cc9bcd 11388 /* Disable FW logging to host memory */
1165a5c2 11389 lpfc_ras_stop_fwlog(phba);
d2cc9bcd 11390
d1f525aa
JS
11391 /* Unset the queues shared with the hardware then release all
11392 * allocated resources.
11393 */
11394 lpfc_sli4_queue_unset(phba);
11395 lpfc_sli4_queue_destroy(phba);
11396
3677a3a7
JS
11397 /* Reset SLI4 HBA FCoE function */
11398 lpfc_pci_function_reset(phba);
11399
1165a5c2
JS
11400 /* Free RAS DMA memory */
11401 if (phba->ras_fwlog.ras_enabled)
11402 lpfc_sli4_ras_dma_free(phba);
11403
da0436e9 11404 /* Stop the SLI4 device port */
1ffdd2c0
JS
11405 if (phba->pport)
11406 phba->pport->work_port_events = 0;
da0436e9
JS
11407}
11408
28baac74
JS
11409 /**
11410 * lpfc_pc_sli4_params_get - Get the SLI4_PARAMS port capabilities.
11411 * @phba: Pointer to HBA context object.
11412 * @mboxq: Pointer to the mailboxq memory for the mailbox command response.
11413 *
11414 * This function is called in the SLI4 code path to read the port's
11415 * sli4 capabilities.
11416 *
11417 * This function may be be called from any context that can block-wait
11418 * for the completion. The expectation is that this routine is called
11419 * typically from probe_one or from the online routine.
11420 **/
11421int
11422lpfc_pc_sli4_params_get(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
11423{
11424 int rc;
11425 struct lpfc_mqe *mqe;
11426 struct lpfc_pc_sli4_params *sli4_params;
11427 uint32_t mbox_tmo;
11428
11429 rc = 0;
11430 mqe = &mboxq->u.mqe;
11431
11432 /* Read the port's SLI4 Parameters port capabilities */
fedd3b7b 11433 lpfc_pc_sli4_params(mboxq);
28baac74
JS
11434 if (!phba->sli4_hba.intr_enable)
11435 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
11436 else {
a183a15f 11437 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
28baac74
JS
11438 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
11439 }
11440
11441 if (unlikely(rc))
11442 return 1;
11443
11444 sli4_params = &phba->sli4_hba.pc_sli4_params;
11445 sli4_params->if_type = bf_get(if_type, &mqe->un.sli4_params);
11446 sli4_params->sli_rev = bf_get(sli_rev, &mqe->un.sli4_params);
11447 sli4_params->sli_family = bf_get(sli_family, &mqe->un.sli4_params);
11448 sli4_params->featurelevel_1 = bf_get(featurelevel_1,
11449 &mqe->un.sli4_params);
11450 sli4_params->featurelevel_2 = bf_get(featurelevel_2,
11451 &mqe->un.sli4_params);
11452 sli4_params->proto_types = mqe->un.sli4_params.word3;
11453 sli4_params->sge_supp_len = mqe->un.sli4_params.sge_supp_len;
11454 sli4_params->if_page_sz = bf_get(if_page_sz, &mqe->un.sli4_params);
11455 sli4_params->rq_db_window = bf_get(rq_db_window, &mqe->un.sli4_params);
11456 sli4_params->loopbk_scope = bf_get(loopbk_scope, &mqe->un.sli4_params);
11457 sli4_params->eq_pages_max = bf_get(eq_pages, &mqe->un.sli4_params);
11458 sli4_params->eqe_size = bf_get(eqe_size, &mqe->un.sli4_params);
11459 sli4_params->cq_pages_max = bf_get(cq_pages, &mqe->un.sli4_params);
11460 sli4_params->cqe_size = bf_get(cqe_size, &mqe->un.sli4_params);
11461 sli4_params->mq_pages_max = bf_get(mq_pages, &mqe->un.sli4_params);
11462 sli4_params->mqe_size = bf_get(mqe_size, &mqe->un.sli4_params);
11463 sli4_params->mq_elem_cnt = bf_get(mq_elem_cnt, &mqe->un.sli4_params);
11464 sli4_params->wq_pages_max = bf_get(wq_pages, &mqe->un.sli4_params);
11465 sli4_params->wqe_size = bf_get(wqe_size, &mqe->un.sli4_params);
11466 sli4_params->rq_pages_max = bf_get(rq_pages, &mqe->un.sli4_params);
11467 sli4_params->rqe_size = bf_get(rqe_size, &mqe->un.sli4_params);
11468 sli4_params->hdr_pages_max = bf_get(hdr_pages, &mqe->un.sli4_params);
11469 sli4_params->hdr_size = bf_get(hdr_size, &mqe->un.sli4_params);
11470 sli4_params->hdr_pp_align = bf_get(hdr_pp_align, &mqe->un.sli4_params);
11471 sli4_params->sgl_pages_max = bf_get(sgl_pages, &mqe->un.sli4_params);
11472 sli4_params->sgl_pp_align = bf_get(sgl_pp_align, &mqe->un.sli4_params);
0558056c
JS
11473
11474 /* Make sure that sge_supp_len can be handled by the driver */
11475 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
11476 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
11477
28baac74
JS
11478 return rc;
11479}
11480
fedd3b7b
JS
11481/**
11482 * lpfc_get_sli4_parameters - Get the SLI4 Config PARAMETERS.
11483 * @phba: Pointer to HBA context object.
11484 * @mboxq: Pointer to the mailboxq memory for the mailbox command response.
11485 *
11486 * This function is called in the SLI4 code path to read the port's
11487 * sli4 capabilities.
11488 *
11489 * This function may be be called from any context that can block-wait
11490 * for the completion. The expectation is that this routine is called
11491 * typically from probe_one or from the online routine.
11492 **/
11493int
11494lpfc_get_sli4_parameters(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
11495{
11496 int rc;
11497 struct lpfc_mqe *mqe = &mboxq->u.mqe;
11498 struct lpfc_pc_sli4_params *sli4_params;
a183a15f 11499 uint32_t mbox_tmo;
fedd3b7b 11500 int length;
bf316c78 11501 bool exp_wqcq_pages = true;
fedd3b7b
JS
11502 struct lpfc_sli4_parameters *mbx_sli4_parameters;
11503
6d368e53
JS
11504 /*
11505 * By default, the driver assumes the SLI4 port requires RPI
11506 * header postings. The SLI4_PARAM response will correct this
11507 * assumption.
11508 */
11509 phba->sli4_hba.rpi_hdrs_in_use = 1;
11510
fedd3b7b
JS
11511 /* Read the port's SLI4 Config Parameters */
11512 length = (sizeof(struct lpfc_mbx_get_sli4_parameters) -
11513 sizeof(struct lpfc_sli4_cfg_mhdr));
11514 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
11515 LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS,
11516 length, LPFC_SLI4_MBX_EMBED);
11517 if (!phba->sli4_hba.intr_enable)
11518 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
a183a15f
JS
11519 else {
11520 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
11521 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
11522 }
fedd3b7b
JS
11523 if (unlikely(rc))
11524 return rc;
11525 sli4_params = &phba->sli4_hba.pc_sli4_params;
11526 mbx_sli4_parameters = &mqe->un.get_sli4_parameters.sli4_parameters;
11527 sli4_params->if_type = bf_get(cfg_if_type, mbx_sli4_parameters);
11528 sli4_params->sli_rev = bf_get(cfg_sli_rev, mbx_sli4_parameters);
11529 sli4_params->sli_family = bf_get(cfg_sli_family, mbx_sli4_parameters);
11530 sli4_params->featurelevel_1 = bf_get(cfg_sli_hint_1,
11531 mbx_sli4_parameters);
11532 sli4_params->featurelevel_2 = bf_get(cfg_sli_hint_2,
11533 mbx_sli4_parameters);
11534 if (bf_get(cfg_phwq, mbx_sli4_parameters))
11535 phba->sli3_options |= LPFC_SLI4_PHWQ_ENABLED;
11536 else
11537 phba->sli3_options &= ~LPFC_SLI4_PHWQ_ENABLED;
11538 sli4_params->sge_supp_len = mbx_sli4_parameters->sge_supp_len;
11539 sli4_params->loopbk_scope = bf_get(loopbk_scope, mbx_sli4_parameters);
1ba981fd 11540 sli4_params->oas_supported = bf_get(cfg_oas, mbx_sli4_parameters);
fedd3b7b
JS
11541 sli4_params->cqv = bf_get(cfg_cqv, mbx_sli4_parameters);
11542 sli4_params->mqv = bf_get(cfg_mqv, mbx_sli4_parameters);
11543 sli4_params->wqv = bf_get(cfg_wqv, mbx_sli4_parameters);
11544 sli4_params->rqv = bf_get(cfg_rqv, mbx_sli4_parameters);
7365f6fd
JS
11545 sli4_params->eqav = bf_get(cfg_eqav, mbx_sli4_parameters);
11546 sli4_params->cqav = bf_get(cfg_cqav, mbx_sli4_parameters);
0c651878 11547 sli4_params->wqsize = bf_get(cfg_wqsize, mbx_sli4_parameters);
66e9e6bf 11548 sli4_params->bv1s = bf_get(cfg_bv1s, mbx_sli4_parameters);
fedd3b7b
JS
11549 sli4_params->sgl_pages_max = bf_get(cfg_sgl_page_cnt,
11550 mbx_sli4_parameters);
895427bd 11551 sli4_params->wqpcnt = bf_get(cfg_wqpcnt, mbx_sli4_parameters);
fedd3b7b
JS
11552 sli4_params->sgl_pp_align = bf_get(cfg_sgl_pp_align,
11553 mbx_sli4_parameters);
6d368e53
JS
11554 phba->sli4_hba.extents_in_use = bf_get(cfg_ext, mbx_sli4_parameters);
11555 phba->sli4_hba.rpi_hdrs_in_use = bf_get(cfg_hdrr, mbx_sli4_parameters);
c15e0704 11556
d79c9e9d
JS
11557 /* Check for Extended Pre-Registered SGL support */
11558 phba->cfg_xpsgl = bf_get(cfg_xpsgl, mbx_sli4_parameters);
11559
c15e0704
JS
11560 /* Check for firmware nvme support */
11561 rc = (bf_get(cfg_nvme, mbx_sli4_parameters) &&
11562 bf_get(cfg_xib, mbx_sli4_parameters));
11563
11564 if (rc) {
11565 /* Save this to indicate the Firmware supports NVME */
11566 sli4_params->nvme = 1;
11567
11568 /* Firmware NVME support, check driver FC4 NVME support */
11569 if (phba->cfg_enable_fc4_type == LPFC_ENABLE_FCP) {
11570 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
11571 "6133 Disabling NVME support: "
11572 "FC4 type not supported: x%x\n",
11573 phba->cfg_enable_fc4_type);
11574 goto fcponly;
11575 }
11576 } else {
11577 /* No firmware NVME support, check driver FC4 NVME support */
11578 sli4_params->nvme = 0;
11579 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
11580 lpfc_printf_log(phba, KERN_ERR, LOG_INIT | LOG_NVME,
11581 "6101 Disabling NVME support: Not "
11582 "supported by firmware (%d %d) x%x\n",
11583 bf_get(cfg_nvme, mbx_sli4_parameters),
11584 bf_get(cfg_xib, mbx_sli4_parameters),
11585 phba->cfg_enable_fc4_type);
11586fcponly:
11587 phba->nvme_support = 0;
11588 phba->nvmet_support = 0;
11589 phba->cfg_nvmet_mrq = 0;
6a224b47 11590 phba->cfg_nvme_seg_cnt = 0;
c15e0704
JS
11591
11592 /* If no FC4 type support, move to just SCSI support */
11593 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
11594 return -ENODEV;
11595 phba->cfg_enable_fc4_type = LPFC_ENABLE_FCP;
11596 }
895427bd 11597 }
0558056c 11598
c26c265b 11599 /* If the NVME FC4 type is enabled, scale the sg_seg_cnt to
a5f7337f 11600 * accommodate 512K and 1M IOs in a single nvme buf.
c26c265b 11601 */
a5f7337f 11602 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
c26c265b 11603 phba->cfg_sg_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
c26c265b 11604
414abe0a
JS
11605 /* Only embed PBDE for if_type 6, PBDE support requires xib be set */
11606 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
11607 LPFC_SLI_INTF_IF_TYPE_6) || (!bf_get(cfg_xib, mbx_sli4_parameters)))
11608 phba->cfg_enable_pbde = 0;
0bc2b7c5 11609
20aefac3
JS
11610 /*
11611 * To support Suppress Response feature we must satisfy 3 conditions.
11612 * lpfc_suppress_rsp module parameter must be set (default).
11613 * In SLI4-Parameters Descriptor:
11614 * Extended Inline Buffers (XIB) must be supported.
11615 * Suppress Response IU Not Supported (SRIUNS) must NOT be supported
11616 * (double negative).
11617 */
11618 if (phba->cfg_suppress_rsp && bf_get(cfg_xib, mbx_sli4_parameters) &&
11619 !(bf_get(cfg_nosr, mbx_sli4_parameters)))
f358dd0c 11620 phba->sli.sli_flag |= LPFC_SLI_SUPPRESS_RSP;
20aefac3
JS
11621 else
11622 phba->cfg_suppress_rsp = 0;
f358dd0c 11623
0cf07f84
JS
11624 if (bf_get(cfg_eqdr, mbx_sli4_parameters))
11625 phba->sli.sli_flag |= LPFC_SLI_USE_EQDR;
11626
0558056c
JS
11627 /* Make sure that sge_supp_len can be handled by the driver */
11628 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
11629 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
11630
b5c53958 11631 /*
c176ffa0
JS
11632 * Check whether the adapter supports an embedded copy of the
11633 * FCP CMD IU within the WQE for FCP_Ixxx commands. In order
11634 * to use this option, 128-byte WQEs must be used.
b5c53958
JS
11635 */
11636 if (bf_get(cfg_ext_embed_cb, mbx_sli4_parameters))
11637 phba->fcp_embed_io = 1;
11638 else
11639 phba->fcp_embed_io = 0;
7bdedb34 11640
0bc2b7c5 11641 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
414abe0a 11642 "6422 XIB %d PBDE %d: FCP %d NVME %d %d %d\n",
0bc2b7c5 11643 bf_get(cfg_xib, mbx_sli4_parameters),
414abe0a
JS
11644 phba->cfg_enable_pbde,
11645 phba->fcp_embed_io, phba->nvme_support,
4e565cf0 11646 phba->cfg_nvme_embed_cmd, phba->cfg_suppress_rsp);
0bc2b7c5 11647
bf316c78
JS
11648 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
11649 LPFC_SLI_INTF_IF_TYPE_2) &&
11650 (bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf) ==
c221768b 11651 LPFC_SLI_INTF_FAMILY_LNCR_A0))
bf316c78
JS
11652 exp_wqcq_pages = false;
11653
c176ffa0
JS
11654 if ((bf_get(cfg_cqpsize, mbx_sli4_parameters) & LPFC_CQ_16K_PAGE_SZ) &&
11655 (bf_get(cfg_wqpsize, mbx_sli4_parameters) & LPFC_WQ_16K_PAGE_SZ) &&
bf316c78 11656 exp_wqcq_pages &&
c176ffa0
JS
11657 (sli4_params->wqsize & LPFC_WQ_SZ128_SUPPORT))
11658 phba->enab_exp_wqcq_pages = 1;
11659 else
11660 phba->enab_exp_wqcq_pages = 0;
7bdedb34
JS
11661 /*
11662 * Check if the SLI port supports MDS Diagnostics
11663 */
11664 if (bf_get(cfg_mds_diags, mbx_sli4_parameters))
11665 phba->mds_diags_support = 1;
11666 else
11667 phba->mds_diags_support = 0;
d2cc9bcd 11668
0d8af096
JS
11669 /*
11670 * Check if the SLI port supports NSLER
11671 */
11672 if (bf_get(cfg_nsler, mbx_sli4_parameters))
11673 phba->nsler = 1;
11674 else
11675 phba->nsler = 0;
11676
fedd3b7b
JS
11677 return 0;
11678}
11679
da0436e9
JS
11680/**
11681 * lpfc_pci_probe_one_s3 - PCI probe func to reg SLI-3 device to PCI subsystem.
11682 * @pdev: pointer to PCI device
11683 * @pid: pointer to PCI device identifier
11684 *
11685 * This routine is to be called to attach a device with SLI-3 interface spec
11686 * to the PCI subsystem. When an Emulex HBA with SLI-3 interface spec is
11687 * presented on PCI bus, the kernel PCI subsystem looks at PCI device-specific
11688 * information of the device and driver to see if the driver state that it can
11689 * support this kind of device. If the match is successful, the driver core
11690 * invokes this routine. If this routine determines it can claim the HBA, it
11691 * does all the initialization that it needs to do to handle the HBA properly.
11692 *
11693 * Return code
11694 * 0 - driver can claim the device
11695 * negative value - driver can not claim the device
11696 **/
6f039790 11697static int
da0436e9
JS
11698lpfc_pci_probe_one_s3(struct pci_dev *pdev, const struct pci_device_id *pid)
11699{
11700 struct lpfc_hba *phba;
11701 struct lpfc_vport *vport = NULL;
6669f9bb 11702 struct Scsi_Host *shost = NULL;
da0436e9
JS
11703 int error;
11704 uint32_t cfg_mode, intr_mode;
11705
11706 /* Allocate memory for HBA structure */
11707 phba = lpfc_hba_alloc(pdev);
11708 if (!phba)
11709 return -ENOMEM;
11710
11711 /* Perform generic PCI device enabling operation */
11712 error = lpfc_enable_pci_dev(phba);
079b5c91 11713 if (error)
da0436e9 11714 goto out_free_phba;
da0436e9
JS
11715
11716 /* Set up SLI API function jump table for PCI-device group-0 HBAs */
11717 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_LP);
11718 if (error)
11719 goto out_disable_pci_dev;
11720
11721 /* Set up SLI-3 specific device PCI memory space */
11722 error = lpfc_sli_pci_mem_setup(phba);
11723 if (error) {
11724 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11725 "1402 Failed to set up pci memory space.\n");
11726 goto out_disable_pci_dev;
11727 }
11728
da0436e9
JS
11729 /* Set up SLI-3 specific device driver resources */
11730 error = lpfc_sli_driver_resource_setup(phba);
11731 if (error) {
11732 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11733 "1404 Failed to set up driver resource.\n");
11734 goto out_unset_pci_mem_s3;
11735 }
11736
11737 /* Initialize and populate the iocb list per host */
d1f525aa 11738
da0436e9
JS
11739 error = lpfc_init_iocb_list(phba, LPFC_IOCB_LIST_CNT);
11740 if (error) {
11741 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11742 "1405 Failed to initialize iocb list.\n");
11743 goto out_unset_driver_resource_s3;
11744 }
11745
11746 /* Set up common device driver resources */
11747 error = lpfc_setup_driver_resource_phase2(phba);
11748 if (error) {
11749 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11750 "1406 Failed to set up driver resource.\n");
11751 goto out_free_iocb_list;
11752 }
11753
079b5c91
JS
11754 /* Get the default values for Model Name and Description */
11755 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
11756
da0436e9
JS
11757 /* Create SCSI host to the physical port */
11758 error = lpfc_create_shost(phba);
11759 if (error) {
11760 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11761 "1407 Failed to create scsi host.\n");
11762 goto out_unset_driver_resource;
11763 }
11764
11765 /* Configure sysfs attributes */
11766 vport = phba->pport;
11767 error = lpfc_alloc_sysfs_attr(vport);
11768 if (error) {
11769 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11770 "1476 Failed to allocate sysfs attr\n");
11771 goto out_destroy_shost;
11772 }
11773
6669f9bb 11774 shost = lpfc_shost_from_vport(vport); /* save shost for error cleanup */
da0436e9
JS
11775 /* Now, trying to enable interrupt and bring up the device */
11776 cfg_mode = phba->cfg_use_msi;
11777 while (true) {
11778 /* Put device to a known state before enabling interrupt */
11779 lpfc_stop_port(phba);
11780 /* Configure and enable interrupt */
11781 intr_mode = lpfc_sli_enable_intr(phba, cfg_mode);
11782 if (intr_mode == LPFC_INTR_ERROR) {
11783 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11784 "0431 Failed to enable interrupt.\n");
11785 error = -ENODEV;
11786 goto out_free_sysfs_attr;
11787 }
11788 /* SLI-3 HBA setup */
11789 if (lpfc_sli_hba_setup(phba)) {
11790 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11791 "1477 Failed to set up hba\n");
11792 error = -ENODEV;
11793 goto out_remove_device;
11794 }
11795
11796 /* Wait 50ms for the interrupts of previous mailbox commands */
11797 msleep(50);
11798 /* Check active interrupts on message signaled interrupts */
11799 if (intr_mode == 0 ||
11800 phba->sli.slistat.sli_intr > LPFC_MSIX_VECTORS) {
11801 /* Log the current active interrupt mode */
11802 phba->intr_mode = intr_mode;
11803 lpfc_log_intr_mode(phba, intr_mode);
11804 break;
11805 } else {
11806 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11807 "0447 Configure interrupt mode (%d) "
11808 "failed active interrupt test.\n",
11809 intr_mode);
11810 /* Disable the current interrupt mode */
11811 lpfc_sli_disable_intr(phba);
11812 /* Try next level of interrupt mode */
11813 cfg_mode = --intr_mode;
11814 }
11815 }
11816
11817 /* Perform post initialization setup */
11818 lpfc_post_init_setup(phba);
11819
11820 /* Check if there are static vports to be created. */
11821 lpfc_create_static_vport(phba);
11822
11823 return 0;
11824
11825out_remove_device:
11826 lpfc_unset_hba(phba);
11827out_free_sysfs_attr:
11828 lpfc_free_sysfs_attr(vport);
11829out_destroy_shost:
11830 lpfc_destroy_shost(phba);
11831out_unset_driver_resource:
11832 lpfc_unset_driver_resource_phase2(phba);
11833out_free_iocb_list:
11834 lpfc_free_iocb_list(phba);
11835out_unset_driver_resource_s3:
11836 lpfc_sli_driver_resource_unset(phba);
11837out_unset_pci_mem_s3:
11838 lpfc_sli_pci_mem_unset(phba);
11839out_disable_pci_dev:
11840 lpfc_disable_pci_dev(phba);
6669f9bb
JS
11841 if (shost)
11842 scsi_host_put(shost);
da0436e9
JS
11843out_free_phba:
11844 lpfc_hba_free(phba);
11845 return error;
11846}
11847
11848/**
11849 * lpfc_pci_remove_one_s3 - PCI func to unreg SLI-3 device from PCI subsystem.
11850 * @pdev: pointer to PCI device
11851 *
11852 * This routine is to be called to disattach a device with SLI-3 interface
11853 * spec from PCI subsystem. When an Emulex HBA with SLI-3 interface spec is
11854 * removed from PCI bus, it performs all the necessary cleanup for the HBA
11855 * device to be removed from the PCI subsystem properly.
11856 **/
6f039790 11857static void
da0436e9
JS
11858lpfc_pci_remove_one_s3(struct pci_dev *pdev)
11859{
11860 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11861 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
11862 struct lpfc_vport **vports;
11863 struct lpfc_hba *phba = vport->phba;
11864 int i;
da0436e9
JS
11865
11866 spin_lock_irq(&phba->hbalock);
11867 vport->load_flag |= FC_UNLOADING;
11868 spin_unlock_irq(&phba->hbalock);
11869
11870 lpfc_free_sysfs_attr(vport);
11871
11872 /* Release all the vports against this physical port */
11873 vports = lpfc_create_vport_work_array(phba);
11874 if (vports != NULL)
587a37f6
JS
11875 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
11876 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
11877 continue;
da0436e9 11878 fc_vport_terminate(vports[i]->fc_vport);
587a37f6 11879 }
da0436e9
JS
11880 lpfc_destroy_vport_work_array(phba, vports);
11881
11882 /* Remove FC host and then SCSI host with the physical port */
11883 fc_remove_host(shost);
11884 scsi_remove_host(shost);
d613b6a7 11885
da0436e9
JS
11886 lpfc_cleanup(vport);
11887
11888 /*
11889 * Bring down the SLI Layer. This step disable all interrupts,
11890 * clears the rings, discards all mailbox commands, and resets
11891 * the HBA.
11892 */
11893
48e34d0f 11894 /* HBA interrupt will be disabled after this call */
da0436e9
JS
11895 lpfc_sli_hba_down(phba);
11896 /* Stop kthread signal shall trigger work_done one more time */
11897 kthread_stop(phba->worker_thread);
11898 /* Final cleanup of txcmplq and reset the HBA */
11899 lpfc_sli_brdrestart(phba);
11900
72859909
JS
11901 kfree(phba->vpi_bmask);
11902 kfree(phba->vpi_ids);
11903
da0436e9 11904 lpfc_stop_hba_timers(phba);
523128e5 11905 spin_lock_irq(&phba->port_list_lock);
da0436e9 11906 list_del_init(&vport->listentry);
523128e5 11907 spin_unlock_irq(&phba->port_list_lock);
da0436e9
JS
11908
11909 lpfc_debugfs_terminate(vport);
11910
912e3acd
JS
11911 /* Disable SR-IOV if enabled */
11912 if (phba->cfg_sriov_nr_virtfn)
11913 pci_disable_sriov(pdev);
11914
da0436e9
JS
11915 /* Disable interrupt */
11916 lpfc_sli_disable_intr(phba);
11917
da0436e9
JS
11918 scsi_host_put(shost);
11919
11920 /*
11921 * Call scsi_free before mem_free since scsi bufs are released to their
11922 * corresponding pools here.
11923 */
11924 lpfc_scsi_free(phba);
0794d601
JS
11925 lpfc_free_iocb_list(phba);
11926
da0436e9
JS
11927 lpfc_mem_free_all(phba);
11928
11929 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
11930 phba->hbqslimp.virt, phba->hbqslimp.phys);
11931
11932 /* Free resources associated with SLI2 interface */
11933 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
11934 phba->slim2p.virt, phba->slim2p.phys);
11935
11936 /* unmap adapter SLIM and Control Registers */
11937 iounmap(phba->ctrl_regs_memmap_p);
11938 iounmap(phba->slim_memmap_p);
11939
11940 lpfc_hba_free(phba);
11941
e0c0483c 11942 pci_release_mem_regions(pdev);
da0436e9
JS
11943 pci_disable_device(pdev);
11944}
11945
11946/**
11947 * lpfc_pci_suspend_one_s3 - PCI func to suspend SLI-3 device for power mgmnt
11948 * @pdev: pointer to PCI device
11949 * @msg: power management message
11950 *
11951 * This routine is to be called from the kernel's PCI subsystem to support
11952 * system Power Management (PM) to device with SLI-3 interface spec. When
11953 * PM invokes this method, it quiesces the device by stopping the driver's
11954 * worker thread for the device, turning off device's interrupt and DMA,
11955 * and bring the device offline. Note that as the driver implements the
11956 * minimum PM requirements to a power-aware driver's PM support for the
11957 * suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE, FREEZE)
11958 * to the suspend() method call will be treated as SUSPEND and the driver will
11959 * fully reinitialize its device during resume() method call, the driver will
11960 * set device to PCI_D3hot state in PCI config space instead of setting it
11961 * according to the @msg provided by the PM.
11962 *
11963 * Return code
11964 * 0 - driver suspended the device
11965 * Error otherwise
11966 **/
11967static int
11968lpfc_pci_suspend_one_s3(struct pci_dev *pdev, pm_message_t msg)
11969{
11970 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11971 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11972
11973 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11974 "0473 PCI device Power Management suspend.\n");
11975
11976 /* Bring down the device */
618a5230 11977 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
da0436e9
JS
11978 lpfc_offline(phba);
11979 kthread_stop(phba->worker_thread);
11980
11981 /* Disable interrupt from device */
11982 lpfc_sli_disable_intr(phba);
11983
11984 /* Save device state to PCI config space */
11985 pci_save_state(pdev);
11986 pci_set_power_state(pdev, PCI_D3hot);
11987
11988 return 0;
11989}
11990
11991/**
11992 * lpfc_pci_resume_one_s3 - PCI func to resume SLI-3 device for power mgmnt
11993 * @pdev: pointer to PCI device
11994 *
11995 * This routine is to be called from the kernel's PCI subsystem to support
11996 * system Power Management (PM) to device with SLI-3 interface spec. When PM
11997 * invokes this method, it restores the device's PCI config space state and
11998 * fully reinitializes the device and brings it online. Note that as the
11999 * driver implements the minimum PM requirements to a power-aware driver's
12000 * PM for suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE,
12001 * FREEZE) to the suspend() method call will be treated as SUSPEND and the
12002 * driver will fully reinitialize its device during resume() method call,
12003 * the device will be set to PCI_D0 directly in PCI config space before
12004 * restoring the state.
12005 *
12006 * Return code
12007 * 0 - driver suspended the device
12008 * Error otherwise
12009 **/
12010static int
12011lpfc_pci_resume_one_s3(struct pci_dev *pdev)
12012{
12013 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12014 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12015 uint32_t intr_mode;
12016 int error;
12017
12018 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12019 "0452 PCI device Power Management resume.\n");
12020
12021 /* Restore device state from PCI config space */
12022 pci_set_power_state(pdev, PCI_D0);
12023 pci_restore_state(pdev);
0d878419 12024
1dfb5a47
JS
12025 /*
12026 * As the new kernel behavior of pci_restore_state() API call clears
12027 * device saved_state flag, need to save the restored state again.
12028 */
12029 pci_save_state(pdev);
12030
da0436e9
JS
12031 if (pdev->is_busmaster)
12032 pci_set_master(pdev);
12033
12034 /* Startup the kernel thread for this host adapter. */
12035 phba->worker_thread = kthread_run(lpfc_do_work, phba,
12036 "lpfc_worker_%d", phba->brd_no);
12037 if (IS_ERR(phba->worker_thread)) {
12038 error = PTR_ERR(phba->worker_thread);
12039 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12040 "0434 PM resume failed to start worker "
12041 "thread: error=x%x.\n", error);
12042 return error;
12043 }
12044
12045 /* Configure and enable interrupt */
12046 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
12047 if (intr_mode == LPFC_INTR_ERROR) {
12048 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12049 "0430 PM resume Failed to enable interrupt\n");
12050 return -EIO;
12051 } else
12052 phba->intr_mode = intr_mode;
12053
12054 /* Restart HBA and bring it online */
12055 lpfc_sli_brdrestart(phba);
12056 lpfc_online(phba);
12057
12058 /* Log the current active interrupt mode */
12059 lpfc_log_intr_mode(phba, phba->intr_mode);
12060
12061 return 0;
12062}
12063
891478a2
JS
12064/**
12065 * lpfc_sli_prep_dev_for_recover - Prepare SLI3 device for pci slot recover
12066 * @phba: pointer to lpfc hba data structure.
12067 *
12068 * This routine is called to prepare the SLI3 device for PCI slot recover. It
e2af0d2e 12069 * aborts all the outstanding SCSI I/Os to the pci device.
891478a2
JS
12070 **/
12071static void
12072lpfc_sli_prep_dev_for_recover(struct lpfc_hba *phba)
12073{
12074 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12075 "2723 PCI channel I/O abort preparing for recovery\n");
e2af0d2e
JS
12076
12077 /*
12078 * There may be errored I/Os through HBA, abort all I/Os on txcmplq
12079 * and let the SCSI mid-layer to retry them to recover.
12080 */
db55fba8 12081 lpfc_sli_abort_fcp_rings(phba);
891478a2
JS
12082}
12083
0d878419
JS
12084/**
12085 * lpfc_sli_prep_dev_for_reset - Prepare SLI3 device for pci slot reset
12086 * @phba: pointer to lpfc hba data structure.
12087 *
12088 * This routine is called to prepare the SLI3 device for PCI slot reset. It
12089 * disables the device interrupt and pci device, and aborts the internal FCP
12090 * pending I/Os.
12091 **/
12092static void
12093lpfc_sli_prep_dev_for_reset(struct lpfc_hba *phba)
12094{
0d878419 12095 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
891478a2 12096 "2710 PCI channel disable preparing for reset\n");
e2af0d2e 12097
75baf696 12098 /* Block any management I/Os to the device */
618a5230 12099 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
75baf696 12100
e2af0d2e
JS
12101 /* Block all SCSI devices' I/Os on the host */
12102 lpfc_scsi_dev_block(phba);
12103
ea714f3d 12104 /* Flush all driver's outstanding SCSI I/Os as we are to reset */
c00f62e6 12105 lpfc_sli_flush_io_rings(phba);
ea714f3d 12106
e2af0d2e
JS
12107 /* stop all timers */
12108 lpfc_stop_hba_timers(phba);
12109
0d878419
JS
12110 /* Disable interrupt and pci device */
12111 lpfc_sli_disable_intr(phba);
12112 pci_disable_device(phba->pcidev);
0d878419
JS
12113}
12114
12115/**
12116 * lpfc_sli_prep_dev_for_perm_failure - Prepare SLI3 dev for pci slot disable
12117 * @phba: pointer to lpfc hba data structure.
12118 *
12119 * This routine is called to prepare the SLI3 device for PCI slot permanently
12120 * disabling. It blocks the SCSI transport layer traffic and flushes the FCP
12121 * pending I/Os.
12122 **/
12123static void
75baf696 12124lpfc_sli_prep_dev_for_perm_failure(struct lpfc_hba *phba)
0d878419
JS
12125{
12126 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
891478a2 12127 "2711 PCI channel permanent disable for failure\n");
e2af0d2e
JS
12128 /* Block all SCSI devices' I/Os on the host */
12129 lpfc_scsi_dev_block(phba);
12130
12131 /* stop all timers */
12132 lpfc_stop_hba_timers(phba);
12133
0d878419 12134 /* Clean up all driver's outstanding SCSI I/Os */
c00f62e6 12135 lpfc_sli_flush_io_rings(phba);
0d878419
JS
12136}
12137
da0436e9
JS
12138/**
12139 * lpfc_io_error_detected_s3 - Method for handling SLI-3 device PCI I/O error
12140 * @pdev: pointer to PCI device.
12141 * @state: the current PCI connection state.
12142 *
12143 * This routine is called from the PCI subsystem for I/O error handling to
12144 * device with SLI-3 interface spec. This function is called by the PCI
12145 * subsystem after a PCI bus error affecting this device has been detected.
12146 * When this function is invoked, it will need to stop all the I/Os and
12147 * interrupt(s) to the device. Once that is done, it will return
12148 * PCI_ERS_RESULT_NEED_RESET for the PCI subsystem to perform proper recovery
12149 * as desired.
12150 *
12151 * Return codes
0d878419 12152 * PCI_ERS_RESULT_CAN_RECOVER - can be recovered with reset_link
da0436e9
JS
12153 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
12154 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
12155 **/
12156static pci_ers_result_t
12157lpfc_io_error_detected_s3(struct pci_dev *pdev, pci_channel_state_t state)
12158{
12159 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12160 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
da0436e9 12161
0d878419
JS
12162 switch (state) {
12163 case pci_channel_io_normal:
891478a2
JS
12164 /* Non-fatal error, prepare for recovery */
12165 lpfc_sli_prep_dev_for_recover(phba);
0d878419
JS
12166 return PCI_ERS_RESULT_CAN_RECOVER;
12167 case pci_channel_io_frozen:
12168 /* Fatal error, prepare for slot reset */
12169 lpfc_sli_prep_dev_for_reset(phba);
12170 return PCI_ERS_RESULT_NEED_RESET;
12171 case pci_channel_io_perm_failure:
12172 /* Permanent failure, prepare for device down */
75baf696 12173 lpfc_sli_prep_dev_for_perm_failure(phba);
da0436e9 12174 return PCI_ERS_RESULT_DISCONNECT;
0d878419
JS
12175 default:
12176 /* Unknown state, prepare and request slot reset */
12177 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12178 "0472 Unknown PCI error state: x%x\n", state);
12179 lpfc_sli_prep_dev_for_reset(phba);
12180 return PCI_ERS_RESULT_NEED_RESET;
da0436e9 12181 }
da0436e9
JS
12182}
12183
12184/**
12185 * lpfc_io_slot_reset_s3 - Method for restarting PCI SLI-3 device from scratch.
12186 * @pdev: pointer to PCI device.
12187 *
12188 * This routine is called from the PCI subsystem for error handling to
12189 * device with SLI-3 interface spec. This is called after PCI bus has been
12190 * reset to restart the PCI card from scratch, as if from a cold-boot.
12191 * During the PCI subsystem error recovery, after driver returns
12192 * PCI_ERS_RESULT_NEED_RESET, the PCI subsystem will perform proper error
12193 * recovery and then call this routine before calling the .resume method
12194 * to recover the device. This function will initialize the HBA device,
12195 * enable the interrupt, but it will just put the HBA to offline state
12196 * without passing any I/O traffic.
12197 *
12198 * Return codes
12199 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
12200 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
12201 */
12202static pci_ers_result_t
12203lpfc_io_slot_reset_s3(struct pci_dev *pdev)
12204{
12205 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12206 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12207 struct lpfc_sli *psli = &phba->sli;
12208 uint32_t intr_mode;
12209
12210 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
12211 if (pci_enable_device_mem(pdev)) {
12212 printk(KERN_ERR "lpfc: Cannot re-enable "
12213 "PCI device after reset.\n");
12214 return PCI_ERS_RESULT_DISCONNECT;
12215 }
12216
12217 pci_restore_state(pdev);
1dfb5a47
JS
12218
12219 /*
12220 * As the new kernel behavior of pci_restore_state() API call clears
12221 * device saved_state flag, need to save the restored state again.
12222 */
12223 pci_save_state(pdev);
12224
da0436e9
JS
12225 if (pdev->is_busmaster)
12226 pci_set_master(pdev);
12227
12228 spin_lock_irq(&phba->hbalock);
12229 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
12230 spin_unlock_irq(&phba->hbalock);
12231
12232 /* Configure and enable interrupt */
12233 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
12234 if (intr_mode == LPFC_INTR_ERROR) {
12235 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12236 "0427 Cannot re-enable interrupt after "
12237 "slot reset.\n");
12238 return PCI_ERS_RESULT_DISCONNECT;
12239 } else
12240 phba->intr_mode = intr_mode;
12241
75baf696 12242 /* Take device offline, it will perform cleanup */
618a5230 12243 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
da0436e9
JS
12244 lpfc_offline(phba);
12245 lpfc_sli_brdrestart(phba);
12246
12247 /* Log the current active interrupt mode */
12248 lpfc_log_intr_mode(phba, phba->intr_mode);
12249
12250 return PCI_ERS_RESULT_RECOVERED;
12251}
12252
12253/**
12254 * lpfc_io_resume_s3 - Method for resuming PCI I/O operation on SLI-3 device.
12255 * @pdev: pointer to PCI device
12256 *
12257 * This routine is called from the PCI subsystem for error handling to device
12258 * with SLI-3 interface spec. It is called when kernel error recovery tells
12259 * the lpfc driver that it is ok to resume normal PCI operation after PCI bus
12260 * error recovery. After this call, traffic can start to flow from this device
12261 * again.
12262 */
12263static void
12264lpfc_io_resume_s3(struct pci_dev *pdev)
12265{
12266 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12267 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
3772a991 12268
e2af0d2e 12269 /* Bring device online, it will be no-op for non-fatal error resume */
da0436e9
JS
12270 lpfc_online(phba);
12271}
3772a991 12272
da0436e9
JS
12273/**
12274 * lpfc_sli4_get_els_iocb_cnt - Calculate the # of ELS IOCBs to reserve
12275 * @phba: pointer to lpfc hba data structure.
12276 *
12277 * returns the number of ELS/CT IOCBs to reserve
12278 **/
12279int
12280lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *phba)
12281{
12282 int max_xri = phba->sli4_hba.max_cfg_param.max_xri;
12283
f1126688
JS
12284 if (phba->sli_rev == LPFC_SLI_REV4) {
12285 if (max_xri <= 100)
6a9c52cf 12286 return 10;
f1126688 12287 else if (max_xri <= 256)
6a9c52cf 12288 return 25;
f1126688 12289 else if (max_xri <= 512)
6a9c52cf 12290 return 50;
f1126688 12291 else if (max_xri <= 1024)
6a9c52cf 12292 return 100;
8a9d2e80 12293 else if (max_xri <= 1536)
6a9c52cf 12294 return 150;
8a9d2e80
JS
12295 else if (max_xri <= 2048)
12296 return 200;
12297 else
12298 return 250;
f1126688
JS
12299 } else
12300 return 0;
3772a991
JS
12301}
12302
895427bd
JS
12303/**
12304 * lpfc_sli4_get_iocb_cnt - Calculate the # of total IOCBs to reserve
12305 * @phba: pointer to lpfc hba data structure.
12306 *
f358dd0c 12307 * returns the number of ELS/CT + NVMET IOCBs to reserve
895427bd
JS
12308 **/
12309int
12310lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba)
12311{
12312 int max_xri = lpfc_sli4_get_els_iocb_cnt(phba);
12313
f358dd0c
JS
12314 if (phba->nvmet_support)
12315 max_xri += LPFC_NVMET_BUF_POST;
895427bd
JS
12316 return max_xri;
12317}
12318
12319
1feb8204
JS
12320static void
12321lpfc_log_write_firmware_error(struct lpfc_hba *phba, uint32_t offset,
12322 uint32_t magic_number, uint32_t ftype, uint32_t fid, uint32_t fsize,
12323 const struct firmware *fw)
12324{
a72d56b2
JS
12325 if ((offset == ADD_STATUS_FW_NOT_SUPPORTED) ||
12326 (phba->pcidev->device == PCI_DEVICE_ID_LANCER_G6_FC &&
12327 magic_number != MAGIC_NUMER_G6) ||
12328 (phba->pcidev->device == PCI_DEVICE_ID_LANCER_G7_FC &&
12329 magic_number != MAGIC_NUMER_G7))
1feb8204
JS
12330 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12331 "3030 This firmware version is not supported on "
12332 "this HBA model. Device:%x Magic:%x Type:%x "
12333 "ID:%x Size %d %zd\n",
12334 phba->pcidev->device, magic_number, ftype, fid,
12335 fsize, fw->size);
12336 else
12337 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12338 "3022 FW Download failed. Device:%x Magic:%x Type:%x "
12339 "ID:%x Size %d %zd\n",
12340 phba->pcidev->device, magic_number, ftype, fid,
12341 fsize, fw->size);
12342}
12343
12344
52d52440
JS
12345/**
12346 * lpfc_write_firmware - attempt to write a firmware image to the port
52d52440 12347 * @fw: pointer to firmware image returned from request_firmware.
ce396282 12348 * @phba: pointer to lpfc hba data structure.
52d52440 12349 *
52d52440 12350 **/
ce396282
JS
12351static void
12352lpfc_write_firmware(const struct firmware *fw, void *context)
52d52440 12353{
ce396282 12354 struct lpfc_hba *phba = (struct lpfc_hba *)context;
6b5151fd 12355 char fwrev[FW_REV_STR_SIZE];
ce396282 12356 struct lpfc_grp_hdr *image;
52d52440
JS
12357 struct list_head dma_buffer_list;
12358 int i, rc = 0;
12359 struct lpfc_dmabuf *dmabuf, *next;
12360 uint32_t offset = 0, temp_offset = 0;
6b6ef5db 12361 uint32_t magic_number, ftype, fid, fsize;
52d52440 12362
c71ab861 12363 /* It can be null in no-wait mode, sanity check */
ce396282
JS
12364 if (!fw) {
12365 rc = -ENXIO;
12366 goto out;
12367 }
12368 image = (struct lpfc_grp_hdr *)fw->data;
12369
6b6ef5db
JS
12370 magic_number = be32_to_cpu(image->magic_number);
12371 ftype = bf_get_be32(lpfc_grp_hdr_file_type, image);
1feb8204 12372 fid = bf_get_be32(lpfc_grp_hdr_id, image);
6b6ef5db
JS
12373 fsize = be32_to_cpu(image->size);
12374
52d52440 12375 INIT_LIST_HEAD(&dma_buffer_list);
52d52440 12376 lpfc_decode_firmware_rev(phba, fwrev, 1);
88a2cfbb 12377 if (strncmp(fwrev, image->revision, strnlen(image->revision, 16))) {
52d52440 12378 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
ce396282 12379 "3023 Updating Firmware, Current Version:%s "
52d52440 12380 "New Version:%s\n",
88a2cfbb 12381 fwrev, image->revision);
52d52440
JS
12382 for (i = 0; i < LPFC_MBX_WR_CONFIG_MAX_BDE; i++) {
12383 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf),
12384 GFP_KERNEL);
12385 if (!dmabuf) {
12386 rc = -ENOMEM;
ce396282 12387 goto release_out;
52d52440
JS
12388 }
12389 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
12390 SLI4_PAGE_SIZE,
12391 &dmabuf->phys,
12392 GFP_KERNEL);
12393 if (!dmabuf->virt) {
12394 kfree(dmabuf);
12395 rc = -ENOMEM;
ce396282 12396 goto release_out;
52d52440
JS
12397 }
12398 list_add_tail(&dmabuf->list, &dma_buffer_list);
12399 }
12400 while (offset < fw->size) {
12401 temp_offset = offset;
12402 list_for_each_entry(dmabuf, &dma_buffer_list, list) {
079b5c91 12403 if (temp_offset + SLI4_PAGE_SIZE > fw->size) {
52d52440
JS
12404 memcpy(dmabuf->virt,
12405 fw->data + temp_offset,
079b5c91
JS
12406 fw->size - temp_offset);
12407 temp_offset = fw->size;
52d52440
JS
12408 break;
12409 }
52d52440
JS
12410 memcpy(dmabuf->virt, fw->data + temp_offset,
12411 SLI4_PAGE_SIZE);
88a2cfbb 12412 temp_offset += SLI4_PAGE_SIZE;
52d52440
JS
12413 }
12414 rc = lpfc_wr_object(phba, &dma_buffer_list,
12415 (fw->size - offset), &offset);
1feb8204
JS
12416 if (rc) {
12417 lpfc_log_write_firmware_error(phba, offset,
12418 magic_number, ftype, fid, fsize, fw);
ce396282 12419 goto release_out;
1feb8204 12420 }
52d52440
JS
12421 }
12422 rc = offset;
1feb8204
JS
12423 } else
12424 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12425 "3029 Skipped Firmware update, Current "
12426 "Version:%s New Version:%s\n",
12427 fwrev, image->revision);
ce396282
JS
12428
12429release_out:
52d52440
JS
12430 list_for_each_entry_safe(dmabuf, next, &dma_buffer_list, list) {
12431 list_del(&dmabuf->list);
12432 dma_free_coherent(&phba->pcidev->dev, SLI4_PAGE_SIZE,
12433 dmabuf->virt, dmabuf->phys);
12434 kfree(dmabuf);
12435 }
ce396282
JS
12436 release_firmware(fw);
12437out:
12438 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
c71ab861 12439 "3024 Firmware update done: %d.\n", rc);
ce396282 12440 return;
52d52440
JS
12441}
12442
c71ab861
JS
12443/**
12444 * lpfc_sli4_request_firmware_update - Request linux generic firmware upgrade
12445 * @phba: pointer to lpfc hba data structure.
12446 *
12447 * This routine is called to perform Linux generic firmware upgrade on device
12448 * that supports such feature.
12449 **/
12450int
12451lpfc_sli4_request_firmware_update(struct lpfc_hba *phba, uint8_t fw_upgrade)
12452{
12453 uint8_t file_name[ELX_MODEL_NAME_SIZE];
12454 int ret;
12455 const struct firmware *fw;
12456
12457 /* Only supported on SLI4 interface type 2 for now */
27d6ac0a 12458 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
c71ab861
JS
12459 LPFC_SLI_INTF_IF_TYPE_2)
12460 return -EPERM;
12461
12462 snprintf(file_name, ELX_MODEL_NAME_SIZE, "%s.grp", phba->ModelName);
12463
12464 if (fw_upgrade == INT_FW_UPGRADE) {
12465 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
12466 file_name, &phba->pcidev->dev,
12467 GFP_KERNEL, (void *)phba,
12468 lpfc_write_firmware);
12469 } else if (fw_upgrade == RUN_FW_UPGRADE) {
12470 ret = request_firmware(&fw, file_name, &phba->pcidev->dev);
12471 if (!ret)
12472 lpfc_write_firmware(fw, (void *)phba);
12473 } else {
12474 ret = -EINVAL;
12475 }
12476
12477 return ret;
12478}
12479
3772a991 12480/**
da0436e9 12481 * lpfc_pci_probe_one_s4 - PCI probe func to reg SLI-4 device to PCI subsys
3772a991
JS
12482 * @pdev: pointer to PCI device
12483 * @pid: pointer to PCI device identifier
12484 *
da0436e9
JS
12485 * This routine is called from the kernel's PCI subsystem to device with
12486 * SLI-4 interface spec. When an Emulex HBA with SLI-4 interface spec is
3772a991 12487 * presented on PCI bus, the kernel PCI subsystem looks at PCI device-specific
da0436e9
JS
12488 * information of the device and driver to see if the driver state that it
12489 * can support this kind of device. If the match is successful, the driver
12490 * core invokes this routine. If this routine determines it can claim the HBA,
12491 * it does all the initialization that it needs to do to handle the HBA
12492 * properly.
3772a991
JS
12493 *
12494 * Return code
12495 * 0 - driver can claim the device
12496 * negative value - driver can not claim the device
12497 **/
6f039790 12498static int
da0436e9 12499lpfc_pci_probe_one_s4(struct pci_dev *pdev, const struct pci_device_id *pid)
3772a991
JS
12500{
12501 struct lpfc_hba *phba;
12502 struct lpfc_vport *vport = NULL;
6669f9bb 12503 struct Scsi_Host *shost = NULL;
6c621a22 12504 int error;
3772a991
JS
12505 uint32_t cfg_mode, intr_mode;
12506
12507 /* Allocate memory for HBA structure */
12508 phba = lpfc_hba_alloc(pdev);
12509 if (!phba)
12510 return -ENOMEM;
12511
12512 /* Perform generic PCI device enabling operation */
12513 error = lpfc_enable_pci_dev(phba);
079b5c91 12514 if (error)
3772a991 12515 goto out_free_phba;
3772a991 12516
da0436e9
JS
12517 /* Set up SLI API function jump table for PCI-device group-1 HBAs */
12518 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_OC);
3772a991
JS
12519 if (error)
12520 goto out_disable_pci_dev;
12521
da0436e9
JS
12522 /* Set up SLI-4 specific device PCI memory space */
12523 error = lpfc_sli4_pci_mem_setup(phba);
3772a991
JS
12524 if (error) {
12525 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 12526 "1410 Failed to set up pci memory space.\n");
3772a991
JS
12527 goto out_disable_pci_dev;
12528 }
12529
da0436e9
JS
12530 /* Set up SLI-4 Specific device driver resources */
12531 error = lpfc_sli4_driver_resource_setup(phba);
3772a991
JS
12532 if (error) {
12533 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9
JS
12534 "1412 Failed to set up driver resource.\n");
12535 goto out_unset_pci_mem_s4;
3772a991
JS
12536 }
12537
19ca7609 12538 INIT_LIST_HEAD(&phba->active_rrq_list);
7d791df7 12539 INIT_LIST_HEAD(&phba->fcf.fcf_pri_list);
19ca7609 12540
3772a991
JS
12541 /* Set up common device driver resources */
12542 error = lpfc_setup_driver_resource_phase2(phba);
12543 if (error) {
12544 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 12545 "1414 Failed to set up driver resource.\n");
6c621a22 12546 goto out_unset_driver_resource_s4;
3772a991
JS
12547 }
12548
079b5c91
JS
12549 /* Get the default values for Model Name and Description */
12550 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
12551
3772a991 12552 /* Now, trying to enable interrupt and bring up the device */
5b75da2f 12553 cfg_mode = phba->cfg_use_msi;
5b75da2f 12554
7b15db32 12555 /* Put device to a known state before enabling interrupt */
cdb42bec 12556 phba->pport = NULL;
7b15db32 12557 lpfc_stop_port(phba);
895427bd 12558
7b15db32
JS
12559 /* Configure and enable interrupt */
12560 intr_mode = lpfc_sli4_enable_intr(phba, cfg_mode);
12561 if (intr_mode == LPFC_INTR_ERROR) {
12562 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12563 "0426 Failed to enable interrupt.\n");
12564 error = -ENODEV;
cdb42bec 12565 goto out_unset_driver_resource;
7b15db32
JS
12566 }
12567 /* Default to single EQ for non-MSI-X */
895427bd 12568 if (phba->intr_type != MSIX) {
6a828b0f 12569 phba->cfg_irq_chann = 1;
2d7dbc4c 12570 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
2d7dbc4c
JS
12571 if (phba->nvmet_support)
12572 phba->cfg_nvmet_mrq = 1;
12573 }
cdb42bec 12574 }
6a828b0f 12575 lpfc_cpu_affinity_check(phba, phba->cfg_irq_chann);
cdb42bec
JS
12576
12577 /* Create SCSI host to the physical port */
12578 error = lpfc_create_shost(phba);
12579 if (error) {
12580 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12581 "1415 Failed to create scsi host.\n");
12582 goto out_disable_intr;
12583 }
12584 vport = phba->pport;
12585 shost = lpfc_shost_from_vport(vport); /* save shost for error cleanup */
12586
12587 /* Configure sysfs attributes */
12588 error = lpfc_alloc_sysfs_attr(vport);
12589 if (error) {
12590 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12591 "1416 Failed to allocate sysfs attr\n");
12592 goto out_destroy_shost;
895427bd
JS
12593 }
12594
7b15db32
JS
12595 /* Set up SLI-4 HBA */
12596 if (lpfc_sli4_hba_setup(phba)) {
12597 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12598 "1421 Failed to set up hba\n");
12599 error = -ENODEV;
cdb42bec 12600 goto out_free_sysfs_attr;
98c9ea5c 12601 }
858c9f6c 12602
7b15db32
JS
12603 /* Log the current active interrupt mode */
12604 phba->intr_mode = intr_mode;
12605 lpfc_log_intr_mode(phba, intr_mode);
12606
3772a991
JS
12607 /* Perform post initialization setup */
12608 lpfc_post_init_setup(phba);
dea3101e 12609
01649561
JS
12610 /* NVME support in FW earlier in the driver load corrects the
12611 * FC4 type making a check for nvme_support unnecessary.
12612 */
0794d601
JS
12613 if (phba->nvmet_support == 0) {
12614 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
12615 /* Create NVME binding with nvme_fc_transport. This
12616 * ensures the vport is initialized. If the localport
12617 * create fails, it should not unload the driver to
12618 * support field issues.
12619 */
12620 error = lpfc_nvme_create_localport(vport);
12621 if (error) {
12622 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12623 "6004 NVME registration "
12624 "failed, error x%x\n",
12625 error);
12626 }
01649561
JS
12627 }
12628 }
895427bd 12629
c71ab861
JS
12630 /* check for firmware upgrade or downgrade */
12631 if (phba->cfg_request_firmware_upgrade)
db6f1c2f 12632 lpfc_sli4_request_firmware_update(phba, INT_FW_UPGRADE);
52d52440 12633
1c6834a7
JS
12634 /* Check if there are static vports to be created. */
12635 lpfc_create_static_vport(phba);
d2cc9bcd
JS
12636
12637 /* Enable RAS FW log support */
12638 lpfc_sli4_ras_setup(phba);
12639
dea3101e 12640 return 0;
12641
5b75da2f
JS
12642out_free_sysfs_attr:
12643 lpfc_free_sysfs_attr(vport);
3772a991
JS
12644out_destroy_shost:
12645 lpfc_destroy_shost(phba);
cdb42bec
JS
12646out_disable_intr:
12647 lpfc_sli4_disable_intr(phba);
3772a991
JS
12648out_unset_driver_resource:
12649 lpfc_unset_driver_resource_phase2(phba);
da0436e9
JS
12650out_unset_driver_resource_s4:
12651 lpfc_sli4_driver_resource_unset(phba);
12652out_unset_pci_mem_s4:
12653 lpfc_sli4_pci_mem_unset(phba);
3772a991
JS
12654out_disable_pci_dev:
12655 lpfc_disable_pci_dev(phba);
6669f9bb
JS
12656 if (shost)
12657 scsi_host_put(shost);
2e0fef85 12658out_free_phba:
3772a991 12659 lpfc_hba_free(phba);
dea3101e 12660 return error;
12661}
12662
e59058c4 12663/**
da0436e9 12664 * lpfc_pci_remove_one_s4 - PCI func to unreg SLI-4 device from PCI subsystem
e59058c4
JS
12665 * @pdev: pointer to PCI device
12666 *
da0436e9
JS
12667 * This routine is called from the kernel's PCI subsystem to device with
12668 * SLI-4 interface spec. When an Emulex HBA with SLI-4 interface spec is
3772a991
JS
12669 * removed from PCI bus, it performs all the necessary cleanup for the HBA
12670 * device to be removed from the PCI subsystem properly.
e59058c4 12671 **/
6f039790 12672static void
da0436e9 12673lpfc_pci_remove_one_s4(struct pci_dev *pdev)
dea3101e 12674{
da0436e9 12675 struct Scsi_Host *shost = pci_get_drvdata(pdev);
2e0fef85 12676 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
eada272d 12677 struct lpfc_vport **vports;
da0436e9 12678 struct lpfc_hba *phba = vport->phba;
eada272d 12679 int i;
8a4df120 12680
da0436e9 12681 /* Mark the device unloading flag */
549e55cd 12682 spin_lock_irq(&phba->hbalock);
51ef4c26 12683 vport->load_flag |= FC_UNLOADING;
549e55cd 12684 spin_unlock_irq(&phba->hbalock);
2e0fef85 12685
da0436e9 12686 /* Free the HBA sysfs attributes */
858c9f6c
JS
12687 lpfc_free_sysfs_attr(vport);
12688
eada272d
JS
12689 /* Release all the vports against this physical port */
12690 vports = lpfc_create_vport_work_array(phba);
12691 if (vports != NULL)
587a37f6
JS
12692 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
12693 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
12694 continue;
eada272d 12695 fc_vport_terminate(vports[i]->fc_vport);
587a37f6 12696 }
eada272d
JS
12697 lpfc_destroy_vport_work_array(phba, vports);
12698
12699 /* Remove FC host and then SCSI host with the physical port */
858c9f6c
JS
12700 fc_remove_host(shost);
12701 scsi_remove_host(shost);
da0436e9 12702
d613b6a7
JS
12703 /* Perform ndlp cleanup on the physical port. The nvme and nvmet
12704 * localports are destroyed after to cleanup all transport memory.
895427bd 12705 */
87af33fe 12706 lpfc_cleanup(vport);
d613b6a7
JS
12707 lpfc_nvmet_destroy_targetport(phba);
12708 lpfc_nvme_destroy_localport(vport);
87af33fe 12709
c490850a
JS
12710 /* De-allocate multi-XRI pools */
12711 if (phba->cfg_xri_rebalancing)
12712 lpfc_destroy_multixri_pools(phba);
12713
281d6190
JS
12714 /*
12715 * Bring down the SLI Layer. This step disables all interrupts,
12716 * clears the rings, discards all mailbox commands, and resets
12717 * the HBA FCoE function.
12718 */
12719 lpfc_debugfs_terminate(vport);
a257bf90 12720
1901762f 12721 lpfc_stop_hba_timers(phba);
523128e5 12722 spin_lock_irq(&phba->port_list_lock);
858c9f6c 12723 list_del_init(&vport->listentry);
523128e5 12724 spin_unlock_irq(&phba->port_list_lock);
858c9f6c 12725
3677a3a7 12726 /* Perform scsi free before driver resource_unset since scsi
da0436e9 12727 * buffers are released to their corresponding pools here.
2e0fef85 12728 */
5e5b511d 12729 lpfc_io_free(phba);
01649561 12730 lpfc_free_iocb_list(phba);
5e5b511d 12731 lpfc_sli4_hba_unset(phba);
67d12733 12732
0cdb84ec 12733 lpfc_unset_driver_resource_phase2(phba);
da0436e9 12734 lpfc_sli4_driver_resource_unset(phba);
ed957684 12735
da0436e9
JS
12736 /* Unmap adapter Control and Doorbell registers */
12737 lpfc_sli4_pci_mem_unset(phba);
2e0fef85 12738
da0436e9
JS
12739 /* Release PCI resources and disable device's PCI function */
12740 scsi_host_put(shost);
12741 lpfc_disable_pci_dev(phba);
2e0fef85 12742
da0436e9 12743 /* Finally, free the driver's device data structure */
3772a991 12744 lpfc_hba_free(phba);
2e0fef85 12745
da0436e9 12746 return;
dea3101e 12747}
12748
3a55b532 12749/**
da0436e9 12750 * lpfc_pci_suspend_one_s4 - PCI func to suspend SLI-4 device for power mgmnt
3a55b532
JS
12751 * @pdev: pointer to PCI device
12752 * @msg: power management message
12753 *
da0436e9
JS
12754 * This routine is called from the kernel's PCI subsystem to support system
12755 * Power Management (PM) to device with SLI-4 interface spec. When PM invokes
12756 * this method, it quiesces the device by stopping the driver's worker
12757 * thread for the device, turning off device's interrupt and DMA, and bring
12758 * the device offline. Note that as the driver implements the minimum PM
12759 * requirements to a power-aware driver's PM support for suspend/resume -- all
12760 * the possible PM messages (SUSPEND, HIBERNATE, FREEZE) to the suspend()
12761 * method call will be treated as SUSPEND and the driver will fully
12762 * reinitialize its device during resume() method call, the driver will set
12763 * device to PCI_D3hot state in PCI config space instead of setting it
3772a991 12764 * according to the @msg provided by the PM.
3a55b532
JS
12765 *
12766 * Return code
3772a991
JS
12767 * 0 - driver suspended the device
12768 * Error otherwise
3a55b532
JS
12769 **/
12770static int
da0436e9 12771lpfc_pci_suspend_one_s4(struct pci_dev *pdev, pm_message_t msg)
3a55b532
JS
12772{
12773 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12774 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12775
12776 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
75baf696 12777 "2843 PCI device Power Management suspend.\n");
3a55b532
JS
12778
12779 /* Bring down the device */
618a5230 12780 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
3a55b532
JS
12781 lpfc_offline(phba);
12782 kthread_stop(phba->worker_thread);
12783
12784 /* Disable interrupt from device */
da0436e9 12785 lpfc_sli4_disable_intr(phba);
5350d872 12786 lpfc_sli4_queue_destroy(phba);
3a55b532
JS
12787
12788 /* Save device state to PCI config space */
12789 pci_save_state(pdev);
12790 pci_set_power_state(pdev, PCI_D3hot);
12791
12792 return 0;
12793}
12794
12795/**
da0436e9 12796 * lpfc_pci_resume_one_s4 - PCI func to resume SLI-4 device for power mgmnt
3a55b532
JS
12797 * @pdev: pointer to PCI device
12798 *
da0436e9
JS
12799 * This routine is called from the kernel's PCI subsystem to support system
12800 * Power Management (PM) to device with SLI-4 interface spac. When PM invokes
12801 * this method, it restores the device's PCI config space state and fully
12802 * reinitializes the device and brings it online. Note that as the driver
12803 * implements the minimum PM requirements to a power-aware driver's PM for
12804 * suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE, FREEZE)
12805 * to the suspend() method call will be treated as SUSPEND and the driver
12806 * will fully reinitialize its device during resume() method call, the device
12807 * will be set to PCI_D0 directly in PCI config space before restoring the
12808 * state.
3a55b532
JS
12809 *
12810 * Return code
3772a991
JS
12811 * 0 - driver suspended the device
12812 * Error otherwise
3a55b532
JS
12813 **/
12814static int
da0436e9 12815lpfc_pci_resume_one_s4(struct pci_dev *pdev)
3a55b532
JS
12816{
12817 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12818 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
5b75da2f 12819 uint32_t intr_mode;
3a55b532
JS
12820 int error;
12821
12822 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
da0436e9 12823 "0292 PCI device Power Management resume.\n");
3a55b532
JS
12824
12825 /* Restore device state from PCI config space */
12826 pci_set_power_state(pdev, PCI_D0);
12827 pci_restore_state(pdev);
1dfb5a47
JS
12828
12829 /*
12830 * As the new kernel behavior of pci_restore_state() API call clears
12831 * device saved_state flag, need to save the restored state again.
12832 */
12833 pci_save_state(pdev);
12834
3a55b532
JS
12835 if (pdev->is_busmaster)
12836 pci_set_master(pdev);
12837
da0436e9 12838 /* Startup the kernel thread for this host adapter. */
3a55b532
JS
12839 phba->worker_thread = kthread_run(lpfc_do_work, phba,
12840 "lpfc_worker_%d", phba->brd_no);
12841 if (IS_ERR(phba->worker_thread)) {
12842 error = PTR_ERR(phba->worker_thread);
12843 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 12844 "0293 PM resume failed to start worker "
3a55b532
JS
12845 "thread: error=x%x.\n", error);
12846 return error;
12847 }
12848
5b75da2f 12849 /* Configure and enable interrupt */
da0436e9 12850 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
5b75da2f 12851 if (intr_mode == LPFC_INTR_ERROR) {
3a55b532 12852 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 12853 "0294 PM resume Failed to enable interrupt\n");
5b75da2f
JS
12854 return -EIO;
12855 } else
12856 phba->intr_mode = intr_mode;
3a55b532
JS
12857
12858 /* Restart HBA and bring it online */
12859 lpfc_sli_brdrestart(phba);
12860 lpfc_online(phba);
12861
5b75da2f
JS
12862 /* Log the current active interrupt mode */
12863 lpfc_log_intr_mode(phba, phba->intr_mode);
12864
3a55b532
JS
12865 return 0;
12866}
12867
75baf696
JS
12868/**
12869 * lpfc_sli4_prep_dev_for_recover - Prepare SLI4 device for pci slot recover
12870 * @phba: pointer to lpfc hba data structure.
12871 *
12872 * This routine is called to prepare the SLI4 device for PCI slot recover. It
12873 * aborts all the outstanding SCSI I/Os to the pci device.
12874 **/
12875static void
12876lpfc_sli4_prep_dev_for_recover(struct lpfc_hba *phba)
12877{
75baf696
JS
12878 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12879 "2828 PCI channel I/O abort preparing for recovery\n");
12880 /*
12881 * There may be errored I/Os through HBA, abort all I/Os on txcmplq
12882 * and let the SCSI mid-layer to retry them to recover.
12883 */
db55fba8 12884 lpfc_sli_abort_fcp_rings(phba);
75baf696
JS
12885}
12886
12887/**
12888 * lpfc_sli4_prep_dev_for_reset - Prepare SLI4 device for pci slot reset
12889 * @phba: pointer to lpfc hba data structure.
12890 *
12891 * This routine is called to prepare the SLI4 device for PCI slot reset. It
12892 * disables the device interrupt and pci device, and aborts the internal FCP
12893 * pending I/Os.
12894 **/
12895static void
12896lpfc_sli4_prep_dev_for_reset(struct lpfc_hba *phba)
12897{
12898 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12899 "2826 PCI channel disable preparing for reset\n");
12900
12901 /* Block any management I/Os to the device */
618a5230 12902 lpfc_block_mgmt_io(phba, LPFC_MBX_NO_WAIT);
75baf696
JS
12903
12904 /* Block all SCSI devices' I/Os on the host */
12905 lpfc_scsi_dev_block(phba);
12906
c00f62e6
JS
12907 /* Flush all driver's outstanding I/Os as we are to reset */
12908 lpfc_sli_flush_io_rings(phba);
c3725bdc 12909
75baf696
JS
12910 /* stop all timers */
12911 lpfc_stop_hba_timers(phba);
12912
12913 /* Disable interrupt and pci device */
12914 lpfc_sli4_disable_intr(phba);
5350d872 12915 lpfc_sli4_queue_destroy(phba);
75baf696 12916 pci_disable_device(phba->pcidev);
75baf696
JS
12917}
12918
12919/**
12920 * lpfc_sli4_prep_dev_for_perm_failure - Prepare SLI4 dev for pci slot disable
12921 * @phba: pointer to lpfc hba data structure.
12922 *
12923 * This routine is called to prepare the SLI4 device for PCI slot permanently
12924 * disabling. It blocks the SCSI transport layer traffic and flushes the FCP
12925 * pending I/Os.
12926 **/
12927static void
12928lpfc_sli4_prep_dev_for_perm_failure(struct lpfc_hba *phba)
12929{
12930 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12931 "2827 PCI channel permanent disable for failure\n");
12932
12933 /* Block all SCSI devices' I/Os on the host */
12934 lpfc_scsi_dev_block(phba);
12935
12936 /* stop all timers */
12937 lpfc_stop_hba_timers(phba);
12938
c00f62e6
JS
12939 /* Clean up all driver's outstanding I/Os */
12940 lpfc_sli_flush_io_rings(phba);
75baf696
JS
12941}
12942
8d63f375 12943/**
da0436e9 12944 * lpfc_io_error_detected_s4 - Method for handling PCI I/O error to SLI-4 device
e59058c4
JS
12945 * @pdev: pointer to PCI device.
12946 * @state: the current PCI connection state.
8d63f375 12947 *
da0436e9
JS
12948 * This routine is called from the PCI subsystem for error handling to device
12949 * with SLI-4 interface spec. This function is called by the PCI subsystem
12950 * after a PCI bus error affecting this device has been detected. When this
12951 * function is invoked, it will need to stop all the I/Os and interrupt(s)
12952 * to the device. Once that is done, it will return PCI_ERS_RESULT_NEED_RESET
12953 * for the PCI subsystem to perform proper recovery as desired.
e59058c4
JS
12954 *
12955 * Return codes
3772a991
JS
12956 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
12957 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
e59058c4 12958 **/
3772a991 12959static pci_ers_result_t
da0436e9 12960lpfc_io_error_detected_s4(struct pci_dev *pdev, pci_channel_state_t state)
8d63f375 12961{
75baf696
JS
12962 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12963 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12964
12965 switch (state) {
12966 case pci_channel_io_normal:
12967 /* Non-fatal error, prepare for recovery */
12968 lpfc_sli4_prep_dev_for_recover(phba);
12969 return PCI_ERS_RESULT_CAN_RECOVER;
12970 case pci_channel_io_frozen:
12971 /* Fatal error, prepare for slot reset */
12972 lpfc_sli4_prep_dev_for_reset(phba);
12973 return PCI_ERS_RESULT_NEED_RESET;
12974 case pci_channel_io_perm_failure:
12975 /* Permanent failure, prepare for device down */
12976 lpfc_sli4_prep_dev_for_perm_failure(phba);
12977 return PCI_ERS_RESULT_DISCONNECT;
12978 default:
12979 /* Unknown state, prepare and request slot reset */
12980 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12981 "2825 Unknown PCI error state: x%x\n", state);
12982 lpfc_sli4_prep_dev_for_reset(phba);
12983 return PCI_ERS_RESULT_NEED_RESET;
12984 }
8d63f375
LV
12985}
12986
12987/**
da0436e9 12988 * lpfc_io_slot_reset_s4 - Method for restart PCI SLI-4 device from scratch
e59058c4
JS
12989 * @pdev: pointer to PCI device.
12990 *
da0436e9
JS
12991 * This routine is called from the PCI subsystem for error handling to device
12992 * with SLI-4 interface spec. It is called after PCI bus has been reset to
12993 * restart the PCI card from scratch, as if from a cold-boot. During the
12994 * PCI subsystem error recovery, after the driver returns
3772a991 12995 * PCI_ERS_RESULT_NEED_RESET, the PCI subsystem will perform proper error
da0436e9
JS
12996 * recovery and then call this routine before calling the .resume method to
12997 * recover the device. This function will initialize the HBA device, enable
12998 * the interrupt, but it will just put the HBA to offline state without
12999 * passing any I/O traffic.
8d63f375 13000 *
e59058c4 13001 * Return codes
3772a991
JS
13002 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
13003 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
8d63f375 13004 */
3772a991 13005static pci_ers_result_t
da0436e9 13006lpfc_io_slot_reset_s4(struct pci_dev *pdev)
8d63f375 13007{
75baf696
JS
13008 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13009 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13010 struct lpfc_sli *psli = &phba->sli;
13011 uint32_t intr_mode;
13012
13013 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
13014 if (pci_enable_device_mem(pdev)) {
13015 printk(KERN_ERR "lpfc: Cannot re-enable "
13016 "PCI device after reset.\n");
13017 return PCI_ERS_RESULT_DISCONNECT;
13018 }
13019
13020 pci_restore_state(pdev);
0a96e975
JS
13021
13022 /*
13023 * As the new kernel behavior of pci_restore_state() API call clears
13024 * device saved_state flag, need to save the restored state again.
13025 */
13026 pci_save_state(pdev);
13027
75baf696
JS
13028 if (pdev->is_busmaster)
13029 pci_set_master(pdev);
13030
13031 spin_lock_irq(&phba->hbalock);
13032 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
13033 spin_unlock_irq(&phba->hbalock);
13034
13035 /* Configure and enable interrupt */
13036 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
13037 if (intr_mode == LPFC_INTR_ERROR) {
13038 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13039 "2824 Cannot re-enable interrupt after "
13040 "slot reset.\n");
13041 return PCI_ERS_RESULT_DISCONNECT;
13042 } else
13043 phba->intr_mode = intr_mode;
13044
13045 /* Log the current active interrupt mode */
13046 lpfc_log_intr_mode(phba, phba->intr_mode);
13047
8d63f375
LV
13048 return PCI_ERS_RESULT_RECOVERED;
13049}
13050
13051/**
da0436e9 13052 * lpfc_io_resume_s4 - Method for resuming PCI I/O operation to SLI-4 device
e59058c4 13053 * @pdev: pointer to PCI device
8d63f375 13054 *
3772a991 13055 * This routine is called from the PCI subsystem for error handling to device
da0436e9 13056 * with SLI-4 interface spec. It is called when kernel error recovery tells
3772a991
JS
13057 * the lpfc driver that it is ok to resume normal PCI operation after PCI bus
13058 * error recovery. After this call, traffic can start to flow from this device
13059 * again.
da0436e9 13060 **/
3772a991 13061static void
da0436e9 13062lpfc_io_resume_s4(struct pci_dev *pdev)
8d63f375 13063{
75baf696
JS
13064 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13065 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13066
13067 /*
13068 * In case of slot reset, as function reset is performed through
13069 * mailbox command which needs DMA to be enabled, this operation
13070 * has to be moved to the io resume phase. Taking device offline
13071 * will perform the necessary cleanup.
13072 */
13073 if (!(phba->sli.sli_flag & LPFC_SLI_ACTIVE)) {
13074 /* Perform device reset */
618a5230 13075 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
75baf696
JS
13076 lpfc_offline(phba);
13077 lpfc_sli_brdrestart(phba);
13078 /* Bring the device back online */
13079 lpfc_online(phba);
13080 }
8d63f375
LV
13081}
13082
3772a991
JS
13083/**
13084 * lpfc_pci_probe_one - lpfc PCI probe func to reg dev to PCI subsystem
13085 * @pdev: pointer to PCI device
13086 * @pid: pointer to PCI device identifier
13087 *
13088 * This routine is to be registered to the kernel's PCI subsystem. When an
13089 * Emulex HBA device is presented on PCI bus, the kernel PCI subsystem looks
13090 * at PCI device-specific information of the device and driver to see if the
13091 * driver state that it can support this kind of device. If the match is
13092 * successful, the driver core invokes this routine. This routine dispatches
13093 * the action to the proper SLI-3 or SLI-4 device probing routine, which will
13094 * do all the initialization that it needs to do to handle the HBA device
13095 * properly.
13096 *
13097 * Return code
13098 * 0 - driver can claim the device
13099 * negative value - driver can not claim the device
13100 **/
6f039790 13101static int
3772a991
JS
13102lpfc_pci_probe_one(struct pci_dev *pdev, const struct pci_device_id *pid)
13103{
13104 int rc;
8fa38513 13105 struct lpfc_sli_intf intf;
3772a991 13106
28baac74 13107 if (pci_read_config_dword(pdev, LPFC_SLI_INTF, &intf.word0))
3772a991
JS
13108 return -ENODEV;
13109
8fa38513 13110 if ((bf_get(lpfc_sli_intf_valid, &intf) == LPFC_SLI_INTF_VALID) &&
28baac74 13111 (bf_get(lpfc_sli_intf_slirev, &intf) == LPFC_SLI_INTF_REV_SLI4))
da0436e9 13112 rc = lpfc_pci_probe_one_s4(pdev, pid);
8fa38513 13113 else
3772a991 13114 rc = lpfc_pci_probe_one_s3(pdev, pid);
8fa38513 13115
3772a991
JS
13116 return rc;
13117}
13118
13119/**
13120 * lpfc_pci_remove_one - lpfc PCI func to unreg dev from PCI subsystem
13121 * @pdev: pointer to PCI device
13122 *
13123 * This routine is to be registered to the kernel's PCI subsystem. When an
13124 * Emulex HBA is removed from PCI bus, the driver core invokes this routine.
13125 * This routine dispatches the action to the proper SLI-3 or SLI-4 device
13126 * remove routine, which will perform all the necessary cleanup for the
13127 * device to be removed from the PCI subsystem properly.
13128 **/
6f039790 13129static void
3772a991
JS
13130lpfc_pci_remove_one(struct pci_dev *pdev)
13131{
13132 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13133 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13134
13135 switch (phba->pci_dev_grp) {
13136 case LPFC_PCI_DEV_LP:
13137 lpfc_pci_remove_one_s3(pdev);
13138 break;
da0436e9
JS
13139 case LPFC_PCI_DEV_OC:
13140 lpfc_pci_remove_one_s4(pdev);
13141 break;
3772a991
JS
13142 default:
13143 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13144 "1424 Invalid PCI device group: 0x%x\n",
13145 phba->pci_dev_grp);
13146 break;
13147 }
13148 return;
13149}
13150
13151/**
13152 * lpfc_pci_suspend_one - lpfc PCI func to suspend dev for power management
13153 * @pdev: pointer to PCI device
13154 * @msg: power management message
13155 *
13156 * This routine is to be registered to the kernel's PCI subsystem to support
13157 * system Power Management (PM). When PM invokes this method, it dispatches
13158 * the action to the proper SLI-3 or SLI-4 device suspend routine, which will
13159 * suspend the device.
13160 *
13161 * Return code
13162 * 0 - driver suspended the device
13163 * Error otherwise
13164 **/
13165static int
13166lpfc_pci_suspend_one(struct pci_dev *pdev, pm_message_t msg)
13167{
13168 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13169 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13170 int rc = -ENODEV;
13171
13172 switch (phba->pci_dev_grp) {
13173 case LPFC_PCI_DEV_LP:
13174 rc = lpfc_pci_suspend_one_s3(pdev, msg);
13175 break;
da0436e9
JS
13176 case LPFC_PCI_DEV_OC:
13177 rc = lpfc_pci_suspend_one_s4(pdev, msg);
13178 break;
3772a991
JS
13179 default:
13180 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13181 "1425 Invalid PCI device group: 0x%x\n",
13182 phba->pci_dev_grp);
13183 break;
13184 }
13185 return rc;
13186}
13187
13188/**
13189 * lpfc_pci_resume_one - lpfc PCI func to resume dev for power management
13190 * @pdev: pointer to PCI device
13191 *
13192 * This routine is to be registered to the kernel's PCI subsystem to support
13193 * system Power Management (PM). When PM invokes this method, it dispatches
13194 * the action to the proper SLI-3 or SLI-4 device resume routine, which will
13195 * resume the device.
13196 *
13197 * Return code
13198 * 0 - driver suspended the device
13199 * Error otherwise
13200 **/
13201static int
13202lpfc_pci_resume_one(struct pci_dev *pdev)
13203{
13204 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13205 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13206 int rc = -ENODEV;
13207
13208 switch (phba->pci_dev_grp) {
13209 case LPFC_PCI_DEV_LP:
13210 rc = lpfc_pci_resume_one_s3(pdev);
13211 break;
da0436e9
JS
13212 case LPFC_PCI_DEV_OC:
13213 rc = lpfc_pci_resume_one_s4(pdev);
13214 break;
3772a991
JS
13215 default:
13216 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13217 "1426 Invalid PCI device group: 0x%x\n",
13218 phba->pci_dev_grp);
13219 break;
13220 }
13221 return rc;
13222}
13223
13224/**
13225 * lpfc_io_error_detected - lpfc method for handling PCI I/O error
13226 * @pdev: pointer to PCI device.
13227 * @state: the current PCI connection state.
13228 *
13229 * This routine is registered to the PCI subsystem for error handling. This
13230 * function is called by the PCI subsystem after a PCI bus error affecting
13231 * this device has been detected. When this routine is invoked, it dispatches
13232 * the action to the proper SLI-3 or SLI-4 device error detected handling
13233 * routine, which will perform the proper error detected operation.
13234 *
13235 * Return codes
13236 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
13237 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
13238 **/
13239static pci_ers_result_t
13240lpfc_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
13241{
13242 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13243 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13244 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
13245
13246 switch (phba->pci_dev_grp) {
13247 case LPFC_PCI_DEV_LP:
13248 rc = lpfc_io_error_detected_s3(pdev, state);
13249 break;
da0436e9
JS
13250 case LPFC_PCI_DEV_OC:
13251 rc = lpfc_io_error_detected_s4(pdev, state);
13252 break;
3772a991
JS
13253 default:
13254 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13255 "1427 Invalid PCI device group: 0x%x\n",
13256 phba->pci_dev_grp);
13257 break;
13258 }
13259 return rc;
13260}
13261
13262/**
13263 * lpfc_io_slot_reset - lpfc method for restart PCI dev from scratch
13264 * @pdev: pointer to PCI device.
13265 *
13266 * This routine is registered to the PCI subsystem for error handling. This
13267 * function is called after PCI bus has been reset to restart the PCI card
13268 * from scratch, as if from a cold-boot. When this routine is invoked, it
13269 * dispatches the action to the proper SLI-3 or SLI-4 device reset handling
13270 * routine, which will perform the proper device reset.
13271 *
13272 * Return codes
13273 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
13274 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
13275 **/
13276static pci_ers_result_t
13277lpfc_io_slot_reset(struct pci_dev *pdev)
13278{
13279 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13280 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13281 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
13282
13283 switch (phba->pci_dev_grp) {
13284 case LPFC_PCI_DEV_LP:
13285 rc = lpfc_io_slot_reset_s3(pdev);
13286 break;
da0436e9
JS
13287 case LPFC_PCI_DEV_OC:
13288 rc = lpfc_io_slot_reset_s4(pdev);
13289 break;
3772a991
JS
13290 default:
13291 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13292 "1428 Invalid PCI device group: 0x%x\n",
13293 phba->pci_dev_grp);
13294 break;
13295 }
13296 return rc;
13297}
13298
13299/**
13300 * lpfc_io_resume - lpfc method for resuming PCI I/O operation
13301 * @pdev: pointer to PCI device
13302 *
13303 * This routine is registered to the PCI subsystem for error handling. It
13304 * is called when kernel error recovery tells the lpfc driver that it is
13305 * OK to resume normal PCI operation after PCI bus error recovery. When
13306 * this routine is invoked, it dispatches the action to the proper SLI-3
13307 * or SLI-4 device io_resume routine, which will resume the device operation.
13308 **/
13309static void
13310lpfc_io_resume(struct pci_dev *pdev)
13311{
13312 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13313 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13314
13315 switch (phba->pci_dev_grp) {
13316 case LPFC_PCI_DEV_LP:
13317 lpfc_io_resume_s3(pdev);
13318 break;
da0436e9
JS
13319 case LPFC_PCI_DEV_OC:
13320 lpfc_io_resume_s4(pdev);
13321 break;
3772a991
JS
13322 default:
13323 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13324 "1429 Invalid PCI device group: 0x%x\n",
13325 phba->pci_dev_grp);
13326 break;
13327 }
13328 return;
13329}
13330
1ba981fd
JS
13331/**
13332 * lpfc_sli4_oas_verify - Verify OAS is supported by this adapter
13333 * @phba: pointer to lpfc hba data structure.
13334 *
13335 * This routine checks to see if OAS is supported for this adapter. If
13336 * supported, the configure Flash Optimized Fabric flag is set. Otherwise,
13337 * the enable oas flag is cleared and the pool created for OAS device data
13338 * is destroyed.
13339 *
13340 **/
c7092975 13341static void
1ba981fd
JS
13342lpfc_sli4_oas_verify(struct lpfc_hba *phba)
13343{
13344
13345 if (!phba->cfg_EnableXLane)
13346 return;
13347
13348 if (phba->sli4_hba.pc_sli4_params.oas_supported) {
13349 phba->cfg_fof = 1;
13350 } else {
f38fa0bb 13351 phba->cfg_fof = 0;
1ba981fd
JS
13352 if (phba->device_data_mem_pool)
13353 mempool_destroy(phba->device_data_mem_pool);
13354 phba->device_data_mem_pool = NULL;
13355 }
13356
13357 return;
13358}
13359
d2cc9bcd
JS
13360/**
13361 * lpfc_sli4_ras_init - Verify RAS-FW log is supported by this adapter
13362 * @phba: pointer to lpfc hba data structure.
13363 *
13364 * This routine checks to see if RAS is supported by the adapter. Check the
13365 * function through which RAS support enablement is to be done.
13366 **/
13367void
13368lpfc_sli4_ras_init(struct lpfc_hba *phba)
13369{
13370 switch (phba->pcidev->device) {
13371 case PCI_DEVICE_ID_LANCER_G6_FC:
13372 case PCI_DEVICE_ID_LANCER_G7_FC:
13373 phba->ras_fwlog.ras_hwsupport = true;
cb34990b
JS
13374 if (phba->cfg_ras_fwlog_func == PCI_FUNC(phba->pcidev->devfn) &&
13375 phba->cfg_ras_fwlog_buffsize)
d2cc9bcd
JS
13376 phba->ras_fwlog.ras_enabled = true;
13377 else
13378 phba->ras_fwlog.ras_enabled = false;
13379 break;
13380 default:
13381 phba->ras_fwlog.ras_hwsupport = false;
13382 }
13383}
13384
1ba981fd 13385
dea3101e 13386MODULE_DEVICE_TABLE(pci, lpfc_id_table);
13387
a55b2d21 13388static const struct pci_error_handlers lpfc_err_handler = {
8d63f375
LV
13389 .error_detected = lpfc_io_error_detected,
13390 .slot_reset = lpfc_io_slot_reset,
13391 .resume = lpfc_io_resume,
13392};
13393
dea3101e 13394static struct pci_driver lpfc_driver = {
13395 .name = LPFC_DRIVER_NAME,
13396 .id_table = lpfc_id_table,
13397 .probe = lpfc_pci_probe_one,
6f039790 13398 .remove = lpfc_pci_remove_one,
85e8a239 13399 .shutdown = lpfc_pci_remove_one,
3a55b532 13400 .suspend = lpfc_pci_suspend_one,
3772a991 13401 .resume = lpfc_pci_resume_one,
2e0fef85 13402 .err_handler = &lpfc_err_handler,
dea3101e 13403};
13404
3ef6d24c 13405static const struct file_operations lpfc_mgmt_fop = {
858feacd 13406 .owner = THIS_MODULE,
3ef6d24c
JS
13407};
13408
13409static struct miscdevice lpfc_mgmt_dev = {
13410 .minor = MISC_DYNAMIC_MINOR,
13411 .name = "lpfcmgmt",
13412 .fops = &lpfc_mgmt_fop,
13413};
13414
e59058c4 13415/**
3621a710 13416 * lpfc_init - lpfc module initialization routine
e59058c4
JS
13417 *
13418 * This routine is to be invoked when the lpfc module is loaded into the
13419 * kernel. The special kernel macro module_init() is used to indicate the
13420 * role of this routine to the kernel as lpfc module entry point.
13421 *
13422 * Return codes
13423 * 0 - successful
13424 * -ENOMEM - FC attach transport failed
13425 * all others - failed
13426 */
dea3101e 13427static int __init
13428lpfc_init(void)
13429{
13430 int error = 0;
13431
13432 printk(LPFC_MODULE_DESC "\n");
c44ce173 13433 printk(LPFC_COPYRIGHT "\n");
dea3101e 13434
3ef6d24c
JS
13435 error = misc_register(&lpfc_mgmt_dev);
13436 if (error)
13437 printk(KERN_ERR "Could not register lpfcmgmt device, "
13438 "misc_register returned with status %d", error);
13439
458c083e
JS
13440 lpfc_transport_functions.vport_create = lpfc_vport_create;
13441 lpfc_transport_functions.vport_delete = lpfc_vport_delete;
dea3101e 13442 lpfc_transport_template =
13443 fc_attach_transport(&lpfc_transport_functions);
7ee5d43e 13444 if (lpfc_transport_template == NULL)
dea3101e 13445 return -ENOMEM;
458c083e
JS
13446 lpfc_vport_transport_template =
13447 fc_attach_transport(&lpfc_vport_transport_functions);
13448 if (lpfc_vport_transport_template == NULL) {
13449 fc_release_transport(lpfc_transport_template);
13450 return -ENOMEM;
7ee5d43e 13451 }
5fd11085 13452 lpfc_nvme_cmd_template();
bd3061ba 13453 lpfc_nvmet_cmd_template();
7bb03bbf
JS
13454
13455 /* Initialize in case vector mapping is needed */
2ea259ee 13456 lpfc_present_cpu = num_present_cpus();
7bb03bbf 13457
dea3101e 13458 error = pci_register_driver(&lpfc_driver);
92d7f7b0 13459 if (error) {
dea3101e 13460 fc_release_transport(lpfc_transport_template);
458c083e 13461 fc_release_transport(lpfc_vport_transport_template);
92d7f7b0 13462 }
dea3101e 13463
13464 return error;
13465}
13466
e59058c4 13467/**
3621a710 13468 * lpfc_exit - lpfc module removal routine
e59058c4
JS
13469 *
13470 * This routine is invoked when the lpfc module is removed from the kernel.
13471 * The special kernel macro module_exit() is used to indicate the role of
13472 * this routine to the kernel as lpfc module exit point.
13473 */
dea3101e 13474static void __exit
13475lpfc_exit(void)
13476{
3ef6d24c 13477 misc_deregister(&lpfc_mgmt_dev);
dea3101e 13478 pci_unregister_driver(&lpfc_driver);
13479 fc_release_transport(lpfc_transport_template);
458c083e 13480 fc_release_transport(lpfc_vport_transport_template);
7973967f 13481 idr_destroy(&lpfc_hba_index);
dea3101e 13482}
13483
13484module_init(lpfc_init);
13485module_exit(lpfc_exit);
13486MODULE_LICENSE("GPL");
13487MODULE_DESCRIPTION(LPFC_MODULE_DESC);
d080abe0 13488MODULE_AUTHOR("Broadcom");
dea3101e 13489MODULE_VERSION("0:" LPFC_DRIVER_VERSION);