scsi: lpfc: Slight fast-path performance optimizations
[linux-2.6-block.git] / drivers / scsi / lpfc / lpfc_init.c
CommitLineData
dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
0d041215 4 * Copyright (C) 2017-2019 Broadcom. All Rights Reserved. The term *
3e21d1cb 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
50611577 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
c44ce173 7 * EMULEX and SLI are trademarks of Emulex. *
d080abe0 8 * www.broadcom.com *
c44ce173 9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e 10 * *
11 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC
12 * modify it under the terms of version 2 of the GNU General *
13 * Public License as published by the Free Software Foundation. *
14 * This program is distributed in the hope that it will be useful. *
15 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
16 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
18 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
19 * TO BE LEGALLY INVALID. See the GNU General Public License for *
20 * more details, a copy of which can be found in the file COPYING *
21 * included with this package. *
dea3101e 22 *******************************************************************/
23
dea3101e 24#include <linux/blkdev.h>
25#include <linux/delay.h>
26#include <linux/dma-mapping.h>
27#include <linux/idr.h>
28#include <linux/interrupt.h>
acf3368f 29#include <linux/module.h>
dea3101e 30#include <linux/kthread.h>
31#include <linux/pci.h>
32#include <linux/spinlock.h>
92d7f7b0 33#include <linux/ctype.h>
0d878419 34#include <linux/aer.h>
5a0e3ad6 35#include <linux/slab.h>
52d52440 36#include <linux/firmware.h>
3ef6d24c 37#include <linux/miscdevice.h>
7bb03bbf 38#include <linux/percpu.h>
895427bd 39#include <linux/msi.h>
6a828b0f 40#include <linux/irq.h>
286871a6 41#include <linux/bitops.h>
31f06d2e 42#include <linux/crash_dump.h>
dea3101e 43
91886523 44#include <scsi/scsi.h>
dea3101e 45#include <scsi/scsi_device.h>
46#include <scsi/scsi_host.h>
47#include <scsi/scsi_transport_fc.h>
86c67379
JS
48#include <scsi/scsi_tcq.h>
49#include <scsi/fc/fc_fs.h>
50
51#include <linux/nvme-fc-driver.h>
dea3101e 52
da0436e9 53#include "lpfc_hw4.h"
dea3101e 54#include "lpfc_hw.h"
55#include "lpfc_sli.h"
da0436e9 56#include "lpfc_sli4.h"
ea2151b4 57#include "lpfc_nl.h"
dea3101e 58#include "lpfc_disc.h"
dea3101e 59#include "lpfc.h"
895427bd
JS
60#include "lpfc_scsi.h"
61#include "lpfc_nvme.h"
86c67379 62#include "lpfc_nvmet.h"
dea3101e 63#include "lpfc_logmsg.h"
64#include "lpfc_crtn.h"
92d7f7b0 65#include "lpfc_vport.h"
dea3101e 66#include "lpfc_version.h"
12f44457 67#include "lpfc_ids.h"
dea3101e 68
7bb03bbf 69/* Used when mapping IRQ vectors in a driver centric manner */
d7b761b0 70static uint32_t lpfc_present_cpu;
7bb03bbf 71
dea3101e 72static void lpfc_get_hba_model_desc(struct lpfc_hba *, uint8_t *, uint8_t *);
73static int lpfc_post_rcv_buf(struct lpfc_hba *);
5350d872 74static int lpfc_sli4_queue_verify(struct lpfc_hba *);
da0436e9
JS
75static int lpfc_create_bootstrap_mbox(struct lpfc_hba *);
76static int lpfc_setup_endian_order(struct lpfc_hba *);
da0436e9 77static void lpfc_destroy_bootstrap_mbox(struct lpfc_hba *);
8a9d2e80 78static void lpfc_free_els_sgl_list(struct lpfc_hba *);
f358dd0c 79static void lpfc_free_nvmet_sgl_list(struct lpfc_hba *);
8a9d2e80 80static void lpfc_init_sgl_list(struct lpfc_hba *);
da0436e9
JS
81static int lpfc_init_active_sgl_array(struct lpfc_hba *);
82static void lpfc_free_active_sgl(struct lpfc_hba *);
83static int lpfc_hba_down_post_s3(struct lpfc_hba *phba);
84static int lpfc_hba_down_post_s4(struct lpfc_hba *phba);
85static int lpfc_sli4_cq_event_pool_create(struct lpfc_hba *);
86static void lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *);
87static void lpfc_sli4_cq_event_release_all(struct lpfc_hba *);
618a5230
JS
88static void lpfc_sli4_disable_intr(struct lpfc_hba *);
89static uint32_t lpfc_sli4_enable_intr(struct lpfc_hba *, uint32_t);
1ba981fd 90static void lpfc_sli4_oas_verify(struct lpfc_hba *phba);
6a828b0f 91static uint16_t lpfc_find_cpu_handle(struct lpfc_hba *, uint16_t, int);
aa6ff309 92static void lpfc_setup_bg(struct lpfc_hba *, struct Scsi_Host *);
dea3101e 93
94static struct scsi_transport_template *lpfc_transport_template = NULL;
92d7f7b0 95static struct scsi_transport_template *lpfc_vport_transport_template = NULL;
dea3101e 96static DEFINE_IDR(lpfc_hba_index);
f358dd0c 97#define LPFC_NVMET_BUF_POST 254
dea3101e 98
e59058c4 99/**
3621a710 100 * lpfc_config_port_prep - Perform lpfc initialization prior to config port
e59058c4
JS
101 * @phba: pointer to lpfc hba data structure.
102 *
103 * This routine will do LPFC initialization prior to issuing the CONFIG_PORT
104 * mailbox command. It retrieves the revision information from the HBA and
105 * collects the Vital Product Data (VPD) about the HBA for preparing the
106 * configuration of the HBA.
107 *
108 * Return codes:
109 * 0 - success.
110 * -ERESTART - requests the SLI layer to reset the HBA and try again.
111 * Any other value - indicates an error.
112 **/
dea3101e 113int
2e0fef85 114lpfc_config_port_prep(struct lpfc_hba *phba)
dea3101e 115{
116 lpfc_vpd_t *vp = &phba->vpd;
117 int i = 0, rc;
118 LPFC_MBOXQ_t *pmb;
119 MAILBOX_t *mb;
120 char *lpfc_vpd_data = NULL;
121 uint16_t offset = 0;
122 static char licensed[56] =
123 "key unlock for use with gnu public licensed code only\0";
65a29c16 124 static int init_key = 1;
dea3101e 125
126 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
127 if (!pmb) {
2e0fef85 128 phba->link_state = LPFC_HBA_ERROR;
dea3101e 129 return -ENOMEM;
130 }
131
04c68496 132 mb = &pmb->u.mb;
2e0fef85 133 phba->link_state = LPFC_INIT_MBX_CMDS;
dea3101e 134
135 if (lpfc_is_LC_HBA(phba->pcidev->device)) {
65a29c16
JS
136 if (init_key) {
137 uint32_t *ptext = (uint32_t *) licensed;
dea3101e 138
65a29c16
JS
139 for (i = 0; i < 56; i += sizeof (uint32_t), ptext++)
140 *ptext = cpu_to_be32(*ptext);
141 init_key = 0;
142 }
dea3101e 143
144 lpfc_read_nv(phba, pmb);
145 memset((char*)mb->un.varRDnvp.rsvd3, 0,
146 sizeof (mb->un.varRDnvp.rsvd3));
147 memcpy((char*)mb->un.varRDnvp.rsvd3, licensed,
148 sizeof (licensed));
149
150 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
151
152 if (rc != MBX_SUCCESS) {
ed957684 153 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
e8b62011 154 "0324 Config Port initialization "
dea3101e 155 "error, mbxCmd x%x READ_NVPARM, "
156 "mbxStatus x%x\n",
dea3101e 157 mb->mbxCommand, mb->mbxStatus);
158 mempool_free(pmb, phba->mbox_mem_pool);
159 return -ERESTART;
160 }
161 memcpy(phba->wwnn, (char *)mb->un.varRDnvp.nodename,
2e0fef85
JS
162 sizeof(phba->wwnn));
163 memcpy(phba->wwpn, (char *)mb->un.varRDnvp.portname,
164 sizeof(phba->wwpn));
dea3101e 165 }
166
dfb75133
MW
167 /*
168 * Clear all option bits except LPFC_SLI3_BG_ENABLED,
169 * which was already set in lpfc_get_cfgparam()
170 */
171 phba->sli3_options &= (uint32_t)LPFC_SLI3_BG_ENABLED;
92d7f7b0 172
dea3101e 173 /* Setup and issue mailbox READ REV command */
174 lpfc_read_rev(phba, pmb);
175 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
176 if (rc != MBX_SUCCESS) {
ed957684 177 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011 178 "0439 Adapter failed to init, mbxCmd x%x "
dea3101e 179 "READ_REV, mbxStatus x%x\n",
dea3101e 180 mb->mbxCommand, mb->mbxStatus);
181 mempool_free( pmb, phba->mbox_mem_pool);
182 return -ERESTART;
183 }
184
92d7f7b0 185
1de933f3
JSEC
186 /*
187 * The value of rr must be 1 since the driver set the cv field to 1.
188 * This setting requires the FW to set all revision fields.
dea3101e 189 */
1de933f3 190 if (mb->un.varRdRev.rr == 0) {
dea3101e 191 vp->rev.rBit = 0;
1de933f3 192 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011
JS
193 "0440 Adapter failed to init, READ_REV has "
194 "missing revision information.\n");
dea3101e 195 mempool_free(pmb, phba->mbox_mem_pool);
196 return -ERESTART;
dea3101e 197 }
198
495a714c
JS
199 if (phba->sli_rev == 3 && !mb->un.varRdRev.v3rsp) {
200 mempool_free(pmb, phba->mbox_mem_pool);
ed957684 201 return -EINVAL;
495a714c 202 }
ed957684 203
dea3101e 204 /* Save information as VPD data */
1de933f3 205 vp->rev.rBit = 1;
92d7f7b0 206 memcpy(&vp->sli3Feat, &mb->un.varRdRev.sli3Feat, sizeof(uint32_t));
1de933f3
JSEC
207 vp->rev.sli1FwRev = mb->un.varRdRev.sli1FwRev;
208 memcpy(vp->rev.sli1FwName, (char*) mb->un.varRdRev.sli1FwName, 16);
209 vp->rev.sli2FwRev = mb->un.varRdRev.sli2FwRev;
210 memcpy(vp->rev.sli2FwName, (char *) mb->un.varRdRev.sli2FwName, 16);
dea3101e 211 vp->rev.biuRev = mb->un.varRdRev.biuRev;
212 vp->rev.smRev = mb->un.varRdRev.smRev;
213 vp->rev.smFwRev = mb->un.varRdRev.un.smFwRev;
214 vp->rev.endecRev = mb->un.varRdRev.endecRev;
215 vp->rev.fcphHigh = mb->un.varRdRev.fcphHigh;
216 vp->rev.fcphLow = mb->un.varRdRev.fcphLow;
217 vp->rev.feaLevelHigh = mb->un.varRdRev.feaLevelHigh;
218 vp->rev.feaLevelLow = mb->un.varRdRev.feaLevelLow;
219 vp->rev.postKernRev = mb->un.varRdRev.postKernRev;
220 vp->rev.opFwRev = mb->un.varRdRev.opFwRev;
221
92d7f7b0
JS
222 /* If the sli feature level is less then 9, we must
223 * tear down all RPIs and VPIs on link down if NPIV
224 * is enabled.
225 */
226 if (vp->rev.feaLevelHigh < 9)
227 phba->sli3_options |= LPFC_SLI3_VPORT_TEARDOWN;
228
dea3101e 229 if (lpfc_is_LC_HBA(phba->pcidev->device))
230 memcpy(phba->RandomData, (char *)&mb->un.varWords[24],
231 sizeof (phba->RandomData));
232
dea3101e 233 /* Get adapter VPD information */
dea3101e 234 lpfc_vpd_data = kmalloc(DMP_VPD_SIZE, GFP_KERNEL);
235 if (!lpfc_vpd_data)
d7c255b2 236 goto out_free_mbox;
dea3101e 237 do {
a0c87cbd 238 lpfc_dump_mem(phba, pmb, offset, DMP_REGION_VPD);
dea3101e 239 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
240
241 if (rc != MBX_SUCCESS) {
242 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011 243 "0441 VPD not present on adapter, "
dea3101e 244 "mbxCmd x%x DUMP VPD, mbxStatus x%x\n",
dea3101e 245 mb->mbxCommand, mb->mbxStatus);
74b72a59 246 mb->un.varDmp.word_cnt = 0;
dea3101e 247 }
04c68496
JS
248 /* dump mem may return a zero when finished or we got a
249 * mailbox error, either way we are done.
250 */
251 if (mb->un.varDmp.word_cnt == 0)
252 break;
74b72a59
JW
253 if (mb->un.varDmp.word_cnt > DMP_VPD_SIZE - offset)
254 mb->un.varDmp.word_cnt = DMP_VPD_SIZE - offset;
d7c255b2
JS
255 lpfc_sli_pcimem_bcopy(((uint8_t *)mb) + DMP_RSP_OFFSET,
256 lpfc_vpd_data + offset,
92d7f7b0 257 mb->un.varDmp.word_cnt);
dea3101e 258 offset += mb->un.varDmp.word_cnt;
74b72a59
JW
259 } while (mb->un.varDmp.word_cnt && offset < DMP_VPD_SIZE);
260 lpfc_parse_vpd(phba, lpfc_vpd_data, offset);
dea3101e 261
262 kfree(lpfc_vpd_data);
dea3101e 263out_free_mbox:
264 mempool_free(pmb, phba->mbox_mem_pool);
265 return 0;
266}
267
e59058c4 268/**
3621a710 269 * lpfc_config_async_cmpl - Completion handler for config async event mbox cmd
e59058c4
JS
270 * @phba: pointer to lpfc hba data structure.
271 * @pmboxq: pointer to the driver internal queue element for mailbox command.
272 *
273 * This is the completion handler for driver's configuring asynchronous event
274 * mailbox command to the device. If the mailbox command returns successfully,
275 * it will set internal async event support flag to 1; otherwise, it will
276 * set internal async event support flag to 0.
277 **/
57127f15
JS
278static void
279lpfc_config_async_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
280{
04c68496 281 if (pmboxq->u.mb.mbxStatus == MBX_SUCCESS)
57127f15
JS
282 phba->temp_sensor_support = 1;
283 else
284 phba->temp_sensor_support = 0;
285 mempool_free(pmboxq, phba->mbox_mem_pool);
286 return;
287}
288
97207482 289/**
3621a710 290 * lpfc_dump_wakeup_param_cmpl - dump memory mailbox command completion handler
97207482
JS
291 * @phba: pointer to lpfc hba data structure.
292 * @pmboxq: pointer to the driver internal queue element for mailbox command.
293 *
294 * This is the completion handler for dump mailbox command for getting
295 * wake up parameters. When this command complete, the response contain
296 * Option rom version of the HBA. This function translate the version number
297 * into a human readable string and store it in OptionROMVersion.
298 **/
299static void
300lpfc_dump_wakeup_param_cmpl(struct lpfc_hba *phba, LPFC_MBOXQ_t *pmboxq)
301{
302 struct prog_id *prg;
303 uint32_t prog_id_word;
304 char dist = ' ';
305 /* character array used for decoding dist type. */
306 char dist_char[] = "nabx";
307
04c68496 308 if (pmboxq->u.mb.mbxStatus != MBX_SUCCESS) {
9f1e1b50 309 mempool_free(pmboxq, phba->mbox_mem_pool);
97207482 310 return;
9f1e1b50 311 }
97207482
JS
312
313 prg = (struct prog_id *) &prog_id_word;
314
315 /* word 7 contain option rom version */
04c68496 316 prog_id_word = pmboxq->u.mb.un.varWords[7];
97207482
JS
317
318 /* Decode the Option rom version word to a readable string */
319 if (prg->dist < 4)
320 dist = dist_char[prg->dist];
321
322 if ((prg->dist == 3) && (prg->num == 0))
a2fc4aef 323 snprintf(phba->OptionROMVersion, 32, "%d.%d%d",
97207482
JS
324 prg->ver, prg->rev, prg->lev);
325 else
a2fc4aef 326 snprintf(phba->OptionROMVersion, 32, "%d.%d%d%c%d",
97207482
JS
327 prg->ver, prg->rev, prg->lev,
328 dist, prg->num);
9f1e1b50 329 mempool_free(pmboxq, phba->mbox_mem_pool);
97207482
JS
330 return;
331}
332
0558056c
JS
333/**
334 * lpfc_update_vport_wwn - Updates the fc_nodename, fc_portname,
335 * cfg_soft_wwnn, cfg_soft_wwpn
336 * @vport: pointer to lpfc vport data structure.
337 *
338 *
339 * Return codes
340 * None.
341 **/
342void
343lpfc_update_vport_wwn(struct lpfc_vport *vport)
344{
aeb3c817
JS
345 uint8_t vvvl = vport->fc_sparam.cmn.valid_vendor_ver_level;
346 u32 *fawwpn_key = (u32 *)&vport->fc_sparam.un.vendorVersion[0];
347
0558056c
JS
348 /* If the soft name exists then update it using the service params */
349 if (vport->phba->cfg_soft_wwnn)
350 u64_to_wwn(vport->phba->cfg_soft_wwnn,
351 vport->fc_sparam.nodeName.u.wwn);
352 if (vport->phba->cfg_soft_wwpn)
353 u64_to_wwn(vport->phba->cfg_soft_wwpn,
354 vport->fc_sparam.portName.u.wwn);
355
356 /*
357 * If the name is empty or there exists a soft name
358 * then copy the service params name, otherwise use the fc name
359 */
360 if (vport->fc_nodename.u.wwn[0] == 0 || vport->phba->cfg_soft_wwnn)
361 memcpy(&vport->fc_nodename, &vport->fc_sparam.nodeName,
362 sizeof(struct lpfc_name));
363 else
364 memcpy(&vport->fc_sparam.nodeName, &vport->fc_nodename,
365 sizeof(struct lpfc_name));
366
aeb3c817
JS
367 /*
368 * If the port name has changed, then set the Param changes flag
369 * to unreg the login
370 */
371 if (vport->fc_portname.u.wwn[0] != 0 &&
372 memcmp(&vport->fc_portname, &vport->fc_sparam.portName,
373 sizeof(struct lpfc_name)))
374 vport->vport_flag |= FAWWPN_PARAM_CHG;
375
376 if (vport->fc_portname.u.wwn[0] == 0 ||
377 vport->phba->cfg_soft_wwpn ||
378 (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR) ||
379 vport->vport_flag & FAWWPN_SET) {
0558056c
JS
380 memcpy(&vport->fc_portname, &vport->fc_sparam.portName,
381 sizeof(struct lpfc_name));
aeb3c817
JS
382 vport->vport_flag &= ~FAWWPN_SET;
383 if (vvvl == 1 && cpu_to_be32(*fawwpn_key) == FAPWWN_KEY_VENDOR)
384 vport->vport_flag |= FAWWPN_SET;
385 }
0558056c
JS
386 else
387 memcpy(&vport->fc_sparam.portName, &vport->fc_portname,
388 sizeof(struct lpfc_name));
389}
390
e59058c4 391/**
3621a710 392 * lpfc_config_port_post - Perform lpfc initialization after config port
e59058c4
JS
393 * @phba: pointer to lpfc hba data structure.
394 *
395 * This routine will do LPFC initialization after the CONFIG_PORT mailbox
396 * command call. It performs all internal resource and state setups on the
397 * port: post IOCB buffers, enable appropriate host interrupt attentions,
398 * ELS ring timers, etc.
399 *
400 * Return codes
401 * 0 - success.
402 * Any other value - error.
403 **/
dea3101e 404int
2e0fef85 405lpfc_config_port_post(struct lpfc_hba *phba)
dea3101e 406{
2e0fef85 407 struct lpfc_vport *vport = phba->pport;
a257bf90 408 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
dea3101e 409 LPFC_MBOXQ_t *pmb;
410 MAILBOX_t *mb;
411 struct lpfc_dmabuf *mp;
412 struct lpfc_sli *psli = &phba->sli;
413 uint32_t status, timeout;
2e0fef85
JS
414 int i, j;
415 int rc;
dea3101e 416
7af67051
JS
417 spin_lock_irq(&phba->hbalock);
418 /*
419 * If the Config port completed correctly the HBA is not
420 * over heated any more.
421 */
422 if (phba->over_temp_state == HBA_OVER_TEMP)
423 phba->over_temp_state = HBA_NORMAL_TEMP;
424 spin_unlock_irq(&phba->hbalock);
425
dea3101e 426 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
427 if (!pmb) {
2e0fef85 428 phba->link_state = LPFC_HBA_ERROR;
dea3101e 429 return -ENOMEM;
430 }
04c68496 431 mb = &pmb->u.mb;
dea3101e 432
dea3101e 433 /* Get login parameters for NID. */
9f1177a3
JS
434 rc = lpfc_read_sparam(phba, pmb, 0);
435 if (rc) {
436 mempool_free(pmb, phba->mbox_mem_pool);
437 return -ENOMEM;
438 }
439
ed957684 440 pmb->vport = vport;
dea3101e 441 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
ed957684 442 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011 443 "0448 Adapter failed init, mbxCmd x%x "
dea3101e 444 "READ_SPARM mbxStatus x%x\n",
dea3101e 445 mb->mbxCommand, mb->mbxStatus);
2e0fef85 446 phba->link_state = LPFC_HBA_ERROR;
3e1f0718 447 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
9f1177a3 448 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 449 lpfc_mbuf_free(phba, mp->virt, mp->phys);
450 kfree(mp);
451 return -EIO;
452 }
453
3e1f0718 454 mp = (struct lpfc_dmabuf *)pmb->ctx_buf;
dea3101e 455
2e0fef85 456 memcpy(&vport->fc_sparam, mp->virt, sizeof (struct serv_parm));
dea3101e 457 lpfc_mbuf_free(phba, mp->virt, mp->phys);
458 kfree(mp);
3e1f0718 459 pmb->ctx_buf = NULL;
0558056c 460 lpfc_update_vport_wwn(vport);
a257bf90
JS
461
462 /* Update the fc_host data structures with new wwn. */
463 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
464 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
21e9a0a5 465 fc_host_max_npiv_vports(shost) = phba->max_vpi;
a257bf90 466
dea3101e 467 /* If no serial number in VPD data, use low 6 bytes of WWNN */
468 /* This should be consolidated into parse_vpd ? - mr */
469 if (phba->SerialNumber[0] == 0) {
470 uint8_t *outptr;
471
2e0fef85 472 outptr = &vport->fc_nodename.u.s.IEEE[0];
dea3101e 473 for (i = 0; i < 12; i++) {
474 status = *outptr++;
475 j = ((status & 0xf0) >> 4);
476 if (j <= 9)
477 phba->SerialNumber[i] =
478 (char)((uint8_t) 0x30 + (uint8_t) j);
479 else
480 phba->SerialNumber[i] =
481 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
482 i++;
483 j = (status & 0xf);
484 if (j <= 9)
485 phba->SerialNumber[i] =
486 (char)((uint8_t) 0x30 + (uint8_t) j);
487 else
488 phba->SerialNumber[i] =
489 (char)((uint8_t) 0x61 + (uint8_t) (j - 10));
490 }
491 }
492
dea3101e 493 lpfc_read_config(phba, pmb);
ed957684 494 pmb->vport = vport;
dea3101e 495 if (lpfc_sli_issue_mbox(phba, pmb, MBX_POLL) != MBX_SUCCESS) {
ed957684 496 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011 497 "0453 Adapter failed to init, mbxCmd x%x "
dea3101e 498 "READ_CONFIG, mbxStatus x%x\n",
dea3101e 499 mb->mbxCommand, mb->mbxStatus);
2e0fef85 500 phba->link_state = LPFC_HBA_ERROR;
dea3101e 501 mempool_free( pmb, phba->mbox_mem_pool);
502 return -EIO;
503 }
504
a0c87cbd
JS
505 /* Check if the port is disabled */
506 lpfc_sli_read_link_ste(phba);
507
dea3101e 508 /* Reset the DFT_HBA_Q_DEPTH to the max xri */
572709e2
JS
509 i = (mb->un.varRdConfig.max_xri + 1);
510 if (phba->cfg_hba_queue_depth > i) {
511 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
512 "3359 HBA queue depth changed from %d to %d\n",
513 phba->cfg_hba_queue_depth, i);
514 phba->cfg_hba_queue_depth = i;
515 }
516
517 /* Reset the DFT_LUN_Q_DEPTH to (max xri >> 3) */
518 i = (mb->un.varRdConfig.max_xri >> 3);
519 if (phba->pport->cfg_lun_queue_depth > i) {
520 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
521 "3360 LUN queue depth changed from %d to %d\n",
522 phba->pport->cfg_lun_queue_depth, i);
523 phba->pport->cfg_lun_queue_depth = i;
524 }
dea3101e 525
526 phba->lmt = mb->un.varRdConfig.lmt;
74b72a59
JW
527
528 /* Get the default values for Model Name and Description */
529 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
530
2e0fef85 531 phba->link_state = LPFC_LINK_DOWN;
dea3101e 532
0b727fea 533 /* Only process IOCBs on ELS ring till hba_state is READY */
895427bd
JS
534 if (psli->sli3_ring[LPFC_EXTRA_RING].sli.sli3.cmdringaddr)
535 psli->sli3_ring[LPFC_EXTRA_RING].flag |= LPFC_STOP_IOCB_EVENT;
536 if (psli->sli3_ring[LPFC_FCP_RING].sli.sli3.cmdringaddr)
537 psli->sli3_ring[LPFC_FCP_RING].flag |= LPFC_STOP_IOCB_EVENT;
dea3101e 538
539 /* Post receive buffers for desired rings */
ed957684
JS
540 if (phba->sli_rev != 3)
541 lpfc_post_rcv_buf(phba);
dea3101e 542
9399627f
JS
543 /*
544 * Configure HBA MSI-X attention conditions to messages if MSI-X mode
545 */
546 if (phba->intr_type == MSIX) {
547 rc = lpfc_config_msi(phba, pmb);
548 if (rc) {
549 mempool_free(pmb, phba->mbox_mem_pool);
550 return -EIO;
551 }
552 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
553 if (rc != MBX_SUCCESS) {
554 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
555 "0352 Config MSI mailbox command "
556 "failed, mbxCmd x%x, mbxStatus x%x\n",
04c68496
JS
557 pmb->u.mb.mbxCommand,
558 pmb->u.mb.mbxStatus);
9399627f
JS
559 mempool_free(pmb, phba->mbox_mem_pool);
560 return -EIO;
561 }
562 }
563
04c68496 564 spin_lock_irq(&phba->hbalock);
9399627f
JS
565 /* Initialize ERATT handling flag */
566 phba->hba_flag &= ~HBA_ERATT_HANDLED;
567
dea3101e 568 /* Enable appropriate host interrupts */
9940b97b
JS
569 if (lpfc_readl(phba->HCregaddr, &status)) {
570 spin_unlock_irq(&phba->hbalock);
571 return -EIO;
572 }
dea3101e 573 status |= HC_MBINT_ENA | HC_ERINT_ENA | HC_LAINT_ENA;
574 if (psli->num_rings > 0)
575 status |= HC_R0INT_ENA;
576 if (psli->num_rings > 1)
577 status |= HC_R1INT_ENA;
578 if (psli->num_rings > 2)
579 status |= HC_R2INT_ENA;
580 if (psli->num_rings > 3)
581 status |= HC_R3INT_ENA;
582
875fbdfe
JSEC
583 if ((phba->cfg_poll & ENABLE_FCP_RING_POLLING) &&
584 (phba->cfg_poll & DISABLE_FCP_RING_INT))
9399627f 585 status &= ~(HC_R0INT_ENA);
875fbdfe 586
dea3101e 587 writel(status, phba->HCregaddr);
588 readl(phba->HCregaddr); /* flush */
2e0fef85 589 spin_unlock_irq(&phba->hbalock);
dea3101e 590
9399627f
JS
591 /* Set up ring-0 (ELS) timer */
592 timeout = phba->fc_ratov * 2;
256ec0d0
JS
593 mod_timer(&vport->els_tmofunc,
594 jiffies + msecs_to_jiffies(1000 * timeout));
9399627f 595 /* Set up heart beat (HB) timer */
256ec0d0
JS
596 mod_timer(&phba->hb_tmofunc,
597 jiffies + msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
598 phba->hb_outstanding = 0;
599 phba->last_completion_time = jiffies;
9399627f 600 /* Set up error attention (ERATT) polling timer */
256ec0d0 601 mod_timer(&phba->eratt_poll,
65791f1f 602 jiffies + msecs_to_jiffies(1000 * phba->eratt_poll_interval));
dea3101e 603
a0c87cbd
JS
604 if (phba->hba_flag & LINK_DISABLED) {
605 lpfc_printf_log(phba,
606 KERN_ERR, LOG_INIT,
607 "2598 Adapter Link is disabled.\n");
608 lpfc_down_link(phba, pmb);
609 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
610 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
611 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
612 lpfc_printf_log(phba,
613 KERN_ERR, LOG_INIT,
614 "2599 Adapter failed to issue DOWN_LINK"
615 " mbox command rc 0x%x\n", rc);
616
617 mempool_free(pmb, phba->mbox_mem_pool);
618 return -EIO;
619 }
e40a02c1 620 } else if (phba->cfg_suppress_link_up == LPFC_INITIALIZE_LINK) {
026abb87
JS
621 mempool_free(pmb, phba->mbox_mem_pool);
622 rc = phba->lpfc_hba_init_link(phba, MBX_NOWAIT);
623 if (rc)
624 return rc;
dea3101e 625 }
626 /* MBOX buffer will be freed in mbox compl */
57127f15 627 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9f1177a3
JS
628 if (!pmb) {
629 phba->link_state = LPFC_HBA_ERROR;
630 return -ENOMEM;
631 }
632
57127f15
JS
633 lpfc_config_async(phba, pmb, LPFC_ELS_RING);
634 pmb->mbox_cmpl = lpfc_config_async_cmpl;
635 pmb->vport = phba->pport;
636 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
dea3101e 637
57127f15
JS
638 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
639 lpfc_printf_log(phba,
640 KERN_ERR,
641 LOG_INIT,
642 "0456 Adapter failed to issue "
e4e74273 643 "ASYNCEVT_ENABLE mbox status x%x\n",
57127f15
JS
644 rc);
645 mempool_free(pmb, phba->mbox_mem_pool);
646 }
97207482
JS
647
648 /* Get Option rom version */
649 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9f1177a3
JS
650 if (!pmb) {
651 phba->link_state = LPFC_HBA_ERROR;
652 return -ENOMEM;
653 }
654
97207482
JS
655 lpfc_dump_wakeup_param(phba, pmb);
656 pmb->mbox_cmpl = lpfc_dump_wakeup_param_cmpl;
657 pmb->vport = phba->pport;
658 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
659
660 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
661 lpfc_printf_log(phba, KERN_ERR, LOG_INIT, "0435 Adapter failed "
e4e74273 662 "to get Option ROM version status x%x\n", rc);
97207482
JS
663 mempool_free(pmb, phba->mbox_mem_pool);
664 }
665
d7c255b2 666 return 0;
ce8b3ce5
JS
667}
668
84d1b006
JS
669/**
670 * lpfc_hba_init_link - Initialize the FC link
671 * @phba: pointer to lpfc hba data structure.
6e7288d9 672 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
84d1b006
JS
673 *
674 * This routine will issue the INIT_LINK mailbox command call.
675 * It is available to other drivers through the lpfc_hba data
676 * structure for use as a delayed link up mechanism with the
677 * module parameter lpfc_suppress_link_up.
678 *
679 * Return code
680 * 0 - success
681 * Any other value - error
682 **/
e399b228 683static int
6e7288d9 684lpfc_hba_init_link(struct lpfc_hba *phba, uint32_t flag)
1b51197d
JS
685{
686 return lpfc_hba_init_link_fc_topology(phba, phba->cfg_topology, flag);
687}
688
689/**
690 * lpfc_hba_init_link_fc_topology - Initialize FC link with desired topology
691 * @phba: pointer to lpfc hba data structure.
692 * @fc_topology: desired fc topology.
693 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
694 *
695 * This routine will issue the INIT_LINK mailbox command call.
696 * It is available to other drivers through the lpfc_hba data
697 * structure for use as a delayed link up mechanism with the
698 * module parameter lpfc_suppress_link_up.
699 *
700 * Return code
701 * 0 - success
702 * Any other value - error
703 **/
704int
705lpfc_hba_init_link_fc_topology(struct lpfc_hba *phba, uint32_t fc_topology,
706 uint32_t flag)
84d1b006
JS
707{
708 struct lpfc_vport *vport = phba->pport;
709 LPFC_MBOXQ_t *pmb;
710 MAILBOX_t *mb;
711 int rc;
712
713 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
714 if (!pmb) {
715 phba->link_state = LPFC_HBA_ERROR;
716 return -ENOMEM;
717 }
718 mb = &pmb->u.mb;
719 pmb->vport = vport;
720
026abb87
JS
721 if ((phba->cfg_link_speed > LPFC_USER_LINK_SPEED_MAX) ||
722 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_1G) &&
723 !(phba->lmt & LMT_1Gb)) ||
724 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_2G) &&
725 !(phba->lmt & LMT_2Gb)) ||
726 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_4G) &&
727 !(phba->lmt & LMT_4Gb)) ||
728 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_8G) &&
729 !(phba->lmt & LMT_8Gb)) ||
730 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_10G) &&
731 !(phba->lmt & LMT_10Gb)) ||
732 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_16G) &&
d38dd52c
JS
733 !(phba->lmt & LMT_16Gb)) ||
734 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_32G) &&
fbd8a6ba
JS
735 !(phba->lmt & LMT_32Gb)) ||
736 ((phba->cfg_link_speed == LPFC_USER_LINK_SPEED_64G) &&
737 !(phba->lmt & LMT_64Gb))) {
026abb87
JS
738 /* Reset link speed to auto */
739 lpfc_printf_log(phba, KERN_ERR, LOG_LINK_EVENT,
740 "1302 Invalid speed for this board:%d "
741 "Reset link speed to auto.\n",
742 phba->cfg_link_speed);
743 phba->cfg_link_speed = LPFC_USER_LINK_SPEED_AUTO;
744 }
1b51197d 745 lpfc_init_link(phba, pmb, fc_topology, phba->cfg_link_speed);
84d1b006 746 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
1b51197d
JS
747 if (phba->sli_rev < LPFC_SLI_REV4)
748 lpfc_set_loopback_flag(phba);
6e7288d9 749 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
76a95d75 750 if ((rc != MBX_BUSY) && (rc != MBX_SUCCESS)) {
84d1b006
JS
751 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
752 "0498 Adapter failed to init, mbxCmd x%x "
753 "INIT_LINK, mbxStatus x%x\n",
754 mb->mbxCommand, mb->mbxStatus);
76a95d75
JS
755 if (phba->sli_rev <= LPFC_SLI_REV3) {
756 /* Clear all interrupt enable conditions */
757 writel(0, phba->HCregaddr);
758 readl(phba->HCregaddr); /* flush */
759 /* Clear all pending interrupts */
760 writel(0xffffffff, phba->HAregaddr);
761 readl(phba->HAregaddr); /* flush */
762 }
84d1b006 763 phba->link_state = LPFC_HBA_ERROR;
6e7288d9 764 if (rc != MBX_BUSY || flag == MBX_POLL)
84d1b006
JS
765 mempool_free(pmb, phba->mbox_mem_pool);
766 return -EIO;
767 }
e40a02c1 768 phba->cfg_suppress_link_up = LPFC_INITIALIZE_LINK;
6e7288d9
JS
769 if (flag == MBX_POLL)
770 mempool_free(pmb, phba->mbox_mem_pool);
84d1b006
JS
771
772 return 0;
773}
774
775/**
776 * lpfc_hba_down_link - this routine downs the FC link
6e7288d9
JS
777 * @phba: pointer to lpfc hba data structure.
778 * @flag: mailbox command issue mode - either MBX_POLL or MBX_NOWAIT
84d1b006
JS
779 *
780 * This routine will issue the DOWN_LINK mailbox command call.
781 * It is available to other drivers through the lpfc_hba data
782 * structure for use to stop the link.
783 *
784 * Return code
785 * 0 - success
786 * Any other value - error
787 **/
e399b228 788static int
6e7288d9 789lpfc_hba_down_link(struct lpfc_hba *phba, uint32_t flag)
84d1b006
JS
790{
791 LPFC_MBOXQ_t *pmb;
792 int rc;
793
794 pmb = mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
795 if (!pmb) {
796 phba->link_state = LPFC_HBA_ERROR;
797 return -ENOMEM;
798 }
799
800 lpfc_printf_log(phba,
801 KERN_ERR, LOG_INIT,
802 "0491 Adapter Link is disabled.\n");
803 lpfc_down_link(phba, pmb);
804 pmb->mbox_cmpl = lpfc_sli_def_mbox_cmpl;
6e7288d9 805 rc = lpfc_sli_issue_mbox(phba, pmb, flag);
84d1b006
JS
806 if ((rc != MBX_SUCCESS) && (rc != MBX_BUSY)) {
807 lpfc_printf_log(phba,
808 KERN_ERR, LOG_INIT,
809 "2522 Adapter failed to issue DOWN_LINK"
810 " mbox command rc 0x%x\n", rc);
811
812 mempool_free(pmb, phba->mbox_mem_pool);
813 return -EIO;
814 }
6e7288d9
JS
815 if (flag == MBX_POLL)
816 mempool_free(pmb, phba->mbox_mem_pool);
817
84d1b006
JS
818 return 0;
819}
820
e59058c4 821/**
3621a710 822 * lpfc_hba_down_prep - Perform lpfc uninitialization prior to HBA reset
e59058c4
JS
823 * @phba: pointer to lpfc HBA data structure.
824 *
825 * This routine will do LPFC uninitialization before the HBA is reset when
826 * bringing down the SLI Layer.
827 *
828 * Return codes
829 * 0 - success.
830 * Any other value - error.
831 **/
dea3101e 832int
2e0fef85 833lpfc_hba_down_prep(struct lpfc_hba *phba)
dea3101e 834{
1b32f6aa
JS
835 struct lpfc_vport **vports;
836 int i;
3772a991
JS
837
838 if (phba->sli_rev <= LPFC_SLI_REV3) {
839 /* Disable interrupts */
840 writel(0, phba->HCregaddr);
841 readl(phba->HCregaddr); /* flush */
842 }
dea3101e 843
1b32f6aa
JS
844 if (phba->pport->load_flag & FC_UNLOADING)
845 lpfc_cleanup_discovery_resources(phba->pport);
846 else {
847 vports = lpfc_create_vport_work_array(phba);
848 if (vports != NULL)
3772a991
JS
849 for (i = 0; i <= phba->max_vports &&
850 vports[i] != NULL; i++)
1b32f6aa
JS
851 lpfc_cleanup_discovery_resources(vports[i]);
852 lpfc_destroy_vport_work_array(phba, vports);
7f5f3d0d
JS
853 }
854 return 0;
dea3101e 855}
856
68e814f5
JS
857/**
858 * lpfc_sli4_free_sp_events - Cleanup sp_queue_events to free
859 * rspiocb which got deferred
860 *
861 * @phba: pointer to lpfc HBA data structure.
862 *
863 * This routine will cleanup completed slow path events after HBA is reset
864 * when bringing down the SLI Layer.
865 *
866 *
867 * Return codes
868 * void.
869 **/
870static void
871lpfc_sli4_free_sp_events(struct lpfc_hba *phba)
872{
873 struct lpfc_iocbq *rspiocbq;
874 struct hbq_dmabuf *dmabuf;
875 struct lpfc_cq_event *cq_event;
876
877 spin_lock_irq(&phba->hbalock);
878 phba->hba_flag &= ~HBA_SP_QUEUE_EVT;
879 spin_unlock_irq(&phba->hbalock);
880
881 while (!list_empty(&phba->sli4_hba.sp_queue_event)) {
882 /* Get the response iocb from the head of work queue */
883 spin_lock_irq(&phba->hbalock);
884 list_remove_head(&phba->sli4_hba.sp_queue_event,
885 cq_event, struct lpfc_cq_event, list);
886 spin_unlock_irq(&phba->hbalock);
887
888 switch (bf_get(lpfc_wcqe_c_code, &cq_event->cqe.wcqe_cmpl)) {
889 case CQE_CODE_COMPL_WQE:
890 rspiocbq = container_of(cq_event, struct lpfc_iocbq,
891 cq_event);
892 lpfc_sli_release_iocbq(phba, rspiocbq);
893 break;
894 case CQE_CODE_RECEIVE:
895 case CQE_CODE_RECEIVE_V1:
896 dmabuf = container_of(cq_event, struct hbq_dmabuf,
897 cq_event);
898 lpfc_in_buf_free(phba, &dmabuf->dbuf);
899 }
900 }
901}
902
e59058c4 903/**
bcece5f5 904 * lpfc_hba_free_post_buf - Perform lpfc uninitialization after HBA reset
e59058c4
JS
905 * @phba: pointer to lpfc HBA data structure.
906 *
bcece5f5
JS
907 * This routine will cleanup posted ELS buffers after the HBA is reset
908 * when bringing down the SLI Layer.
909 *
e59058c4
JS
910 *
911 * Return codes
bcece5f5 912 * void.
e59058c4 913 **/
bcece5f5
JS
914static void
915lpfc_hba_free_post_buf(struct lpfc_hba *phba)
41415862
JW
916{
917 struct lpfc_sli *psli = &phba->sli;
918 struct lpfc_sli_ring *pring;
919 struct lpfc_dmabuf *mp, *next_mp;
07eab624
JS
920 LIST_HEAD(buflist);
921 int count;
41415862 922
92d7f7b0
JS
923 if (phba->sli3_options & LPFC_SLI3_HBQ_ENABLED)
924 lpfc_sli_hbqbuf_free_all(phba);
925 else {
926 /* Cleanup preposted buffers on the ELS ring */
895427bd 927 pring = &psli->sli3_ring[LPFC_ELS_RING];
07eab624
JS
928 spin_lock_irq(&phba->hbalock);
929 list_splice_init(&pring->postbufq, &buflist);
930 spin_unlock_irq(&phba->hbalock);
931
932 count = 0;
933 list_for_each_entry_safe(mp, next_mp, &buflist, list) {
92d7f7b0 934 list_del(&mp->list);
07eab624 935 count++;
92d7f7b0
JS
936 lpfc_mbuf_free(phba, mp->virt, mp->phys);
937 kfree(mp);
938 }
07eab624
JS
939
940 spin_lock_irq(&phba->hbalock);
941 pring->postbufq_cnt -= count;
bcece5f5 942 spin_unlock_irq(&phba->hbalock);
41415862 943 }
bcece5f5
JS
944}
945
946/**
947 * lpfc_hba_clean_txcmplq - Perform lpfc uninitialization after HBA reset
948 * @phba: pointer to lpfc HBA data structure.
949 *
950 * This routine will cleanup the txcmplq after the HBA is reset when bringing
951 * down the SLI Layer.
952 *
953 * Return codes
954 * void
955 **/
956static void
957lpfc_hba_clean_txcmplq(struct lpfc_hba *phba)
958{
959 struct lpfc_sli *psli = &phba->sli;
895427bd 960 struct lpfc_queue *qp = NULL;
bcece5f5
JS
961 struct lpfc_sli_ring *pring;
962 LIST_HEAD(completions);
963 int i;
c1dd9111 964 struct lpfc_iocbq *piocb, *next_iocb;
bcece5f5 965
895427bd
JS
966 if (phba->sli_rev != LPFC_SLI_REV4) {
967 for (i = 0; i < psli->num_rings; i++) {
968 pring = &psli->sli3_ring[i];
bcece5f5 969 spin_lock_irq(&phba->hbalock);
895427bd
JS
970 /* At this point in time the HBA is either reset or DOA
971 * Nothing should be on txcmplq as it will
972 * NEVER complete.
973 */
974 list_splice_init(&pring->txcmplq, &completions);
975 pring->txcmplq_cnt = 0;
bcece5f5 976 spin_unlock_irq(&phba->hbalock);
09372820 977
895427bd
JS
978 lpfc_sli_abort_iocb_ring(phba, pring);
979 }
a257bf90 980 /* Cancel all the IOCBs from the completions list */
895427bd
JS
981 lpfc_sli_cancel_iocbs(phba, &completions,
982 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
983 return;
984 }
985 list_for_each_entry(qp, &phba->sli4_hba.lpfc_wq_list, wq_list) {
986 pring = qp->pring;
987 if (!pring)
988 continue;
989 spin_lock_irq(&pring->ring_lock);
c1dd9111
JS
990 list_for_each_entry_safe(piocb, next_iocb,
991 &pring->txcmplq, list)
992 piocb->iocb_flag &= ~LPFC_IO_ON_TXCMPLQ;
895427bd
JS
993 list_splice_init(&pring->txcmplq, &completions);
994 pring->txcmplq_cnt = 0;
995 spin_unlock_irq(&pring->ring_lock);
41415862
JW
996 lpfc_sli_abort_iocb_ring(phba, pring);
997 }
895427bd
JS
998 /* Cancel all the IOCBs from the completions list */
999 lpfc_sli_cancel_iocbs(phba, &completions,
1000 IOSTAT_LOCAL_REJECT, IOERR_SLI_ABORTED);
bcece5f5 1001}
41415862 1002
bcece5f5
JS
1003/**
1004 * lpfc_hba_down_post_s3 - Perform lpfc uninitialization after HBA reset
1005 int i;
1006 * @phba: pointer to lpfc HBA data structure.
1007 *
1008 * This routine will do uninitialization after the HBA is reset when bring
1009 * down the SLI Layer.
1010 *
1011 * Return codes
1012 * 0 - success.
1013 * Any other value - error.
1014 **/
1015static int
1016lpfc_hba_down_post_s3(struct lpfc_hba *phba)
1017{
1018 lpfc_hba_free_post_buf(phba);
1019 lpfc_hba_clean_txcmplq(phba);
41415862
JW
1020 return 0;
1021}
5af5eee7 1022
da0436e9
JS
1023/**
1024 * lpfc_hba_down_post_s4 - Perform lpfc uninitialization after HBA reset
1025 * @phba: pointer to lpfc HBA data structure.
1026 *
1027 * This routine will do uninitialization after the HBA is reset when bring
1028 * down the SLI Layer.
1029 *
1030 * Return codes
af901ca1 1031 * 0 - success.
da0436e9
JS
1032 * Any other value - error.
1033 **/
1034static int
1035lpfc_hba_down_post_s4(struct lpfc_hba *phba)
1036{
c490850a 1037 struct lpfc_io_buf *psb, *psb_next;
86c67379 1038 struct lpfc_nvmet_rcv_ctx *ctxp, *ctxp_next;
5e5b511d 1039 struct lpfc_sli4_hdw_queue *qp;
da0436e9 1040 LIST_HEAD(aborts);
895427bd 1041 LIST_HEAD(nvme_aborts);
86c67379 1042 LIST_HEAD(nvmet_aborts);
0f65ff68 1043 struct lpfc_sglq *sglq_entry = NULL;
5e5b511d 1044 int cnt, idx;
0f65ff68 1045
895427bd
JS
1046
1047 lpfc_sli_hbqbuf_free_all(phba);
bcece5f5
JS
1048 lpfc_hba_clean_txcmplq(phba);
1049
da0436e9
JS
1050 /* At this point in time the HBA is either reset or DOA. Either
1051 * way, nothing should be on lpfc_abts_els_sgl_list, it needs to be
895427bd 1052 * on the lpfc_els_sgl_list so that it can either be freed if the
da0436e9
JS
1053 * driver is unloading or reposted if the driver is restarting
1054 * the port.
1055 */
895427bd 1056 spin_lock_irq(&phba->hbalock); /* required for lpfc_els_sgl_list and */
da0436e9 1057 /* scsl_buf_list */
895427bd 1058 /* sgl_list_lock required because worker thread uses this
da0436e9
JS
1059 * list.
1060 */
895427bd 1061 spin_lock(&phba->sli4_hba.sgl_list_lock);
0f65ff68
JS
1062 list_for_each_entry(sglq_entry,
1063 &phba->sli4_hba.lpfc_abts_els_sgl_list, list)
1064 sglq_entry->state = SGL_FREED;
1065
da0436e9 1066 list_splice_init(&phba->sli4_hba.lpfc_abts_els_sgl_list,
895427bd
JS
1067 &phba->sli4_hba.lpfc_els_sgl_list);
1068
f358dd0c 1069
895427bd 1070 spin_unlock(&phba->sli4_hba.sgl_list_lock);
5e5b511d
JS
1071
1072 /* abts_xxxx_buf_list_lock required because worker thread uses this
da0436e9
JS
1073 * list.
1074 */
5e5b511d
JS
1075 cnt = 0;
1076 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
1077 qp = &phba->sli4_hba.hdwq[idx];
da0436e9 1078
c00f62e6
JS
1079 spin_lock(&qp->abts_io_buf_list_lock);
1080 list_splice_init(&qp->lpfc_abts_io_buf_list,
5e5b511d 1081 &aborts);
68e814f5 1082
0794d601 1083 list_for_each_entry_safe(psb, psb_next, &aborts, list) {
86c67379
JS
1084 psb->pCmd = NULL;
1085 psb->status = IOSTAT_SUCCESS;
cf1a1d3e 1086 cnt++;
86c67379 1087 }
5e5b511d
JS
1088 spin_lock(&qp->io_buf_list_put_lock);
1089 list_splice_init(&aborts, &qp->lpfc_io_buf_list_put);
1090 qp->put_io_bufs += qp->abts_scsi_io_bufs;
c00f62e6 1091 qp->put_io_bufs += qp->abts_nvme_io_bufs;
5e5b511d 1092 qp->abts_scsi_io_bufs = 0;
c00f62e6 1093 qp->abts_nvme_io_bufs = 0;
5e5b511d 1094 spin_unlock(&qp->io_buf_list_put_lock);
c00f62e6 1095 spin_unlock(&qp->abts_io_buf_list_lock);
5e5b511d 1096 }
731eedcb 1097 spin_unlock_irq(&phba->hbalock);
86c67379 1098
5e5b511d 1099 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
731eedcb 1100 spin_lock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
5e5b511d
JS
1101 list_splice_init(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list,
1102 &nvmet_aborts);
731eedcb 1103 spin_unlock_irq(&phba->sli4_hba.abts_nvmet_buf_list_lock);
86c67379
JS
1104 list_for_each_entry_safe(ctxp, ctxp_next, &nvmet_aborts, list) {
1105 ctxp->flag &= ~(LPFC_NVMET_XBUSY | LPFC_NVMET_ABORT_OP);
6c621a22 1106 lpfc_nvmet_ctxbuf_post(phba, ctxp->ctxbuf);
86c67379 1107 }
895427bd 1108 }
895427bd 1109
68e814f5 1110 lpfc_sli4_free_sp_events(phba);
5e5b511d 1111 return cnt;
da0436e9
JS
1112}
1113
1114/**
1115 * lpfc_hba_down_post - Wrapper func for hba down post routine
1116 * @phba: pointer to lpfc HBA data structure.
1117 *
1118 * This routine wraps the actual SLI3 or SLI4 routine for performing
1119 * uninitialization after the HBA is reset when bring down the SLI Layer.
1120 *
1121 * Return codes
af901ca1 1122 * 0 - success.
da0436e9
JS
1123 * Any other value - error.
1124 **/
1125int
1126lpfc_hba_down_post(struct lpfc_hba *phba)
1127{
1128 return (*phba->lpfc_hba_down_post)(phba);
1129}
41415862 1130
e59058c4 1131/**
3621a710 1132 * lpfc_hb_timeout - The HBA-timer timeout handler
e59058c4
JS
1133 * @ptr: unsigned long holds the pointer to lpfc hba data structure.
1134 *
1135 * This is the HBA-timer timeout handler registered to the lpfc driver. When
1136 * this timer fires, a HBA timeout event shall be posted to the lpfc driver
1137 * work-port-events bitmap and the worker thread is notified. This timeout
1138 * event will be used by the worker thread to invoke the actual timeout
1139 * handler routine, lpfc_hb_timeout_handler. Any periodical operations will
1140 * be performed in the timeout handler and the HBA timeout event bit shall
1141 * be cleared by the worker thread after it has taken the event bitmap out.
1142 **/
a6ababd2 1143static void
f22eb4d3 1144lpfc_hb_timeout(struct timer_list *t)
858c9f6c
JS
1145{
1146 struct lpfc_hba *phba;
5e9d9b82 1147 uint32_t tmo_posted;
858c9f6c
JS
1148 unsigned long iflag;
1149
f22eb4d3 1150 phba = from_timer(phba, t, hb_tmofunc);
9399627f
JS
1151
1152 /* Check for heart beat timeout conditions */
858c9f6c 1153 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
5e9d9b82
JS
1154 tmo_posted = phba->pport->work_port_events & WORKER_HB_TMO;
1155 if (!tmo_posted)
858c9f6c
JS
1156 phba->pport->work_port_events |= WORKER_HB_TMO;
1157 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
1158
9399627f 1159 /* Tell the worker thread there is work to do */
5e9d9b82
JS
1160 if (!tmo_posted)
1161 lpfc_worker_wake_up(phba);
858c9f6c
JS
1162 return;
1163}
1164
19ca7609
JS
1165/**
1166 * lpfc_rrq_timeout - The RRQ-timer timeout handler
1167 * @ptr: unsigned long holds the pointer to lpfc hba data structure.
1168 *
1169 * This is the RRQ-timer timeout handler registered to the lpfc driver. When
1170 * this timer fires, a RRQ timeout event shall be posted to the lpfc driver
1171 * work-port-events bitmap and the worker thread is notified. This timeout
1172 * event will be used by the worker thread to invoke the actual timeout
1173 * handler routine, lpfc_rrq_handler. Any periodical operations will
1174 * be performed in the timeout handler and the RRQ timeout event bit shall
1175 * be cleared by the worker thread after it has taken the event bitmap out.
1176 **/
1177static void
f22eb4d3 1178lpfc_rrq_timeout(struct timer_list *t)
19ca7609
JS
1179{
1180 struct lpfc_hba *phba;
19ca7609
JS
1181 unsigned long iflag;
1182
f22eb4d3 1183 phba = from_timer(phba, t, rrq_tmr);
19ca7609 1184 spin_lock_irqsave(&phba->pport->work_port_lock, iflag);
06918ac5
JS
1185 if (!(phba->pport->load_flag & FC_UNLOADING))
1186 phba->hba_flag |= HBA_RRQ_ACTIVE;
1187 else
1188 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
19ca7609 1189 spin_unlock_irqrestore(&phba->pport->work_port_lock, iflag);
06918ac5
JS
1190
1191 if (!(phba->pport->load_flag & FC_UNLOADING))
1192 lpfc_worker_wake_up(phba);
19ca7609
JS
1193}
1194
e59058c4 1195/**
3621a710 1196 * lpfc_hb_mbox_cmpl - The lpfc heart-beat mailbox command callback function
e59058c4
JS
1197 * @phba: pointer to lpfc hba data structure.
1198 * @pmboxq: pointer to the driver internal queue element for mailbox command.
1199 *
1200 * This is the callback function to the lpfc heart-beat mailbox command.
1201 * If configured, the lpfc driver issues the heart-beat mailbox command to
1202 * the HBA every LPFC_HB_MBOX_INTERVAL (current 5) seconds. At the time the
1203 * heart-beat mailbox command is issued, the driver shall set up heart-beat
1204 * timeout timer to LPFC_HB_MBOX_TIMEOUT (current 30) seconds and marks
1205 * heart-beat outstanding state. Once the mailbox command comes back and
1206 * no error conditions detected, the heart-beat mailbox command timer is
1207 * reset to LPFC_HB_MBOX_INTERVAL seconds and the heart-beat outstanding
1208 * state is cleared for the next heart-beat. If the timer expired with the
1209 * heart-beat outstanding state set, the driver will put the HBA offline.
1210 **/
858c9f6c
JS
1211static void
1212lpfc_hb_mbox_cmpl(struct lpfc_hba * phba, LPFC_MBOXQ_t * pmboxq)
1213{
1214 unsigned long drvr_flag;
1215
1216 spin_lock_irqsave(&phba->hbalock, drvr_flag);
1217 phba->hb_outstanding = 0;
1218 spin_unlock_irqrestore(&phba->hbalock, drvr_flag);
1219
9399627f 1220 /* Check and reset heart-beat timer is necessary */
858c9f6c
JS
1221 mempool_free(pmboxq, phba->mbox_mem_pool);
1222 if (!(phba->pport->fc_flag & FC_OFFLINE_MODE) &&
1223 !(phba->link_state == LPFC_HBA_ERROR) &&
51ef4c26 1224 !(phba->pport->load_flag & FC_UNLOADING))
858c9f6c 1225 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1226 jiffies +
1227 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1228 return;
1229}
1230
32517fc0
JS
1231static void
1232lpfc_hb_eq_delay_work(struct work_struct *work)
1233{
1234 struct lpfc_hba *phba = container_of(to_delayed_work(work),
1235 struct lpfc_hba, eq_delay_work);
1236 struct lpfc_eq_intr_info *eqi, *eqi_new;
1237 struct lpfc_queue *eq, *eq_next;
1238 unsigned char *eqcnt = NULL;
1239 uint32_t usdelay;
1240 int i;
8d34a59c 1241 bool update = false;
32517fc0
JS
1242
1243 if (!phba->cfg_auto_imax || phba->pport->load_flag & FC_UNLOADING)
1244 return;
1245
1246 if (phba->link_state == LPFC_HBA_ERROR ||
1247 phba->pport->fc_flag & FC_OFFLINE_MODE)
1248 goto requeue;
1249
1250 eqcnt = kcalloc(num_possible_cpus(), sizeof(unsigned char),
1251 GFP_KERNEL);
1252 if (!eqcnt)
1253 goto requeue;
1254
8d34a59c
JS
1255 if (phba->cfg_irq_chann > 1) {
1256 /* Loop thru all IRQ vectors */
1257 for (i = 0; i < phba->cfg_irq_chann; i++) {
1258 /* Get the EQ corresponding to the IRQ vector */
1259 eq = phba->sli4_hba.hba_eq_hdl[i].eq;
1260 if (!eq)
1261 continue;
1262 if (eq->q_mode) {
1263 update = true;
1264 break;
1265 }
1266 if (eqcnt[eq->last_cpu] < 2)
1267 eqcnt[eq->last_cpu]++;
1268 }
1269 } else
1270 update = true;
32517fc0
JS
1271
1272 for_each_present_cpu(i) {
32517fc0 1273 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, i);
8d34a59c
JS
1274 if (!update && eqcnt[i] < 2) {
1275 eqi->icnt = 0;
1276 continue;
1277 }
32517fc0
JS
1278
1279 usdelay = (eqi->icnt / LPFC_IMAX_THRESHOLD) *
1280 LPFC_EQ_DELAY_STEP;
1281 if (usdelay > LPFC_MAX_AUTO_EQ_DELAY)
1282 usdelay = LPFC_MAX_AUTO_EQ_DELAY;
1283
1284 eqi->icnt = 0;
1285
1286 list_for_each_entry_safe(eq, eq_next, &eqi->list, cpu_list) {
1287 if (eq->last_cpu != i) {
1288 eqi_new = per_cpu_ptr(phba->sli4_hba.eq_info,
1289 eq->last_cpu);
1290 list_move_tail(&eq->cpu_list, &eqi_new->list);
1291 continue;
1292 }
1293 if (usdelay != eq->q_mode)
1294 lpfc_modify_hba_eq_delay(phba, eq->hdwq, 1,
1295 usdelay);
1296 }
1297 }
1298
1299 kfree(eqcnt);
1300
1301requeue:
1302 queue_delayed_work(phba->wq, &phba->eq_delay_work,
1303 msecs_to_jiffies(LPFC_EQ_DELAY_MSECS));
1304}
1305
c490850a
JS
1306/**
1307 * lpfc_hb_mxp_handler - Multi-XRI pools handler to adjust XRI distribution
1308 * @phba: pointer to lpfc hba data structure.
1309 *
1310 * For each heartbeat, this routine does some heuristic methods to adjust
1311 * XRI distribution. The goal is to fully utilize free XRIs.
1312 **/
1313static void lpfc_hb_mxp_handler(struct lpfc_hba *phba)
1314{
1315 u32 i;
1316 u32 hwq_count;
1317
1318 hwq_count = phba->cfg_hdw_queue;
1319 for (i = 0; i < hwq_count; i++) {
1320 /* Adjust XRIs in private pool */
1321 lpfc_adjust_pvt_pool_count(phba, i);
1322
1323 /* Adjust high watermark */
1324 lpfc_adjust_high_watermark(phba, i);
1325
1326#ifdef LPFC_MXP_STAT
1327 /* Snapshot pbl, pvt and busy count */
1328 lpfc_snapshot_mxp(phba, i);
1329#endif
1330 }
1331}
1332
e59058c4 1333/**
3621a710 1334 * lpfc_hb_timeout_handler - The HBA-timer timeout handler
e59058c4
JS
1335 * @phba: pointer to lpfc hba data structure.
1336 *
1337 * This is the actual HBA-timer timeout handler to be invoked by the worker
1338 * thread whenever the HBA timer fired and HBA-timeout event posted. This
1339 * handler performs any periodic operations needed for the device. If such
1340 * periodic event has already been attended to either in the interrupt handler
1341 * or by processing slow-ring or fast-ring events within the HBA-timer
1342 * timeout window (LPFC_HB_MBOX_INTERVAL), this handler just simply resets
1343 * the timer for the next timeout period. If lpfc heart-beat mailbox command
1344 * is configured and there is no heart-beat mailbox command outstanding, a
1345 * heart-beat mailbox is issued and timer set properly. Otherwise, if there
1346 * has been a heart-beat mailbox command outstanding, the HBA shall be put
1347 * to offline.
1348 **/
858c9f6c
JS
1349void
1350lpfc_hb_timeout_handler(struct lpfc_hba *phba)
1351{
45ed1190 1352 struct lpfc_vport **vports;
858c9f6c 1353 LPFC_MBOXQ_t *pmboxq;
0ff10d46 1354 struct lpfc_dmabuf *buf_ptr;
45ed1190 1355 int retval, i;
858c9f6c 1356 struct lpfc_sli *psli = &phba->sli;
0ff10d46 1357 LIST_HEAD(completions);
858c9f6c 1358
c490850a
JS
1359 if (phba->cfg_xri_rebalancing) {
1360 /* Multi-XRI pools handler */
1361 lpfc_hb_mxp_handler(phba);
1362 }
858c9f6c 1363
45ed1190
JS
1364 vports = lpfc_create_vport_work_array(phba);
1365 if (vports != NULL)
4258e98e 1366 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
45ed1190 1367 lpfc_rcv_seq_check_edtov(vports[i]);
4258e98e
JS
1368 lpfc_fdmi_num_disc_check(vports[i]);
1369 }
45ed1190
JS
1370 lpfc_destroy_vport_work_array(phba, vports);
1371
858c9f6c 1372 if ((phba->link_state == LPFC_HBA_ERROR) ||
51ef4c26 1373 (phba->pport->load_flag & FC_UNLOADING) ||
858c9f6c
JS
1374 (phba->pport->fc_flag & FC_OFFLINE_MODE))
1375 return;
1376
1377 spin_lock_irq(&phba->pport->work_port_lock);
858c9f6c 1378
256ec0d0
JS
1379 if (time_after(phba->last_completion_time +
1380 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL),
1381 jiffies)) {
858c9f6c
JS
1382 spin_unlock_irq(&phba->pport->work_port_lock);
1383 if (!phba->hb_outstanding)
1384 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1385 jiffies +
1386 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1387 else
1388 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1389 jiffies +
1390 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c
JS
1391 return;
1392 }
1393 spin_unlock_irq(&phba->pport->work_port_lock);
1394
0ff10d46
JS
1395 if (phba->elsbuf_cnt &&
1396 (phba->elsbuf_cnt == phba->elsbuf_prev_cnt)) {
1397 spin_lock_irq(&phba->hbalock);
1398 list_splice_init(&phba->elsbuf, &completions);
1399 phba->elsbuf_cnt = 0;
1400 phba->elsbuf_prev_cnt = 0;
1401 spin_unlock_irq(&phba->hbalock);
1402
1403 while (!list_empty(&completions)) {
1404 list_remove_head(&completions, buf_ptr,
1405 struct lpfc_dmabuf, list);
1406 lpfc_mbuf_free(phba, buf_ptr->virt, buf_ptr->phys);
1407 kfree(buf_ptr);
1408 }
1409 }
1410 phba->elsbuf_prev_cnt = phba->elsbuf_cnt;
1411
858c9f6c 1412 /* If there is no heart beat outstanding, issue a heartbeat command */
13815c83
JS
1413 if (phba->cfg_enable_hba_heartbeat) {
1414 if (!phba->hb_outstanding) {
bc73905a
JS
1415 if ((!(psli->sli_flag & LPFC_SLI_MBOX_ACTIVE)) &&
1416 (list_empty(&psli->mboxq))) {
1417 pmboxq = mempool_alloc(phba->mbox_mem_pool,
1418 GFP_KERNEL);
1419 if (!pmboxq) {
1420 mod_timer(&phba->hb_tmofunc,
1421 jiffies +
256ec0d0
JS
1422 msecs_to_jiffies(1000 *
1423 LPFC_HB_MBOX_INTERVAL));
bc73905a
JS
1424 return;
1425 }
1426
1427 lpfc_heart_beat(phba, pmboxq);
1428 pmboxq->mbox_cmpl = lpfc_hb_mbox_cmpl;
1429 pmboxq->vport = phba->pport;
1430 retval = lpfc_sli_issue_mbox(phba, pmboxq,
1431 MBX_NOWAIT);
1432
1433 if (retval != MBX_BUSY &&
1434 retval != MBX_SUCCESS) {
1435 mempool_free(pmboxq,
1436 phba->mbox_mem_pool);
1437 mod_timer(&phba->hb_tmofunc,
1438 jiffies +
256ec0d0
JS
1439 msecs_to_jiffies(1000 *
1440 LPFC_HB_MBOX_INTERVAL));
bc73905a
JS
1441 return;
1442 }
1443 phba->skipped_hb = 0;
1444 phba->hb_outstanding = 1;
1445 } else if (time_before_eq(phba->last_completion_time,
1446 phba->skipped_hb)) {
1447 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
1448 "2857 Last completion time not "
1449 " updated in %d ms\n",
1450 jiffies_to_msecs(jiffies
1451 - phba->last_completion_time));
1452 } else
1453 phba->skipped_hb = jiffies;
1454
858c9f6c 1455 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1456 jiffies +
1457 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c 1458 return;
13815c83
JS
1459 } else {
1460 /*
1461 * If heart beat timeout called with hb_outstanding set
dcf2a4e0
JS
1462 * we need to give the hb mailbox cmd a chance to
1463 * complete or TMO.
13815c83 1464 */
dcf2a4e0
JS
1465 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1466 "0459 Adapter heartbeat still out"
1467 "standing:last compl time was %d ms.\n",
1468 jiffies_to_msecs(jiffies
1469 - phba->last_completion_time));
1470 mod_timer(&phba->hb_tmofunc,
256ec0d0
JS
1471 jiffies +
1472 msecs_to_jiffies(1000 * LPFC_HB_MBOX_TIMEOUT));
858c9f6c 1473 }
4258e98e
JS
1474 } else {
1475 mod_timer(&phba->hb_tmofunc,
1476 jiffies +
1477 msecs_to_jiffies(1000 * LPFC_HB_MBOX_INTERVAL));
858c9f6c
JS
1478 }
1479}
1480
e59058c4 1481/**
3621a710 1482 * lpfc_offline_eratt - Bring lpfc offline on hardware error attention
e59058c4
JS
1483 * @phba: pointer to lpfc hba data structure.
1484 *
1485 * This routine is called to bring the HBA offline when HBA hardware error
1486 * other than Port Error 6 has been detected.
1487 **/
09372820
JS
1488static void
1489lpfc_offline_eratt(struct lpfc_hba *phba)
1490{
1491 struct lpfc_sli *psli = &phba->sli;
1492
1493 spin_lock_irq(&phba->hbalock);
f4b4c68f 1494 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
09372820 1495 spin_unlock_irq(&phba->hbalock);
618a5230 1496 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
09372820
JS
1497
1498 lpfc_offline(phba);
1499 lpfc_reset_barrier(phba);
f4b4c68f 1500 spin_lock_irq(&phba->hbalock);
09372820 1501 lpfc_sli_brdreset(phba);
f4b4c68f 1502 spin_unlock_irq(&phba->hbalock);
09372820
JS
1503 lpfc_hba_down_post(phba);
1504 lpfc_sli_brdready(phba, HS_MBRDY);
1505 lpfc_unblock_mgmt_io(phba);
1506 phba->link_state = LPFC_HBA_ERROR;
1507 return;
1508}
1509
da0436e9
JS
1510/**
1511 * lpfc_sli4_offline_eratt - Bring lpfc offline on SLI4 hardware error attention
1512 * @phba: pointer to lpfc hba data structure.
1513 *
1514 * This routine is called to bring a SLI4 HBA offline when HBA hardware error
1515 * other than Port Error 6 has been detected.
1516 **/
a88dbb6a 1517void
da0436e9
JS
1518lpfc_sli4_offline_eratt(struct lpfc_hba *phba)
1519{
946727dc
JS
1520 spin_lock_irq(&phba->hbalock);
1521 phba->link_state = LPFC_HBA_ERROR;
1522 spin_unlock_irq(&phba->hbalock);
1523
618a5230 1524 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
c00f62e6 1525 lpfc_sli_flush_io_rings(phba);
da0436e9 1526 lpfc_offline(phba);
da0436e9 1527 lpfc_hba_down_post(phba);
da0436e9 1528 lpfc_unblock_mgmt_io(phba);
da0436e9
JS
1529}
1530
a257bf90
JS
1531/**
1532 * lpfc_handle_deferred_eratt - The HBA hardware deferred error handler
1533 * @phba: pointer to lpfc hba data structure.
1534 *
1535 * This routine is invoked to handle the deferred HBA hardware error
1536 * conditions. This type of error is indicated by HBA by setting ER1
1537 * and another ER bit in the host status register. The driver will
1538 * wait until the ER1 bit clears before handling the error condition.
1539 **/
1540static void
1541lpfc_handle_deferred_eratt(struct lpfc_hba *phba)
1542{
1543 uint32_t old_host_status = phba->work_hs;
a257bf90
JS
1544 struct lpfc_sli *psli = &phba->sli;
1545
f4b4c68f
JS
1546 /* If the pci channel is offline, ignore possible errors,
1547 * since we cannot communicate with the pci card anyway.
1548 */
1549 if (pci_channel_offline(phba->pcidev)) {
1550 spin_lock_irq(&phba->hbalock);
1551 phba->hba_flag &= ~DEFER_ERATT;
1552 spin_unlock_irq(&phba->hbalock);
1553 return;
1554 }
1555
a257bf90
JS
1556 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1557 "0479 Deferred Adapter Hardware Error "
1558 "Data: x%x x%x x%x\n",
1559 phba->work_hs,
1560 phba->work_status[0], phba->work_status[1]);
1561
1562 spin_lock_irq(&phba->hbalock);
f4b4c68f 1563 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
a257bf90
JS
1564 spin_unlock_irq(&phba->hbalock);
1565
1566
1567 /*
1568 * Firmware stops when it triggred erratt. That could cause the I/Os
1569 * dropped by the firmware. Error iocb (I/O) on txcmplq and let the
1570 * SCSI layer retry it after re-establishing link.
1571 */
db55fba8 1572 lpfc_sli_abort_fcp_rings(phba);
a257bf90
JS
1573
1574 /*
1575 * There was a firmware error. Take the hba offline and then
1576 * attempt to restart it.
1577 */
618a5230 1578 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
a257bf90
JS
1579 lpfc_offline(phba);
1580
1581 /* Wait for the ER1 bit to clear.*/
1582 while (phba->work_hs & HS_FFER1) {
1583 msleep(100);
9940b97b
JS
1584 if (lpfc_readl(phba->HSregaddr, &phba->work_hs)) {
1585 phba->work_hs = UNPLUG_ERR ;
1586 break;
1587 }
a257bf90
JS
1588 /* If driver is unloading let the worker thread continue */
1589 if (phba->pport->load_flag & FC_UNLOADING) {
1590 phba->work_hs = 0;
1591 break;
1592 }
1593 }
1594
1595 /*
1596 * This is to ptrotect against a race condition in which
1597 * first write to the host attention register clear the
1598 * host status register.
1599 */
1600 if ((!phba->work_hs) && (!(phba->pport->load_flag & FC_UNLOADING)))
1601 phba->work_hs = old_host_status & ~HS_FFER1;
1602
3772a991 1603 spin_lock_irq(&phba->hbalock);
a257bf90 1604 phba->hba_flag &= ~DEFER_ERATT;
3772a991 1605 spin_unlock_irq(&phba->hbalock);
a257bf90
JS
1606 phba->work_status[0] = readl(phba->MBslimaddr + 0xa8);
1607 phba->work_status[1] = readl(phba->MBslimaddr + 0xac);
1608}
1609
3772a991
JS
1610static void
1611lpfc_board_errevt_to_mgmt(struct lpfc_hba *phba)
1612{
1613 struct lpfc_board_event_header board_event;
1614 struct Scsi_Host *shost;
1615
1616 board_event.event_type = FC_REG_BOARD_EVENT;
1617 board_event.subcategory = LPFC_EVENT_PORTINTERR;
1618 shost = lpfc_shost_from_vport(phba->pport);
1619 fc_host_post_vendor_event(shost, fc_get_event_number(),
1620 sizeof(board_event),
1621 (char *) &board_event,
1622 LPFC_NL_VENDOR_ID);
1623}
1624
e59058c4 1625/**
3772a991 1626 * lpfc_handle_eratt_s3 - The SLI3 HBA hardware error handler
e59058c4
JS
1627 * @phba: pointer to lpfc hba data structure.
1628 *
1629 * This routine is invoked to handle the following HBA hardware error
1630 * conditions:
1631 * 1 - HBA error attention interrupt
1632 * 2 - DMA ring index out of range
1633 * 3 - Mailbox command came back as unknown
1634 **/
3772a991
JS
1635static void
1636lpfc_handle_eratt_s3(struct lpfc_hba *phba)
dea3101e 1637{
2e0fef85 1638 struct lpfc_vport *vport = phba->pport;
2e0fef85 1639 struct lpfc_sli *psli = &phba->sli;
d2873e4c 1640 uint32_t event_data;
57127f15
JS
1641 unsigned long temperature;
1642 struct temp_event temp_event_data;
92d7f7b0 1643 struct Scsi_Host *shost;
2e0fef85 1644
8d63f375 1645 /* If the pci channel is offline, ignore possible errors,
3772a991
JS
1646 * since we cannot communicate with the pci card anyway.
1647 */
1648 if (pci_channel_offline(phba->pcidev)) {
1649 spin_lock_irq(&phba->hbalock);
1650 phba->hba_flag &= ~DEFER_ERATT;
1651 spin_unlock_irq(&phba->hbalock);
8d63f375 1652 return;
3772a991
JS
1653 }
1654
13815c83
JS
1655 /* If resets are disabled then leave the HBA alone and return */
1656 if (!phba->cfg_enable_hba_reset)
1657 return;
dea3101e 1658
ea2151b4 1659 /* Send an internal error event to mgmt application */
3772a991 1660 lpfc_board_errevt_to_mgmt(phba);
ea2151b4 1661
a257bf90
JS
1662 if (phba->hba_flag & DEFER_ERATT)
1663 lpfc_handle_deferred_eratt(phba);
1664
dcf2a4e0
JS
1665 if ((phba->work_hs & HS_FFER6) || (phba->work_hs & HS_FFER8)) {
1666 if (phba->work_hs & HS_FFER6)
1667 /* Re-establishing Link */
1668 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1669 "1301 Re-establishing Link "
1670 "Data: x%x x%x x%x\n",
1671 phba->work_hs, phba->work_status[0],
1672 phba->work_status[1]);
1673 if (phba->work_hs & HS_FFER8)
1674 /* Device Zeroization */
1675 lpfc_printf_log(phba, KERN_INFO, LOG_LINK_EVENT,
1676 "2861 Host Authentication device "
1677 "zeroization Data:x%x x%x x%x\n",
1678 phba->work_hs, phba->work_status[0],
1679 phba->work_status[1]);
58da1ffb 1680
92d7f7b0 1681 spin_lock_irq(&phba->hbalock);
f4b4c68f 1682 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
92d7f7b0 1683 spin_unlock_irq(&phba->hbalock);
dea3101e 1684
1685 /*
1686 * Firmware stops when it triggled erratt with HS_FFER6.
1687 * That could cause the I/Os dropped by the firmware.
1688 * Error iocb (I/O) on txcmplq and let the SCSI layer
1689 * retry it after re-establishing link.
1690 */
db55fba8 1691 lpfc_sli_abort_fcp_rings(phba);
dea3101e 1692
dea3101e 1693 /*
1694 * There was a firmware error. Take the hba offline and then
1695 * attempt to restart it.
1696 */
618a5230 1697 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
dea3101e 1698 lpfc_offline(phba);
41415862 1699 lpfc_sli_brdrestart(phba);
dea3101e 1700 if (lpfc_online(phba) == 0) { /* Initialize the HBA */
46fa311e 1701 lpfc_unblock_mgmt_io(phba);
dea3101e 1702 return;
1703 }
46fa311e 1704 lpfc_unblock_mgmt_io(phba);
57127f15
JS
1705 } else if (phba->work_hs & HS_CRIT_TEMP) {
1706 temperature = readl(phba->MBslimaddr + TEMPERATURE_OFFSET);
1707 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1708 temp_event_data.event_code = LPFC_CRIT_TEMP;
1709 temp_event_data.data = (uint32_t)temperature;
1710
1711 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
d7c255b2 1712 "0406 Adapter maximum temperature exceeded "
57127f15
JS
1713 "(%ld), taking this port offline "
1714 "Data: x%x x%x x%x\n",
1715 temperature, phba->work_hs,
1716 phba->work_status[0], phba->work_status[1]);
1717
1718 shost = lpfc_shost_from_vport(phba->pport);
1719 fc_host_post_vendor_event(shost, fc_get_event_number(),
1720 sizeof(temp_event_data),
1721 (char *) &temp_event_data,
1722 SCSI_NL_VID_TYPE_PCI
1723 | PCI_VENDOR_ID_EMULEX);
1724
7af67051 1725 spin_lock_irq(&phba->hbalock);
7af67051
JS
1726 phba->over_temp_state = HBA_OVER_TEMP;
1727 spin_unlock_irq(&phba->hbalock);
09372820 1728 lpfc_offline_eratt(phba);
57127f15 1729
dea3101e 1730 } else {
1731 /* The if clause above forces this code path when the status
9399627f
JS
1732 * failure is a value other than FFER6. Do not call the offline
1733 * twice. This is the adapter hardware error path.
dea3101e 1734 */
1735 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e8b62011 1736 "0457 Adapter Hardware Error "
dea3101e 1737 "Data: x%x x%x x%x\n",
e8b62011 1738 phba->work_hs,
dea3101e 1739 phba->work_status[0], phba->work_status[1]);
1740
d2873e4c 1741 event_data = FC_REG_DUMP_EVENT;
92d7f7b0 1742 shost = lpfc_shost_from_vport(vport);
2e0fef85 1743 fc_host_post_vendor_event(shost, fc_get_event_number(),
d2873e4c
JS
1744 sizeof(event_data), (char *) &event_data,
1745 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
1746
09372820 1747 lpfc_offline_eratt(phba);
dea3101e 1748 }
9399627f 1749 return;
dea3101e 1750}
1751
618a5230
JS
1752/**
1753 * lpfc_sli4_port_sta_fn_reset - The SLI4 function reset due to port status reg
1754 * @phba: pointer to lpfc hba data structure.
1755 * @mbx_action: flag for mailbox shutdown action.
1756 *
1757 * This routine is invoked to perform an SLI4 port PCI function reset in
1758 * response to port status register polling attention. It waits for port
1759 * status register (ERR, RDY, RN) bits before proceeding with function reset.
1760 * During this process, interrupt vectors are freed and later requested
1761 * for handling possible port resource change.
1762 **/
1763static int
e10b2022
JS
1764lpfc_sli4_port_sta_fn_reset(struct lpfc_hba *phba, int mbx_action,
1765 bool en_rn_msg)
618a5230
JS
1766{
1767 int rc;
1768 uint32_t intr_mode;
1769
27d6ac0a 1770 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
65791f1f
JS
1771 LPFC_SLI_INTF_IF_TYPE_2) {
1772 /*
1773 * On error status condition, driver need to wait for port
1774 * ready before performing reset.
1775 */
1776 rc = lpfc_sli4_pdev_status_reg_wait(phba);
0e916ee7 1777 if (rc)
65791f1f
JS
1778 return rc;
1779 }
0e916ee7 1780
65791f1f
JS
1781 /* need reset: attempt for port recovery */
1782 if (en_rn_msg)
1783 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1784 "2887 Reset Needed: Attempting Port "
1785 "Recovery...\n");
1786 lpfc_offline_prep(phba, mbx_action);
c00f62e6 1787 lpfc_sli_flush_io_rings(phba);
65791f1f
JS
1788 lpfc_offline(phba);
1789 /* release interrupt for possible resource change */
1790 lpfc_sli4_disable_intr(phba);
5a9eeff5
JS
1791 rc = lpfc_sli_brdrestart(phba);
1792 if (rc) {
1793 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1794 "6309 Failed to restart board\n");
1795 return rc;
1796 }
65791f1f
JS
1797 /* request and enable interrupt */
1798 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
1799 if (intr_mode == LPFC_INTR_ERROR) {
1800 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1801 "3175 Failed to enable interrupt\n");
1802 return -EIO;
618a5230 1803 }
65791f1f
JS
1804 phba->intr_mode = intr_mode;
1805 rc = lpfc_online(phba);
1806 if (rc == 0)
1807 lpfc_unblock_mgmt_io(phba);
1808
618a5230
JS
1809 return rc;
1810}
1811
da0436e9
JS
1812/**
1813 * lpfc_handle_eratt_s4 - The SLI4 HBA hardware error handler
1814 * @phba: pointer to lpfc hba data structure.
1815 *
1816 * This routine is invoked to handle the SLI4 HBA hardware error attention
1817 * conditions.
1818 **/
1819static void
1820lpfc_handle_eratt_s4(struct lpfc_hba *phba)
1821{
1822 struct lpfc_vport *vport = phba->pport;
1823 uint32_t event_data;
1824 struct Scsi_Host *shost;
2fcee4bf 1825 uint32_t if_type;
2e90f4b5
JS
1826 struct lpfc_register portstat_reg = {0};
1827 uint32_t reg_err1, reg_err2;
1828 uint32_t uerrlo_reg, uemasklo_reg;
65791f1f 1829 uint32_t smphr_port_status = 0, pci_rd_rc1, pci_rd_rc2;
e10b2022 1830 bool en_rn_msg = true;
946727dc 1831 struct temp_event temp_event_data;
65791f1f
JS
1832 struct lpfc_register portsmphr_reg;
1833 int rc, i;
da0436e9
JS
1834
1835 /* If the pci channel is offline, ignore possible errors, since
1836 * we cannot communicate with the pci card anyway.
1837 */
32a93100
JS
1838 if (pci_channel_offline(phba->pcidev)) {
1839 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1840 "3166 pci channel is offline\n");
1841 lpfc_sli4_offline_eratt(phba);
da0436e9 1842 return;
32a93100 1843 }
da0436e9 1844
65791f1f 1845 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
2fcee4bf
JS
1846 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
1847 switch (if_type) {
1848 case LPFC_SLI_INTF_IF_TYPE_0:
2e90f4b5
JS
1849 pci_rd_rc1 = lpfc_readl(
1850 phba->sli4_hba.u.if_type0.UERRLOregaddr,
1851 &uerrlo_reg);
1852 pci_rd_rc2 = lpfc_readl(
1853 phba->sli4_hba.u.if_type0.UEMASKLOregaddr,
1854 &uemasklo_reg);
1855 /* consider PCI bus read error as pci_channel_offline */
1856 if (pci_rd_rc1 == -EIO && pci_rd_rc2 == -EIO)
1857 return;
65791f1f
JS
1858 if (!(phba->hba_flag & HBA_RECOVERABLE_UE)) {
1859 lpfc_sli4_offline_eratt(phba);
1860 return;
1861 }
1862 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1863 "7623 Checking UE recoverable");
1864
1865 for (i = 0; i < phba->sli4_hba.ue_to_sr / 1000; i++) {
1866 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1867 &portsmphr_reg.word0))
1868 continue;
1869
1870 smphr_port_status = bf_get(lpfc_port_smphr_port_status,
1871 &portsmphr_reg);
1872 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1873 LPFC_PORT_SEM_UE_RECOVERABLE)
1874 break;
1875 /*Sleep for 1Sec, before checking SEMAPHORE */
1876 msleep(1000);
1877 }
1878
1879 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1880 "4827 smphr_port_status x%x : Waited %dSec",
1881 smphr_port_status, i);
1882
1883 /* Recoverable UE, reset the HBA device */
1884 if ((smphr_port_status & LPFC_PORT_SEM_MASK) ==
1885 LPFC_PORT_SEM_UE_RECOVERABLE) {
1886 for (i = 0; i < 20; i++) {
1887 msleep(1000);
1888 if (!lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
1889 &portsmphr_reg.word0) &&
1890 (LPFC_POST_STAGE_PORT_READY ==
1891 bf_get(lpfc_port_smphr_port_status,
1892 &portsmphr_reg))) {
1893 rc = lpfc_sli4_port_sta_fn_reset(phba,
1894 LPFC_MBX_NO_WAIT, en_rn_msg);
1895 if (rc == 0)
1896 return;
1897 lpfc_printf_log(phba,
1898 KERN_ERR, LOG_INIT,
1899 "4215 Failed to recover UE");
1900 break;
1901 }
1902 }
1903 }
1904 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1905 "7624 Firmware not ready: Failing UE recovery,"
1906 " waited %dSec", i);
8c24a4f6 1907 phba->link_state = LPFC_HBA_ERROR;
2fcee4bf 1908 break;
946727dc 1909
2fcee4bf 1910 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 1911 case LPFC_SLI_INTF_IF_TYPE_6:
2e90f4b5
JS
1912 pci_rd_rc1 = lpfc_readl(
1913 phba->sli4_hba.u.if_type2.STATUSregaddr,
1914 &portstat_reg.word0);
1915 /* consider PCI bus read error as pci_channel_offline */
6b5151fd
JS
1916 if (pci_rd_rc1 == -EIO) {
1917 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1918 "3151 PCI bus read access failure: x%x\n",
1919 readl(phba->sli4_hba.u.if_type2.STATUSregaddr));
32a93100 1920 lpfc_sli4_offline_eratt(phba);
2e90f4b5 1921 return;
6b5151fd 1922 }
2e90f4b5
JS
1923 reg_err1 = readl(phba->sli4_hba.u.if_type2.ERR1regaddr);
1924 reg_err2 = readl(phba->sli4_hba.u.if_type2.ERR2regaddr);
2fcee4bf 1925 if (bf_get(lpfc_sliport_status_oti, &portstat_reg)) {
2fcee4bf
JS
1926 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1927 "2889 Port Overtemperature event, "
946727dc
JS
1928 "taking port offline Data: x%x x%x\n",
1929 reg_err1, reg_err2);
1930
310429ef 1931 phba->sfp_alarm |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
946727dc
JS
1932 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
1933 temp_event_data.event_code = LPFC_CRIT_TEMP;
1934 temp_event_data.data = 0xFFFFFFFF;
1935
1936 shost = lpfc_shost_from_vport(phba->pport);
1937 fc_host_post_vendor_event(shost, fc_get_event_number(),
1938 sizeof(temp_event_data),
1939 (char *)&temp_event_data,
1940 SCSI_NL_VID_TYPE_PCI
1941 | PCI_VENDOR_ID_EMULEX);
1942
2fcee4bf
JS
1943 spin_lock_irq(&phba->hbalock);
1944 phba->over_temp_state = HBA_OVER_TEMP;
1945 spin_unlock_irq(&phba->hbalock);
1946 lpfc_sli4_offline_eratt(phba);
946727dc 1947 return;
2fcee4bf 1948 }
2e90f4b5 1949 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
e10b2022 1950 reg_err2 == SLIPORT_ERR2_REG_FW_RESTART) {
2e90f4b5 1951 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e10b2022
JS
1952 "3143 Port Down: Firmware Update "
1953 "Detected\n");
1954 en_rn_msg = false;
1955 } else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
2e90f4b5
JS
1956 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
1957 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1958 "3144 Port Down: Debug Dump\n");
1959 else if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1960 reg_err2 == SLIPORT_ERR2_REG_FUNC_PROVISON)
1961 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
1962 "3145 Port Down: Provisioning\n");
618a5230 1963
946727dc
JS
1964 /* If resets are disabled then leave the HBA alone and return */
1965 if (!phba->cfg_enable_hba_reset)
1966 return;
1967
618a5230 1968 /* Check port status register for function reset */
e10b2022
JS
1969 rc = lpfc_sli4_port_sta_fn_reset(phba, LPFC_MBX_NO_WAIT,
1970 en_rn_msg);
618a5230
JS
1971 if (rc == 0) {
1972 /* don't report event on forced debug dump */
1973 if (reg_err1 == SLIPORT_ERR1_REG_ERR_CODE_2 &&
1974 reg_err2 == SLIPORT_ERR2_REG_FORCED_DUMP)
1975 return;
1976 else
1977 break;
2fcee4bf 1978 }
618a5230 1979 /* fall through for not able to recover */
6b5151fd 1980 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8c24a4f6
JS
1981 "3152 Unrecoverable error\n");
1982 phba->link_state = LPFC_HBA_ERROR;
2fcee4bf
JS
1983 break;
1984 case LPFC_SLI_INTF_IF_TYPE_1:
1985 default:
1986 break;
1987 }
2e90f4b5
JS
1988 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
1989 "3123 Report dump event to upper layer\n");
1990 /* Send an internal error event to mgmt application */
1991 lpfc_board_errevt_to_mgmt(phba);
1992
1993 event_data = FC_REG_DUMP_EVENT;
1994 shost = lpfc_shost_from_vport(vport);
1995 fc_host_post_vendor_event(shost, fc_get_event_number(),
1996 sizeof(event_data), (char *) &event_data,
1997 SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_EMULEX);
da0436e9
JS
1998}
1999
2000/**
2001 * lpfc_handle_eratt - Wrapper func for handling hba error attention
2002 * @phba: pointer to lpfc HBA data structure.
2003 *
2004 * This routine wraps the actual SLI3 or SLI4 hba error attention handling
2005 * routine from the API jump table function pointer from the lpfc_hba struct.
2006 *
2007 * Return codes
af901ca1 2008 * 0 - success.
da0436e9
JS
2009 * Any other value - error.
2010 **/
2011void
2012lpfc_handle_eratt(struct lpfc_hba *phba)
2013{
2014 (*phba->lpfc_handle_eratt)(phba);
2015}
2016
e59058c4 2017/**
3621a710 2018 * lpfc_handle_latt - The HBA link event handler
e59058c4
JS
2019 * @phba: pointer to lpfc hba data structure.
2020 *
2021 * This routine is invoked from the worker thread to handle a HBA host
895427bd 2022 * attention link event. SLI3 only.
e59058c4 2023 **/
dea3101e 2024void
2e0fef85 2025lpfc_handle_latt(struct lpfc_hba *phba)
dea3101e 2026{
2e0fef85
JS
2027 struct lpfc_vport *vport = phba->pport;
2028 struct lpfc_sli *psli = &phba->sli;
dea3101e 2029 LPFC_MBOXQ_t *pmb;
2030 volatile uint32_t control;
2031 struct lpfc_dmabuf *mp;
09372820 2032 int rc = 0;
dea3101e 2033
2034 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
09372820
JS
2035 if (!pmb) {
2036 rc = 1;
dea3101e 2037 goto lpfc_handle_latt_err_exit;
09372820 2038 }
dea3101e 2039
2040 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
09372820
JS
2041 if (!mp) {
2042 rc = 2;
dea3101e 2043 goto lpfc_handle_latt_free_pmb;
09372820 2044 }
dea3101e 2045
2046 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
09372820
JS
2047 if (!mp->virt) {
2048 rc = 3;
dea3101e 2049 goto lpfc_handle_latt_free_mp;
09372820 2050 }
dea3101e 2051
6281bfe0 2052 /* Cleanup any outstanding ELS commands */
549e55cd 2053 lpfc_els_flush_all_cmd(phba);
dea3101e 2054
2055 psli->slistat.link_event++;
76a95d75
JS
2056 lpfc_read_topology(phba, pmb, mp);
2057 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
2e0fef85 2058 pmb->vport = vport;
0d2b6b83 2059 /* Block ELS IOCBs until we have processed this mbox command */
895427bd 2060 phba->sli.sli3_ring[LPFC_ELS_RING].flag |= LPFC_STOP_IOCB_EVENT;
0b727fea 2061 rc = lpfc_sli_issue_mbox (phba, pmb, MBX_NOWAIT);
09372820
JS
2062 if (rc == MBX_NOT_FINISHED) {
2063 rc = 4;
14691150 2064 goto lpfc_handle_latt_free_mbuf;
09372820 2065 }
dea3101e 2066
2067 /* Clear Link Attention in HA REG */
2e0fef85 2068 spin_lock_irq(&phba->hbalock);
dea3101e 2069 writel(HA_LATT, phba->HAregaddr);
2070 readl(phba->HAregaddr); /* flush */
2e0fef85 2071 spin_unlock_irq(&phba->hbalock);
dea3101e 2072
2073 return;
2074
14691150 2075lpfc_handle_latt_free_mbuf:
895427bd 2076 phba->sli.sli3_ring[LPFC_ELS_RING].flag &= ~LPFC_STOP_IOCB_EVENT;
14691150 2077 lpfc_mbuf_free(phba, mp->virt, mp->phys);
dea3101e 2078lpfc_handle_latt_free_mp:
2079 kfree(mp);
2080lpfc_handle_latt_free_pmb:
1dcb58e5 2081 mempool_free(pmb, phba->mbox_mem_pool);
dea3101e 2082lpfc_handle_latt_err_exit:
2083 /* Enable Link attention interrupts */
2e0fef85 2084 spin_lock_irq(&phba->hbalock);
dea3101e 2085 psli->sli_flag |= LPFC_PROCESS_LA;
2086 control = readl(phba->HCregaddr);
2087 control |= HC_LAINT_ENA;
2088 writel(control, phba->HCregaddr);
2089 readl(phba->HCregaddr); /* flush */
2090
2091 /* Clear Link Attention in HA REG */
2092 writel(HA_LATT, phba->HAregaddr);
2093 readl(phba->HAregaddr); /* flush */
2e0fef85 2094 spin_unlock_irq(&phba->hbalock);
dea3101e 2095 lpfc_linkdown(phba);
2e0fef85 2096 phba->link_state = LPFC_HBA_ERROR;
dea3101e 2097
09372820
JS
2098 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX,
2099 "0300 LATT: Cannot issue READ_LA: Data:%d\n", rc);
dea3101e 2100
2101 return;
2102}
2103
e59058c4 2104/**
3621a710 2105 * lpfc_parse_vpd - Parse VPD (Vital Product Data)
e59058c4
JS
2106 * @phba: pointer to lpfc hba data structure.
2107 * @vpd: pointer to the vital product data.
2108 * @len: length of the vital product data in bytes.
2109 *
2110 * This routine parses the Vital Product Data (VPD). The VPD is treated as
2111 * an array of characters. In this routine, the ModelName, ProgramType, and
2112 * ModelDesc, etc. fields of the phba data structure will be populated.
2113 *
2114 * Return codes
2115 * 0 - pointer to the VPD passed in is NULL
2116 * 1 - success
2117 **/
3772a991 2118int
2e0fef85 2119lpfc_parse_vpd(struct lpfc_hba *phba, uint8_t *vpd, int len)
dea3101e 2120{
2121 uint8_t lenlo, lenhi;
07da60c1 2122 int Length;
dea3101e 2123 int i, j;
2124 int finished = 0;
2125 int index = 0;
2126
2127 if (!vpd)
2128 return 0;
2129
2130 /* Vital Product */
ed957684 2131 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011 2132 "0455 Vital Product Data: x%x x%x x%x x%x\n",
dea3101e 2133 (uint32_t) vpd[0], (uint32_t) vpd[1], (uint32_t) vpd[2],
2134 (uint32_t) vpd[3]);
74b72a59 2135 while (!finished && (index < (len - 4))) {
dea3101e 2136 switch (vpd[index]) {
2137 case 0x82:
74b72a59 2138 case 0x91:
dea3101e 2139 index += 1;
2140 lenlo = vpd[index];
2141 index += 1;
2142 lenhi = vpd[index];
2143 index += 1;
2144 i = ((((unsigned short)lenhi) << 8) + lenlo);
2145 index += i;
2146 break;
2147 case 0x90:
2148 index += 1;
2149 lenlo = vpd[index];
2150 index += 1;
2151 lenhi = vpd[index];
2152 index += 1;
2153 Length = ((((unsigned short)lenhi) << 8) + lenlo);
74b72a59
JW
2154 if (Length > len - index)
2155 Length = len - index;
dea3101e 2156 while (Length > 0) {
2157 /* Look for Serial Number */
2158 if ((vpd[index] == 'S') && (vpd[index+1] == 'N')) {
2159 index += 2;
2160 i = vpd[index];
2161 index += 1;
2162 j = 0;
2163 Length -= (3+i);
2164 while(i--) {
2165 phba->SerialNumber[j++] = vpd[index++];
2166 if (j == 31)
2167 break;
2168 }
2169 phba->SerialNumber[j] = 0;
2170 continue;
2171 }
2172 else if ((vpd[index] == 'V') && (vpd[index+1] == '1')) {
2173 phba->vpd_flag |= VPD_MODEL_DESC;
2174 index += 2;
2175 i = vpd[index];
2176 index += 1;
2177 j = 0;
2178 Length -= (3+i);
2179 while(i--) {
2180 phba->ModelDesc[j++] = vpd[index++];
2181 if (j == 255)
2182 break;
2183 }
2184 phba->ModelDesc[j] = 0;
2185 continue;
2186 }
2187 else if ((vpd[index] == 'V') && (vpd[index+1] == '2')) {
2188 phba->vpd_flag |= VPD_MODEL_NAME;
2189 index += 2;
2190 i = vpd[index];
2191 index += 1;
2192 j = 0;
2193 Length -= (3+i);
2194 while(i--) {
2195 phba->ModelName[j++] = vpd[index++];
2196 if (j == 79)
2197 break;
2198 }
2199 phba->ModelName[j] = 0;
2200 continue;
2201 }
2202 else if ((vpd[index] == 'V') && (vpd[index+1] == '3')) {
2203 phba->vpd_flag |= VPD_PROGRAM_TYPE;
2204 index += 2;
2205 i = vpd[index];
2206 index += 1;
2207 j = 0;
2208 Length -= (3+i);
2209 while(i--) {
2210 phba->ProgramType[j++] = vpd[index++];
2211 if (j == 255)
2212 break;
2213 }
2214 phba->ProgramType[j] = 0;
2215 continue;
2216 }
2217 else if ((vpd[index] == 'V') && (vpd[index+1] == '4')) {
2218 phba->vpd_flag |= VPD_PORT;
2219 index += 2;
2220 i = vpd[index];
2221 index += 1;
2222 j = 0;
2223 Length -= (3+i);
2224 while(i--) {
cd1c8301
JS
2225 if ((phba->sli_rev == LPFC_SLI_REV4) &&
2226 (phba->sli4_hba.pport_name_sta ==
2227 LPFC_SLI4_PPNAME_GET)) {
2228 j++;
2229 index++;
2230 } else
2231 phba->Port[j++] = vpd[index++];
2232 if (j == 19)
2233 break;
dea3101e 2234 }
cd1c8301
JS
2235 if ((phba->sli_rev != LPFC_SLI_REV4) ||
2236 (phba->sli4_hba.pport_name_sta ==
2237 LPFC_SLI4_PPNAME_NON))
2238 phba->Port[j] = 0;
dea3101e 2239 continue;
2240 }
2241 else {
2242 index += 2;
2243 i = vpd[index];
2244 index += 1;
2245 index += i;
2246 Length -= (3 + i);
2247 }
2248 }
2249 finished = 0;
2250 break;
2251 case 0x78:
2252 finished = 1;
2253 break;
2254 default:
2255 index ++;
2256 break;
2257 }
74b72a59 2258 }
dea3101e 2259
2260 return(1);
2261}
2262
e59058c4 2263/**
3621a710 2264 * lpfc_get_hba_model_desc - Retrieve HBA device model name and description
e59058c4
JS
2265 * @phba: pointer to lpfc hba data structure.
2266 * @mdp: pointer to the data structure to hold the derived model name.
2267 * @descp: pointer to the data structure to hold the derived description.
2268 *
2269 * This routine retrieves HBA's description based on its registered PCI device
2270 * ID. The @descp passed into this function points to an array of 256 chars. It
2271 * shall be returned with the model name, maximum speed, and the host bus type.
2272 * The @mdp passed into this function points to an array of 80 chars. When the
2273 * function returns, the @mdp will be filled with the model name.
2274 **/
dea3101e 2275static void
2e0fef85 2276lpfc_get_hba_model_desc(struct lpfc_hba *phba, uint8_t *mdp, uint8_t *descp)
dea3101e 2277{
2278 lpfc_vpd_t *vp;
fefcb2b6 2279 uint16_t dev_id = phba->pcidev->device;
74b72a59 2280 int max_speed;
84774a4d 2281 int GE = 0;
da0436e9 2282 int oneConnect = 0; /* default is not a oneConnect */
74b72a59 2283 struct {
a747c9ce
JS
2284 char *name;
2285 char *bus;
2286 char *function;
2287 } m = {"<Unknown>", "", ""};
74b72a59
JW
2288
2289 if (mdp && mdp[0] != '\0'
2290 && descp && descp[0] != '\0')
2291 return;
2292
fbd8a6ba
JS
2293 if (phba->lmt & LMT_64Gb)
2294 max_speed = 64;
2295 else if (phba->lmt & LMT_32Gb)
d38dd52c
JS
2296 max_speed = 32;
2297 else if (phba->lmt & LMT_16Gb)
c0c11512
JS
2298 max_speed = 16;
2299 else if (phba->lmt & LMT_10Gb)
74b72a59
JW
2300 max_speed = 10;
2301 else if (phba->lmt & LMT_8Gb)
2302 max_speed = 8;
2303 else if (phba->lmt & LMT_4Gb)
2304 max_speed = 4;
2305 else if (phba->lmt & LMT_2Gb)
2306 max_speed = 2;
4169d868 2307 else if (phba->lmt & LMT_1Gb)
74b72a59 2308 max_speed = 1;
4169d868
JS
2309 else
2310 max_speed = 0;
dea3101e 2311
2312 vp = &phba->vpd;
dea3101e 2313
e4adb204 2314 switch (dev_id) {
06325e74 2315 case PCI_DEVICE_ID_FIREFLY:
12222f4f
JS
2316 m = (typeof(m)){"LP6000", "PCI",
2317 "Obsolete, Unsupported Fibre Channel Adapter"};
06325e74 2318 break;
dea3101e 2319 case PCI_DEVICE_ID_SUPERFLY:
2320 if (vp->rev.biuRev >= 1 && vp->rev.biuRev <= 3)
12222f4f 2321 m = (typeof(m)){"LP7000", "PCI", ""};
dea3101e 2322 else
12222f4f
JS
2323 m = (typeof(m)){"LP7000E", "PCI", ""};
2324 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
dea3101e 2325 break;
2326 case PCI_DEVICE_ID_DRAGONFLY:
a747c9ce 2327 m = (typeof(m)){"LP8000", "PCI",
12222f4f 2328 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2329 break;
2330 case PCI_DEVICE_ID_CENTAUR:
2331 if (FC_JEDEC_ID(vp->rev.biuRev) == CENTAUR_2G_JEDEC_ID)
12222f4f 2332 m = (typeof(m)){"LP9002", "PCI", ""};
dea3101e 2333 else
12222f4f
JS
2334 m = (typeof(m)){"LP9000", "PCI", ""};
2335 m.function = "Obsolete, Unsupported Fibre Channel Adapter";
dea3101e 2336 break;
2337 case PCI_DEVICE_ID_RFLY:
a747c9ce 2338 m = (typeof(m)){"LP952", "PCI",
12222f4f 2339 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2340 break;
2341 case PCI_DEVICE_ID_PEGASUS:
a747c9ce 2342 m = (typeof(m)){"LP9802", "PCI-X",
12222f4f 2343 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2344 break;
2345 case PCI_DEVICE_ID_THOR:
a747c9ce 2346 m = (typeof(m)){"LP10000", "PCI-X",
12222f4f 2347 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2348 break;
2349 case PCI_DEVICE_ID_VIPER:
a747c9ce 2350 m = (typeof(m)){"LPX1000", "PCI-X",
12222f4f 2351 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2352 break;
2353 case PCI_DEVICE_ID_PFLY:
a747c9ce 2354 m = (typeof(m)){"LP982", "PCI-X",
12222f4f 2355 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2356 break;
2357 case PCI_DEVICE_ID_TFLY:
a747c9ce 2358 m = (typeof(m)){"LP1050", "PCI-X",
12222f4f 2359 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2360 break;
2361 case PCI_DEVICE_ID_HELIOS:
a747c9ce 2362 m = (typeof(m)){"LP11000", "PCI-X2",
12222f4f 2363 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2364 break;
e4adb204 2365 case PCI_DEVICE_ID_HELIOS_SCSP:
a747c9ce 2366 m = (typeof(m)){"LP11000-SP", "PCI-X2",
12222f4f 2367 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2368 break;
2369 case PCI_DEVICE_ID_HELIOS_DCSP:
a747c9ce 2370 m = (typeof(m)){"LP11002-SP", "PCI-X2",
12222f4f 2371 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2372 break;
2373 case PCI_DEVICE_ID_NEPTUNE:
12222f4f
JS
2374 m = (typeof(m)){"LPe1000", "PCIe",
2375 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2376 break;
2377 case PCI_DEVICE_ID_NEPTUNE_SCSP:
12222f4f
JS
2378 m = (typeof(m)){"LPe1000-SP", "PCIe",
2379 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204
JSEC
2380 break;
2381 case PCI_DEVICE_ID_NEPTUNE_DCSP:
12222f4f
JS
2382 m = (typeof(m)){"LPe1002-SP", "PCIe",
2383 "Obsolete, Unsupported Fibre Channel Adapter"};
e4adb204 2384 break;
dea3101e 2385 case PCI_DEVICE_ID_BMID:
a747c9ce 2386 m = (typeof(m)){"LP1150", "PCI-X2", "Fibre Channel Adapter"};
dea3101e 2387 break;
2388 case PCI_DEVICE_ID_BSMB:
12222f4f
JS
2389 m = (typeof(m)){"LP111", "PCI-X2",
2390 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2391 break;
2392 case PCI_DEVICE_ID_ZEPHYR:
a747c9ce 2393 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
dea3101e 2394 break;
e4adb204 2395 case PCI_DEVICE_ID_ZEPHYR_SCSP:
a747c9ce 2396 m = (typeof(m)){"LPe11000", "PCIe", "Fibre Channel Adapter"};
e4adb204
JSEC
2397 break;
2398 case PCI_DEVICE_ID_ZEPHYR_DCSP:
a747c9ce 2399 m = (typeof(m)){"LP2105", "PCIe", "FCoE Adapter"};
a257bf90 2400 GE = 1;
e4adb204 2401 break;
dea3101e 2402 case PCI_DEVICE_ID_ZMID:
a747c9ce 2403 m = (typeof(m)){"LPe1150", "PCIe", "Fibre Channel Adapter"};
dea3101e 2404 break;
2405 case PCI_DEVICE_ID_ZSMB:
a747c9ce 2406 m = (typeof(m)){"LPe111", "PCIe", "Fibre Channel Adapter"};
dea3101e 2407 break;
2408 case PCI_DEVICE_ID_LP101:
12222f4f
JS
2409 m = (typeof(m)){"LP101", "PCI-X",
2410 "Obsolete, Unsupported Fibre Channel Adapter"};
dea3101e 2411 break;
2412 case PCI_DEVICE_ID_LP10000S:
12222f4f
JS
2413 m = (typeof(m)){"LP10000-S", "PCI",
2414 "Obsolete, Unsupported Fibre Channel Adapter"};
06325e74 2415 break;
e4adb204 2416 case PCI_DEVICE_ID_LP11000S:
12222f4f
JS
2417 m = (typeof(m)){"LP11000-S", "PCI-X2",
2418 "Obsolete, Unsupported Fibre Channel Adapter"};
18a3b596 2419 break;
e4adb204 2420 case PCI_DEVICE_ID_LPE11000S:
12222f4f
JS
2421 m = (typeof(m)){"LPe11000-S", "PCIe",
2422 "Obsolete, Unsupported Fibre Channel Adapter"};
5cc36b3c 2423 break;
b87eab38 2424 case PCI_DEVICE_ID_SAT:
a747c9ce 2425 m = (typeof(m)){"LPe12000", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2426 break;
2427 case PCI_DEVICE_ID_SAT_MID:
a747c9ce 2428 m = (typeof(m)){"LPe1250", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2429 break;
2430 case PCI_DEVICE_ID_SAT_SMB:
a747c9ce 2431 m = (typeof(m)){"LPe121", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2432 break;
2433 case PCI_DEVICE_ID_SAT_DCSP:
a747c9ce 2434 m = (typeof(m)){"LPe12002-SP", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2435 break;
2436 case PCI_DEVICE_ID_SAT_SCSP:
a747c9ce 2437 m = (typeof(m)){"LPe12000-SP", "PCIe", "Fibre Channel Adapter"};
b87eab38
JS
2438 break;
2439 case PCI_DEVICE_ID_SAT_S:
a747c9ce 2440 m = (typeof(m)){"LPe12000-S", "PCIe", "Fibre Channel Adapter"};
b87eab38 2441 break;
84774a4d 2442 case PCI_DEVICE_ID_HORNET:
12222f4f
JS
2443 m = (typeof(m)){"LP21000", "PCIe",
2444 "Obsolete, Unsupported FCoE Adapter"};
84774a4d
JS
2445 GE = 1;
2446 break;
2447 case PCI_DEVICE_ID_PROTEUS_VF:
a747c9ce 2448 m = (typeof(m)){"LPev12000", "PCIe IOV",
12222f4f 2449 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d
JS
2450 break;
2451 case PCI_DEVICE_ID_PROTEUS_PF:
a747c9ce 2452 m = (typeof(m)){"LPev12000", "PCIe IOV",
12222f4f 2453 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d
JS
2454 break;
2455 case PCI_DEVICE_ID_PROTEUS_S:
a747c9ce 2456 m = (typeof(m)){"LPemv12002-S", "PCIe IOV",
12222f4f 2457 "Obsolete, Unsupported Fibre Channel Adapter"};
84774a4d 2458 break;
da0436e9
JS
2459 case PCI_DEVICE_ID_TIGERSHARK:
2460 oneConnect = 1;
a747c9ce 2461 m = (typeof(m)){"OCe10100", "PCIe", "FCoE"};
da0436e9 2462 break;
a747c9ce 2463 case PCI_DEVICE_ID_TOMCAT:
6669f9bb 2464 oneConnect = 1;
a747c9ce
JS
2465 m = (typeof(m)){"OCe11100", "PCIe", "FCoE"};
2466 break;
2467 case PCI_DEVICE_ID_FALCON:
2468 m = (typeof(m)){"LPSe12002-ML1-E", "PCIe",
2469 "EmulexSecure Fibre"};
6669f9bb 2470 break;
98fc5dd9
JS
2471 case PCI_DEVICE_ID_BALIUS:
2472 m = (typeof(m)){"LPVe12002", "PCIe Shared I/O",
12222f4f 2473 "Obsolete, Unsupported Fibre Channel Adapter"};
98fc5dd9 2474 break;
085c647c 2475 case PCI_DEVICE_ID_LANCER_FC:
c0c11512 2476 m = (typeof(m)){"LPe16000", "PCIe", "Fibre Channel Adapter"};
085c647c 2477 break;
12222f4f
JS
2478 case PCI_DEVICE_ID_LANCER_FC_VF:
2479 m = (typeof(m)){"LPe16000", "PCIe",
2480 "Obsolete, Unsupported Fibre Channel Adapter"};
2481 break;
085c647c
JS
2482 case PCI_DEVICE_ID_LANCER_FCOE:
2483 oneConnect = 1;
079b5c91 2484 m = (typeof(m)){"OCe15100", "PCIe", "FCoE"};
085c647c 2485 break;
12222f4f
JS
2486 case PCI_DEVICE_ID_LANCER_FCOE_VF:
2487 oneConnect = 1;
2488 m = (typeof(m)){"OCe15100", "PCIe",
2489 "Obsolete, Unsupported FCoE"};
2490 break;
d38dd52c
JS
2491 case PCI_DEVICE_ID_LANCER_G6_FC:
2492 m = (typeof(m)){"LPe32000", "PCIe", "Fibre Channel Adapter"};
2493 break;
c238b9b6
JS
2494 case PCI_DEVICE_ID_LANCER_G7_FC:
2495 m = (typeof(m)){"LPe36000", "PCIe", "Fibre Channel Adapter"};
2496 break;
f8cafd38
JS
2497 case PCI_DEVICE_ID_SKYHAWK:
2498 case PCI_DEVICE_ID_SKYHAWK_VF:
2499 oneConnect = 1;
2500 m = (typeof(m)){"OCe14000", "PCIe", "FCoE"};
2501 break;
5cc36b3c 2502 default:
a747c9ce 2503 m = (typeof(m)){"Unknown", "", ""};
e4adb204 2504 break;
dea3101e 2505 }
74b72a59
JW
2506
2507 if (mdp && mdp[0] == '\0')
2508 snprintf(mdp, 79,"%s", m.name);
c0c11512
JS
2509 /*
2510 * oneConnect hba requires special processing, they are all initiators
da0436e9
JS
2511 * and we put the port number on the end
2512 */
2513 if (descp && descp[0] == '\0') {
2514 if (oneConnect)
2515 snprintf(descp, 255,
4169d868 2516 "Emulex OneConnect %s, %s Initiator %s",
a747c9ce 2517 m.name, m.function,
da0436e9 2518 phba->Port);
4169d868
JS
2519 else if (max_speed == 0)
2520 snprintf(descp, 255,
290237d2 2521 "Emulex %s %s %s",
4169d868 2522 m.name, m.bus, m.function);
da0436e9
JS
2523 else
2524 snprintf(descp, 255,
2525 "Emulex %s %d%s %s %s",
a747c9ce
JS
2526 m.name, max_speed, (GE) ? "GE" : "Gb",
2527 m.bus, m.function);
da0436e9 2528 }
dea3101e 2529}
2530
e59058c4 2531/**
3621a710 2532 * lpfc_post_buffer - Post IOCB(s) with DMA buffer descriptor(s) to a IOCB ring
e59058c4
JS
2533 * @phba: pointer to lpfc hba data structure.
2534 * @pring: pointer to a IOCB ring.
2535 * @cnt: the number of IOCBs to be posted to the IOCB ring.
2536 *
2537 * This routine posts a given number of IOCBs with the associated DMA buffer
2538 * descriptors specified by the cnt argument to the given IOCB ring.
2539 *
2540 * Return codes
2541 * The number of IOCBs NOT able to be posted to the IOCB ring.
2542 **/
dea3101e 2543int
495a714c 2544lpfc_post_buffer(struct lpfc_hba *phba, struct lpfc_sli_ring *pring, int cnt)
dea3101e 2545{
2546 IOCB_t *icmd;
0bd4ca25 2547 struct lpfc_iocbq *iocb;
dea3101e 2548 struct lpfc_dmabuf *mp1, *mp2;
2549
2550 cnt += pring->missbufcnt;
2551
2552 /* While there are buffers to post */
2553 while (cnt > 0) {
2554 /* Allocate buffer for command iocb */
0bd4ca25 2555 iocb = lpfc_sli_get_iocbq(phba);
dea3101e 2556 if (iocb == NULL) {
2557 pring->missbufcnt = cnt;
2558 return cnt;
2559 }
dea3101e 2560 icmd = &iocb->iocb;
2561
2562 /* 2 buffers can be posted per command */
2563 /* Allocate buffer to post */
2564 mp1 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2565 if (mp1)
98c9ea5c
JS
2566 mp1->virt = lpfc_mbuf_alloc(phba, MEM_PRI, &mp1->phys);
2567 if (!mp1 || !mp1->virt) {
c9475cb0 2568 kfree(mp1);
604a3e30 2569 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2570 pring->missbufcnt = cnt;
2571 return cnt;
2572 }
2573
2574 INIT_LIST_HEAD(&mp1->list);
2575 /* Allocate buffer to post */
2576 if (cnt > 1) {
2577 mp2 = kmalloc(sizeof (struct lpfc_dmabuf), GFP_KERNEL);
2578 if (mp2)
2579 mp2->virt = lpfc_mbuf_alloc(phba, MEM_PRI,
2580 &mp2->phys);
98c9ea5c 2581 if (!mp2 || !mp2->virt) {
c9475cb0 2582 kfree(mp2);
dea3101e 2583 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2584 kfree(mp1);
604a3e30 2585 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2586 pring->missbufcnt = cnt;
2587 return cnt;
2588 }
2589
2590 INIT_LIST_HEAD(&mp2->list);
2591 } else {
2592 mp2 = NULL;
2593 }
2594
2595 icmd->un.cont64[0].addrHigh = putPaddrHigh(mp1->phys);
2596 icmd->un.cont64[0].addrLow = putPaddrLow(mp1->phys);
2597 icmd->un.cont64[0].tus.f.bdeSize = FCELSSIZE;
2598 icmd->ulpBdeCount = 1;
2599 cnt--;
2600 if (mp2) {
2601 icmd->un.cont64[1].addrHigh = putPaddrHigh(mp2->phys);
2602 icmd->un.cont64[1].addrLow = putPaddrLow(mp2->phys);
2603 icmd->un.cont64[1].tus.f.bdeSize = FCELSSIZE;
2604 cnt--;
2605 icmd->ulpBdeCount = 2;
2606 }
2607
2608 icmd->ulpCommand = CMD_QUE_RING_BUF64_CN;
2609 icmd->ulpLe = 1;
2610
3772a991
JS
2611 if (lpfc_sli_issue_iocb(phba, pring->ringno, iocb, 0) ==
2612 IOCB_ERROR) {
dea3101e 2613 lpfc_mbuf_free(phba, mp1->virt, mp1->phys);
2614 kfree(mp1);
2615 cnt++;
2616 if (mp2) {
2617 lpfc_mbuf_free(phba, mp2->virt, mp2->phys);
2618 kfree(mp2);
2619 cnt++;
2620 }
604a3e30 2621 lpfc_sli_release_iocbq(phba, iocb);
dea3101e 2622 pring->missbufcnt = cnt;
dea3101e 2623 return cnt;
2624 }
dea3101e 2625 lpfc_sli_ringpostbuf_put(phba, pring, mp1);
92d7f7b0 2626 if (mp2)
dea3101e 2627 lpfc_sli_ringpostbuf_put(phba, pring, mp2);
dea3101e 2628 }
2629 pring->missbufcnt = 0;
2630 return 0;
2631}
2632
e59058c4 2633/**
3621a710 2634 * lpfc_post_rcv_buf - Post the initial receive IOCB buffers to ELS ring
e59058c4
JS
2635 * @phba: pointer to lpfc hba data structure.
2636 *
2637 * This routine posts initial receive IOCB buffers to the ELS ring. The
2638 * current number of initial IOCB buffers specified by LPFC_BUF_RING0 is
895427bd 2639 * set to 64 IOCBs. SLI3 only.
e59058c4
JS
2640 *
2641 * Return codes
2642 * 0 - success (currently always success)
2643 **/
dea3101e 2644static int
2e0fef85 2645lpfc_post_rcv_buf(struct lpfc_hba *phba)
dea3101e 2646{
2647 struct lpfc_sli *psli = &phba->sli;
2648
2649 /* Ring 0, ELS / CT buffers */
895427bd 2650 lpfc_post_buffer(phba, &psli->sli3_ring[LPFC_ELS_RING], LPFC_BUF_RING0);
dea3101e 2651 /* Ring 2 - FCP no buffers needed */
2652
2653 return 0;
2654}
2655
2656#define S(N,V) (((V)<<(N))|((V)>>(32-(N))))
2657
e59058c4 2658/**
3621a710 2659 * lpfc_sha_init - Set up initial array of hash table entries
e59058c4
JS
2660 * @HashResultPointer: pointer to an array as hash table.
2661 *
2662 * This routine sets up the initial values to the array of hash table entries
2663 * for the LC HBAs.
2664 **/
dea3101e 2665static void
2666lpfc_sha_init(uint32_t * HashResultPointer)
2667{
2668 HashResultPointer[0] = 0x67452301;
2669 HashResultPointer[1] = 0xEFCDAB89;
2670 HashResultPointer[2] = 0x98BADCFE;
2671 HashResultPointer[3] = 0x10325476;
2672 HashResultPointer[4] = 0xC3D2E1F0;
2673}
2674
e59058c4 2675/**
3621a710 2676 * lpfc_sha_iterate - Iterate initial hash table with the working hash table
e59058c4
JS
2677 * @HashResultPointer: pointer to an initial/result hash table.
2678 * @HashWorkingPointer: pointer to an working hash table.
2679 *
2680 * This routine iterates an initial hash table pointed by @HashResultPointer
2681 * with the values from the working hash table pointeed by @HashWorkingPointer.
2682 * The results are putting back to the initial hash table, returned through
2683 * the @HashResultPointer as the result hash table.
2684 **/
dea3101e 2685static void
2686lpfc_sha_iterate(uint32_t * HashResultPointer, uint32_t * HashWorkingPointer)
2687{
2688 int t;
2689 uint32_t TEMP;
2690 uint32_t A, B, C, D, E;
2691 t = 16;
2692 do {
2693 HashWorkingPointer[t] =
2694 S(1,
2695 HashWorkingPointer[t - 3] ^ HashWorkingPointer[t -
2696 8] ^
2697 HashWorkingPointer[t - 14] ^ HashWorkingPointer[t - 16]);
2698 } while (++t <= 79);
2699 t = 0;
2700 A = HashResultPointer[0];
2701 B = HashResultPointer[1];
2702 C = HashResultPointer[2];
2703 D = HashResultPointer[3];
2704 E = HashResultPointer[4];
2705
2706 do {
2707 if (t < 20) {
2708 TEMP = ((B & C) | ((~B) & D)) + 0x5A827999;
2709 } else if (t < 40) {
2710 TEMP = (B ^ C ^ D) + 0x6ED9EBA1;
2711 } else if (t < 60) {
2712 TEMP = ((B & C) | (B & D) | (C & D)) + 0x8F1BBCDC;
2713 } else {
2714 TEMP = (B ^ C ^ D) + 0xCA62C1D6;
2715 }
2716 TEMP += S(5, A) + E + HashWorkingPointer[t];
2717 E = D;
2718 D = C;
2719 C = S(30, B);
2720 B = A;
2721 A = TEMP;
2722 } while (++t <= 79);
2723
2724 HashResultPointer[0] += A;
2725 HashResultPointer[1] += B;
2726 HashResultPointer[2] += C;
2727 HashResultPointer[3] += D;
2728 HashResultPointer[4] += E;
2729
2730}
2731
e59058c4 2732/**
3621a710 2733 * lpfc_challenge_key - Create challenge key based on WWPN of the HBA
e59058c4
JS
2734 * @RandomChallenge: pointer to the entry of host challenge random number array.
2735 * @HashWorking: pointer to the entry of the working hash array.
2736 *
2737 * This routine calculates the working hash array referred by @HashWorking
2738 * from the challenge random numbers associated with the host, referred by
2739 * @RandomChallenge. The result is put into the entry of the working hash
2740 * array and returned by reference through @HashWorking.
2741 **/
dea3101e 2742static void
2743lpfc_challenge_key(uint32_t * RandomChallenge, uint32_t * HashWorking)
2744{
2745 *HashWorking = (*RandomChallenge ^ *HashWorking);
2746}
2747
e59058c4 2748/**
3621a710 2749 * lpfc_hba_init - Perform special handling for LC HBA initialization
e59058c4
JS
2750 * @phba: pointer to lpfc hba data structure.
2751 * @hbainit: pointer to an array of unsigned 32-bit integers.
2752 *
2753 * This routine performs the special handling for LC HBA initialization.
2754 **/
dea3101e 2755void
2756lpfc_hba_init(struct lpfc_hba *phba, uint32_t *hbainit)
2757{
2758 int t;
2759 uint32_t *HashWorking;
2e0fef85 2760 uint32_t *pwwnn = (uint32_t *) phba->wwnn;
dea3101e 2761
bbfbbbc1 2762 HashWorking = kcalloc(80, sizeof(uint32_t), GFP_KERNEL);
dea3101e 2763 if (!HashWorking)
2764 return;
2765
dea3101e 2766 HashWorking[0] = HashWorking[78] = *pwwnn++;
2767 HashWorking[1] = HashWorking[79] = *pwwnn;
2768
2769 for (t = 0; t < 7; t++)
2770 lpfc_challenge_key(phba->RandomData + t, HashWorking + t);
2771
2772 lpfc_sha_init(hbainit);
2773 lpfc_sha_iterate(hbainit, HashWorking);
2774 kfree(HashWorking);
2775}
2776
e59058c4 2777/**
3621a710 2778 * lpfc_cleanup - Performs vport cleanups before deleting a vport
e59058c4
JS
2779 * @vport: pointer to a virtual N_Port data structure.
2780 *
2781 * This routine performs the necessary cleanups before deleting the @vport.
2782 * It invokes the discovery state machine to perform necessary state
2783 * transitions and to release the ndlps associated with the @vport. Note,
2784 * the physical port is treated as @vport 0.
2785 **/
87af33fe 2786void
2e0fef85 2787lpfc_cleanup(struct lpfc_vport *vport)
dea3101e 2788{
87af33fe 2789 struct lpfc_hba *phba = vport->phba;
dea3101e 2790 struct lpfc_nodelist *ndlp, *next_ndlp;
a8adb832 2791 int i = 0;
dea3101e 2792
87af33fe
JS
2793 if (phba->link_state > LPFC_LINK_DOWN)
2794 lpfc_port_link_failure(vport);
2795
2796 list_for_each_entry_safe(ndlp, next_ndlp, &vport->fc_nodes, nlp_listp) {
e47c9093
JS
2797 if (!NLP_CHK_NODE_ACT(ndlp)) {
2798 ndlp = lpfc_enable_node(vport, ndlp,
2799 NLP_STE_UNUSED_NODE);
2800 if (!ndlp)
2801 continue;
2802 spin_lock_irq(&phba->ndlp_lock);
2803 NLP_SET_FREE_REQ(ndlp);
2804 spin_unlock_irq(&phba->ndlp_lock);
2805 /* Trigger the release of the ndlp memory */
2806 lpfc_nlp_put(ndlp);
2807 continue;
2808 }
2809 spin_lock_irq(&phba->ndlp_lock);
2810 if (NLP_CHK_FREE_REQ(ndlp)) {
2811 /* The ndlp should not be in memory free mode already */
2812 spin_unlock_irq(&phba->ndlp_lock);
2813 continue;
2814 } else
2815 /* Indicate request for freeing ndlp memory */
2816 NLP_SET_FREE_REQ(ndlp);
2817 spin_unlock_irq(&phba->ndlp_lock);
2818
58da1ffb
JS
2819 if (vport->port_type != LPFC_PHYSICAL_PORT &&
2820 ndlp->nlp_DID == Fabric_DID) {
2821 /* Just free up ndlp with Fabric_DID for vports */
2822 lpfc_nlp_put(ndlp);
2823 continue;
2824 }
2825
eff4a01b
JS
2826 /* take care of nodes in unused state before the state
2827 * machine taking action.
2828 */
2829 if (ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
2830 lpfc_nlp_put(ndlp);
2831 continue;
2832 }
2833
87af33fe
JS
2834 if (ndlp->nlp_type & NLP_FABRIC)
2835 lpfc_disc_state_machine(vport, ndlp, NULL,
2836 NLP_EVT_DEVICE_RECOVERY);
e47c9093 2837
87af33fe
JS
2838 lpfc_disc_state_machine(vport, ndlp, NULL,
2839 NLP_EVT_DEVICE_RM);
2840 }
2841
a8adb832
JS
2842 /* At this point, ALL ndlp's should be gone
2843 * because of the previous NLP_EVT_DEVICE_RM.
2844 * Lets wait for this to happen, if needed.
2845 */
87af33fe 2846 while (!list_empty(&vport->fc_nodes)) {
a8adb832 2847 if (i++ > 3000) {
87af33fe 2848 lpfc_printf_vlog(vport, KERN_ERR, LOG_DISCOVERY,
a8adb832 2849 "0233 Nodelist not empty\n");
e47c9093
JS
2850 list_for_each_entry_safe(ndlp, next_ndlp,
2851 &vport->fc_nodes, nlp_listp) {
2852 lpfc_printf_vlog(ndlp->vport, KERN_ERR,
2853 LOG_NODE,
32350664 2854 "0282 did:x%x ndlp:x%px "
e47c9093
JS
2855 "usgmap:x%x refcnt:%d\n",
2856 ndlp->nlp_DID, (void *)ndlp,
2857 ndlp->nlp_usg_map,
2c935bc5 2858 kref_read(&ndlp->kref));
e47c9093 2859 }
a8adb832 2860 break;
87af33fe 2861 }
a8adb832
JS
2862
2863 /* Wait for any activity on ndlps to settle */
2864 msleep(10);
87af33fe 2865 }
1151e3ec 2866 lpfc_cleanup_vports_rrqs(vport, NULL);
dea3101e 2867}
2868
e59058c4 2869/**
3621a710 2870 * lpfc_stop_vport_timers - Stop all the timers associated with a vport
e59058c4
JS
2871 * @vport: pointer to a virtual N_Port data structure.
2872 *
2873 * This routine stops all the timers associated with a @vport. This function
2874 * is invoked before disabling or deleting a @vport. Note that the physical
2875 * port is treated as @vport 0.
2876 **/
92d7f7b0
JS
2877void
2878lpfc_stop_vport_timers(struct lpfc_vport *vport)
dea3101e 2879{
92d7f7b0 2880 del_timer_sync(&vport->els_tmofunc);
92494144 2881 del_timer_sync(&vport->delayed_disc_tmo);
92d7f7b0
JS
2882 lpfc_can_disctmo(vport);
2883 return;
dea3101e 2884}
2885
ecfd03c6
JS
2886/**
2887 * __lpfc_sli4_stop_fcf_redisc_wait_timer - Stop FCF rediscovery wait timer
2888 * @phba: pointer to lpfc hba data structure.
2889 *
2890 * This routine stops the SLI4 FCF rediscover wait timer if it's on. The
2891 * caller of this routine should already hold the host lock.
2892 **/
2893void
2894__lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2895{
5ac6b303
JS
2896 /* Clear pending FCF rediscovery wait flag */
2897 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
2898
ecfd03c6
JS
2899 /* Now, try to stop the timer */
2900 del_timer(&phba->fcf.redisc_wait);
2901}
2902
2903/**
2904 * lpfc_sli4_stop_fcf_redisc_wait_timer - Stop FCF rediscovery wait timer
2905 * @phba: pointer to lpfc hba data structure.
2906 *
2907 * This routine stops the SLI4 FCF rediscover wait timer if it's on. It
2908 * checks whether the FCF rediscovery wait timer is pending with the host
2909 * lock held before proceeding with disabling the timer and clearing the
2910 * wait timer pendig flag.
2911 **/
2912void
2913lpfc_sli4_stop_fcf_redisc_wait_timer(struct lpfc_hba *phba)
2914{
2915 spin_lock_irq(&phba->hbalock);
2916 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
2917 /* FCF rediscovery timer already fired or stopped */
2918 spin_unlock_irq(&phba->hbalock);
2919 return;
2920 }
2921 __lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
5ac6b303
JS
2922 /* Clear failover in progress flags */
2923 phba->fcf.fcf_flag &= ~(FCF_DEAD_DISC | FCF_ACVL_DISC);
ecfd03c6
JS
2924 spin_unlock_irq(&phba->hbalock);
2925}
2926
e59058c4 2927/**
3772a991 2928 * lpfc_stop_hba_timers - Stop all the timers associated with an HBA
e59058c4
JS
2929 * @phba: pointer to lpfc hba data structure.
2930 *
2931 * This routine stops all the timers associated with a HBA. This function is
2932 * invoked before either putting a HBA offline or unloading the driver.
2933 **/
3772a991
JS
2934void
2935lpfc_stop_hba_timers(struct lpfc_hba *phba)
dea3101e 2936{
cdb42bec
JS
2937 if (phba->pport)
2938 lpfc_stop_vport_timers(phba->pport);
32517fc0 2939 cancel_delayed_work_sync(&phba->eq_delay_work);
2e0fef85 2940 del_timer_sync(&phba->sli.mbox_tmo);
92d7f7b0 2941 del_timer_sync(&phba->fabric_block_timer);
9399627f 2942 del_timer_sync(&phba->eratt_poll);
3772a991 2943 del_timer_sync(&phba->hb_tmofunc);
1151e3ec
JS
2944 if (phba->sli_rev == LPFC_SLI_REV4) {
2945 del_timer_sync(&phba->rrq_tmr);
2946 phba->hba_flag &= ~HBA_RRQ_ACTIVE;
2947 }
3772a991
JS
2948 phba->hb_outstanding = 0;
2949
2950 switch (phba->pci_dev_grp) {
2951 case LPFC_PCI_DEV_LP:
2952 /* Stop any LightPulse device specific driver timers */
2953 del_timer_sync(&phba->fcp_poll_timer);
2954 break;
2955 case LPFC_PCI_DEV_OC:
cc0e5f1c 2956 /* Stop any OneConnect device specific driver timers */
ecfd03c6 2957 lpfc_sli4_stop_fcf_redisc_wait_timer(phba);
3772a991
JS
2958 break;
2959 default:
2960 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2961 "0297 Invalid device group (x%x)\n",
2962 phba->pci_dev_grp);
2963 break;
2964 }
2e0fef85 2965 return;
dea3101e 2966}
2967
e59058c4 2968/**
3621a710 2969 * lpfc_block_mgmt_io - Mark a HBA's management interface as blocked
e59058c4
JS
2970 * @phba: pointer to lpfc hba data structure.
2971 *
2972 * This routine marks a HBA's management interface as blocked. Once the HBA's
2973 * management interface is marked as blocked, all the user space access to
2974 * the HBA, whether they are from sysfs interface or libdfc interface will
2975 * all be blocked. The HBA is set to block the management interface when the
2976 * driver prepares the HBA interface for online or offline.
2977 **/
a6ababd2 2978static void
618a5230 2979lpfc_block_mgmt_io(struct lpfc_hba *phba, int mbx_action)
a6ababd2
AB
2980{
2981 unsigned long iflag;
6e7288d9
JS
2982 uint8_t actcmd = MBX_HEARTBEAT;
2983 unsigned long timeout;
2984
a6ababd2
AB
2985 spin_lock_irqsave(&phba->hbalock, iflag);
2986 phba->sli.sli_flag |= LPFC_BLOCK_MGMT_IO;
618a5230
JS
2987 spin_unlock_irqrestore(&phba->hbalock, iflag);
2988 if (mbx_action == LPFC_MBX_NO_WAIT)
2989 return;
2990 timeout = msecs_to_jiffies(LPFC_MBOX_TMO * 1000) + jiffies;
2991 spin_lock_irqsave(&phba->hbalock, iflag);
a183a15f 2992 if (phba->sli.mbox_active) {
6e7288d9 2993 actcmd = phba->sli.mbox_active->u.mb.mbxCommand;
a183a15f
JS
2994 /* Determine how long we might wait for the active mailbox
2995 * command to be gracefully completed by firmware.
2996 */
2997 timeout = msecs_to_jiffies(lpfc_mbox_tmo_val(phba,
2998 phba->sli.mbox_active) * 1000) + jiffies;
2999 }
a6ababd2 3000 spin_unlock_irqrestore(&phba->hbalock, iflag);
a183a15f 3001
6e7288d9
JS
3002 /* Wait for the outstnading mailbox command to complete */
3003 while (phba->sli.mbox_active) {
3004 /* Check active mailbox complete status every 2ms */
3005 msleep(2);
3006 if (time_after(jiffies, timeout)) {
3007 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3008 "2813 Mgmt IO is Blocked %x "
3009 "- mbox cmd %x still active\n",
3010 phba->sli.sli_flag, actcmd);
3011 break;
3012 }
3013 }
a6ababd2
AB
3014}
3015
6b5151fd
JS
3016/**
3017 * lpfc_sli4_node_prep - Assign RPIs for active nodes.
3018 * @phba: pointer to lpfc hba data structure.
3019 *
3020 * Allocate RPIs for all active remote nodes. This is needed whenever
3021 * an SLI4 adapter is reset and the driver is not unloading. Its purpose
3022 * is to fixup the temporary rpi assignments.
3023 **/
3024void
3025lpfc_sli4_node_prep(struct lpfc_hba *phba)
3026{
3027 struct lpfc_nodelist *ndlp, *next_ndlp;
3028 struct lpfc_vport **vports;
9d3d340d
JS
3029 int i, rpi;
3030 unsigned long flags;
6b5151fd
JS
3031
3032 if (phba->sli_rev != LPFC_SLI_REV4)
3033 return;
3034
3035 vports = lpfc_create_vport_work_array(phba);
9d3d340d
JS
3036 if (vports == NULL)
3037 return;
6b5151fd 3038
9d3d340d
JS
3039 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
3040 if (vports[i]->load_flag & FC_UNLOADING)
3041 continue;
3042
3043 list_for_each_entry_safe(ndlp, next_ndlp,
3044 &vports[i]->fc_nodes,
3045 nlp_listp) {
3046 if (!NLP_CHK_NODE_ACT(ndlp))
3047 continue;
3048 rpi = lpfc_sli4_alloc_rpi(phba);
3049 if (rpi == LPFC_RPI_ALLOC_ERROR) {
3050 spin_lock_irqsave(&phba->ndlp_lock, flags);
3051 NLP_CLR_NODE_ACT(ndlp);
3052 spin_unlock_irqrestore(&phba->ndlp_lock, flags);
3053 continue;
6b5151fd 3054 }
9d3d340d 3055 ndlp->nlp_rpi = rpi;
0f154226
JS
3056 lpfc_printf_vlog(ndlp->vport, KERN_INFO,
3057 LOG_NODE | LOG_DISCOVERY,
3058 "0009 Assign RPI x%x to ndlp x%px "
3059 "DID:x%06x flg:x%x map:x%x\n",
3060 ndlp->nlp_rpi, ndlp, ndlp->nlp_DID,
3061 ndlp->nlp_flag, ndlp->nlp_usg_map);
6b5151fd
JS
3062 }
3063 }
3064 lpfc_destroy_vport_work_array(phba, vports);
3065}
3066
c490850a
JS
3067/**
3068 * lpfc_create_expedite_pool - create expedite pool
3069 * @phba: pointer to lpfc hba data structure.
3070 *
3071 * This routine moves a batch of XRIs from lpfc_io_buf_list_put of HWQ 0
3072 * to expedite pool. Mark them as expedite.
3073 **/
3999df75 3074static void lpfc_create_expedite_pool(struct lpfc_hba *phba)
c490850a
JS
3075{
3076 struct lpfc_sli4_hdw_queue *qp;
3077 struct lpfc_io_buf *lpfc_ncmd;
3078 struct lpfc_io_buf *lpfc_ncmd_next;
3079 struct lpfc_epd_pool *epd_pool;
3080 unsigned long iflag;
3081
3082 epd_pool = &phba->epd_pool;
3083 qp = &phba->sli4_hba.hdwq[0];
3084
3085 spin_lock_init(&epd_pool->lock);
3086 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3087 spin_lock(&epd_pool->lock);
3088 INIT_LIST_HEAD(&epd_pool->list);
3089 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3090 &qp->lpfc_io_buf_list_put, list) {
3091 list_move_tail(&lpfc_ncmd->list, &epd_pool->list);
3092 lpfc_ncmd->expedite = true;
3093 qp->put_io_bufs--;
3094 epd_pool->count++;
3095 if (epd_pool->count >= XRI_BATCH)
3096 break;
3097 }
3098 spin_unlock(&epd_pool->lock);
3099 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3100}
3101
3102/**
3103 * lpfc_destroy_expedite_pool - destroy expedite pool
3104 * @phba: pointer to lpfc hba data structure.
3105 *
3106 * This routine returns XRIs from expedite pool to lpfc_io_buf_list_put
3107 * of HWQ 0. Clear the mark.
3108 **/
3999df75 3109static void lpfc_destroy_expedite_pool(struct lpfc_hba *phba)
c490850a
JS
3110{
3111 struct lpfc_sli4_hdw_queue *qp;
3112 struct lpfc_io_buf *lpfc_ncmd;
3113 struct lpfc_io_buf *lpfc_ncmd_next;
3114 struct lpfc_epd_pool *epd_pool;
3115 unsigned long iflag;
3116
3117 epd_pool = &phba->epd_pool;
3118 qp = &phba->sli4_hba.hdwq[0];
3119
3120 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3121 spin_lock(&epd_pool->lock);
3122 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3123 &epd_pool->list, list) {
3124 list_move_tail(&lpfc_ncmd->list,
3125 &qp->lpfc_io_buf_list_put);
3126 lpfc_ncmd->flags = false;
3127 qp->put_io_bufs++;
3128 epd_pool->count--;
3129 }
3130 spin_unlock(&epd_pool->lock);
3131 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3132}
3133
3134/**
3135 * lpfc_create_multixri_pools - create multi-XRI pools
3136 * @phba: pointer to lpfc hba data structure.
3137 *
3138 * This routine initialize public, private per HWQ. Then, move XRIs from
3139 * lpfc_io_buf_list_put to public pool. High and low watermark are also
3140 * Initialized.
3141 **/
3142void lpfc_create_multixri_pools(struct lpfc_hba *phba)
3143{
3144 u32 i, j;
3145 u32 hwq_count;
3146 u32 count_per_hwq;
3147 struct lpfc_io_buf *lpfc_ncmd;
3148 struct lpfc_io_buf *lpfc_ncmd_next;
3149 unsigned long iflag;
3150 struct lpfc_sli4_hdw_queue *qp;
3151 struct lpfc_multixri_pool *multixri_pool;
3152 struct lpfc_pbl_pool *pbl_pool;
3153 struct lpfc_pvt_pool *pvt_pool;
3154
3155 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3156 "1234 num_hdw_queue=%d num_present_cpu=%d common_xri_cnt=%d\n",
3157 phba->cfg_hdw_queue, phba->sli4_hba.num_present_cpu,
3158 phba->sli4_hba.io_xri_cnt);
3159
3160 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3161 lpfc_create_expedite_pool(phba);
3162
3163 hwq_count = phba->cfg_hdw_queue;
3164 count_per_hwq = phba->sli4_hba.io_xri_cnt / hwq_count;
3165
3166 for (i = 0; i < hwq_count; i++) {
3167 multixri_pool = kzalloc(sizeof(*multixri_pool), GFP_KERNEL);
3168
3169 if (!multixri_pool) {
3170 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3171 "1238 Failed to allocate memory for "
3172 "multixri_pool\n");
3173
3174 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3175 lpfc_destroy_expedite_pool(phba);
3176
3177 j = 0;
3178 while (j < i) {
3179 qp = &phba->sli4_hba.hdwq[j];
3180 kfree(qp->p_multixri_pool);
3181 j++;
3182 }
3183 phba->cfg_xri_rebalancing = 0;
3184 return;
3185 }
3186
3187 qp = &phba->sli4_hba.hdwq[i];
3188 qp->p_multixri_pool = multixri_pool;
3189
3190 multixri_pool->xri_limit = count_per_hwq;
3191 multixri_pool->rrb_next_hwqid = i;
3192
3193 /* Deal with public free xri pool */
3194 pbl_pool = &multixri_pool->pbl_pool;
3195 spin_lock_init(&pbl_pool->lock);
3196 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3197 spin_lock(&pbl_pool->lock);
3198 INIT_LIST_HEAD(&pbl_pool->list);
3199 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3200 &qp->lpfc_io_buf_list_put, list) {
3201 list_move_tail(&lpfc_ncmd->list, &pbl_pool->list);
3202 qp->put_io_bufs--;
3203 pbl_pool->count++;
3204 }
3205 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3206 "1235 Moved %d buffers from PUT list over to pbl_pool[%d]\n",
3207 pbl_pool->count, i);
3208 spin_unlock(&pbl_pool->lock);
3209 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3210
3211 /* Deal with private free xri pool */
3212 pvt_pool = &multixri_pool->pvt_pool;
3213 pvt_pool->high_watermark = multixri_pool->xri_limit / 2;
3214 pvt_pool->low_watermark = XRI_BATCH;
3215 spin_lock_init(&pvt_pool->lock);
3216 spin_lock_irqsave(&pvt_pool->lock, iflag);
3217 INIT_LIST_HEAD(&pvt_pool->list);
3218 pvt_pool->count = 0;
3219 spin_unlock_irqrestore(&pvt_pool->lock, iflag);
3220 }
3221}
3222
3223/**
3224 * lpfc_destroy_multixri_pools - destroy multi-XRI pools
3225 * @phba: pointer to lpfc hba data structure.
3226 *
3227 * This routine returns XRIs from public/private to lpfc_io_buf_list_put.
3228 **/
3999df75 3229static void lpfc_destroy_multixri_pools(struct lpfc_hba *phba)
c490850a
JS
3230{
3231 u32 i;
3232 u32 hwq_count;
3233 struct lpfc_io_buf *lpfc_ncmd;
3234 struct lpfc_io_buf *lpfc_ncmd_next;
3235 unsigned long iflag;
3236 struct lpfc_sli4_hdw_queue *qp;
3237 struct lpfc_multixri_pool *multixri_pool;
3238 struct lpfc_pbl_pool *pbl_pool;
3239 struct lpfc_pvt_pool *pvt_pool;
3240
3241 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
3242 lpfc_destroy_expedite_pool(phba);
3243
c00f62e6
JS
3244 if (!(phba->pport->load_flag & FC_UNLOADING))
3245 lpfc_sli_flush_io_rings(phba);
c66a9197 3246
c490850a
JS
3247 hwq_count = phba->cfg_hdw_queue;
3248
3249 for (i = 0; i < hwq_count; i++) {
3250 qp = &phba->sli4_hba.hdwq[i];
3251 multixri_pool = qp->p_multixri_pool;
3252 if (!multixri_pool)
3253 continue;
3254
3255 qp->p_multixri_pool = NULL;
3256
3257 spin_lock_irqsave(&qp->io_buf_list_put_lock, iflag);
3258
3259 /* Deal with public free xri pool */
3260 pbl_pool = &multixri_pool->pbl_pool;
3261 spin_lock(&pbl_pool->lock);
3262
3263 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3264 "1236 Moving %d buffers from pbl_pool[%d] TO PUT list\n",
3265 pbl_pool->count, i);
3266
3267 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3268 &pbl_pool->list, list) {
3269 list_move_tail(&lpfc_ncmd->list,
3270 &qp->lpfc_io_buf_list_put);
3271 qp->put_io_bufs++;
3272 pbl_pool->count--;
3273 }
3274
3275 INIT_LIST_HEAD(&pbl_pool->list);
3276 pbl_pool->count = 0;
3277
3278 spin_unlock(&pbl_pool->lock);
3279
3280 /* Deal with private free xri pool */
3281 pvt_pool = &multixri_pool->pvt_pool;
3282 spin_lock(&pvt_pool->lock);
3283
3284 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3285 "1237 Moving %d buffers from pvt_pool[%d] TO PUT list\n",
3286 pvt_pool->count, i);
3287
3288 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3289 &pvt_pool->list, list) {
3290 list_move_tail(&lpfc_ncmd->list,
3291 &qp->lpfc_io_buf_list_put);
3292 qp->put_io_bufs++;
3293 pvt_pool->count--;
3294 }
3295
3296 INIT_LIST_HEAD(&pvt_pool->list);
3297 pvt_pool->count = 0;
3298
3299 spin_unlock(&pvt_pool->lock);
3300 spin_unlock_irqrestore(&qp->io_buf_list_put_lock, iflag);
3301
3302 kfree(multixri_pool);
3303 }
3304}
3305
e59058c4 3306/**
3621a710 3307 * lpfc_online - Initialize and bring a HBA online
e59058c4
JS
3308 * @phba: pointer to lpfc hba data structure.
3309 *
3310 * This routine initializes the HBA and brings a HBA online. During this
3311 * process, the management interface is blocked to prevent user space access
3312 * to the HBA interfering with the driver initialization.
3313 *
3314 * Return codes
3315 * 0 - successful
3316 * 1 - failed
3317 **/
dea3101e 3318int
2e0fef85 3319lpfc_online(struct lpfc_hba *phba)
dea3101e 3320{
372bd282 3321 struct lpfc_vport *vport;
549e55cd 3322 struct lpfc_vport **vports;
a145fda3 3323 int i, error = 0;
16a3a208 3324 bool vpis_cleared = false;
2e0fef85 3325
dea3101e 3326 if (!phba)
3327 return 0;
372bd282 3328 vport = phba->pport;
dea3101e 3329
2e0fef85 3330 if (!(vport->fc_flag & FC_OFFLINE_MODE))
dea3101e 3331 return 0;
3332
ed957684 3333 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
e8b62011 3334 "0458 Bring Adapter online\n");
dea3101e 3335
618a5230 3336 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
46fa311e 3337
da0436e9
JS
3338 if (phba->sli_rev == LPFC_SLI_REV4) {
3339 if (lpfc_sli4_hba_setup(phba)) { /* Initialize SLI4 HBA */
3340 lpfc_unblock_mgmt_io(phba);
3341 return 1;
3342 }
16a3a208
JS
3343 spin_lock_irq(&phba->hbalock);
3344 if (!phba->sli4_hba.max_cfg_param.vpi_used)
3345 vpis_cleared = true;
3346 spin_unlock_irq(&phba->hbalock);
a145fda3
DK
3347
3348 /* Reestablish the local initiator port.
3349 * The offline process destroyed the previous lport.
3350 */
3351 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME &&
3352 !phba->nvmet_support) {
3353 error = lpfc_nvme_create_localport(phba->pport);
3354 if (error)
3355 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
3356 "6132 NVME restore reg failed "
3357 "on nvmei error x%x\n", error);
3358 }
da0436e9 3359 } else {
895427bd 3360 lpfc_sli_queue_init(phba);
da0436e9
JS
3361 if (lpfc_sli_hba_setup(phba)) { /* Initialize SLI2/SLI3 HBA */
3362 lpfc_unblock_mgmt_io(phba);
3363 return 1;
3364 }
46fa311e 3365 }
dea3101e 3366
549e55cd 3367 vports = lpfc_create_vport_work_array(phba);
aeb6641f 3368 if (vports != NULL) {
da0436e9 3369 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
549e55cd
JS
3370 struct Scsi_Host *shost;
3371 shost = lpfc_shost_from_vport(vports[i]);
3372 spin_lock_irq(shost->host_lock);
3373 vports[i]->fc_flag &= ~FC_OFFLINE_MODE;
3374 if (phba->sli3_options & LPFC_SLI3_NPIV_ENABLED)
3375 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
16a3a208 3376 if (phba->sli_rev == LPFC_SLI_REV4) {
1c6834a7 3377 vports[i]->fc_flag |= FC_VPORT_NEEDS_INIT_VPI;
16a3a208
JS
3378 if ((vpis_cleared) &&
3379 (vports[i]->port_type !=
3380 LPFC_PHYSICAL_PORT))
3381 vports[i]->vpi = 0;
3382 }
549e55cd
JS
3383 spin_unlock_irq(shost->host_lock);
3384 }
aeb6641f
AB
3385 }
3386 lpfc_destroy_vport_work_array(phba, vports);
dea3101e 3387
c490850a
JS
3388 if (phba->cfg_xri_rebalancing)
3389 lpfc_create_multixri_pools(phba);
3390
46fa311e 3391 lpfc_unblock_mgmt_io(phba);
dea3101e 3392 return 0;
3393}
3394
e59058c4 3395/**
3621a710 3396 * lpfc_unblock_mgmt_io - Mark a HBA's management interface to be not blocked
e59058c4
JS
3397 * @phba: pointer to lpfc hba data structure.
3398 *
3399 * This routine marks a HBA's management interface as not blocked. Once the
3400 * HBA's management interface is marked as not blocked, all the user space
3401 * access to the HBA, whether they are from sysfs interface or libdfc
3402 * interface will be allowed. The HBA is set to block the management interface
3403 * when the driver prepares the HBA interface for online or offline and then
3404 * set to unblock the management interface afterwards.
3405 **/
46fa311e
JS
3406void
3407lpfc_unblock_mgmt_io(struct lpfc_hba * phba)
3408{
3409 unsigned long iflag;
3410
2e0fef85
JS
3411 spin_lock_irqsave(&phba->hbalock, iflag);
3412 phba->sli.sli_flag &= ~LPFC_BLOCK_MGMT_IO;
3413 spin_unlock_irqrestore(&phba->hbalock, iflag);
46fa311e
JS
3414}
3415
e59058c4 3416/**
3621a710 3417 * lpfc_offline_prep - Prepare a HBA to be brought offline
e59058c4
JS
3418 * @phba: pointer to lpfc hba data structure.
3419 *
3420 * This routine is invoked to prepare a HBA to be brought offline. It performs
3421 * unregistration login to all the nodes on all vports and flushes the mailbox
3422 * queue to make it ready to be brought offline.
3423 **/
46fa311e 3424void
618a5230 3425lpfc_offline_prep(struct lpfc_hba *phba, int mbx_action)
46fa311e 3426{
2e0fef85 3427 struct lpfc_vport *vport = phba->pport;
46fa311e 3428 struct lpfc_nodelist *ndlp, *next_ndlp;
87af33fe 3429 struct lpfc_vport **vports;
72100cc4 3430 struct Scsi_Host *shost;
87af33fe 3431 int i;
dea3101e 3432
2e0fef85 3433 if (vport->fc_flag & FC_OFFLINE_MODE)
46fa311e 3434 return;
dea3101e 3435
618a5230 3436 lpfc_block_mgmt_io(phba, mbx_action);
dea3101e 3437
3438 lpfc_linkdown(phba);
3439
87af33fe
JS
3440 /* Issue an unreg_login to all nodes on all vports */
3441 vports = lpfc_create_vport_work_array(phba);
3442 if (vports != NULL) {
da0436e9 3443 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
a8adb832
JS
3444 if (vports[i]->load_flag & FC_UNLOADING)
3445 continue;
72100cc4
JS
3446 shost = lpfc_shost_from_vport(vports[i]);
3447 spin_lock_irq(shost->host_lock);
c868595d 3448 vports[i]->vpi_state &= ~LPFC_VPI_REGISTERED;
695a814e
JS
3449 vports[i]->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
3450 vports[i]->fc_flag &= ~FC_VFI_REGISTERED;
72100cc4 3451 spin_unlock_irq(shost->host_lock);
695a814e 3452
87af33fe
JS
3453 shost = lpfc_shost_from_vport(vports[i]);
3454 list_for_each_entry_safe(ndlp, next_ndlp,
3455 &vports[i]->fc_nodes,
3456 nlp_listp) {
0f154226
JS
3457 if ((!NLP_CHK_NODE_ACT(ndlp)) ||
3458 ndlp->nlp_state == NLP_STE_UNUSED_NODE) {
3459 /* Driver must assume RPI is invalid for
3460 * any unused or inactive node.
3461 */
3462 ndlp->nlp_rpi = LPFC_RPI_ALLOC_ERROR;
87af33fe 3463 continue;
0f154226
JS
3464 }
3465
87af33fe
JS
3466 if (ndlp->nlp_type & NLP_FABRIC) {
3467 lpfc_disc_state_machine(vports[i], ndlp,
3468 NULL, NLP_EVT_DEVICE_RECOVERY);
3469 lpfc_disc_state_machine(vports[i], ndlp,
3470 NULL, NLP_EVT_DEVICE_RM);
3471 }
3472 spin_lock_irq(shost->host_lock);
3473 ndlp->nlp_flag &= ~NLP_NPR_ADISC;
401ee0c1 3474 spin_unlock_irq(shost->host_lock);
6b5151fd
JS
3475 /*
3476 * Whenever an SLI4 port goes offline, free the
401ee0c1
JS
3477 * RPI. Get a new RPI when the adapter port
3478 * comes back online.
6b5151fd 3479 */
be6bb941 3480 if (phba->sli_rev == LPFC_SLI_REV4) {
0f154226
JS
3481 lpfc_printf_vlog(ndlp->vport, KERN_INFO,
3482 LOG_NODE | LOG_DISCOVERY,
3483 "0011 Free RPI x%x on "
3484 "ndlp:x%px did x%x "
3485 "usgmap:x%x\n",
3486 ndlp->nlp_rpi, ndlp,
3487 ndlp->nlp_DID,
3488 ndlp->nlp_usg_map);
6b5151fd 3489 lpfc_sli4_free_rpi(phba, ndlp->nlp_rpi);
0f154226 3490 ndlp->nlp_rpi = LPFC_RPI_ALLOC_ERROR;
be6bb941 3491 }
87af33fe
JS
3492 lpfc_unreg_rpi(vports[i], ndlp);
3493 }
3494 }
3495 }
09372820 3496 lpfc_destroy_vport_work_array(phba, vports);
dea3101e 3497
618a5230 3498 lpfc_sli_mbox_sys_shutdown(phba, mbx_action);
f485c18d
DK
3499
3500 if (phba->wq)
3501 flush_workqueue(phba->wq);
46fa311e
JS
3502}
3503
e59058c4 3504/**
3621a710 3505 * lpfc_offline - Bring a HBA offline
e59058c4
JS
3506 * @phba: pointer to lpfc hba data structure.
3507 *
3508 * This routine actually brings a HBA offline. It stops all the timers
3509 * associated with the HBA, brings down the SLI layer, and eventually
3510 * marks the HBA as in offline state for the upper layer protocol.
3511 **/
46fa311e 3512void
2e0fef85 3513lpfc_offline(struct lpfc_hba *phba)
46fa311e 3514{
549e55cd
JS
3515 struct Scsi_Host *shost;
3516 struct lpfc_vport **vports;
3517 int i;
46fa311e 3518
549e55cd 3519 if (phba->pport->fc_flag & FC_OFFLINE_MODE)
46fa311e 3520 return;
688a8863 3521
da0436e9
JS
3522 /* stop port and all timers associated with this hba */
3523 lpfc_stop_port(phba);
4b40d02b
DK
3524
3525 /* Tear down the local and target port registrations. The
3526 * nvme transports need to cleanup.
3527 */
3528 lpfc_nvmet_destroy_targetport(phba);
3529 lpfc_nvme_destroy_localport(phba->pport);
3530
51ef4c26
JS
3531 vports = lpfc_create_vport_work_array(phba);
3532 if (vports != NULL)
da0436e9 3533 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
51ef4c26 3534 lpfc_stop_vport_timers(vports[i]);
09372820 3535 lpfc_destroy_vport_work_array(phba, vports);
92d7f7b0 3536 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
e8b62011 3537 "0460 Bring Adapter offline\n");
dea3101e 3538 /* Bring down the SLI Layer and cleanup. The HBA is offline
3539 now. */
3540 lpfc_sli_hba_down(phba);
92d7f7b0 3541 spin_lock_irq(&phba->hbalock);
7054a606 3542 phba->work_ha = 0;
92d7f7b0 3543 spin_unlock_irq(&phba->hbalock);
549e55cd
JS
3544 vports = lpfc_create_vport_work_array(phba);
3545 if (vports != NULL)
da0436e9 3546 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
549e55cd 3547 shost = lpfc_shost_from_vport(vports[i]);
549e55cd
JS
3548 spin_lock_irq(shost->host_lock);
3549 vports[i]->work_port_events = 0;
3550 vports[i]->fc_flag |= FC_OFFLINE_MODE;
3551 spin_unlock_irq(shost->host_lock);
3552 }
09372820 3553 lpfc_destroy_vport_work_array(phba, vports);
c490850a
JS
3554
3555 if (phba->cfg_xri_rebalancing)
3556 lpfc_destroy_multixri_pools(phba);
dea3101e 3557}
3558
e59058c4 3559/**
3621a710 3560 * lpfc_scsi_free - Free all the SCSI buffers and IOCBs from driver lists
e59058c4
JS
3561 * @phba: pointer to lpfc hba data structure.
3562 *
3563 * This routine is to free all the SCSI buffers and IOCBs from the driver
3564 * list back to kernel. It is called from lpfc_pci_remove_one to free
3565 * the internal resources before the device is removed from the system.
e59058c4 3566 **/
8a9d2e80 3567static void
2e0fef85 3568lpfc_scsi_free(struct lpfc_hba *phba)
dea3101e 3569{
c490850a 3570 struct lpfc_io_buf *sb, *sb_next;
dea3101e 3571
895427bd
JS
3572 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
3573 return;
3574
2e0fef85 3575 spin_lock_irq(&phba->hbalock);
a40fc5f0 3576
dea3101e 3577 /* Release all the lpfc_scsi_bufs maintained by this host. */
a40fc5f0
JS
3578
3579 spin_lock(&phba->scsi_buf_list_put_lock);
3580 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_put,
3581 list) {
dea3101e 3582 list_del(&sb->list);
771db5c0 3583 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
92d7f7b0 3584 sb->dma_handle);
dea3101e 3585 kfree(sb);
3586 phba->total_scsi_bufs--;
3587 }
a40fc5f0
JS
3588 spin_unlock(&phba->scsi_buf_list_put_lock);
3589
3590 spin_lock(&phba->scsi_buf_list_get_lock);
3591 list_for_each_entry_safe(sb, sb_next, &phba->lpfc_scsi_buf_list_get,
3592 list) {
dea3101e 3593 list_del(&sb->list);
771db5c0 3594 dma_pool_free(phba->lpfc_sg_dma_buf_pool, sb->data,
92d7f7b0 3595 sb->dma_handle);
dea3101e 3596 kfree(sb);
3597 phba->total_scsi_bufs--;
3598 }
a40fc5f0 3599 spin_unlock(&phba->scsi_buf_list_get_lock);
2e0fef85 3600 spin_unlock_irq(&phba->hbalock);
8a9d2e80 3601}
0794d601 3602
895427bd 3603/**
5e5b511d 3604 * lpfc_io_free - Free all the IO buffers and IOCBs from driver lists
895427bd
JS
3605 * @phba: pointer to lpfc hba data structure.
3606 *
0794d601 3607 * This routine is to free all the IO buffers and IOCBs from the driver
895427bd
JS
3608 * list back to kernel. It is called from lpfc_pci_remove_one to free
3609 * the internal resources before the device is removed from the system.
3610 **/
c490850a 3611void
5e5b511d 3612lpfc_io_free(struct lpfc_hba *phba)
895427bd 3613{
c490850a 3614 struct lpfc_io_buf *lpfc_ncmd, *lpfc_ncmd_next;
5e5b511d
JS
3615 struct lpfc_sli4_hdw_queue *qp;
3616 int idx;
895427bd 3617
5e5b511d
JS
3618 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3619 qp = &phba->sli4_hba.hdwq[idx];
3620 /* Release all the lpfc_nvme_bufs maintained by this host. */
3621 spin_lock(&qp->io_buf_list_put_lock);
3622 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3623 &qp->lpfc_io_buf_list_put,
3624 list) {
3625 list_del(&lpfc_ncmd->list);
3626 qp->put_io_bufs--;
3627 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3628 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
d79c9e9d
JS
3629 if (phba->cfg_xpsgl && !phba->nvmet_support)
3630 lpfc_put_sgl_per_hdwq(phba, lpfc_ncmd);
3631 lpfc_put_cmd_rsp_buf_per_hdwq(phba, lpfc_ncmd);
5e5b511d
JS
3632 kfree(lpfc_ncmd);
3633 qp->total_io_bufs--;
3634 }
3635 spin_unlock(&qp->io_buf_list_put_lock);
3636
3637 spin_lock(&qp->io_buf_list_get_lock);
3638 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
3639 &qp->lpfc_io_buf_list_get,
3640 list) {
3641 list_del(&lpfc_ncmd->list);
3642 qp->get_io_bufs--;
3643 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
3644 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
d79c9e9d
JS
3645 if (phba->cfg_xpsgl && !phba->nvmet_support)
3646 lpfc_put_sgl_per_hdwq(phba, lpfc_ncmd);
3647 lpfc_put_cmd_rsp_buf_per_hdwq(phba, lpfc_ncmd);
5e5b511d
JS
3648 kfree(lpfc_ncmd);
3649 qp->total_io_bufs--;
3650 }
3651 spin_unlock(&qp->io_buf_list_get_lock);
895427bd 3652 }
895427bd 3653}
0794d601 3654
8a9d2e80 3655/**
895427bd 3656 * lpfc_sli4_els_sgl_update - update ELS xri-sgl sizing and mapping
8a9d2e80
JS
3657 * @phba: pointer to lpfc hba data structure.
3658 *
3659 * This routine first calculates the sizes of the current els and allocated
3660 * scsi sgl lists, and then goes through all sgls to updates the physical
3661 * XRIs assigned due to port function reset. During port initialization, the
3662 * current els and allocated scsi sgl lists are 0s.
3663 *
3664 * Return codes
3665 * 0 - successful (for now, it always returns 0)
3666 **/
3667int
895427bd 3668lpfc_sli4_els_sgl_update(struct lpfc_hba *phba)
8a9d2e80
JS
3669{
3670 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
895427bd 3671 uint16_t i, lxri, xri_cnt, els_xri_cnt;
8a9d2e80 3672 LIST_HEAD(els_sgl_list);
8a9d2e80
JS
3673 int rc;
3674
3675 /*
3676 * update on pci function's els xri-sgl list
3677 */
3678 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
895427bd 3679
8a9d2e80
JS
3680 if (els_xri_cnt > phba->sli4_hba.els_xri_cnt) {
3681 /* els xri-sgl expanded */
3682 xri_cnt = els_xri_cnt - phba->sli4_hba.els_xri_cnt;
3683 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3684 "3157 ELS xri-sgl count increased from "
3685 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3686 els_xri_cnt);
3687 /* allocate the additional els sgls */
3688 for (i = 0; i < xri_cnt; i++) {
3689 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3690 GFP_KERNEL);
3691 if (sglq_entry == NULL) {
3692 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3693 "2562 Failure to allocate an "
3694 "ELS sgl entry:%d\n", i);
3695 rc = -ENOMEM;
3696 goto out_free_mem;
3697 }
3698 sglq_entry->buff_type = GEN_BUFF_TYPE;
3699 sglq_entry->virt = lpfc_mbuf_alloc(phba, 0,
3700 &sglq_entry->phys);
3701 if (sglq_entry->virt == NULL) {
3702 kfree(sglq_entry);
3703 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3704 "2563 Failure to allocate an "
3705 "ELS mbuf:%d\n", i);
3706 rc = -ENOMEM;
3707 goto out_free_mem;
3708 }
3709 sglq_entry->sgl = sglq_entry->virt;
3710 memset(sglq_entry->sgl, 0, LPFC_BPL_SIZE);
3711 sglq_entry->state = SGL_FREED;
3712 list_add_tail(&sglq_entry->list, &els_sgl_list);
3713 }
38c20673 3714 spin_lock_irq(&phba->hbalock);
895427bd
JS
3715 spin_lock(&phba->sli4_hba.sgl_list_lock);
3716 list_splice_init(&els_sgl_list,
3717 &phba->sli4_hba.lpfc_els_sgl_list);
3718 spin_unlock(&phba->sli4_hba.sgl_list_lock);
38c20673 3719 spin_unlock_irq(&phba->hbalock);
8a9d2e80
JS
3720 } else if (els_xri_cnt < phba->sli4_hba.els_xri_cnt) {
3721 /* els xri-sgl shrinked */
3722 xri_cnt = phba->sli4_hba.els_xri_cnt - els_xri_cnt;
3723 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3724 "3158 ELS xri-sgl count decreased from "
3725 "%d to %d\n", phba->sli4_hba.els_xri_cnt,
3726 els_xri_cnt);
3727 spin_lock_irq(&phba->hbalock);
895427bd
JS
3728 spin_lock(&phba->sli4_hba.sgl_list_lock);
3729 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list,
3730 &els_sgl_list);
8a9d2e80
JS
3731 /* release extra els sgls from list */
3732 for (i = 0; i < xri_cnt; i++) {
3733 list_remove_head(&els_sgl_list,
3734 sglq_entry, struct lpfc_sglq, list);
3735 if (sglq_entry) {
895427bd
JS
3736 __lpfc_mbuf_free(phba, sglq_entry->virt,
3737 sglq_entry->phys);
8a9d2e80
JS
3738 kfree(sglq_entry);
3739 }
3740 }
895427bd
JS
3741 list_splice_init(&els_sgl_list,
3742 &phba->sli4_hba.lpfc_els_sgl_list);
3743 spin_unlock(&phba->sli4_hba.sgl_list_lock);
8a9d2e80
JS
3744 spin_unlock_irq(&phba->hbalock);
3745 } else
3746 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3747 "3163 ELS xri-sgl count unchanged: %d\n",
3748 els_xri_cnt);
3749 phba->sli4_hba.els_xri_cnt = els_xri_cnt;
3750
3751 /* update xris to els sgls on the list */
3752 sglq_entry = NULL;
3753 sglq_entry_next = NULL;
3754 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
895427bd 3755 &phba->sli4_hba.lpfc_els_sgl_list, list) {
8a9d2e80
JS
3756 lxri = lpfc_sli4_next_xritag(phba);
3757 if (lxri == NO_XRI) {
3758 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3759 "2400 Failed to allocate xri for "
3760 "ELS sgl\n");
3761 rc = -ENOMEM;
3762 goto out_free_mem;
3763 }
3764 sglq_entry->sli4_lxritag = lxri;
3765 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3766 }
895427bd
JS
3767 return 0;
3768
3769out_free_mem:
3770 lpfc_free_els_sgl_list(phba);
3771 return rc;
3772}
3773
f358dd0c
JS
3774/**
3775 * lpfc_sli4_nvmet_sgl_update - update xri-sgl sizing and mapping
3776 * @phba: pointer to lpfc hba data structure.
3777 *
3778 * This routine first calculates the sizes of the current els and allocated
3779 * scsi sgl lists, and then goes through all sgls to updates the physical
3780 * XRIs assigned due to port function reset. During port initialization, the
3781 * current els and allocated scsi sgl lists are 0s.
3782 *
3783 * Return codes
3784 * 0 - successful (for now, it always returns 0)
3785 **/
3786int
3787lpfc_sli4_nvmet_sgl_update(struct lpfc_hba *phba)
3788{
3789 struct lpfc_sglq *sglq_entry = NULL, *sglq_entry_next = NULL;
3790 uint16_t i, lxri, xri_cnt, els_xri_cnt;
6c621a22 3791 uint16_t nvmet_xri_cnt;
f358dd0c
JS
3792 LIST_HEAD(nvmet_sgl_list);
3793 int rc;
3794
3795 /*
3796 * update on pci function's nvmet xri-sgl list
3797 */
3798 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
61f3d4bf 3799
6c621a22
JS
3800 /* For NVMET, ALL remaining XRIs are dedicated for IO processing */
3801 nvmet_xri_cnt = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
f358dd0c
JS
3802 if (nvmet_xri_cnt > phba->sli4_hba.nvmet_xri_cnt) {
3803 /* els xri-sgl expanded */
3804 xri_cnt = nvmet_xri_cnt - phba->sli4_hba.nvmet_xri_cnt;
3805 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3806 "6302 NVMET xri-sgl cnt grew from %d to %d\n",
3807 phba->sli4_hba.nvmet_xri_cnt, nvmet_xri_cnt);
3808 /* allocate the additional nvmet sgls */
3809 for (i = 0; i < xri_cnt; i++) {
3810 sglq_entry = kzalloc(sizeof(struct lpfc_sglq),
3811 GFP_KERNEL);
3812 if (sglq_entry == NULL) {
3813 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3814 "6303 Failure to allocate an "
3815 "NVMET sgl entry:%d\n", i);
3816 rc = -ENOMEM;
3817 goto out_free_mem;
3818 }
3819 sglq_entry->buff_type = NVMET_BUFF_TYPE;
3820 sglq_entry->virt = lpfc_nvmet_buf_alloc(phba, 0,
3821 &sglq_entry->phys);
3822 if (sglq_entry->virt == NULL) {
3823 kfree(sglq_entry);
3824 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3825 "6304 Failure to allocate an "
3826 "NVMET buf:%d\n", i);
3827 rc = -ENOMEM;
3828 goto out_free_mem;
3829 }
3830 sglq_entry->sgl = sglq_entry->virt;
3831 memset(sglq_entry->sgl, 0,
3832 phba->cfg_sg_dma_buf_size);
3833 sglq_entry->state = SGL_FREED;
3834 list_add_tail(&sglq_entry->list, &nvmet_sgl_list);
3835 }
3836 spin_lock_irq(&phba->hbalock);
3837 spin_lock(&phba->sli4_hba.sgl_list_lock);
3838 list_splice_init(&nvmet_sgl_list,
3839 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3840 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3841 spin_unlock_irq(&phba->hbalock);
3842 } else if (nvmet_xri_cnt < phba->sli4_hba.nvmet_xri_cnt) {
3843 /* nvmet xri-sgl shrunk */
3844 xri_cnt = phba->sli4_hba.nvmet_xri_cnt - nvmet_xri_cnt;
3845 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3846 "6305 NVMET xri-sgl count decreased from "
3847 "%d to %d\n", phba->sli4_hba.nvmet_xri_cnt,
3848 nvmet_xri_cnt);
3849 spin_lock_irq(&phba->hbalock);
3850 spin_lock(&phba->sli4_hba.sgl_list_lock);
3851 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list,
3852 &nvmet_sgl_list);
3853 /* release extra nvmet sgls from list */
3854 for (i = 0; i < xri_cnt; i++) {
3855 list_remove_head(&nvmet_sgl_list,
3856 sglq_entry, struct lpfc_sglq, list);
3857 if (sglq_entry) {
3858 lpfc_nvmet_buf_free(phba, sglq_entry->virt,
3859 sglq_entry->phys);
3860 kfree(sglq_entry);
3861 }
3862 }
3863 list_splice_init(&nvmet_sgl_list,
3864 &phba->sli4_hba.lpfc_nvmet_sgl_list);
3865 spin_unlock(&phba->sli4_hba.sgl_list_lock);
3866 spin_unlock_irq(&phba->hbalock);
3867 } else
3868 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
3869 "6306 NVMET xri-sgl count unchanged: %d\n",
3870 nvmet_xri_cnt);
3871 phba->sli4_hba.nvmet_xri_cnt = nvmet_xri_cnt;
3872
3873 /* update xris to nvmet sgls on the list */
3874 sglq_entry = NULL;
3875 sglq_entry_next = NULL;
3876 list_for_each_entry_safe(sglq_entry, sglq_entry_next,
3877 &phba->sli4_hba.lpfc_nvmet_sgl_list, list) {
3878 lxri = lpfc_sli4_next_xritag(phba);
3879 if (lxri == NO_XRI) {
3880 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
3881 "6307 Failed to allocate xri for "
3882 "NVMET sgl\n");
3883 rc = -ENOMEM;
3884 goto out_free_mem;
3885 }
3886 sglq_entry->sli4_lxritag = lxri;
3887 sglq_entry->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
3888 }
3889 return 0;
3890
3891out_free_mem:
3892 lpfc_free_nvmet_sgl_list(phba);
3893 return rc;
3894}
3895
5e5b511d
JS
3896int
3897lpfc_io_buf_flush(struct lpfc_hba *phba, struct list_head *cbuf)
3898{
3899 LIST_HEAD(blist);
3900 struct lpfc_sli4_hdw_queue *qp;
c490850a
JS
3901 struct lpfc_io_buf *lpfc_cmd;
3902 struct lpfc_io_buf *iobufp, *prev_iobufp;
5e5b511d
JS
3903 int idx, cnt, xri, inserted;
3904
3905 cnt = 0;
3906 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3907 qp = &phba->sli4_hba.hdwq[idx];
3908 spin_lock_irq(&qp->io_buf_list_get_lock);
3909 spin_lock(&qp->io_buf_list_put_lock);
3910
3911 /* Take everything off the get and put lists */
3912 list_splice_init(&qp->lpfc_io_buf_list_get, &blist);
3913 list_splice(&qp->lpfc_io_buf_list_put, &blist);
3914 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
3915 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
3916 cnt += qp->get_io_bufs + qp->put_io_bufs;
3917 qp->get_io_bufs = 0;
3918 qp->put_io_bufs = 0;
3919 qp->total_io_bufs = 0;
3920 spin_unlock(&qp->io_buf_list_put_lock);
3921 spin_unlock_irq(&qp->io_buf_list_get_lock);
3922 }
3923
3924 /*
3925 * Take IO buffers off blist and put on cbuf sorted by XRI.
3926 * This is because POST_SGL takes a sequential range of XRIs
3927 * to post to the firmware.
3928 */
3929 for (idx = 0; idx < cnt; idx++) {
c490850a 3930 list_remove_head(&blist, lpfc_cmd, struct lpfc_io_buf, list);
5e5b511d
JS
3931 if (!lpfc_cmd)
3932 return cnt;
3933 if (idx == 0) {
3934 list_add_tail(&lpfc_cmd->list, cbuf);
3935 continue;
3936 }
3937 xri = lpfc_cmd->cur_iocbq.sli4_xritag;
3938 inserted = 0;
3939 prev_iobufp = NULL;
3940 list_for_each_entry(iobufp, cbuf, list) {
3941 if (xri < iobufp->cur_iocbq.sli4_xritag) {
3942 if (prev_iobufp)
3943 list_add(&lpfc_cmd->list,
3944 &prev_iobufp->list);
3945 else
3946 list_add(&lpfc_cmd->list, cbuf);
3947 inserted = 1;
3948 break;
3949 }
3950 prev_iobufp = iobufp;
3951 }
3952 if (!inserted)
3953 list_add_tail(&lpfc_cmd->list, cbuf);
3954 }
3955 return cnt;
3956}
3957
3958int
3959lpfc_io_buf_replenish(struct lpfc_hba *phba, struct list_head *cbuf)
3960{
3961 struct lpfc_sli4_hdw_queue *qp;
c490850a 3962 struct lpfc_io_buf *lpfc_cmd;
5e5b511d
JS
3963 int idx, cnt;
3964
3965 qp = phba->sli4_hba.hdwq;
3966 cnt = 0;
3967 while (!list_empty(cbuf)) {
3968 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
3969 list_remove_head(cbuf, lpfc_cmd,
c490850a 3970 struct lpfc_io_buf, list);
5e5b511d
JS
3971 if (!lpfc_cmd)
3972 return cnt;
3973 cnt++;
3974 qp = &phba->sli4_hba.hdwq[idx];
1fbf9742
JS
3975 lpfc_cmd->hdwq_no = idx;
3976 lpfc_cmd->hdwq = qp;
5e5b511d
JS
3977 lpfc_cmd->cur_iocbq.wqe_cmpl = NULL;
3978 lpfc_cmd->cur_iocbq.iocb_cmpl = NULL;
3979 spin_lock(&qp->io_buf_list_put_lock);
3980 list_add_tail(&lpfc_cmd->list,
3981 &qp->lpfc_io_buf_list_put);
3982 qp->put_io_bufs++;
3983 qp->total_io_bufs++;
3984 spin_unlock(&qp->io_buf_list_put_lock);
3985 }
3986 }
3987 return cnt;
3988}
3989
895427bd 3990/**
5e5b511d 3991 * lpfc_sli4_io_sgl_update - update xri-sgl sizing and mapping
895427bd
JS
3992 * @phba: pointer to lpfc hba data structure.
3993 *
3994 * This routine first calculates the sizes of the current els and allocated
3995 * scsi sgl lists, and then goes through all sgls to updates the physical
3996 * XRIs assigned due to port function reset. During port initialization, the
3997 * current els and allocated scsi sgl lists are 0s.
3998 *
3999 * Return codes
4000 * 0 - successful (for now, it always returns 0)
4001 **/
4002int
5e5b511d 4003lpfc_sli4_io_sgl_update(struct lpfc_hba *phba)
895427bd 4004{
c490850a 4005 struct lpfc_io_buf *lpfc_ncmd = NULL, *lpfc_ncmd_next = NULL;
0794d601 4006 uint16_t i, lxri, els_xri_cnt;
5e5b511d
JS
4007 uint16_t io_xri_cnt, io_xri_max;
4008 LIST_HEAD(io_sgl_list);
0794d601 4009 int rc, cnt;
8a9d2e80 4010
895427bd 4011 /*
0794d601 4012 * update on pci function's allocated nvme xri-sgl list
895427bd 4013 */
8a9d2e80 4014
0794d601
JS
4015 /* maximum number of xris available for nvme buffers */
4016 els_xri_cnt = lpfc_sli4_get_els_iocb_cnt(phba);
5e5b511d
JS
4017 io_xri_max = phba->sli4_hba.max_cfg_param.max_xri - els_xri_cnt;
4018 phba->sli4_hba.io_xri_max = io_xri_max;
895427bd 4019
e8c0a779 4020 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
0794d601
JS
4021 "6074 Current allocated XRI sgl count:%d, "
4022 "maximum XRI count:%d\n",
5e5b511d
JS
4023 phba->sli4_hba.io_xri_cnt,
4024 phba->sli4_hba.io_xri_max);
8a9d2e80 4025
5e5b511d 4026 cnt = lpfc_io_buf_flush(phba, &io_sgl_list);
8a9d2e80 4027
5e5b511d 4028 if (phba->sli4_hba.io_xri_cnt > phba->sli4_hba.io_xri_max) {
0794d601 4029 /* max nvme xri shrunk below the allocated nvme buffers */
5e5b511d
JS
4030 io_xri_cnt = phba->sli4_hba.io_xri_cnt -
4031 phba->sli4_hba.io_xri_max;
0794d601 4032 /* release the extra allocated nvme buffers */
5e5b511d
JS
4033 for (i = 0; i < io_xri_cnt; i++) {
4034 list_remove_head(&io_sgl_list, lpfc_ncmd,
c490850a 4035 struct lpfc_io_buf, list);
0794d601 4036 if (lpfc_ncmd) {
771db5c0 4037 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
0794d601
JS
4038 lpfc_ncmd->data,
4039 lpfc_ncmd->dma_handle);
4040 kfree(lpfc_ncmd);
a2fc4aef 4041 }
8a9d2e80 4042 }
5e5b511d 4043 phba->sli4_hba.io_xri_cnt -= io_xri_cnt;
8a9d2e80
JS
4044 }
4045
0794d601
JS
4046 /* update xris associated to remaining allocated nvme buffers */
4047 lpfc_ncmd = NULL;
4048 lpfc_ncmd_next = NULL;
5e5b511d 4049 phba->sli4_hba.io_xri_cnt = cnt;
0794d601 4050 list_for_each_entry_safe(lpfc_ncmd, lpfc_ncmd_next,
5e5b511d 4051 &io_sgl_list, list) {
8a9d2e80
JS
4052 lxri = lpfc_sli4_next_xritag(phba);
4053 if (lxri == NO_XRI) {
4054 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
0794d601
JS
4055 "6075 Failed to allocate xri for "
4056 "nvme buffer\n");
8a9d2e80
JS
4057 rc = -ENOMEM;
4058 goto out_free_mem;
4059 }
0794d601
JS
4060 lpfc_ncmd->cur_iocbq.sli4_lxritag = lxri;
4061 lpfc_ncmd->cur_iocbq.sli4_xritag = phba->sli4_hba.xri_ids[lxri];
8a9d2e80 4062 }
5e5b511d 4063 cnt = lpfc_io_buf_replenish(phba, &io_sgl_list);
dea3101e 4064 return 0;
8a9d2e80
JS
4065
4066out_free_mem:
5e5b511d 4067 lpfc_io_free(phba);
8a9d2e80 4068 return rc;
dea3101e 4069}
4070
0794d601 4071/**
5e5b511d 4072 * lpfc_new_io_buf - IO buffer allocator for HBA with SLI4 IF spec
0794d601
JS
4073 * @vport: The virtual port for which this call being executed.
4074 * @num_to_allocate: The requested number of buffers to allocate.
4075 *
4076 * This routine allocates nvme buffers for device with SLI-4 interface spec,
4077 * the nvme buffer contains all the necessary information needed to initiate
4078 * an I/O. After allocating up to @num_to_allocate IO buffers and put
4079 * them on a list, it post them to the port by using SGL block post.
4080 *
4081 * Return codes:
5e5b511d 4082 * int - number of IO buffers that were allocated and posted.
0794d601
JS
4083 * 0 = failure, less than num_to_alloc is a partial failure.
4084 **/
4085int
5e5b511d 4086lpfc_new_io_buf(struct lpfc_hba *phba, int num_to_alloc)
0794d601 4087{
c490850a 4088 struct lpfc_io_buf *lpfc_ncmd;
0794d601
JS
4089 struct lpfc_iocbq *pwqeq;
4090 uint16_t iotag, lxri = 0;
4091 int bcnt, num_posted;
4092 LIST_HEAD(prep_nblist);
4093 LIST_HEAD(post_nblist);
4094 LIST_HEAD(nvme_nblist);
4095
5e5b511d 4096 phba->sli4_hba.io_xri_cnt = 0;
0794d601 4097 for (bcnt = 0; bcnt < num_to_alloc; bcnt++) {
7f9989ba 4098 lpfc_ncmd = kzalloc(sizeof(*lpfc_ncmd), GFP_KERNEL);
0794d601
JS
4099 if (!lpfc_ncmd)
4100 break;
4101 /*
4102 * Get memory from the pci pool to map the virt space to
4103 * pci bus space for an I/O. The DMA buffer includes the
4104 * number of SGE's necessary to support the sg_tablesize.
4105 */
a5c990ee
TM
4106 lpfc_ncmd->data = dma_pool_zalloc(phba->lpfc_sg_dma_buf_pool,
4107 GFP_KERNEL,
4108 &lpfc_ncmd->dma_handle);
0794d601
JS
4109 if (!lpfc_ncmd->data) {
4110 kfree(lpfc_ncmd);
4111 break;
4112 }
0794d601 4113
d79c9e9d
JS
4114 if (phba->cfg_xpsgl && !phba->nvmet_support) {
4115 INIT_LIST_HEAD(&lpfc_ncmd->dma_sgl_xtra_list);
4116 } else {
4117 /*
4118 * 4K Page alignment is CRITICAL to BlockGuard, double
4119 * check to be sure.
4120 */
4121 if ((phba->sli3_options & LPFC_SLI3_BG_ENABLED) &&
4122 (((unsigned long)(lpfc_ncmd->data) &
4123 (unsigned long)(SLI4_PAGE_SIZE - 1)) != 0)) {
4124 lpfc_printf_log(phba, KERN_ERR, LOG_FCP,
4125 "3369 Memory alignment err: "
4126 "addr=%lx\n",
4127 (unsigned long)lpfc_ncmd->data);
4128 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4129 lpfc_ncmd->data,
4130 lpfc_ncmd->dma_handle);
4131 kfree(lpfc_ncmd);
4132 break;
4133 }
0794d601
JS
4134 }
4135
d79c9e9d
JS
4136 INIT_LIST_HEAD(&lpfc_ncmd->dma_cmd_rsp_list);
4137
0794d601
JS
4138 lxri = lpfc_sli4_next_xritag(phba);
4139 if (lxri == NO_XRI) {
4140 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4141 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4142 kfree(lpfc_ncmd);
4143 break;
4144 }
4145 pwqeq = &lpfc_ncmd->cur_iocbq;
4146
4147 /* Allocate iotag for lpfc_ncmd->cur_iocbq. */
4148 iotag = lpfc_sli_next_iotag(phba, pwqeq);
4149 if (iotag == 0) {
4150 dma_pool_free(phba->lpfc_sg_dma_buf_pool,
4151 lpfc_ncmd->data, lpfc_ncmd->dma_handle);
4152 kfree(lpfc_ncmd);
4153 lpfc_printf_log(phba, KERN_ERR, LOG_NVME_IOERR,
4154 "6121 Failed to allocate IOTAG for"
4155 " XRI:0x%x\n", lxri);
4156 lpfc_sli4_free_xri(phba, lxri);
4157 break;
4158 }
4159 pwqeq->sli4_lxritag = lxri;
4160 pwqeq->sli4_xritag = phba->sli4_hba.xri_ids[lxri];
4161 pwqeq->context1 = lpfc_ncmd;
4162
4163 /* Initialize local short-hand pointers. */
4164 lpfc_ncmd->dma_sgl = lpfc_ncmd->data;
4165 lpfc_ncmd->dma_phys_sgl = lpfc_ncmd->dma_handle;
4166 lpfc_ncmd->cur_iocbq.context1 = lpfc_ncmd;
c2017260 4167 spin_lock_init(&lpfc_ncmd->buf_lock);
0794d601
JS
4168
4169 /* add the nvme buffer to a post list */
4170 list_add_tail(&lpfc_ncmd->list, &post_nblist);
5e5b511d 4171 phba->sli4_hba.io_xri_cnt++;
0794d601
JS
4172 }
4173 lpfc_printf_log(phba, KERN_INFO, LOG_NVME,
4174 "6114 Allocate %d out of %d requested new NVME "
4175 "buffers\n", bcnt, num_to_alloc);
4176
4177 /* post the list of nvme buffer sgls to port if available */
4178 if (!list_empty(&post_nblist))
5e5b511d 4179 num_posted = lpfc_sli4_post_io_sgl_list(
0794d601
JS
4180 phba, &post_nblist, bcnt);
4181 else
4182 num_posted = 0;
4183
4184 return num_posted;
4185}
4186
96418b5e
JS
4187static uint64_t
4188lpfc_get_wwpn(struct lpfc_hba *phba)
4189{
4190 uint64_t wwn;
4191 int rc;
4192 LPFC_MBOXQ_t *mboxq;
4193 MAILBOX_t *mb;
4194
96418b5e
JS
4195 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
4196 GFP_KERNEL);
4197 if (!mboxq)
4198 return (uint64_t)-1;
4199
4200 /* First get WWN of HBA instance */
4201 lpfc_read_nv(phba, mboxq);
4202 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
4203 if (rc != MBX_SUCCESS) {
4204 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4205 "6019 Mailbox failed , mbxCmd x%x "
4206 "READ_NV, mbxStatus x%x\n",
4207 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
4208 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
4209 mempool_free(mboxq, phba->mbox_mem_pool);
4210 return (uint64_t) -1;
4211 }
4212 mb = &mboxq->u.mb;
4213 memcpy(&wwn, (char *)mb->un.varRDnvp.portname, sizeof(uint64_t));
4214 /* wwn is WWPN of HBA instance */
4215 mempool_free(mboxq, phba->mbox_mem_pool);
4216 if (phba->sli_rev == LPFC_SLI_REV4)
4217 return be64_to_cpu(wwn);
4218 else
286871a6 4219 return rol64(wwn, 32);
96418b5e
JS
4220}
4221
e59058c4 4222/**
3621a710 4223 * lpfc_create_port - Create an FC port
e59058c4
JS
4224 * @phba: pointer to lpfc hba data structure.
4225 * @instance: a unique integer ID to this FC port.
4226 * @dev: pointer to the device data structure.
4227 *
4228 * This routine creates a FC port for the upper layer protocol. The FC port
4229 * can be created on top of either a physical port or a virtual port provided
4230 * by the HBA. This routine also allocates a SCSI host data structure (shost)
4231 * and associates the FC port created before adding the shost into the SCSI
4232 * layer.
4233 *
4234 * Return codes
4235 * @vport - pointer to the virtual N_Port data structure.
4236 * NULL - port create failed.
4237 **/
2e0fef85 4238struct lpfc_vport *
3de2a653 4239lpfc_create_port(struct lpfc_hba *phba, int instance, struct device *dev)
47a8617c 4240{
2e0fef85 4241 struct lpfc_vport *vport;
895427bd 4242 struct Scsi_Host *shost = NULL;
2e0fef85 4243 int error = 0;
96418b5e
JS
4244 int i;
4245 uint64_t wwn;
4246 bool use_no_reset_hba = false;
56bc8028 4247 int rc;
96418b5e 4248
56bc8028
JS
4249 if (lpfc_no_hba_reset_cnt) {
4250 if (phba->sli_rev < LPFC_SLI_REV4 &&
4251 dev == &phba->pcidev->dev) {
4252 /* Reset the port first */
4253 lpfc_sli_brdrestart(phba);
4254 rc = lpfc_sli_chipset_init(phba);
4255 if (rc)
4256 return NULL;
4257 }
4258 wwn = lpfc_get_wwpn(phba);
4259 }
96418b5e
JS
4260
4261 for (i = 0; i < lpfc_no_hba_reset_cnt; i++) {
4262 if (wwn == lpfc_no_hba_reset[i]) {
4263 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4264 "6020 Setting use_no_reset port=%llx\n",
4265 wwn);
4266 use_no_reset_hba = true;
4267 break;
4268 }
4269 }
47a8617c 4270
895427bd
JS
4271 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
4272 if (dev != &phba->pcidev->dev) {
4273 shost = scsi_host_alloc(&lpfc_vport_template,
4274 sizeof(struct lpfc_vport));
4275 } else {
96418b5e 4276 if (!use_no_reset_hba)
895427bd
JS
4277 shost = scsi_host_alloc(&lpfc_template,
4278 sizeof(struct lpfc_vport));
4279 else
96418b5e 4280 shost = scsi_host_alloc(&lpfc_template_no_hr,
895427bd
JS
4281 sizeof(struct lpfc_vport));
4282 }
4283 } else if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
4284 shost = scsi_host_alloc(&lpfc_template_nvme,
ea4142f6
JS
4285 sizeof(struct lpfc_vport));
4286 }
2e0fef85
JS
4287 if (!shost)
4288 goto out;
47a8617c 4289
2e0fef85
JS
4290 vport = (struct lpfc_vport *) shost->hostdata;
4291 vport->phba = phba;
2e0fef85 4292 vport->load_flag |= FC_LOADING;
92d7f7b0 4293 vport->fc_flag |= FC_VPORT_NEEDS_REG_VPI;
7f5f3d0d 4294 vport->fc_rscn_flush = 0;
3de2a653 4295 lpfc_get_vport_cfgparam(vport);
895427bd 4296
f6e84790
JS
4297 /* Adjust value in vport */
4298 vport->cfg_enable_fc4_type = phba->cfg_enable_fc4_type;
4299
2e0fef85
JS
4300 shost->unique_id = instance;
4301 shost->max_id = LPFC_MAX_TARGET;
3de2a653 4302 shost->max_lun = vport->cfg_max_luns;
2e0fef85
JS
4303 shost->this_id = -1;
4304 shost->max_cmd_len = 16;
6a828b0f 4305
da0436e9 4306 if (phba->sli_rev == LPFC_SLI_REV4) {
77ffd346
JS
4307 if (!phba->cfg_fcp_mq_threshold ||
4308 phba->cfg_fcp_mq_threshold > phba->cfg_hdw_queue)
4309 phba->cfg_fcp_mq_threshold = phba->cfg_hdw_queue;
4310
4311 shost->nr_hw_queues = min_t(int, 2 * num_possible_nodes(),
4312 phba->cfg_fcp_mq_threshold);
6a828b0f 4313
28baac74 4314 shost->dma_boundary =
cb5172ea 4315 phba->sli4_hba.pc_sli4_params.sge_supp_len-1;
d79c9e9d
JS
4316
4317 if (phba->cfg_xpsgl && !phba->nvmet_support)
4318 shost->sg_tablesize = LPFC_MAX_SG_TABLESIZE;
4319 else
4320 shost->sg_tablesize = phba->cfg_scsi_seg_cnt;
ace44e48
JS
4321 } else
4322 /* SLI-3 has a limited number of hardware queues (3),
4323 * thus there is only one for FCP processing.
4324 */
4325 shost->nr_hw_queues = 1;
81301a9b 4326
47a8617c 4327 /*
2e0fef85
JS
4328 * Set initial can_queue value since 0 is no longer supported and
4329 * scsi_add_host will fail. This will be adjusted later based on the
4330 * max xri value determined in hba setup.
47a8617c 4331 */
2e0fef85 4332 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3de2a653 4333 if (dev != &phba->pcidev->dev) {
92d7f7b0
JS
4334 shost->transportt = lpfc_vport_transport_template;
4335 vport->port_type = LPFC_NPIV_PORT;
4336 } else {
4337 shost->transportt = lpfc_transport_template;
4338 vport->port_type = LPFC_PHYSICAL_PORT;
4339 }
47a8617c 4340
2e0fef85
JS
4341 /* Initialize all internally managed lists. */
4342 INIT_LIST_HEAD(&vport->fc_nodes);
da0436e9 4343 INIT_LIST_HEAD(&vport->rcv_buffer_list);
2e0fef85 4344 spin_lock_init(&vport->work_port_lock);
47a8617c 4345
f22eb4d3 4346 timer_setup(&vport->fc_disctmo, lpfc_disc_timeout, 0);
47a8617c 4347
f22eb4d3 4348 timer_setup(&vport->els_tmofunc, lpfc_els_timeout, 0);
92494144 4349
f22eb4d3 4350 timer_setup(&vport->delayed_disc_tmo, lpfc_delayed_disc_tmo, 0);
92494144 4351
aa6ff309
JS
4352 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED)
4353 lpfc_setup_bg(phba, shost);
4354
d139b9bd 4355 error = scsi_add_host_with_dma(shost, dev, &phba->pcidev->dev);
2e0fef85
JS
4356 if (error)
4357 goto out_put_shost;
47a8617c 4358
523128e5 4359 spin_lock_irq(&phba->port_list_lock);
2e0fef85 4360 list_add_tail(&vport->listentry, &phba->port_list);
523128e5 4361 spin_unlock_irq(&phba->port_list_lock);
2e0fef85 4362 return vport;
47a8617c 4363
2e0fef85
JS
4364out_put_shost:
4365 scsi_host_put(shost);
4366out:
4367 return NULL;
47a8617c
JS
4368}
4369
e59058c4 4370/**
3621a710 4371 * destroy_port - destroy an FC port
e59058c4
JS
4372 * @vport: pointer to an lpfc virtual N_Port data structure.
4373 *
4374 * This routine destroys a FC port from the upper layer protocol. All the
4375 * resources associated with the port are released.
4376 **/
2e0fef85
JS
4377void
4378destroy_port(struct lpfc_vport *vport)
47a8617c 4379{
92d7f7b0
JS
4380 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
4381 struct lpfc_hba *phba = vport->phba;
47a8617c 4382
858c9f6c 4383 lpfc_debugfs_terminate(vport);
92d7f7b0
JS
4384 fc_remove_host(shost);
4385 scsi_remove_host(shost);
47a8617c 4386
523128e5 4387 spin_lock_irq(&phba->port_list_lock);
92d7f7b0 4388 list_del_init(&vport->listentry);
523128e5 4389 spin_unlock_irq(&phba->port_list_lock);
47a8617c 4390
92d7f7b0 4391 lpfc_cleanup(vport);
47a8617c 4392 return;
47a8617c
JS
4393}
4394
e59058c4 4395/**
3621a710 4396 * lpfc_get_instance - Get a unique integer ID
e59058c4
JS
4397 *
4398 * This routine allocates a unique integer ID from lpfc_hba_index pool. It
4399 * uses the kernel idr facility to perform the task.
4400 *
4401 * Return codes:
4402 * instance - a unique integer ID allocated as the new instance.
4403 * -1 - lpfc get instance failed.
4404 **/
92d7f7b0
JS
4405int
4406lpfc_get_instance(void)
4407{
ab516036
TH
4408 int ret;
4409
4410 ret = idr_alloc(&lpfc_hba_index, NULL, 0, 0, GFP_KERNEL);
4411 return ret < 0 ? -1 : ret;
47a8617c
JS
4412}
4413
e59058c4 4414/**
3621a710 4415 * lpfc_scan_finished - method for SCSI layer to detect whether scan is done
e59058c4
JS
4416 * @shost: pointer to SCSI host data structure.
4417 * @time: elapsed time of the scan in jiffies.
4418 *
4419 * This routine is called by the SCSI layer with a SCSI host to determine
4420 * whether the scan host is finished.
4421 *
4422 * Note: there is no scan_start function as adapter initialization will have
4423 * asynchronously kicked off the link initialization.
4424 *
4425 * Return codes
4426 * 0 - SCSI host scan is not over yet.
4427 * 1 - SCSI host scan is over.
4428 **/
47a8617c
JS
4429int lpfc_scan_finished(struct Scsi_Host *shost, unsigned long time)
4430{
2e0fef85
JS
4431 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4432 struct lpfc_hba *phba = vport->phba;
858c9f6c 4433 int stat = 0;
47a8617c 4434
858c9f6c
JS
4435 spin_lock_irq(shost->host_lock);
4436
51ef4c26 4437 if (vport->load_flag & FC_UNLOADING) {
858c9f6c
JS
4438 stat = 1;
4439 goto finished;
4440 }
256ec0d0 4441 if (time >= msecs_to_jiffies(30 * 1000)) {
2e0fef85 4442 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011
JS
4443 "0461 Scanning longer than 30 "
4444 "seconds. Continuing initialization\n");
858c9f6c 4445 stat = 1;
47a8617c 4446 goto finished;
2e0fef85 4447 }
256ec0d0
JS
4448 if (time >= msecs_to_jiffies(15 * 1000) &&
4449 phba->link_state <= LPFC_LINK_DOWN) {
2e0fef85 4450 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
e8b62011
JS
4451 "0465 Link down longer than 15 "
4452 "seconds. Continuing initialization\n");
858c9f6c 4453 stat = 1;
47a8617c 4454 goto finished;
2e0fef85 4455 }
47a8617c 4456
2e0fef85 4457 if (vport->port_state != LPFC_VPORT_READY)
858c9f6c 4458 goto finished;
2e0fef85 4459 if (vport->num_disc_nodes || vport->fc_prli_sent)
858c9f6c 4460 goto finished;
256ec0d0 4461 if (vport->fc_map_cnt == 0 && time < msecs_to_jiffies(2 * 1000))
858c9f6c 4462 goto finished;
2e0fef85 4463 if ((phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) != 0)
858c9f6c
JS
4464 goto finished;
4465
4466 stat = 1;
47a8617c
JS
4467
4468finished:
858c9f6c
JS
4469 spin_unlock_irq(shost->host_lock);
4470 return stat;
92d7f7b0 4471}
47a8617c 4472
3999df75 4473static void lpfc_host_supported_speeds_set(struct Scsi_Host *shost)
cd71348a
JS
4474{
4475 struct lpfc_vport *vport = (struct lpfc_vport *)shost->hostdata;
4476 struct lpfc_hba *phba = vport->phba;
4477
4478 fc_host_supported_speeds(shost) = 0;
1dc5ec24
JS
4479 if (phba->lmt & LMT_128Gb)
4480 fc_host_supported_speeds(shost) |= FC_PORTSPEED_128GBIT;
cd71348a
JS
4481 if (phba->lmt & LMT_64Gb)
4482 fc_host_supported_speeds(shost) |= FC_PORTSPEED_64GBIT;
4483 if (phba->lmt & LMT_32Gb)
4484 fc_host_supported_speeds(shost) |= FC_PORTSPEED_32GBIT;
4485 if (phba->lmt & LMT_16Gb)
4486 fc_host_supported_speeds(shost) |= FC_PORTSPEED_16GBIT;
4487 if (phba->lmt & LMT_10Gb)
4488 fc_host_supported_speeds(shost) |= FC_PORTSPEED_10GBIT;
4489 if (phba->lmt & LMT_8Gb)
4490 fc_host_supported_speeds(shost) |= FC_PORTSPEED_8GBIT;
4491 if (phba->lmt & LMT_4Gb)
4492 fc_host_supported_speeds(shost) |= FC_PORTSPEED_4GBIT;
4493 if (phba->lmt & LMT_2Gb)
4494 fc_host_supported_speeds(shost) |= FC_PORTSPEED_2GBIT;
4495 if (phba->lmt & LMT_1Gb)
4496 fc_host_supported_speeds(shost) |= FC_PORTSPEED_1GBIT;
4497}
4498
e59058c4 4499/**
3621a710 4500 * lpfc_host_attrib_init - Initialize SCSI host attributes on a FC port
e59058c4
JS
4501 * @shost: pointer to SCSI host data structure.
4502 *
4503 * This routine initializes a given SCSI host attributes on a FC port. The
4504 * SCSI host can be either on top of a physical port or a virtual port.
4505 **/
92d7f7b0
JS
4506void lpfc_host_attrib_init(struct Scsi_Host *shost)
4507{
4508 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
4509 struct lpfc_hba *phba = vport->phba;
47a8617c 4510 /*
2e0fef85 4511 * Set fixed host attributes. Must done after lpfc_sli_hba_setup().
47a8617c
JS
4512 */
4513
2e0fef85
JS
4514 fc_host_node_name(shost) = wwn_to_u64(vport->fc_nodename.u.wwn);
4515 fc_host_port_name(shost) = wwn_to_u64(vport->fc_portname.u.wwn);
47a8617c
JS
4516 fc_host_supported_classes(shost) = FC_COS_CLASS3;
4517
4518 memset(fc_host_supported_fc4s(shost), 0,
2e0fef85 4519 sizeof(fc_host_supported_fc4s(shost)));
47a8617c
JS
4520 fc_host_supported_fc4s(shost)[2] = 1;
4521 fc_host_supported_fc4s(shost)[7] = 1;
4522
92d7f7b0
JS
4523 lpfc_vport_symbolic_node_name(vport, fc_host_symbolic_name(shost),
4524 sizeof fc_host_symbolic_name(shost));
47a8617c 4525
cd71348a 4526 lpfc_host_supported_speeds_set(shost);
47a8617c
JS
4527
4528 fc_host_maxframe_size(shost) =
2e0fef85
JS
4529 (((uint32_t) vport->fc_sparam.cmn.bbRcvSizeMsb & 0x0F) << 8) |
4530 (uint32_t) vport->fc_sparam.cmn.bbRcvSizeLsb;
47a8617c 4531
0af5d708
MC
4532 fc_host_dev_loss_tmo(shost) = vport->cfg_devloss_tmo;
4533
47a8617c
JS
4534 /* This value is also unchanging */
4535 memset(fc_host_active_fc4s(shost), 0,
2e0fef85 4536 sizeof(fc_host_active_fc4s(shost)));
47a8617c
JS
4537 fc_host_active_fc4s(shost)[2] = 1;
4538 fc_host_active_fc4s(shost)[7] = 1;
4539
92d7f7b0 4540 fc_host_max_npiv_vports(shost) = phba->max_vpi;
47a8617c 4541 spin_lock_irq(shost->host_lock);
51ef4c26 4542 vport->load_flag &= ~FC_LOADING;
47a8617c 4543 spin_unlock_irq(shost->host_lock);
47a8617c 4544}
dea3101e 4545
e59058c4 4546/**
da0436e9 4547 * lpfc_stop_port_s3 - Stop SLI3 device port
e59058c4
JS
4548 * @phba: pointer to lpfc hba data structure.
4549 *
da0436e9
JS
4550 * This routine is invoked to stop an SLI3 device port, it stops the device
4551 * from generating interrupts and stops the device driver's timers for the
4552 * device.
e59058c4 4553 **/
da0436e9
JS
4554static void
4555lpfc_stop_port_s3(struct lpfc_hba *phba)
db2378e0 4556{
da0436e9
JS
4557 /* Clear all interrupt enable conditions */
4558 writel(0, phba->HCregaddr);
4559 readl(phba->HCregaddr); /* flush */
4560 /* Clear all pending interrupts */
4561 writel(0xffffffff, phba->HAregaddr);
4562 readl(phba->HAregaddr); /* flush */
db2378e0 4563
da0436e9
JS
4564 /* Reset some HBA SLI setup states */
4565 lpfc_stop_hba_timers(phba);
4566 phba->pport->work_port_events = 0;
4567}
db2378e0 4568
da0436e9
JS
4569/**
4570 * lpfc_stop_port_s4 - Stop SLI4 device port
4571 * @phba: pointer to lpfc hba data structure.
4572 *
4573 * This routine is invoked to stop an SLI4 device port, it stops the device
4574 * from generating interrupts and stops the device driver's timers for the
4575 * device.
4576 **/
4577static void
4578lpfc_stop_port_s4(struct lpfc_hba *phba)
4579{
4580 /* Reset some HBA SLI4 setup states */
4581 lpfc_stop_hba_timers(phba);
cdb42bec
JS
4582 if (phba->pport)
4583 phba->pport->work_port_events = 0;
da0436e9 4584 phba->sli4_hba.intr_enable = 0;
da0436e9 4585}
9399627f 4586
da0436e9
JS
4587/**
4588 * lpfc_stop_port - Wrapper function for stopping hba port
4589 * @phba: Pointer to HBA context object.
4590 *
4591 * This routine wraps the actual SLI3 or SLI4 hba stop port routine from
4592 * the API jump table function pointer from the lpfc_hba struct.
4593 **/
4594void
4595lpfc_stop_port(struct lpfc_hba *phba)
4596{
4597 phba->lpfc_stop_port(phba);
f485c18d
DK
4598
4599 if (phba->wq)
4600 flush_workqueue(phba->wq);
da0436e9 4601}
db2378e0 4602
ecfd03c6
JS
4603/**
4604 * lpfc_fcf_redisc_wait_start_timer - Start fcf rediscover wait timer
4605 * @phba: Pointer to hba for which this call is being executed.
4606 *
4607 * This routine starts the timer waiting for the FCF rediscovery to complete.
4608 **/
4609void
4610lpfc_fcf_redisc_wait_start_timer(struct lpfc_hba *phba)
4611{
4612 unsigned long fcf_redisc_wait_tmo =
4613 (jiffies + msecs_to_jiffies(LPFC_FCF_REDISCOVER_WAIT_TMO));
4614 /* Start fcf rediscovery wait period timer */
4615 mod_timer(&phba->fcf.redisc_wait, fcf_redisc_wait_tmo);
4616 spin_lock_irq(&phba->hbalock);
4617 /* Allow action to new fcf asynchronous event */
4618 phba->fcf.fcf_flag &= ~(FCF_AVAILABLE | FCF_SCAN_DONE);
4619 /* Mark the FCF rediscovery pending state */
4620 phba->fcf.fcf_flag |= FCF_REDISC_PEND;
4621 spin_unlock_irq(&phba->hbalock);
4622}
4623
4624/**
4625 * lpfc_sli4_fcf_redisc_wait_tmo - FCF table rediscover wait timeout
4626 * @ptr: Map to lpfc_hba data structure pointer.
4627 *
4628 * This routine is invoked when waiting for FCF table rediscover has been
4629 * timed out. If new FCF record(s) has (have) been discovered during the
4630 * wait period, a new FCF event shall be added to the FCOE async event
4631 * list, and then worker thread shall be waked up for processing from the
4632 * worker thread context.
4633 **/
e399b228 4634static void
f22eb4d3 4635lpfc_sli4_fcf_redisc_wait_tmo(struct timer_list *t)
ecfd03c6 4636{
f22eb4d3 4637 struct lpfc_hba *phba = from_timer(phba, t, fcf.redisc_wait);
ecfd03c6
JS
4638
4639 /* Don't send FCF rediscovery event if timer cancelled */
4640 spin_lock_irq(&phba->hbalock);
4641 if (!(phba->fcf.fcf_flag & FCF_REDISC_PEND)) {
4642 spin_unlock_irq(&phba->hbalock);
4643 return;
4644 }
4645 /* Clear FCF rediscovery timer pending flag */
4646 phba->fcf.fcf_flag &= ~FCF_REDISC_PEND;
4647 /* FCF rediscovery event to worker thread */
4648 phba->fcf.fcf_flag |= FCF_REDISC_EVT;
4649 spin_unlock_irq(&phba->hbalock);
0c9ab6f5 4650 lpfc_printf_log(phba, KERN_INFO, LOG_FIP,
a93ff37a 4651 "2776 FCF rediscover quiescent timer expired\n");
ecfd03c6
JS
4652 /* wake up worker thread */
4653 lpfc_worker_wake_up(phba);
4654}
4655
e59058c4 4656/**
da0436e9 4657 * lpfc_sli4_parse_latt_fault - Parse sli4 link-attention link fault code
e59058c4 4658 * @phba: pointer to lpfc hba data structure.
da0436e9 4659 * @acqe_link: pointer to the async link completion queue entry.
e59058c4 4660 *
23288b78 4661 * This routine is to parse the SLI4 link-attention link fault code.
e59058c4 4662 **/
23288b78 4663static void
da0436e9
JS
4664lpfc_sli4_parse_latt_fault(struct lpfc_hba *phba,
4665 struct lpfc_acqe_link *acqe_link)
db2378e0 4666{
da0436e9
JS
4667 switch (bf_get(lpfc_acqe_link_fault, acqe_link)) {
4668 case LPFC_ASYNC_LINK_FAULT_NONE:
4669 case LPFC_ASYNC_LINK_FAULT_LOCAL:
4670 case LPFC_ASYNC_LINK_FAULT_REMOTE:
23288b78 4671 case LPFC_ASYNC_LINK_FAULT_LR_LRR:
da0436e9
JS
4672 break;
4673 default:
4674 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
23288b78 4675 "0398 Unknown link fault code: x%x\n",
da0436e9 4676 bf_get(lpfc_acqe_link_fault, acqe_link));
da0436e9
JS
4677 break;
4678 }
db2378e0
JS
4679}
4680
5b75da2f 4681/**
da0436e9 4682 * lpfc_sli4_parse_latt_type - Parse sli4 link attention type
5b75da2f 4683 * @phba: pointer to lpfc hba data structure.
da0436e9 4684 * @acqe_link: pointer to the async link completion queue entry.
5b75da2f 4685 *
da0436e9
JS
4686 * This routine is to parse the SLI4 link attention type and translate it
4687 * into the base driver's link attention type coding.
5b75da2f 4688 *
da0436e9
JS
4689 * Return: Link attention type in terms of base driver's coding.
4690 **/
4691static uint8_t
4692lpfc_sli4_parse_latt_type(struct lpfc_hba *phba,
4693 struct lpfc_acqe_link *acqe_link)
5b75da2f 4694{
da0436e9 4695 uint8_t att_type;
5b75da2f 4696
da0436e9
JS
4697 switch (bf_get(lpfc_acqe_link_status, acqe_link)) {
4698 case LPFC_ASYNC_LINK_STATUS_DOWN:
4699 case LPFC_ASYNC_LINK_STATUS_LOGICAL_DOWN:
76a95d75 4700 att_type = LPFC_ATT_LINK_DOWN;
da0436e9
JS
4701 break;
4702 case LPFC_ASYNC_LINK_STATUS_UP:
4703 /* Ignore physical link up events - wait for logical link up */
76a95d75 4704 att_type = LPFC_ATT_RESERVED;
da0436e9
JS
4705 break;
4706 case LPFC_ASYNC_LINK_STATUS_LOGICAL_UP:
76a95d75 4707 att_type = LPFC_ATT_LINK_UP;
da0436e9
JS
4708 break;
4709 default:
4710 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
4711 "0399 Invalid link attention type: x%x\n",
4712 bf_get(lpfc_acqe_link_status, acqe_link));
76a95d75 4713 att_type = LPFC_ATT_RESERVED;
da0436e9 4714 break;
5b75da2f 4715 }
da0436e9 4716 return att_type;
5b75da2f
JS
4717}
4718
8b68cd52
JS
4719/**
4720 * lpfc_sli_port_speed_get - Get sli3 link speed code to link speed
4721 * @phba: pointer to lpfc hba data structure.
4722 *
4723 * This routine is to get an SLI3 FC port's link speed in Mbps.
4724 *
4725 * Return: link speed in terms of Mbps.
4726 **/
4727uint32_t
4728lpfc_sli_port_speed_get(struct lpfc_hba *phba)
4729{
4730 uint32_t link_speed;
4731
4732 if (!lpfc_is_link_up(phba))
4733 return 0;
4734
a085e87c
JS
4735 if (phba->sli_rev <= LPFC_SLI_REV3) {
4736 switch (phba->fc_linkspeed) {
4737 case LPFC_LINK_SPEED_1GHZ:
4738 link_speed = 1000;
4739 break;
4740 case LPFC_LINK_SPEED_2GHZ:
4741 link_speed = 2000;
4742 break;
4743 case LPFC_LINK_SPEED_4GHZ:
4744 link_speed = 4000;
4745 break;
4746 case LPFC_LINK_SPEED_8GHZ:
4747 link_speed = 8000;
4748 break;
4749 case LPFC_LINK_SPEED_10GHZ:
4750 link_speed = 10000;
4751 break;
4752 case LPFC_LINK_SPEED_16GHZ:
4753 link_speed = 16000;
4754 break;
4755 default:
4756 link_speed = 0;
4757 }
4758 } else {
4759 if (phba->sli4_hba.link_state.logical_speed)
4760 link_speed =
4761 phba->sli4_hba.link_state.logical_speed;
4762 else
4763 link_speed = phba->sli4_hba.link_state.speed;
8b68cd52
JS
4764 }
4765 return link_speed;
4766}
4767
4768/**
4769 * lpfc_sli4_port_speed_parse - Parse async evt link speed code to link speed
4770 * @phba: pointer to lpfc hba data structure.
4771 * @evt_code: asynchronous event code.
4772 * @speed_code: asynchronous event link speed code.
4773 *
4774 * This routine is to parse the giving SLI4 async event link speed code into
4775 * value of Mbps for the link speed.
4776 *
4777 * Return: link speed in terms of Mbps.
4778 **/
4779static uint32_t
4780lpfc_sli4_port_speed_parse(struct lpfc_hba *phba, uint32_t evt_code,
4781 uint8_t speed_code)
4782{
4783 uint32_t port_speed;
4784
4785 switch (evt_code) {
4786 case LPFC_TRAILER_CODE_LINK:
4787 switch (speed_code) {
26d830ec 4788 case LPFC_ASYNC_LINK_SPEED_ZERO:
8b68cd52
JS
4789 port_speed = 0;
4790 break;
26d830ec 4791 case LPFC_ASYNC_LINK_SPEED_10MBPS:
8b68cd52
JS
4792 port_speed = 10;
4793 break;
26d830ec 4794 case LPFC_ASYNC_LINK_SPEED_100MBPS:
8b68cd52
JS
4795 port_speed = 100;
4796 break;
26d830ec 4797 case LPFC_ASYNC_LINK_SPEED_1GBPS:
8b68cd52
JS
4798 port_speed = 1000;
4799 break;
26d830ec 4800 case LPFC_ASYNC_LINK_SPEED_10GBPS:
8b68cd52
JS
4801 port_speed = 10000;
4802 break;
26d830ec
JS
4803 case LPFC_ASYNC_LINK_SPEED_20GBPS:
4804 port_speed = 20000;
4805 break;
4806 case LPFC_ASYNC_LINK_SPEED_25GBPS:
4807 port_speed = 25000;
4808 break;
4809 case LPFC_ASYNC_LINK_SPEED_40GBPS:
4810 port_speed = 40000;
4811 break;
8b68cd52
JS
4812 default:
4813 port_speed = 0;
4814 }
4815 break;
4816 case LPFC_TRAILER_CODE_FC:
4817 switch (speed_code) {
26d830ec 4818 case LPFC_FC_LA_SPEED_UNKNOWN:
8b68cd52
JS
4819 port_speed = 0;
4820 break;
26d830ec 4821 case LPFC_FC_LA_SPEED_1G:
8b68cd52
JS
4822 port_speed = 1000;
4823 break;
26d830ec 4824 case LPFC_FC_LA_SPEED_2G:
8b68cd52
JS
4825 port_speed = 2000;
4826 break;
26d830ec 4827 case LPFC_FC_LA_SPEED_4G:
8b68cd52
JS
4828 port_speed = 4000;
4829 break;
26d830ec 4830 case LPFC_FC_LA_SPEED_8G:
8b68cd52
JS
4831 port_speed = 8000;
4832 break;
26d830ec 4833 case LPFC_FC_LA_SPEED_10G:
8b68cd52
JS
4834 port_speed = 10000;
4835 break;
26d830ec 4836 case LPFC_FC_LA_SPEED_16G:
8b68cd52
JS
4837 port_speed = 16000;
4838 break;
d38dd52c
JS
4839 case LPFC_FC_LA_SPEED_32G:
4840 port_speed = 32000;
4841 break;
fbd8a6ba
JS
4842 case LPFC_FC_LA_SPEED_64G:
4843 port_speed = 64000;
4844 break;
1dc5ec24
JS
4845 case LPFC_FC_LA_SPEED_128G:
4846 port_speed = 128000;
4847 break;
8b68cd52
JS
4848 default:
4849 port_speed = 0;
4850 }
4851 break;
4852 default:
4853 port_speed = 0;
4854 }
4855 return port_speed;
4856}
4857
da0436e9 4858/**
70f3c073 4859 * lpfc_sli4_async_link_evt - Process the asynchronous FCoE link event
da0436e9
JS
4860 * @phba: pointer to lpfc hba data structure.
4861 * @acqe_link: pointer to the async link completion queue entry.
4862 *
70f3c073 4863 * This routine is to handle the SLI4 asynchronous FCoE link event.
da0436e9
JS
4864 **/
4865static void
4866lpfc_sli4_async_link_evt(struct lpfc_hba *phba,
4867 struct lpfc_acqe_link *acqe_link)
4868{
4869 struct lpfc_dmabuf *mp;
4870 LPFC_MBOXQ_t *pmb;
4871 MAILBOX_t *mb;
76a95d75 4872 struct lpfc_mbx_read_top *la;
da0436e9 4873 uint8_t att_type;
76a95d75 4874 int rc;
da0436e9
JS
4875
4876 att_type = lpfc_sli4_parse_latt_type(phba, acqe_link);
76a95d75 4877 if (att_type != LPFC_ATT_LINK_DOWN && att_type != LPFC_ATT_LINK_UP)
da0436e9 4878 return;
32b9793f 4879 phba->fcoe_eventtag = acqe_link->event_tag;
da0436e9
JS
4880 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
4881 if (!pmb) {
4882 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4883 "0395 The mboxq allocation failed\n");
4884 return;
4885 }
4886 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
4887 if (!mp) {
4888 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4889 "0396 The lpfc_dmabuf allocation failed\n");
4890 goto out_free_pmb;
4891 }
4892 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
4893 if (!mp->virt) {
4894 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
4895 "0397 The mbuf allocation failed\n");
4896 goto out_free_dmabuf;
4897 }
4898
4899 /* Cleanup any outstanding ELS commands */
4900 lpfc_els_flush_all_cmd(phba);
4901
4902 /* Block ELS IOCBs until we have done process link event */
895427bd 4903 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
da0436e9
JS
4904
4905 /* Update link event statistics */
4906 phba->sli.slistat.link_event++;
4907
76a95d75
JS
4908 /* Create lpfc_handle_latt mailbox command from link ACQE */
4909 lpfc_read_topology(phba, pmb, mp);
4910 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
da0436e9
JS
4911 pmb->vport = phba->pport;
4912
da0436e9
JS
4913 /* Keep the link status for extra SLI4 state machine reference */
4914 phba->sli4_hba.link_state.speed =
8b68cd52
JS
4915 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_LINK,
4916 bf_get(lpfc_acqe_link_speed, acqe_link));
da0436e9
JS
4917 phba->sli4_hba.link_state.duplex =
4918 bf_get(lpfc_acqe_link_duplex, acqe_link);
4919 phba->sli4_hba.link_state.status =
4920 bf_get(lpfc_acqe_link_status, acqe_link);
70f3c073
JS
4921 phba->sli4_hba.link_state.type =
4922 bf_get(lpfc_acqe_link_type, acqe_link);
4923 phba->sli4_hba.link_state.number =
4924 bf_get(lpfc_acqe_link_number, acqe_link);
da0436e9
JS
4925 phba->sli4_hba.link_state.fault =
4926 bf_get(lpfc_acqe_link_fault, acqe_link);
65467b6b 4927 phba->sli4_hba.link_state.logical_speed =
8b68cd52
JS
4928 bf_get(lpfc_acqe_logical_link_speed, acqe_link) * 10;
4929
70f3c073 4930 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
c31098ce
JS
4931 "2900 Async FC/FCoE Link event - Speed:%dGBit "
4932 "duplex:x%x LA Type:x%x Port Type:%d Port Number:%d "
4933 "Logical speed:%dMbps Fault:%d\n",
70f3c073
JS
4934 phba->sli4_hba.link_state.speed,
4935 phba->sli4_hba.link_state.topology,
4936 phba->sli4_hba.link_state.status,
4937 phba->sli4_hba.link_state.type,
4938 phba->sli4_hba.link_state.number,
8b68cd52 4939 phba->sli4_hba.link_state.logical_speed,
70f3c073 4940 phba->sli4_hba.link_state.fault);
76a95d75
JS
4941 /*
4942 * For FC Mode: issue the READ_TOPOLOGY mailbox command to fetch
4943 * topology info. Note: Optional for non FC-AL ports.
4944 */
4945 if (!(phba->hba_flag & HBA_FCOE_MODE)) {
4946 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
4947 if (rc == MBX_NOT_FINISHED)
4948 goto out_free_dmabuf;
4949 return;
4950 }
4951 /*
4952 * For FCoE Mode: fill in all the topology information we need and call
4953 * the READ_TOPOLOGY completion routine to continue without actually
4954 * sending the READ_TOPOLOGY mailbox command to the port.
4955 */
23288b78 4956 /* Initialize completion status */
76a95d75 4957 mb = &pmb->u.mb;
23288b78
JS
4958 mb->mbxStatus = MBX_SUCCESS;
4959
4960 /* Parse port fault information field */
4961 lpfc_sli4_parse_latt_fault(phba, acqe_link);
76a95d75
JS
4962
4963 /* Parse and translate link attention fields */
4964 la = (struct lpfc_mbx_read_top *) &pmb->u.mb.un.varReadTop;
4965 la->eventTag = acqe_link->event_tag;
4966 bf_set(lpfc_mbx_read_top_att_type, la, att_type);
4967 bf_set(lpfc_mbx_read_top_link_spd, la,
a085e87c 4968 (bf_get(lpfc_acqe_link_speed, acqe_link)));
76a95d75
JS
4969
4970 /* Fake the the following irrelvant fields */
4971 bf_set(lpfc_mbx_read_top_topology, la, LPFC_TOPOLOGY_PT_PT);
4972 bf_set(lpfc_mbx_read_top_alpa_granted, la, 0);
4973 bf_set(lpfc_mbx_read_top_il, la, 0);
4974 bf_set(lpfc_mbx_read_top_pb, la, 0);
4975 bf_set(lpfc_mbx_read_top_fa, la, 0);
4976 bf_set(lpfc_mbx_read_top_mm, la, 0);
da0436e9
JS
4977
4978 /* Invoke the lpfc_handle_latt mailbox command callback function */
76a95d75 4979 lpfc_mbx_cmpl_read_topology(phba, pmb);
da0436e9 4980
5b75da2f 4981 return;
da0436e9
JS
4982
4983out_free_dmabuf:
4984 kfree(mp);
4985out_free_pmb:
4986 mempool_free(pmb, phba->mbox_mem_pool);
4987}
4988
1dc5ec24
JS
4989/**
4990 * lpfc_async_link_speed_to_read_top - Parse async evt link speed code to read
4991 * topology.
4992 * @phba: pointer to lpfc hba data structure.
4993 * @evt_code: asynchronous event code.
4994 * @speed_code: asynchronous event link speed code.
4995 *
4996 * This routine is to parse the giving SLI4 async event link speed code into
4997 * value of Read topology link speed.
4998 *
4999 * Return: link speed in terms of Read topology.
5000 **/
5001static uint8_t
5002lpfc_async_link_speed_to_read_top(struct lpfc_hba *phba, uint8_t speed_code)
5003{
5004 uint8_t port_speed;
5005
5006 switch (speed_code) {
5007 case LPFC_FC_LA_SPEED_1G:
5008 port_speed = LPFC_LINK_SPEED_1GHZ;
5009 break;
5010 case LPFC_FC_LA_SPEED_2G:
5011 port_speed = LPFC_LINK_SPEED_2GHZ;
5012 break;
5013 case LPFC_FC_LA_SPEED_4G:
5014 port_speed = LPFC_LINK_SPEED_4GHZ;
5015 break;
5016 case LPFC_FC_LA_SPEED_8G:
5017 port_speed = LPFC_LINK_SPEED_8GHZ;
5018 break;
5019 case LPFC_FC_LA_SPEED_16G:
5020 port_speed = LPFC_LINK_SPEED_16GHZ;
5021 break;
5022 case LPFC_FC_LA_SPEED_32G:
5023 port_speed = LPFC_LINK_SPEED_32GHZ;
5024 break;
5025 case LPFC_FC_LA_SPEED_64G:
5026 port_speed = LPFC_LINK_SPEED_64GHZ;
5027 break;
5028 case LPFC_FC_LA_SPEED_128G:
5029 port_speed = LPFC_LINK_SPEED_128GHZ;
5030 break;
5031 case LPFC_FC_LA_SPEED_256G:
5032 port_speed = LPFC_LINK_SPEED_256GHZ;
5033 break;
5034 default:
5035 port_speed = 0;
5036 break;
5037 }
5038
5039 return port_speed;
5040}
5041
5042#define trunk_link_status(__idx)\
5043 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
5044 ((phba->trunk_link.link##__idx.state == LPFC_LINK_UP) ?\
5045 "Link up" : "Link down") : "NA"
5046/* Did port __idx reported an error */
5047#define trunk_port_fault(__idx)\
5048 bf_get(lpfc_acqe_fc_la_trunk_config_port##__idx, acqe_fc) ?\
5049 (port_fault & (1 << __idx) ? "YES" : "NO") : "NA"
5050
5051static void
5052lpfc_update_trunk_link_status(struct lpfc_hba *phba,
5053 struct lpfc_acqe_fc_la *acqe_fc)
5054{
5055 uint8_t port_fault = bf_get(lpfc_acqe_fc_la_trunk_linkmask, acqe_fc);
5056 uint8_t err = bf_get(lpfc_acqe_fc_la_trunk_fault, acqe_fc);
5057
5058 phba->sli4_hba.link_state.speed =
5059 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
5060 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5061
5062 phba->sli4_hba.link_state.logical_speed =
b8e6f136 5063 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
1dc5ec24
JS
5064 /* We got FC link speed, convert to fc_linkspeed (READ_TOPOLOGY) */
5065 phba->fc_linkspeed =
5066 lpfc_async_link_speed_to_read_top(
5067 phba,
5068 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
5069
5070 if (bf_get(lpfc_acqe_fc_la_trunk_config_port0, acqe_fc)) {
5071 phba->trunk_link.link0.state =
5072 bf_get(lpfc_acqe_fc_la_trunk_link_status_port0, acqe_fc)
5073 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5074 phba->trunk_link.link0.fault = port_fault & 0x1 ? err : 0;
1dc5ec24
JS
5075 }
5076 if (bf_get(lpfc_acqe_fc_la_trunk_config_port1, acqe_fc)) {
5077 phba->trunk_link.link1.state =
5078 bf_get(lpfc_acqe_fc_la_trunk_link_status_port1, acqe_fc)
5079 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5080 phba->trunk_link.link1.fault = port_fault & 0x2 ? err : 0;
1dc5ec24
JS
5081 }
5082 if (bf_get(lpfc_acqe_fc_la_trunk_config_port2, acqe_fc)) {
5083 phba->trunk_link.link2.state =
5084 bf_get(lpfc_acqe_fc_la_trunk_link_status_port2, acqe_fc)
5085 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5086 phba->trunk_link.link2.fault = port_fault & 0x4 ? err : 0;
1dc5ec24
JS
5087 }
5088 if (bf_get(lpfc_acqe_fc_la_trunk_config_port3, acqe_fc)) {
5089 phba->trunk_link.link3.state =
5090 bf_get(lpfc_acqe_fc_la_trunk_link_status_port3, acqe_fc)
5091 ? LPFC_LINK_UP : LPFC_LINK_DOWN;
529b3ddc 5092 phba->trunk_link.link3.fault = port_fault & 0x8 ? err : 0;
1dc5ec24
JS
5093 }
5094
5095 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5096 "2910 Async FC Trunking Event - Speed:%d\n"
5097 "\tLogical speed:%d "
5098 "port0: %s port1: %s port2: %s port3: %s\n",
5099 phba->sli4_hba.link_state.speed,
5100 phba->sli4_hba.link_state.logical_speed,
5101 trunk_link_status(0), trunk_link_status(1),
5102 trunk_link_status(2), trunk_link_status(3));
5103
5104 if (port_fault)
5105 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5106 "3202 trunk error:0x%x (%s) seen on port0:%s "
5107 /*
5108 * SLI-4: We have only 0xA error codes
5109 * defined as of now. print an appropriate
5110 * message in case driver needs to be updated.
5111 */
5112 "port1:%s port2:%s port3:%s\n", err, err > 0xA ?
5113 "UNDEFINED. update driver." : trunk_errmsg[err],
5114 trunk_port_fault(0), trunk_port_fault(1),
5115 trunk_port_fault(2), trunk_port_fault(3));
5116}
5117
5118
70f3c073
JS
5119/**
5120 * lpfc_sli4_async_fc_evt - Process the asynchronous FC link event
5121 * @phba: pointer to lpfc hba data structure.
5122 * @acqe_fc: pointer to the async fc completion queue entry.
5123 *
5124 * This routine is to handle the SLI4 asynchronous FC event. It will simply log
5125 * that the event was received and then issue a read_topology mailbox command so
5126 * that the rest of the driver will treat it the same as SLI3.
5127 **/
5128static void
5129lpfc_sli4_async_fc_evt(struct lpfc_hba *phba, struct lpfc_acqe_fc_la *acqe_fc)
5130{
5131 struct lpfc_dmabuf *mp;
5132 LPFC_MBOXQ_t *pmb;
7bdedb34
JS
5133 MAILBOX_t *mb;
5134 struct lpfc_mbx_read_top *la;
70f3c073
JS
5135 int rc;
5136
5137 if (bf_get(lpfc_trailer_type, acqe_fc) !=
5138 LPFC_FC_LA_EVENT_TYPE_FC_LINK) {
5139 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5140 "2895 Non FC link Event detected.(%d)\n",
5141 bf_get(lpfc_trailer_type, acqe_fc));
5142 return;
5143 }
1dc5ec24
JS
5144
5145 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
5146 LPFC_FC_LA_TYPE_TRUNKING_EVENT) {
5147 lpfc_update_trunk_link_status(phba, acqe_fc);
5148 return;
5149 }
5150
70f3c073
JS
5151 /* Keep the link status for extra SLI4 state machine reference */
5152 phba->sli4_hba.link_state.speed =
8b68cd52
JS
5153 lpfc_sli4_port_speed_parse(phba, LPFC_TRAILER_CODE_FC,
5154 bf_get(lpfc_acqe_fc_la_speed, acqe_fc));
70f3c073
JS
5155 phba->sli4_hba.link_state.duplex = LPFC_ASYNC_LINK_DUPLEX_FULL;
5156 phba->sli4_hba.link_state.topology =
5157 bf_get(lpfc_acqe_fc_la_topology, acqe_fc);
5158 phba->sli4_hba.link_state.status =
5159 bf_get(lpfc_acqe_fc_la_att_type, acqe_fc);
5160 phba->sli4_hba.link_state.type =
5161 bf_get(lpfc_acqe_fc_la_port_type, acqe_fc);
5162 phba->sli4_hba.link_state.number =
5163 bf_get(lpfc_acqe_fc_la_port_number, acqe_fc);
5164 phba->sli4_hba.link_state.fault =
5165 bf_get(lpfc_acqe_link_fault, acqe_fc);
b8e6f136
JS
5166
5167 if (bf_get(lpfc_acqe_fc_la_att_type, acqe_fc) ==
5168 LPFC_FC_LA_TYPE_LINK_DOWN)
5169 phba->sli4_hba.link_state.logical_speed = 0;
5170 else if (!phba->sli4_hba.conf_trunk)
5171 phba->sli4_hba.link_state.logical_speed =
8b68cd52 5172 bf_get(lpfc_acqe_fc_la_llink_spd, acqe_fc) * 10;
b8e6f136 5173
70f3c073
JS
5174 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5175 "2896 Async FC event - Speed:%dGBaud Topology:x%x "
5176 "LA Type:x%x Port Type:%d Port Number:%d Logical speed:"
5177 "%dMbps Fault:%d\n",
5178 phba->sli4_hba.link_state.speed,
5179 phba->sli4_hba.link_state.topology,
5180 phba->sli4_hba.link_state.status,
5181 phba->sli4_hba.link_state.type,
5182 phba->sli4_hba.link_state.number,
8b68cd52 5183 phba->sli4_hba.link_state.logical_speed,
70f3c073
JS
5184 phba->sli4_hba.link_state.fault);
5185 pmb = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
5186 if (!pmb) {
5187 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5188 "2897 The mboxq allocation failed\n");
5189 return;
5190 }
5191 mp = kmalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
5192 if (!mp) {
5193 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5194 "2898 The lpfc_dmabuf allocation failed\n");
5195 goto out_free_pmb;
5196 }
5197 mp->virt = lpfc_mbuf_alloc(phba, 0, &mp->phys);
5198 if (!mp->virt) {
5199 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5200 "2899 The mbuf allocation failed\n");
5201 goto out_free_dmabuf;
5202 }
5203
5204 /* Cleanup any outstanding ELS commands */
5205 lpfc_els_flush_all_cmd(phba);
5206
5207 /* Block ELS IOCBs until we have done process link event */
895427bd 5208 phba->sli4_hba.els_wq->pring->flag |= LPFC_STOP_IOCB_EVENT;
70f3c073
JS
5209
5210 /* Update link event statistics */
5211 phba->sli.slistat.link_event++;
5212
5213 /* Create lpfc_handle_latt mailbox command from link ACQE */
5214 lpfc_read_topology(phba, pmb, mp);
5215 pmb->mbox_cmpl = lpfc_mbx_cmpl_read_topology;
5216 pmb->vport = phba->pport;
5217
7bdedb34 5218 if (phba->sli4_hba.link_state.status != LPFC_FC_LA_TYPE_LINK_UP) {
ae9e28f3
JS
5219 phba->link_flag &= ~(LS_MDS_LINK_DOWN | LS_MDS_LOOPBACK);
5220
5221 switch (phba->sli4_hba.link_state.status) {
5222 case LPFC_FC_LA_TYPE_MDS_LINK_DOWN:
5223 phba->link_flag |= LS_MDS_LINK_DOWN;
5224 break;
5225 case LPFC_FC_LA_TYPE_MDS_LOOPBACK:
5226 phba->link_flag |= LS_MDS_LOOPBACK;
5227 break;
5228 default:
5229 break;
5230 }
5231
23288b78 5232 /* Initialize completion status */
7bdedb34 5233 mb = &pmb->u.mb;
23288b78
JS
5234 mb->mbxStatus = MBX_SUCCESS;
5235
5236 /* Parse port fault information field */
5237 lpfc_sli4_parse_latt_fault(phba, (void *)acqe_fc);
7bdedb34
JS
5238
5239 /* Parse and translate link attention fields */
5240 la = (struct lpfc_mbx_read_top *)&pmb->u.mb.un.varReadTop;
5241 la->eventTag = acqe_fc->event_tag;
7bdedb34 5242
aeb3c817
JS
5243 if (phba->sli4_hba.link_state.status ==
5244 LPFC_FC_LA_TYPE_UNEXP_WWPN) {
5245 bf_set(lpfc_mbx_read_top_att_type, la,
5246 LPFC_FC_LA_TYPE_UNEXP_WWPN);
5247 } else {
5248 bf_set(lpfc_mbx_read_top_att_type, la,
5249 LPFC_FC_LA_TYPE_LINK_DOWN);
5250 }
7bdedb34
JS
5251 /* Invoke the mailbox command callback function */
5252 lpfc_mbx_cmpl_read_topology(phba, pmb);
5253
5254 return;
5255 }
5256
70f3c073
JS
5257 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_NOWAIT);
5258 if (rc == MBX_NOT_FINISHED)
5259 goto out_free_dmabuf;
5260 return;
5261
5262out_free_dmabuf:
5263 kfree(mp);
5264out_free_pmb:
5265 mempool_free(pmb, phba->mbox_mem_pool);
5266}
5267
5268/**
5269 * lpfc_sli4_async_sli_evt - Process the asynchronous SLI link event
5270 * @phba: pointer to lpfc hba data structure.
5271 * @acqe_fc: pointer to the async SLI completion queue entry.
5272 *
5273 * This routine is to handle the SLI4 asynchronous SLI events.
5274 **/
5275static void
5276lpfc_sli4_async_sli_evt(struct lpfc_hba *phba, struct lpfc_acqe_sli *acqe_sli)
5277{
4b8bae08 5278 char port_name;
8c1312e1 5279 char message[128];
4b8bae08 5280 uint8_t status;
946727dc 5281 uint8_t evt_type;
448193b5 5282 uint8_t operational = 0;
946727dc 5283 struct temp_event temp_event_data;
4b8bae08 5284 struct lpfc_acqe_misconfigured_event *misconfigured;
946727dc 5285 struct Scsi_Host *shost;
cd71348a
JS
5286 struct lpfc_vport **vports;
5287 int rc, i;
946727dc
JS
5288
5289 evt_type = bf_get(lpfc_trailer_type, acqe_sli);
4b8bae08 5290
448193b5 5291 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
d11ed16d
JS
5292 "2901 Async SLI event - Type:%d, Event Data: x%08x "
5293 "x%08x x%08x x%08x\n", evt_type,
448193b5 5294 acqe_sli->event_data1, acqe_sli->event_data2,
d11ed16d 5295 acqe_sli->reserved, acqe_sli->trailer);
4b8bae08
JS
5296
5297 port_name = phba->Port[0];
5298 if (port_name == 0x00)
5299 port_name = '?'; /* get port name is empty */
5300
946727dc
JS
5301 switch (evt_type) {
5302 case LPFC_SLI_EVENT_TYPE_OVER_TEMP:
5303 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
5304 temp_event_data.event_code = LPFC_THRESHOLD_TEMP;
5305 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
5306
5307 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
5308 "3190 Over Temperature:%d Celsius- Port Name %c\n",
5309 acqe_sli->event_data1, port_name);
5310
310429ef 5311 phba->sfp_warning |= LPFC_TRANSGRESSION_HIGH_TEMPERATURE;
946727dc
JS
5312 shost = lpfc_shost_from_vport(phba->pport);
5313 fc_host_post_vendor_event(shost, fc_get_event_number(),
5314 sizeof(temp_event_data),
5315 (char *)&temp_event_data,
5316 SCSI_NL_VID_TYPE_PCI
5317 | PCI_VENDOR_ID_EMULEX);
5318 break;
5319 case LPFC_SLI_EVENT_TYPE_NORM_TEMP:
5320 temp_event_data.event_type = FC_REG_TEMPERATURE_EVENT;
5321 temp_event_data.event_code = LPFC_NORMAL_TEMP;
5322 temp_event_data.data = (uint32_t)acqe_sli->event_data1;
5323
5324 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5325 "3191 Normal Temperature:%d Celsius - Port Name %c\n",
5326 acqe_sli->event_data1, port_name);
5327
5328 shost = lpfc_shost_from_vport(phba->pport);
5329 fc_host_post_vendor_event(shost, fc_get_event_number(),
5330 sizeof(temp_event_data),
5331 (char *)&temp_event_data,
5332 SCSI_NL_VID_TYPE_PCI
5333 | PCI_VENDOR_ID_EMULEX);
5334 break;
5335 case LPFC_SLI_EVENT_TYPE_MISCONFIGURED:
5336 misconfigured = (struct lpfc_acqe_misconfigured_event *)
4b8bae08
JS
5337 &acqe_sli->event_data1;
5338
946727dc
JS
5339 /* fetch the status for this port */
5340 switch (phba->sli4_hba.lnk_info.lnk_no) {
5341 case LPFC_LINK_NUMBER_0:
448193b5
JS
5342 status = bf_get(lpfc_sli_misconfigured_port0_state,
5343 &misconfigured->theEvent);
5344 operational = bf_get(lpfc_sli_misconfigured_port0_op,
4b8bae08 5345 &misconfigured->theEvent);
946727dc
JS
5346 break;
5347 case LPFC_LINK_NUMBER_1:
448193b5
JS
5348 status = bf_get(lpfc_sli_misconfigured_port1_state,
5349 &misconfigured->theEvent);
5350 operational = bf_get(lpfc_sli_misconfigured_port1_op,
4b8bae08 5351 &misconfigured->theEvent);
946727dc
JS
5352 break;
5353 case LPFC_LINK_NUMBER_2:
448193b5
JS
5354 status = bf_get(lpfc_sli_misconfigured_port2_state,
5355 &misconfigured->theEvent);
5356 operational = bf_get(lpfc_sli_misconfigured_port2_op,
4b8bae08 5357 &misconfigured->theEvent);
946727dc
JS
5358 break;
5359 case LPFC_LINK_NUMBER_3:
448193b5
JS
5360 status = bf_get(lpfc_sli_misconfigured_port3_state,
5361 &misconfigured->theEvent);
5362 operational = bf_get(lpfc_sli_misconfigured_port3_op,
4b8bae08 5363 &misconfigured->theEvent);
946727dc
JS
5364 break;
5365 default:
448193b5
JS
5366 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5367 "3296 "
5368 "LPFC_SLI_EVENT_TYPE_MISCONFIGURED "
5369 "event: Invalid link %d",
5370 phba->sli4_hba.lnk_info.lnk_no);
5371 return;
946727dc 5372 }
4b8bae08 5373
448193b5
JS
5374 /* Skip if optic state unchanged */
5375 if (phba->sli4_hba.lnk_info.optic_state == status)
5376 return;
5377
946727dc
JS
5378 switch (status) {
5379 case LPFC_SLI_EVENT_STATUS_VALID:
448193b5
JS
5380 sprintf(message, "Physical Link is functional");
5381 break;
946727dc
JS
5382 case LPFC_SLI_EVENT_STATUS_NOT_PRESENT:
5383 sprintf(message, "Optics faulted/incorrectly "
5384 "installed/not installed - Reseat optics, "
5385 "if issue not resolved, replace.");
5386 break;
5387 case LPFC_SLI_EVENT_STATUS_WRONG_TYPE:
5388 sprintf(message,
5389 "Optics of two types installed - Remove one "
5390 "optic or install matching pair of optics.");
5391 break;
5392 case LPFC_SLI_EVENT_STATUS_UNSUPPORTED:
5393 sprintf(message, "Incompatible optics - Replace with "
292098be 5394 "compatible optics for card to function.");
946727dc 5395 break;
448193b5
JS
5396 case LPFC_SLI_EVENT_STATUS_UNQUALIFIED:
5397 sprintf(message, "Unqualified optics - Replace with "
5398 "Avago optics for Warranty and Technical "
5399 "Support - Link is%s operational",
2ea259ee 5400 (operational) ? " not" : "");
448193b5
JS
5401 break;
5402 case LPFC_SLI_EVENT_STATUS_UNCERTIFIED:
5403 sprintf(message, "Uncertified optics - Replace with "
5404 "Avago-certified optics to enable link "
5405 "operation - Link is%s operational",
2ea259ee 5406 (operational) ? " not" : "");
448193b5 5407 break;
946727dc
JS
5408 default:
5409 /* firmware is reporting a status we don't know about */
5410 sprintf(message, "Unknown event status x%02x", status);
5411 break;
5412 }
cd71348a
JS
5413
5414 /* Issue READ_CONFIG mbox command to refresh supported speeds */
5415 rc = lpfc_sli4_read_config(phba);
3952e91f 5416 if (rc) {
cd71348a
JS
5417 phba->lmt = 0;
5418 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5419 "3194 Unable to retrieve supported "
3952e91f 5420 "speeds, rc = 0x%x\n", rc);
cd71348a
JS
5421 }
5422 vports = lpfc_create_vport_work_array(phba);
5423 if (vports != NULL) {
5424 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5425 i++) {
5426 shost = lpfc_shost_from_vport(vports[i]);
5427 lpfc_host_supported_speeds_set(shost);
5428 }
5429 }
5430 lpfc_destroy_vport_work_array(phba, vports);
5431
448193b5 5432 phba->sli4_hba.lnk_info.optic_state = status;
946727dc 5433 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
448193b5 5434 "3176 Port Name %c %s\n", port_name, message);
946727dc
JS
5435 break;
5436 case LPFC_SLI_EVENT_TYPE_REMOTE_DPORT:
5437 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5438 "3192 Remote DPort Test Initiated - "
5439 "Event Data1:x%08x Event Data2: x%08x\n",
5440 acqe_sli->event_data1, acqe_sli->event_data2);
4b8bae08 5441 break;
d11ed16d
JS
5442 case LPFC_SLI_EVENT_TYPE_EEPROM_FAILURE:
5443 /* EEPROM failure. No driver action is required */
5444 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
5445 "2518 EEPROM failure - "
5446 "Event Data1: x%08x Event Data2: x%08x\n",
5447 acqe_sli->event_data1, acqe_sli->event_data2);
5448 break;
4b8bae08 5449 default:
946727dc 5450 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
d11ed16d 5451 "3193 Unrecognized SLI event, type: 0x%x",
946727dc 5452 evt_type);
4b8bae08
JS
5453 break;
5454 }
70f3c073
JS
5455}
5456
fc2b989b
JS
5457/**
5458 * lpfc_sli4_perform_vport_cvl - Perform clear virtual link on a vport
5459 * @vport: pointer to vport data structure.
5460 *
5461 * This routine is to perform Clear Virtual Link (CVL) on a vport in
5462 * response to a CVL event.
5463 *
5464 * Return the pointer to the ndlp with the vport if successful, otherwise
5465 * return NULL.
5466 **/
5467static struct lpfc_nodelist *
5468lpfc_sli4_perform_vport_cvl(struct lpfc_vport *vport)
5469{
5470 struct lpfc_nodelist *ndlp;
5471 struct Scsi_Host *shost;
5472 struct lpfc_hba *phba;
5473
5474 if (!vport)
5475 return NULL;
fc2b989b
JS
5476 phba = vport->phba;
5477 if (!phba)
5478 return NULL;
78730cfe
JS
5479 ndlp = lpfc_findnode_did(vport, Fabric_DID);
5480 if (!ndlp) {
5481 /* Cannot find existing Fabric ndlp, so allocate a new one */
9d3d340d 5482 ndlp = lpfc_nlp_init(vport, Fabric_DID);
78730cfe
JS
5483 if (!ndlp)
5484 return 0;
78730cfe
JS
5485 /* Set the node type */
5486 ndlp->nlp_type |= NLP_FABRIC;
5487 /* Put ndlp onto node list */
5488 lpfc_enqueue_node(vport, ndlp);
5489 } else if (!NLP_CHK_NODE_ACT(ndlp)) {
5490 /* re-setup ndlp without removing from node list */
5491 ndlp = lpfc_enable_node(vport, ndlp, NLP_STE_UNUSED_NODE);
5492 if (!ndlp)
5493 return 0;
5494 }
63e801ce
JS
5495 if ((phba->pport->port_state < LPFC_FLOGI) &&
5496 (phba->pport->port_state != LPFC_VPORT_FAILED))
fc2b989b
JS
5497 return NULL;
5498 /* If virtual link is not yet instantiated ignore CVL */
63e801ce
JS
5499 if ((vport != phba->pport) && (vport->port_state < LPFC_FDISC)
5500 && (vport->port_state != LPFC_VPORT_FAILED))
fc2b989b
JS
5501 return NULL;
5502 shost = lpfc_shost_from_vport(vport);
5503 if (!shost)
5504 return NULL;
5505 lpfc_linkdown_port(vport);
5506 lpfc_cleanup_pending_mbox(vport);
5507 spin_lock_irq(shost->host_lock);
5508 vport->fc_flag |= FC_VPORT_CVL_RCVD;
5509 spin_unlock_irq(shost->host_lock);
5510
5511 return ndlp;
5512}
5513
5514/**
5515 * lpfc_sli4_perform_all_vport_cvl - Perform clear virtual link on all vports
5516 * @vport: pointer to lpfc hba data structure.
5517 *
5518 * This routine is to perform Clear Virtual Link (CVL) on all vports in
5519 * response to a FCF dead event.
5520 **/
5521static void
5522lpfc_sli4_perform_all_vport_cvl(struct lpfc_hba *phba)
5523{
5524 struct lpfc_vport **vports;
5525 int i;
5526
5527 vports = lpfc_create_vport_work_array(phba);
5528 if (vports)
5529 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++)
5530 lpfc_sli4_perform_vport_cvl(vports[i]);
5531 lpfc_destroy_vport_work_array(phba, vports);
5532}
5533
da0436e9 5534/**
76a95d75 5535 * lpfc_sli4_async_fip_evt - Process the asynchronous FCoE FIP event
da0436e9
JS
5536 * @phba: pointer to lpfc hba data structure.
5537 * @acqe_link: pointer to the async fcoe completion queue entry.
5538 *
5539 * This routine is to handle the SLI4 asynchronous fcoe event.
5540 **/
5541static void
76a95d75 5542lpfc_sli4_async_fip_evt(struct lpfc_hba *phba,
70f3c073 5543 struct lpfc_acqe_fip *acqe_fip)
da0436e9 5544{
70f3c073 5545 uint8_t event_type = bf_get(lpfc_trailer_type, acqe_fip);
da0436e9 5546 int rc;
6669f9bb
JS
5547 struct lpfc_vport *vport;
5548 struct lpfc_nodelist *ndlp;
5549 struct Scsi_Host *shost;
695a814e
JS
5550 int active_vlink_present;
5551 struct lpfc_vport **vports;
5552 int i;
da0436e9 5553
70f3c073
JS
5554 phba->fc_eventTag = acqe_fip->event_tag;
5555 phba->fcoe_eventtag = acqe_fip->event_tag;
da0436e9 5556 switch (event_type) {
70f3c073
JS
5557 case LPFC_FIP_EVENT_TYPE_NEW_FCF:
5558 case LPFC_FIP_EVENT_TYPE_FCF_PARAM_MOD:
5559 if (event_type == LPFC_FIP_EVENT_TYPE_NEW_FCF)
999d813f
JS
5560 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
5561 LOG_DISCOVERY,
a93ff37a
JS
5562 "2546 New FCF event, evt_tag:x%x, "
5563 "index:x%x\n",
70f3c073
JS
5564 acqe_fip->event_tag,
5565 acqe_fip->index);
999d813f
JS
5566 else
5567 lpfc_printf_log(phba, KERN_WARNING, LOG_FIP |
5568 LOG_DISCOVERY,
a93ff37a
JS
5569 "2788 FCF param modified event, "
5570 "evt_tag:x%x, index:x%x\n",
70f3c073
JS
5571 acqe_fip->event_tag,
5572 acqe_fip->index);
38b92ef8 5573 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
0c9ab6f5
JS
5574 /*
5575 * During period of FCF discovery, read the FCF
5576 * table record indexed by the event to update
a93ff37a 5577 * FCF roundrobin failover eligible FCF bmask.
0c9ab6f5
JS
5578 */
5579 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5580 LOG_DISCOVERY,
a93ff37a
JS
5581 "2779 Read FCF (x%x) for updating "
5582 "roundrobin FCF failover bmask\n",
70f3c073
JS
5583 acqe_fip->index);
5584 rc = lpfc_sli4_read_fcf_rec(phba, acqe_fip->index);
0c9ab6f5 5585 }
38b92ef8
JS
5586
5587 /* If the FCF discovery is in progress, do nothing. */
3804dc84 5588 spin_lock_irq(&phba->hbalock);
a93ff37a 5589 if (phba->hba_flag & FCF_TS_INPROG) {
38b92ef8
JS
5590 spin_unlock_irq(&phba->hbalock);
5591 break;
5592 }
5593 /* If fast FCF failover rescan event is pending, do nothing */
036cad1f 5594 if (phba->fcf.fcf_flag & (FCF_REDISC_EVT | FCF_REDISC_PEND)) {
38b92ef8
JS
5595 spin_unlock_irq(&phba->hbalock);
5596 break;
5597 }
5598
c2b9712e
JS
5599 /* If the FCF has been in discovered state, do nothing. */
5600 if (phba->fcf.fcf_flag & FCF_SCAN_DONE) {
3804dc84
JS
5601 spin_unlock_irq(&phba->hbalock);
5602 break;
5603 }
5604 spin_unlock_irq(&phba->hbalock);
38b92ef8 5605
0c9ab6f5
JS
5606 /* Otherwise, scan the entire FCF table and re-discover SAN */
5607 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
a93ff37a
JS
5608 "2770 Start FCF table scan per async FCF "
5609 "event, evt_tag:x%x, index:x%x\n",
70f3c073 5610 acqe_fip->event_tag, acqe_fip->index);
0c9ab6f5
JS
5611 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba,
5612 LPFC_FCOE_FCF_GET_FIRST);
da0436e9 5613 if (rc)
0c9ab6f5
JS
5614 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
5615 "2547 Issue FCF scan read FCF mailbox "
a93ff37a 5616 "command failed (x%x)\n", rc);
da0436e9
JS
5617 break;
5618
70f3c073 5619 case LPFC_FIP_EVENT_TYPE_FCF_TABLE_FULL:
da0436e9 5620 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
e4e74273 5621 "2548 FCF Table full count 0x%x tag 0x%x\n",
70f3c073
JS
5622 bf_get(lpfc_acqe_fip_fcf_count, acqe_fip),
5623 acqe_fip->event_tag);
da0436e9
JS
5624 break;
5625
70f3c073 5626 case LPFC_FIP_EVENT_TYPE_FCF_DEAD:
80c17849 5627 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
0c9ab6f5 5628 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
a93ff37a 5629 "2549 FCF (x%x) disconnected from network, "
70f3c073 5630 "tag:x%x\n", acqe_fip->index, acqe_fip->event_tag);
38b92ef8
JS
5631 /*
5632 * If we are in the middle of FCF failover process, clear
5633 * the corresponding FCF bit in the roundrobin bitmap.
da0436e9 5634 */
fc2b989b 5635 spin_lock_irq(&phba->hbalock);
a1cadfef
JS
5636 if ((phba->fcf.fcf_flag & FCF_DISCOVERY) &&
5637 (phba->fcf.current_rec.fcf_indx != acqe_fip->index)) {
fc2b989b 5638 spin_unlock_irq(&phba->hbalock);
0c9ab6f5 5639 /* Update FLOGI FCF failover eligible FCF bmask */
70f3c073 5640 lpfc_sli4_fcf_rr_index_clear(phba, acqe_fip->index);
fc2b989b
JS
5641 break;
5642 }
38b92ef8
JS
5643 spin_unlock_irq(&phba->hbalock);
5644
5645 /* If the event is not for currently used fcf do nothing */
70f3c073 5646 if (phba->fcf.current_rec.fcf_indx != acqe_fip->index)
38b92ef8
JS
5647 break;
5648
5649 /*
5650 * Otherwise, request the port to rediscover the entire FCF
5651 * table for a fast recovery from case that the current FCF
5652 * is no longer valid as we are not in the middle of FCF
5653 * failover process already.
5654 */
c2b9712e
JS
5655 spin_lock_irq(&phba->hbalock);
5656 /* Mark the fast failover process in progress */
5657 phba->fcf.fcf_flag |= FCF_DEAD_DISC;
5658 spin_unlock_irq(&phba->hbalock);
5659
5660 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
5661 "2771 Start FCF fast failover process due to "
5662 "FCF DEAD event: evt_tag:x%x, fcf_index:x%x "
5663 "\n", acqe_fip->event_tag, acqe_fip->index);
5664 rc = lpfc_sli4_redisc_fcf_table(phba);
5665 if (rc) {
5666 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
5667 LOG_DISCOVERY,
7afc0ce9 5668 "2772 Issue FCF rediscover mailbox "
c2b9712e
JS
5669 "command failed, fail through to FCF "
5670 "dead event\n");
5671 spin_lock_irq(&phba->hbalock);
5672 phba->fcf.fcf_flag &= ~FCF_DEAD_DISC;
5673 spin_unlock_irq(&phba->hbalock);
5674 /*
5675 * Last resort will fail over by treating this
5676 * as a link down to FCF registration.
5677 */
5678 lpfc_sli4_fcf_dead_failthrough(phba);
5679 } else {
5680 /* Reset FCF roundrobin bmask for new discovery */
5681 lpfc_sli4_clear_fcf_rr_bmask(phba);
5682 /*
5683 * Handling fast FCF failover to a DEAD FCF event is
5684 * considered equalivant to receiving CVL to all vports.
5685 */
5686 lpfc_sli4_perform_all_vport_cvl(phba);
5687 }
da0436e9 5688 break;
70f3c073 5689 case LPFC_FIP_EVENT_TYPE_CVL:
80c17849 5690 phba->fcoe_cvl_eventtag = acqe_fip->event_tag;
0c9ab6f5 5691 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
6669f9bb 5692 "2718 Clear Virtual Link Received for VPI 0x%x"
70f3c073 5693 " tag 0x%x\n", acqe_fip->index, acqe_fip->event_tag);
6d368e53 5694
6669f9bb 5695 vport = lpfc_find_vport_by_vpid(phba,
5248a749 5696 acqe_fip->index);
fc2b989b 5697 ndlp = lpfc_sli4_perform_vport_cvl(vport);
6669f9bb
JS
5698 if (!ndlp)
5699 break;
695a814e
JS
5700 active_vlink_present = 0;
5701
5702 vports = lpfc_create_vport_work_array(phba);
5703 if (vports) {
5704 for (i = 0; i <= phba->max_vports && vports[i] != NULL;
5705 i++) {
5706 if ((!(vports[i]->fc_flag &
5707 FC_VPORT_CVL_RCVD)) &&
5708 (vports[i]->port_state > LPFC_FDISC)) {
5709 active_vlink_present = 1;
5710 break;
5711 }
5712 }
5713 lpfc_destroy_vport_work_array(phba, vports);
5714 }
5715
cc82355a
JS
5716 /*
5717 * Don't re-instantiate if vport is marked for deletion.
5718 * If we are here first then vport_delete is going to wait
5719 * for discovery to complete.
5720 */
5721 if (!(vport->load_flag & FC_UNLOADING) &&
5722 active_vlink_present) {
695a814e
JS
5723 /*
5724 * If there are other active VLinks present,
5725 * re-instantiate the Vlink using FDISC.
5726 */
256ec0d0
JS
5727 mod_timer(&ndlp->nlp_delayfunc,
5728 jiffies + msecs_to_jiffies(1000));
fc2b989b 5729 shost = lpfc_shost_from_vport(vport);
6669f9bb
JS
5730 spin_lock_irq(shost->host_lock);
5731 ndlp->nlp_flag |= NLP_DELAY_TMO;
5732 spin_unlock_irq(shost->host_lock);
695a814e
JS
5733 ndlp->nlp_last_elscmd = ELS_CMD_FDISC;
5734 vport->port_state = LPFC_FDISC;
5735 } else {
ecfd03c6
JS
5736 /*
5737 * Otherwise, we request port to rediscover
5738 * the entire FCF table for a fast recovery
5739 * from possible case that the current FCF
0c9ab6f5
JS
5740 * is no longer valid if we are not already
5741 * in the FCF failover process.
ecfd03c6 5742 */
fc2b989b 5743 spin_lock_irq(&phba->hbalock);
0c9ab6f5 5744 if (phba->fcf.fcf_flag & FCF_DISCOVERY) {
fc2b989b
JS
5745 spin_unlock_irq(&phba->hbalock);
5746 break;
5747 }
5748 /* Mark the fast failover process in progress */
0c9ab6f5 5749 phba->fcf.fcf_flag |= FCF_ACVL_DISC;
fc2b989b 5750 spin_unlock_irq(&phba->hbalock);
0c9ab6f5
JS
5751 lpfc_printf_log(phba, KERN_INFO, LOG_FIP |
5752 LOG_DISCOVERY,
a93ff37a 5753 "2773 Start FCF failover per CVL, "
70f3c073 5754 "evt_tag:x%x\n", acqe_fip->event_tag);
ecfd03c6 5755 rc = lpfc_sli4_redisc_fcf_table(phba);
fc2b989b 5756 if (rc) {
0c9ab6f5
JS
5757 lpfc_printf_log(phba, KERN_ERR, LOG_FIP |
5758 LOG_DISCOVERY,
5759 "2774 Issue FCF rediscover "
7afc0ce9 5760 "mailbox command failed, "
0c9ab6f5 5761 "through to CVL event\n");
fc2b989b 5762 spin_lock_irq(&phba->hbalock);
0c9ab6f5 5763 phba->fcf.fcf_flag &= ~FCF_ACVL_DISC;
fc2b989b 5764 spin_unlock_irq(&phba->hbalock);
ecfd03c6
JS
5765 /*
5766 * Last resort will be re-try on the
5767 * the current registered FCF entry.
5768 */
5769 lpfc_retry_pport_discovery(phba);
38b92ef8
JS
5770 } else
5771 /*
5772 * Reset FCF roundrobin bmask for new
5773 * discovery.
5774 */
7d791df7 5775 lpfc_sli4_clear_fcf_rr_bmask(phba);
6669f9bb
JS
5776 }
5777 break;
da0436e9
JS
5778 default:
5779 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5780 "0288 Unknown FCoE event type 0x%x event tag "
70f3c073 5781 "0x%x\n", event_type, acqe_fip->event_tag);
da0436e9
JS
5782 break;
5783 }
5784}
5785
5786/**
5787 * lpfc_sli4_async_dcbx_evt - Process the asynchronous dcbx event
5788 * @phba: pointer to lpfc hba data structure.
5789 * @acqe_link: pointer to the async dcbx completion queue entry.
5790 *
5791 * This routine is to handle the SLI4 asynchronous dcbx event.
5792 **/
5793static void
5794lpfc_sli4_async_dcbx_evt(struct lpfc_hba *phba,
5795 struct lpfc_acqe_dcbx *acqe_dcbx)
5796{
4d9ab994 5797 phba->fc_eventTag = acqe_dcbx->event_tag;
da0436e9
JS
5798 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5799 "0290 The SLI4 DCBX asynchronous event is not "
5800 "handled yet\n");
5801}
5802
b19a061a
JS
5803/**
5804 * lpfc_sli4_async_grp5_evt - Process the asynchronous group5 event
5805 * @phba: pointer to lpfc hba data structure.
5806 * @acqe_link: pointer to the async grp5 completion queue entry.
5807 *
5808 * This routine is to handle the SLI4 asynchronous grp5 event. A grp5 event
5809 * is an asynchronous notified of a logical link speed change. The Port
5810 * reports the logical link speed in units of 10Mbps.
5811 **/
5812static void
5813lpfc_sli4_async_grp5_evt(struct lpfc_hba *phba,
5814 struct lpfc_acqe_grp5 *acqe_grp5)
5815{
5816 uint16_t prev_ll_spd;
5817
5818 phba->fc_eventTag = acqe_grp5->event_tag;
5819 phba->fcoe_eventtag = acqe_grp5->event_tag;
5820 prev_ll_spd = phba->sli4_hba.link_state.logical_speed;
5821 phba->sli4_hba.link_state.logical_speed =
8b68cd52 5822 (bf_get(lpfc_acqe_grp5_llink_spd, acqe_grp5)) * 10;
b19a061a
JS
5823 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
5824 "2789 GRP5 Async Event: Updating logical link speed "
8b68cd52
JS
5825 "from %dMbps to %dMbps\n", prev_ll_spd,
5826 phba->sli4_hba.link_state.logical_speed);
b19a061a
JS
5827}
5828
da0436e9
JS
5829/**
5830 * lpfc_sli4_async_event_proc - Process all the pending asynchronous event
5831 * @phba: pointer to lpfc hba data structure.
5832 *
5833 * This routine is invoked by the worker thread to process all the pending
5834 * SLI4 asynchronous events.
5835 **/
5836void lpfc_sli4_async_event_proc(struct lpfc_hba *phba)
5837{
5838 struct lpfc_cq_event *cq_event;
5839
5840 /* First, declare the async event has been handled */
5841 spin_lock_irq(&phba->hbalock);
5842 phba->hba_flag &= ~ASYNC_EVENT;
5843 spin_unlock_irq(&phba->hbalock);
5844 /* Now, handle all the async events */
5845 while (!list_empty(&phba->sli4_hba.sp_asynce_work_queue)) {
5846 /* Get the first event from the head of the event queue */
5847 spin_lock_irq(&phba->hbalock);
5848 list_remove_head(&phba->sli4_hba.sp_asynce_work_queue,
5849 cq_event, struct lpfc_cq_event, list);
5850 spin_unlock_irq(&phba->hbalock);
5851 /* Process the asynchronous event */
5852 switch (bf_get(lpfc_trailer_code, &cq_event->cqe.mcqe_cmpl)) {
5853 case LPFC_TRAILER_CODE_LINK:
5854 lpfc_sli4_async_link_evt(phba,
5855 &cq_event->cqe.acqe_link);
5856 break;
5857 case LPFC_TRAILER_CODE_FCOE:
70f3c073 5858 lpfc_sli4_async_fip_evt(phba, &cq_event->cqe.acqe_fip);
da0436e9
JS
5859 break;
5860 case LPFC_TRAILER_CODE_DCBX:
5861 lpfc_sli4_async_dcbx_evt(phba,
5862 &cq_event->cqe.acqe_dcbx);
5863 break;
b19a061a
JS
5864 case LPFC_TRAILER_CODE_GRP5:
5865 lpfc_sli4_async_grp5_evt(phba,
5866 &cq_event->cqe.acqe_grp5);
5867 break;
70f3c073
JS
5868 case LPFC_TRAILER_CODE_FC:
5869 lpfc_sli4_async_fc_evt(phba, &cq_event->cqe.acqe_fc);
5870 break;
5871 case LPFC_TRAILER_CODE_SLI:
5872 lpfc_sli4_async_sli_evt(phba, &cq_event->cqe.acqe_sli);
5873 break;
da0436e9
JS
5874 default:
5875 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
5876 "1804 Invalid asynchrous event code: "
5877 "x%x\n", bf_get(lpfc_trailer_code,
5878 &cq_event->cqe.mcqe_cmpl));
5879 break;
5880 }
5881 /* Free the completion event processed to the free pool */
5882 lpfc_sli4_cq_event_release(phba, cq_event);
5883 }
5884}
5885
ecfd03c6
JS
5886/**
5887 * lpfc_sli4_fcf_redisc_event_proc - Process fcf table rediscovery event
5888 * @phba: pointer to lpfc hba data structure.
5889 *
5890 * This routine is invoked by the worker thread to process FCF table
5891 * rediscovery pending completion event.
5892 **/
5893void lpfc_sli4_fcf_redisc_event_proc(struct lpfc_hba *phba)
5894{
5895 int rc;
5896
5897 spin_lock_irq(&phba->hbalock);
5898 /* Clear FCF rediscovery timeout event */
5899 phba->fcf.fcf_flag &= ~FCF_REDISC_EVT;
5900 /* Clear driver fast failover FCF record flag */
5901 phba->fcf.failover_rec.flag = 0;
5902 /* Set state for FCF fast failover */
5903 phba->fcf.fcf_flag |= FCF_REDISC_FOV;
5904 spin_unlock_irq(&phba->hbalock);
5905
5906 /* Scan FCF table from the first entry to re-discover SAN */
0c9ab6f5 5907 lpfc_printf_log(phba, KERN_INFO, LOG_FIP | LOG_DISCOVERY,
a93ff37a 5908 "2777 Start post-quiescent FCF table scan\n");
0c9ab6f5 5909 rc = lpfc_sli4_fcf_scan_read_fcf_rec(phba, LPFC_FCOE_FCF_GET_FIRST);
ecfd03c6 5910 if (rc)
0c9ab6f5
JS
5911 lpfc_printf_log(phba, KERN_ERR, LOG_FIP | LOG_DISCOVERY,
5912 "2747 Issue FCF scan read FCF mailbox "
5913 "command failed 0x%x\n", rc);
ecfd03c6
JS
5914}
5915
da0436e9
JS
5916/**
5917 * lpfc_api_table_setup - Set up per hba pci-device group func api jump table
5918 * @phba: pointer to lpfc hba data structure.
5919 * @dev_grp: The HBA PCI-Device group number.
5920 *
5921 * This routine is invoked to set up the per HBA PCI-Device group function
5922 * API jump table entries.
5923 *
5924 * Return: 0 if success, otherwise -ENODEV
5925 **/
5926int
5927lpfc_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
5928{
5929 int rc;
5930
5931 /* Set up lpfc PCI-device group */
5932 phba->pci_dev_grp = dev_grp;
5933
5934 /* The LPFC_PCI_DEV_OC uses SLI4 */
5935 if (dev_grp == LPFC_PCI_DEV_OC)
5936 phba->sli_rev = LPFC_SLI_REV4;
5937
5938 /* Set up device INIT API function jump table */
5939 rc = lpfc_init_api_table_setup(phba, dev_grp);
5940 if (rc)
5941 return -ENODEV;
5942 /* Set up SCSI API function jump table */
5943 rc = lpfc_scsi_api_table_setup(phba, dev_grp);
5944 if (rc)
5945 return -ENODEV;
5946 /* Set up SLI API function jump table */
5947 rc = lpfc_sli_api_table_setup(phba, dev_grp);
5948 if (rc)
5949 return -ENODEV;
5950 /* Set up MBOX API function jump table */
5951 rc = lpfc_mbox_api_table_setup(phba, dev_grp);
5952 if (rc)
5953 return -ENODEV;
5954
5955 return 0;
5b75da2f
JS
5956}
5957
5958/**
3621a710 5959 * lpfc_log_intr_mode - Log the active interrupt mode
5b75da2f
JS
5960 * @phba: pointer to lpfc hba data structure.
5961 * @intr_mode: active interrupt mode adopted.
5962 *
5963 * This routine it invoked to log the currently used active interrupt mode
5964 * to the device.
3772a991
JS
5965 **/
5966static void lpfc_log_intr_mode(struct lpfc_hba *phba, uint32_t intr_mode)
5b75da2f
JS
5967{
5968 switch (intr_mode) {
5969 case 0:
5970 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5971 "0470 Enable INTx interrupt mode.\n");
5972 break;
5973 case 1:
5974 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5975 "0481 Enabled MSI interrupt mode.\n");
5976 break;
5977 case 2:
5978 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
5979 "0480 Enabled MSI-X interrupt mode.\n");
5980 break;
5981 default:
5982 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5983 "0482 Illegal interrupt mode.\n");
5984 break;
5985 }
5986 return;
5987}
5988
5b75da2f 5989/**
3772a991 5990 * lpfc_enable_pci_dev - Enable a generic PCI device.
5b75da2f
JS
5991 * @phba: pointer to lpfc hba data structure.
5992 *
3772a991
JS
5993 * This routine is invoked to enable the PCI device that is common to all
5994 * PCI devices.
5b75da2f
JS
5995 *
5996 * Return codes
af901ca1 5997 * 0 - successful
3772a991 5998 * other values - error
5b75da2f 5999 **/
3772a991
JS
6000static int
6001lpfc_enable_pci_dev(struct lpfc_hba *phba)
5b75da2f 6002{
3772a991 6003 struct pci_dev *pdev;
5b75da2f 6004
3772a991
JS
6005 /* Obtain PCI device reference */
6006 if (!phba->pcidev)
6007 goto out_error;
6008 else
6009 pdev = phba->pcidev;
3772a991
JS
6010 /* Enable PCI device */
6011 if (pci_enable_device_mem(pdev))
6012 goto out_error;
6013 /* Request PCI resource for the device */
e0c0483c 6014 if (pci_request_mem_regions(pdev, LPFC_DRIVER_NAME))
3772a991
JS
6015 goto out_disable_device;
6016 /* Set up device as PCI master and save state for EEH */
6017 pci_set_master(pdev);
6018 pci_try_set_mwi(pdev);
6019 pci_save_state(pdev);
5b75da2f 6020
0558056c 6021 /* PCIe EEH recovery on powerpc platforms needs fundamental reset */
453193e0 6022 if (pci_is_pcie(pdev))
0558056c
JS
6023 pdev->needs_freset = 1;
6024
3772a991 6025 return 0;
5b75da2f 6026
3772a991
JS
6027out_disable_device:
6028 pci_disable_device(pdev);
6029out_error:
079b5c91 6030 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
e0c0483c 6031 "1401 Failed to enable pci device\n");
3772a991 6032 return -ENODEV;
5b75da2f
JS
6033}
6034
6035/**
3772a991 6036 * lpfc_disable_pci_dev - Disable a generic PCI device.
5b75da2f
JS
6037 * @phba: pointer to lpfc hba data structure.
6038 *
3772a991
JS
6039 * This routine is invoked to disable the PCI device that is common to all
6040 * PCI devices.
5b75da2f
JS
6041 **/
6042static void
3772a991 6043lpfc_disable_pci_dev(struct lpfc_hba *phba)
5b75da2f 6044{
3772a991 6045 struct pci_dev *pdev;
5b75da2f 6046
3772a991
JS
6047 /* Obtain PCI device reference */
6048 if (!phba->pcidev)
6049 return;
6050 else
6051 pdev = phba->pcidev;
3772a991 6052 /* Release PCI resource and disable PCI device */
e0c0483c 6053 pci_release_mem_regions(pdev);
3772a991 6054 pci_disable_device(pdev);
5b75da2f
JS
6055
6056 return;
6057}
6058
e59058c4 6059/**
3772a991
JS
6060 * lpfc_reset_hba - Reset a hba
6061 * @phba: pointer to lpfc hba data structure.
e59058c4 6062 *
3772a991
JS
6063 * This routine is invoked to reset a hba device. It brings the HBA
6064 * offline, performs a board restart, and then brings the board back
6065 * online. The lpfc_offline calls lpfc_sli_hba_down which will clean up
6066 * on outstanding mailbox commands.
e59058c4 6067 **/
3772a991
JS
6068void
6069lpfc_reset_hba(struct lpfc_hba *phba)
dea3101e 6070{
3772a991
JS
6071 /* If resets are disabled then set error state and return. */
6072 if (!phba->cfg_enable_hba_reset) {
6073 phba->link_state = LPFC_HBA_ERROR;
6074 return;
6075 }
ee62021a
JS
6076 if (phba->sli.sli_flag & LPFC_SLI_ACTIVE)
6077 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
6078 else
6079 lpfc_offline_prep(phba, LPFC_MBX_NO_WAIT);
3772a991
JS
6080 lpfc_offline(phba);
6081 lpfc_sli_brdrestart(phba);
6082 lpfc_online(phba);
6083 lpfc_unblock_mgmt_io(phba);
6084}
dea3101e 6085
0a96e975
JS
6086/**
6087 * lpfc_sli_sriov_nr_virtfn_get - Get the number of sr-iov virtual functions
6088 * @phba: pointer to lpfc hba data structure.
6089 *
6090 * This function enables the PCI SR-IOV virtual functions to a physical
6091 * function. It invokes the PCI SR-IOV api with the @nr_vfn provided to
6092 * enable the number of virtual functions to the physical function. As
6093 * not all devices support SR-IOV, the return code from the pci_enable_sriov()
6094 * API call does not considered as an error condition for most of the device.
6095 **/
6096uint16_t
6097lpfc_sli_sriov_nr_virtfn_get(struct lpfc_hba *phba)
6098{
6099 struct pci_dev *pdev = phba->pcidev;
6100 uint16_t nr_virtfn;
6101 int pos;
6102
0a96e975
JS
6103 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
6104 if (pos == 0)
6105 return 0;
6106
6107 pci_read_config_word(pdev, pos + PCI_SRIOV_TOTAL_VF, &nr_virtfn);
6108 return nr_virtfn;
6109}
6110
912e3acd
JS
6111/**
6112 * lpfc_sli_probe_sriov_nr_virtfn - Enable a number of sr-iov virtual functions
6113 * @phba: pointer to lpfc hba data structure.
6114 * @nr_vfn: number of virtual functions to be enabled.
6115 *
6116 * This function enables the PCI SR-IOV virtual functions to a physical
6117 * function. It invokes the PCI SR-IOV api with the @nr_vfn provided to
6118 * enable the number of virtual functions to the physical function. As
6119 * not all devices support SR-IOV, the return code from the pci_enable_sriov()
6120 * API call does not considered as an error condition for most of the device.
6121 **/
6122int
6123lpfc_sli_probe_sriov_nr_virtfn(struct lpfc_hba *phba, int nr_vfn)
6124{
6125 struct pci_dev *pdev = phba->pcidev;
0a96e975 6126 uint16_t max_nr_vfn;
912e3acd
JS
6127 int rc;
6128
0a96e975
JS
6129 max_nr_vfn = lpfc_sli_sriov_nr_virtfn_get(phba);
6130 if (nr_vfn > max_nr_vfn) {
6131 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6132 "3057 Requested vfs (%d) greater than "
6133 "supported vfs (%d)", nr_vfn, max_nr_vfn);
6134 return -EINVAL;
6135 }
6136
912e3acd
JS
6137 rc = pci_enable_sriov(pdev, nr_vfn);
6138 if (rc) {
6139 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6140 "2806 Failed to enable sriov on this device "
6141 "with vfn number nr_vf:%d, rc:%d\n",
6142 nr_vfn, rc);
6143 } else
6144 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6145 "2807 Successful enable sriov on this device "
6146 "with vfn number nr_vf:%d\n", nr_vfn);
6147 return rc;
6148}
6149
3772a991 6150/**
895427bd 6151 * lpfc_setup_driver_resource_phase1 - Phase1 etup driver internal resources.
3772a991
JS
6152 * @phba: pointer to lpfc hba data structure.
6153 *
895427bd
JS
6154 * This routine is invoked to set up the driver internal resources before the
6155 * device specific resource setup to support the HBA device it attached to.
3772a991
JS
6156 *
6157 * Return codes
895427bd
JS
6158 * 0 - successful
6159 * other values - error
3772a991
JS
6160 **/
6161static int
895427bd 6162lpfc_setup_driver_resource_phase1(struct lpfc_hba *phba)
3772a991 6163{
895427bd 6164 struct lpfc_sli *psli = &phba->sli;
dea3101e 6165
2e0fef85 6166 /*
895427bd 6167 * Driver resources common to all SLI revisions
2e0fef85 6168 */
895427bd
JS
6169 atomic_set(&phba->fast_event_count, 0);
6170 spin_lock_init(&phba->hbalock);
dea3101e 6171
895427bd
JS
6172 /* Initialize ndlp management spinlock */
6173 spin_lock_init(&phba->ndlp_lock);
6174
523128e5
JS
6175 /* Initialize port_list spinlock */
6176 spin_lock_init(&phba->port_list_lock);
895427bd 6177 INIT_LIST_HEAD(&phba->port_list);
523128e5 6178
895427bd
JS
6179 INIT_LIST_HEAD(&phba->work_list);
6180 init_waitqueue_head(&phba->wait_4_mlo_m_q);
6181
6182 /* Initialize the wait queue head for the kernel thread */
6183 init_waitqueue_head(&phba->work_waitq);
6184
6185 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
f358dd0c 6186 "1403 Protocols supported %s %s %s\n",
895427bd
JS
6187 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) ?
6188 "SCSI" : " "),
6189 ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) ?
f358dd0c
JS
6190 "NVME" : " "),
6191 (phba->nvmet_support ? "NVMET" : " "));
895427bd 6192
0794d601
JS
6193 /* Initialize the IO buffer list used by driver for SLI3 SCSI */
6194 spin_lock_init(&phba->scsi_buf_list_get_lock);
6195 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_get);
6196 spin_lock_init(&phba->scsi_buf_list_put_lock);
6197 INIT_LIST_HEAD(&phba->lpfc_scsi_buf_list_put);
895427bd
JS
6198
6199 /* Initialize the fabric iocb list */
6200 INIT_LIST_HEAD(&phba->fabric_iocb_list);
6201
6202 /* Initialize list to save ELS buffers */
6203 INIT_LIST_HEAD(&phba->elsbuf);
6204
6205 /* Initialize FCF connection rec list */
6206 INIT_LIST_HEAD(&phba->fcf_conn_rec_list);
6207
6208 /* Initialize OAS configuration list */
6209 spin_lock_init(&phba->devicelock);
6210 INIT_LIST_HEAD(&phba->luns);
858c9f6c 6211
3772a991 6212 /* MBOX heartbeat timer */
f22eb4d3 6213 timer_setup(&psli->mbox_tmo, lpfc_mbox_timeout, 0);
3772a991 6214 /* Fabric block timer */
f22eb4d3 6215 timer_setup(&phba->fabric_block_timer, lpfc_fabric_block_timeout, 0);
3772a991 6216 /* EA polling mode timer */
f22eb4d3 6217 timer_setup(&phba->eratt_poll, lpfc_poll_eratt, 0);
895427bd 6218 /* Heartbeat timer */
f22eb4d3 6219 timer_setup(&phba->hb_tmofunc, lpfc_hb_timeout, 0);
895427bd 6220
32517fc0
JS
6221 INIT_DELAYED_WORK(&phba->eq_delay_work, lpfc_hb_eq_delay_work);
6222
895427bd
JS
6223 return 0;
6224}
6225
6226/**
6227 * lpfc_sli_driver_resource_setup - Setup driver internal resources for SLI3 dev
6228 * @phba: pointer to lpfc hba data structure.
6229 *
6230 * This routine is invoked to set up the driver internal resources specific to
6231 * support the SLI-3 HBA device it attached to.
6232 *
6233 * Return codes
6234 * 0 - successful
6235 * other values - error
6236 **/
6237static int
6238lpfc_sli_driver_resource_setup(struct lpfc_hba *phba)
6239{
0794d601 6240 int rc, entry_sz;
895427bd
JS
6241
6242 /*
6243 * Initialize timers used by driver
6244 */
6245
6246 /* FCP polling mode timer */
f22eb4d3 6247 timer_setup(&phba->fcp_poll_timer, lpfc_poll_timeout, 0);
dea3101e 6248
3772a991
JS
6249 /* Host attention work mask setup */
6250 phba->work_ha_mask = (HA_ERATT | HA_MBATT | HA_LATT);
6251 phba->work_ha_mask |= (HA_RXMASK << (LPFC_ELS_RING * 4));
dea3101e 6252
3772a991
JS
6253 /* Get all the module params for configuring this host */
6254 lpfc_get_cfgparam(phba);
895427bd
JS
6255 /* Set up phase-1 common device driver resources */
6256
6257 rc = lpfc_setup_driver_resource_phase1(phba);
6258 if (rc)
6259 return -ENODEV;
6260
49198b37
JS
6261 if (phba->pcidev->device == PCI_DEVICE_ID_HORNET) {
6262 phba->menlo_flag |= HBA_MENLO_SUPPORT;
6263 /* check for menlo minimum sg count */
6264 if (phba->cfg_sg_seg_cnt < LPFC_DEFAULT_MENLO_SG_SEG_CNT)
6265 phba->cfg_sg_seg_cnt = LPFC_DEFAULT_MENLO_SG_SEG_CNT;
6266 }
6267
895427bd 6268 if (!phba->sli.sli3_ring)
6396bb22
KC
6269 phba->sli.sli3_ring = kcalloc(LPFC_SLI3_MAX_RING,
6270 sizeof(struct lpfc_sli_ring),
6271 GFP_KERNEL);
895427bd 6272 if (!phba->sli.sli3_ring)
2a76a283
JS
6273 return -ENOMEM;
6274
dea3101e 6275 /*
96f7077f 6276 * Since lpfc_sg_seg_cnt is module parameter, the sg_dma_buf_size
3772a991 6277 * used to create the sg_dma_buf_pool must be dynamically calculated.
dea3101e 6278 */
3772a991 6279
96f7077f
JS
6280 /* Initialize the host templates the configured values. */
6281 lpfc_vport_template.sg_tablesize = phba->cfg_sg_seg_cnt;
96418b5e
JS
6282 lpfc_template_no_hr.sg_tablesize = phba->cfg_sg_seg_cnt;
6283 lpfc_template.sg_tablesize = phba->cfg_sg_seg_cnt;
96f7077f 6284
0794d601
JS
6285 if (phba->sli_rev == LPFC_SLI_REV4)
6286 entry_sz = sizeof(struct sli4_sge);
6287 else
6288 entry_sz = sizeof(struct ulp_bde64);
6289
96f7077f 6290 /* There are going to be 2 reserved BDEs: 1 FCP cmnd + 1 FCP rsp */
3772a991 6291 if (phba->cfg_enable_bg) {
96f7077f
JS
6292 /*
6293 * The scsi_buf for a T10-DIF I/O will hold the FCP cmnd,
6294 * the FCP rsp, and a BDE for each. Sice we have no control
6295 * over how many protection data segments the SCSI Layer
6296 * will hand us (ie: there could be one for every block
6297 * in the IO), we just allocate enough BDEs to accomidate
6298 * our max amount and we need to limit lpfc_sg_seg_cnt to
6299 * minimize the risk of running out.
6300 */
6301 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6302 sizeof(struct fcp_rsp) +
0794d601 6303 (LPFC_MAX_SG_SEG_CNT * entry_sz);
96f7077f
JS
6304
6305 if (phba->cfg_sg_seg_cnt > LPFC_MAX_SG_SEG_CNT_DIF)
6306 phba->cfg_sg_seg_cnt = LPFC_MAX_SG_SEG_CNT_DIF;
6307
6308 /* Total BDEs in BPL for scsi_sg_list and scsi_sg_prot_list */
6309 phba->cfg_total_seg_cnt = LPFC_MAX_SG_SEG_CNT;
6310 } else {
6311 /*
6312 * The scsi_buf for a regular I/O will hold the FCP cmnd,
6313 * the FCP rsp, a BDE for each, and a BDE for up to
6314 * cfg_sg_seg_cnt data segments.
6315 */
6316 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6317 sizeof(struct fcp_rsp) +
0794d601 6318 ((phba->cfg_sg_seg_cnt + 2) * entry_sz);
96f7077f
JS
6319
6320 /* Total BDEs in BPL for scsi_sg_list */
6321 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + 2;
901a920f 6322 }
dea3101e 6323
96f7077f
JS
6324 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
6325 "9088 sg_tablesize:%d dmabuf_size:%d total_bde:%d\n",
6326 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
6327 phba->cfg_total_seg_cnt);
dea3101e 6328
3772a991
JS
6329 phba->max_vpi = LPFC_MAX_VPI;
6330 /* This will be set to correct value after config_port mbox */
6331 phba->max_vports = 0;
dea3101e 6332
3772a991
JS
6333 /*
6334 * Initialize the SLI Layer to run with lpfc HBAs.
6335 */
6336 lpfc_sli_setup(phba);
895427bd 6337 lpfc_sli_queue_init(phba);
ed957684 6338
3772a991
JS
6339 /* Allocate device driver memory */
6340 if (lpfc_mem_alloc(phba, BPL_ALIGN_SZ))
6341 return -ENOMEM;
51ef4c26 6342
d79c9e9d
JS
6343 phba->lpfc_sg_dma_buf_pool =
6344 dma_pool_create("lpfc_sg_dma_buf_pool",
6345 &phba->pcidev->dev, phba->cfg_sg_dma_buf_size,
6346 BPL_ALIGN_SZ, 0);
6347
6348 if (!phba->lpfc_sg_dma_buf_pool)
6349 goto fail_free_mem;
6350
6351 phba->lpfc_cmd_rsp_buf_pool =
6352 dma_pool_create("lpfc_cmd_rsp_buf_pool",
6353 &phba->pcidev->dev,
6354 sizeof(struct fcp_cmnd) +
6355 sizeof(struct fcp_rsp),
6356 BPL_ALIGN_SZ, 0);
6357
6358 if (!phba->lpfc_cmd_rsp_buf_pool)
6359 goto fail_free_dma_buf_pool;
6360
912e3acd
JS
6361 /*
6362 * Enable sr-iov virtual functions if supported and configured
6363 * through the module parameter.
6364 */
6365 if (phba->cfg_sriov_nr_virtfn > 0) {
6366 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
6367 phba->cfg_sriov_nr_virtfn);
6368 if (rc) {
6369 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6370 "2808 Requested number of SR-IOV "
6371 "virtual functions (%d) is not "
6372 "supported\n",
6373 phba->cfg_sriov_nr_virtfn);
6374 phba->cfg_sriov_nr_virtfn = 0;
6375 }
6376 }
6377
3772a991 6378 return 0;
d79c9e9d
JS
6379
6380fail_free_dma_buf_pool:
6381 dma_pool_destroy(phba->lpfc_sg_dma_buf_pool);
6382 phba->lpfc_sg_dma_buf_pool = NULL;
6383fail_free_mem:
6384 lpfc_mem_free(phba);
6385 return -ENOMEM;
3772a991 6386}
ed957684 6387
3772a991
JS
6388/**
6389 * lpfc_sli_driver_resource_unset - Unset drvr internal resources for SLI3 dev
6390 * @phba: pointer to lpfc hba data structure.
6391 *
6392 * This routine is invoked to unset the driver internal resources set up
6393 * specific for supporting the SLI-3 HBA device it attached to.
6394 **/
6395static void
6396lpfc_sli_driver_resource_unset(struct lpfc_hba *phba)
6397{
6398 /* Free device driver memory allocated */
6399 lpfc_mem_free_all(phba);
3163f725 6400
3772a991
JS
6401 return;
6402}
dea3101e 6403
3772a991 6404/**
da0436e9 6405 * lpfc_sli4_driver_resource_setup - Setup drvr internal resources for SLI4 dev
3772a991
JS
6406 * @phba: pointer to lpfc hba data structure.
6407 *
da0436e9
JS
6408 * This routine is invoked to set up the driver internal resources specific to
6409 * support the SLI-4 HBA device it attached to.
3772a991
JS
6410 *
6411 * Return codes
af901ca1 6412 * 0 - successful
da0436e9 6413 * other values - error
3772a991
JS
6414 **/
6415static int
da0436e9 6416lpfc_sli4_driver_resource_setup(struct lpfc_hba *phba)
3772a991 6417{
28baac74 6418 LPFC_MBOXQ_t *mboxq;
f358dd0c 6419 MAILBOX_t *mb;
895427bd 6420 int rc, i, max_buf_size;
28baac74
JS
6421 uint8_t pn_page[LPFC_MAX_SUPPORTED_PAGES] = {0};
6422 struct lpfc_mqe *mqe;
09294d46 6423 int longs;
81e6a637 6424 int extra;
f358dd0c 6425 uint64_t wwn;
b92dc72d
JS
6426 u32 if_type;
6427 u32 if_fam;
da0436e9 6428
895427bd 6429 phba->sli4_hba.num_present_cpu = lpfc_present_cpu;
222e9239 6430 phba->sli4_hba.num_possible_cpu = num_possible_cpus();
895427bd
JS
6431 phba->sli4_hba.curr_disp_cpu = 0;
6432
716d3bc5
JS
6433 /* Get all the module params for configuring this host */
6434 lpfc_get_cfgparam(phba);
6435
895427bd
JS
6436 /* Set up phase-1 common device driver resources */
6437 rc = lpfc_setup_driver_resource_phase1(phba);
6438 if (rc)
6439 return -ENODEV;
6440
da0436e9
JS
6441 /* Before proceed, wait for POST done and device ready */
6442 rc = lpfc_sli4_post_status_check(phba);
6443 if (rc)
6444 return -ENODEV;
6445
3cee98db
JS
6446 /* Allocate all driver workqueues here */
6447
6448 /* The lpfc_wq workqueue for deferred irq use */
6449 phba->wq = alloc_workqueue("lpfc_wq", WQ_MEM_RECLAIM, 0);
6450
3772a991 6451 /*
da0436e9 6452 * Initialize timers used by driver
3772a991 6453 */
3772a991 6454
f22eb4d3 6455 timer_setup(&phba->rrq_tmr, lpfc_rrq_timeout, 0);
3772a991 6456
ecfd03c6 6457 /* FCF rediscover timer */
f22eb4d3 6458 timer_setup(&phba->fcf.redisc_wait, lpfc_sli4_fcf_redisc_wait_tmo, 0);
ecfd03c6 6459
7ad20aa9
JS
6460 /*
6461 * Control structure for handling external multi-buffer mailbox
6462 * command pass-through.
6463 */
6464 memset((uint8_t *)&phba->mbox_ext_buf_ctx, 0,
6465 sizeof(struct lpfc_mbox_ext_buf_ctx));
6466 INIT_LIST_HEAD(&phba->mbox_ext_buf_ctx.ext_dmabuf_list);
6467
da0436e9 6468 phba->max_vpi = LPFC_MAX_VPI;
67d12733 6469
da0436e9
JS
6470 /* This will be set to correct value after the read_config mbox */
6471 phba->max_vports = 0;
3772a991 6472
da0436e9
JS
6473 /* Program the default value of vlan_id and fc_map */
6474 phba->valid_vlan = 0;
6475 phba->fc_map[0] = LPFC_FCOE_FCF_MAP0;
6476 phba->fc_map[1] = LPFC_FCOE_FCF_MAP1;
6477 phba->fc_map[2] = LPFC_FCOE_FCF_MAP2;
3772a991 6478
2a76a283
JS
6479 /*
6480 * For SLI4, instead of using ring 0 (LPFC_FCP_RING) for FCP commands
895427bd
JS
6481 * we will associate a new ring, for each EQ/CQ/WQ tuple.
6482 * The WQ create will allocate the ring.
2a76a283 6483 */
09294d46 6484
da0436e9 6485 /* Initialize buffer queue management fields */
895427bd 6486 INIT_LIST_HEAD(&phba->hbqs[LPFC_ELS_HBQ].hbq_buffer_list);
da0436e9
JS
6487 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_sli4_rb_alloc;
6488 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_sli4_rb_free;
3772a991 6489
da0436e9
JS
6490 /*
6491 * Initialize the SLI Layer to run with lpfc SLI4 HBAs.
6492 */
c00f62e6
JS
6493 /* Initialize the Abort buffer list used by driver */
6494 spin_lock_init(&phba->sli4_hba.abts_io_buf_list_lock);
6495 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_io_buf_list);
895427bd
JS
6496
6497 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6498 /* Initialize the Abort nvme buffer list used by driver */
5e5b511d 6499 spin_lock_init(&phba->sli4_hba.abts_nvmet_buf_list_lock);
86c67379 6500 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
a8cf5dfe 6501 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_io_wait_list);
79d8c4ce
JS
6502 spin_lock_init(&phba->sli4_hba.t_active_list_lock);
6503 INIT_LIST_HEAD(&phba->sli4_hba.t_active_ctx_list);
895427bd
JS
6504 }
6505
da0436e9 6506 /* This abort list used by worker thread */
895427bd 6507 spin_lock_init(&phba->sli4_hba.sgl_list_lock);
a8cf5dfe 6508 spin_lock_init(&phba->sli4_hba.nvmet_io_wait_lock);
3772a991 6509
da0436e9 6510 /*
6d368e53 6511 * Initialize driver internal slow-path work queues
da0436e9 6512 */
3772a991 6513
da0436e9
JS
6514 /* Driver internel slow-path CQ Event pool */
6515 INIT_LIST_HEAD(&phba->sli4_hba.sp_cqe_event_pool);
6516 /* Response IOCB work queue list */
45ed1190 6517 INIT_LIST_HEAD(&phba->sli4_hba.sp_queue_event);
da0436e9
JS
6518 /* Asynchronous event CQ Event work queue list */
6519 INIT_LIST_HEAD(&phba->sli4_hba.sp_asynce_work_queue);
6520 /* Fast-path XRI aborted CQ Event work queue list */
6521 INIT_LIST_HEAD(&phba->sli4_hba.sp_fcp_xri_aborted_work_queue);
6522 /* Slow-path XRI aborted CQ Event work queue list */
6523 INIT_LIST_HEAD(&phba->sli4_hba.sp_els_xri_aborted_work_queue);
6524 /* Receive queue CQ Event work queue list */
6525 INIT_LIST_HEAD(&phba->sli4_hba.sp_unsol_work_queue);
6526
6d368e53
JS
6527 /* Initialize extent block lists. */
6528 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_blk_list);
6529 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_xri_blk_list);
6530 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_vfi_blk_list);
6531 INIT_LIST_HEAD(&phba->lpfc_vpi_blk_list);
6532
d1f525aa
JS
6533 /* Initialize mboxq lists. If the early init routines fail
6534 * these lists need to be correctly initialized.
6535 */
6536 INIT_LIST_HEAD(&phba->sli.mboxq);
6537 INIT_LIST_HEAD(&phba->sli.mboxq_cmpl);
6538
448193b5
JS
6539 /* initialize optic_state to 0xFF */
6540 phba->sli4_hba.lnk_info.optic_state = 0xff;
6541
da0436e9
JS
6542 /* Allocate device driver memory */
6543 rc = lpfc_mem_alloc(phba, SGL_ALIGN_SZ);
6544 if (rc)
6545 return -ENOMEM;
6546
2fcee4bf 6547 /* IF Type 2 ports get initialized now. */
27d6ac0a 6548 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) >=
2fcee4bf
JS
6549 LPFC_SLI_INTF_IF_TYPE_2) {
6550 rc = lpfc_pci_function_reset(phba);
895427bd
JS
6551 if (unlikely(rc)) {
6552 rc = -ENODEV;
6553 goto out_free_mem;
6554 }
946727dc 6555 phba->temp_sensor_support = 1;
2fcee4bf
JS
6556 }
6557
da0436e9
JS
6558 /* Create the bootstrap mailbox command */
6559 rc = lpfc_create_bootstrap_mbox(phba);
6560 if (unlikely(rc))
6561 goto out_free_mem;
6562
6563 /* Set up the host's endian order with the device. */
6564 rc = lpfc_setup_endian_order(phba);
6565 if (unlikely(rc))
6566 goto out_free_bsmbx;
6567
6568 /* Set up the hba's configuration parameters. */
6569 rc = lpfc_sli4_read_config(phba);
cff261f6
JS
6570 if (unlikely(rc))
6571 goto out_free_bsmbx;
6572 rc = lpfc_mem_alloc_active_rrq_pool_s4(phba);
da0436e9
JS
6573 if (unlikely(rc))
6574 goto out_free_bsmbx;
6575
2fcee4bf
JS
6576 /* IF Type 0 ports get initialized now. */
6577 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
6578 LPFC_SLI_INTF_IF_TYPE_0) {
6579 rc = lpfc_pci_function_reset(phba);
6580 if (unlikely(rc))
6581 goto out_free_bsmbx;
6582 }
da0436e9 6583
cb5172ea
JS
6584 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
6585 GFP_KERNEL);
6586 if (!mboxq) {
6587 rc = -ENOMEM;
6588 goto out_free_bsmbx;
6589 }
6590
f358dd0c 6591 /* Check for NVMET being configured */
895427bd 6592 phba->nvmet_support = 0;
f358dd0c
JS
6593 if (lpfc_enable_nvmet_cnt) {
6594
6595 /* First get WWN of HBA instance */
6596 lpfc_read_nv(phba, mboxq);
6597 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
6598 if (rc != MBX_SUCCESS) {
6599 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
6600 "6016 Mailbox failed , mbxCmd x%x "
6601 "READ_NV, mbxStatus x%x\n",
6602 bf_get(lpfc_mqe_command, &mboxq->u.mqe),
6603 bf_get(lpfc_mqe_status, &mboxq->u.mqe));
d1f525aa 6604 mempool_free(mboxq, phba->mbox_mem_pool);
f358dd0c
JS
6605 rc = -EIO;
6606 goto out_free_bsmbx;
6607 }
6608 mb = &mboxq->u.mb;
6609 memcpy(&wwn, (char *)mb->un.varRDnvp.nodename,
6610 sizeof(uint64_t));
6611 wwn = cpu_to_be64(wwn);
6612 phba->sli4_hba.wwnn.u.name = wwn;
6613 memcpy(&wwn, (char *)mb->un.varRDnvp.portname,
6614 sizeof(uint64_t));
6615 /* wwn is WWPN of HBA instance */
6616 wwn = cpu_to_be64(wwn);
6617 phba->sli4_hba.wwpn.u.name = wwn;
6618
6619 /* Check to see if it matches any module parameter */
6620 for (i = 0; i < lpfc_enable_nvmet_cnt; i++) {
6621 if (wwn == lpfc_enable_nvmet[i]) {
7d708033 6622#if (IS_ENABLED(CONFIG_NVME_TARGET_FC))
3c603be9
JS
6623 if (lpfc_nvmet_mem_alloc(phba))
6624 break;
6625
6626 phba->nvmet_support = 1; /* a match */
6627
f358dd0c
JS
6628 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6629 "6017 NVME Target %016llx\n",
6630 wwn);
7d708033
JS
6631#else
6632 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6633 "6021 Can't enable NVME Target."
6634 " NVME_TARGET_FC infrastructure"
6635 " is not in kernel\n");
6636#endif
c490850a
JS
6637 /* Not supported for NVMET */
6638 phba->cfg_xri_rebalancing = 0;
3c603be9 6639 break;
f358dd0c
JS
6640 }
6641 }
6642 }
895427bd
JS
6643
6644 lpfc_nvme_mod_param_dep(phba);
6645
fedd3b7b 6646 /* Get the Supported Pages if PORT_CAPABILITIES is supported by port. */
cb5172ea
JS
6647 lpfc_supported_pages(mboxq);
6648 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
fedd3b7b
JS
6649 if (!rc) {
6650 mqe = &mboxq->u.mqe;
6651 memcpy(&pn_page[0], ((uint8_t *)&mqe->un.supp_pages.word3),
6652 LPFC_MAX_SUPPORTED_PAGES);
6653 for (i = 0; i < LPFC_MAX_SUPPORTED_PAGES; i++) {
6654 switch (pn_page[i]) {
6655 case LPFC_SLI4_PARAMETERS:
6656 phba->sli4_hba.pc_sli4_params.supported = 1;
6657 break;
6658 default:
6659 break;
6660 }
6661 }
6662 /* Read the port's SLI4 Parameters capabilities if supported. */
6663 if (phba->sli4_hba.pc_sli4_params.supported)
6664 rc = lpfc_pc_sli4_params_get(phba, mboxq);
6665 if (rc) {
6666 mempool_free(mboxq, phba->mbox_mem_pool);
6667 rc = -EIO;
6668 goto out_free_bsmbx;
cb5172ea
JS
6669 }
6670 }
65791f1f 6671
fedd3b7b
JS
6672 /*
6673 * Get sli4 parameters that override parameters from Port capabilities.
6d368e53
JS
6674 * If this call fails, it isn't critical unless the SLI4 parameters come
6675 * back in conflict.
fedd3b7b 6676 */
6d368e53
JS
6677 rc = lpfc_get_sli4_parameters(phba, mboxq);
6678 if (rc) {
b92dc72d
JS
6679 if_type = bf_get(lpfc_sli_intf_if_type,
6680 &phba->sli4_hba.sli_intf);
6681 if_fam = bf_get(lpfc_sli_intf_sli_family,
6682 &phba->sli4_hba.sli_intf);
6d368e53
JS
6683 if (phba->sli4_hba.extents_in_use &&
6684 phba->sli4_hba.rpi_hdrs_in_use) {
6685 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6686 "2999 Unsupported SLI4 Parameters "
6687 "Extents and RPI headers enabled.\n");
b92dc72d
JS
6688 if (if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
6689 if_fam == LPFC_SLI_INTF_FAMILY_BE2) {
6690 mempool_free(mboxq, phba->mbox_mem_pool);
6691 rc = -EIO;
6692 goto out_free_bsmbx;
6693 }
6694 }
6695 if (!(if_type == LPFC_SLI_INTF_IF_TYPE_0 &&
6696 if_fam == LPFC_SLI_INTF_FAMILY_BE2)) {
6697 mempool_free(mboxq, phba->mbox_mem_pool);
6698 rc = -EIO;
6699 goto out_free_bsmbx;
6d368e53
JS
6700 }
6701 }
895427bd 6702
d79c9e9d
JS
6703 /*
6704 * 1 for cmd, 1 for rsp, NVME adds an extra one
6705 * for boundary conditions in its max_sgl_segment template.
6706 */
6707 extra = 2;
6708 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
6709 extra++;
6710
6711 /*
6712 * It doesn't matter what family our adapter is in, we are
6713 * limited to 2 Pages, 512 SGEs, for our SGL.
6714 * There are going to be 2 reserved SGEs: 1 FCP cmnd + 1 FCP rsp
6715 */
6716 max_buf_size = (2 * SLI4_PAGE_SIZE);
6717
6718 /*
6719 * Since lpfc_sg_seg_cnt is module param, the sg_dma_buf_size
6720 * used to create the sg_dma_buf_pool must be calculated.
6721 */
6722 if (phba->sli3_options & LPFC_SLI3_BG_ENABLED) {
6723 /* Both cfg_enable_bg and cfg_external_dif code paths */
6724
6725 /*
6726 * The scsi_buf for a T10-DIF I/O holds the FCP cmnd,
6727 * the FCP rsp, and a SGE. Sice we have no control
6728 * over how many protection segments the SCSI Layer
6729 * will hand us (ie: there could be one for every block
6730 * in the IO), just allocate enough SGEs to accomidate
6731 * our max amount and we need to limit lpfc_sg_seg_cnt
6732 * to minimize the risk of running out.
6733 */
6734 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6735 sizeof(struct fcp_rsp) + max_buf_size;
6736
6737 /* Total SGEs for scsi_sg_list and scsi_sg_prot_list */
6738 phba->cfg_total_seg_cnt = LPFC_MAX_SGL_SEG_CNT;
6739
6740 /*
6741 * If supporting DIF, reduce the seg count for scsi to
6742 * allow room for the DIF sges.
6743 */
6744 if (phba->cfg_enable_bg &&
6745 phba->cfg_sg_seg_cnt > LPFC_MAX_BG_SLI4_SEG_CNT_DIF)
6746 phba->cfg_scsi_seg_cnt = LPFC_MAX_BG_SLI4_SEG_CNT_DIF;
6747 else
6748 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
6749
6750 } else {
6751 /*
6752 * The scsi_buf for a regular I/O holds the FCP cmnd,
6753 * the FCP rsp, a SGE for each, and a SGE for up to
6754 * cfg_sg_seg_cnt data segments.
6755 */
6756 phba->cfg_sg_dma_buf_size = sizeof(struct fcp_cmnd) +
6757 sizeof(struct fcp_rsp) +
6758 ((phba->cfg_sg_seg_cnt + extra) *
6759 sizeof(struct sli4_sge));
6760
6761 /* Total SGEs for scsi_sg_list */
6762 phba->cfg_total_seg_cnt = phba->cfg_sg_seg_cnt + extra;
6763 phba->cfg_scsi_seg_cnt = phba->cfg_sg_seg_cnt;
6764
6765 /*
6766 * NOTE: if (phba->cfg_sg_seg_cnt + extra) <= 256 we only
6767 * need to post 1 page for the SGL.
6768 */
6769 }
6770
6771 if (phba->cfg_xpsgl && !phba->nvmet_support)
6772 phba->cfg_sg_dma_buf_size = LPFC_DEFAULT_XPSGL_SIZE;
6773 else if (phba->cfg_sg_dma_buf_size <= LPFC_MIN_SG_SLI4_BUF_SZ)
6774 phba->cfg_sg_dma_buf_size = LPFC_MIN_SG_SLI4_BUF_SZ;
6775 else
6776 phba->cfg_sg_dma_buf_size =
6777 SLI4_PAGE_ALIGN(phba->cfg_sg_dma_buf_size);
6778
6779 phba->border_sge_num = phba->cfg_sg_dma_buf_size /
6780 sizeof(struct sli4_sge);
6781
6782 /* Limit to LPFC_MAX_NVME_SEG_CNT for NVME. */
6783 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
6784 if (phba->cfg_sg_seg_cnt > LPFC_MAX_NVME_SEG_CNT) {
6785 lpfc_printf_log(phba, KERN_INFO, LOG_NVME | LOG_INIT,
6786 "6300 Reducing NVME sg segment "
6787 "cnt to %d\n",
6788 LPFC_MAX_NVME_SEG_CNT);
6789 phba->cfg_nvme_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
6790 } else
6791 phba->cfg_nvme_seg_cnt = phba->cfg_sg_seg_cnt;
6792 }
6793
6794 /* Initialize the host templates with the updated values. */
6795 lpfc_vport_template.sg_tablesize = phba->cfg_scsi_seg_cnt;
6796 lpfc_template.sg_tablesize = phba->cfg_scsi_seg_cnt;
6797 lpfc_template_no_hr.sg_tablesize = phba->cfg_scsi_seg_cnt;
6798
6799 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_FCP,
6800 "9087 sg_seg_cnt:%d dmabuf_size:%d "
6801 "total:%d scsi:%d nvme:%d\n",
6802 phba->cfg_sg_seg_cnt, phba->cfg_sg_dma_buf_size,
6803 phba->cfg_total_seg_cnt, phba->cfg_scsi_seg_cnt,
6804 phba->cfg_nvme_seg_cnt);
6805
6806 if (phba->cfg_sg_dma_buf_size < SLI4_PAGE_SIZE)
6807 i = phba->cfg_sg_dma_buf_size;
6808 else
6809 i = SLI4_PAGE_SIZE;
6810
6811 phba->lpfc_sg_dma_buf_pool =
6812 dma_pool_create("lpfc_sg_dma_buf_pool",
6813 &phba->pcidev->dev,
6814 phba->cfg_sg_dma_buf_size,
6815 i, 0);
6816 if (!phba->lpfc_sg_dma_buf_pool)
6817 goto out_free_bsmbx;
6818
6819 phba->lpfc_cmd_rsp_buf_pool =
6820 dma_pool_create("lpfc_cmd_rsp_buf_pool",
6821 &phba->pcidev->dev,
6822 sizeof(struct fcp_cmnd) +
6823 sizeof(struct fcp_rsp),
6824 i, 0);
6825 if (!phba->lpfc_cmd_rsp_buf_pool)
6826 goto out_free_sg_dma_buf;
6827
cb5172ea 6828 mempool_free(mboxq, phba->mbox_mem_pool);
1ba981fd
JS
6829
6830 /* Verify OAS is supported */
6831 lpfc_sli4_oas_verify(phba);
1ba981fd 6832
d2cc9bcd
JS
6833 /* Verify RAS support on adapter */
6834 lpfc_sli4_ras_init(phba);
6835
5350d872
JS
6836 /* Verify all the SLI4 queues */
6837 rc = lpfc_sli4_queue_verify(phba);
da0436e9 6838 if (rc)
d79c9e9d 6839 goto out_free_cmd_rsp_buf;
da0436e9
JS
6840
6841 /* Create driver internal CQE event pool */
6842 rc = lpfc_sli4_cq_event_pool_create(phba);
6843 if (rc)
d79c9e9d 6844 goto out_free_cmd_rsp_buf;
da0436e9 6845
8a9d2e80
JS
6846 /* Initialize sgl lists per host */
6847 lpfc_init_sgl_list(phba);
6848
6849 /* Allocate and initialize active sgl array */
da0436e9
JS
6850 rc = lpfc_init_active_sgl_array(phba);
6851 if (rc) {
6852 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6853 "1430 Failed to initialize sgl list.\n");
8a9d2e80 6854 goto out_destroy_cq_event_pool;
da0436e9 6855 }
da0436e9
JS
6856 rc = lpfc_sli4_init_rpi_hdrs(phba);
6857 if (rc) {
6858 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6859 "1432 Failed to initialize rpi headers.\n");
6860 goto out_free_active_sgl;
6861 }
6862
a93ff37a 6863 /* Allocate eligible FCF bmask memory for FCF roundrobin failover */
0c9ab6f5 6864 longs = (LPFC_SLI4_FCF_TBL_INDX_MAX + BITS_PER_LONG - 1)/BITS_PER_LONG;
6396bb22 6865 phba->fcf.fcf_rr_bmask = kcalloc(longs, sizeof(unsigned long),
0c9ab6f5
JS
6866 GFP_KERNEL);
6867 if (!phba->fcf.fcf_rr_bmask) {
6868 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6869 "2759 Failed allocate memory for FCF round "
6870 "robin failover bmask\n");
0558056c 6871 rc = -ENOMEM;
0c9ab6f5
JS
6872 goto out_remove_rpi_hdrs;
6873 }
6874
6a828b0f 6875 phba->sli4_hba.hba_eq_hdl = kcalloc(phba->cfg_irq_chann,
cdb42bec
JS
6876 sizeof(struct lpfc_hba_eq_hdl),
6877 GFP_KERNEL);
895427bd 6878 if (!phba->sli4_hba.hba_eq_hdl) {
67d12733
JS
6879 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6880 "2572 Failed allocate memory for "
6881 "fast-path per-EQ handle array\n");
6882 rc = -ENOMEM;
6883 goto out_free_fcf_rr_bmask;
da0436e9
JS
6884 }
6885
222e9239 6886 phba->sli4_hba.cpu_map = kcalloc(phba->sli4_hba.num_possible_cpu,
895427bd
JS
6887 sizeof(struct lpfc_vector_map_info),
6888 GFP_KERNEL);
7bb03bbf
JS
6889 if (!phba->sli4_hba.cpu_map) {
6890 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6891 "3327 Failed allocate memory for msi-x "
6892 "interrupt vector mapping\n");
6893 rc = -ENOMEM;
895427bd 6894 goto out_free_hba_eq_hdl;
7bb03bbf 6895 }
b246de17 6896
32517fc0
JS
6897 phba->sli4_hba.eq_info = alloc_percpu(struct lpfc_eq_intr_info);
6898 if (!phba->sli4_hba.eq_info) {
6899 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6900 "3321 Failed allocation for per_cpu stats\n");
6901 rc = -ENOMEM;
6902 goto out_free_hba_cpu_map;
6903 }
912e3acd
JS
6904 /*
6905 * Enable sr-iov virtual functions if supported and configured
6906 * through the module parameter.
6907 */
6908 if (phba->cfg_sriov_nr_virtfn > 0) {
6909 rc = lpfc_sli_probe_sriov_nr_virtfn(phba,
6910 phba->cfg_sriov_nr_virtfn);
6911 if (rc) {
6912 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
6913 "3020 Requested number of SR-IOV "
6914 "virtual functions (%d) is not "
6915 "supported\n",
6916 phba->cfg_sriov_nr_virtfn);
6917 phba->cfg_sriov_nr_virtfn = 0;
6918 }
6919 }
6920
5248a749 6921 return 0;
da0436e9 6922
32517fc0
JS
6923out_free_hba_cpu_map:
6924 kfree(phba->sli4_hba.cpu_map);
895427bd
JS
6925out_free_hba_eq_hdl:
6926 kfree(phba->sli4_hba.hba_eq_hdl);
0c9ab6f5
JS
6927out_free_fcf_rr_bmask:
6928 kfree(phba->fcf.fcf_rr_bmask);
da0436e9
JS
6929out_remove_rpi_hdrs:
6930 lpfc_sli4_remove_rpi_hdrs(phba);
6931out_free_active_sgl:
6932 lpfc_free_active_sgl(phba);
da0436e9
JS
6933out_destroy_cq_event_pool:
6934 lpfc_sli4_cq_event_pool_destroy(phba);
d79c9e9d
JS
6935out_free_cmd_rsp_buf:
6936 dma_pool_destroy(phba->lpfc_cmd_rsp_buf_pool);
6937 phba->lpfc_cmd_rsp_buf_pool = NULL;
6938out_free_sg_dma_buf:
6939 dma_pool_destroy(phba->lpfc_sg_dma_buf_pool);
6940 phba->lpfc_sg_dma_buf_pool = NULL;
da0436e9
JS
6941out_free_bsmbx:
6942 lpfc_destroy_bootstrap_mbox(phba);
6943out_free_mem:
6944 lpfc_mem_free(phba);
6945 return rc;
6946}
6947
6948/**
6949 * lpfc_sli4_driver_resource_unset - Unset drvr internal resources for SLI4 dev
6950 * @phba: pointer to lpfc hba data structure.
6951 *
6952 * This routine is invoked to unset the driver internal resources set up
6953 * specific for supporting the SLI-4 HBA device it attached to.
6954 **/
6955static void
6956lpfc_sli4_driver_resource_unset(struct lpfc_hba *phba)
6957{
6958 struct lpfc_fcf_conn_entry *conn_entry, *next_conn_entry;
6959
32517fc0
JS
6960 free_percpu(phba->sli4_hba.eq_info);
6961
7bb03bbf
JS
6962 /* Free memory allocated for msi-x interrupt vector to CPU mapping */
6963 kfree(phba->sli4_hba.cpu_map);
222e9239 6964 phba->sli4_hba.num_possible_cpu = 0;
7bb03bbf 6965 phba->sli4_hba.num_present_cpu = 0;
76fd07a6 6966 phba->sli4_hba.curr_disp_cpu = 0;
7bb03bbf 6967
da0436e9 6968 /* Free memory allocated for fast-path work queue handles */
895427bd 6969 kfree(phba->sli4_hba.hba_eq_hdl);
da0436e9
JS
6970
6971 /* Free the allocated rpi headers. */
6972 lpfc_sli4_remove_rpi_hdrs(phba);
d11e31dd 6973 lpfc_sli4_remove_rpis(phba);
da0436e9 6974
0c9ab6f5
JS
6975 /* Free eligible FCF index bmask */
6976 kfree(phba->fcf.fcf_rr_bmask);
6977
da0436e9
JS
6978 /* Free the ELS sgl list */
6979 lpfc_free_active_sgl(phba);
8a9d2e80 6980 lpfc_free_els_sgl_list(phba);
f358dd0c 6981 lpfc_free_nvmet_sgl_list(phba);
da0436e9 6982
da0436e9
JS
6983 /* Free the completion queue EQ event pool */
6984 lpfc_sli4_cq_event_release_all(phba);
6985 lpfc_sli4_cq_event_pool_destroy(phba);
6986
6d368e53
JS
6987 /* Release resource identifiers. */
6988 lpfc_sli4_dealloc_resource_identifiers(phba);
6989
da0436e9
JS
6990 /* Free the bsmbx region. */
6991 lpfc_destroy_bootstrap_mbox(phba);
6992
6993 /* Free the SLI Layer memory with SLI4 HBAs */
6994 lpfc_mem_free_all(phba);
6995
6996 /* Free the current connect table */
6997 list_for_each_entry_safe(conn_entry, next_conn_entry,
4d9ab994
JS
6998 &phba->fcf_conn_rec_list, list) {
6999 list_del_init(&conn_entry->list);
da0436e9 7000 kfree(conn_entry);
4d9ab994 7001 }
da0436e9
JS
7002
7003 return;
7004}
7005
7006/**
25985edc 7007 * lpfc_init_api_table_setup - Set up init api function jump table
da0436e9
JS
7008 * @phba: The hba struct for which this call is being executed.
7009 * @dev_grp: The HBA PCI-Device group number.
7010 *
7011 * This routine sets up the device INIT interface API function jump table
7012 * in @phba struct.
7013 *
7014 * Returns: 0 - success, -ENODEV - failure.
7015 **/
7016int
7017lpfc_init_api_table_setup(struct lpfc_hba *phba, uint8_t dev_grp)
7018{
84d1b006
JS
7019 phba->lpfc_hba_init_link = lpfc_hba_init_link;
7020 phba->lpfc_hba_down_link = lpfc_hba_down_link;
7f86059a 7021 phba->lpfc_selective_reset = lpfc_selective_reset;
da0436e9
JS
7022 switch (dev_grp) {
7023 case LPFC_PCI_DEV_LP:
7024 phba->lpfc_hba_down_post = lpfc_hba_down_post_s3;
7025 phba->lpfc_handle_eratt = lpfc_handle_eratt_s3;
7026 phba->lpfc_stop_port = lpfc_stop_port_s3;
7027 break;
7028 case LPFC_PCI_DEV_OC:
7029 phba->lpfc_hba_down_post = lpfc_hba_down_post_s4;
7030 phba->lpfc_handle_eratt = lpfc_handle_eratt_s4;
7031 phba->lpfc_stop_port = lpfc_stop_port_s4;
7032 break;
7033 default:
7034 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7035 "1431 Invalid HBA PCI-device group: 0x%x\n",
7036 dev_grp);
7037 return -ENODEV;
7038 break;
7039 }
7040 return 0;
7041}
7042
da0436e9
JS
7043/**
7044 * lpfc_setup_driver_resource_phase2 - Phase2 setup driver internal resources.
7045 * @phba: pointer to lpfc hba data structure.
7046 *
7047 * This routine is invoked to set up the driver internal resources after the
7048 * device specific resource setup to support the HBA device it attached to.
7049 *
7050 * Return codes
af901ca1 7051 * 0 - successful
da0436e9
JS
7052 * other values - error
7053 **/
7054static int
7055lpfc_setup_driver_resource_phase2(struct lpfc_hba *phba)
7056{
7057 int error;
7058
7059 /* Startup the kernel thread for this host adapter. */
7060 phba->worker_thread = kthread_run(lpfc_do_work, phba,
7061 "lpfc_worker_%d", phba->brd_no);
7062 if (IS_ERR(phba->worker_thread)) {
7063 error = PTR_ERR(phba->worker_thread);
7064 return error;
3772a991
JS
7065 }
7066
7067 return 0;
7068}
7069
7070/**
7071 * lpfc_unset_driver_resource_phase2 - Phase2 unset driver internal resources.
7072 * @phba: pointer to lpfc hba data structure.
7073 *
7074 * This routine is invoked to unset the driver internal resources set up after
7075 * the device specific resource setup for supporting the HBA device it
7076 * attached to.
7077 **/
7078static void
7079lpfc_unset_driver_resource_phase2(struct lpfc_hba *phba)
7080{
f485c18d
DK
7081 if (phba->wq) {
7082 flush_workqueue(phba->wq);
7083 destroy_workqueue(phba->wq);
7084 phba->wq = NULL;
7085 }
7086
3772a991 7087 /* Stop kernel worker thread */
0cdb84ec
JS
7088 if (phba->worker_thread)
7089 kthread_stop(phba->worker_thread);
3772a991
JS
7090}
7091
7092/**
7093 * lpfc_free_iocb_list - Free iocb list.
7094 * @phba: pointer to lpfc hba data structure.
7095 *
7096 * This routine is invoked to free the driver's IOCB list and memory.
7097 **/
6c621a22 7098void
3772a991
JS
7099lpfc_free_iocb_list(struct lpfc_hba *phba)
7100{
7101 struct lpfc_iocbq *iocbq_entry = NULL, *iocbq_next = NULL;
7102
7103 spin_lock_irq(&phba->hbalock);
7104 list_for_each_entry_safe(iocbq_entry, iocbq_next,
7105 &phba->lpfc_iocb_list, list) {
7106 list_del(&iocbq_entry->list);
7107 kfree(iocbq_entry);
7108 phba->total_iocbq_bufs--;
98c9ea5c 7109 }
3772a991
JS
7110 spin_unlock_irq(&phba->hbalock);
7111
7112 return;
7113}
7114
7115/**
7116 * lpfc_init_iocb_list - Allocate and initialize iocb list.
7117 * @phba: pointer to lpfc hba data structure.
7118 *
7119 * This routine is invoked to allocate and initizlize the driver's IOCB
7120 * list and set up the IOCB tag array accordingly.
7121 *
7122 * Return codes
af901ca1 7123 * 0 - successful
3772a991
JS
7124 * other values - error
7125 **/
6c621a22 7126int
3772a991
JS
7127lpfc_init_iocb_list(struct lpfc_hba *phba, int iocb_count)
7128{
7129 struct lpfc_iocbq *iocbq_entry = NULL;
7130 uint16_t iotag;
7131 int i;
dea3101e 7132
7133 /* Initialize and populate the iocb list per host. */
7134 INIT_LIST_HEAD(&phba->lpfc_iocb_list);
3772a991 7135 for (i = 0; i < iocb_count; i++) {
dd00cc48 7136 iocbq_entry = kzalloc(sizeof(struct lpfc_iocbq), GFP_KERNEL);
dea3101e 7137 if (iocbq_entry == NULL) {
7138 printk(KERN_ERR "%s: only allocated %d iocbs of "
7139 "expected %d count. Unloading driver.\n",
a5f7337f 7140 __func__, i, iocb_count);
dea3101e 7141 goto out_free_iocbq;
7142 }
7143
604a3e30
JB
7144 iotag = lpfc_sli_next_iotag(phba, iocbq_entry);
7145 if (iotag == 0) {
3772a991 7146 kfree(iocbq_entry);
604a3e30 7147 printk(KERN_ERR "%s: failed to allocate IOTAG. "
3772a991 7148 "Unloading driver.\n", __func__);
604a3e30
JB
7149 goto out_free_iocbq;
7150 }
6d368e53 7151 iocbq_entry->sli4_lxritag = NO_XRI;
3772a991 7152 iocbq_entry->sli4_xritag = NO_XRI;
2e0fef85
JS
7153
7154 spin_lock_irq(&phba->hbalock);
dea3101e 7155 list_add(&iocbq_entry->list, &phba->lpfc_iocb_list);
7156 phba->total_iocbq_bufs++;
2e0fef85 7157 spin_unlock_irq(&phba->hbalock);
dea3101e 7158 }
7159
3772a991 7160 return 0;
dea3101e 7161
3772a991
JS
7162out_free_iocbq:
7163 lpfc_free_iocb_list(phba);
dea3101e 7164
3772a991
JS
7165 return -ENOMEM;
7166}
5e9d9b82 7167
3772a991 7168/**
8a9d2e80 7169 * lpfc_free_sgl_list - Free a given sgl list.
da0436e9 7170 * @phba: pointer to lpfc hba data structure.
8a9d2e80 7171 * @sglq_list: pointer to the head of sgl list.
3772a991 7172 *
8a9d2e80 7173 * This routine is invoked to free a give sgl list and memory.
3772a991 7174 **/
8a9d2e80
JS
7175void
7176lpfc_free_sgl_list(struct lpfc_hba *phba, struct list_head *sglq_list)
3772a991 7177{
da0436e9 7178 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
8a9d2e80
JS
7179
7180 list_for_each_entry_safe(sglq_entry, sglq_next, sglq_list, list) {
7181 list_del(&sglq_entry->list);
7182 lpfc_mbuf_free(phba, sglq_entry->virt, sglq_entry->phys);
7183 kfree(sglq_entry);
7184 }
7185}
7186
7187/**
7188 * lpfc_free_els_sgl_list - Free els sgl list.
7189 * @phba: pointer to lpfc hba data structure.
7190 *
7191 * This routine is invoked to free the driver's els sgl list and memory.
7192 **/
7193static void
7194lpfc_free_els_sgl_list(struct lpfc_hba *phba)
7195{
da0436e9 7196 LIST_HEAD(sglq_list);
dea3101e 7197
8a9d2e80 7198 /* Retrieve all els sgls from driver list */
da0436e9 7199 spin_lock_irq(&phba->hbalock);
895427bd
JS
7200 spin_lock(&phba->sli4_hba.sgl_list_lock);
7201 list_splice_init(&phba->sli4_hba.lpfc_els_sgl_list, &sglq_list);
7202 spin_unlock(&phba->sli4_hba.sgl_list_lock);
da0436e9 7203 spin_unlock_irq(&phba->hbalock);
dea3101e 7204
8a9d2e80
JS
7205 /* Now free the sgl list */
7206 lpfc_free_sgl_list(phba, &sglq_list);
da0436e9 7207}
92d7f7b0 7208
f358dd0c
JS
7209/**
7210 * lpfc_free_nvmet_sgl_list - Free nvmet sgl list.
7211 * @phba: pointer to lpfc hba data structure.
7212 *
7213 * This routine is invoked to free the driver's nvmet sgl list and memory.
7214 **/
7215static void
7216lpfc_free_nvmet_sgl_list(struct lpfc_hba *phba)
7217{
7218 struct lpfc_sglq *sglq_entry = NULL, *sglq_next = NULL;
7219 LIST_HEAD(sglq_list);
7220
7221 /* Retrieve all nvmet sgls from driver list */
7222 spin_lock_irq(&phba->hbalock);
7223 spin_lock(&phba->sli4_hba.sgl_list_lock);
7224 list_splice_init(&phba->sli4_hba.lpfc_nvmet_sgl_list, &sglq_list);
7225 spin_unlock(&phba->sli4_hba.sgl_list_lock);
7226 spin_unlock_irq(&phba->hbalock);
7227
7228 /* Now free the sgl list */
7229 list_for_each_entry_safe(sglq_entry, sglq_next, &sglq_list, list) {
7230 list_del(&sglq_entry->list);
7231 lpfc_nvmet_buf_free(phba, sglq_entry->virt, sglq_entry->phys);
7232 kfree(sglq_entry);
7233 }
4b40d02b
DK
7234
7235 /* Update the nvmet_xri_cnt to reflect no current sgls.
7236 * The next initialization cycle sets the count and allocates
7237 * the sgls over again.
7238 */
7239 phba->sli4_hba.nvmet_xri_cnt = 0;
f358dd0c
JS
7240}
7241
da0436e9
JS
7242/**
7243 * lpfc_init_active_sgl_array - Allocate the buf to track active ELS XRIs.
7244 * @phba: pointer to lpfc hba data structure.
7245 *
7246 * This routine is invoked to allocate the driver's active sgl memory.
7247 * This array will hold the sglq_entry's for active IOs.
7248 **/
7249static int
7250lpfc_init_active_sgl_array(struct lpfc_hba *phba)
7251{
7252 int size;
7253 size = sizeof(struct lpfc_sglq *);
7254 size *= phba->sli4_hba.max_cfg_param.max_xri;
7255
7256 phba->sli4_hba.lpfc_sglq_active_list =
7257 kzalloc(size, GFP_KERNEL);
7258 if (!phba->sli4_hba.lpfc_sglq_active_list)
7259 return -ENOMEM;
7260 return 0;
3772a991
JS
7261}
7262
7263/**
da0436e9 7264 * lpfc_free_active_sgl - Free the buf that tracks active ELS XRIs.
3772a991
JS
7265 * @phba: pointer to lpfc hba data structure.
7266 *
da0436e9
JS
7267 * This routine is invoked to walk through the array of active sglq entries
7268 * and free all of the resources.
7269 * This is just a place holder for now.
3772a991
JS
7270 **/
7271static void
da0436e9 7272lpfc_free_active_sgl(struct lpfc_hba *phba)
3772a991 7273{
da0436e9 7274 kfree(phba->sli4_hba.lpfc_sglq_active_list);
3772a991
JS
7275}
7276
7277/**
da0436e9 7278 * lpfc_init_sgl_list - Allocate and initialize sgl list.
3772a991
JS
7279 * @phba: pointer to lpfc hba data structure.
7280 *
da0436e9
JS
7281 * This routine is invoked to allocate and initizlize the driver's sgl
7282 * list and set up the sgl xritag tag array accordingly.
3772a991 7283 *
3772a991 7284 **/
8a9d2e80 7285static void
da0436e9 7286lpfc_init_sgl_list(struct lpfc_hba *phba)
3772a991 7287{
da0436e9 7288 /* Initialize and populate the sglq list per host/VF. */
895427bd 7289 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_els_sgl_list);
da0436e9 7290 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_els_sgl_list);
f358dd0c 7291 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_nvmet_sgl_list);
86c67379 7292 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
da0436e9 7293
8a9d2e80
JS
7294 /* els xri-sgl book keeping */
7295 phba->sli4_hba.els_xri_cnt = 0;
0ff10d46 7296
895427bd 7297 /* nvme xri-buffer book keeping */
5e5b511d 7298 phba->sli4_hba.io_xri_cnt = 0;
da0436e9
JS
7299}
7300
7301/**
7302 * lpfc_sli4_init_rpi_hdrs - Post the rpi header memory region to the port
7303 * @phba: pointer to lpfc hba data structure.
7304 *
7305 * This routine is invoked to post rpi header templates to the
88a2cfbb 7306 * port for those SLI4 ports that do not support extents. This routine
da0436e9 7307 * posts a PAGE_SIZE memory region to the port to hold up to
88a2cfbb
JS
7308 * PAGE_SIZE modulo 64 rpi context headers. This is an initialization routine
7309 * and should be called only when interrupts are disabled.
da0436e9
JS
7310 *
7311 * Return codes
af901ca1 7312 * 0 - successful
88a2cfbb 7313 * -ERROR - otherwise.
da0436e9
JS
7314 **/
7315int
7316lpfc_sli4_init_rpi_hdrs(struct lpfc_hba *phba)
7317{
7318 int rc = 0;
da0436e9
JS
7319 struct lpfc_rpi_hdr *rpi_hdr;
7320
7321 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_rpi_hdr_list);
ff78d8f9 7322 if (!phba->sli4_hba.rpi_hdrs_in_use)
6d368e53 7323 return rc;
6d368e53
JS
7324 if (phba->sli4_hba.extents_in_use)
7325 return -EIO;
da0436e9
JS
7326
7327 rpi_hdr = lpfc_sli4_create_rpi_hdr(phba);
7328 if (!rpi_hdr) {
7329 lpfc_printf_log(phba, KERN_ERR, LOG_MBOX | LOG_SLI,
7330 "0391 Error during rpi post operation\n");
7331 lpfc_sli4_remove_rpis(phba);
7332 rc = -ENODEV;
7333 }
7334
7335 return rc;
7336}
7337
7338/**
7339 * lpfc_sli4_create_rpi_hdr - Allocate an rpi header memory region
7340 * @phba: pointer to lpfc hba data structure.
7341 *
7342 * This routine is invoked to allocate a single 4KB memory region to
7343 * support rpis and stores them in the phba. This single region
7344 * provides support for up to 64 rpis. The region is used globally
7345 * by the device.
7346 *
7347 * Returns:
7348 * A valid rpi hdr on success.
7349 * A NULL pointer on any failure.
7350 **/
7351struct lpfc_rpi_hdr *
7352lpfc_sli4_create_rpi_hdr(struct lpfc_hba *phba)
7353{
7354 uint16_t rpi_limit, curr_rpi_range;
7355 struct lpfc_dmabuf *dmabuf;
7356 struct lpfc_rpi_hdr *rpi_hdr;
7357
6d368e53
JS
7358 /*
7359 * If the SLI4 port supports extents, posting the rpi header isn't
7360 * required. Set the expected maximum count and let the actual value
7361 * get set when extents are fully allocated.
7362 */
7363 if (!phba->sli4_hba.rpi_hdrs_in_use)
7364 return NULL;
7365 if (phba->sli4_hba.extents_in_use)
7366 return NULL;
7367
7368 /* The limit on the logical index is just the max_rpi count. */
845d9e8d 7369 rpi_limit = phba->sli4_hba.max_cfg_param.max_rpi;
da0436e9
JS
7370
7371 spin_lock_irq(&phba->hbalock);
6d368e53
JS
7372 /*
7373 * Establish the starting RPI in this header block. The starting
7374 * rpi is normalized to a zero base because the physical rpi is
7375 * port based.
7376 */
97f2ecf1 7377 curr_rpi_range = phba->sli4_hba.next_rpi;
da0436e9
JS
7378 spin_unlock_irq(&phba->hbalock);
7379
845d9e8d
JS
7380 /* Reached full RPI range */
7381 if (curr_rpi_range == rpi_limit)
6d368e53 7382 return NULL;
845d9e8d 7383
da0436e9
JS
7384 /*
7385 * First allocate the protocol header region for the port. The
7386 * port expects a 4KB DMA-mapped memory region that is 4K aligned.
7387 */
7388 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
7389 if (!dmabuf)
7390 return NULL;
7391
750afb08
LC
7392 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
7393 LPFC_HDR_TEMPLATE_SIZE,
7394 &dmabuf->phys, GFP_KERNEL);
da0436e9
JS
7395 if (!dmabuf->virt) {
7396 rpi_hdr = NULL;
7397 goto err_free_dmabuf;
7398 }
7399
da0436e9
JS
7400 if (!IS_ALIGNED(dmabuf->phys, LPFC_HDR_TEMPLATE_SIZE)) {
7401 rpi_hdr = NULL;
7402 goto err_free_coherent;
7403 }
7404
7405 /* Save the rpi header data for cleanup later. */
7406 rpi_hdr = kzalloc(sizeof(struct lpfc_rpi_hdr), GFP_KERNEL);
7407 if (!rpi_hdr)
7408 goto err_free_coherent;
7409
7410 rpi_hdr->dmabuf = dmabuf;
7411 rpi_hdr->len = LPFC_HDR_TEMPLATE_SIZE;
7412 rpi_hdr->page_count = 1;
7413 spin_lock_irq(&phba->hbalock);
6d368e53
JS
7414
7415 /* The rpi_hdr stores the logical index only. */
7416 rpi_hdr->start_rpi = curr_rpi_range;
845d9e8d 7417 rpi_hdr->next_rpi = phba->sli4_hba.next_rpi + LPFC_RPI_HDR_COUNT;
da0436e9
JS
7418 list_add_tail(&rpi_hdr->list, &phba->sli4_hba.lpfc_rpi_hdr_list);
7419
da0436e9
JS
7420 spin_unlock_irq(&phba->hbalock);
7421 return rpi_hdr;
7422
7423 err_free_coherent:
7424 dma_free_coherent(&phba->pcidev->dev, LPFC_HDR_TEMPLATE_SIZE,
7425 dmabuf->virt, dmabuf->phys);
7426 err_free_dmabuf:
7427 kfree(dmabuf);
7428 return NULL;
7429}
7430
7431/**
7432 * lpfc_sli4_remove_rpi_hdrs - Remove all rpi header memory regions
7433 * @phba: pointer to lpfc hba data structure.
7434 *
7435 * This routine is invoked to remove all memory resources allocated
6d368e53
JS
7436 * to support rpis for SLI4 ports not supporting extents. This routine
7437 * presumes the caller has released all rpis consumed by fabric or port
7438 * logins and is prepared to have the header pages removed.
da0436e9
JS
7439 **/
7440void
7441lpfc_sli4_remove_rpi_hdrs(struct lpfc_hba *phba)
7442{
7443 struct lpfc_rpi_hdr *rpi_hdr, *next_rpi_hdr;
7444
6d368e53
JS
7445 if (!phba->sli4_hba.rpi_hdrs_in_use)
7446 goto exit;
7447
da0436e9
JS
7448 list_for_each_entry_safe(rpi_hdr, next_rpi_hdr,
7449 &phba->sli4_hba.lpfc_rpi_hdr_list, list) {
7450 list_del(&rpi_hdr->list);
7451 dma_free_coherent(&phba->pcidev->dev, rpi_hdr->len,
7452 rpi_hdr->dmabuf->virt, rpi_hdr->dmabuf->phys);
7453 kfree(rpi_hdr->dmabuf);
7454 kfree(rpi_hdr);
7455 }
6d368e53
JS
7456 exit:
7457 /* There are no rpis available to the port now. */
7458 phba->sli4_hba.next_rpi = 0;
da0436e9
JS
7459}
7460
7461/**
7462 * lpfc_hba_alloc - Allocate driver hba data structure for a device.
7463 * @pdev: pointer to pci device data structure.
7464 *
7465 * This routine is invoked to allocate the driver hba data structure for an
7466 * HBA device. If the allocation is successful, the phba reference to the
7467 * PCI device data structure is set.
7468 *
7469 * Return codes
af901ca1 7470 * pointer to @phba - successful
da0436e9
JS
7471 * NULL - error
7472 **/
7473static struct lpfc_hba *
7474lpfc_hba_alloc(struct pci_dev *pdev)
7475{
7476 struct lpfc_hba *phba;
7477
7478 /* Allocate memory for HBA structure */
7479 phba = kzalloc(sizeof(struct lpfc_hba), GFP_KERNEL);
7480 if (!phba) {
e34ccdfe 7481 dev_err(&pdev->dev, "failed to allocate hba struct\n");
da0436e9
JS
7482 return NULL;
7483 }
7484
7485 /* Set reference to PCI device in HBA structure */
7486 phba->pcidev = pdev;
7487
7488 /* Assign an unused board number */
7489 phba->brd_no = lpfc_get_instance();
7490 if (phba->brd_no < 0) {
7491 kfree(phba);
7492 return NULL;
7493 }
65791f1f 7494 phba->eratt_poll_interval = LPFC_ERATT_POLL_INTERVAL;
da0436e9 7495
4fede78f 7496 spin_lock_init(&phba->ct_ev_lock);
f1c3b0fc
JS
7497 INIT_LIST_HEAD(&phba->ct_ev_waiters);
7498
da0436e9
JS
7499 return phba;
7500}
7501
7502/**
7503 * lpfc_hba_free - Free driver hba data structure with a device.
7504 * @phba: pointer to lpfc hba data structure.
7505 *
7506 * This routine is invoked to free the driver hba data structure with an
7507 * HBA device.
7508 **/
7509static void
7510lpfc_hba_free(struct lpfc_hba *phba)
7511{
5e5b511d
JS
7512 if (phba->sli_rev == LPFC_SLI_REV4)
7513 kfree(phba->sli4_hba.hdwq);
7514
da0436e9
JS
7515 /* Release the driver assigned board number */
7516 idr_remove(&lpfc_hba_index, phba->brd_no);
7517
895427bd
JS
7518 /* Free memory allocated with sli3 rings */
7519 kfree(phba->sli.sli3_ring);
7520 phba->sli.sli3_ring = NULL;
2a76a283 7521
da0436e9
JS
7522 kfree(phba);
7523 return;
7524}
7525
7526/**
7527 * lpfc_create_shost - Create hba physical port with associated scsi host.
7528 * @phba: pointer to lpfc hba data structure.
7529 *
7530 * This routine is invoked to create HBA physical port and associate a SCSI
7531 * host with it.
7532 *
7533 * Return codes
af901ca1 7534 * 0 - successful
da0436e9
JS
7535 * other values - error
7536 **/
7537static int
7538lpfc_create_shost(struct lpfc_hba *phba)
7539{
7540 struct lpfc_vport *vport;
7541 struct Scsi_Host *shost;
7542
7543 /* Initialize HBA FC structure */
7544 phba->fc_edtov = FF_DEF_EDTOV;
7545 phba->fc_ratov = FF_DEF_RATOV;
7546 phba->fc_altov = FF_DEF_ALTOV;
7547 phba->fc_arbtov = FF_DEF_ARBTOV;
7548
d7c47992 7549 atomic_set(&phba->sdev_cnt, 0);
da0436e9
JS
7550 vport = lpfc_create_port(phba, phba->brd_no, &phba->pcidev->dev);
7551 if (!vport)
7552 return -ENODEV;
7553
7554 shost = lpfc_shost_from_vport(vport);
7555 phba->pport = vport;
2ea259ee 7556
f358dd0c
JS
7557 if (phba->nvmet_support) {
7558 /* Only 1 vport (pport) will support NVME target */
7559 if (phba->txrdy_payload_pool == NULL) {
771db5c0
RP
7560 phba->txrdy_payload_pool = dma_pool_create(
7561 "txrdy_pool", &phba->pcidev->dev,
f358dd0c
JS
7562 TXRDY_PAYLOAD_LEN, 16, 0);
7563 if (phba->txrdy_payload_pool) {
7564 phba->targetport = NULL;
7565 phba->cfg_enable_fc4_type = LPFC_ENABLE_NVME;
7566 lpfc_printf_log(phba, KERN_INFO,
7567 LOG_INIT | LOG_NVME_DISC,
7568 "6076 NVME Target Found\n");
7569 }
7570 }
7571 }
7572
da0436e9
JS
7573 lpfc_debugfs_initialize(vport);
7574 /* Put reference to SCSI host to driver's device private data */
7575 pci_set_drvdata(phba->pcidev, shost);
2e0fef85 7576
4258e98e
JS
7577 /*
7578 * At this point we are fully registered with PSA. In addition,
7579 * any initial discovery should be completed.
7580 */
7581 vport->load_flag |= FC_ALLOW_FDMI;
8663cbbe
JS
7582 if (phba->cfg_enable_SmartSAN ||
7583 (phba->cfg_fdmi_on == LPFC_FDMI_SUPPORT)) {
4258e98e
JS
7584
7585 /* Setup appropriate attribute masks */
7586 vport->fdmi_hba_mask = LPFC_FDMI2_HBA_ATTR;
8663cbbe 7587 if (phba->cfg_enable_SmartSAN)
4258e98e
JS
7588 vport->fdmi_port_mask = LPFC_FDMI2_SMART_ATTR;
7589 else
7590 vport->fdmi_port_mask = LPFC_FDMI2_PORT_ATTR;
7591 }
3772a991
JS
7592 return 0;
7593}
db2378e0 7594
3772a991
JS
7595/**
7596 * lpfc_destroy_shost - Destroy hba physical port with associated scsi host.
7597 * @phba: pointer to lpfc hba data structure.
7598 *
7599 * This routine is invoked to destroy HBA physical port and the associated
7600 * SCSI host.
7601 **/
7602static void
7603lpfc_destroy_shost(struct lpfc_hba *phba)
7604{
7605 struct lpfc_vport *vport = phba->pport;
7606
7607 /* Destroy physical port that associated with the SCSI host */
7608 destroy_port(vport);
7609
7610 return;
7611}
7612
7613/**
7614 * lpfc_setup_bg - Setup Block guard structures and debug areas.
7615 * @phba: pointer to lpfc hba data structure.
7616 * @shost: the shost to be used to detect Block guard settings.
7617 *
7618 * This routine sets up the local Block guard protocol settings for @shost.
7619 * This routine also allocates memory for debugging bg buffers.
7620 **/
7621static void
7622lpfc_setup_bg(struct lpfc_hba *phba, struct Scsi_Host *shost)
7623{
bbeb79b9
JS
7624 uint32_t old_mask;
7625 uint32_t old_guard;
7626
b3b98b74 7627 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
3772a991
JS
7628 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7629 "1478 Registering BlockGuard with the "
7630 "SCSI layer\n");
bbeb79b9 7631
b3b98b74
JS
7632 old_mask = phba->cfg_prot_mask;
7633 old_guard = phba->cfg_prot_guard;
bbeb79b9
JS
7634
7635 /* Only allow supported values */
b3b98b74 7636 phba->cfg_prot_mask &= (SHOST_DIF_TYPE1_PROTECTION |
bbeb79b9
JS
7637 SHOST_DIX_TYPE0_PROTECTION |
7638 SHOST_DIX_TYPE1_PROTECTION);
b3b98b74
JS
7639 phba->cfg_prot_guard &= (SHOST_DIX_GUARD_IP |
7640 SHOST_DIX_GUARD_CRC);
bbeb79b9
JS
7641
7642 /* DIF Type 1 protection for profiles AST1/C1 is end to end */
b3b98b74
JS
7643 if (phba->cfg_prot_mask == SHOST_DIX_TYPE1_PROTECTION)
7644 phba->cfg_prot_mask |= SHOST_DIF_TYPE1_PROTECTION;
bbeb79b9 7645
b3b98b74
JS
7646 if (phba->cfg_prot_mask && phba->cfg_prot_guard) {
7647 if ((old_mask != phba->cfg_prot_mask) ||
7648 (old_guard != phba->cfg_prot_guard))
bbeb79b9
JS
7649 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7650 "1475 Registering BlockGuard with the "
7651 "SCSI layer: mask %d guard %d\n",
b3b98b74
JS
7652 phba->cfg_prot_mask,
7653 phba->cfg_prot_guard);
bbeb79b9 7654
b3b98b74
JS
7655 scsi_host_set_prot(shost, phba->cfg_prot_mask);
7656 scsi_host_set_guard(shost, phba->cfg_prot_guard);
bbeb79b9
JS
7657 } else
7658 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7659 "1479 Not Registering BlockGuard with the SCSI "
7660 "layer, Bad protection parameters: %d %d\n",
7661 old_mask, old_guard);
3772a991 7662 }
3772a991
JS
7663}
7664
7665/**
7666 * lpfc_post_init_setup - Perform necessary device post initialization setup.
7667 * @phba: pointer to lpfc hba data structure.
7668 *
7669 * This routine is invoked to perform all the necessary post initialization
7670 * setup for the device.
7671 **/
7672static void
7673lpfc_post_init_setup(struct lpfc_hba *phba)
7674{
7675 struct Scsi_Host *shost;
7676 struct lpfc_adapter_event_header adapter_event;
7677
7678 /* Get the default values for Model Name and Description */
7679 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
7680
7681 /*
7682 * hba setup may have changed the hba_queue_depth so we need to
7683 * adjust the value of can_queue.
7684 */
7685 shost = pci_get_drvdata(phba->pcidev);
7686 shost->can_queue = phba->cfg_hba_queue_depth - 10;
3772a991
JS
7687
7688 lpfc_host_attrib_init(shost);
7689
7690 if (phba->cfg_poll & DISABLE_FCP_RING_INT) {
7691 spin_lock_irq(shost->host_lock);
7692 lpfc_poll_start_timer(phba);
7693 spin_unlock_irq(shost->host_lock);
7694 }
7695
7696 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
7697 "0428 Perform SCSI scan\n");
7698 /* Send board arrival event to upper layer */
7699 adapter_event.event_type = FC_REG_ADAPTER_EVENT;
7700 adapter_event.subcategory = LPFC_EVENT_ARRIVAL;
7701 fc_host_post_vendor_event(shost, fc_get_event_number(),
7702 sizeof(adapter_event),
7703 (char *) &adapter_event,
7704 LPFC_NL_VENDOR_ID);
7705 return;
7706}
7707
7708/**
7709 * lpfc_sli_pci_mem_setup - Setup SLI3 HBA PCI memory space.
7710 * @phba: pointer to lpfc hba data structure.
7711 *
7712 * This routine is invoked to set up the PCI device memory space for device
7713 * with SLI-3 interface spec.
7714 *
7715 * Return codes
af901ca1 7716 * 0 - successful
3772a991
JS
7717 * other values - error
7718 **/
7719static int
7720lpfc_sli_pci_mem_setup(struct lpfc_hba *phba)
7721{
f30e1bfd 7722 struct pci_dev *pdev = phba->pcidev;
3772a991
JS
7723 unsigned long bar0map_len, bar2map_len;
7724 int i, hbq_count;
7725 void *ptr;
56de8357 7726 int error;
3772a991 7727
f30e1bfd 7728 if (!pdev)
56de8357 7729 return -ENODEV;
3772a991
JS
7730
7731 /* Set the device DMA mask size */
56de8357
HR
7732 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
7733 if (error)
7734 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
7735 if (error)
f30e1bfd 7736 return error;
56de8357 7737 error = -ENODEV;
3772a991
JS
7738
7739 /* Get the bus address of Bar0 and Bar2 and the number of bytes
7740 * required by each mapping.
7741 */
7742 phba->pci_bar0_map = pci_resource_start(pdev, 0);
7743 bar0map_len = pci_resource_len(pdev, 0);
7744
7745 phba->pci_bar2_map = pci_resource_start(pdev, 2);
7746 bar2map_len = pci_resource_len(pdev, 2);
7747
7748 /* Map HBA SLIM to a kernel virtual address. */
7749 phba->slim_memmap_p = ioremap(phba->pci_bar0_map, bar0map_len);
7750 if (!phba->slim_memmap_p) {
7751 dev_printk(KERN_ERR, &pdev->dev,
7752 "ioremap failed for SLIM memory.\n");
7753 goto out;
7754 }
7755
7756 /* Map HBA Control Registers to a kernel virtual address. */
7757 phba->ctrl_regs_memmap_p = ioremap(phba->pci_bar2_map, bar2map_len);
7758 if (!phba->ctrl_regs_memmap_p) {
7759 dev_printk(KERN_ERR, &pdev->dev,
7760 "ioremap failed for HBA control registers.\n");
7761 goto out_iounmap_slim;
7762 }
7763
7764 /* Allocate memory for SLI-2 structures */
750afb08
LC
7765 phba->slim2p.virt = dma_alloc_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7766 &phba->slim2p.phys, GFP_KERNEL);
3772a991
JS
7767 if (!phba->slim2p.virt)
7768 goto out_iounmap;
7769
3772a991 7770 phba->mbox = phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, mbx);
7a470277
JS
7771 phba->mbox_ext = (phba->slim2p.virt +
7772 offsetof(struct lpfc_sli2_slim, mbx_ext_words));
3772a991
JS
7773 phba->pcb = (phba->slim2p.virt + offsetof(struct lpfc_sli2_slim, pcb));
7774 phba->IOCBs = (phba->slim2p.virt +
7775 offsetof(struct lpfc_sli2_slim, IOCBs));
7776
7777 phba->hbqslimp.virt = dma_alloc_coherent(&pdev->dev,
7778 lpfc_sli_hbq_size(),
7779 &phba->hbqslimp.phys,
7780 GFP_KERNEL);
7781 if (!phba->hbqslimp.virt)
7782 goto out_free_slim;
7783
7784 hbq_count = lpfc_sli_hbq_count();
7785 ptr = phba->hbqslimp.virt;
7786 for (i = 0; i < hbq_count; ++i) {
7787 phba->hbqs[i].hbq_virt = ptr;
7788 INIT_LIST_HEAD(&phba->hbqs[i].hbq_buffer_list);
7789 ptr += (lpfc_hbq_defs[i]->entry_count *
7790 sizeof(struct lpfc_hbq_entry));
7791 }
7792 phba->hbqs[LPFC_ELS_HBQ].hbq_alloc_buffer = lpfc_els_hbq_alloc;
7793 phba->hbqs[LPFC_ELS_HBQ].hbq_free_buffer = lpfc_els_hbq_free;
7794
7795 memset(phba->hbqslimp.virt, 0, lpfc_sli_hbq_size());
7796
3772a991
JS
7797 phba->MBslimaddr = phba->slim_memmap_p;
7798 phba->HAregaddr = phba->ctrl_regs_memmap_p + HA_REG_OFFSET;
7799 phba->CAregaddr = phba->ctrl_regs_memmap_p + CA_REG_OFFSET;
7800 phba->HSregaddr = phba->ctrl_regs_memmap_p + HS_REG_OFFSET;
7801 phba->HCregaddr = phba->ctrl_regs_memmap_p + HC_REG_OFFSET;
7802
7803 return 0;
7804
7805out_free_slim:
7806 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7807 phba->slim2p.virt, phba->slim2p.phys);
7808out_iounmap:
7809 iounmap(phba->ctrl_regs_memmap_p);
7810out_iounmap_slim:
7811 iounmap(phba->slim_memmap_p);
7812out:
7813 return error;
7814}
7815
7816/**
7817 * lpfc_sli_pci_mem_unset - Unset SLI3 HBA PCI memory space.
7818 * @phba: pointer to lpfc hba data structure.
7819 *
7820 * This routine is invoked to unset the PCI device memory space for device
7821 * with SLI-3 interface spec.
7822 **/
7823static void
7824lpfc_sli_pci_mem_unset(struct lpfc_hba *phba)
7825{
7826 struct pci_dev *pdev;
7827
7828 /* Obtain PCI device reference */
7829 if (!phba->pcidev)
7830 return;
7831 else
7832 pdev = phba->pcidev;
7833
7834 /* Free coherent DMA memory allocated */
7835 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
7836 phba->hbqslimp.virt, phba->hbqslimp.phys);
7837 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
7838 phba->slim2p.virt, phba->slim2p.phys);
7839
7840 /* I/O memory unmap */
7841 iounmap(phba->ctrl_regs_memmap_p);
7842 iounmap(phba->slim_memmap_p);
7843
7844 return;
7845}
7846
7847/**
da0436e9 7848 * lpfc_sli4_post_status_check - Wait for SLI4 POST done and check status
3772a991
JS
7849 * @phba: pointer to lpfc hba data structure.
7850 *
da0436e9
JS
7851 * This routine is invoked to wait for SLI4 device Power On Self Test (POST)
7852 * done and check status.
3772a991 7853 *
da0436e9 7854 * Return 0 if successful, otherwise -ENODEV.
3772a991 7855 **/
da0436e9
JS
7856int
7857lpfc_sli4_post_status_check(struct lpfc_hba *phba)
3772a991 7858{
2fcee4bf
JS
7859 struct lpfc_register portsmphr_reg, uerrlo_reg, uerrhi_reg;
7860 struct lpfc_register reg_data;
7861 int i, port_error = 0;
7862 uint32_t if_type;
3772a991 7863
9940b97b
JS
7864 memset(&portsmphr_reg, 0, sizeof(portsmphr_reg));
7865 memset(&reg_data, 0, sizeof(reg_data));
2fcee4bf 7866 if (!phba->sli4_hba.PSMPHRregaddr)
da0436e9 7867 return -ENODEV;
3772a991 7868
da0436e9
JS
7869 /* Wait up to 30 seconds for the SLI Port POST done and ready */
7870 for (i = 0; i < 3000; i++) {
9940b97b
JS
7871 if (lpfc_readl(phba->sli4_hba.PSMPHRregaddr,
7872 &portsmphr_reg.word0) ||
7873 (bf_get(lpfc_port_smphr_perr, &portsmphr_reg))) {
2fcee4bf 7874 /* Port has a fatal POST error, break out */
da0436e9
JS
7875 port_error = -ENODEV;
7876 break;
7877 }
2fcee4bf
JS
7878 if (LPFC_POST_STAGE_PORT_READY ==
7879 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg))
da0436e9 7880 break;
da0436e9 7881 msleep(10);
3772a991
JS
7882 }
7883
2fcee4bf
JS
7884 /*
7885 * If there was a port error during POST, then don't proceed with
7886 * other register reads as the data may not be valid. Just exit.
7887 */
7888 if (port_error) {
da0436e9 7889 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
2fcee4bf
JS
7890 "1408 Port Failed POST - portsmphr=0x%x, "
7891 "perr=x%x, sfi=x%x, nip=x%x, ipc=x%x, scr1=x%x, "
7892 "scr2=x%x, hscratch=x%x, pstatus=x%x\n",
7893 portsmphr_reg.word0,
7894 bf_get(lpfc_port_smphr_perr, &portsmphr_reg),
7895 bf_get(lpfc_port_smphr_sfi, &portsmphr_reg),
7896 bf_get(lpfc_port_smphr_nip, &portsmphr_reg),
7897 bf_get(lpfc_port_smphr_ipc, &portsmphr_reg),
7898 bf_get(lpfc_port_smphr_scr1, &portsmphr_reg),
7899 bf_get(lpfc_port_smphr_scr2, &portsmphr_reg),
7900 bf_get(lpfc_port_smphr_host_scratch, &portsmphr_reg),
7901 bf_get(lpfc_port_smphr_port_status, &portsmphr_reg));
7902 } else {
28baac74 7903 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
2fcee4bf
JS
7904 "2534 Device Info: SLIFamily=0x%x, "
7905 "SLIRev=0x%x, IFType=0x%x, SLIHint_1=0x%x, "
7906 "SLIHint_2=0x%x, FT=0x%x\n",
28baac74
JS
7907 bf_get(lpfc_sli_intf_sli_family,
7908 &phba->sli4_hba.sli_intf),
7909 bf_get(lpfc_sli_intf_slirev,
7910 &phba->sli4_hba.sli_intf),
085c647c
JS
7911 bf_get(lpfc_sli_intf_if_type,
7912 &phba->sli4_hba.sli_intf),
7913 bf_get(lpfc_sli_intf_sli_hint1,
28baac74 7914 &phba->sli4_hba.sli_intf),
085c647c
JS
7915 bf_get(lpfc_sli_intf_sli_hint2,
7916 &phba->sli4_hba.sli_intf),
7917 bf_get(lpfc_sli_intf_func_type,
28baac74 7918 &phba->sli4_hba.sli_intf));
2fcee4bf
JS
7919 /*
7920 * Check for other Port errors during the initialization
7921 * process. Fail the load if the port did not come up
7922 * correctly.
7923 */
7924 if_type = bf_get(lpfc_sli_intf_if_type,
7925 &phba->sli4_hba.sli_intf);
7926 switch (if_type) {
7927 case LPFC_SLI_INTF_IF_TYPE_0:
7928 phba->sli4_hba.ue_mask_lo =
7929 readl(phba->sli4_hba.u.if_type0.UEMASKLOregaddr);
7930 phba->sli4_hba.ue_mask_hi =
7931 readl(phba->sli4_hba.u.if_type0.UEMASKHIregaddr);
7932 uerrlo_reg.word0 =
7933 readl(phba->sli4_hba.u.if_type0.UERRLOregaddr);
7934 uerrhi_reg.word0 =
7935 readl(phba->sli4_hba.u.if_type0.UERRHIregaddr);
7936 if ((~phba->sli4_hba.ue_mask_lo & uerrlo_reg.word0) ||
7937 (~phba->sli4_hba.ue_mask_hi & uerrhi_reg.word0)) {
7938 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
7939 "1422 Unrecoverable Error "
7940 "Detected during POST "
7941 "uerr_lo_reg=0x%x, "
7942 "uerr_hi_reg=0x%x, "
7943 "ue_mask_lo_reg=0x%x, "
7944 "ue_mask_hi_reg=0x%x\n",
7945 uerrlo_reg.word0,
7946 uerrhi_reg.word0,
7947 phba->sli4_hba.ue_mask_lo,
7948 phba->sli4_hba.ue_mask_hi);
7949 port_error = -ENODEV;
7950 }
7951 break;
7952 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 7953 case LPFC_SLI_INTF_IF_TYPE_6:
2fcee4bf 7954 /* Final checks. The port status should be clean. */
9940b97b
JS
7955 if (lpfc_readl(phba->sli4_hba.u.if_type2.STATUSregaddr,
7956 &reg_data.word0) ||
0558056c
JS
7957 (bf_get(lpfc_sliport_status_err, &reg_data) &&
7958 !bf_get(lpfc_sliport_status_rn, &reg_data))) {
2fcee4bf
JS
7959 phba->work_status[0] =
7960 readl(phba->sli4_hba.u.if_type2.
7961 ERR1regaddr);
7962 phba->work_status[1] =
7963 readl(phba->sli4_hba.u.if_type2.
7964 ERR2regaddr);
7965 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8fcb8acd
JS
7966 "2888 Unrecoverable port error "
7967 "following POST: port status reg "
7968 "0x%x, port_smphr reg 0x%x, "
2fcee4bf
JS
7969 "error 1=0x%x, error 2=0x%x\n",
7970 reg_data.word0,
7971 portsmphr_reg.word0,
7972 phba->work_status[0],
7973 phba->work_status[1]);
7974 port_error = -ENODEV;
7975 }
7976 break;
7977 case LPFC_SLI_INTF_IF_TYPE_1:
7978 default:
7979 break;
7980 }
28baac74 7981 }
da0436e9
JS
7982 return port_error;
7983}
3772a991 7984
da0436e9
JS
7985/**
7986 * lpfc_sli4_bar0_register_memmap - Set up SLI4 BAR0 register memory map.
7987 * @phba: pointer to lpfc hba data structure.
2fcee4bf 7988 * @if_type: The SLI4 interface type getting configured.
da0436e9
JS
7989 *
7990 * This routine is invoked to set up SLI4 BAR0 PCI config space register
7991 * memory map.
7992 **/
7993static void
2fcee4bf
JS
7994lpfc_sli4_bar0_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
7995{
7996 switch (if_type) {
7997 case LPFC_SLI_INTF_IF_TYPE_0:
7998 phba->sli4_hba.u.if_type0.UERRLOregaddr =
7999 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_LO;
8000 phba->sli4_hba.u.if_type0.UERRHIregaddr =
8001 phba->sli4_hba.conf_regs_memmap_p + LPFC_UERR_STATUS_HI;
8002 phba->sli4_hba.u.if_type0.UEMASKLOregaddr =
8003 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_LO;
8004 phba->sli4_hba.u.if_type0.UEMASKHIregaddr =
8005 phba->sli4_hba.conf_regs_memmap_p + LPFC_UE_MASK_HI;
8006 phba->sli4_hba.SLIINTFregaddr =
8007 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
8008 break;
8009 case LPFC_SLI_INTF_IF_TYPE_2:
0cf07f84
JS
8010 phba->sli4_hba.u.if_type2.EQDregaddr =
8011 phba->sli4_hba.conf_regs_memmap_p +
8012 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
2fcee4bf 8013 phba->sli4_hba.u.if_type2.ERR1regaddr =
88a2cfbb
JS
8014 phba->sli4_hba.conf_regs_memmap_p +
8015 LPFC_CTL_PORT_ER1_OFFSET;
2fcee4bf 8016 phba->sli4_hba.u.if_type2.ERR2regaddr =
88a2cfbb
JS
8017 phba->sli4_hba.conf_regs_memmap_p +
8018 LPFC_CTL_PORT_ER2_OFFSET;
2fcee4bf 8019 phba->sli4_hba.u.if_type2.CTRLregaddr =
88a2cfbb
JS
8020 phba->sli4_hba.conf_regs_memmap_p +
8021 LPFC_CTL_PORT_CTL_OFFSET;
2fcee4bf 8022 phba->sli4_hba.u.if_type2.STATUSregaddr =
88a2cfbb
JS
8023 phba->sli4_hba.conf_regs_memmap_p +
8024 LPFC_CTL_PORT_STA_OFFSET;
2fcee4bf
JS
8025 phba->sli4_hba.SLIINTFregaddr =
8026 phba->sli4_hba.conf_regs_memmap_p + LPFC_SLI_INTF;
8027 phba->sli4_hba.PSMPHRregaddr =
88a2cfbb
JS
8028 phba->sli4_hba.conf_regs_memmap_p +
8029 LPFC_CTL_PORT_SEM_OFFSET;
2fcee4bf 8030 phba->sli4_hba.RQDBregaddr =
962bc51b
JS
8031 phba->sli4_hba.conf_regs_memmap_p +
8032 LPFC_ULP0_RQ_DOORBELL;
2fcee4bf 8033 phba->sli4_hba.WQDBregaddr =
962bc51b
JS
8034 phba->sli4_hba.conf_regs_memmap_p +
8035 LPFC_ULP0_WQ_DOORBELL;
9dd35425 8036 phba->sli4_hba.CQDBregaddr =
2fcee4bf 8037 phba->sli4_hba.conf_regs_memmap_p + LPFC_EQCQ_DOORBELL;
9dd35425 8038 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
2fcee4bf
JS
8039 phba->sli4_hba.MQDBregaddr =
8040 phba->sli4_hba.conf_regs_memmap_p + LPFC_MQ_DOORBELL;
8041 phba->sli4_hba.BMBXregaddr =
8042 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
8043 break;
27d6ac0a
JS
8044 case LPFC_SLI_INTF_IF_TYPE_6:
8045 phba->sli4_hba.u.if_type2.EQDregaddr =
8046 phba->sli4_hba.conf_regs_memmap_p +
8047 LPFC_CTL_PORT_EQ_DELAY_OFFSET;
8048 phba->sli4_hba.u.if_type2.ERR1regaddr =
8049 phba->sli4_hba.conf_regs_memmap_p +
8050 LPFC_CTL_PORT_ER1_OFFSET;
8051 phba->sli4_hba.u.if_type2.ERR2regaddr =
8052 phba->sli4_hba.conf_regs_memmap_p +
8053 LPFC_CTL_PORT_ER2_OFFSET;
8054 phba->sli4_hba.u.if_type2.CTRLregaddr =
8055 phba->sli4_hba.conf_regs_memmap_p +
8056 LPFC_CTL_PORT_CTL_OFFSET;
8057 phba->sli4_hba.u.if_type2.STATUSregaddr =
8058 phba->sli4_hba.conf_regs_memmap_p +
8059 LPFC_CTL_PORT_STA_OFFSET;
8060 phba->sli4_hba.PSMPHRregaddr =
8061 phba->sli4_hba.conf_regs_memmap_p +
8062 LPFC_CTL_PORT_SEM_OFFSET;
8063 phba->sli4_hba.BMBXregaddr =
8064 phba->sli4_hba.conf_regs_memmap_p + LPFC_BMBX;
8065 break;
2fcee4bf
JS
8066 case LPFC_SLI_INTF_IF_TYPE_1:
8067 default:
8068 dev_printk(KERN_ERR, &phba->pcidev->dev,
8069 "FATAL - unsupported SLI4 interface type - %d\n",
8070 if_type);
8071 break;
8072 }
da0436e9 8073}
3772a991 8074
da0436e9
JS
8075/**
8076 * lpfc_sli4_bar1_register_memmap - Set up SLI4 BAR1 register memory map.
8077 * @phba: pointer to lpfc hba data structure.
8078 *
27d6ac0a 8079 * This routine is invoked to set up SLI4 BAR1 register memory map.
da0436e9
JS
8080 **/
8081static void
27d6ac0a 8082lpfc_sli4_bar1_register_memmap(struct lpfc_hba *phba, uint32_t if_type)
da0436e9 8083{
27d6ac0a
JS
8084 switch (if_type) {
8085 case LPFC_SLI_INTF_IF_TYPE_0:
8086 phba->sli4_hba.PSMPHRregaddr =
8087 phba->sli4_hba.ctrl_regs_memmap_p +
8088 LPFC_SLIPORT_IF0_SMPHR;
8089 phba->sli4_hba.ISRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8090 LPFC_HST_ISR0;
8091 phba->sli4_hba.IMRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8092 LPFC_HST_IMR0;
8093 phba->sli4_hba.ISCRregaddr = phba->sli4_hba.ctrl_regs_memmap_p +
8094 LPFC_HST_ISCR0;
8095 break;
8096 case LPFC_SLI_INTF_IF_TYPE_6:
8097 phba->sli4_hba.RQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8098 LPFC_IF6_RQ_DOORBELL;
8099 phba->sli4_hba.WQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8100 LPFC_IF6_WQ_DOORBELL;
8101 phba->sli4_hba.CQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8102 LPFC_IF6_CQ_DOORBELL;
8103 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8104 LPFC_IF6_EQ_DOORBELL;
8105 phba->sli4_hba.MQDBregaddr = phba->sli4_hba.drbl_regs_memmap_p +
8106 LPFC_IF6_MQ_DOORBELL;
8107 break;
8108 case LPFC_SLI_INTF_IF_TYPE_2:
8109 case LPFC_SLI_INTF_IF_TYPE_1:
8110 default:
8111 dev_err(&phba->pcidev->dev,
8112 "FATAL - unsupported SLI4 interface type - %d\n",
8113 if_type);
8114 break;
8115 }
3772a991
JS
8116}
8117
8118/**
da0436e9 8119 * lpfc_sli4_bar2_register_memmap - Set up SLI4 BAR2 register memory map.
3772a991 8120 * @phba: pointer to lpfc hba data structure.
da0436e9 8121 * @vf: virtual function number
3772a991 8122 *
da0436e9
JS
8123 * This routine is invoked to set up SLI4 BAR2 doorbell register memory map
8124 * based on the given viftual function number, @vf.
8125 *
8126 * Return 0 if successful, otherwise -ENODEV.
3772a991 8127 **/
da0436e9
JS
8128static int
8129lpfc_sli4_bar2_register_memmap(struct lpfc_hba *phba, uint32_t vf)
3772a991 8130{
da0436e9
JS
8131 if (vf > LPFC_VIR_FUNC_MAX)
8132 return -ENODEV;
3772a991 8133
da0436e9 8134 phba->sli4_hba.RQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
962bc51b
JS
8135 vf * LPFC_VFR_PAGE_SIZE +
8136 LPFC_ULP0_RQ_DOORBELL);
da0436e9 8137 phba->sli4_hba.WQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
962bc51b
JS
8138 vf * LPFC_VFR_PAGE_SIZE +
8139 LPFC_ULP0_WQ_DOORBELL);
9dd35425
JS
8140 phba->sli4_hba.CQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8141 vf * LPFC_VFR_PAGE_SIZE +
8142 LPFC_EQCQ_DOORBELL);
8143 phba->sli4_hba.EQDBregaddr = phba->sli4_hba.CQDBregaddr;
da0436e9
JS
8144 phba->sli4_hba.MQDBregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8145 vf * LPFC_VFR_PAGE_SIZE + LPFC_MQ_DOORBELL);
8146 phba->sli4_hba.BMBXregaddr = (phba->sli4_hba.drbl_regs_memmap_p +
8147 vf * LPFC_VFR_PAGE_SIZE + LPFC_BMBX);
8148 return 0;
3772a991
JS
8149}
8150
8151/**
da0436e9 8152 * lpfc_create_bootstrap_mbox - Create the bootstrap mailbox
3772a991
JS
8153 * @phba: pointer to lpfc hba data structure.
8154 *
da0436e9
JS
8155 * This routine is invoked to create the bootstrap mailbox
8156 * region consistent with the SLI-4 interface spec. This
8157 * routine allocates all memory necessary to communicate
8158 * mailbox commands to the port and sets up all alignment
8159 * needs. No locks are expected to be held when calling
8160 * this routine.
3772a991
JS
8161 *
8162 * Return codes
af901ca1 8163 * 0 - successful
d439d286 8164 * -ENOMEM - could not allocated memory.
da0436e9 8165 **/
3772a991 8166static int
da0436e9 8167lpfc_create_bootstrap_mbox(struct lpfc_hba *phba)
3772a991 8168{
da0436e9
JS
8169 uint32_t bmbx_size;
8170 struct lpfc_dmabuf *dmabuf;
8171 struct dma_address *dma_address;
8172 uint32_t pa_addr;
8173 uint64_t phys_addr;
8174
8175 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf), GFP_KERNEL);
8176 if (!dmabuf)
8177 return -ENOMEM;
3772a991 8178
da0436e9
JS
8179 /*
8180 * The bootstrap mailbox region is comprised of 2 parts
8181 * plus an alignment restriction of 16 bytes.
8182 */
8183 bmbx_size = sizeof(struct lpfc_bmbx_create) + (LPFC_ALIGN_16_BYTE - 1);
750afb08
LC
8184 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev, bmbx_size,
8185 &dmabuf->phys, GFP_KERNEL);
da0436e9
JS
8186 if (!dmabuf->virt) {
8187 kfree(dmabuf);
8188 return -ENOMEM;
3772a991
JS
8189 }
8190
da0436e9
JS
8191 /*
8192 * Initialize the bootstrap mailbox pointers now so that the register
8193 * operations are simple later. The mailbox dma address is required
8194 * to be 16-byte aligned. Also align the virtual memory as each
8195 * maibox is copied into the bmbx mailbox region before issuing the
8196 * command to the port.
8197 */
8198 phba->sli4_hba.bmbx.dmabuf = dmabuf;
8199 phba->sli4_hba.bmbx.bmbx_size = bmbx_size;
8200
8201 phba->sli4_hba.bmbx.avirt = PTR_ALIGN(dmabuf->virt,
8202 LPFC_ALIGN_16_BYTE);
8203 phba->sli4_hba.bmbx.aphys = ALIGN(dmabuf->phys,
8204 LPFC_ALIGN_16_BYTE);
8205
8206 /*
8207 * Set the high and low physical addresses now. The SLI4 alignment
8208 * requirement is 16 bytes and the mailbox is posted to the port
8209 * as two 30-bit addresses. The other data is a bit marking whether
8210 * the 30-bit address is the high or low address.
8211 * Upcast bmbx aphys to 64bits so shift instruction compiles
8212 * clean on 32 bit machines.
8213 */
8214 dma_address = &phba->sli4_hba.bmbx.dma_address;
8215 phys_addr = (uint64_t)phba->sli4_hba.bmbx.aphys;
8216 pa_addr = (uint32_t) ((phys_addr >> 34) & 0x3fffffff);
8217 dma_address->addr_hi = (uint32_t) ((pa_addr << 2) |
8218 LPFC_BMBX_BIT1_ADDR_HI);
8219
8220 pa_addr = (uint32_t) ((phba->sli4_hba.bmbx.aphys >> 4) & 0x3fffffff);
8221 dma_address->addr_lo = (uint32_t) ((pa_addr << 2) |
8222 LPFC_BMBX_BIT1_ADDR_LO);
8223 return 0;
3772a991
JS
8224}
8225
8226/**
da0436e9 8227 * lpfc_destroy_bootstrap_mbox - Destroy all bootstrap mailbox resources
3772a991
JS
8228 * @phba: pointer to lpfc hba data structure.
8229 *
da0436e9
JS
8230 * This routine is invoked to teardown the bootstrap mailbox
8231 * region and release all host resources. This routine requires
8232 * the caller to ensure all mailbox commands recovered, no
8233 * additional mailbox comands are sent, and interrupts are disabled
8234 * before calling this routine.
8235 *
8236 **/
3772a991 8237static void
da0436e9 8238lpfc_destroy_bootstrap_mbox(struct lpfc_hba *phba)
3772a991 8239{
da0436e9
JS
8240 dma_free_coherent(&phba->pcidev->dev,
8241 phba->sli4_hba.bmbx.bmbx_size,
8242 phba->sli4_hba.bmbx.dmabuf->virt,
8243 phba->sli4_hba.bmbx.dmabuf->phys);
8244
8245 kfree(phba->sli4_hba.bmbx.dmabuf);
8246 memset(&phba->sli4_hba.bmbx, 0, sizeof(struct lpfc_bmbx));
3772a991
JS
8247}
8248
8249/**
da0436e9 8250 * lpfc_sli4_read_config - Get the config parameters.
3772a991
JS
8251 * @phba: pointer to lpfc hba data structure.
8252 *
da0436e9
JS
8253 * This routine is invoked to read the configuration parameters from the HBA.
8254 * The configuration parameters are used to set the base and maximum values
8255 * for RPI's XRI's VPI's VFI's and FCFIs. These values also affect the resource
8256 * allocation for the port.
3772a991
JS
8257 *
8258 * Return codes
af901ca1 8259 * 0 - successful
25985edc 8260 * -ENOMEM - No available memory
d439d286 8261 * -EIO - The mailbox failed to complete successfully.
3772a991 8262 **/
ff78d8f9 8263int
da0436e9 8264lpfc_sli4_read_config(struct lpfc_hba *phba)
3772a991 8265{
da0436e9
JS
8266 LPFC_MBOXQ_t *pmb;
8267 struct lpfc_mbx_read_config *rd_config;
912e3acd
JS
8268 union lpfc_sli4_cfg_shdr *shdr;
8269 uint32_t shdr_status, shdr_add_status;
8270 struct lpfc_mbx_get_func_cfg *get_func_cfg;
8271 struct lpfc_rsrc_desc_fcfcoe *desc;
8aa134a8 8272 char *pdesc_0;
c691816e 8273 uint16_t forced_link_speed;
6a828b0f 8274 uint32_t if_type, qmin;
8aa134a8 8275 int length, i, rc = 0, rc2;
3772a991 8276
da0436e9
JS
8277 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
8278 if (!pmb) {
8279 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8280 "2011 Unable to allocate memory for issuing "
8281 "SLI_CONFIG_SPECIAL mailbox command\n");
8282 return -ENOMEM;
3772a991
JS
8283 }
8284
da0436e9 8285 lpfc_read_config(phba, pmb);
3772a991 8286
da0436e9
JS
8287 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
8288 if (rc != MBX_SUCCESS) {
8289 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8290 "2012 Mailbox failed , mbxCmd x%x "
8291 "READ_CONFIG, mbxStatus x%x\n",
8292 bf_get(lpfc_mqe_command, &pmb->u.mqe),
8293 bf_get(lpfc_mqe_status, &pmb->u.mqe));
8294 rc = -EIO;
8295 } else {
8296 rd_config = &pmb->u.mqe.un.rd_config;
ff78d8f9
JS
8297 if (bf_get(lpfc_mbx_rd_conf_lnk_ldv, rd_config)) {
8298 phba->sli4_hba.lnk_info.lnk_dv = LPFC_LNK_DAT_VAL;
8299 phba->sli4_hba.lnk_info.lnk_tp =
8300 bf_get(lpfc_mbx_rd_conf_lnk_type, rd_config);
8301 phba->sli4_hba.lnk_info.lnk_no =
8302 bf_get(lpfc_mbx_rd_conf_lnk_numb, rd_config);
8303 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8304 "3081 lnk_type:%d, lnk_numb:%d\n",
8305 phba->sli4_hba.lnk_info.lnk_tp,
8306 phba->sli4_hba.lnk_info.lnk_no);
8307 } else
8308 lpfc_printf_log(phba, KERN_WARNING, LOG_SLI,
8309 "3082 Mailbox (x%x) returned ldv:x0\n",
8310 bf_get(lpfc_mqe_command, &pmb->u.mqe));
44fd7fe3
JS
8311 if (bf_get(lpfc_mbx_rd_conf_bbscn_def, rd_config)) {
8312 phba->bbcredit_support = 1;
8313 phba->sli4_hba.bbscn_params.word0 = rd_config->word8;
8314 }
8315
1dc5ec24
JS
8316 phba->sli4_hba.conf_trunk =
8317 bf_get(lpfc_mbx_rd_conf_trunk, rd_config);
6d368e53
JS
8318 phba->sli4_hba.extents_in_use =
8319 bf_get(lpfc_mbx_rd_conf_extnts_inuse, rd_config);
da0436e9
JS
8320 phba->sli4_hba.max_cfg_param.max_xri =
8321 bf_get(lpfc_mbx_rd_conf_xri_count, rd_config);
31f06d2e
JS
8322 /* Reduce resource usage in kdump environment */
8323 if (is_kdump_kernel() &&
8324 phba->sli4_hba.max_cfg_param.max_xri > 512)
8325 phba->sli4_hba.max_cfg_param.max_xri = 512;
da0436e9
JS
8326 phba->sli4_hba.max_cfg_param.xri_base =
8327 bf_get(lpfc_mbx_rd_conf_xri_base, rd_config);
8328 phba->sli4_hba.max_cfg_param.max_vpi =
8329 bf_get(lpfc_mbx_rd_conf_vpi_count, rd_config);
8b47ae69
JS
8330 /* Limit the max we support */
8331 if (phba->sli4_hba.max_cfg_param.max_vpi > LPFC_MAX_VPORTS)
8332 phba->sli4_hba.max_cfg_param.max_vpi = LPFC_MAX_VPORTS;
da0436e9
JS
8333 phba->sli4_hba.max_cfg_param.vpi_base =
8334 bf_get(lpfc_mbx_rd_conf_vpi_base, rd_config);
8335 phba->sli4_hba.max_cfg_param.max_rpi =
8336 bf_get(lpfc_mbx_rd_conf_rpi_count, rd_config);
8337 phba->sli4_hba.max_cfg_param.rpi_base =
8338 bf_get(lpfc_mbx_rd_conf_rpi_base, rd_config);
8339 phba->sli4_hba.max_cfg_param.max_vfi =
8340 bf_get(lpfc_mbx_rd_conf_vfi_count, rd_config);
8341 phba->sli4_hba.max_cfg_param.vfi_base =
8342 bf_get(lpfc_mbx_rd_conf_vfi_base, rd_config);
8343 phba->sli4_hba.max_cfg_param.max_fcfi =
8344 bf_get(lpfc_mbx_rd_conf_fcfi_count, rd_config);
da0436e9
JS
8345 phba->sli4_hba.max_cfg_param.max_eq =
8346 bf_get(lpfc_mbx_rd_conf_eq_count, rd_config);
8347 phba->sli4_hba.max_cfg_param.max_rq =
8348 bf_get(lpfc_mbx_rd_conf_rq_count, rd_config);
8349 phba->sli4_hba.max_cfg_param.max_wq =
8350 bf_get(lpfc_mbx_rd_conf_wq_count, rd_config);
8351 phba->sli4_hba.max_cfg_param.max_cq =
8352 bf_get(lpfc_mbx_rd_conf_cq_count, rd_config);
8353 phba->lmt = bf_get(lpfc_mbx_rd_conf_lmt, rd_config);
8354 phba->sli4_hba.next_xri = phba->sli4_hba.max_cfg_param.xri_base;
8355 phba->vpi_base = phba->sli4_hba.max_cfg_param.vpi_base;
8356 phba->vfi_base = phba->sli4_hba.max_cfg_param.vfi_base;
5ffc266e
JS
8357 phba->max_vpi = (phba->sli4_hba.max_cfg_param.max_vpi > 0) ?
8358 (phba->sli4_hba.max_cfg_param.max_vpi - 1) : 0;
da0436e9
JS
8359 phba->max_vports = phba->max_vpi;
8360 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
6d368e53
JS
8361 "2003 cfg params Extents? %d "
8362 "XRI(B:%d M:%d), "
da0436e9
JS
8363 "VPI(B:%d M:%d) "
8364 "VFI(B:%d M:%d) "
8365 "RPI(B:%d M:%d) "
2ea259ee 8366 "FCFI:%d EQ:%d CQ:%d WQ:%d RQ:%d\n",
6d368e53 8367 phba->sli4_hba.extents_in_use,
da0436e9
JS
8368 phba->sli4_hba.max_cfg_param.xri_base,
8369 phba->sli4_hba.max_cfg_param.max_xri,
8370 phba->sli4_hba.max_cfg_param.vpi_base,
8371 phba->sli4_hba.max_cfg_param.max_vpi,
8372 phba->sli4_hba.max_cfg_param.vfi_base,
8373 phba->sli4_hba.max_cfg_param.max_vfi,
8374 phba->sli4_hba.max_cfg_param.rpi_base,
8375 phba->sli4_hba.max_cfg_param.max_rpi,
2ea259ee
JS
8376 phba->sli4_hba.max_cfg_param.max_fcfi,
8377 phba->sli4_hba.max_cfg_param.max_eq,
8378 phba->sli4_hba.max_cfg_param.max_cq,
8379 phba->sli4_hba.max_cfg_param.max_wq,
8380 phba->sli4_hba.max_cfg_param.max_rq);
8381
d38f33b3 8382 /*
6a828b0f
JS
8383 * Calculate queue resources based on how
8384 * many WQ/CQ/EQs are available.
d38f33b3 8385 */
6a828b0f
JS
8386 qmin = phba->sli4_hba.max_cfg_param.max_wq;
8387 if (phba->sli4_hba.max_cfg_param.max_cq < qmin)
8388 qmin = phba->sli4_hba.max_cfg_param.max_cq;
8389 if (phba->sli4_hba.max_cfg_param.max_eq < qmin)
8390 qmin = phba->sli4_hba.max_cfg_param.max_eq;
8391 /*
8392 * Whats left after this can go toward NVME / FCP.
8393 * The minus 4 accounts for ELS, NVME LS, MBOX
8394 * plus one extra. When configured for
8395 * NVMET, FCP io channel WQs are not created.
8396 */
8397 qmin -= 4;
d38f33b3 8398
6a828b0f
JS
8399 /* Check to see if there is enough for NVME */
8400 if ((phba->cfg_irq_chann > qmin) ||
8401 (phba->cfg_hdw_queue > qmin)) {
8402 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8403 "2005 Reducing Queues: "
8404 "WQ %d CQ %d EQ %d: min %d: "
8405 "IRQ %d HDWQ %d\n",
d38f33b3
JS
8406 phba->sli4_hba.max_cfg_param.max_wq,
8407 phba->sli4_hba.max_cfg_param.max_cq,
6a828b0f
JS
8408 phba->sli4_hba.max_cfg_param.max_eq,
8409 qmin, phba->cfg_irq_chann,
cdb42bec 8410 phba->cfg_hdw_queue);
d38f33b3 8411
6a828b0f
JS
8412 if (phba->cfg_irq_chann > qmin)
8413 phba->cfg_irq_chann = qmin;
8414 if (phba->cfg_hdw_queue > qmin)
8415 phba->cfg_hdw_queue = qmin;
d38f33b3 8416 }
3772a991 8417 }
912e3acd
JS
8418
8419 if (rc)
8420 goto read_cfg_out;
da0436e9 8421
c691816e
JS
8422 /* Update link speed if forced link speed is supported */
8423 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
27d6ac0a 8424 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
c691816e
JS
8425 forced_link_speed =
8426 bf_get(lpfc_mbx_rd_conf_link_speed, rd_config);
8427 if (forced_link_speed) {
8428 phba->hba_flag |= HBA_FORCED_LINK_SPEED;
8429
8430 switch (forced_link_speed) {
8431 case LINK_SPEED_1G:
8432 phba->cfg_link_speed =
8433 LPFC_USER_LINK_SPEED_1G;
8434 break;
8435 case LINK_SPEED_2G:
8436 phba->cfg_link_speed =
8437 LPFC_USER_LINK_SPEED_2G;
8438 break;
8439 case LINK_SPEED_4G:
8440 phba->cfg_link_speed =
8441 LPFC_USER_LINK_SPEED_4G;
8442 break;
8443 case LINK_SPEED_8G:
8444 phba->cfg_link_speed =
8445 LPFC_USER_LINK_SPEED_8G;
8446 break;
8447 case LINK_SPEED_10G:
8448 phba->cfg_link_speed =
8449 LPFC_USER_LINK_SPEED_10G;
8450 break;
8451 case LINK_SPEED_16G:
8452 phba->cfg_link_speed =
8453 LPFC_USER_LINK_SPEED_16G;
8454 break;
8455 case LINK_SPEED_32G:
8456 phba->cfg_link_speed =
8457 LPFC_USER_LINK_SPEED_32G;
8458 break;
fbd8a6ba
JS
8459 case LINK_SPEED_64G:
8460 phba->cfg_link_speed =
8461 LPFC_USER_LINK_SPEED_64G;
8462 break;
c691816e
JS
8463 case 0xffff:
8464 phba->cfg_link_speed =
8465 LPFC_USER_LINK_SPEED_AUTO;
8466 break;
8467 default:
8468 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8469 "0047 Unrecognized link "
8470 "speed : %d\n",
8471 forced_link_speed);
8472 phba->cfg_link_speed =
8473 LPFC_USER_LINK_SPEED_AUTO;
8474 }
8475 }
8476 }
8477
da0436e9 8478 /* Reset the DFT_HBA_Q_DEPTH to the max xri */
572709e2
JS
8479 length = phba->sli4_hba.max_cfg_param.max_xri -
8480 lpfc_sli4_get_els_iocb_cnt(phba);
8481 if (phba->cfg_hba_queue_depth > length) {
8482 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
8483 "3361 HBA queue depth changed from %d to %d\n",
8484 phba->cfg_hba_queue_depth, length);
8485 phba->cfg_hba_queue_depth = length;
8486 }
912e3acd 8487
27d6ac0a 8488 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
912e3acd
JS
8489 LPFC_SLI_INTF_IF_TYPE_2)
8490 goto read_cfg_out;
8491
8492 /* get the pf# and vf# for SLI4 if_type 2 port */
8493 length = (sizeof(struct lpfc_mbx_get_func_cfg) -
8494 sizeof(struct lpfc_sli4_cfg_mhdr));
8495 lpfc_sli4_config(phba, pmb, LPFC_MBOX_SUBSYSTEM_COMMON,
8496 LPFC_MBOX_OPCODE_GET_FUNCTION_CONFIG,
8497 length, LPFC_SLI4_MBX_EMBED);
8498
8aa134a8 8499 rc2 = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
912e3acd
JS
8500 shdr = (union lpfc_sli4_cfg_shdr *)
8501 &pmb->u.mqe.un.sli4_config.header.cfg_shdr;
8502 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
8503 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
8aa134a8 8504 if (rc2 || shdr_status || shdr_add_status) {
912e3acd
JS
8505 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8506 "3026 Mailbox failed , mbxCmd x%x "
8507 "GET_FUNCTION_CONFIG, mbxStatus x%x\n",
8508 bf_get(lpfc_mqe_command, &pmb->u.mqe),
8509 bf_get(lpfc_mqe_status, &pmb->u.mqe));
912e3acd
JS
8510 goto read_cfg_out;
8511 }
8512
8513 /* search for fc_fcoe resrouce descriptor */
8514 get_func_cfg = &pmb->u.mqe.un.get_func_cfg;
912e3acd 8515
8aa134a8
JS
8516 pdesc_0 = (char *)&get_func_cfg->func_cfg.desc[0];
8517 desc = (struct lpfc_rsrc_desc_fcfcoe *)pdesc_0;
8518 length = bf_get(lpfc_rsrc_desc_fcfcoe_length, desc);
8519 if (length == LPFC_RSRC_DESC_TYPE_FCFCOE_V0_RSVD)
8520 length = LPFC_RSRC_DESC_TYPE_FCFCOE_V0_LENGTH;
8521 else if (length != LPFC_RSRC_DESC_TYPE_FCFCOE_V1_LENGTH)
8522 goto read_cfg_out;
8523
912e3acd 8524 for (i = 0; i < LPFC_RSRC_DESC_MAX_NUM; i++) {
8aa134a8 8525 desc = (struct lpfc_rsrc_desc_fcfcoe *)(pdesc_0 + length * i);
912e3acd 8526 if (LPFC_RSRC_DESC_TYPE_FCFCOE ==
8aa134a8 8527 bf_get(lpfc_rsrc_desc_fcfcoe_type, desc)) {
912e3acd
JS
8528 phba->sli4_hba.iov.pf_number =
8529 bf_get(lpfc_rsrc_desc_fcfcoe_pfnum, desc);
8530 phba->sli4_hba.iov.vf_number =
8531 bf_get(lpfc_rsrc_desc_fcfcoe_vfnum, desc);
8532 break;
8533 }
8534 }
8535
8536 if (i < LPFC_RSRC_DESC_MAX_NUM)
8537 lpfc_printf_log(phba, KERN_INFO, LOG_SLI,
8538 "3027 GET_FUNCTION_CONFIG: pf_number:%d, "
8539 "vf_number:%d\n", phba->sli4_hba.iov.pf_number,
8540 phba->sli4_hba.iov.vf_number);
8aa134a8 8541 else
912e3acd
JS
8542 lpfc_printf_log(phba, KERN_ERR, LOG_SLI,
8543 "3028 GET_FUNCTION_CONFIG: failed to find "
c4dba187 8544 "Resource Descriptor:x%x\n",
912e3acd 8545 LPFC_RSRC_DESC_TYPE_FCFCOE);
912e3acd
JS
8546
8547read_cfg_out:
8548 mempool_free(pmb, phba->mbox_mem_pool);
da0436e9 8549 return rc;
3772a991
JS
8550}
8551
8552/**
2fcee4bf 8553 * lpfc_setup_endian_order - Write endian order to an SLI4 if_type 0 port.
3772a991
JS
8554 * @phba: pointer to lpfc hba data structure.
8555 *
2fcee4bf
JS
8556 * This routine is invoked to setup the port-side endian order when
8557 * the port if_type is 0. This routine has no function for other
8558 * if_types.
da0436e9
JS
8559 *
8560 * Return codes
af901ca1 8561 * 0 - successful
25985edc 8562 * -ENOMEM - No available memory
d439d286 8563 * -EIO - The mailbox failed to complete successfully.
3772a991 8564 **/
da0436e9
JS
8565static int
8566lpfc_setup_endian_order(struct lpfc_hba *phba)
3772a991 8567{
da0436e9 8568 LPFC_MBOXQ_t *mboxq;
2fcee4bf 8569 uint32_t if_type, rc = 0;
da0436e9
JS
8570 uint32_t endian_mb_data[2] = {HOST_ENDIAN_LOW_WORD0,
8571 HOST_ENDIAN_HIGH_WORD1};
3772a991 8572
2fcee4bf
JS
8573 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
8574 switch (if_type) {
8575 case LPFC_SLI_INTF_IF_TYPE_0:
8576 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
8577 GFP_KERNEL);
8578 if (!mboxq) {
8579 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8580 "0492 Unable to allocate memory for "
8581 "issuing SLI_CONFIG_SPECIAL mailbox "
8582 "command\n");
8583 return -ENOMEM;
8584 }
3772a991 8585
2fcee4bf
JS
8586 /*
8587 * The SLI4_CONFIG_SPECIAL mailbox command requires the first
8588 * two words to contain special data values and no other data.
8589 */
8590 memset(mboxq, 0, sizeof(LPFC_MBOXQ_t));
8591 memcpy(&mboxq->u.mqe, &endian_mb_data, sizeof(endian_mb_data));
8592 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
8593 if (rc != MBX_SUCCESS) {
8594 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8595 "0493 SLI_CONFIG_SPECIAL mailbox "
8596 "failed with status x%x\n",
8597 rc);
8598 rc = -EIO;
8599 }
8600 mempool_free(mboxq, phba->mbox_mem_pool);
8601 break;
27d6ac0a 8602 case LPFC_SLI_INTF_IF_TYPE_6:
2fcee4bf
JS
8603 case LPFC_SLI_INTF_IF_TYPE_2:
8604 case LPFC_SLI_INTF_IF_TYPE_1:
8605 default:
8606 break;
da0436e9 8607 }
da0436e9 8608 return rc;
3772a991
JS
8609}
8610
8611/**
895427bd 8612 * lpfc_sli4_queue_verify - Verify and update EQ counts
3772a991
JS
8613 * @phba: pointer to lpfc hba data structure.
8614 *
895427bd
JS
8615 * This routine is invoked to check the user settable queue counts for EQs.
8616 * After this routine is called the counts will be set to valid values that
5350d872
JS
8617 * adhere to the constraints of the system's interrupt vectors and the port's
8618 * queue resources.
da0436e9
JS
8619 *
8620 * Return codes
af901ca1 8621 * 0 - successful
25985edc 8622 * -ENOMEM - No available memory
3772a991 8623 **/
da0436e9 8624static int
5350d872 8625lpfc_sli4_queue_verify(struct lpfc_hba *phba)
3772a991 8626{
da0436e9 8627 /*
67d12733 8628 * Sanity check for configured queue parameters against the run-time
da0436e9
JS
8629 * device parameters
8630 */
3772a991 8631
bcb24f65 8632 if (phba->nvmet_support) {
97a9ed3b
JS
8633 if (phba->cfg_hdw_queue < phba->cfg_nvmet_mrq)
8634 phba->cfg_nvmet_mrq = phba->cfg_hdw_queue;
982ab128
JS
8635 if (phba->cfg_nvmet_mrq > LPFC_NVMET_MRQ_MAX)
8636 phba->cfg_nvmet_mrq = LPFC_NVMET_MRQ_MAX;
bcb24f65 8637 }
895427bd
JS
8638
8639 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6a828b0f
JS
8640 "2574 IO channels: hdwQ %d IRQ %d MRQ: %d\n",
8641 phba->cfg_hdw_queue, phba->cfg_irq_chann,
8642 phba->cfg_nvmet_mrq);
3772a991 8643
da0436e9
JS
8644 /* Get EQ depth from module parameter, fake the default for now */
8645 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
8646 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
3772a991 8647
5350d872
JS
8648 /* Get CQ depth from module parameter, fake the default for now */
8649 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
8650 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
895427bd
JS
8651 return 0;
8652}
8653
8654static int
c00f62e6 8655lpfc_alloc_io_wq_cq(struct lpfc_hba *phba, int idx)
895427bd
JS
8656{
8657 struct lpfc_queue *qdesc;
c00f62e6 8658 u32 wqesize;
c1a21ebc 8659 int cpu;
895427bd 8660
c00f62e6
JS
8661 cpu = lpfc_find_cpu_handle(phba, idx, LPFC_FIND_BY_HDWQ);
8662 /* Create Fast Path IO CQs */
c176ffa0 8663 if (phba->enab_exp_wqcq_pages)
a51e41b6
JS
8664 /* Increase the CQ size when WQEs contain an embedded cdb */
8665 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
8666 phba->sli4_hba.cq_esize,
c1a21ebc 8667 LPFC_CQE_EXP_COUNT, cpu);
a51e41b6
JS
8668
8669 else
8670 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8671 phba->sli4_hba.cq_esize,
c1a21ebc 8672 phba->sli4_hba.cq_ecount, cpu);
895427bd
JS
8673 if (!qdesc) {
8674 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
c00f62e6 8675 "0499 Failed allocate fast-path IO CQ (%d)\n", idx);
895427bd
JS
8676 return 1;
8677 }
7365f6fd 8678 qdesc->qe_valid = 1;
c00f62e6 8679 qdesc->hdwq = idx;
c1a21ebc 8680 qdesc->chann = cpu;
c00f62e6 8681 phba->sli4_hba.hdwq[idx].io_cq = qdesc;
895427bd 8682
c00f62e6 8683 /* Create Fast Path IO WQs */
c176ffa0 8684 if (phba->enab_exp_wqcq_pages) {
a51e41b6 8685 /* Increase the WQ size when WQEs contain an embedded cdb */
c176ffa0
JS
8686 wqesize = (phba->fcp_embed_io) ?
8687 LPFC_WQE128_SIZE : phba->sli4_hba.wq_esize;
a51e41b6 8688 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_EXPANDED_PAGE_SIZE,
c176ffa0 8689 wqesize,
c1a21ebc 8690 LPFC_WQE_EXP_COUNT, cpu);
c176ffa0 8691 } else
a51e41b6
JS
8692 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8693 phba->sli4_hba.wq_esize,
c1a21ebc 8694 phba->sli4_hba.wq_ecount, cpu);
c176ffa0 8695
895427bd
JS
8696 if (!qdesc) {
8697 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
c00f62e6
JS
8698 "0503 Failed allocate fast-path IO WQ (%d)\n",
8699 idx);
895427bd
JS
8700 return 1;
8701 }
c00f62e6
JS
8702 qdesc->hdwq = idx;
8703 qdesc->chann = cpu;
8704 phba->sli4_hba.hdwq[idx].io_wq = qdesc;
895427bd 8705 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
5350d872 8706 return 0;
5350d872
JS
8707}
8708
8709/**
8710 * lpfc_sli4_queue_create - Create all the SLI4 queues
8711 * @phba: pointer to lpfc hba data structure.
8712 *
8713 * This routine is invoked to allocate all the SLI4 queues for the FCoE HBA
8714 * operation. For each SLI4 queue type, the parameters such as queue entry
8715 * count (queue depth) shall be taken from the module parameter. For now,
8716 * we just use some constant number as place holder.
8717 *
8718 * Return codes
4907cb7b 8719 * 0 - successful
5350d872
JS
8720 * -ENOMEM - No availble memory
8721 * -EIO - The mailbox failed to complete successfully.
8722 **/
8723int
8724lpfc_sli4_queue_create(struct lpfc_hba *phba)
8725{
8726 struct lpfc_queue *qdesc;
657add4e 8727 int idx, cpu, eqcpu;
5e5b511d 8728 struct lpfc_sli4_hdw_queue *qp;
657add4e
JS
8729 struct lpfc_vector_map_info *cpup;
8730 struct lpfc_vector_map_info *eqcpup;
32517fc0 8731 struct lpfc_eq_intr_info *eqi;
5350d872
JS
8732
8733 /*
67d12733 8734 * Create HBA Record arrays.
895427bd 8735 * Both NVME and FCP will share that same vectors / EQs
5350d872 8736 */
67d12733
JS
8737 phba->sli4_hba.mq_esize = LPFC_MQE_SIZE;
8738 phba->sli4_hba.mq_ecount = LPFC_MQE_DEF_COUNT;
8739 phba->sli4_hba.wq_esize = LPFC_WQE_SIZE;
8740 phba->sli4_hba.wq_ecount = LPFC_WQE_DEF_COUNT;
8741 phba->sli4_hba.rq_esize = LPFC_RQE_SIZE;
8742 phba->sli4_hba.rq_ecount = LPFC_RQE_DEF_COUNT;
895427bd
JS
8743 phba->sli4_hba.eq_esize = LPFC_EQE_SIZE_4B;
8744 phba->sli4_hba.eq_ecount = LPFC_EQE_DEF_COUNT;
8745 phba->sli4_hba.cq_esize = LPFC_CQE_SIZE;
8746 phba->sli4_hba.cq_ecount = LPFC_CQE_DEF_COUNT;
67d12733 8747
cdb42bec 8748 if (!phba->sli4_hba.hdwq) {
5e5b511d
JS
8749 phba->sli4_hba.hdwq = kcalloc(
8750 phba->cfg_hdw_queue, sizeof(struct lpfc_sli4_hdw_queue),
8751 GFP_KERNEL);
8752 if (!phba->sli4_hba.hdwq) {
895427bd 8753 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
5e5b511d
JS
8754 "6427 Failed allocate memory for "
8755 "fast-path Hardware Queue array\n");
895427bd
JS
8756 goto out_error;
8757 }
5e5b511d
JS
8758 /* Prepare hardware queues to take IO buffers */
8759 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
8760 qp = &phba->sli4_hba.hdwq[idx];
8761 spin_lock_init(&qp->io_buf_list_get_lock);
8762 spin_lock_init(&qp->io_buf_list_put_lock);
8763 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_get);
8764 INIT_LIST_HEAD(&qp->lpfc_io_buf_list_put);
8765 qp->get_io_bufs = 0;
8766 qp->put_io_bufs = 0;
8767 qp->total_io_bufs = 0;
c00f62e6
JS
8768 spin_lock_init(&qp->abts_io_buf_list_lock);
8769 INIT_LIST_HEAD(&qp->lpfc_abts_io_buf_list);
5e5b511d 8770 qp->abts_scsi_io_bufs = 0;
5e5b511d 8771 qp->abts_nvme_io_bufs = 0;
d79c9e9d
JS
8772 INIT_LIST_HEAD(&qp->sgl_list);
8773 INIT_LIST_HEAD(&qp->cmd_rsp_buf_list);
8774 spin_lock_init(&qp->hdwq_lock);
895427bd 8775 }
67d12733
JS
8776 }
8777
cdb42bec 8778 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
2d7dbc4c
JS
8779 if (phba->nvmet_support) {
8780 phba->sli4_hba.nvmet_cqset = kcalloc(
8781 phba->cfg_nvmet_mrq,
8782 sizeof(struct lpfc_queue *),
8783 GFP_KERNEL);
8784 if (!phba->sli4_hba.nvmet_cqset) {
8785 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8786 "3121 Fail allocate memory for "
8787 "fast-path CQ set array\n");
8788 goto out_error;
8789 }
8790 phba->sli4_hba.nvmet_mrq_hdr = kcalloc(
8791 phba->cfg_nvmet_mrq,
8792 sizeof(struct lpfc_queue *),
8793 GFP_KERNEL);
8794 if (!phba->sli4_hba.nvmet_mrq_hdr) {
8795 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8796 "3122 Fail allocate memory for "
8797 "fast-path RQ set hdr array\n");
8798 goto out_error;
8799 }
8800 phba->sli4_hba.nvmet_mrq_data = kcalloc(
8801 phba->cfg_nvmet_mrq,
8802 sizeof(struct lpfc_queue *),
8803 GFP_KERNEL);
8804 if (!phba->sli4_hba.nvmet_mrq_data) {
8805 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8806 "3124 Fail allocate memory for "
8807 "fast-path RQ set data array\n");
8808 goto out_error;
8809 }
8810 }
da0436e9 8811 }
67d12733 8812
895427bd 8813 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
67d12733 8814
895427bd 8815 /* Create HBA Event Queues (EQs) */
657add4e
JS
8816 for_each_present_cpu(cpu) {
8817 /* We only want to create 1 EQ per vector, even though
8818 * multiple CPUs might be using that vector. so only
8819 * selects the CPUs that are LPFC_CPU_FIRST_IRQ.
6a828b0f 8820 */
657add4e
JS
8821 cpup = &phba->sli4_hba.cpu_map[cpu];
8822 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
6a828b0f 8823 continue;
657add4e
JS
8824
8825 /* Get a ptr to the Hardware Queue associated with this CPU */
8826 qp = &phba->sli4_hba.hdwq[cpup->hdwq];
8827
8828 /* Allocate an EQ */
81b96eda
JS
8829 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8830 phba->sli4_hba.eq_esize,
c1a21ebc 8831 phba->sli4_hba.eq_ecount, cpu);
da0436e9
JS
8832 if (!qdesc) {
8833 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
657add4e
JS
8834 "0497 Failed allocate EQ (%d)\n",
8835 cpup->hdwq);
67d12733 8836 goto out_error;
da0436e9 8837 }
7365f6fd 8838 qdesc->qe_valid = 1;
657add4e 8839 qdesc->hdwq = cpup->hdwq;
3ad348d9 8840 qdesc->chann = cpu; /* First CPU this EQ is affinitized to */
32517fc0 8841 qdesc->last_cpu = qdesc->chann;
657add4e
JS
8842
8843 /* Save the allocated EQ in the Hardware Queue */
8844 qp->hba_eq = qdesc;
8845
32517fc0
JS
8846 eqi = per_cpu_ptr(phba->sli4_hba.eq_info, qdesc->last_cpu);
8847 list_add(&qdesc->cpu_list, &eqi->list);
895427bd 8848 }
67d12733 8849
657add4e
JS
8850 /* Now we need to populate the other Hardware Queues, that share
8851 * an IRQ vector, with the associated EQ ptr.
8852 */
8853 for_each_present_cpu(cpu) {
8854 cpup = &phba->sli4_hba.cpu_map[cpu];
8855
8856 /* Check for EQ already allocated in previous loop */
8857 if (cpup->flag & LPFC_CPU_FIRST_IRQ)
8858 continue;
8859
8860 /* Check for multiple CPUs per hdwq */
8861 qp = &phba->sli4_hba.hdwq[cpup->hdwq];
8862 if (qp->hba_eq)
8863 continue;
8864
8865 /* We need to share an EQ for this hdwq */
8866 eqcpu = lpfc_find_cpu_handle(phba, cpup->eq, LPFC_FIND_BY_EQ);
8867 eqcpup = &phba->sli4_hba.cpu_map[eqcpu];
8868 qp->hba_eq = phba->sli4_hba.hdwq[eqcpup->hdwq].hba_eq;
8869 }
67d12733 8870
c00f62e6 8871 /* Allocate IO Path SLI4 CQ/WQs */
6a828b0f 8872 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
c00f62e6 8873 if (lpfc_alloc_io_wq_cq(phba, idx))
67d12733 8874 goto out_error;
6a828b0f 8875 }
da0436e9 8876
c00f62e6
JS
8877 if (phba->nvmet_support) {
8878 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
8879 cpu = lpfc_find_cpu_handle(phba, idx,
8880 LPFC_FIND_BY_HDWQ);
8881 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda
JS
8882 LPFC_DEFAULT_PAGE_SIZE,
8883 phba->sli4_hba.cq_esize,
c1a21ebc
JS
8884 phba->sli4_hba.cq_ecount,
8885 cpu);
c00f62e6
JS
8886 if (!qdesc) {
8887 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
cdb42bec
JS
8888 "3142 Failed allocate NVME "
8889 "CQ Set (%d)\n", idx);
c00f62e6 8890 goto out_error;
2d7dbc4c 8891 }
c00f62e6
JS
8892 qdesc->qe_valid = 1;
8893 qdesc->hdwq = idx;
8894 qdesc->chann = cpu;
8895 phba->sli4_hba.nvmet_cqset[idx] = qdesc;
2d7dbc4c
JS
8896 }
8897 }
8898
da0436e9 8899 /*
67d12733 8900 * Create Slow Path Completion Queues (CQs)
da0436e9
JS
8901 */
8902
c1a21ebc 8903 cpu = lpfc_find_cpu_handle(phba, 0, LPFC_FIND_BY_EQ);
da0436e9 8904 /* Create slow-path Mailbox Command Complete Queue */
81b96eda
JS
8905 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8906 phba->sli4_hba.cq_esize,
c1a21ebc 8907 phba->sli4_hba.cq_ecount, cpu);
da0436e9
JS
8908 if (!qdesc) {
8909 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8910 "0500 Failed allocate slow-path mailbox CQ\n");
67d12733 8911 goto out_error;
da0436e9 8912 }
7365f6fd 8913 qdesc->qe_valid = 1;
da0436e9
JS
8914 phba->sli4_hba.mbx_cq = qdesc;
8915
8916 /* Create slow-path ELS Complete Queue */
81b96eda
JS
8917 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8918 phba->sli4_hba.cq_esize,
c1a21ebc 8919 phba->sli4_hba.cq_ecount, cpu);
da0436e9
JS
8920 if (!qdesc) {
8921 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8922 "0501 Failed allocate slow-path ELS CQ\n");
67d12733 8923 goto out_error;
da0436e9 8924 }
7365f6fd 8925 qdesc->qe_valid = 1;
c00f62e6 8926 qdesc->chann = cpu;
da0436e9
JS
8927 phba->sli4_hba.els_cq = qdesc;
8928
da0436e9 8929
5350d872 8930 /*
67d12733 8931 * Create Slow Path Work Queues (WQs)
5350d872 8932 */
da0436e9
JS
8933
8934 /* Create Mailbox Command Queue */
da0436e9 8935
81b96eda
JS
8936 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8937 phba->sli4_hba.mq_esize,
c1a21ebc 8938 phba->sli4_hba.mq_ecount, cpu);
da0436e9
JS
8939 if (!qdesc) {
8940 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8941 "0505 Failed allocate slow-path MQ\n");
67d12733 8942 goto out_error;
da0436e9 8943 }
c00f62e6 8944 qdesc->chann = cpu;
da0436e9
JS
8945 phba->sli4_hba.mbx_wq = qdesc;
8946
8947 /*
67d12733 8948 * Create ELS Work Queues
da0436e9 8949 */
da0436e9
JS
8950
8951 /* Create slow-path ELS Work Queue */
81b96eda
JS
8952 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8953 phba->sli4_hba.wq_esize,
c1a21ebc 8954 phba->sli4_hba.wq_ecount, cpu);
da0436e9
JS
8955 if (!qdesc) {
8956 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8957 "0504 Failed allocate slow-path ELS WQ\n");
67d12733 8958 goto out_error;
da0436e9 8959 }
c00f62e6 8960 qdesc->chann = cpu;
da0436e9 8961 phba->sli4_hba.els_wq = qdesc;
895427bd
JS
8962 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
8963
8964 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
8965 /* Create NVME LS Complete Queue */
81b96eda
JS
8966 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8967 phba->sli4_hba.cq_esize,
c1a21ebc 8968 phba->sli4_hba.cq_ecount, cpu);
895427bd
JS
8969 if (!qdesc) {
8970 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8971 "6079 Failed allocate NVME LS CQ\n");
8972 goto out_error;
8973 }
c00f62e6 8974 qdesc->chann = cpu;
7365f6fd 8975 qdesc->qe_valid = 1;
895427bd
JS
8976 phba->sli4_hba.nvmels_cq = qdesc;
8977
8978 /* Create NVME LS Work Queue */
81b96eda
JS
8979 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8980 phba->sli4_hba.wq_esize,
c1a21ebc 8981 phba->sli4_hba.wq_ecount, cpu);
895427bd
JS
8982 if (!qdesc) {
8983 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
8984 "6080 Failed allocate NVME LS WQ\n");
8985 goto out_error;
8986 }
c00f62e6 8987 qdesc->chann = cpu;
895427bd
JS
8988 phba->sli4_hba.nvmels_wq = qdesc;
8989 list_add_tail(&qdesc->wq_list, &phba->sli4_hba.lpfc_wq_list);
8990 }
da0436e9 8991
da0436e9
JS
8992 /*
8993 * Create Receive Queue (RQ)
8994 */
da0436e9
JS
8995
8996 /* Create Receive Queue for header */
81b96eda
JS
8997 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
8998 phba->sli4_hba.rq_esize,
c1a21ebc 8999 phba->sli4_hba.rq_ecount, cpu);
da0436e9
JS
9000 if (!qdesc) {
9001 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9002 "0506 Failed allocate receive HRQ\n");
67d12733 9003 goto out_error;
da0436e9
JS
9004 }
9005 phba->sli4_hba.hdr_rq = qdesc;
9006
9007 /* Create Receive Queue for data */
81b96eda
JS
9008 qdesc = lpfc_sli4_queue_alloc(phba, LPFC_DEFAULT_PAGE_SIZE,
9009 phba->sli4_hba.rq_esize,
c1a21ebc 9010 phba->sli4_hba.rq_ecount, cpu);
da0436e9
JS
9011 if (!qdesc) {
9012 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9013 "0507 Failed allocate receive DRQ\n");
67d12733 9014 goto out_error;
da0436e9
JS
9015 }
9016 phba->sli4_hba.dat_rq = qdesc;
9017
cdb42bec
JS
9018 if ((phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) &&
9019 phba->nvmet_support) {
2d7dbc4c 9020 for (idx = 0; idx < phba->cfg_nvmet_mrq; idx++) {
c1a21ebc
JS
9021 cpu = lpfc_find_cpu_handle(phba, idx,
9022 LPFC_FIND_BY_HDWQ);
2d7dbc4c
JS
9023 /* Create NVMET Receive Queue for header */
9024 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda 9025 LPFC_DEFAULT_PAGE_SIZE,
2d7dbc4c 9026 phba->sli4_hba.rq_esize,
c1a21ebc
JS
9027 LPFC_NVMET_RQE_DEF_COUNT,
9028 cpu);
2d7dbc4c
JS
9029 if (!qdesc) {
9030 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9031 "3146 Failed allocate "
9032 "receive HRQ\n");
9033 goto out_error;
9034 }
5e5b511d 9035 qdesc->hdwq = idx;
2d7dbc4c
JS
9036 phba->sli4_hba.nvmet_mrq_hdr[idx] = qdesc;
9037
9038 /* Only needed for header of RQ pair */
c1a21ebc
JS
9039 qdesc->rqbp = kzalloc_node(sizeof(*qdesc->rqbp),
9040 GFP_KERNEL,
9041 cpu_to_node(cpu));
2d7dbc4c
JS
9042 if (qdesc->rqbp == NULL) {
9043 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9044 "6131 Failed allocate "
9045 "Header RQBP\n");
9046 goto out_error;
9047 }
9048
4b40d02b
DK
9049 /* Put list in known state in case driver load fails. */
9050 INIT_LIST_HEAD(&qdesc->rqbp->rqb_buffer_list);
9051
2d7dbc4c
JS
9052 /* Create NVMET Receive Queue for data */
9053 qdesc = lpfc_sli4_queue_alloc(phba,
81b96eda 9054 LPFC_DEFAULT_PAGE_SIZE,
2d7dbc4c 9055 phba->sli4_hba.rq_esize,
c1a21ebc
JS
9056 LPFC_NVMET_RQE_DEF_COUNT,
9057 cpu);
2d7dbc4c
JS
9058 if (!qdesc) {
9059 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9060 "3156 Failed allocate "
9061 "receive DRQ\n");
9062 goto out_error;
9063 }
5e5b511d 9064 qdesc->hdwq = idx;
2d7dbc4c
JS
9065 phba->sli4_hba.nvmet_mrq_data[idx] = qdesc;
9066 }
9067 }
9068
4c47efc1
JS
9069#if defined(BUILD_NVME)
9070 /* Clear NVME stats */
9071 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
9072 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9073 memset(&phba->sli4_hba.hdwq[idx].nvme_cstat, 0,
9074 sizeof(phba->sli4_hba.hdwq[idx].nvme_cstat));
9075 }
9076 }
9077#endif
9078
9079 /* Clear SCSI stats */
9080 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP) {
9081 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9082 memset(&phba->sli4_hba.hdwq[idx].scsi_cstat, 0,
9083 sizeof(phba->sli4_hba.hdwq[idx].scsi_cstat));
9084 }
9085 }
9086
da0436e9
JS
9087 return 0;
9088
da0436e9 9089out_error:
67d12733 9090 lpfc_sli4_queue_destroy(phba);
da0436e9
JS
9091 return -ENOMEM;
9092}
9093
895427bd
JS
9094static inline void
9095__lpfc_sli4_release_queue(struct lpfc_queue **qp)
9096{
9097 if (*qp != NULL) {
9098 lpfc_sli4_queue_free(*qp);
9099 *qp = NULL;
9100 }
9101}
9102
9103static inline void
9104lpfc_sli4_release_queues(struct lpfc_queue ***qs, int max)
9105{
9106 int idx;
9107
9108 if (*qs == NULL)
9109 return;
9110
9111 for (idx = 0; idx < max; idx++)
9112 __lpfc_sli4_release_queue(&(*qs)[idx]);
9113
9114 kfree(*qs);
9115 *qs = NULL;
9116}
9117
9118static inline void
6a828b0f 9119lpfc_sli4_release_hdwq(struct lpfc_hba *phba)
895427bd 9120{
6a828b0f 9121 struct lpfc_sli4_hdw_queue *hdwq;
657add4e 9122 struct lpfc_queue *eq;
cdb42bec
JS
9123 uint32_t idx;
9124
6a828b0f 9125 hdwq = phba->sli4_hba.hdwq;
6a828b0f 9126
657add4e
JS
9127 /* Loop thru all Hardware Queues */
9128 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
9129 /* Free the CQ/WQ corresponding to the Hardware Queue */
c00f62e6
JS
9130 lpfc_sli4_queue_free(hdwq[idx].io_cq);
9131 lpfc_sli4_queue_free(hdwq[idx].io_wq);
9132 hdwq[idx].io_cq = NULL;
9133 hdwq[idx].io_wq = NULL;
d79c9e9d
JS
9134 if (phba->cfg_xpsgl && !phba->nvmet_support)
9135 lpfc_free_sgl_per_hdwq(phba, &hdwq[idx]);
9136 lpfc_free_cmd_rsp_buf_per_hdwq(phba, &hdwq[idx]);
895427bd 9137 }
657add4e
JS
9138 /* Loop thru all IRQ vectors */
9139 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
9140 /* Free the EQ corresponding to the IRQ vector */
9141 eq = phba->sli4_hba.hba_eq_hdl[idx].eq;
9142 lpfc_sli4_queue_free(eq);
9143 phba->sli4_hba.hba_eq_hdl[idx].eq = NULL;
9144 }
895427bd
JS
9145}
9146
da0436e9
JS
9147/**
9148 * lpfc_sli4_queue_destroy - Destroy all the SLI4 queues
9149 * @phba: pointer to lpfc hba data structure.
9150 *
9151 * This routine is invoked to release all the SLI4 queues with the FCoE HBA
9152 * operation.
9153 *
9154 * Return codes
af901ca1 9155 * 0 - successful
25985edc 9156 * -ENOMEM - No available memory
d439d286 9157 * -EIO - The mailbox failed to complete successfully.
da0436e9 9158 **/
5350d872 9159void
da0436e9
JS
9160lpfc_sli4_queue_destroy(struct lpfc_hba *phba)
9161{
4645f7b5
JS
9162 /*
9163 * Set FREE_INIT before beginning to free the queues.
9164 * Wait until the users of queues to acknowledge to
9165 * release queues by clearing FREE_WAIT.
9166 */
9167 spin_lock_irq(&phba->hbalock);
9168 phba->sli.sli_flag |= LPFC_QUEUE_FREE_INIT;
9169 while (phba->sli.sli_flag & LPFC_QUEUE_FREE_WAIT) {
9170 spin_unlock_irq(&phba->hbalock);
9171 msleep(20);
9172 spin_lock_irq(&phba->hbalock);
9173 }
9174 spin_unlock_irq(&phba->hbalock);
9175
895427bd 9176 /* Release HBA eqs */
cdb42bec 9177 if (phba->sli4_hba.hdwq)
6a828b0f 9178 lpfc_sli4_release_hdwq(phba);
895427bd 9179
bcb24f65
JS
9180 if (phba->nvmet_support) {
9181 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_cqset,
9182 phba->cfg_nvmet_mrq);
2d7dbc4c 9183
bcb24f65
JS
9184 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_hdr,
9185 phba->cfg_nvmet_mrq);
9186 lpfc_sli4_release_queues(&phba->sli4_hba.nvmet_mrq_data,
9187 phba->cfg_nvmet_mrq);
9188 }
2d7dbc4c 9189
895427bd
JS
9190 /* Release mailbox command work queue */
9191 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_wq);
9192
9193 /* Release ELS work queue */
9194 __lpfc_sli4_release_queue(&phba->sli4_hba.els_wq);
9195
9196 /* Release ELS work queue */
9197 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_wq);
9198
9199 /* Release unsolicited receive queue */
9200 __lpfc_sli4_release_queue(&phba->sli4_hba.hdr_rq);
9201 __lpfc_sli4_release_queue(&phba->sli4_hba.dat_rq);
9202
9203 /* Release ELS complete queue */
9204 __lpfc_sli4_release_queue(&phba->sli4_hba.els_cq);
9205
9206 /* Release NVME LS complete queue */
9207 __lpfc_sli4_release_queue(&phba->sli4_hba.nvmels_cq);
9208
9209 /* Release mailbox command complete queue */
9210 __lpfc_sli4_release_queue(&phba->sli4_hba.mbx_cq);
9211
9212 /* Everything on this list has been freed */
9213 INIT_LIST_HEAD(&phba->sli4_hba.lpfc_wq_list);
4645f7b5
JS
9214
9215 /* Done with freeing the queues */
9216 spin_lock_irq(&phba->hbalock);
9217 phba->sli.sli_flag &= ~LPFC_QUEUE_FREE_INIT;
9218 spin_unlock_irq(&phba->hbalock);
895427bd
JS
9219}
9220
895427bd
JS
9221int
9222lpfc_free_rq_buffer(struct lpfc_hba *phba, struct lpfc_queue *rq)
9223{
9224 struct lpfc_rqb *rqbp;
9225 struct lpfc_dmabuf *h_buf;
9226 struct rqb_dmabuf *rqb_buffer;
9227
9228 rqbp = rq->rqbp;
9229 while (!list_empty(&rqbp->rqb_buffer_list)) {
9230 list_remove_head(&rqbp->rqb_buffer_list, h_buf,
9231 struct lpfc_dmabuf, list);
9232
9233 rqb_buffer = container_of(h_buf, struct rqb_dmabuf, hbuf);
9234 (rqbp->rqb_free_buffer)(phba, rqb_buffer);
9235 rqbp->buffer_count--;
67d12733 9236 }
895427bd
JS
9237 return 1;
9238}
67d12733 9239
895427bd
JS
9240static int
9241lpfc_create_wq_cq(struct lpfc_hba *phba, struct lpfc_queue *eq,
9242 struct lpfc_queue *cq, struct lpfc_queue *wq, uint16_t *cq_map,
9243 int qidx, uint32_t qtype)
9244{
9245 struct lpfc_sli_ring *pring;
9246 int rc;
9247
9248 if (!eq || !cq || !wq) {
9249 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9250 "6085 Fast-path %s (%d) not allocated\n",
9251 ((eq) ? ((cq) ? "WQ" : "CQ") : "EQ"), qidx);
9252 return -ENOMEM;
9253 }
9254
9255 /* create the Cq first */
9256 rc = lpfc_cq_create(phba, cq, eq,
9257 (qtype == LPFC_MBOX) ? LPFC_MCQ : LPFC_WCQ, qtype);
9258 if (rc) {
9259 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9260 "6086 Failed setup of CQ (%d), rc = 0x%x\n",
9261 qidx, (uint32_t)rc);
9262 return rc;
67d12733
JS
9263 }
9264
895427bd 9265 if (qtype != LPFC_MBOX) {
cdb42bec 9266 /* Setup cq_map for fast lookup */
895427bd
JS
9267 if (cq_map)
9268 *cq_map = cq->queue_id;
da0436e9 9269
895427bd
JS
9270 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9271 "6087 CQ setup: cq[%d]-id=%d, parent eq[%d]-id=%d\n",
9272 qidx, cq->queue_id, qidx, eq->queue_id);
da0436e9 9273
895427bd
JS
9274 /* create the wq */
9275 rc = lpfc_wq_create(phba, wq, cq, qtype);
9276 if (rc) {
9277 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
c835c085 9278 "4618 Fail setup fastpath WQ (%d), rc = 0x%x\n",
895427bd
JS
9279 qidx, (uint32_t)rc);
9280 /* no need to tear down cq - caller will do so */
9281 return rc;
9282 }
da0436e9 9283
895427bd
JS
9284 /* Bind this CQ/WQ to the NVME ring */
9285 pring = wq->pring;
9286 pring->sli.sli4.wqp = (void *)wq;
9287 cq->pring = pring;
da0436e9 9288
895427bd
JS
9289 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9290 "2593 WQ setup: wq[%d]-id=%d assoc=%d, cq[%d]-id=%d\n",
9291 qidx, wq->queue_id, wq->assoc_qid, qidx, cq->queue_id);
9292 } else {
9293 rc = lpfc_mq_create(phba, wq, cq, LPFC_MBOX);
9294 if (rc) {
9295 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9296 "0539 Failed setup of slow-path MQ: "
9297 "rc = 0x%x\n", rc);
9298 /* no need to tear down cq - caller will do so */
9299 return rc;
9300 }
da0436e9 9301
895427bd
JS
9302 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9303 "2589 MBX MQ setup: wq-id=%d, parent cq-id=%d\n",
9304 phba->sli4_hba.mbx_wq->queue_id,
9305 phba->sli4_hba.mbx_cq->queue_id);
67d12733 9306 }
da0436e9 9307
895427bd 9308 return 0;
da0436e9
JS
9309}
9310
6a828b0f
JS
9311/**
9312 * lpfc_setup_cq_lookup - Setup the CQ lookup table
9313 * @phba: pointer to lpfc hba data structure.
9314 *
9315 * This routine will populate the cq_lookup table by all
9316 * available CQ queue_id's.
9317 **/
3999df75 9318static void
6a828b0f
JS
9319lpfc_setup_cq_lookup(struct lpfc_hba *phba)
9320{
9321 struct lpfc_queue *eq, *childq;
6a828b0f
JS
9322 int qidx;
9323
6a828b0f
JS
9324 memset(phba->sli4_hba.cq_lookup, 0,
9325 (sizeof(struct lpfc_queue *) * (phba->sli4_hba.cq_max + 1)));
657add4e 9326 /* Loop thru all IRQ vectors */
6a828b0f 9327 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
657add4e
JS
9328 /* Get the EQ corresponding to the IRQ vector */
9329 eq = phba->sli4_hba.hba_eq_hdl[qidx].eq;
6a828b0f
JS
9330 if (!eq)
9331 continue;
657add4e 9332 /* Loop through all CQs associated with that EQ */
6a828b0f
JS
9333 list_for_each_entry(childq, &eq->child_list, list) {
9334 if (childq->queue_id > phba->sli4_hba.cq_max)
9335 continue;
c00f62e6 9336 if (childq->subtype == LPFC_IO)
6a828b0f
JS
9337 phba->sli4_hba.cq_lookup[childq->queue_id] =
9338 childq;
9339 }
9340 }
9341}
9342
da0436e9
JS
9343/**
9344 * lpfc_sli4_queue_setup - Set up all the SLI4 queues
9345 * @phba: pointer to lpfc hba data structure.
9346 *
9347 * This routine is invoked to set up all the SLI4 queues for the FCoE HBA
9348 * operation.
9349 *
9350 * Return codes
af901ca1 9351 * 0 - successful
25985edc 9352 * -ENOMEM - No available memory
d439d286 9353 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9354 **/
9355int
9356lpfc_sli4_queue_setup(struct lpfc_hba *phba)
9357{
962bc51b
JS
9358 uint32_t shdr_status, shdr_add_status;
9359 union lpfc_sli4_cfg_shdr *shdr;
657add4e 9360 struct lpfc_vector_map_info *cpup;
cdb42bec 9361 struct lpfc_sli4_hdw_queue *qp;
962bc51b 9362 LPFC_MBOXQ_t *mboxq;
657add4e 9363 int qidx, cpu;
cb733e35 9364 uint32_t length, usdelay;
895427bd 9365 int rc = -ENOMEM;
962bc51b
JS
9366
9367 /* Check for dual-ULP support */
9368 mboxq = (LPFC_MBOXQ_t *)mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
9369 if (!mboxq) {
9370 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9371 "3249 Unable to allocate memory for "
9372 "QUERY_FW_CFG mailbox command\n");
9373 return -ENOMEM;
9374 }
9375 length = (sizeof(struct lpfc_mbx_query_fw_config) -
9376 sizeof(struct lpfc_sli4_cfg_mhdr));
9377 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
9378 LPFC_MBOX_OPCODE_QUERY_FW_CFG,
9379 length, LPFC_SLI4_MBX_EMBED);
9380
9381 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
9382
9383 shdr = (union lpfc_sli4_cfg_shdr *)
9384 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
9385 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
9386 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status, &shdr->response);
9387 if (shdr_status || shdr_add_status || rc) {
9388 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9389 "3250 QUERY_FW_CFG mailbox failed with status "
9390 "x%x add_status x%x, mbx status x%x\n",
9391 shdr_status, shdr_add_status, rc);
9392 if (rc != MBX_TIMEOUT)
9393 mempool_free(mboxq, phba->mbox_mem_pool);
9394 rc = -ENXIO;
9395 goto out_error;
9396 }
9397
9398 phba->sli4_hba.fw_func_mode =
9399 mboxq->u.mqe.un.query_fw_cfg.rsp.function_mode;
9400 phba->sli4_hba.ulp0_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp0_mode;
9401 phba->sli4_hba.ulp1_mode = mboxq->u.mqe.un.query_fw_cfg.rsp.ulp1_mode;
8b017a30
JS
9402 phba->sli4_hba.physical_port =
9403 mboxq->u.mqe.un.query_fw_cfg.rsp.physical_port;
962bc51b
JS
9404 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9405 "3251 QUERY_FW_CFG: func_mode:x%x, ulp0_mode:x%x, "
9406 "ulp1_mode:x%x\n", phba->sli4_hba.fw_func_mode,
9407 phba->sli4_hba.ulp0_mode, phba->sli4_hba.ulp1_mode);
9408
9409 if (rc != MBX_TIMEOUT)
9410 mempool_free(mboxq, phba->mbox_mem_pool);
da0436e9
JS
9411
9412 /*
67d12733 9413 * Set up HBA Event Queues (EQs)
da0436e9 9414 */
cdb42bec 9415 qp = phba->sli4_hba.hdwq;
da0436e9 9416
67d12733 9417 /* Set up HBA event queue */
cdb42bec 9418 if (!qp) {
2e90f4b5
JS
9419 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9420 "3147 Fast-path EQs not allocated\n");
1b51197d 9421 rc = -ENOMEM;
67d12733 9422 goto out_error;
2e90f4b5 9423 }
657add4e
JS
9424
9425 /* Loop thru all IRQ vectors */
6a828b0f 9426 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
657add4e
JS
9427 /* Create HBA Event Queues (EQs) in order */
9428 for_each_present_cpu(cpu) {
9429 cpup = &phba->sli4_hba.cpu_map[cpu];
9430
9431 /* Look for the CPU thats using that vector with
9432 * LPFC_CPU_FIRST_IRQ set.
9433 */
9434 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
9435 continue;
9436 if (qidx != cpup->eq)
9437 continue;
9438
9439 /* Create an EQ for that vector */
9440 rc = lpfc_eq_create(phba, qp[cpup->hdwq].hba_eq,
9441 phba->cfg_fcp_imax);
9442 if (rc) {
9443 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9444 "0523 Failed setup of fast-path"
9445 " EQ (%d), rc = 0x%x\n",
9446 cpup->eq, (uint32_t)rc);
9447 goto out_destroy;
9448 }
9449
9450 /* Save the EQ for that vector in the hba_eq_hdl */
9451 phba->sli4_hba.hba_eq_hdl[cpup->eq].eq =
9452 qp[cpup->hdwq].hba_eq;
9453
9454 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9455 "2584 HBA EQ setup: queue[%d]-id=%d\n",
9456 cpup->eq,
9457 qp[cpup->hdwq].hba_eq->queue_id);
da0436e9 9458 }
67d12733
JS
9459 }
9460
657add4e 9461 /* Loop thru all Hardware Queues */
cdb42bec 9462 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
657add4e
JS
9463 cpu = lpfc_find_cpu_handle(phba, qidx, LPFC_FIND_BY_HDWQ);
9464 cpup = &phba->sli4_hba.cpu_map[cpu];
9465
9466 /* Create the CQ/WQ corresponding to the Hardware Queue */
cdb42bec 9467 rc = lpfc_create_wq_cq(phba,
657add4e 9468 phba->sli4_hba.hdwq[cpup->hdwq].hba_eq,
c00f62e6
JS
9469 qp[qidx].io_cq,
9470 qp[qidx].io_wq,
9471 &phba->sli4_hba.hdwq[qidx].io_cq_map,
9472 qidx,
9473 LPFC_IO);
cdb42bec 9474 if (rc) {
67d12733 9475 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
895427bd 9476 "0535 Failed to setup fastpath "
c00f62e6 9477 "IO WQ/CQ (%d), rc = 0x%x\n",
895427bd 9478 qidx, (uint32_t)rc);
cdb42bec 9479 goto out_destroy;
895427bd 9480 }
67d12733 9481 }
895427bd 9482
da0436e9 9483 /*
895427bd 9484 * Set up Slow Path Complete Queues (CQs)
da0436e9
JS
9485 */
9486
895427bd 9487 /* Set up slow-path MBOX CQ/MQ */
da0436e9 9488
895427bd 9489 if (!phba->sli4_hba.mbx_cq || !phba->sli4_hba.mbx_wq) {
da0436e9 9490 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
895427bd
JS
9491 "0528 %s not allocated\n",
9492 phba->sli4_hba.mbx_cq ?
d1f525aa 9493 "Mailbox WQ" : "Mailbox CQ");
1b51197d 9494 rc = -ENOMEM;
895427bd 9495 goto out_destroy;
da0436e9 9496 }
da0436e9 9497
cdb42bec 9498 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
d1f525aa
JS
9499 phba->sli4_hba.mbx_cq,
9500 phba->sli4_hba.mbx_wq,
9501 NULL, 0, LPFC_MBOX);
da0436e9
JS
9502 if (rc) {
9503 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
895427bd
JS
9504 "0529 Failed setup of mailbox WQ/CQ: rc = 0x%x\n",
9505 (uint32_t)rc);
9506 goto out_destroy;
da0436e9 9507 }
2d7dbc4c
JS
9508 if (phba->nvmet_support) {
9509 if (!phba->sli4_hba.nvmet_cqset) {
9510 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9511 "3165 Fast-path NVME CQ Set "
9512 "array not allocated\n");
9513 rc = -ENOMEM;
9514 goto out_destroy;
9515 }
9516 if (phba->cfg_nvmet_mrq > 1) {
9517 rc = lpfc_cq_create_set(phba,
9518 phba->sli4_hba.nvmet_cqset,
cdb42bec 9519 qp,
2d7dbc4c
JS
9520 LPFC_WCQ, LPFC_NVMET);
9521 if (rc) {
9522 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9523 "3164 Failed setup of NVME CQ "
9524 "Set, rc = 0x%x\n",
9525 (uint32_t)rc);
9526 goto out_destroy;
9527 }
9528 } else {
9529 /* Set up NVMET Receive Complete Queue */
9530 rc = lpfc_cq_create(phba, phba->sli4_hba.nvmet_cqset[0],
cdb42bec 9531 qp[0].hba_eq,
2d7dbc4c
JS
9532 LPFC_WCQ, LPFC_NVMET);
9533 if (rc) {
9534 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9535 "6089 Failed setup NVMET CQ: "
9536 "rc = 0x%x\n", (uint32_t)rc);
9537 goto out_destroy;
9538 }
81b96eda
JS
9539 phba->sli4_hba.nvmet_cqset[0]->chann = 0;
9540
2d7dbc4c
JS
9541 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9542 "6090 NVMET CQ setup: cq-id=%d, "
9543 "parent eq-id=%d\n",
9544 phba->sli4_hba.nvmet_cqset[0]->queue_id,
cdb42bec 9545 qp[0].hba_eq->queue_id);
2d7dbc4c
JS
9546 }
9547 }
da0436e9 9548
895427bd
JS
9549 /* Set up slow-path ELS WQ/CQ */
9550 if (!phba->sli4_hba.els_cq || !phba->sli4_hba.els_wq) {
da0436e9 9551 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
895427bd
JS
9552 "0530 ELS %s not allocated\n",
9553 phba->sli4_hba.els_cq ? "WQ" : "CQ");
1b51197d 9554 rc = -ENOMEM;
895427bd 9555 goto out_destroy;
da0436e9 9556 }
cdb42bec
JS
9557 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9558 phba->sli4_hba.els_cq,
9559 phba->sli4_hba.els_wq,
9560 NULL, 0, LPFC_ELS);
da0436e9
JS
9561 if (rc) {
9562 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
cdb42bec
JS
9563 "0525 Failed setup of ELS WQ/CQ: rc = 0x%x\n",
9564 (uint32_t)rc);
895427bd 9565 goto out_destroy;
da0436e9
JS
9566 }
9567 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9568 "2590 ELS WQ setup: wq-id=%d, parent cq-id=%d\n",
9569 phba->sli4_hba.els_wq->queue_id,
9570 phba->sli4_hba.els_cq->queue_id);
9571
cdb42bec 9572 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
895427bd
JS
9573 /* Set up NVME LS Complete Queue */
9574 if (!phba->sli4_hba.nvmels_cq || !phba->sli4_hba.nvmels_wq) {
9575 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9576 "6091 LS %s not allocated\n",
9577 phba->sli4_hba.nvmels_cq ? "WQ" : "CQ");
9578 rc = -ENOMEM;
9579 goto out_destroy;
9580 }
cdb42bec
JS
9581 rc = lpfc_create_wq_cq(phba, qp[0].hba_eq,
9582 phba->sli4_hba.nvmels_cq,
9583 phba->sli4_hba.nvmels_wq,
9584 NULL, 0, LPFC_NVME_LS);
895427bd
JS
9585 if (rc) {
9586 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
cdb42bec
JS
9587 "0526 Failed setup of NVVME LS WQ/CQ: "
9588 "rc = 0x%x\n", (uint32_t)rc);
895427bd
JS
9589 goto out_destroy;
9590 }
9591
9592 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9593 "6096 ELS WQ setup: wq-id=%d, "
9594 "parent cq-id=%d\n",
9595 phba->sli4_hba.nvmels_wq->queue_id,
9596 phba->sli4_hba.nvmels_cq->queue_id);
9597 }
9598
2d7dbc4c
JS
9599 /*
9600 * Create NVMET Receive Queue (RQ)
9601 */
9602 if (phba->nvmet_support) {
9603 if ((!phba->sli4_hba.nvmet_cqset) ||
9604 (!phba->sli4_hba.nvmet_mrq_hdr) ||
9605 (!phba->sli4_hba.nvmet_mrq_data)) {
9606 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9607 "6130 MRQ CQ Queues not "
9608 "allocated\n");
9609 rc = -ENOMEM;
9610 goto out_destroy;
9611 }
9612 if (phba->cfg_nvmet_mrq > 1) {
9613 rc = lpfc_mrq_create(phba,
9614 phba->sli4_hba.nvmet_mrq_hdr,
9615 phba->sli4_hba.nvmet_mrq_data,
9616 phba->sli4_hba.nvmet_cqset,
9617 LPFC_NVMET);
9618 if (rc) {
9619 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9620 "6098 Failed setup of NVMET "
9621 "MRQ: rc = 0x%x\n",
9622 (uint32_t)rc);
9623 goto out_destroy;
9624 }
9625
9626 } else {
9627 rc = lpfc_rq_create(phba,
9628 phba->sli4_hba.nvmet_mrq_hdr[0],
9629 phba->sli4_hba.nvmet_mrq_data[0],
9630 phba->sli4_hba.nvmet_cqset[0],
9631 LPFC_NVMET);
9632 if (rc) {
9633 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9634 "6057 Failed setup of NVMET "
9635 "Receive Queue: rc = 0x%x\n",
9636 (uint32_t)rc);
9637 goto out_destroy;
9638 }
9639
9640 lpfc_printf_log(
9641 phba, KERN_INFO, LOG_INIT,
9642 "6099 NVMET RQ setup: hdr-rq-id=%d, "
9643 "dat-rq-id=%d parent cq-id=%d\n",
9644 phba->sli4_hba.nvmet_mrq_hdr[0]->queue_id,
9645 phba->sli4_hba.nvmet_mrq_data[0]->queue_id,
9646 phba->sli4_hba.nvmet_cqset[0]->queue_id);
9647
9648 }
9649 }
9650
da0436e9
JS
9651 if (!phba->sli4_hba.hdr_rq || !phba->sli4_hba.dat_rq) {
9652 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9653 "0540 Receive Queue not allocated\n");
1b51197d 9654 rc = -ENOMEM;
895427bd 9655 goto out_destroy;
da0436e9 9656 }
73d91e50 9657
da0436e9 9658 rc = lpfc_rq_create(phba, phba->sli4_hba.hdr_rq, phba->sli4_hba.dat_rq,
4d9ab994 9659 phba->sli4_hba.els_cq, LPFC_USOL);
da0436e9
JS
9660 if (rc) {
9661 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9662 "0541 Failed setup of Receive Queue: "
a2fc4aef 9663 "rc = 0x%x\n", (uint32_t)rc);
895427bd 9664 goto out_destroy;
da0436e9 9665 }
73d91e50 9666
da0436e9
JS
9667 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
9668 "2592 USL RQ setup: hdr-rq-id=%d, dat-rq-id=%d "
9669 "parent cq-id=%d\n",
9670 phba->sli4_hba.hdr_rq->queue_id,
9671 phba->sli4_hba.dat_rq->queue_id,
4d9ab994 9672 phba->sli4_hba.els_cq->queue_id);
1ba981fd 9673
cb733e35
JS
9674 if (phba->cfg_fcp_imax)
9675 usdelay = LPFC_SEC_TO_USEC / phba->cfg_fcp_imax;
9676 else
9677 usdelay = 0;
9678
6a828b0f 9679 for (qidx = 0; qidx < phba->cfg_irq_chann;
cdb42bec 9680 qidx += LPFC_MAX_EQ_DELAY_EQID_CNT)
0cf07f84 9681 lpfc_modify_hba_eq_delay(phba, qidx, LPFC_MAX_EQ_DELAY_EQID_CNT,
cb733e35 9682 usdelay);
43140ca6 9683
6a828b0f
JS
9684 if (phba->sli4_hba.cq_max) {
9685 kfree(phba->sli4_hba.cq_lookup);
9686 phba->sli4_hba.cq_lookup = kcalloc((phba->sli4_hba.cq_max + 1),
9687 sizeof(struct lpfc_queue *), GFP_KERNEL);
9688 if (!phba->sli4_hba.cq_lookup) {
1ba981fd 9689 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
6a828b0f
JS
9690 "0549 Failed setup of CQ Lookup table: "
9691 "size 0x%x\n", phba->sli4_hba.cq_max);
fad28e3d 9692 rc = -ENOMEM;
895427bd 9693 goto out_destroy;
1ba981fd 9694 }
6a828b0f 9695 lpfc_setup_cq_lookup(phba);
1ba981fd 9696 }
da0436e9
JS
9697 return 0;
9698
895427bd
JS
9699out_destroy:
9700 lpfc_sli4_queue_unset(phba);
da0436e9
JS
9701out_error:
9702 return rc;
9703}
9704
9705/**
9706 * lpfc_sli4_queue_unset - Unset all the SLI4 queues
9707 * @phba: pointer to lpfc hba data structure.
9708 *
9709 * This routine is invoked to unset all the SLI4 queues with the FCoE HBA
9710 * operation.
9711 *
9712 * Return codes
af901ca1 9713 * 0 - successful
25985edc 9714 * -ENOMEM - No available memory
d439d286 9715 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9716 **/
9717void
9718lpfc_sli4_queue_unset(struct lpfc_hba *phba)
9719{
cdb42bec 9720 struct lpfc_sli4_hdw_queue *qp;
657add4e 9721 struct lpfc_queue *eq;
895427bd 9722 int qidx;
da0436e9
JS
9723
9724 /* Unset mailbox command work queue */
895427bd
JS
9725 if (phba->sli4_hba.mbx_wq)
9726 lpfc_mq_destroy(phba, phba->sli4_hba.mbx_wq);
9727
9728 /* Unset NVME LS work queue */
9729 if (phba->sli4_hba.nvmels_wq)
9730 lpfc_wq_destroy(phba, phba->sli4_hba.nvmels_wq);
9731
da0436e9 9732 /* Unset ELS work queue */
019c0d66 9733 if (phba->sli4_hba.els_wq)
895427bd
JS
9734 lpfc_wq_destroy(phba, phba->sli4_hba.els_wq);
9735
da0436e9 9736 /* Unset unsolicited receive queue */
895427bd
JS
9737 if (phba->sli4_hba.hdr_rq)
9738 lpfc_rq_destroy(phba, phba->sli4_hba.hdr_rq,
9739 phba->sli4_hba.dat_rq);
9740
da0436e9 9741 /* Unset mailbox command complete queue */
895427bd
JS
9742 if (phba->sli4_hba.mbx_cq)
9743 lpfc_cq_destroy(phba, phba->sli4_hba.mbx_cq);
9744
da0436e9 9745 /* Unset ELS complete queue */
895427bd
JS
9746 if (phba->sli4_hba.els_cq)
9747 lpfc_cq_destroy(phba, phba->sli4_hba.els_cq);
9748
9749 /* Unset NVME LS complete queue */
9750 if (phba->sli4_hba.nvmels_cq)
9751 lpfc_cq_destroy(phba, phba->sli4_hba.nvmels_cq);
9752
bcb24f65
JS
9753 if (phba->nvmet_support) {
9754 /* Unset NVMET MRQ queue */
9755 if (phba->sli4_hba.nvmet_mrq_hdr) {
9756 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
9757 lpfc_rq_destroy(
9758 phba,
2d7dbc4c
JS
9759 phba->sli4_hba.nvmet_mrq_hdr[qidx],
9760 phba->sli4_hba.nvmet_mrq_data[qidx]);
bcb24f65 9761 }
2d7dbc4c 9762
bcb24f65
JS
9763 /* Unset NVMET CQ Set complete queue */
9764 if (phba->sli4_hba.nvmet_cqset) {
9765 for (qidx = 0; qidx < phba->cfg_nvmet_mrq; qidx++)
9766 lpfc_cq_destroy(
9767 phba, phba->sli4_hba.nvmet_cqset[qidx]);
9768 }
2d7dbc4c
JS
9769 }
9770
cdb42bec
JS
9771 /* Unset fast-path SLI4 queues */
9772 if (phba->sli4_hba.hdwq) {
657add4e 9773 /* Loop thru all Hardware Queues */
cdb42bec 9774 for (qidx = 0; qidx < phba->cfg_hdw_queue; qidx++) {
657add4e 9775 /* Destroy the CQ/WQ corresponding to Hardware Queue */
cdb42bec 9776 qp = &phba->sli4_hba.hdwq[qidx];
c00f62e6
JS
9777 lpfc_wq_destroy(phba, qp->io_wq);
9778 lpfc_cq_destroy(phba, qp->io_cq);
657add4e
JS
9779 }
9780 /* Loop thru all IRQ vectors */
9781 for (qidx = 0; qidx < phba->cfg_irq_chann; qidx++) {
9782 /* Destroy the EQ corresponding to the IRQ vector */
9783 eq = phba->sli4_hba.hba_eq_hdl[qidx].eq;
9784 lpfc_eq_destroy(phba, eq);
cdb42bec
JS
9785 }
9786 }
895427bd 9787
6a828b0f
JS
9788 kfree(phba->sli4_hba.cq_lookup);
9789 phba->sli4_hba.cq_lookup = NULL;
9790 phba->sli4_hba.cq_max = 0;
da0436e9
JS
9791}
9792
9793/**
9794 * lpfc_sli4_cq_event_pool_create - Create completion-queue event free pool
9795 * @phba: pointer to lpfc hba data structure.
9796 *
9797 * This routine is invoked to allocate and set up a pool of completion queue
9798 * events. The body of the completion queue event is a completion queue entry
9799 * CQE. For now, this pool is used for the interrupt service routine to queue
9800 * the following HBA completion queue events for the worker thread to process:
9801 * - Mailbox asynchronous events
9802 * - Receive queue completion unsolicited events
9803 * Later, this can be used for all the slow-path events.
9804 *
9805 * Return codes
af901ca1 9806 * 0 - successful
25985edc 9807 * -ENOMEM - No available memory
da0436e9
JS
9808 **/
9809static int
9810lpfc_sli4_cq_event_pool_create(struct lpfc_hba *phba)
9811{
9812 struct lpfc_cq_event *cq_event;
9813 int i;
9814
9815 for (i = 0; i < (4 * phba->sli4_hba.cq_ecount); i++) {
9816 cq_event = kmalloc(sizeof(struct lpfc_cq_event), GFP_KERNEL);
9817 if (!cq_event)
9818 goto out_pool_create_fail;
9819 list_add_tail(&cq_event->list,
9820 &phba->sli4_hba.sp_cqe_event_pool);
9821 }
9822 return 0;
9823
9824out_pool_create_fail:
9825 lpfc_sli4_cq_event_pool_destroy(phba);
9826 return -ENOMEM;
9827}
9828
9829/**
9830 * lpfc_sli4_cq_event_pool_destroy - Free completion-queue event free pool
9831 * @phba: pointer to lpfc hba data structure.
9832 *
9833 * This routine is invoked to free the pool of completion queue events at
9834 * driver unload time. Note that, it is the responsibility of the driver
9835 * cleanup routine to free all the outstanding completion-queue events
9836 * allocated from this pool back into the pool before invoking this routine
9837 * to destroy the pool.
9838 **/
9839static void
9840lpfc_sli4_cq_event_pool_destroy(struct lpfc_hba *phba)
9841{
9842 struct lpfc_cq_event *cq_event, *next_cq_event;
9843
9844 list_for_each_entry_safe(cq_event, next_cq_event,
9845 &phba->sli4_hba.sp_cqe_event_pool, list) {
9846 list_del(&cq_event->list);
9847 kfree(cq_event);
9848 }
9849}
9850
9851/**
9852 * __lpfc_sli4_cq_event_alloc - Allocate a completion-queue event from free pool
9853 * @phba: pointer to lpfc hba data structure.
9854 *
9855 * This routine is the lock free version of the API invoked to allocate a
9856 * completion-queue event from the free pool.
9857 *
9858 * Return: Pointer to the newly allocated completion-queue event if successful
9859 * NULL otherwise.
9860 **/
9861struct lpfc_cq_event *
9862__lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
9863{
9864 struct lpfc_cq_event *cq_event = NULL;
9865
9866 list_remove_head(&phba->sli4_hba.sp_cqe_event_pool, cq_event,
9867 struct lpfc_cq_event, list);
9868 return cq_event;
9869}
9870
9871/**
9872 * lpfc_sli4_cq_event_alloc - Allocate a completion-queue event from free pool
9873 * @phba: pointer to lpfc hba data structure.
9874 *
9875 * This routine is the lock version of the API invoked to allocate a
9876 * completion-queue event from the free pool.
9877 *
9878 * Return: Pointer to the newly allocated completion-queue event if successful
9879 * NULL otherwise.
9880 **/
9881struct lpfc_cq_event *
9882lpfc_sli4_cq_event_alloc(struct lpfc_hba *phba)
9883{
9884 struct lpfc_cq_event *cq_event;
9885 unsigned long iflags;
9886
9887 spin_lock_irqsave(&phba->hbalock, iflags);
9888 cq_event = __lpfc_sli4_cq_event_alloc(phba);
9889 spin_unlock_irqrestore(&phba->hbalock, iflags);
9890 return cq_event;
9891}
9892
9893/**
9894 * __lpfc_sli4_cq_event_release - Release a completion-queue event to free pool
9895 * @phba: pointer to lpfc hba data structure.
9896 * @cq_event: pointer to the completion queue event to be freed.
9897 *
9898 * This routine is the lock free version of the API invoked to release a
9899 * completion-queue event back into the free pool.
9900 **/
9901void
9902__lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
9903 struct lpfc_cq_event *cq_event)
9904{
9905 list_add_tail(&cq_event->list, &phba->sli4_hba.sp_cqe_event_pool);
9906}
9907
9908/**
9909 * lpfc_sli4_cq_event_release - Release a completion-queue event to free pool
9910 * @phba: pointer to lpfc hba data structure.
9911 * @cq_event: pointer to the completion queue event to be freed.
9912 *
9913 * This routine is the lock version of the API invoked to release a
9914 * completion-queue event back into the free pool.
9915 **/
9916void
9917lpfc_sli4_cq_event_release(struct lpfc_hba *phba,
9918 struct lpfc_cq_event *cq_event)
9919{
9920 unsigned long iflags;
9921 spin_lock_irqsave(&phba->hbalock, iflags);
9922 __lpfc_sli4_cq_event_release(phba, cq_event);
9923 spin_unlock_irqrestore(&phba->hbalock, iflags);
9924}
9925
9926/**
9927 * lpfc_sli4_cq_event_release_all - Release all cq events to the free pool
9928 * @phba: pointer to lpfc hba data structure.
9929 *
9930 * This routine is to free all the pending completion-queue events to the
9931 * back into the free pool for device reset.
9932 **/
9933static void
9934lpfc_sli4_cq_event_release_all(struct lpfc_hba *phba)
9935{
9936 LIST_HEAD(cqelist);
9937 struct lpfc_cq_event *cqe;
9938 unsigned long iflags;
9939
9940 /* Retrieve all the pending WCQEs from pending WCQE lists */
9941 spin_lock_irqsave(&phba->hbalock, iflags);
9942 /* Pending FCP XRI abort events */
9943 list_splice_init(&phba->sli4_hba.sp_fcp_xri_aborted_work_queue,
9944 &cqelist);
9945 /* Pending ELS XRI abort events */
9946 list_splice_init(&phba->sli4_hba.sp_els_xri_aborted_work_queue,
9947 &cqelist);
9948 /* Pending asynnc events */
9949 list_splice_init(&phba->sli4_hba.sp_asynce_work_queue,
9950 &cqelist);
9951 spin_unlock_irqrestore(&phba->hbalock, iflags);
9952
9953 while (!list_empty(&cqelist)) {
9954 list_remove_head(&cqelist, cqe, struct lpfc_cq_event, list);
9955 lpfc_sli4_cq_event_release(phba, cqe);
9956 }
9957}
9958
9959/**
9960 * lpfc_pci_function_reset - Reset pci function.
9961 * @phba: pointer to lpfc hba data structure.
9962 *
9963 * This routine is invoked to request a PCI function reset. It will destroys
9964 * all resources assigned to the PCI function which originates this request.
9965 *
9966 * Return codes
af901ca1 9967 * 0 - successful
25985edc 9968 * -ENOMEM - No available memory
d439d286 9969 * -EIO - The mailbox failed to complete successfully.
da0436e9
JS
9970 **/
9971int
9972lpfc_pci_function_reset(struct lpfc_hba *phba)
9973{
9974 LPFC_MBOXQ_t *mboxq;
2fcee4bf 9975 uint32_t rc = 0, if_type;
da0436e9 9976 uint32_t shdr_status, shdr_add_status;
2f6fa2c9
JS
9977 uint32_t rdy_chk;
9978 uint32_t port_reset = 0;
da0436e9 9979 union lpfc_sli4_cfg_shdr *shdr;
2fcee4bf 9980 struct lpfc_register reg_data;
2b81f942 9981 uint16_t devid;
da0436e9 9982
2fcee4bf
JS
9983 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
9984 switch (if_type) {
9985 case LPFC_SLI_INTF_IF_TYPE_0:
9986 mboxq = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool,
9987 GFP_KERNEL);
9988 if (!mboxq) {
9989 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
9990 "0494 Unable to allocate memory for "
9991 "issuing SLI_FUNCTION_RESET mailbox "
9992 "command\n");
9993 return -ENOMEM;
9994 }
da0436e9 9995
2fcee4bf
JS
9996 /* Setup PCI function reset mailbox-ioctl command */
9997 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
9998 LPFC_MBOX_OPCODE_FUNCTION_RESET, 0,
9999 LPFC_SLI4_MBX_EMBED);
10000 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
10001 shdr = (union lpfc_sli4_cfg_shdr *)
10002 &mboxq->u.mqe.un.sli4_config.header.cfg_shdr;
10003 shdr_status = bf_get(lpfc_mbox_hdr_status, &shdr->response);
10004 shdr_add_status = bf_get(lpfc_mbox_hdr_add_status,
10005 &shdr->response);
10006 if (rc != MBX_TIMEOUT)
10007 mempool_free(mboxq, phba->mbox_mem_pool);
10008 if (shdr_status || shdr_add_status || rc) {
10009 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10010 "0495 SLI_FUNCTION_RESET mailbox "
10011 "failed with status x%x add_status x%x,"
10012 " mbx status x%x\n",
10013 shdr_status, shdr_add_status, rc);
10014 rc = -ENXIO;
10015 }
10016 break;
10017 case LPFC_SLI_INTF_IF_TYPE_2:
27d6ac0a 10018 case LPFC_SLI_INTF_IF_TYPE_6:
2f6fa2c9
JS
10019wait:
10020 /*
10021 * Poll the Port Status Register and wait for RDY for
10022 * up to 30 seconds. If the port doesn't respond, treat
10023 * it as an error.
10024 */
77d093fb 10025 for (rdy_chk = 0; rdy_chk < 1500; rdy_chk++) {
2f6fa2c9
JS
10026 if (lpfc_readl(phba->sli4_hba.u.if_type2.
10027 STATUSregaddr, &reg_data.word0)) {
10028 rc = -ENODEV;
10029 goto out;
10030 }
10031 if (bf_get(lpfc_sliport_status_rdy, &reg_data))
10032 break;
10033 msleep(20);
10034 }
10035
10036 if (!bf_get(lpfc_sliport_status_rdy, &reg_data)) {
10037 phba->work_status[0] = readl(
10038 phba->sli4_hba.u.if_type2.ERR1regaddr);
10039 phba->work_status[1] = readl(
10040 phba->sli4_hba.u.if_type2.ERR2regaddr);
10041 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10042 "2890 Port not ready, port status reg "
10043 "0x%x error 1=0x%x, error 2=0x%x\n",
10044 reg_data.word0,
10045 phba->work_status[0],
10046 phba->work_status[1]);
10047 rc = -ENODEV;
10048 goto out;
10049 }
10050
10051 if (!port_reset) {
10052 /*
10053 * Reset the port now
10054 */
2fcee4bf
JS
10055 reg_data.word0 = 0;
10056 bf_set(lpfc_sliport_ctrl_end, &reg_data,
10057 LPFC_SLIPORT_LITTLE_ENDIAN);
10058 bf_set(lpfc_sliport_ctrl_ip, &reg_data,
10059 LPFC_SLIPORT_INIT_PORT);
10060 writel(reg_data.word0, phba->sli4_hba.u.if_type2.
10061 CTRLregaddr);
8fcb8acd 10062 /* flush */
2b81f942
JS
10063 pci_read_config_word(phba->pcidev,
10064 PCI_DEVICE_ID, &devid);
2fcee4bf 10065
2f6fa2c9
JS
10066 port_reset = 1;
10067 msleep(20);
10068 goto wait;
10069 } else if (bf_get(lpfc_sliport_status_rn, &reg_data)) {
10070 rc = -ENODEV;
10071 goto out;
2fcee4bf
JS
10072 }
10073 break;
2f6fa2c9 10074
2fcee4bf
JS
10075 case LPFC_SLI_INTF_IF_TYPE_1:
10076 default:
10077 break;
da0436e9 10078 }
2fcee4bf 10079
73d91e50 10080out:
2fcee4bf 10081 /* Catch the not-ready port failure after a port reset. */
2f6fa2c9 10082 if (rc) {
229adb0e
JS
10083 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10084 "3317 HBA not functional: IP Reset Failed "
2f6fa2c9 10085 "try: echo fw_reset > board_mode\n");
2fcee4bf 10086 rc = -ENODEV;
229adb0e 10087 }
2fcee4bf 10088
da0436e9
JS
10089 return rc;
10090}
10091
da0436e9
JS
10092/**
10093 * lpfc_sli4_pci_mem_setup - Setup SLI4 HBA PCI memory space.
10094 * @phba: pointer to lpfc hba data structure.
10095 *
10096 * This routine is invoked to set up the PCI device memory space for device
10097 * with SLI-4 interface spec.
10098 *
10099 * Return codes
af901ca1 10100 * 0 - successful
da0436e9
JS
10101 * other values - error
10102 **/
10103static int
10104lpfc_sli4_pci_mem_setup(struct lpfc_hba *phba)
10105{
f30e1bfd 10106 struct pci_dev *pdev = phba->pcidev;
da0436e9 10107 unsigned long bar0map_len, bar1map_len, bar2map_len;
3a487ff7 10108 int error;
2fcee4bf 10109 uint32_t if_type;
da0436e9 10110
f30e1bfd 10111 if (!pdev)
56de8357 10112 return -ENODEV;
da0436e9
JS
10113
10114 /* Set the device DMA mask size */
56de8357
HR
10115 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
10116 if (error)
10117 error = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
10118 if (error)
f30e1bfd 10119 return error;
da0436e9 10120
2fcee4bf
JS
10121 /*
10122 * The BARs and register set definitions and offset locations are
10123 * dependent on the if_type.
10124 */
10125 if (pci_read_config_dword(pdev, LPFC_SLI_INTF,
10126 &phba->sli4_hba.sli_intf.word0)) {
3a487ff7 10127 return -ENODEV;
2fcee4bf
JS
10128 }
10129
10130 /* There is no SLI3 failback for SLI4 devices. */
10131 if (bf_get(lpfc_sli_intf_valid, &phba->sli4_hba.sli_intf) !=
10132 LPFC_SLI_INTF_VALID) {
10133 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10134 "2894 SLI_INTF reg contents invalid "
10135 "sli_intf reg 0x%x\n",
10136 phba->sli4_hba.sli_intf.word0);
3a487ff7 10137 return -ENODEV;
2fcee4bf
JS
10138 }
10139
10140 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
10141 /*
10142 * Get the bus address of SLI4 device Bar regions and the
10143 * number of bytes required by each mapping. The mapping of the
10144 * particular PCI BARs regions is dependent on the type of
10145 * SLI4 device.
da0436e9 10146 */
f5ca6f2e
JS
10147 if (pci_resource_start(pdev, PCI_64BIT_BAR0)) {
10148 phba->pci_bar0_map = pci_resource_start(pdev, PCI_64BIT_BAR0);
10149 bar0map_len = pci_resource_len(pdev, PCI_64BIT_BAR0);
2fcee4bf
JS
10150
10151 /*
10152 * Map SLI4 PCI Config Space Register base to a kernel virtual
10153 * addr
10154 */
10155 phba->sli4_hba.conf_regs_memmap_p =
10156 ioremap(phba->pci_bar0_map, bar0map_len);
10157 if (!phba->sli4_hba.conf_regs_memmap_p) {
10158 dev_printk(KERN_ERR, &pdev->dev,
10159 "ioremap failed for SLI4 PCI config "
10160 "registers.\n");
3a487ff7 10161 return -ENODEV;
2fcee4bf 10162 }
f5ca6f2e 10163 phba->pci_bar0_memmap_p = phba->sli4_hba.conf_regs_memmap_p;
2fcee4bf
JS
10164 /* Set up BAR0 PCI config space register memory map */
10165 lpfc_sli4_bar0_register_memmap(phba, if_type);
1dfb5a47
JS
10166 } else {
10167 phba->pci_bar0_map = pci_resource_start(pdev, 1);
10168 bar0map_len = pci_resource_len(pdev, 1);
27d6ac0a 10169 if (if_type >= LPFC_SLI_INTF_IF_TYPE_2) {
2fcee4bf
JS
10170 dev_printk(KERN_ERR, &pdev->dev,
10171 "FATAL - No BAR0 mapping for SLI4, if_type 2\n");
3a487ff7 10172 return -ENODEV;
2fcee4bf
JS
10173 }
10174 phba->sli4_hba.conf_regs_memmap_p =
da0436e9 10175 ioremap(phba->pci_bar0_map, bar0map_len);
2fcee4bf
JS
10176 if (!phba->sli4_hba.conf_regs_memmap_p) {
10177 dev_printk(KERN_ERR, &pdev->dev,
10178 "ioremap failed for SLI4 PCI config "
10179 "registers.\n");
3a487ff7 10180 return -ENODEV;
2fcee4bf
JS
10181 }
10182 lpfc_sli4_bar0_register_memmap(phba, if_type);
da0436e9
JS
10183 }
10184
e4b9794e
JS
10185 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
10186 if (pci_resource_start(pdev, PCI_64BIT_BAR2)) {
10187 /*
10188 * Map SLI4 if type 0 HBA Control Register base to a
10189 * kernel virtual address and setup the registers.
10190 */
10191 phba->pci_bar1_map = pci_resource_start(pdev,
10192 PCI_64BIT_BAR2);
10193 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
10194 phba->sli4_hba.ctrl_regs_memmap_p =
10195 ioremap(phba->pci_bar1_map,
10196 bar1map_len);
10197 if (!phba->sli4_hba.ctrl_regs_memmap_p) {
10198 dev_err(&pdev->dev,
10199 "ioremap failed for SLI4 HBA "
10200 "control registers.\n");
10201 error = -ENOMEM;
10202 goto out_iounmap_conf;
10203 }
10204 phba->pci_bar2_memmap_p =
10205 phba->sli4_hba.ctrl_regs_memmap_p;
27d6ac0a 10206 lpfc_sli4_bar1_register_memmap(phba, if_type);
e4b9794e
JS
10207 } else {
10208 error = -ENOMEM;
2fcee4bf
JS
10209 goto out_iounmap_conf;
10210 }
da0436e9
JS
10211 }
10212
27d6ac0a
JS
10213 if ((if_type == LPFC_SLI_INTF_IF_TYPE_6) &&
10214 (pci_resource_start(pdev, PCI_64BIT_BAR2))) {
10215 /*
10216 * Map SLI4 if type 6 HBA Doorbell Register base to a kernel
10217 * virtual address and setup the registers.
10218 */
10219 phba->pci_bar1_map = pci_resource_start(pdev, PCI_64BIT_BAR2);
10220 bar1map_len = pci_resource_len(pdev, PCI_64BIT_BAR2);
10221 phba->sli4_hba.drbl_regs_memmap_p =
10222 ioremap(phba->pci_bar1_map, bar1map_len);
10223 if (!phba->sli4_hba.drbl_regs_memmap_p) {
10224 dev_err(&pdev->dev,
10225 "ioremap failed for SLI4 HBA doorbell registers.\n");
3a487ff7 10226 error = -ENOMEM;
27d6ac0a
JS
10227 goto out_iounmap_conf;
10228 }
10229 phba->pci_bar2_memmap_p = phba->sli4_hba.drbl_regs_memmap_p;
10230 lpfc_sli4_bar1_register_memmap(phba, if_type);
10231 }
10232
e4b9794e
JS
10233 if (if_type == LPFC_SLI_INTF_IF_TYPE_0) {
10234 if (pci_resource_start(pdev, PCI_64BIT_BAR4)) {
10235 /*
10236 * Map SLI4 if type 0 HBA Doorbell Register base to
10237 * a kernel virtual address and setup the registers.
10238 */
10239 phba->pci_bar2_map = pci_resource_start(pdev,
10240 PCI_64BIT_BAR4);
10241 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
10242 phba->sli4_hba.drbl_regs_memmap_p =
10243 ioremap(phba->pci_bar2_map,
10244 bar2map_len);
10245 if (!phba->sli4_hba.drbl_regs_memmap_p) {
10246 dev_err(&pdev->dev,
10247 "ioremap failed for SLI4 HBA"
10248 " doorbell registers.\n");
10249 error = -ENOMEM;
10250 goto out_iounmap_ctrl;
10251 }
10252 phba->pci_bar4_memmap_p =
10253 phba->sli4_hba.drbl_regs_memmap_p;
10254 error = lpfc_sli4_bar2_register_memmap(phba, LPFC_VF0);
10255 if (error)
10256 goto out_iounmap_all;
10257 } else {
10258 error = -ENOMEM;
2fcee4bf 10259 goto out_iounmap_all;
e4b9794e 10260 }
da0436e9
JS
10261 }
10262
1351e69f
JS
10263 if (if_type == LPFC_SLI_INTF_IF_TYPE_6 &&
10264 pci_resource_start(pdev, PCI_64BIT_BAR4)) {
10265 /*
10266 * Map SLI4 if type 6 HBA DPP Register base to a kernel
10267 * virtual address and setup the registers.
10268 */
10269 phba->pci_bar2_map = pci_resource_start(pdev, PCI_64BIT_BAR4);
10270 bar2map_len = pci_resource_len(pdev, PCI_64BIT_BAR4);
10271 phba->sli4_hba.dpp_regs_memmap_p =
10272 ioremap(phba->pci_bar2_map, bar2map_len);
10273 if (!phba->sli4_hba.dpp_regs_memmap_p) {
10274 dev_err(&pdev->dev,
10275 "ioremap failed for SLI4 HBA dpp registers.\n");
3a487ff7 10276 error = -ENOMEM;
1351e69f
JS
10277 goto out_iounmap_ctrl;
10278 }
10279 phba->pci_bar4_memmap_p = phba->sli4_hba.dpp_regs_memmap_p;
10280 }
10281
b71413dd 10282 /* Set up the EQ/CQ register handeling functions now */
27d6ac0a
JS
10283 switch (if_type) {
10284 case LPFC_SLI_INTF_IF_TYPE_0:
10285 case LPFC_SLI_INTF_IF_TYPE_2:
b71413dd 10286 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_eq_clr_intr;
32517fc0
JS
10287 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_write_eq_db;
10288 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_write_cq_db;
27d6ac0a
JS
10289 break;
10290 case LPFC_SLI_INTF_IF_TYPE_6:
10291 phba->sli4_hba.sli4_eq_clr_intr = lpfc_sli4_if6_eq_clr_intr;
32517fc0
JS
10292 phba->sli4_hba.sli4_write_eq_db = lpfc_sli4_if6_write_eq_db;
10293 phba->sli4_hba.sli4_write_cq_db = lpfc_sli4_if6_write_cq_db;
27d6ac0a
JS
10294 break;
10295 default:
10296 break;
b71413dd
JS
10297 }
10298
da0436e9
JS
10299 return 0;
10300
10301out_iounmap_all:
10302 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10303out_iounmap_ctrl:
10304 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
10305out_iounmap_conf:
10306 iounmap(phba->sli4_hba.conf_regs_memmap_p);
3a487ff7 10307
da0436e9
JS
10308 return error;
10309}
10310
10311/**
10312 * lpfc_sli4_pci_mem_unset - Unset SLI4 HBA PCI memory space.
10313 * @phba: pointer to lpfc hba data structure.
10314 *
10315 * This routine is invoked to unset the PCI device memory space for device
10316 * with SLI-4 interface spec.
10317 **/
10318static void
10319lpfc_sli4_pci_mem_unset(struct lpfc_hba *phba)
10320{
2e90f4b5
JS
10321 uint32_t if_type;
10322 if_type = bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf);
da0436e9 10323
2e90f4b5
JS
10324 switch (if_type) {
10325 case LPFC_SLI_INTF_IF_TYPE_0:
10326 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10327 iounmap(phba->sli4_hba.ctrl_regs_memmap_p);
10328 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10329 break;
10330 case LPFC_SLI_INTF_IF_TYPE_2:
10331 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10332 break;
27d6ac0a
JS
10333 case LPFC_SLI_INTF_IF_TYPE_6:
10334 iounmap(phba->sli4_hba.drbl_regs_memmap_p);
10335 iounmap(phba->sli4_hba.conf_regs_memmap_p);
10336 break;
2e90f4b5
JS
10337 case LPFC_SLI_INTF_IF_TYPE_1:
10338 default:
10339 dev_printk(KERN_ERR, &phba->pcidev->dev,
10340 "FATAL - unsupported SLI4 interface type - %d\n",
10341 if_type);
10342 break;
10343 }
da0436e9
JS
10344}
10345
10346/**
10347 * lpfc_sli_enable_msix - Enable MSI-X interrupt mode on SLI-3 device
10348 * @phba: pointer to lpfc hba data structure.
10349 *
10350 * This routine is invoked to enable the MSI-X interrupt vectors to device
45ffac19 10351 * with SLI-3 interface specs.
da0436e9
JS
10352 *
10353 * Return codes
af901ca1 10354 * 0 - successful
da0436e9
JS
10355 * other values - error
10356 **/
10357static int
10358lpfc_sli_enable_msix(struct lpfc_hba *phba)
10359{
45ffac19 10360 int rc;
da0436e9
JS
10361 LPFC_MBOXQ_t *pmb;
10362
10363 /* Set up MSI-X multi-message vectors */
45ffac19
CH
10364 rc = pci_alloc_irq_vectors(phba->pcidev,
10365 LPFC_MSIX_VECTORS, LPFC_MSIX_VECTORS, PCI_IRQ_MSIX);
10366 if (rc < 0) {
da0436e9
JS
10367 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10368 "0420 PCI enable MSI-X failed (%d)\n", rc);
029165ac 10369 goto vec_fail_out;
da0436e9 10370 }
45ffac19 10371
da0436e9
JS
10372 /*
10373 * Assign MSI-X vectors to interrupt handlers
10374 */
10375
10376 /* vector-0 is associated to slow-path handler */
45ffac19 10377 rc = request_irq(pci_irq_vector(phba->pcidev, 0),
ed243d37 10378 &lpfc_sli_sp_intr_handler, 0,
da0436e9
JS
10379 LPFC_SP_DRIVER_HANDLER_NAME, phba);
10380 if (rc) {
10381 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10382 "0421 MSI-X slow-path request_irq failed "
10383 "(%d)\n", rc);
10384 goto msi_fail_out;
10385 }
10386
10387 /* vector-1 is associated to fast-path handler */
45ffac19 10388 rc = request_irq(pci_irq_vector(phba->pcidev, 1),
ed243d37 10389 &lpfc_sli_fp_intr_handler, 0,
da0436e9
JS
10390 LPFC_FP_DRIVER_HANDLER_NAME, phba);
10391
10392 if (rc) {
10393 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10394 "0429 MSI-X fast-path request_irq failed "
10395 "(%d)\n", rc);
10396 goto irq_fail_out;
10397 }
10398
10399 /*
10400 * Configure HBA MSI-X attention conditions to messages
10401 */
10402 pmb = (LPFC_MBOXQ_t *) mempool_alloc(phba->mbox_mem_pool, GFP_KERNEL);
10403
10404 if (!pmb) {
10405 rc = -ENOMEM;
10406 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10407 "0474 Unable to allocate memory for issuing "
10408 "MBOX_CONFIG_MSI command\n");
10409 goto mem_fail_out;
10410 }
10411 rc = lpfc_config_msi(phba, pmb);
10412 if (rc)
10413 goto mbx_fail_out;
10414 rc = lpfc_sli_issue_mbox(phba, pmb, MBX_POLL);
10415 if (rc != MBX_SUCCESS) {
10416 lpfc_printf_log(phba, KERN_WARNING, LOG_MBOX,
10417 "0351 Config MSI mailbox command failed, "
10418 "mbxCmd x%x, mbxStatus x%x\n",
10419 pmb->u.mb.mbxCommand, pmb->u.mb.mbxStatus);
10420 goto mbx_fail_out;
10421 }
10422
10423 /* Free memory allocated for mailbox command */
10424 mempool_free(pmb, phba->mbox_mem_pool);
10425 return rc;
10426
10427mbx_fail_out:
10428 /* Free memory allocated for mailbox command */
10429 mempool_free(pmb, phba->mbox_mem_pool);
10430
10431mem_fail_out:
10432 /* free the irq already requested */
45ffac19 10433 free_irq(pci_irq_vector(phba->pcidev, 1), phba);
da0436e9
JS
10434
10435irq_fail_out:
10436 /* free the irq already requested */
45ffac19 10437 free_irq(pci_irq_vector(phba->pcidev, 0), phba);
da0436e9
JS
10438
10439msi_fail_out:
10440 /* Unconfigure MSI-X capability structure */
45ffac19 10441 pci_free_irq_vectors(phba->pcidev);
029165ac
AG
10442
10443vec_fail_out:
da0436e9
JS
10444 return rc;
10445}
10446
da0436e9
JS
10447/**
10448 * lpfc_sli_enable_msi - Enable MSI interrupt mode on SLI-3 device.
10449 * @phba: pointer to lpfc hba data structure.
10450 *
10451 * This routine is invoked to enable the MSI interrupt mode to device with
10452 * SLI-3 interface spec. The kernel function pci_enable_msi() is called to
10453 * enable the MSI vector. The device driver is responsible for calling the
10454 * request_irq() to register MSI vector with a interrupt the handler, which
10455 * is done in this function.
10456 *
10457 * Return codes
af901ca1 10458 * 0 - successful
da0436e9
JS
10459 * other values - error
10460 */
10461static int
10462lpfc_sli_enable_msi(struct lpfc_hba *phba)
10463{
10464 int rc;
10465
10466 rc = pci_enable_msi(phba->pcidev);
10467 if (!rc)
10468 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10469 "0462 PCI enable MSI mode success.\n");
10470 else {
10471 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10472 "0471 PCI enable MSI mode failed (%d)\n", rc);
10473 return rc;
10474 }
10475
10476 rc = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
ed243d37 10477 0, LPFC_DRIVER_NAME, phba);
da0436e9
JS
10478 if (rc) {
10479 pci_disable_msi(phba->pcidev);
10480 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
10481 "0478 MSI request_irq failed (%d)\n", rc);
10482 }
10483 return rc;
10484}
10485
da0436e9
JS
10486/**
10487 * lpfc_sli_enable_intr - Enable device interrupt to SLI-3 device.
10488 * @phba: pointer to lpfc hba data structure.
10489 *
10490 * This routine is invoked to enable device interrupt and associate driver's
10491 * interrupt handler(s) to interrupt vector(s) to device with SLI-3 interface
10492 * spec. Depends on the interrupt mode configured to the driver, the driver
10493 * will try to fallback from the configured interrupt mode to an interrupt
10494 * mode which is supported by the platform, kernel, and device in the order
10495 * of:
10496 * MSI-X -> MSI -> IRQ.
10497 *
10498 * Return codes
af901ca1 10499 * 0 - successful
da0436e9
JS
10500 * other values - error
10501 **/
10502static uint32_t
10503lpfc_sli_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
10504{
10505 uint32_t intr_mode = LPFC_INTR_ERROR;
10506 int retval;
10507
10508 if (cfg_mode == 2) {
10509 /* Need to issue conf_port mbox cmd before conf_msi mbox cmd */
10510 retval = lpfc_sli_config_port(phba, LPFC_SLI_REV3);
10511 if (!retval) {
10512 /* Now, try to enable MSI-X interrupt mode */
10513 retval = lpfc_sli_enable_msix(phba);
10514 if (!retval) {
10515 /* Indicate initialization to MSI-X mode */
10516 phba->intr_type = MSIX;
10517 intr_mode = 2;
10518 }
10519 }
10520 }
10521
10522 /* Fallback to MSI if MSI-X initialization failed */
10523 if (cfg_mode >= 1 && phba->intr_type == NONE) {
10524 retval = lpfc_sli_enable_msi(phba);
10525 if (!retval) {
10526 /* Indicate initialization to MSI mode */
10527 phba->intr_type = MSI;
10528 intr_mode = 1;
10529 }
10530 }
10531
10532 /* Fallback to INTx if both MSI-X/MSI initalization failed */
10533 if (phba->intr_type == NONE) {
10534 retval = request_irq(phba->pcidev->irq, lpfc_sli_intr_handler,
10535 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
10536 if (!retval) {
10537 /* Indicate initialization to INTx mode */
10538 phba->intr_type = INTx;
10539 intr_mode = 0;
10540 }
10541 }
10542 return intr_mode;
10543}
10544
10545/**
10546 * lpfc_sli_disable_intr - Disable device interrupt to SLI-3 device.
10547 * @phba: pointer to lpfc hba data structure.
10548 *
10549 * This routine is invoked to disable device interrupt and disassociate the
10550 * driver's interrupt handler(s) from interrupt vector(s) to device with
10551 * SLI-3 interface spec. Depending on the interrupt mode, the driver will
10552 * release the interrupt vector(s) for the message signaled interrupt.
10553 **/
10554static void
10555lpfc_sli_disable_intr(struct lpfc_hba *phba)
10556{
45ffac19
CH
10557 int nr_irqs, i;
10558
da0436e9 10559 if (phba->intr_type == MSIX)
45ffac19
CH
10560 nr_irqs = LPFC_MSIX_VECTORS;
10561 else
10562 nr_irqs = 1;
10563
10564 for (i = 0; i < nr_irqs; i++)
10565 free_irq(pci_irq_vector(phba->pcidev, i), phba);
10566 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
10567
10568 /* Reset interrupt management states */
10569 phba->intr_type = NONE;
10570 phba->sli.slistat.sli_intr = 0;
da0436e9
JS
10571}
10572
6a828b0f 10573/**
657add4e 10574 * lpfc_find_cpu_handle - Find the CPU that corresponds to the specified Queue
6a828b0f
JS
10575 * @phba: pointer to lpfc hba data structure.
10576 * @id: EQ vector index or Hardware Queue index
10577 * @match: LPFC_FIND_BY_EQ = match by EQ
10578 * LPFC_FIND_BY_HDWQ = match by Hardware Queue
657add4e 10579 * Return the CPU that matches the selection criteria
6a828b0f
JS
10580 */
10581static uint16_t
10582lpfc_find_cpu_handle(struct lpfc_hba *phba, uint16_t id, int match)
10583{
10584 struct lpfc_vector_map_info *cpup;
10585 int cpu;
10586
657add4e 10587 /* Loop through all CPUs */
222e9239
JS
10588 for_each_present_cpu(cpu) {
10589 cpup = &phba->sli4_hba.cpu_map[cpu];
657add4e
JS
10590
10591 /* If we are matching by EQ, there may be multiple CPUs using
10592 * using the same vector, so select the one with
10593 * LPFC_CPU_FIRST_IRQ set.
10594 */
6a828b0f 10595 if ((match == LPFC_FIND_BY_EQ) &&
657add4e 10596 (cpup->flag & LPFC_CPU_FIRST_IRQ) &&
6a828b0f
JS
10597 (cpup->irq != LPFC_VECTOR_MAP_EMPTY) &&
10598 (cpup->eq == id))
10599 return cpu;
657add4e
JS
10600
10601 /* If matching by HDWQ, select the first CPU that matches */
6a828b0f
JS
10602 if ((match == LPFC_FIND_BY_HDWQ) && (cpup->hdwq == id))
10603 return cpu;
6a828b0f
JS
10604 }
10605 return 0;
10606}
10607
6a828b0f
JS
10608#ifdef CONFIG_X86
10609/**
10610 * lpfc_find_hyper - Determine if the CPU map entry is hyper-threaded
10611 * @phba: pointer to lpfc hba data structure.
10612 * @cpu: CPU map index
10613 * @phys_id: CPU package physical id
10614 * @core_id: CPU core id
10615 */
10616static int
10617lpfc_find_hyper(struct lpfc_hba *phba, int cpu,
10618 uint16_t phys_id, uint16_t core_id)
10619{
10620 struct lpfc_vector_map_info *cpup;
10621 int idx;
10622
222e9239
JS
10623 for_each_present_cpu(idx) {
10624 cpup = &phba->sli4_hba.cpu_map[idx];
6a828b0f
JS
10625 /* Does the cpup match the one we are looking for */
10626 if ((cpup->phys_id == phys_id) &&
10627 (cpup->core_id == core_id) &&
222e9239 10628 (cpu != idx))
6a828b0f 10629 return 1;
6a828b0f
JS
10630 }
10631 return 0;
10632}
10633#endif
10634
7bb03bbf 10635/**
895427bd 10636 * lpfc_cpu_affinity_check - Check vector CPU affinity mappings
7bb03bbf 10637 * @phba: pointer to lpfc hba data structure.
895427bd
JS
10638 * @vectors: number of msix vectors allocated.
10639 *
10640 * The routine will figure out the CPU affinity assignment for every
6a828b0f 10641 * MSI-X vector allocated for the HBA.
895427bd
JS
10642 * In addition, the CPU to IO channel mapping will be calculated
10643 * and the phba->sli4_hba.cpu_map array will reflect this.
7bb03bbf 10644 */
895427bd
JS
10645static void
10646lpfc_cpu_affinity_check(struct lpfc_hba *phba, int vectors)
7bb03bbf 10647{
3ad348d9 10648 int i, cpu, idx, next_idx, new_cpu, start_cpu, first_cpu;
6a828b0f
JS
10649 int max_phys_id, min_phys_id;
10650 int max_core_id, min_core_id;
7bb03bbf 10651 struct lpfc_vector_map_info *cpup;
d9954a2d 10652 struct lpfc_vector_map_info *new_cpup;
75508a8b 10653 const struct cpumask *maskp;
7bb03bbf
JS
10654#ifdef CONFIG_X86
10655 struct cpuinfo_x86 *cpuinfo;
10656#endif
7bb03bbf
JS
10657
10658 /* Init cpu_map array */
d9954a2d
JS
10659 for_each_possible_cpu(cpu) {
10660 cpup = &phba->sli4_hba.cpu_map[cpu];
10661 cpup->phys_id = LPFC_VECTOR_MAP_EMPTY;
10662 cpup->core_id = LPFC_VECTOR_MAP_EMPTY;
10663 cpup->hdwq = LPFC_VECTOR_MAP_EMPTY;
10664 cpup->eq = LPFC_VECTOR_MAP_EMPTY;
10665 cpup->irq = LPFC_VECTOR_MAP_EMPTY;
10666 cpup->flag = 0;
10667 }
7bb03bbf 10668
6a828b0f 10669 max_phys_id = 0;
d9954a2d 10670 min_phys_id = LPFC_VECTOR_MAP_EMPTY;
6a828b0f 10671 max_core_id = 0;
d9954a2d 10672 min_core_id = LPFC_VECTOR_MAP_EMPTY;
7bb03bbf
JS
10673
10674 /* Update CPU map with physical id and core id of each CPU */
222e9239
JS
10675 for_each_present_cpu(cpu) {
10676 cpup = &phba->sli4_hba.cpu_map[cpu];
7bb03bbf
JS
10677#ifdef CONFIG_X86
10678 cpuinfo = &cpu_data(cpu);
10679 cpup->phys_id = cpuinfo->phys_proc_id;
10680 cpup->core_id = cpuinfo->cpu_core_id;
d9954a2d
JS
10681 if (lpfc_find_hyper(phba, cpu, cpup->phys_id, cpup->core_id))
10682 cpup->flag |= LPFC_CPU_MAP_HYPER;
7bb03bbf
JS
10683#else
10684 /* No distinction between CPUs for other platforms */
10685 cpup->phys_id = 0;
6a828b0f 10686 cpup->core_id = cpu;
7bb03bbf 10687#endif
6a828b0f 10688
b3295c2a 10689 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
3ad348d9
JS
10690 "3328 CPU %d physid %d coreid %d flag x%x\n",
10691 cpu, cpup->phys_id, cpup->core_id, cpup->flag);
6a828b0f
JS
10692
10693 if (cpup->phys_id > max_phys_id)
10694 max_phys_id = cpup->phys_id;
10695 if (cpup->phys_id < min_phys_id)
10696 min_phys_id = cpup->phys_id;
10697
10698 if (cpup->core_id > max_core_id)
10699 max_core_id = cpup->core_id;
10700 if (cpup->core_id < min_core_id)
10701 min_core_id = cpup->core_id;
7bb03bbf 10702 }
7bb03bbf 10703
32517fc0
JS
10704 for_each_possible_cpu(i) {
10705 struct lpfc_eq_intr_info *eqi =
10706 per_cpu_ptr(phba->sli4_hba.eq_info, i);
10707
10708 INIT_LIST_HEAD(&eqi->list);
10709 eqi->icnt = 0;
10710 }
10711
d9954a2d
JS
10712 /* This loop sets up all CPUs that are affinitized with a
10713 * irq vector assigned to the driver. All affinitized CPUs
657add4e 10714 * will get a link to that vectors IRQ and EQ.
a86c71ba
JS
10715 *
10716 * NULL affinity mask handling:
10717 * If irq count is greater than one, log an error message.
10718 * If the null mask is received for the first irq, find the
10719 * first present cpu, and assign the eq index to ensure at
10720 * least one EQ is assigned.
d9954a2d 10721 */
75508a8b 10722 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
657add4e 10723 /* Get a CPU mask for all CPUs affinitized to this vector */
75508a8b 10724 maskp = pci_irq_get_affinity(phba->pcidev, idx);
a86c71ba
JS
10725 if (!maskp) {
10726 if (phba->cfg_irq_chann > 1)
10727 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10728 "3329 No affinity mask found "
10729 "for vector %d (%d)\n",
10730 idx, phba->cfg_irq_chann);
10731 if (!idx) {
10732 cpu = cpumask_first(cpu_present_mask);
10733 cpup = &phba->sli4_hba.cpu_map[cpu];
10734 cpup->eq = idx;
10735 cpup->irq = pci_irq_vector(phba->pcidev, idx);
10736 cpup->flag |= LPFC_CPU_FIRST_IRQ;
10737 }
10738 break;
10739 }
75508a8b 10740
657add4e
JS
10741 i = 0;
10742 /* Loop through all CPUs associated with vector idx */
75508a8b 10743 for_each_cpu_and(cpu, maskp, cpu_present_mask) {
657add4e 10744 /* Set the EQ index and IRQ for that vector */
75508a8b 10745 cpup = &phba->sli4_hba.cpu_map[cpu];
6a828b0f 10746 cpup->eq = idx;
6a828b0f
JS
10747 cpup->irq = pci_irq_vector(phba->pcidev, idx);
10748
657add4e
JS
10749 /* If this is the first CPU thats assigned to this
10750 * vector, set LPFC_CPU_FIRST_IRQ.
10751 */
10752 if (!i)
10753 cpup->flag |= LPFC_CPU_FIRST_IRQ;
10754 i++;
3ad348d9
JS
10755
10756 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
10757 "3336 Set Affinity: CPU %d "
10758 "irq %d eq %d flag x%x\n",
10759 cpu, cpup->irq, cpup->eq, cpup->flag);
6a828b0f 10760 }
b3295c2a 10761 }
d9954a2d
JS
10762
10763 /* After looking at each irq vector assigned to this pcidev, its
10764 * possible to see that not ALL CPUs have been accounted for.
657add4e
JS
10765 * Next we will set any unassigned (unaffinitized) cpu map
10766 * entries to a IRQ on the same phys_id.
d9954a2d
JS
10767 */
10768 first_cpu = cpumask_first(cpu_present_mask);
10769 start_cpu = first_cpu;
10770
10771 for_each_present_cpu(cpu) {
10772 cpup = &phba->sli4_hba.cpu_map[cpu];
10773
10774 /* Is this CPU entry unassigned */
10775 if (cpup->eq == LPFC_VECTOR_MAP_EMPTY) {
10776 /* Mark CPU as IRQ not assigned by the kernel */
10777 cpup->flag |= LPFC_CPU_MAP_UNASSIGN;
10778
657add4e 10779 /* If so, find a new_cpup thats on the the SAME
d9954a2d
JS
10780 * phys_id as cpup. start_cpu will start where we
10781 * left off so all unassigned entries don't get assgined
10782 * the IRQ of the first entry.
10783 */
10784 new_cpu = start_cpu;
10785 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
10786 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
10787 if (!(new_cpup->flag & LPFC_CPU_MAP_UNASSIGN) &&
10788 (new_cpup->irq != LPFC_VECTOR_MAP_EMPTY) &&
10789 (new_cpup->phys_id == cpup->phys_id))
10790 goto found_same;
10791 new_cpu = cpumask_next(
10792 new_cpu, cpu_present_mask);
10793 if (new_cpu == nr_cpumask_bits)
10794 new_cpu = first_cpu;
10795 }
10796 /* At this point, we leave the CPU as unassigned */
10797 continue;
10798found_same:
10799 /* We found a matching phys_id, so copy the IRQ info */
10800 cpup->eq = new_cpup->eq;
d9954a2d
JS
10801 cpup->irq = new_cpup->irq;
10802
10803 /* Bump start_cpu to the next slot to minmize the
10804 * chance of having multiple unassigned CPU entries
10805 * selecting the same IRQ.
10806 */
10807 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
10808 if (start_cpu == nr_cpumask_bits)
10809 start_cpu = first_cpu;
10810
657add4e 10811 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
d9954a2d 10812 "3337 Set Affinity: CPU %d "
657add4e 10813 "irq %d from id %d same "
d9954a2d 10814 "phys_id (%d)\n",
657add4e 10815 cpu, cpup->irq, new_cpu, cpup->phys_id);
d9954a2d
JS
10816 }
10817 }
10818
10819 /* Set any unassigned cpu map entries to a IRQ on any phys_id */
10820 start_cpu = first_cpu;
10821
10822 for_each_present_cpu(cpu) {
10823 cpup = &phba->sli4_hba.cpu_map[cpu];
10824
10825 /* Is this entry unassigned */
10826 if (cpup->eq == LPFC_VECTOR_MAP_EMPTY) {
10827 /* Mark it as IRQ not assigned by the kernel */
10828 cpup->flag |= LPFC_CPU_MAP_UNASSIGN;
10829
657add4e 10830 /* If so, find a new_cpup thats on ANY phys_id
d9954a2d
JS
10831 * as the cpup. start_cpu will start where we
10832 * left off so all unassigned entries don't get
10833 * assigned the IRQ of the first entry.
10834 */
10835 new_cpu = start_cpu;
10836 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
10837 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
10838 if (!(new_cpup->flag & LPFC_CPU_MAP_UNASSIGN) &&
10839 (new_cpup->irq != LPFC_VECTOR_MAP_EMPTY))
10840 goto found_any;
10841 new_cpu = cpumask_next(
10842 new_cpu, cpu_present_mask);
10843 if (new_cpu == nr_cpumask_bits)
10844 new_cpu = first_cpu;
10845 }
10846 /* We should never leave an entry unassigned */
10847 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10848 "3339 Set Affinity: CPU %d "
657add4e
JS
10849 "irq %d UNASSIGNED\n",
10850 cpup->hdwq, cpup->irq);
d9954a2d
JS
10851 continue;
10852found_any:
10853 /* We found an available entry, copy the IRQ info */
10854 cpup->eq = new_cpup->eq;
d9954a2d
JS
10855 cpup->irq = new_cpup->irq;
10856
10857 /* Bump start_cpu to the next slot to minmize the
10858 * chance of having multiple unassigned CPU entries
10859 * selecting the same IRQ.
10860 */
10861 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
10862 if (start_cpu == nr_cpumask_bits)
10863 start_cpu = first_cpu;
10864
657add4e 10865 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
d9954a2d 10866 "3338 Set Affinity: CPU %d "
657add4e
JS
10867 "irq %d from id %d (%d/%d)\n",
10868 cpu, cpup->irq, new_cpu,
d9954a2d
JS
10869 new_cpup->phys_id, new_cpup->core_id);
10870 }
10871 }
657add4e 10872
3ad348d9
JS
10873 /* Assign hdwq indices that are unique across all cpus in the map
10874 * that are also FIRST_CPUs.
10875 */
10876 idx = 0;
10877 for_each_present_cpu(cpu) {
10878 cpup = &phba->sli4_hba.cpu_map[cpu];
10879
10880 /* Only FIRST IRQs get a hdwq index assignment. */
10881 if (!(cpup->flag & LPFC_CPU_FIRST_IRQ))
10882 continue;
10883
10884 /* 1 to 1, the first LPFC_CPU_FIRST_IRQ cpus to a unique hdwq */
10885 cpup->hdwq = idx;
10886 idx++;
10887 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10888 "3333 Set Affinity: CPU %d (phys %d core %d): "
10889 "hdwq %d eq %d irq %d flg x%x\n",
10890 cpu, cpup->phys_id, cpup->core_id,
10891 cpup->hdwq, cpup->eq, cpup->irq, cpup->flag);
10892 }
657add4e
JS
10893 /* Finally we need to associate a hdwq with each cpu_map entry
10894 * This will be 1 to 1 - hdwq to cpu, unless there are less
10895 * hardware queues then CPUs. For that case we will just round-robin
10896 * the available hardware queues as they get assigned to CPUs.
3ad348d9
JS
10897 * The next_idx is the idx from the FIRST_CPU loop above to account
10898 * for irq_chann < hdwq. The idx is used for round-robin assignments
10899 * and needs to start at 0.
657add4e 10900 */
3ad348d9 10901 next_idx = idx;
657add4e 10902 start_cpu = 0;
3ad348d9 10903 idx = 0;
657add4e
JS
10904 for_each_present_cpu(cpu) {
10905 cpup = &phba->sli4_hba.cpu_map[cpu];
657add4e 10906
3ad348d9
JS
10907 /* FIRST cpus are already mapped. */
10908 if (cpup->flag & LPFC_CPU_FIRST_IRQ)
10909 continue;
10910
10911 /* If the cfg_irq_chann < cfg_hdw_queue, set the hdwq
10912 * of the unassigned cpus to the next idx so that all
10913 * hdw queues are fully utilized.
10914 */
10915 if (next_idx < phba->cfg_hdw_queue) {
10916 cpup->hdwq = next_idx;
10917 next_idx++;
10918 continue;
10919 }
10920
10921 /* Not a First CPU and all hdw_queues are used. Reuse a
10922 * Hardware Queue for another CPU, so be smart about it
10923 * and pick one that has its IRQ/EQ mapped to the same phys_id
10924 * (CPU package) and core_id.
10925 */
10926 new_cpu = start_cpu;
10927 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
10928 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
10929 if (new_cpup->hdwq != LPFC_VECTOR_MAP_EMPTY &&
10930 new_cpup->phys_id == cpup->phys_id &&
10931 new_cpup->core_id == cpup->core_id) {
10932 goto found_hdwq;
657add4e 10933 }
3ad348d9
JS
10934 new_cpu = cpumask_next(new_cpu, cpu_present_mask);
10935 if (new_cpu == nr_cpumask_bits)
10936 new_cpu = first_cpu;
10937 }
657add4e 10938
3ad348d9
JS
10939 /* If we can't match both phys_id and core_id,
10940 * settle for just a phys_id match.
10941 */
10942 new_cpu = start_cpu;
10943 for (i = 0; i < phba->sli4_hba.num_present_cpu; i++) {
10944 new_cpup = &phba->sli4_hba.cpu_map[new_cpu];
10945 if (new_cpup->hdwq != LPFC_VECTOR_MAP_EMPTY &&
10946 new_cpup->phys_id == cpup->phys_id)
10947 goto found_hdwq;
10948
10949 new_cpu = cpumask_next(new_cpu, cpu_present_mask);
10950 if (new_cpu == nr_cpumask_bits)
10951 new_cpu = first_cpu;
657add4e 10952 }
3ad348d9
JS
10953
10954 /* Otherwise just round robin on cfg_hdw_queue */
10955 cpup->hdwq = idx % phba->cfg_hdw_queue;
10956 idx++;
10957 goto logit;
10958 found_hdwq:
10959 /* We found an available entry, copy the IRQ info */
10960 start_cpu = cpumask_next(new_cpu, cpu_present_mask);
10961 if (start_cpu == nr_cpumask_bits)
10962 start_cpu = first_cpu;
10963 cpup->hdwq = new_cpup->hdwq;
10964 logit:
657add4e
JS
10965 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
10966 "3335 Set Affinity: CPU %d (phys %d core %d): "
10967 "hdwq %d eq %d irq %d flg x%x\n",
10968 cpu, cpup->phys_id, cpup->core_id,
10969 cpup->hdwq, cpup->eq, cpup->irq, cpup->flag);
657add4e
JS
10970 }
10971
10972 /* The cpu_map array will be used later during initialization
10973 * when EQ / CQ / WQs are allocated and configured.
10974 */
b3295c2a 10975 return;
7bb03bbf 10976}
7bb03bbf 10977
da0436e9
JS
10978/**
10979 * lpfc_sli4_enable_msix - Enable MSI-X interrupt mode to SLI-4 device
10980 * @phba: pointer to lpfc hba data structure.
10981 *
10982 * This routine is invoked to enable the MSI-X interrupt vectors to device
45ffac19 10983 * with SLI-4 interface spec.
da0436e9
JS
10984 *
10985 * Return codes
af901ca1 10986 * 0 - successful
da0436e9
JS
10987 * other values - error
10988 **/
10989static int
10990lpfc_sli4_enable_msix(struct lpfc_hba *phba)
10991{
75baf696 10992 int vectors, rc, index;
b83d005e 10993 char *name;
da0436e9
JS
10994
10995 /* Set up MSI-X multi-message vectors */
6a828b0f 10996 vectors = phba->cfg_irq_chann;
45ffac19 10997
f358dd0c 10998 rc = pci_alloc_irq_vectors(phba->pcidev,
75508a8b 10999 1,
f358dd0c 11000 vectors, PCI_IRQ_MSIX | PCI_IRQ_AFFINITY);
4f871e1b 11001 if (rc < 0) {
da0436e9
JS
11002 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11003 "0484 PCI enable MSI-X failed (%d)\n", rc);
029165ac 11004 goto vec_fail_out;
da0436e9 11005 }
4f871e1b 11006 vectors = rc;
75baf696 11007
7bb03bbf 11008 /* Assign MSI-X vectors to interrupt handlers */
67d12733 11009 for (index = 0; index < vectors; index++) {
b83d005e
JS
11010 name = phba->sli4_hba.hba_eq_hdl[index].handler_name;
11011 memset(name, 0, LPFC_SLI4_HANDLER_NAME_SZ);
11012 snprintf(name, LPFC_SLI4_HANDLER_NAME_SZ,
4305f183 11013 LPFC_DRIVER_HANDLER_NAME"%d", index);
da0436e9 11014
895427bd
JS
11015 phba->sli4_hba.hba_eq_hdl[index].idx = index;
11016 phba->sli4_hba.hba_eq_hdl[index].phba = phba;
7370d10a
JS
11017 rc = request_irq(pci_irq_vector(phba->pcidev, index),
11018 &lpfc_sli4_hba_intr_handler, 0,
11019 name,
11020 &phba->sli4_hba.hba_eq_hdl[index]);
da0436e9
JS
11021 if (rc) {
11022 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
11023 "0486 MSI-X fast-path (%d) "
11024 "request_irq failed (%d)\n", index, rc);
11025 goto cfg_fail_out;
11026 }
11027 }
11028
6a828b0f 11029 if (vectors != phba->cfg_irq_chann) {
82c3e9ba
JS
11030 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11031 "3238 Reducing IO channels to match number of "
11032 "MSI-X vectors, requested %d got %d\n",
6a828b0f
JS
11033 phba->cfg_irq_chann, vectors);
11034 if (phba->cfg_irq_chann > vectors)
11035 phba->cfg_irq_chann = vectors;
82c3e9ba 11036 }
7bb03bbf 11037
da0436e9
JS
11038 return rc;
11039
11040cfg_fail_out:
11041 /* free the irq already requested */
895427bd
JS
11042 for (--index; index >= 0; index--)
11043 free_irq(pci_irq_vector(phba->pcidev, index),
11044 &phba->sli4_hba.hba_eq_hdl[index]);
da0436e9 11045
da0436e9 11046 /* Unconfigure MSI-X capability structure */
45ffac19 11047 pci_free_irq_vectors(phba->pcidev);
029165ac
AG
11048
11049vec_fail_out:
da0436e9
JS
11050 return rc;
11051}
11052
da0436e9
JS
11053/**
11054 * lpfc_sli4_enable_msi - Enable MSI interrupt mode to SLI-4 device
11055 * @phba: pointer to lpfc hba data structure.
11056 *
11057 * This routine is invoked to enable the MSI interrupt mode to device with
07b1b914
JS
11058 * SLI-4 interface spec. The kernel function pci_alloc_irq_vectors() is
11059 * called to enable the MSI vector. The device driver is responsible for
11060 * calling the request_irq() to register MSI vector with a interrupt the
11061 * handler, which is done in this function.
da0436e9
JS
11062 *
11063 * Return codes
af901ca1 11064 * 0 - successful
da0436e9
JS
11065 * other values - error
11066 **/
11067static int
11068lpfc_sli4_enable_msi(struct lpfc_hba *phba)
11069{
11070 int rc, index;
11071
07b1b914
JS
11072 rc = pci_alloc_irq_vectors(phba->pcidev, 1, 1,
11073 PCI_IRQ_MSI | PCI_IRQ_AFFINITY);
11074 if (rc > 0)
da0436e9
JS
11075 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11076 "0487 PCI enable MSI mode success.\n");
11077 else {
11078 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11079 "0488 PCI enable MSI mode failed (%d)\n", rc);
07b1b914 11080 return rc ? rc : -1;
da0436e9
JS
11081 }
11082
11083 rc = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
ed243d37 11084 0, LPFC_DRIVER_NAME, phba);
da0436e9 11085 if (rc) {
07b1b914 11086 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
11087 lpfc_printf_log(phba, KERN_WARNING, LOG_INIT,
11088 "0490 MSI request_irq failed (%d)\n", rc);
75baf696 11089 return rc;
da0436e9
JS
11090 }
11091
6a828b0f 11092 for (index = 0; index < phba->cfg_irq_chann; index++) {
895427bd
JS
11093 phba->sli4_hba.hba_eq_hdl[index].idx = index;
11094 phba->sli4_hba.hba_eq_hdl[index].phba = phba;
da0436e9
JS
11095 }
11096
75baf696 11097 return 0;
da0436e9
JS
11098}
11099
da0436e9
JS
11100/**
11101 * lpfc_sli4_enable_intr - Enable device interrupt to SLI-4 device
11102 * @phba: pointer to lpfc hba data structure.
11103 *
11104 * This routine is invoked to enable device interrupt and associate driver's
11105 * interrupt handler(s) to interrupt vector(s) to device with SLI-4
11106 * interface spec. Depends on the interrupt mode configured to the driver,
11107 * the driver will try to fallback from the configured interrupt mode to an
11108 * interrupt mode which is supported by the platform, kernel, and device in
11109 * the order of:
11110 * MSI-X -> MSI -> IRQ.
11111 *
11112 * Return codes
af901ca1 11113 * 0 - successful
da0436e9
JS
11114 * other values - error
11115 **/
11116static uint32_t
11117lpfc_sli4_enable_intr(struct lpfc_hba *phba, uint32_t cfg_mode)
11118{
11119 uint32_t intr_mode = LPFC_INTR_ERROR;
895427bd 11120 int retval, idx;
da0436e9
JS
11121
11122 if (cfg_mode == 2) {
11123 /* Preparation before conf_msi mbox cmd */
11124 retval = 0;
11125 if (!retval) {
11126 /* Now, try to enable MSI-X interrupt mode */
11127 retval = lpfc_sli4_enable_msix(phba);
11128 if (!retval) {
11129 /* Indicate initialization to MSI-X mode */
11130 phba->intr_type = MSIX;
11131 intr_mode = 2;
11132 }
11133 }
11134 }
11135
11136 /* Fallback to MSI if MSI-X initialization failed */
11137 if (cfg_mode >= 1 && phba->intr_type == NONE) {
11138 retval = lpfc_sli4_enable_msi(phba);
11139 if (!retval) {
11140 /* Indicate initialization to MSI mode */
11141 phba->intr_type = MSI;
11142 intr_mode = 1;
11143 }
11144 }
11145
11146 /* Fallback to INTx if both MSI-X/MSI initalization failed */
11147 if (phba->intr_type == NONE) {
11148 retval = request_irq(phba->pcidev->irq, lpfc_sli4_intr_handler,
11149 IRQF_SHARED, LPFC_DRIVER_NAME, phba);
11150 if (!retval) {
895427bd
JS
11151 struct lpfc_hba_eq_hdl *eqhdl;
11152
da0436e9
JS
11153 /* Indicate initialization to INTx mode */
11154 phba->intr_type = INTx;
11155 intr_mode = 0;
895427bd 11156
6a828b0f 11157 for (idx = 0; idx < phba->cfg_irq_chann; idx++) {
895427bd
JS
11158 eqhdl = &phba->sli4_hba.hba_eq_hdl[idx];
11159 eqhdl->idx = idx;
11160 eqhdl->phba = phba;
1ba981fd 11161 }
da0436e9
JS
11162 }
11163 }
11164 return intr_mode;
11165}
11166
11167/**
11168 * lpfc_sli4_disable_intr - Disable device interrupt to SLI-4 device
11169 * @phba: pointer to lpfc hba data structure.
11170 *
11171 * This routine is invoked to disable device interrupt and disassociate
11172 * the driver's interrupt handler(s) from interrupt vector(s) to device
11173 * with SLI-4 interface spec. Depending on the interrupt mode, the driver
11174 * will release the interrupt vector(s) for the message signaled interrupt.
11175 **/
11176static void
11177lpfc_sli4_disable_intr(struct lpfc_hba *phba)
11178{
11179 /* Disable the currently initialized interrupt mode */
45ffac19
CH
11180 if (phba->intr_type == MSIX) {
11181 int index;
11182
11183 /* Free up MSI-X multi-message vectors */
6a828b0f 11184 for (index = 0; index < phba->cfg_irq_chann; index++) {
b3295c2a
JS
11185 irq_set_affinity_hint(
11186 pci_irq_vector(phba->pcidev, index),
11187 NULL);
895427bd
JS
11188 free_irq(pci_irq_vector(phba->pcidev, index),
11189 &phba->sli4_hba.hba_eq_hdl[index]);
b3295c2a 11190 }
45ffac19 11191 } else {
da0436e9 11192 free_irq(phba->pcidev->irq, phba);
45ffac19
CH
11193 }
11194
11195 pci_free_irq_vectors(phba->pcidev);
da0436e9
JS
11196
11197 /* Reset interrupt management states */
11198 phba->intr_type = NONE;
11199 phba->sli.slistat.sli_intr = 0;
da0436e9
JS
11200}
11201
11202/**
11203 * lpfc_unset_hba - Unset SLI3 hba device initialization
11204 * @phba: pointer to lpfc hba data structure.
11205 *
11206 * This routine is invoked to unset the HBA device initialization steps to
11207 * a device with SLI-3 interface spec.
11208 **/
11209static void
11210lpfc_unset_hba(struct lpfc_hba *phba)
11211{
11212 struct lpfc_vport *vport = phba->pport;
11213 struct Scsi_Host *shost = lpfc_shost_from_vport(vport);
11214
11215 spin_lock_irq(shost->host_lock);
11216 vport->load_flag |= FC_UNLOADING;
11217 spin_unlock_irq(shost->host_lock);
11218
72859909
JS
11219 kfree(phba->vpi_bmask);
11220 kfree(phba->vpi_ids);
11221
da0436e9
JS
11222 lpfc_stop_hba_timers(phba);
11223
11224 phba->pport->work_port_events = 0;
11225
11226 lpfc_sli_hba_down(phba);
11227
11228 lpfc_sli_brdrestart(phba);
11229
11230 lpfc_sli_disable_intr(phba);
11231
11232 return;
11233}
11234
5af5eee7
JS
11235/**
11236 * lpfc_sli4_xri_exchange_busy_wait - Wait for device XRI exchange busy
11237 * @phba: Pointer to HBA context object.
11238 *
11239 * This function is called in the SLI4 code path to wait for completion
11240 * of device's XRIs exchange busy. It will check the XRI exchange busy
11241 * on outstanding FCP and ELS I/Os every 10ms for up to 10 seconds; after
11242 * that, it will check the XRI exchange busy on outstanding FCP and ELS
11243 * I/Os every 30 seconds, log error message, and wait forever. Only when
11244 * all XRI exchange busy complete, the driver unload shall proceed with
11245 * invoking the function reset ioctl mailbox command to the CNA and the
11246 * the rest of the driver unload resource release.
11247 **/
11248static void
11249lpfc_sli4_xri_exchange_busy_wait(struct lpfc_hba *phba)
11250{
5e5b511d 11251 struct lpfc_sli4_hdw_queue *qp;
c00f62e6 11252 int idx, ccnt;
5af5eee7 11253 int wait_time = 0;
5e5b511d 11254 int io_xri_cmpl = 1;
86c67379 11255 int nvmet_xri_cmpl = 1;
5af5eee7
JS
11256 int els_xri_cmpl = list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
11257
c3725bdc
JS
11258 /* Driver just aborted IOs during the hba_unset process. Pause
11259 * here to give the HBA time to complete the IO and get entries
11260 * into the abts lists.
11261 */
11262 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1 * 5);
11263
11264 /* Wait for NVME pending IO to flush back to transport. */
11265 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
11266 lpfc_nvme_wait_for_io_drain(phba);
11267
5e5b511d 11268 ccnt = 0;
5e5b511d
JS
11269 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
11270 qp = &phba->sli4_hba.hdwq[idx];
c00f62e6
JS
11271 io_xri_cmpl = list_empty(&qp->lpfc_abts_io_buf_list);
11272 if (!io_xri_cmpl) /* if list is NOT empty */
11273 ccnt++;
5e5b511d
JS
11274 }
11275 if (ccnt)
11276 io_xri_cmpl = 0;
5e5b511d 11277
86c67379 11278 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
86c67379
JS
11279 nvmet_xri_cmpl =
11280 list_empty(&phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
11281 }
895427bd 11282
c00f62e6 11283 while (!els_xri_cmpl || !io_xri_cmpl || !nvmet_xri_cmpl) {
5af5eee7 11284 if (wait_time > LPFC_XRI_EXCH_BUSY_WAIT_TMO) {
68c9b55d
JS
11285 if (!nvmet_xri_cmpl)
11286 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11287 "6424 NVMET XRI exchange busy "
11288 "wait time: %d seconds.\n",
11289 wait_time/1000);
5e5b511d 11290 if (!io_xri_cmpl)
895427bd 11291 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
c00f62e6 11292 "6100 IO XRI exchange busy "
5af5eee7
JS
11293 "wait time: %d seconds.\n",
11294 wait_time/1000);
11295 if (!els_xri_cmpl)
11296 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11297 "2878 ELS XRI exchange busy "
11298 "wait time: %d seconds.\n",
11299 wait_time/1000);
11300 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T2);
11301 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T2;
11302 } else {
11303 msleep(LPFC_XRI_EXCH_BUSY_WAIT_T1);
11304 wait_time += LPFC_XRI_EXCH_BUSY_WAIT_T1;
11305 }
5e5b511d
JS
11306
11307 ccnt = 0;
5e5b511d
JS
11308 for (idx = 0; idx < phba->cfg_hdw_queue; idx++) {
11309 qp = &phba->sli4_hba.hdwq[idx];
c00f62e6
JS
11310 io_xri_cmpl = list_empty(
11311 &qp->lpfc_abts_io_buf_list);
11312 if (!io_xri_cmpl) /* if list is NOT empty */
11313 ccnt++;
5e5b511d
JS
11314 }
11315 if (ccnt)
11316 io_xri_cmpl = 0;
5e5b511d 11317
86c67379 11318 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
86c67379
JS
11319 nvmet_xri_cmpl = list_empty(
11320 &phba->sli4_hba.lpfc_abts_nvmet_ctx_list);
11321 }
5af5eee7
JS
11322 els_xri_cmpl =
11323 list_empty(&phba->sli4_hba.lpfc_abts_els_sgl_list);
f358dd0c 11324
5af5eee7
JS
11325 }
11326}
11327
da0436e9
JS
11328/**
11329 * lpfc_sli4_hba_unset - Unset the fcoe hba
11330 * @phba: Pointer to HBA context object.
11331 *
11332 * This function is called in the SLI4 code path to reset the HBA's FCoE
11333 * function. The caller is not required to hold any lock. This routine
11334 * issues PCI function reset mailbox command to reset the FCoE function.
11335 * At the end of the function, it calls lpfc_hba_down_post function to
11336 * free any pending commands.
11337 **/
11338static void
11339lpfc_sli4_hba_unset(struct lpfc_hba *phba)
11340{
11341 int wait_cnt = 0;
11342 LPFC_MBOXQ_t *mboxq;
912e3acd 11343 struct pci_dev *pdev = phba->pcidev;
da0436e9
JS
11344
11345 lpfc_stop_hba_timers(phba);
cdb42bec
JS
11346 if (phba->pport)
11347 phba->sli4_hba.intr_enable = 0;
da0436e9
JS
11348
11349 /*
11350 * Gracefully wait out the potential current outstanding asynchronous
11351 * mailbox command.
11352 */
11353
11354 /* First, block any pending async mailbox command from posted */
11355 spin_lock_irq(&phba->hbalock);
11356 phba->sli.sli_flag |= LPFC_SLI_ASYNC_MBX_BLK;
11357 spin_unlock_irq(&phba->hbalock);
11358 /* Now, trying to wait it out if we can */
11359 while (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
11360 msleep(10);
11361 if (++wait_cnt > LPFC_ACTIVE_MBOX_WAIT_CNT)
11362 break;
11363 }
11364 /* Forcefully release the outstanding mailbox command if timed out */
11365 if (phba->sli.sli_flag & LPFC_SLI_MBOX_ACTIVE) {
11366 spin_lock_irq(&phba->hbalock);
11367 mboxq = phba->sli.mbox_active;
11368 mboxq->u.mb.mbxStatus = MBX_NOT_FINISHED;
11369 __lpfc_mbox_cmpl_put(phba, mboxq);
11370 phba->sli.sli_flag &= ~LPFC_SLI_MBOX_ACTIVE;
11371 phba->sli.mbox_active = NULL;
11372 spin_unlock_irq(&phba->hbalock);
11373 }
11374
5af5eee7
JS
11375 /* Abort all iocbs associated with the hba */
11376 lpfc_sli_hba_iocb_abort(phba);
11377
11378 /* Wait for completion of device XRI exchange busy */
11379 lpfc_sli4_xri_exchange_busy_wait(phba);
11380
da0436e9
JS
11381 /* Disable PCI subsystem interrupt */
11382 lpfc_sli4_disable_intr(phba);
11383
912e3acd
JS
11384 /* Disable SR-IOV if enabled */
11385 if (phba->cfg_sriov_nr_virtfn)
11386 pci_disable_sriov(pdev);
11387
da0436e9
JS
11388 /* Stop kthread signal shall trigger work_done one more time */
11389 kthread_stop(phba->worker_thread);
11390
d2cc9bcd 11391 /* Disable FW logging to host memory */
1165a5c2 11392 lpfc_ras_stop_fwlog(phba);
d2cc9bcd 11393
d1f525aa
JS
11394 /* Unset the queues shared with the hardware then release all
11395 * allocated resources.
11396 */
11397 lpfc_sli4_queue_unset(phba);
11398 lpfc_sli4_queue_destroy(phba);
11399
3677a3a7
JS
11400 /* Reset SLI4 HBA FCoE function */
11401 lpfc_pci_function_reset(phba);
11402
1165a5c2
JS
11403 /* Free RAS DMA memory */
11404 if (phba->ras_fwlog.ras_enabled)
11405 lpfc_sli4_ras_dma_free(phba);
11406
da0436e9 11407 /* Stop the SLI4 device port */
1ffdd2c0
JS
11408 if (phba->pport)
11409 phba->pport->work_port_events = 0;
da0436e9
JS
11410}
11411
28baac74
JS
11412 /**
11413 * lpfc_pc_sli4_params_get - Get the SLI4_PARAMS port capabilities.
11414 * @phba: Pointer to HBA context object.
11415 * @mboxq: Pointer to the mailboxq memory for the mailbox command response.
11416 *
11417 * This function is called in the SLI4 code path to read the port's
11418 * sli4 capabilities.
11419 *
11420 * This function may be be called from any context that can block-wait
11421 * for the completion. The expectation is that this routine is called
11422 * typically from probe_one or from the online routine.
11423 **/
11424int
11425lpfc_pc_sli4_params_get(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
11426{
11427 int rc;
11428 struct lpfc_mqe *mqe;
11429 struct lpfc_pc_sli4_params *sli4_params;
11430 uint32_t mbox_tmo;
11431
11432 rc = 0;
11433 mqe = &mboxq->u.mqe;
11434
11435 /* Read the port's SLI4 Parameters port capabilities */
fedd3b7b 11436 lpfc_pc_sli4_params(mboxq);
28baac74
JS
11437 if (!phba->sli4_hba.intr_enable)
11438 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
11439 else {
a183a15f 11440 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
28baac74
JS
11441 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
11442 }
11443
11444 if (unlikely(rc))
11445 return 1;
11446
11447 sli4_params = &phba->sli4_hba.pc_sli4_params;
11448 sli4_params->if_type = bf_get(if_type, &mqe->un.sli4_params);
11449 sli4_params->sli_rev = bf_get(sli_rev, &mqe->un.sli4_params);
11450 sli4_params->sli_family = bf_get(sli_family, &mqe->un.sli4_params);
11451 sli4_params->featurelevel_1 = bf_get(featurelevel_1,
11452 &mqe->un.sli4_params);
11453 sli4_params->featurelevel_2 = bf_get(featurelevel_2,
11454 &mqe->un.sli4_params);
11455 sli4_params->proto_types = mqe->un.sli4_params.word3;
11456 sli4_params->sge_supp_len = mqe->un.sli4_params.sge_supp_len;
11457 sli4_params->if_page_sz = bf_get(if_page_sz, &mqe->un.sli4_params);
11458 sli4_params->rq_db_window = bf_get(rq_db_window, &mqe->un.sli4_params);
11459 sli4_params->loopbk_scope = bf_get(loopbk_scope, &mqe->un.sli4_params);
11460 sli4_params->eq_pages_max = bf_get(eq_pages, &mqe->un.sli4_params);
11461 sli4_params->eqe_size = bf_get(eqe_size, &mqe->un.sli4_params);
11462 sli4_params->cq_pages_max = bf_get(cq_pages, &mqe->un.sli4_params);
11463 sli4_params->cqe_size = bf_get(cqe_size, &mqe->un.sli4_params);
11464 sli4_params->mq_pages_max = bf_get(mq_pages, &mqe->un.sli4_params);
11465 sli4_params->mqe_size = bf_get(mqe_size, &mqe->un.sli4_params);
11466 sli4_params->mq_elem_cnt = bf_get(mq_elem_cnt, &mqe->un.sli4_params);
11467 sli4_params->wq_pages_max = bf_get(wq_pages, &mqe->un.sli4_params);
11468 sli4_params->wqe_size = bf_get(wqe_size, &mqe->un.sli4_params);
11469 sli4_params->rq_pages_max = bf_get(rq_pages, &mqe->un.sli4_params);
11470 sli4_params->rqe_size = bf_get(rqe_size, &mqe->un.sli4_params);
11471 sli4_params->hdr_pages_max = bf_get(hdr_pages, &mqe->un.sli4_params);
11472 sli4_params->hdr_size = bf_get(hdr_size, &mqe->un.sli4_params);
11473 sli4_params->hdr_pp_align = bf_get(hdr_pp_align, &mqe->un.sli4_params);
11474 sli4_params->sgl_pages_max = bf_get(sgl_pages, &mqe->un.sli4_params);
11475 sli4_params->sgl_pp_align = bf_get(sgl_pp_align, &mqe->un.sli4_params);
0558056c
JS
11476
11477 /* Make sure that sge_supp_len can be handled by the driver */
11478 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
11479 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
11480
28baac74
JS
11481 return rc;
11482}
11483
fedd3b7b
JS
11484/**
11485 * lpfc_get_sli4_parameters - Get the SLI4 Config PARAMETERS.
11486 * @phba: Pointer to HBA context object.
11487 * @mboxq: Pointer to the mailboxq memory for the mailbox command response.
11488 *
11489 * This function is called in the SLI4 code path to read the port's
11490 * sli4 capabilities.
11491 *
11492 * This function may be be called from any context that can block-wait
11493 * for the completion. The expectation is that this routine is called
11494 * typically from probe_one or from the online routine.
11495 **/
11496int
11497lpfc_get_sli4_parameters(struct lpfc_hba *phba, LPFC_MBOXQ_t *mboxq)
11498{
11499 int rc;
11500 struct lpfc_mqe *mqe = &mboxq->u.mqe;
11501 struct lpfc_pc_sli4_params *sli4_params;
a183a15f 11502 uint32_t mbox_tmo;
fedd3b7b 11503 int length;
bf316c78 11504 bool exp_wqcq_pages = true;
fedd3b7b
JS
11505 struct lpfc_sli4_parameters *mbx_sli4_parameters;
11506
6d368e53
JS
11507 /*
11508 * By default, the driver assumes the SLI4 port requires RPI
11509 * header postings. The SLI4_PARAM response will correct this
11510 * assumption.
11511 */
11512 phba->sli4_hba.rpi_hdrs_in_use = 1;
11513
fedd3b7b
JS
11514 /* Read the port's SLI4 Config Parameters */
11515 length = (sizeof(struct lpfc_mbx_get_sli4_parameters) -
11516 sizeof(struct lpfc_sli4_cfg_mhdr));
11517 lpfc_sli4_config(phba, mboxq, LPFC_MBOX_SUBSYSTEM_COMMON,
11518 LPFC_MBOX_OPCODE_GET_SLI4_PARAMETERS,
11519 length, LPFC_SLI4_MBX_EMBED);
11520 if (!phba->sli4_hba.intr_enable)
11521 rc = lpfc_sli_issue_mbox(phba, mboxq, MBX_POLL);
a183a15f
JS
11522 else {
11523 mbox_tmo = lpfc_mbox_tmo_val(phba, mboxq);
11524 rc = lpfc_sli_issue_mbox_wait(phba, mboxq, mbox_tmo);
11525 }
fedd3b7b
JS
11526 if (unlikely(rc))
11527 return rc;
11528 sli4_params = &phba->sli4_hba.pc_sli4_params;
11529 mbx_sli4_parameters = &mqe->un.get_sli4_parameters.sli4_parameters;
11530 sli4_params->if_type = bf_get(cfg_if_type, mbx_sli4_parameters);
11531 sli4_params->sli_rev = bf_get(cfg_sli_rev, mbx_sli4_parameters);
11532 sli4_params->sli_family = bf_get(cfg_sli_family, mbx_sli4_parameters);
11533 sli4_params->featurelevel_1 = bf_get(cfg_sli_hint_1,
11534 mbx_sli4_parameters);
11535 sli4_params->featurelevel_2 = bf_get(cfg_sli_hint_2,
11536 mbx_sli4_parameters);
11537 if (bf_get(cfg_phwq, mbx_sli4_parameters))
11538 phba->sli3_options |= LPFC_SLI4_PHWQ_ENABLED;
11539 else
11540 phba->sli3_options &= ~LPFC_SLI4_PHWQ_ENABLED;
11541 sli4_params->sge_supp_len = mbx_sli4_parameters->sge_supp_len;
11542 sli4_params->loopbk_scope = bf_get(loopbk_scope, mbx_sli4_parameters);
1ba981fd 11543 sli4_params->oas_supported = bf_get(cfg_oas, mbx_sli4_parameters);
fedd3b7b
JS
11544 sli4_params->cqv = bf_get(cfg_cqv, mbx_sli4_parameters);
11545 sli4_params->mqv = bf_get(cfg_mqv, mbx_sli4_parameters);
11546 sli4_params->wqv = bf_get(cfg_wqv, mbx_sli4_parameters);
11547 sli4_params->rqv = bf_get(cfg_rqv, mbx_sli4_parameters);
7365f6fd
JS
11548 sli4_params->eqav = bf_get(cfg_eqav, mbx_sli4_parameters);
11549 sli4_params->cqav = bf_get(cfg_cqav, mbx_sli4_parameters);
0c651878 11550 sli4_params->wqsize = bf_get(cfg_wqsize, mbx_sli4_parameters);
66e9e6bf 11551 sli4_params->bv1s = bf_get(cfg_bv1s, mbx_sli4_parameters);
fedd3b7b
JS
11552 sli4_params->sgl_pages_max = bf_get(cfg_sgl_page_cnt,
11553 mbx_sli4_parameters);
895427bd 11554 sli4_params->wqpcnt = bf_get(cfg_wqpcnt, mbx_sli4_parameters);
fedd3b7b
JS
11555 sli4_params->sgl_pp_align = bf_get(cfg_sgl_pp_align,
11556 mbx_sli4_parameters);
6d368e53
JS
11557 phba->sli4_hba.extents_in_use = bf_get(cfg_ext, mbx_sli4_parameters);
11558 phba->sli4_hba.rpi_hdrs_in_use = bf_get(cfg_hdrr, mbx_sli4_parameters);
c15e0704 11559
d79c9e9d
JS
11560 /* Check for Extended Pre-Registered SGL support */
11561 phba->cfg_xpsgl = bf_get(cfg_xpsgl, mbx_sli4_parameters);
11562
c15e0704
JS
11563 /* Check for firmware nvme support */
11564 rc = (bf_get(cfg_nvme, mbx_sli4_parameters) &&
11565 bf_get(cfg_xib, mbx_sli4_parameters));
11566
11567 if (rc) {
11568 /* Save this to indicate the Firmware supports NVME */
11569 sli4_params->nvme = 1;
11570
11571 /* Firmware NVME support, check driver FC4 NVME support */
11572 if (phba->cfg_enable_fc4_type == LPFC_ENABLE_FCP) {
11573 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
11574 "6133 Disabling NVME support: "
11575 "FC4 type not supported: x%x\n",
11576 phba->cfg_enable_fc4_type);
11577 goto fcponly;
11578 }
11579 } else {
11580 /* No firmware NVME support, check driver FC4 NVME support */
11581 sli4_params->nvme = 0;
11582 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
11583 lpfc_printf_log(phba, KERN_ERR, LOG_INIT | LOG_NVME,
11584 "6101 Disabling NVME support: Not "
11585 "supported by firmware (%d %d) x%x\n",
11586 bf_get(cfg_nvme, mbx_sli4_parameters),
11587 bf_get(cfg_xib, mbx_sli4_parameters),
11588 phba->cfg_enable_fc4_type);
11589fcponly:
11590 phba->nvme_support = 0;
11591 phba->nvmet_support = 0;
11592 phba->cfg_nvmet_mrq = 0;
6a224b47 11593 phba->cfg_nvme_seg_cnt = 0;
c15e0704
JS
11594
11595 /* If no FC4 type support, move to just SCSI support */
11596 if (!(phba->cfg_enable_fc4_type & LPFC_ENABLE_FCP))
11597 return -ENODEV;
11598 phba->cfg_enable_fc4_type = LPFC_ENABLE_FCP;
11599 }
895427bd 11600 }
0558056c 11601
c26c265b 11602 /* If the NVME FC4 type is enabled, scale the sg_seg_cnt to
a5f7337f 11603 * accommodate 512K and 1M IOs in a single nvme buf.
c26c265b 11604 */
a5f7337f 11605 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME)
c26c265b 11606 phba->cfg_sg_seg_cnt = LPFC_MAX_NVME_SEG_CNT;
c26c265b 11607
414abe0a
JS
11608 /* Only embed PBDE for if_type 6, PBDE support requires xib be set */
11609 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) !=
11610 LPFC_SLI_INTF_IF_TYPE_6) || (!bf_get(cfg_xib, mbx_sli4_parameters)))
11611 phba->cfg_enable_pbde = 0;
0bc2b7c5 11612
20aefac3
JS
11613 /*
11614 * To support Suppress Response feature we must satisfy 3 conditions.
11615 * lpfc_suppress_rsp module parameter must be set (default).
11616 * In SLI4-Parameters Descriptor:
11617 * Extended Inline Buffers (XIB) must be supported.
11618 * Suppress Response IU Not Supported (SRIUNS) must NOT be supported
11619 * (double negative).
11620 */
11621 if (phba->cfg_suppress_rsp && bf_get(cfg_xib, mbx_sli4_parameters) &&
11622 !(bf_get(cfg_nosr, mbx_sli4_parameters)))
f358dd0c 11623 phba->sli.sli_flag |= LPFC_SLI_SUPPRESS_RSP;
20aefac3
JS
11624 else
11625 phba->cfg_suppress_rsp = 0;
f358dd0c 11626
0cf07f84
JS
11627 if (bf_get(cfg_eqdr, mbx_sli4_parameters))
11628 phba->sli.sli_flag |= LPFC_SLI_USE_EQDR;
11629
0558056c
JS
11630 /* Make sure that sge_supp_len can be handled by the driver */
11631 if (sli4_params->sge_supp_len > LPFC_MAX_SGE_SIZE)
11632 sli4_params->sge_supp_len = LPFC_MAX_SGE_SIZE;
11633
b5c53958 11634 /*
c176ffa0
JS
11635 * Check whether the adapter supports an embedded copy of the
11636 * FCP CMD IU within the WQE for FCP_Ixxx commands. In order
11637 * to use this option, 128-byte WQEs must be used.
b5c53958
JS
11638 */
11639 if (bf_get(cfg_ext_embed_cb, mbx_sli4_parameters))
11640 phba->fcp_embed_io = 1;
11641 else
11642 phba->fcp_embed_io = 0;
7bdedb34 11643
0bc2b7c5 11644 lpfc_printf_log(phba, KERN_INFO, LOG_INIT | LOG_NVME,
414abe0a 11645 "6422 XIB %d PBDE %d: FCP %d NVME %d %d %d\n",
0bc2b7c5 11646 bf_get(cfg_xib, mbx_sli4_parameters),
414abe0a
JS
11647 phba->cfg_enable_pbde,
11648 phba->fcp_embed_io, phba->nvme_support,
4e565cf0 11649 phba->cfg_nvme_embed_cmd, phba->cfg_suppress_rsp);
0bc2b7c5 11650
bf316c78
JS
11651 if ((bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) ==
11652 LPFC_SLI_INTF_IF_TYPE_2) &&
11653 (bf_get(lpfc_sli_intf_sli_family, &phba->sli4_hba.sli_intf) ==
c221768b 11654 LPFC_SLI_INTF_FAMILY_LNCR_A0))
bf316c78
JS
11655 exp_wqcq_pages = false;
11656
c176ffa0
JS
11657 if ((bf_get(cfg_cqpsize, mbx_sli4_parameters) & LPFC_CQ_16K_PAGE_SZ) &&
11658 (bf_get(cfg_wqpsize, mbx_sli4_parameters) & LPFC_WQ_16K_PAGE_SZ) &&
bf316c78 11659 exp_wqcq_pages &&
c176ffa0
JS
11660 (sli4_params->wqsize & LPFC_WQ_SZ128_SUPPORT))
11661 phba->enab_exp_wqcq_pages = 1;
11662 else
11663 phba->enab_exp_wqcq_pages = 0;
7bdedb34
JS
11664 /*
11665 * Check if the SLI port supports MDS Diagnostics
11666 */
11667 if (bf_get(cfg_mds_diags, mbx_sli4_parameters))
11668 phba->mds_diags_support = 1;
11669 else
11670 phba->mds_diags_support = 0;
d2cc9bcd 11671
0d8af096
JS
11672 /*
11673 * Check if the SLI port supports NSLER
11674 */
11675 if (bf_get(cfg_nsler, mbx_sli4_parameters))
11676 phba->nsler = 1;
11677 else
11678 phba->nsler = 0;
11679
fedd3b7b
JS
11680 return 0;
11681}
11682
da0436e9
JS
11683/**
11684 * lpfc_pci_probe_one_s3 - PCI probe func to reg SLI-3 device to PCI subsystem.
11685 * @pdev: pointer to PCI device
11686 * @pid: pointer to PCI device identifier
11687 *
11688 * This routine is to be called to attach a device with SLI-3 interface spec
11689 * to the PCI subsystem. When an Emulex HBA with SLI-3 interface spec is
11690 * presented on PCI bus, the kernel PCI subsystem looks at PCI device-specific
11691 * information of the device and driver to see if the driver state that it can
11692 * support this kind of device. If the match is successful, the driver core
11693 * invokes this routine. If this routine determines it can claim the HBA, it
11694 * does all the initialization that it needs to do to handle the HBA properly.
11695 *
11696 * Return code
11697 * 0 - driver can claim the device
11698 * negative value - driver can not claim the device
11699 **/
6f039790 11700static int
da0436e9
JS
11701lpfc_pci_probe_one_s3(struct pci_dev *pdev, const struct pci_device_id *pid)
11702{
11703 struct lpfc_hba *phba;
11704 struct lpfc_vport *vport = NULL;
6669f9bb 11705 struct Scsi_Host *shost = NULL;
da0436e9
JS
11706 int error;
11707 uint32_t cfg_mode, intr_mode;
11708
11709 /* Allocate memory for HBA structure */
11710 phba = lpfc_hba_alloc(pdev);
11711 if (!phba)
11712 return -ENOMEM;
11713
11714 /* Perform generic PCI device enabling operation */
11715 error = lpfc_enable_pci_dev(phba);
079b5c91 11716 if (error)
da0436e9 11717 goto out_free_phba;
da0436e9
JS
11718
11719 /* Set up SLI API function jump table for PCI-device group-0 HBAs */
11720 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_LP);
11721 if (error)
11722 goto out_disable_pci_dev;
11723
11724 /* Set up SLI-3 specific device PCI memory space */
11725 error = lpfc_sli_pci_mem_setup(phba);
11726 if (error) {
11727 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11728 "1402 Failed to set up pci memory space.\n");
11729 goto out_disable_pci_dev;
11730 }
11731
da0436e9
JS
11732 /* Set up SLI-3 specific device driver resources */
11733 error = lpfc_sli_driver_resource_setup(phba);
11734 if (error) {
11735 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11736 "1404 Failed to set up driver resource.\n");
11737 goto out_unset_pci_mem_s3;
11738 }
11739
11740 /* Initialize and populate the iocb list per host */
d1f525aa 11741
da0436e9
JS
11742 error = lpfc_init_iocb_list(phba, LPFC_IOCB_LIST_CNT);
11743 if (error) {
11744 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11745 "1405 Failed to initialize iocb list.\n");
11746 goto out_unset_driver_resource_s3;
11747 }
11748
11749 /* Set up common device driver resources */
11750 error = lpfc_setup_driver_resource_phase2(phba);
11751 if (error) {
11752 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11753 "1406 Failed to set up driver resource.\n");
11754 goto out_free_iocb_list;
11755 }
11756
079b5c91
JS
11757 /* Get the default values for Model Name and Description */
11758 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
11759
da0436e9
JS
11760 /* Create SCSI host to the physical port */
11761 error = lpfc_create_shost(phba);
11762 if (error) {
11763 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11764 "1407 Failed to create scsi host.\n");
11765 goto out_unset_driver_resource;
11766 }
11767
11768 /* Configure sysfs attributes */
11769 vport = phba->pport;
11770 error = lpfc_alloc_sysfs_attr(vport);
11771 if (error) {
11772 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11773 "1476 Failed to allocate sysfs attr\n");
11774 goto out_destroy_shost;
11775 }
11776
6669f9bb 11777 shost = lpfc_shost_from_vport(vport); /* save shost for error cleanup */
da0436e9
JS
11778 /* Now, trying to enable interrupt and bring up the device */
11779 cfg_mode = phba->cfg_use_msi;
11780 while (true) {
11781 /* Put device to a known state before enabling interrupt */
11782 lpfc_stop_port(phba);
11783 /* Configure and enable interrupt */
11784 intr_mode = lpfc_sli_enable_intr(phba, cfg_mode);
11785 if (intr_mode == LPFC_INTR_ERROR) {
11786 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11787 "0431 Failed to enable interrupt.\n");
11788 error = -ENODEV;
11789 goto out_free_sysfs_attr;
11790 }
11791 /* SLI-3 HBA setup */
11792 if (lpfc_sli_hba_setup(phba)) {
11793 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
11794 "1477 Failed to set up hba\n");
11795 error = -ENODEV;
11796 goto out_remove_device;
11797 }
11798
11799 /* Wait 50ms for the interrupts of previous mailbox commands */
11800 msleep(50);
11801 /* Check active interrupts on message signaled interrupts */
11802 if (intr_mode == 0 ||
11803 phba->sli.slistat.sli_intr > LPFC_MSIX_VECTORS) {
11804 /* Log the current active interrupt mode */
11805 phba->intr_mode = intr_mode;
11806 lpfc_log_intr_mode(phba, intr_mode);
11807 break;
11808 } else {
11809 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11810 "0447 Configure interrupt mode (%d) "
11811 "failed active interrupt test.\n",
11812 intr_mode);
11813 /* Disable the current interrupt mode */
11814 lpfc_sli_disable_intr(phba);
11815 /* Try next level of interrupt mode */
11816 cfg_mode = --intr_mode;
11817 }
11818 }
11819
11820 /* Perform post initialization setup */
11821 lpfc_post_init_setup(phba);
11822
11823 /* Check if there are static vports to be created. */
11824 lpfc_create_static_vport(phba);
11825
11826 return 0;
11827
11828out_remove_device:
11829 lpfc_unset_hba(phba);
11830out_free_sysfs_attr:
11831 lpfc_free_sysfs_attr(vport);
11832out_destroy_shost:
11833 lpfc_destroy_shost(phba);
11834out_unset_driver_resource:
11835 lpfc_unset_driver_resource_phase2(phba);
11836out_free_iocb_list:
11837 lpfc_free_iocb_list(phba);
11838out_unset_driver_resource_s3:
11839 lpfc_sli_driver_resource_unset(phba);
11840out_unset_pci_mem_s3:
11841 lpfc_sli_pci_mem_unset(phba);
11842out_disable_pci_dev:
11843 lpfc_disable_pci_dev(phba);
6669f9bb
JS
11844 if (shost)
11845 scsi_host_put(shost);
da0436e9
JS
11846out_free_phba:
11847 lpfc_hba_free(phba);
11848 return error;
11849}
11850
11851/**
11852 * lpfc_pci_remove_one_s3 - PCI func to unreg SLI-3 device from PCI subsystem.
11853 * @pdev: pointer to PCI device
11854 *
11855 * This routine is to be called to disattach a device with SLI-3 interface
11856 * spec from PCI subsystem. When an Emulex HBA with SLI-3 interface spec is
11857 * removed from PCI bus, it performs all the necessary cleanup for the HBA
11858 * device to be removed from the PCI subsystem properly.
11859 **/
6f039790 11860static void
da0436e9
JS
11861lpfc_pci_remove_one_s3(struct pci_dev *pdev)
11862{
11863 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11864 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
11865 struct lpfc_vport **vports;
11866 struct lpfc_hba *phba = vport->phba;
11867 int i;
da0436e9
JS
11868
11869 spin_lock_irq(&phba->hbalock);
11870 vport->load_flag |= FC_UNLOADING;
11871 spin_unlock_irq(&phba->hbalock);
11872
11873 lpfc_free_sysfs_attr(vport);
11874
11875 /* Release all the vports against this physical port */
11876 vports = lpfc_create_vport_work_array(phba);
11877 if (vports != NULL)
587a37f6
JS
11878 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
11879 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
11880 continue;
da0436e9 11881 fc_vport_terminate(vports[i]->fc_vport);
587a37f6 11882 }
da0436e9
JS
11883 lpfc_destroy_vport_work_array(phba, vports);
11884
11885 /* Remove FC host and then SCSI host with the physical port */
11886 fc_remove_host(shost);
11887 scsi_remove_host(shost);
d613b6a7 11888
da0436e9
JS
11889 lpfc_cleanup(vport);
11890
11891 /*
11892 * Bring down the SLI Layer. This step disable all interrupts,
11893 * clears the rings, discards all mailbox commands, and resets
11894 * the HBA.
11895 */
11896
48e34d0f 11897 /* HBA interrupt will be disabled after this call */
da0436e9
JS
11898 lpfc_sli_hba_down(phba);
11899 /* Stop kthread signal shall trigger work_done one more time */
11900 kthread_stop(phba->worker_thread);
11901 /* Final cleanup of txcmplq and reset the HBA */
11902 lpfc_sli_brdrestart(phba);
11903
72859909
JS
11904 kfree(phba->vpi_bmask);
11905 kfree(phba->vpi_ids);
11906
da0436e9 11907 lpfc_stop_hba_timers(phba);
523128e5 11908 spin_lock_irq(&phba->port_list_lock);
da0436e9 11909 list_del_init(&vport->listentry);
523128e5 11910 spin_unlock_irq(&phba->port_list_lock);
da0436e9
JS
11911
11912 lpfc_debugfs_terminate(vport);
11913
912e3acd
JS
11914 /* Disable SR-IOV if enabled */
11915 if (phba->cfg_sriov_nr_virtfn)
11916 pci_disable_sriov(pdev);
11917
da0436e9
JS
11918 /* Disable interrupt */
11919 lpfc_sli_disable_intr(phba);
11920
da0436e9
JS
11921 scsi_host_put(shost);
11922
11923 /*
11924 * Call scsi_free before mem_free since scsi bufs are released to their
11925 * corresponding pools here.
11926 */
11927 lpfc_scsi_free(phba);
0794d601
JS
11928 lpfc_free_iocb_list(phba);
11929
da0436e9
JS
11930 lpfc_mem_free_all(phba);
11931
11932 dma_free_coherent(&pdev->dev, lpfc_sli_hbq_size(),
11933 phba->hbqslimp.virt, phba->hbqslimp.phys);
11934
11935 /* Free resources associated with SLI2 interface */
11936 dma_free_coherent(&pdev->dev, SLI2_SLIM_SIZE,
11937 phba->slim2p.virt, phba->slim2p.phys);
11938
11939 /* unmap adapter SLIM and Control Registers */
11940 iounmap(phba->ctrl_regs_memmap_p);
11941 iounmap(phba->slim_memmap_p);
11942
11943 lpfc_hba_free(phba);
11944
e0c0483c 11945 pci_release_mem_regions(pdev);
da0436e9
JS
11946 pci_disable_device(pdev);
11947}
11948
11949/**
11950 * lpfc_pci_suspend_one_s3 - PCI func to suspend SLI-3 device for power mgmnt
11951 * @pdev: pointer to PCI device
11952 * @msg: power management message
11953 *
11954 * This routine is to be called from the kernel's PCI subsystem to support
11955 * system Power Management (PM) to device with SLI-3 interface spec. When
11956 * PM invokes this method, it quiesces the device by stopping the driver's
11957 * worker thread for the device, turning off device's interrupt and DMA,
11958 * and bring the device offline. Note that as the driver implements the
11959 * minimum PM requirements to a power-aware driver's PM support for the
11960 * suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE, FREEZE)
11961 * to the suspend() method call will be treated as SUSPEND and the driver will
11962 * fully reinitialize its device during resume() method call, the driver will
11963 * set device to PCI_D3hot state in PCI config space instead of setting it
11964 * according to the @msg provided by the PM.
11965 *
11966 * Return code
11967 * 0 - driver suspended the device
11968 * Error otherwise
11969 **/
11970static int
11971lpfc_pci_suspend_one_s3(struct pci_dev *pdev, pm_message_t msg)
11972{
11973 struct Scsi_Host *shost = pci_get_drvdata(pdev);
11974 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
11975
11976 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
11977 "0473 PCI device Power Management suspend.\n");
11978
11979 /* Bring down the device */
618a5230 11980 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
da0436e9
JS
11981 lpfc_offline(phba);
11982 kthread_stop(phba->worker_thread);
11983
11984 /* Disable interrupt from device */
11985 lpfc_sli_disable_intr(phba);
11986
11987 /* Save device state to PCI config space */
11988 pci_save_state(pdev);
11989 pci_set_power_state(pdev, PCI_D3hot);
11990
11991 return 0;
11992}
11993
11994/**
11995 * lpfc_pci_resume_one_s3 - PCI func to resume SLI-3 device for power mgmnt
11996 * @pdev: pointer to PCI device
11997 *
11998 * This routine is to be called from the kernel's PCI subsystem to support
11999 * system Power Management (PM) to device with SLI-3 interface spec. When PM
12000 * invokes this method, it restores the device's PCI config space state and
12001 * fully reinitializes the device and brings it online. Note that as the
12002 * driver implements the minimum PM requirements to a power-aware driver's
12003 * PM for suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE,
12004 * FREEZE) to the suspend() method call will be treated as SUSPEND and the
12005 * driver will fully reinitialize its device during resume() method call,
12006 * the device will be set to PCI_D0 directly in PCI config space before
12007 * restoring the state.
12008 *
12009 * Return code
12010 * 0 - driver suspended the device
12011 * Error otherwise
12012 **/
12013static int
12014lpfc_pci_resume_one_s3(struct pci_dev *pdev)
12015{
12016 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12017 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12018 uint32_t intr_mode;
12019 int error;
12020
12021 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
12022 "0452 PCI device Power Management resume.\n");
12023
12024 /* Restore device state from PCI config space */
12025 pci_set_power_state(pdev, PCI_D0);
12026 pci_restore_state(pdev);
0d878419 12027
1dfb5a47
JS
12028 /*
12029 * As the new kernel behavior of pci_restore_state() API call clears
12030 * device saved_state flag, need to save the restored state again.
12031 */
12032 pci_save_state(pdev);
12033
da0436e9
JS
12034 if (pdev->is_busmaster)
12035 pci_set_master(pdev);
12036
12037 /* Startup the kernel thread for this host adapter. */
12038 phba->worker_thread = kthread_run(lpfc_do_work, phba,
12039 "lpfc_worker_%d", phba->brd_no);
12040 if (IS_ERR(phba->worker_thread)) {
12041 error = PTR_ERR(phba->worker_thread);
12042 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12043 "0434 PM resume failed to start worker "
12044 "thread: error=x%x.\n", error);
12045 return error;
12046 }
12047
12048 /* Configure and enable interrupt */
12049 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
12050 if (intr_mode == LPFC_INTR_ERROR) {
12051 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12052 "0430 PM resume Failed to enable interrupt\n");
12053 return -EIO;
12054 } else
12055 phba->intr_mode = intr_mode;
12056
12057 /* Restart HBA and bring it online */
12058 lpfc_sli_brdrestart(phba);
12059 lpfc_online(phba);
12060
12061 /* Log the current active interrupt mode */
12062 lpfc_log_intr_mode(phba, phba->intr_mode);
12063
12064 return 0;
12065}
12066
891478a2
JS
12067/**
12068 * lpfc_sli_prep_dev_for_recover - Prepare SLI3 device for pci slot recover
12069 * @phba: pointer to lpfc hba data structure.
12070 *
12071 * This routine is called to prepare the SLI3 device for PCI slot recover. It
e2af0d2e 12072 * aborts all the outstanding SCSI I/Os to the pci device.
891478a2
JS
12073 **/
12074static void
12075lpfc_sli_prep_dev_for_recover(struct lpfc_hba *phba)
12076{
12077 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12078 "2723 PCI channel I/O abort preparing for recovery\n");
e2af0d2e
JS
12079
12080 /*
12081 * There may be errored I/Os through HBA, abort all I/Os on txcmplq
12082 * and let the SCSI mid-layer to retry them to recover.
12083 */
db55fba8 12084 lpfc_sli_abort_fcp_rings(phba);
891478a2
JS
12085}
12086
0d878419
JS
12087/**
12088 * lpfc_sli_prep_dev_for_reset - Prepare SLI3 device for pci slot reset
12089 * @phba: pointer to lpfc hba data structure.
12090 *
12091 * This routine is called to prepare the SLI3 device for PCI slot reset. It
12092 * disables the device interrupt and pci device, and aborts the internal FCP
12093 * pending I/Os.
12094 **/
12095static void
12096lpfc_sli_prep_dev_for_reset(struct lpfc_hba *phba)
12097{
0d878419 12098 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
891478a2 12099 "2710 PCI channel disable preparing for reset\n");
e2af0d2e 12100
75baf696 12101 /* Block any management I/Os to the device */
618a5230 12102 lpfc_block_mgmt_io(phba, LPFC_MBX_WAIT);
75baf696 12103
e2af0d2e
JS
12104 /* Block all SCSI devices' I/Os on the host */
12105 lpfc_scsi_dev_block(phba);
12106
ea714f3d 12107 /* Flush all driver's outstanding SCSI I/Os as we are to reset */
c00f62e6 12108 lpfc_sli_flush_io_rings(phba);
ea714f3d 12109
e2af0d2e
JS
12110 /* stop all timers */
12111 lpfc_stop_hba_timers(phba);
12112
0d878419
JS
12113 /* Disable interrupt and pci device */
12114 lpfc_sli_disable_intr(phba);
12115 pci_disable_device(phba->pcidev);
0d878419
JS
12116}
12117
12118/**
12119 * lpfc_sli_prep_dev_for_perm_failure - Prepare SLI3 dev for pci slot disable
12120 * @phba: pointer to lpfc hba data structure.
12121 *
12122 * This routine is called to prepare the SLI3 device for PCI slot permanently
12123 * disabling. It blocks the SCSI transport layer traffic and flushes the FCP
12124 * pending I/Os.
12125 **/
12126static void
75baf696 12127lpfc_sli_prep_dev_for_perm_failure(struct lpfc_hba *phba)
0d878419
JS
12128{
12129 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
891478a2 12130 "2711 PCI channel permanent disable for failure\n");
e2af0d2e
JS
12131 /* Block all SCSI devices' I/Os on the host */
12132 lpfc_scsi_dev_block(phba);
12133
12134 /* stop all timers */
12135 lpfc_stop_hba_timers(phba);
12136
0d878419 12137 /* Clean up all driver's outstanding SCSI I/Os */
c00f62e6 12138 lpfc_sli_flush_io_rings(phba);
0d878419
JS
12139}
12140
da0436e9
JS
12141/**
12142 * lpfc_io_error_detected_s3 - Method for handling SLI-3 device PCI I/O error
12143 * @pdev: pointer to PCI device.
12144 * @state: the current PCI connection state.
12145 *
12146 * This routine is called from the PCI subsystem for I/O error handling to
12147 * device with SLI-3 interface spec. This function is called by the PCI
12148 * subsystem after a PCI bus error affecting this device has been detected.
12149 * When this function is invoked, it will need to stop all the I/Os and
12150 * interrupt(s) to the device. Once that is done, it will return
12151 * PCI_ERS_RESULT_NEED_RESET for the PCI subsystem to perform proper recovery
12152 * as desired.
12153 *
12154 * Return codes
0d878419 12155 * PCI_ERS_RESULT_CAN_RECOVER - can be recovered with reset_link
da0436e9
JS
12156 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
12157 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
12158 **/
12159static pci_ers_result_t
12160lpfc_io_error_detected_s3(struct pci_dev *pdev, pci_channel_state_t state)
12161{
12162 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12163 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
da0436e9 12164
0d878419
JS
12165 switch (state) {
12166 case pci_channel_io_normal:
891478a2
JS
12167 /* Non-fatal error, prepare for recovery */
12168 lpfc_sli_prep_dev_for_recover(phba);
0d878419
JS
12169 return PCI_ERS_RESULT_CAN_RECOVER;
12170 case pci_channel_io_frozen:
12171 /* Fatal error, prepare for slot reset */
12172 lpfc_sli_prep_dev_for_reset(phba);
12173 return PCI_ERS_RESULT_NEED_RESET;
12174 case pci_channel_io_perm_failure:
12175 /* Permanent failure, prepare for device down */
75baf696 12176 lpfc_sli_prep_dev_for_perm_failure(phba);
da0436e9 12177 return PCI_ERS_RESULT_DISCONNECT;
0d878419
JS
12178 default:
12179 /* Unknown state, prepare and request slot reset */
12180 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12181 "0472 Unknown PCI error state: x%x\n", state);
12182 lpfc_sli_prep_dev_for_reset(phba);
12183 return PCI_ERS_RESULT_NEED_RESET;
da0436e9 12184 }
da0436e9
JS
12185}
12186
12187/**
12188 * lpfc_io_slot_reset_s3 - Method for restarting PCI SLI-3 device from scratch.
12189 * @pdev: pointer to PCI device.
12190 *
12191 * This routine is called from the PCI subsystem for error handling to
12192 * device with SLI-3 interface spec. This is called after PCI bus has been
12193 * reset to restart the PCI card from scratch, as if from a cold-boot.
12194 * During the PCI subsystem error recovery, after driver returns
12195 * PCI_ERS_RESULT_NEED_RESET, the PCI subsystem will perform proper error
12196 * recovery and then call this routine before calling the .resume method
12197 * to recover the device. This function will initialize the HBA device,
12198 * enable the interrupt, but it will just put the HBA to offline state
12199 * without passing any I/O traffic.
12200 *
12201 * Return codes
12202 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
12203 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
12204 */
12205static pci_ers_result_t
12206lpfc_io_slot_reset_s3(struct pci_dev *pdev)
12207{
12208 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12209 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12210 struct lpfc_sli *psli = &phba->sli;
12211 uint32_t intr_mode;
12212
12213 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
12214 if (pci_enable_device_mem(pdev)) {
12215 printk(KERN_ERR "lpfc: Cannot re-enable "
12216 "PCI device after reset.\n");
12217 return PCI_ERS_RESULT_DISCONNECT;
12218 }
12219
12220 pci_restore_state(pdev);
1dfb5a47
JS
12221
12222 /*
12223 * As the new kernel behavior of pci_restore_state() API call clears
12224 * device saved_state flag, need to save the restored state again.
12225 */
12226 pci_save_state(pdev);
12227
da0436e9
JS
12228 if (pdev->is_busmaster)
12229 pci_set_master(pdev);
12230
12231 spin_lock_irq(&phba->hbalock);
12232 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
12233 spin_unlock_irq(&phba->hbalock);
12234
12235 /* Configure and enable interrupt */
12236 intr_mode = lpfc_sli_enable_intr(phba, phba->intr_mode);
12237 if (intr_mode == LPFC_INTR_ERROR) {
12238 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12239 "0427 Cannot re-enable interrupt after "
12240 "slot reset.\n");
12241 return PCI_ERS_RESULT_DISCONNECT;
12242 } else
12243 phba->intr_mode = intr_mode;
12244
75baf696 12245 /* Take device offline, it will perform cleanup */
618a5230 12246 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
da0436e9
JS
12247 lpfc_offline(phba);
12248 lpfc_sli_brdrestart(phba);
12249
12250 /* Log the current active interrupt mode */
12251 lpfc_log_intr_mode(phba, phba->intr_mode);
12252
12253 return PCI_ERS_RESULT_RECOVERED;
12254}
12255
12256/**
12257 * lpfc_io_resume_s3 - Method for resuming PCI I/O operation on SLI-3 device.
12258 * @pdev: pointer to PCI device
12259 *
12260 * This routine is called from the PCI subsystem for error handling to device
12261 * with SLI-3 interface spec. It is called when kernel error recovery tells
12262 * the lpfc driver that it is ok to resume normal PCI operation after PCI bus
12263 * error recovery. After this call, traffic can start to flow from this device
12264 * again.
12265 */
12266static void
12267lpfc_io_resume_s3(struct pci_dev *pdev)
12268{
12269 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12270 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
3772a991 12271
e2af0d2e 12272 /* Bring device online, it will be no-op for non-fatal error resume */
da0436e9
JS
12273 lpfc_online(phba);
12274}
3772a991 12275
da0436e9
JS
12276/**
12277 * lpfc_sli4_get_els_iocb_cnt - Calculate the # of ELS IOCBs to reserve
12278 * @phba: pointer to lpfc hba data structure.
12279 *
12280 * returns the number of ELS/CT IOCBs to reserve
12281 **/
12282int
12283lpfc_sli4_get_els_iocb_cnt(struct lpfc_hba *phba)
12284{
12285 int max_xri = phba->sli4_hba.max_cfg_param.max_xri;
12286
f1126688
JS
12287 if (phba->sli_rev == LPFC_SLI_REV4) {
12288 if (max_xri <= 100)
6a9c52cf 12289 return 10;
f1126688 12290 else if (max_xri <= 256)
6a9c52cf 12291 return 25;
f1126688 12292 else if (max_xri <= 512)
6a9c52cf 12293 return 50;
f1126688 12294 else if (max_xri <= 1024)
6a9c52cf 12295 return 100;
8a9d2e80 12296 else if (max_xri <= 1536)
6a9c52cf 12297 return 150;
8a9d2e80
JS
12298 else if (max_xri <= 2048)
12299 return 200;
12300 else
12301 return 250;
f1126688
JS
12302 } else
12303 return 0;
3772a991
JS
12304}
12305
895427bd
JS
12306/**
12307 * lpfc_sli4_get_iocb_cnt - Calculate the # of total IOCBs to reserve
12308 * @phba: pointer to lpfc hba data structure.
12309 *
f358dd0c 12310 * returns the number of ELS/CT + NVMET IOCBs to reserve
895427bd
JS
12311 **/
12312int
12313lpfc_sli4_get_iocb_cnt(struct lpfc_hba *phba)
12314{
12315 int max_xri = lpfc_sli4_get_els_iocb_cnt(phba);
12316
f358dd0c
JS
12317 if (phba->nvmet_support)
12318 max_xri += LPFC_NVMET_BUF_POST;
895427bd
JS
12319 return max_xri;
12320}
12321
12322
0a5ce731 12323static int
1feb8204
JS
12324lpfc_log_write_firmware_error(struct lpfc_hba *phba, uint32_t offset,
12325 uint32_t magic_number, uint32_t ftype, uint32_t fid, uint32_t fsize,
12326 const struct firmware *fw)
12327{
0a5ce731
JS
12328 int rc;
12329
12330 /* Three cases: (1) FW was not supported on the detected adapter.
12331 * (2) FW update has been locked out administratively.
12332 * (3) Some other error during FW update.
12333 * In each case, an unmaskable message is written to the console
12334 * for admin diagnosis.
12335 */
12336 if (offset == ADD_STATUS_FW_NOT_SUPPORTED ||
a72d56b2
JS
12337 (phba->pcidev->device == PCI_DEVICE_ID_LANCER_G6_FC &&
12338 magic_number != MAGIC_NUMER_G6) ||
12339 (phba->pcidev->device == PCI_DEVICE_ID_LANCER_G7_FC &&
0a5ce731 12340 magic_number != MAGIC_NUMER_G7)) {
1feb8204 12341 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
0a5ce731
JS
12342 "3030 This firmware version is not supported on"
12343 " this HBA model. Device:%x Magic:%x Type:%x "
12344 "ID:%x Size %d %zd\n",
12345 phba->pcidev->device, magic_number, ftype, fid,
12346 fsize, fw->size);
12347 rc = -EINVAL;
12348 } else if (offset == ADD_STATUS_FW_DOWNLOAD_HW_DISABLED) {
12349 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12350 "3021 Firmware downloads have been prohibited "
12351 "by a system configuration setting on "
12352 "Device:%x Magic:%x Type:%x ID:%x Size %d "
12353 "%zd\n",
12354 phba->pcidev->device, magic_number, ftype, fid,
12355 fsize, fw->size);
12356 rc = -EACCES;
12357 } else {
1feb8204 12358 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
0a5ce731
JS
12359 "3022 FW Download failed. Add Status x%x "
12360 "Device:%x Magic:%x Type:%x ID:%x Size %d "
12361 "%zd\n",
12362 offset, phba->pcidev->device, magic_number,
12363 ftype, fid, fsize, fw->size);
12364 rc = -EIO;
12365 }
12366 return rc;
1feb8204
JS
12367}
12368
52d52440
JS
12369/**
12370 * lpfc_write_firmware - attempt to write a firmware image to the port
52d52440 12371 * @fw: pointer to firmware image returned from request_firmware.
0a5ce731
JS
12372 * @context: pointer to firmware image returned from request_firmware.
12373 * @ret: return value this routine provides to the caller.
52d52440 12374 *
52d52440 12375 **/
ce396282
JS
12376static void
12377lpfc_write_firmware(const struct firmware *fw, void *context)
52d52440 12378{
ce396282 12379 struct lpfc_hba *phba = (struct lpfc_hba *)context;
6b5151fd 12380 char fwrev[FW_REV_STR_SIZE];
ce396282 12381 struct lpfc_grp_hdr *image;
52d52440
JS
12382 struct list_head dma_buffer_list;
12383 int i, rc = 0;
12384 struct lpfc_dmabuf *dmabuf, *next;
12385 uint32_t offset = 0, temp_offset = 0;
6b6ef5db 12386 uint32_t magic_number, ftype, fid, fsize;
52d52440 12387
c71ab861 12388 /* It can be null in no-wait mode, sanity check */
ce396282
JS
12389 if (!fw) {
12390 rc = -ENXIO;
12391 goto out;
12392 }
12393 image = (struct lpfc_grp_hdr *)fw->data;
12394
6b6ef5db
JS
12395 magic_number = be32_to_cpu(image->magic_number);
12396 ftype = bf_get_be32(lpfc_grp_hdr_file_type, image);
1feb8204 12397 fid = bf_get_be32(lpfc_grp_hdr_id, image);
6b6ef5db
JS
12398 fsize = be32_to_cpu(image->size);
12399
52d52440 12400 INIT_LIST_HEAD(&dma_buffer_list);
52d52440 12401 lpfc_decode_firmware_rev(phba, fwrev, 1);
88a2cfbb 12402 if (strncmp(fwrev, image->revision, strnlen(image->revision, 16))) {
52d52440 12403 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
ce396282 12404 "3023 Updating Firmware, Current Version:%s "
52d52440 12405 "New Version:%s\n",
88a2cfbb 12406 fwrev, image->revision);
52d52440
JS
12407 for (i = 0; i < LPFC_MBX_WR_CONFIG_MAX_BDE; i++) {
12408 dmabuf = kzalloc(sizeof(struct lpfc_dmabuf),
12409 GFP_KERNEL);
12410 if (!dmabuf) {
12411 rc = -ENOMEM;
ce396282 12412 goto release_out;
52d52440
JS
12413 }
12414 dmabuf->virt = dma_alloc_coherent(&phba->pcidev->dev,
12415 SLI4_PAGE_SIZE,
12416 &dmabuf->phys,
12417 GFP_KERNEL);
12418 if (!dmabuf->virt) {
12419 kfree(dmabuf);
12420 rc = -ENOMEM;
ce396282 12421 goto release_out;
52d52440
JS
12422 }
12423 list_add_tail(&dmabuf->list, &dma_buffer_list);
12424 }
12425 while (offset < fw->size) {
12426 temp_offset = offset;
12427 list_for_each_entry(dmabuf, &dma_buffer_list, list) {
079b5c91 12428 if (temp_offset + SLI4_PAGE_SIZE > fw->size) {
52d52440
JS
12429 memcpy(dmabuf->virt,
12430 fw->data + temp_offset,
079b5c91
JS
12431 fw->size - temp_offset);
12432 temp_offset = fw->size;
52d52440
JS
12433 break;
12434 }
52d52440
JS
12435 memcpy(dmabuf->virt, fw->data + temp_offset,
12436 SLI4_PAGE_SIZE);
88a2cfbb 12437 temp_offset += SLI4_PAGE_SIZE;
52d52440
JS
12438 }
12439 rc = lpfc_wr_object(phba, &dma_buffer_list,
12440 (fw->size - offset), &offset);
1feb8204 12441 if (rc) {
0a5ce731
JS
12442 rc = lpfc_log_write_firmware_error(phba, offset,
12443 magic_number,
12444 ftype,
12445 fid,
12446 fsize,
12447 fw);
ce396282 12448 goto release_out;
1feb8204 12449 }
52d52440
JS
12450 }
12451 rc = offset;
1feb8204
JS
12452 } else
12453 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12454 "3029 Skipped Firmware update, Current "
12455 "Version:%s New Version:%s\n",
12456 fwrev, image->revision);
ce396282
JS
12457
12458release_out:
52d52440
JS
12459 list_for_each_entry_safe(dmabuf, next, &dma_buffer_list, list) {
12460 list_del(&dmabuf->list);
12461 dma_free_coherent(&phba->pcidev->dev, SLI4_PAGE_SIZE,
12462 dmabuf->virt, dmabuf->phys);
12463 kfree(dmabuf);
12464 }
ce396282
JS
12465 release_firmware(fw);
12466out:
0a5ce731
JS
12467 if (rc < 0)
12468 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12469 "3062 Firmware update error, status %d.\n", rc);
12470 else
12471 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12472 "3024 Firmware update success: size %d.\n", rc);
52d52440
JS
12473}
12474
c71ab861
JS
12475/**
12476 * lpfc_sli4_request_firmware_update - Request linux generic firmware upgrade
12477 * @phba: pointer to lpfc hba data structure.
12478 *
12479 * This routine is called to perform Linux generic firmware upgrade on device
12480 * that supports such feature.
12481 **/
12482int
12483lpfc_sli4_request_firmware_update(struct lpfc_hba *phba, uint8_t fw_upgrade)
12484{
12485 uint8_t file_name[ELX_MODEL_NAME_SIZE];
12486 int ret;
12487 const struct firmware *fw;
12488
12489 /* Only supported on SLI4 interface type 2 for now */
27d6ac0a 12490 if (bf_get(lpfc_sli_intf_if_type, &phba->sli4_hba.sli_intf) <
c71ab861
JS
12491 LPFC_SLI_INTF_IF_TYPE_2)
12492 return -EPERM;
12493
12494 snprintf(file_name, ELX_MODEL_NAME_SIZE, "%s.grp", phba->ModelName);
12495
12496 if (fw_upgrade == INT_FW_UPGRADE) {
12497 ret = request_firmware_nowait(THIS_MODULE, FW_ACTION_HOTPLUG,
12498 file_name, &phba->pcidev->dev,
12499 GFP_KERNEL, (void *)phba,
12500 lpfc_write_firmware);
12501 } else if (fw_upgrade == RUN_FW_UPGRADE) {
12502 ret = request_firmware(&fw, file_name, &phba->pcidev->dev);
12503 if (!ret)
12504 lpfc_write_firmware(fw, (void *)phba);
12505 } else {
12506 ret = -EINVAL;
12507 }
12508
12509 return ret;
12510}
12511
3772a991 12512/**
da0436e9 12513 * lpfc_pci_probe_one_s4 - PCI probe func to reg SLI-4 device to PCI subsys
3772a991
JS
12514 * @pdev: pointer to PCI device
12515 * @pid: pointer to PCI device identifier
12516 *
da0436e9
JS
12517 * This routine is called from the kernel's PCI subsystem to device with
12518 * SLI-4 interface spec. When an Emulex HBA with SLI-4 interface spec is
3772a991 12519 * presented on PCI bus, the kernel PCI subsystem looks at PCI device-specific
da0436e9
JS
12520 * information of the device and driver to see if the driver state that it
12521 * can support this kind of device. If the match is successful, the driver
12522 * core invokes this routine. If this routine determines it can claim the HBA,
12523 * it does all the initialization that it needs to do to handle the HBA
12524 * properly.
3772a991
JS
12525 *
12526 * Return code
12527 * 0 - driver can claim the device
12528 * negative value - driver can not claim the device
12529 **/
6f039790 12530static int
da0436e9 12531lpfc_pci_probe_one_s4(struct pci_dev *pdev, const struct pci_device_id *pid)
3772a991
JS
12532{
12533 struct lpfc_hba *phba;
12534 struct lpfc_vport *vport = NULL;
6669f9bb 12535 struct Scsi_Host *shost = NULL;
6c621a22 12536 int error;
3772a991
JS
12537 uint32_t cfg_mode, intr_mode;
12538
12539 /* Allocate memory for HBA structure */
12540 phba = lpfc_hba_alloc(pdev);
12541 if (!phba)
12542 return -ENOMEM;
12543
12544 /* Perform generic PCI device enabling operation */
12545 error = lpfc_enable_pci_dev(phba);
079b5c91 12546 if (error)
3772a991 12547 goto out_free_phba;
3772a991 12548
da0436e9
JS
12549 /* Set up SLI API function jump table for PCI-device group-1 HBAs */
12550 error = lpfc_api_table_setup(phba, LPFC_PCI_DEV_OC);
3772a991
JS
12551 if (error)
12552 goto out_disable_pci_dev;
12553
da0436e9
JS
12554 /* Set up SLI-4 specific device PCI memory space */
12555 error = lpfc_sli4_pci_mem_setup(phba);
3772a991
JS
12556 if (error) {
12557 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 12558 "1410 Failed to set up pci memory space.\n");
3772a991
JS
12559 goto out_disable_pci_dev;
12560 }
12561
da0436e9
JS
12562 /* Set up SLI-4 Specific device driver resources */
12563 error = lpfc_sli4_driver_resource_setup(phba);
3772a991
JS
12564 if (error) {
12565 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9
JS
12566 "1412 Failed to set up driver resource.\n");
12567 goto out_unset_pci_mem_s4;
3772a991
JS
12568 }
12569
19ca7609 12570 INIT_LIST_HEAD(&phba->active_rrq_list);
7d791df7 12571 INIT_LIST_HEAD(&phba->fcf.fcf_pri_list);
19ca7609 12572
3772a991
JS
12573 /* Set up common device driver resources */
12574 error = lpfc_setup_driver_resource_phase2(phba);
12575 if (error) {
12576 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 12577 "1414 Failed to set up driver resource.\n");
6c621a22 12578 goto out_unset_driver_resource_s4;
3772a991
JS
12579 }
12580
079b5c91
JS
12581 /* Get the default values for Model Name and Description */
12582 lpfc_get_hba_model_desc(phba, phba->ModelName, phba->ModelDesc);
12583
3772a991 12584 /* Now, trying to enable interrupt and bring up the device */
5b75da2f 12585 cfg_mode = phba->cfg_use_msi;
5b75da2f 12586
7b15db32 12587 /* Put device to a known state before enabling interrupt */
cdb42bec 12588 phba->pport = NULL;
7b15db32 12589 lpfc_stop_port(phba);
895427bd 12590
7b15db32
JS
12591 /* Configure and enable interrupt */
12592 intr_mode = lpfc_sli4_enable_intr(phba, cfg_mode);
12593 if (intr_mode == LPFC_INTR_ERROR) {
12594 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12595 "0426 Failed to enable interrupt.\n");
12596 error = -ENODEV;
cdb42bec 12597 goto out_unset_driver_resource;
7b15db32
JS
12598 }
12599 /* Default to single EQ for non-MSI-X */
895427bd 12600 if (phba->intr_type != MSIX) {
6a828b0f 12601 phba->cfg_irq_chann = 1;
2d7dbc4c 12602 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
2d7dbc4c
JS
12603 if (phba->nvmet_support)
12604 phba->cfg_nvmet_mrq = 1;
12605 }
cdb42bec 12606 }
6a828b0f 12607 lpfc_cpu_affinity_check(phba, phba->cfg_irq_chann);
cdb42bec
JS
12608
12609 /* Create SCSI host to the physical port */
12610 error = lpfc_create_shost(phba);
12611 if (error) {
12612 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12613 "1415 Failed to create scsi host.\n");
12614 goto out_disable_intr;
12615 }
12616 vport = phba->pport;
12617 shost = lpfc_shost_from_vport(vport); /* save shost for error cleanup */
12618
12619 /* Configure sysfs attributes */
12620 error = lpfc_alloc_sysfs_attr(vport);
12621 if (error) {
12622 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12623 "1416 Failed to allocate sysfs attr\n");
12624 goto out_destroy_shost;
895427bd
JS
12625 }
12626
7b15db32
JS
12627 /* Set up SLI-4 HBA */
12628 if (lpfc_sli4_hba_setup(phba)) {
12629 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12630 "1421 Failed to set up hba\n");
12631 error = -ENODEV;
cdb42bec 12632 goto out_free_sysfs_attr;
98c9ea5c 12633 }
858c9f6c 12634
7b15db32
JS
12635 /* Log the current active interrupt mode */
12636 phba->intr_mode = intr_mode;
12637 lpfc_log_intr_mode(phba, intr_mode);
12638
3772a991
JS
12639 /* Perform post initialization setup */
12640 lpfc_post_init_setup(phba);
dea3101e 12641
01649561
JS
12642 /* NVME support in FW earlier in the driver load corrects the
12643 * FC4 type making a check for nvme_support unnecessary.
12644 */
0794d601
JS
12645 if (phba->nvmet_support == 0) {
12646 if (phba->cfg_enable_fc4_type & LPFC_ENABLE_NVME) {
12647 /* Create NVME binding with nvme_fc_transport. This
12648 * ensures the vport is initialized. If the localport
12649 * create fails, it should not unload the driver to
12650 * support field issues.
12651 */
12652 error = lpfc_nvme_create_localport(vport);
12653 if (error) {
12654 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12655 "6004 NVME registration "
12656 "failed, error x%x\n",
12657 error);
12658 }
01649561
JS
12659 }
12660 }
895427bd 12661
c71ab861
JS
12662 /* check for firmware upgrade or downgrade */
12663 if (phba->cfg_request_firmware_upgrade)
db6f1c2f 12664 lpfc_sli4_request_firmware_update(phba, INT_FW_UPGRADE);
52d52440 12665
1c6834a7
JS
12666 /* Check if there are static vports to be created. */
12667 lpfc_create_static_vport(phba);
d2cc9bcd
JS
12668
12669 /* Enable RAS FW log support */
12670 lpfc_sli4_ras_setup(phba);
12671
dea3101e 12672 return 0;
12673
5b75da2f
JS
12674out_free_sysfs_attr:
12675 lpfc_free_sysfs_attr(vport);
3772a991
JS
12676out_destroy_shost:
12677 lpfc_destroy_shost(phba);
cdb42bec
JS
12678out_disable_intr:
12679 lpfc_sli4_disable_intr(phba);
3772a991
JS
12680out_unset_driver_resource:
12681 lpfc_unset_driver_resource_phase2(phba);
da0436e9
JS
12682out_unset_driver_resource_s4:
12683 lpfc_sli4_driver_resource_unset(phba);
12684out_unset_pci_mem_s4:
12685 lpfc_sli4_pci_mem_unset(phba);
3772a991
JS
12686out_disable_pci_dev:
12687 lpfc_disable_pci_dev(phba);
6669f9bb
JS
12688 if (shost)
12689 scsi_host_put(shost);
2e0fef85 12690out_free_phba:
3772a991 12691 lpfc_hba_free(phba);
dea3101e 12692 return error;
12693}
12694
e59058c4 12695/**
da0436e9 12696 * lpfc_pci_remove_one_s4 - PCI func to unreg SLI-4 device from PCI subsystem
e59058c4
JS
12697 * @pdev: pointer to PCI device
12698 *
da0436e9
JS
12699 * This routine is called from the kernel's PCI subsystem to device with
12700 * SLI-4 interface spec. When an Emulex HBA with SLI-4 interface spec is
3772a991
JS
12701 * removed from PCI bus, it performs all the necessary cleanup for the HBA
12702 * device to be removed from the PCI subsystem properly.
e59058c4 12703 **/
6f039790 12704static void
da0436e9 12705lpfc_pci_remove_one_s4(struct pci_dev *pdev)
dea3101e 12706{
da0436e9 12707 struct Scsi_Host *shost = pci_get_drvdata(pdev);
2e0fef85 12708 struct lpfc_vport *vport = (struct lpfc_vport *) shost->hostdata;
eada272d 12709 struct lpfc_vport **vports;
da0436e9 12710 struct lpfc_hba *phba = vport->phba;
eada272d 12711 int i;
8a4df120 12712
da0436e9 12713 /* Mark the device unloading flag */
549e55cd 12714 spin_lock_irq(&phba->hbalock);
51ef4c26 12715 vport->load_flag |= FC_UNLOADING;
549e55cd 12716 spin_unlock_irq(&phba->hbalock);
2e0fef85 12717
da0436e9 12718 /* Free the HBA sysfs attributes */
858c9f6c
JS
12719 lpfc_free_sysfs_attr(vport);
12720
eada272d
JS
12721 /* Release all the vports against this physical port */
12722 vports = lpfc_create_vport_work_array(phba);
12723 if (vports != NULL)
587a37f6
JS
12724 for (i = 0; i <= phba->max_vports && vports[i] != NULL; i++) {
12725 if (vports[i]->port_type == LPFC_PHYSICAL_PORT)
12726 continue;
eada272d 12727 fc_vport_terminate(vports[i]->fc_vport);
587a37f6 12728 }
eada272d
JS
12729 lpfc_destroy_vport_work_array(phba, vports);
12730
12731 /* Remove FC host and then SCSI host with the physical port */
858c9f6c
JS
12732 fc_remove_host(shost);
12733 scsi_remove_host(shost);
da0436e9 12734
d613b6a7
JS
12735 /* Perform ndlp cleanup on the physical port. The nvme and nvmet
12736 * localports are destroyed after to cleanup all transport memory.
895427bd 12737 */
87af33fe 12738 lpfc_cleanup(vport);
d613b6a7
JS
12739 lpfc_nvmet_destroy_targetport(phba);
12740 lpfc_nvme_destroy_localport(vport);
87af33fe 12741
c490850a
JS
12742 /* De-allocate multi-XRI pools */
12743 if (phba->cfg_xri_rebalancing)
12744 lpfc_destroy_multixri_pools(phba);
12745
281d6190
JS
12746 /*
12747 * Bring down the SLI Layer. This step disables all interrupts,
12748 * clears the rings, discards all mailbox commands, and resets
12749 * the HBA FCoE function.
12750 */
12751 lpfc_debugfs_terminate(vport);
a257bf90 12752
1901762f 12753 lpfc_stop_hba_timers(phba);
523128e5 12754 spin_lock_irq(&phba->port_list_lock);
858c9f6c 12755 list_del_init(&vport->listentry);
523128e5 12756 spin_unlock_irq(&phba->port_list_lock);
858c9f6c 12757
3677a3a7 12758 /* Perform scsi free before driver resource_unset since scsi
da0436e9 12759 * buffers are released to their corresponding pools here.
2e0fef85 12760 */
5e5b511d 12761 lpfc_io_free(phba);
01649561 12762 lpfc_free_iocb_list(phba);
5e5b511d 12763 lpfc_sli4_hba_unset(phba);
67d12733 12764
0cdb84ec 12765 lpfc_unset_driver_resource_phase2(phba);
da0436e9 12766 lpfc_sli4_driver_resource_unset(phba);
ed957684 12767
da0436e9
JS
12768 /* Unmap adapter Control and Doorbell registers */
12769 lpfc_sli4_pci_mem_unset(phba);
2e0fef85 12770
da0436e9
JS
12771 /* Release PCI resources and disable device's PCI function */
12772 scsi_host_put(shost);
12773 lpfc_disable_pci_dev(phba);
2e0fef85 12774
da0436e9 12775 /* Finally, free the driver's device data structure */
3772a991 12776 lpfc_hba_free(phba);
2e0fef85 12777
da0436e9 12778 return;
dea3101e 12779}
12780
3a55b532 12781/**
da0436e9 12782 * lpfc_pci_suspend_one_s4 - PCI func to suspend SLI-4 device for power mgmnt
3a55b532
JS
12783 * @pdev: pointer to PCI device
12784 * @msg: power management message
12785 *
da0436e9
JS
12786 * This routine is called from the kernel's PCI subsystem to support system
12787 * Power Management (PM) to device with SLI-4 interface spec. When PM invokes
12788 * this method, it quiesces the device by stopping the driver's worker
12789 * thread for the device, turning off device's interrupt and DMA, and bring
12790 * the device offline. Note that as the driver implements the minimum PM
12791 * requirements to a power-aware driver's PM support for suspend/resume -- all
12792 * the possible PM messages (SUSPEND, HIBERNATE, FREEZE) to the suspend()
12793 * method call will be treated as SUSPEND and the driver will fully
12794 * reinitialize its device during resume() method call, the driver will set
12795 * device to PCI_D3hot state in PCI config space instead of setting it
3772a991 12796 * according to the @msg provided by the PM.
3a55b532
JS
12797 *
12798 * Return code
3772a991
JS
12799 * 0 - driver suspended the device
12800 * Error otherwise
3a55b532
JS
12801 **/
12802static int
da0436e9 12803lpfc_pci_suspend_one_s4(struct pci_dev *pdev, pm_message_t msg)
3a55b532
JS
12804{
12805 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12806 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12807
12808 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
75baf696 12809 "2843 PCI device Power Management suspend.\n");
3a55b532
JS
12810
12811 /* Bring down the device */
618a5230 12812 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
3a55b532
JS
12813 lpfc_offline(phba);
12814 kthread_stop(phba->worker_thread);
12815
12816 /* Disable interrupt from device */
da0436e9 12817 lpfc_sli4_disable_intr(phba);
5350d872 12818 lpfc_sli4_queue_destroy(phba);
3a55b532
JS
12819
12820 /* Save device state to PCI config space */
12821 pci_save_state(pdev);
12822 pci_set_power_state(pdev, PCI_D3hot);
12823
12824 return 0;
12825}
12826
12827/**
da0436e9 12828 * lpfc_pci_resume_one_s4 - PCI func to resume SLI-4 device for power mgmnt
3a55b532
JS
12829 * @pdev: pointer to PCI device
12830 *
da0436e9
JS
12831 * This routine is called from the kernel's PCI subsystem to support system
12832 * Power Management (PM) to device with SLI-4 interface spac. When PM invokes
12833 * this method, it restores the device's PCI config space state and fully
12834 * reinitializes the device and brings it online. Note that as the driver
12835 * implements the minimum PM requirements to a power-aware driver's PM for
12836 * suspend/resume -- all the possible PM messages (SUSPEND, HIBERNATE, FREEZE)
12837 * to the suspend() method call will be treated as SUSPEND and the driver
12838 * will fully reinitialize its device during resume() method call, the device
12839 * will be set to PCI_D0 directly in PCI config space before restoring the
12840 * state.
3a55b532
JS
12841 *
12842 * Return code
3772a991
JS
12843 * 0 - driver suspended the device
12844 * Error otherwise
3a55b532
JS
12845 **/
12846static int
da0436e9 12847lpfc_pci_resume_one_s4(struct pci_dev *pdev)
3a55b532
JS
12848{
12849 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12850 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
5b75da2f 12851 uint32_t intr_mode;
3a55b532
JS
12852 int error;
12853
12854 lpfc_printf_log(phba, KERN_INFO, LOG_INIT,
da0436e9 12855 "0292 PCI device Power Management resume.\n");
3a55b532
JS
12856
12857 /* Restore device state from PCI config space */
12858 pci_set_power_state(pdev, PCI_D0);
12859 pci_restore_state(pdev);
1dfb5a47
JS
12860
12861 /*
12862 * As the new kernel behavior of pci_restore_state() API call clears
12863 * device saved_state flag, need to save the restored state again.
12864 */
12865 pci_save_state(pdev);
12866
3a55b532
JS
12867 if (pdev->is_busmaster)
12868 pci_set_master(pdev);
12869
da0436e9 12870 /* Startup the kernel thread for this host adapter. */
3a55b532
JS
12871 phba->worker_thread = kthread_run(lpfc_do_work, phba,
12872 "lpfc_worker_%d", phba->brd_no);
12873 if (IS_ERR(phba->worker_thread)) {
12874 error = PTR_ERR(phba->worker_thread);
12875 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 12876 "0293 PM resume failed to start worker "
3a55b532
JS
12877 "thread: error=x%x.\n", error);
12878 return error;
12879 }
12880
5b75da2f 12881 /* Configure and enable interrupt */
da0436e9 12882 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
5b75da2f 12883 if (intr_mode == LPFC_INTR_ERROR) {
3a55b532 12884 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
da0436e9 12885 "0294 PM resume Failed to enable interrupt\n");
5b75da2f
JS
12886 return -EIO;
12887 } else
12888 phba->intr_mode = intr_mode;
3a55b532
JS
12889
12890 /* Restart HBA and bring it online */
12891 lpfc_sli_brdrestart(phba);
12892 lpfc_online(phba);
12893
5b75da2f
JS
12894 /* Log the current active interrupt mode */
12895 lpfc_log_intr_mode(phba, phba->intr_mode);
12896
3a55b532
JS
12897 return 0;
12898}
12899
75baf696
JS
12900/**
12901 * lpfc_sli4_prep_dev_for_recover - Prepare SLI4 device for pci slot recover
12902 * @phba: pointer to lpfc hba data structure.
12903 *
12904 * This routine is called to prepare the SLI4 device for PCI slot recover. It
12905 * aborts all the outstanding SCSI I/Os to the pci device.
12906 **/
12907static void
12908lpfc_sli4_prep_dev_for_recover(struct lpfc_hba *phba)
12909{
75baf696
JS
12910 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12911 "2828 PCI channel I/O abort preparing for recovery\n");
12912 /*
12913 * There may be errored I/Os through HBA, abort all I/Os on txcmplq
12914 * and let the SCSI mid-layer to retry them to recover.
12915 */
db55fba8 12916 lpfc_sli_abort_fcp_rings(phba);
75baf696
JS
12917}
12918
12919/**
12920 * lpfc_sli4_prep_dev_for_reset - Prepare SLI4 device for pci slot reset
12921 * @phba: pointer to lpfc hba data structure.
12922 *
12923 * This routine is called to prepare the SLI4 device for PCI slot reset. It
12924 * disables the device interrupt and pci device, and aborts the internal FCP
12925 * pending I/Os.
12926 **/
12927static void
12928lpfc_sli4_prep_dev_for_reset(struct lpfc_hba *phba)
12929{
12930 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12931 "2826 PCI channel disable preparing for reset\n");
12932
12933 /* Block any management I/Os to the device */
618a5230 12934 lpfc_block_mgmt_io(phba, LPFC_MBX_NO_WAIT);
75baf696
JS
12935
12936 /* Block all SCSI devices' I/Os on the host */
12937 lpfc_scsi_dev_block(phba);
12938
c00f62e6
JS
12939 /* Flush all driver's outstanding I/Os as we are to reset */
12940 lpfc_sli_flush_io_rings(phba);
c3725bdc 12941
75baf696
JS
12942 /* stop all timers */
12943 lpfc_stop_hba_timers(phba);
12944
12945 /* Disable interrupt and pci device */
12946 lpfc_sli4_disable_intr(phba);
5350d872 12947 lpfc_sli4_queue_destroy(phba);
75baf696 12948 pci_disable_device(phba->pcidev);
75baf696
JS
12949}
12950
12951/**
12952 * lpfc_sli4_prep_dev_for_perm_failure - Prepare SLI4 dev for pci slot disable
12953 * @phba: pointer to lpfc hba data structure.
12954 *
12955 * This routine is called to prepare the SLI4 device for PCI slot permanently
12956 * disabling. It blocks the SCSI transport layer traffic and flushes the FCP
12957 * pending I/Os.
12958 **/
12959static void
12960lpfc_sli4_prep_dev_for_perm_failure(struct lpfc_hba *phba)
12961{
12962 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
12963 "2827 PCI channel permanent disable for failure\n");
12964
12965 /* Block all SCSI devices' I/Os on the host */
12966 lpfc_scsi_dev_block(phba);
12967
12968 /* stop all timers */
12969 lpfc_stop_hba_timers(phba);
12970
c00f62e6
JS
12971 /* Clean up all driver's outstanding I/Os */
12972 lpfc_sli_flush_io_rings(phba);
75baf696
JS
12973}
12974
8d63f375 12975/**
da0436e9 12976 * lpfc_io_error_detected_s4 - Method for handling PCI I/O error to SLI-4 device
e59058c4
JS
12977 * @pdev: pointer to PCI device.
12978 * @state: the current PCI connection state.
8d63f375 12979 *
da0436e9
JS
12980 * This routine is called from the PCI subsystem for error handling to device
12981 * with SLI-4 interface spec. This function is called by the PCI subsystem
12982 * after a PCI bus error affecting this device has been detected. When this
12983 * function is invoked, it will need to stop all the I/Os and interrupt(s)
12984 * to the device. Once that is done, it will return PCI_ERS_RESULT_NEED_RESET
12985 * for the PCI subsystem to perform proper recovery as desired.
e59058c4
JS
12986 *
12987 * Return codes
3772a991
JS
12988 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
12989 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
e59058c4 12990 **/
3772a991 12991static pci_ers_result_t
da0436e9 12992lpfc_io_error_detected_s4(struct pci_dev *pdev, pci_channel_state_t state)
8d63f375 12993{
75baf696
JS
12994 struct Scsi_Host *shost = pci_get_drvdata(pdev);
12995 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
12996
12997 switch (state) {
12998 case pci_channel_io_normal:
12999 /* Non-fatal error, prepare for recovery */
13000 lpfc_sli4_prep_dev_for_recover(phba);
13001 return PCI_ERS_RESULT_CAN_RECOVER;
13002 case pci_channel_io_frozen:
13003 /* Fatal error, prepare for slot reset */
13004 lpfc_sli4_prep_dev_for_reset(phba);
13005 return PCI_ERS_RESULT_NEED_RESET;
13006 case pci_channel_io_perm_failure:
13007 /* Permanent failure, prepare for device down */
13008 lpfc_sli4_prep_dev_for_perm_failure(phba);
13009 return PCI_ERS_RESULT_DISCONNECT;
13010 default:
13011 /* Unknown state, prepare and request slot reset */
13012 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13013 "2825 Unknown PCI error state: x%x\n", state);
13014 lpfc_sli4_prep_dev_for_reset(phba);
13015 return PCI_ERS_RESULT_NEED_RESET;
13016 }
8d63f375
LV
13017}
13018
13019/**
da0436e9 13020 * lpfc_io_slot_reset_s4 - Method for restart PCI SLI-4 device from scratch
e59058c4
JS
13021 * @pdev: pointer to PCI device.
13022 *
da0436e9
JS
13023 * This routine is called from the PCI subsystem for error handling to device
13024 * with SLI-4 interface spec. It is called after PCI bus has been reset to
13025 * restart the PCI card from scratch, as if from a cold-boot. During the
13026 * PCI subsystem error recovery, after the driver returns
3772a991 13027 * PCI_ERS_RESULT_NEED_RESET, the PCI subsystem will perform proper error
da0436e9
JS
13028 * recovery and then call this routine before calling the .resume method to
13029 * recover the device. This function will initialize the HBA device, enable
13030 * the interrupt, but it will just put the HBA to offline state without
13031 * passing any I/O traffic.
8d63f375 13032 *
e59058c4 13033 * Return codes
3772a991
JS
13034 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
13035 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
8d63f375 13036 */
3772a991 13037static pci_ers_result_t
da0436e9 13038lpfc_io_slot_reset_s4(struct pci_dev *pdev)
8d63f375 13039{
75baf696
JS
13040 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13041 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13042 struct lpfc_sli *psli = &phba->sli;
13043 uint32_t intr_mode;
13044
13045 dev_printk(KERN_INFO, &pdev->dev, "recovering from a slot reset.\n");
13046 if (pci_enable_device_mem(pdev)) {
13047 printk(KERN_ERR "lpfc: Cannot re-enable "
13048 "PCI device after reset.\n");
13049 return PCI_ERS_RESULT_DISCONNECT;
13050 }
13051
13052 pci_restore_state(pdev);
0a96e975
JS
13053
13054 /*
13055 * As the new kernel behavior of pci_restore_state() API call clears
13056 * device saved_state flag, need to save the restored state again.
13057 */
13058 pci_save_state(pdev);
13059
75baf696
JS
13060 if (pdev->is_busmaster)
13061 pci_set_master(pdev);
13062
13063 spin_lock_irq(&phba->hbalock);
13064 psli->sli_flag &= ~LPFC_SLI_ACTIVE;
13065 spin_unlock_irq(&phba->hbalock);
13066
13067 /* Configure and enable interrupt */
13068 intr_mode = lpfc_sli4_enable_intr(phba, phba->intr_mode);
13069 if (intr_mode == LPFC_INTR_ERROR) {
13070 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13071 "2824 Cannot re-enable interrupt after "
13072 "slot reset.\n");
13073 return PCI_ERS_RESULT_DISCONNECT;
13074 } else
13075 phba->intr_mode = intr_mode;
13076
13077 /* Log the current active interrupt mode */
13078 lpfc_log_intr_mode(phba, phba->intr_mode);
13079
8d63f375
LV
13080 return PCI_ERS_RESULT_RECOVERED;
13081}
13082
13083/**
da0436e9 13084 * lpfc_io_resume_s4 - Method for resuming PCI I/O operation to SLI-4 device
e59058c4 13085 * @pdev: pointer to PCI device
8d63f375 13086 *
3772a991 13087 * This routine is called from the PCI subsystem for error handling to device
da0436e9 13088 * with SLI-4 interface spec. It is called when kernel error recovery tells
3772a991
JS
13089 * the lpfc driver that it is ok to resume normal PCI operation after PCI bus
13090 * error recovery. After this call, traffic can start to flow from this device
13091 * again.
da0436e9 13092 **/
3772a991 13093static void
da0436e9 13094lpfc_io_resume_s4(struct pci_dev *pdev)
8d63f375 13095{
75baf696
JS
13096 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13097 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13098
13099 /*
13100 * In case of slot reset, as function reset is performed through
13101 * mailbox command which needs DMA to be enabled, this operation
13102 * has to be moved to the io resume phase. Taking device offline
13103 * will perform the necessary cleanup.
13104 */
13105 if (!(phba->sli.sli_flag & LPFC_SLI_ACTIVE)) {
13106 /* Perform device reset */
618a5230 13107 lpfc_offline_prep(phba, LPFC_MBX_WAIT);
75baf696
JS
13108 lpfc_offline(phba);
13109 lpfc_sli_brdrestart(phba);
13110 /* Bring the device back online */
13111 lpfc_online(phba);
13112 }
8d63f375
LV
13113}
13114
3772a991
JS
13115/**
13116 * lpfc_pci_probe_one - lpfc PCI probe func to reg dev to PCI subsystem
13117 * @pdev: pointer to PCI device
13118 * @pid: pointer to PCI device identifier
13119 *
13120 * This routine is to be registered to the kernel's PCI subsystem. When an
13121 * Emulex HBA device is presented on PCI bus, the kernel PCI subsystem looks
13122 * at PCI device-specific information of the device and driver to see if the
13123 * driver state that it can support this kind of device. If the match is
13124 * successful, the driver core invokes this routine. This routine dispatches
13125 * the action to the proper SLI-3 or SLI-4 device probing routine, which will
13126 * do all the initialization that it needs to do to handle the HBA device
13127 * properly.
13128 *
13129 * Return code
13130 * 0 - driver can claim the device
13131 * negative value - driver can not claim the device
13132 **/
6f039790 13133static int
3772a991
JS
13134lpfc_pci_probe_one(struct pci_dev *pdev, const struct pci_device_id *pid)
13135{
13136 int rc;
8fa38513 13137 struct lpfc_sli_intf intf;
3772a991 13138
28baac74 13139 if (pci_read_config_dword(pdev, LPFC_SLI_INTF, &intf.word0))
3772a991
JS
13140 return -ENODEV;
13141
8fa38513 13142 if ((bf_get(lpfc_sli_intf_valid, &intf) == LPFC_SLI_INTF_VALID) &&
28baac74 13143 (bf_get(lpfc_sli_intf_slirev, &intf) == LPFC_SLI_INTF_REV_SLI4))
da0436e9 13144 rc = lpfc_pci_probe_one_s4(pdev, pid);
8fa38513 13145 else
3772a991 13146 rc = lpfc_pci_probe_one_s3(pdev, pid);
8fa38513 13147
3772a991
JS
13148 return rc;
13149}
13150
13151/**
13152 * lpfc_pci_remove_one - lpfc PCI func to unreg dev from PCI subsystem
13153 * @pdev: pointer to PCI device
13154 *
13155 * This routine is to be registered to the kernel's PCI subsystem. When an
13156 * Emulex HBA is removed from PCI bus, the driver core invokes this routine.
13157 * This routine dispatches the action to the proper SLI-3 or SLI-4 device
13158 * remove routine, which will perform all the necessary cleanup for the
13159 * device to be removed from the PCI subsystem properly.
13160 **/
6f039790 13161static void
3772a991
JS
13162lpfc_pci_remove_one(struct pci_dev *pdev)
13163{
13164 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13165 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13166
13167 switch (phba->pci_dev_grp) {
13168 case LPFC_PCI_DEV_LP:
13169 lpfc_pci_remove_one_s3(pdev);
13170 break;
da0436e9
JS
13171 case LPFC_PCI_DEV_OC:
13172 lpfc_pci_remove_one_s4(pdev);
13173 break;
3772a991
JS
13174 default:
13175 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13176 "1424 Invalid PCI device group: 0x%x\n",
13177 phba->pci_dev_grp);
13178 break;
13179 }
13180 return;
13181}
13182
13183/**
13184 * lpfc_pci_suspend_one - lpfc PCI func to suspend dev for power management
13185 * @pdev: pointer to PCI device
13186 * @msg: power management message
13187 *
13188 * This routine is to be registered to the kernel's PCI subsystem to support
13189 * system Power Management (PM). When PM invokes this method, it dispatches
13190 * the action to the proper SLI-3 or SLI-4 device suspend routine, which will
13191 * suspend the device.
13192 *
13193 * Return code
13194 * 0 - driver suspended the device
13195 * Error otherwise
13196 **/
13197static int
13198lpfc_pci_suspend_one(struct pci_dev *pdev, pm_message_t msg)
13199{
13200 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13201 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13202 int rc = -ENODEV;
13203
13204 switch (phba->pci_dev_grp) {
13205 case LPFC_PCI_DEV_LP:
13206 rc = lpfc_pci_suspend_one_s3(pdev, msg);
13207 break;
da0436e9
JS
13208 case LPFC_PCI_DEV_OC:
13209 rc = lpfc_pci_suspend_one_s4(pdev, msg);
13210 break;
3772a991
JS
13211 default:
13212 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13213 "1425 Invalid PCI device group: 0x%x\n",
13214 phba->pci_dev_grp);
13215 break;
13216 }
13217 return rc;
13218}
13219
13220/**
13221 * lpfc_pci_resume_one - lpfc PCI func to resume dev for power management
13222 * @pdev: pointer to PCI device
13223 *
13224 * This routine is to be registered to the kernel's PCI subsystem to support
13225 * system Power Management (PM). When PM invokes this method, it dispatches
13226 * the action to the proper SLI-3 or SLI-4 device resume routine, which will
13227 * resume the device.
13228 *
13229 * Return code
13230 * 0 - driver suspended the device
13231 * Error otherwise
13232 **/
13233static int
13234lpfc_pci_resume_one(struct pci_dev *pdev)
13235{
13236 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13237 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13238 int rc = -ENODEV;
13239
13240 switch (phba->pci_dev_grp) {
13241 case LPFC_PCI_DEV_LP:
13242 rc = lpfc_pci_resume_one_s3(pdev);
13243 break;
da0436e9
JS
13244 case LPFC_PCI_DEV_OC:
13245 rc = lpfc_pci_resume_one_s4(pdev);
13246 break;
3772a991
JS
13247 default:
13248 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13249 "1426 Invalid PCI device group: 0x%x\n",
13250 phba->pci_dev_grp);
13251 break;
13252 }
13253 return rc;
13254}
13255
13256/**
13257 * lpfc_io_error_detected - lpfc method for handling PCI I/O error
13258 * @pdev: pointer to PCI device.
13259 * @state: the current PCI connection state.
13260 *
13261 * This routine is registered to the PCI subsystem for error handling. This
13262 * function is called by the PCI subsystem after a PCI bus error affecting
13263 * this device has been detected. When this routine is invoked, it dispatches
13264 * the action to the proper SLI-3 or SLI-4 device error detected handling
13265 * routine, which will perform the proper error detected operation.
13266 *
13267 * Return codes
13268 * PCI_ERS_RESULT_NEED_RESET - need to reset before recovery
13269 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
13270 **/
13271static pci_ers_result_t
13272lpfc_io_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
13273{
13274 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13275 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13276 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
13277
13278 switch (phba->pci_dev_grp) {
13279 case LPFC_PCI_DEV_LP:
13280 rc = lpfc_io_error_detected_s3(pdev, state);
13281 break;
da0436e9
JS
13282 case LPFC_PCI_DEV_OC:
13283 rc = lpfc_io_error_detected_s4(pdev, state);
13284 break;
3772a991
JS
13285 default:
13286 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13287 "1427 Invalid PCI device group: 0x%x\n",
13288 phba->pci_dev_grp);
13289 break;
13290 }
13291 return rc;
13292}
13293
13294/**
13295 * lpfc_io_slot_reset - lpfc method for restart PCI dev from scratch
13296 * @pdev: pointer to PCI device.
13297 *
13298 * This routine is registered to the PCI subsystem for error handling. This
13299 * function is called after PCI bus has been reset to restart the PCI card
13300 * from scratch, as if from a cold-boot. When this routine is invoked, it
13301 * dispatches the action to the proper SLI-3 or SLI-4 device reset handling
13302 * routine, which will perform the proper device reset.
13303 *
13304 * Return codes
13305 * PCI_ERS_RESULT_RECOVERED - the device has been recovered
13306 * PCI_ERS_RESULT_DISCONNECT - device could not be recovered
13307 **/
13308static pci_ers_result_t
13309lpfc_io_slot_reset(struct pci_dev *pdev)
13310{
13311 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13312 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13313 pci_ers_result_t rc = PCI_ERS_RESULT_DISCONNECT;
13314
13315 switch (phba->pci_dev_grp) {
13316 case LPFC_PCI_DEV_LP:
13317 rc = lpfc_io_slot_reset_s3(pdev);
13318 break;
da0436e9
JS
13319 case LPFC_PCI_DEV_OC:
13320 rc = lpfc_io_slot_reset_s4(pdev);
13321 break;
3772a991
JS
13322 default:
13323 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13324 "1428 Invalid PCI device group: 0x%x\n",
13325 phba->pci_dev_grp);
13326 break;
13327 }
13328 return rc;
13329}
13330
13331/**
13332 * lpfc_io_resume - lpfc method for resuming PCI I/O operation
13333 * @pdev: pointer to PCI device
13334 *
13335 * This routine is registered to the PCI subsystem for error handling. It
13336 * is called when kernel error recovery tells the lpfc driver that it is
13337 * OK to resume normal PCI operation after PCI bus error recovery. When
13338 * this routine is invoked, it dispatches the action to the proper SLI-3
13339 * or SLI-4 device io_resume routine, which will resume the device operation.
13340 **/
13341static void
13342lpfc_io_resume(struct pci_dev *pdev)
13343{
13344 struct Scsi_Host *shost = pci_get_drvdata(pdev);
13345 struct lpfc_hba *phba = ((struct lpfc_vport *)shost->hostdata)->phba;
13346
13347 switch (phba->pci_dev_grp) {
13348 case LPFC_PCI_DEV_LP:
13349 lpfc_io_resume_s3(pdev);
13350 break;
da0436e9
JS
13351 case LPFC_PCI_DEV_OC:
13352 lpfc_io_resume_s4(pdev);
13353 break;
3772a991
JS
13354 default:
13355 lpfc_printf_log(phba, KERN_ERR, LOG_INIT,
13356 "1429 Invalid PCI device group: 0x%x\n",
13357 phba->pci_dev_grp);
13358 break;
13359 }
13360 return;
13361}
13362
1ba981fd
JS
13363/**
13364 * lpfc_sli4_oas_verify - Verify OAS is supported by this adapter
13365 * @phba: pointer to lpfc hba data structure.
13366 *
13367 * This routine checks to see if OAS is supported for this adapter. If
13368 * supported, the configure Flash Optimized Fabric flag is set. Otherwise,
13369 * the enable oas flag is cleared and the pool created for OAS device data
13370 * is destroyed.
13371 *
13372 **/
c7092975 13373static void
1ba981fd
JS
13374lpfc_sli4_oas_verify(struct lpfc_hba *phba)
13375{
13376
13377 if (!phba->cfg_EnableXLane)
13378 return;
13379
13380 if (phba->sli4_hba.pc_sli4_params.oas_supported) {
13381 phba->cfg_fof = 1;
13382 } else {
f38fa0bb 13383 phba->cfg_fof = 0;
1ba981fd
JS
13384 if (phba->device_data_mem_pool)
13385 mempool_destroy(phba->device_data_mem_pool);
13386 phba->device_data_mem_pool = NULL;
13387 }
13388
13389 return;
13390}
13391
d2cc9bcd
JS
13392/**
13393 * lpfc_sli4_ras_init - Verify RAS-FW log is supported by this adapter
13394 * @phba: pointer to lpfc hba data structure.
13395 *
13396 * This routine checks to see if RAS is supported by the adapter. Check the
13397 * function through which RAS support enablement is to be done.
13398 **/
13399void
13400lpfc_sli4_ras_init(struct lpfc_hba *phba)
13401{
13402 switch (phba->pcidev->device) {
13403 case PCI_DEVICE_ID_LANCER_G6_FC:
13404 case PCI_DEVICE_ID_LANCER_G7_FC:
13405 phba->ras_fwlog.ras_hwsupport = true;
cb34990b
JS
13406 if (phba->cfg_ras_fwlog_func == PCI_FUNC(phba->pcidev->devfn) &&
13407 phba->cfg_ras_fwlog_buffsize)
d2cc9bcd
JS
13408 phba->ras_fwlog.ras_enabled = true;
13409 else
13410 phba->ras_fwlog.ras_enabled = false;
13411 break;
13412 default:
13413 phba->ras_fwlog.ras_hwsupport = false;
13414 }
13415}
13416
1ba981fd 13417
dea3101e 13418MODULE_DEVICE_TABLE(pci, lpfc_id_table);
13419
a55b2d21 13420static const struct pci_error_handlers lpfc_err_handler = {
8d63f375
LV
13421 .error_detected = lpfc_io_error_detected,
13422 .slot_reset = lpfc_io_slot_reset,
13423 .resume = lpfc_io_resume,
13424};
13425
dea3101e 13426static struct pci_driver lpfc_driver = {
13427 .name = LPFC_DRIVER_NAME,
13428 .id_table = lpfc_id_table,
13429 .probe = lpfc_pci_probe_one,
6f039790 13430 .remove = lpfc_pci_remove_one,
85e8a239 13431 .shutdown = lpfc_pci_remove_one,
3a55b532 13432 .suspend = lpfc_pci_suspend_one,
3772a991 13433 .resume = lpfc_pci_resume_one,
2e0fef85 13434 .err_handler = &lpfc_err_handler,
dea3101e 13435};
13436
3ef6d24c 13437static const struct file_operations lpfc_mgmt_fop = {
858feacd 13438 .owner = THIS_MODULE,
3ef6d24c
JS
13439};
13440
13441static struct miscdevice lpfc_mgmt_dev = {
13442 .minor = MISC_DYNAMIC_MINOR,
13443 .name = "lpfcmgmt",
13444 .fops = &lpfc_mgmt_fop,
13445};
13446
e59058c4 13447/**
3621a710 13448 * lpfc_init - lpfc module initialization routine
e59058c4
JS
13449 *
13450 * This routine is to be invoked when the lpfc module is loaded into the
13451 * kernel. The special kernel macro module_init() is used to indicate the
13452 * role of this routine to the kernel as lpfc module entry point.
13453 *
13454 * Return codes
13455 * 0 - successful
13456 * -ENOMEM - FC attach transport failed
13457 * all others - failed
13458 */
dea3101e 13459static int __init
13460lpfc_init(void)
13461{
13462 int error = 0;
13463
13464 printk(LPFC_MODULE_DESC "\n");
c44ce173 13465 printk(LPFC_COPYRIGHT "\n");
dea3101e 13466
3ef6d24c
JS
13467 error = misc_register(&lpfc_mgmt_dev);
13468 if (error)
13469 printk(KERN_ERR "Could not register lpfcmgmt device, "
13470 "misc_register returned with status %d", error);
13471
458c083e
JS
13472 lpfc_transport_functions.vport_create = lpfc_vport_create;
13473 lpfc_transport_functions.vport_delete = lpfc_vport_delete;
dea3101e 13474 lpfc_transport_template =
13475 fc_attach_transport(&lpfc_transport_functions);
7ee5d43e 13476 if (lpfc_transport_template == NULL)
dea3101e 13477 return -ENOMEM;
458c083e
JS
13478 lpfc_vport_transport_template =
13479 fc_attach_transport(&lpfc_vport_transport_functions);
13480 if (lpfc_vport_transport_template == NULL) {
13481 fc_release_transport(lpfc_transport_template);
13482 return -ENOMEM;
7ee5d43e 13483 }
5fd11085 13484 lpfc_nvme_cmd_template();
bd3061ba 13485 lpfc_nvmet_cmd_template();
7bb03bbf
JS
13486
13487 /* Initialize in case vector mapping is needed */
2ea259ee 13488 lpfc_present_cpu = num_present_cpus();
7bb03bbf 13489
dea3101e 13490 error = pci_register_driver(&lpfc_driver);
92d7f7b0 13491 if (error) {
dea3101e 13492 fc_release_transport(lpfc_transport_template);
458c083e 13493 fc_release_transport(lpfc_vport_transport_template);
92d7f7b0 13494 }
dea3101e 13495
13496 return error;
13497}
13498
e59058c4 13499/**
3621a710 13500 * lpfc_exit - lpfc module removal routine
e59058c4
JS
13501 *
13502 * This routine is invoked when the lpfc module is removed from the kernel.
13503 * The special kernel macro module_exit() is used to indicate the role of
13504 * this routine to the kernel as lpfc module exit point.
13505 */
dea3101e 13506static void __exit
13507lpfc_exit(void)
13508{
3ef6d24c 13509 misc_deregister(&lpfc_mgmt_dev);
dea3101e 13510 pci_unregister_driver(&lpfc_driver);
13511 fc_release_transport(lpfc_transport_template);
458c083e 13512 fc_release_transport(lpfc_vport_transport_template);
7973967f 13513 idr_destroy(&lpfc_hba_index);
dea3101e 13514}
13515
13516module_init(lpfc_init);
13517module_exit(lpfc_exit);
13518MODULE_LICENSE("GPL");
13519MODULE_DESCRIPTION(LPFC_MODULE_DESC);
d080abe0 13520MODULE_AUTHOR("Broadcom");
dea3101e 13521MODULE_VERSION("0:" LPFC_DRIVER_VERSION);