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Merge patch series "scsi: documentation: clean up docs and fix kernel-doc"
[linux-block.git] / drivers / scsi / lpfc / lpfc.h
CommitLineData
dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
ea4044e4 4 * Copyright (C) 2017-2024 Broadcom. All Rights Reserved. The term *
4ae2ebde 5 * “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. *
50611577 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
c44ce173 7 * EMULEX and SLI are trademarks of Emulex. *
d080abe0 8 * www.broadcom.com *
c44ce173 9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e 10 * *
11 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC		 12 * modify it under the terms of version 2 of the GNU General *
13 * Public License as published by the Free Software Foundation. *
14 * This program is distributed in the hope that it will be useful. *
15 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
16 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
18 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
19 * TO BE LEGALLY INVALID. See the GNU General Public License for *
20 * more details, a copy of which can be found in the file COPYING *
21 * included with this package. *
dea3101e 22 *******************************************************************/
23
2e0fef85 24#include <scsi/scsi_host.h>
2e9bc346 25#include <linux/hashtable.h>
895427bd 26#include <linux/ktime.h>
f485c18d 27#include <linux/workqueue.h>
88a2cfbb
JS		 28
29#if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS)
30#define CONFIG_SCSI_LPFC_DEBUG_FS
31#endif
32
dea3101e 33struct lpfc_sli2_slim;
34
5402a315 35#define ELX_MODEL_NAME_SIZE 80
f5779b52 36#define ELX_FW_NAME_SIZE 84
5402a315 37
3772a991
JS		 38#define LPFC_PCI_DEV_LP 0x1
39#define LPFC_PCI_DEV_OC 0x2
40
41#define LPFC_SLI_REV2 2
42#define LPFC_SLI_REV3 3
43#define LPFC_SLI_REV4 4
44
97eab634 45#define LPFC_MAX_TARGET 4096 /* max number of targets supported */
e17da18e
JS		 46#define LPFC_MAX_DISC_THREADS 64 /* max outstanding discovery els
47 requests */
48#define LPFC_MAX_NS_RETRY 3 /* Number of retry attempts to contact
49 the NameServer before giving up. */
445cf4f4 50#define LPFC_CMD_PER_LUN 3 /* max outstanding cmds per lun */
81301a9b 51#define LPFC_DEFAULT_SG_SEG_CNT 64 /* sg element count per scsi cmnd */
96f7077f 52
d79c9e9d
JS		 53#define LPFC_DEFAULT_XPSGL_SIZE 256
54#define LPFC_MAX_SG_TABLESIZE 0xffff
96f7077f 55#define LPFC_MIN_SG_SLI4_BUF_SZ 0x800 /* based on LPFC_DEFAULT_SG_SEG_CNT */
5b9e70b2 56#define LPFC_MAX_BG_SLI4_SEG_CNT_DIF 128 /* sg element count for BlockGuard */
96f7077f 57#define LPFC_MAX_SG_SEG_CNT_DIF 512 /* sg element count per scsi cmnd */
81301a9b 58#define LPFC_MAX_SG_SEG_CNT 4096 /* sg element count per scsi cmnd */
81e6a637 59#define LPFC_MIN_SG_SEG_CNT 32 /* sg element count per scsi cmnd */
09294d46
JS		 60#define LPFC_MAX_SGL_SEG_CNT 512 /* SGL element count per scsi cmnd */
61#define LPFC_MAX_BPL_SEG_CNT 4096 /* BPL element count per scsi cmnd */
d73154ba 62#define LPFC_MAX_NVME_SEG_CNT 256 /* max SGL element cnt per NVME cmnd */
09294d46 63
0558056c 64#define LPFC_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */
dea3101e 65#define LPFC_IOCB_LIST_CNT 2250 /* list of IOCBs for fast-path usage. */
445cf4f4 66#define LPFC_Q_RAMP_UP_INTERVAL 120 /* lun q_depth ramp up interval */
495a714c 67#define LPFC_VNAME_LEN 100 /* vport symbolic name length */
977b5a0a 68#define LPFC_TGTQ_RAMPUP_PCENT 5 /* Target queue rampup in percentage */
7dc517df 69#define LPFC_MIN_TGT_QDEPTH 10
977b5a0a 70#define LPFC_MAX_TGT_QDEPTH 0xFFFF
dea3101e 71
92d7f7b0
JS		 72/*
73 * Following time intervals are used of adjusting SCSI device
74 * queue depths when there are driver resource error or Firmware
75 * resource error.
76 */
256ec0d0
JS		 77/* 1 Second */
78#define QUEUE_RAMP_DOWN_INTERVAL (msecs_to_jiffies(1000 * 1))
92d7f7b0
JS		 79
80/* Number of exchanges reserved for discovery to complete */
81#define LPFC_DISC_IOCB_BUFF_COUNT 20
82
858c9f6c 83#define LPFC_HB_MBOX_INTERVAL 5 /* Heart beat interval in seconds. */
311464ec 84#define LPFC_HB_MBOX_TIMEOUT 30 /* Heart beat timeout in seconds. */
858c9f6c 85
9399627f
JS		 86/* Error Attention event polling interval */
87#define LPFC_ERATT_POLL_INTERVAL 5 /* EATT poll interval in seconds */
88
dea3101e 89/* Define macros for 64 bit support */
90#define putPaddrLow(addr) ((uint32_t) (0xffffffff & (u64)(addr)))
91#define putPaddrHigh(addr) ((uint32_t) (0xffffffff & (((u64)(addr))>>32)))
92#define getPaddr(high, low) ((dma_addr_t)( \
93 (( (u64)(high)<<16 ) << 16)|( (u64)(low))))
94/* Provide maximum configuration definitions. */
95#define LPFC_DRVR_TIMEOUT 16 /* driver iocb timeout value in sec */
dea3101e 96#define FC_MAX_ADPTMSG 64
97
98#define MAX_HBAEVT 32
96418b5e 99#define MAX_HBAS_NO_RESET 16
dea3101e 100
9399627f
JS		 101/* Number of MSI-X vectors the driver uses */
102#define LPFC_MSIX_VECTORS 2
103
5e9d9b82 104/* lpfc wait event data ready flag */
2ade92ae 105#define LPFC_DATA_READY 0 /* bit 0 */
5e9d9b82 106
809c7536
JS		 107/* queue dump line buffer size */
108#define LPFC_LBUF_SZ 128
109
618a5230
JS		 110/* mailbox system shutdown options */
111#define LPFC_MBX_NO_WAIT 0
112#define LPFC_MBX_WAIT 1
113
72df8a45
JS		 114#define LPFC_CFG_PARAM_MAGIC_NUM 0xFEAA0005
115#define LPFC_PORT_CFG_NAME "/cfg/port.cfg"
116
117#define lpfc_rangecheck(val, min, max) \
118 ((uint)(val) >= (uint)(min) && (val) <= (max))
119
875fbdfe
JSEC		 120enum lpfc_polling_flags {
121 ENABLE_FCP_RING_POLLING = 0x1,
122 DISABLE_FCP_RING_INT = 0x2
123};
124
895427bd
JS		 125struct perf_prof {
126 uint16_t cmd_cpu[40];
127 uint16_t rsp_cpu[40];
128 uint16_t qh_cpu[40];
129 uint16_t wqidx[40];
130};
131
01649561
JS		 132/*
133 * Provide for FC4 TYPE x28 - NVME. The
134 * bit mask for FCP and NVME is 0x8 identically
135 * because they are 32 bit positions distance.
136 */
a0f2d3ef
JS		 137#define LPFC_FC4_TYPE_BITMASK 0x00000100
138
dea3101e 139/* Provide DMA memory definitions the driver uses per port instance. */
140struct lpfc_dmabuf {
141 struct list_head list;
142 void *virt; /* virtual address ptr */
143 dma_addr_t phys; /* mapped address */
76bb24ef 144 uint32_t buffer_tag; /* used for tagged queue ring */
dea3101e 145};
146
6c621a22
JS		 147struct lpfc_nvmet_ctxbuf {
148 struct list_head list;
7cacae2a 149 struct lpfc_async_xchg_ctx *context;
6c621a22
JS		 150 struct lpfc_iocbq *iocbq;
151 struct lpfc_sglq *sglq;
472e146d 152 struct work_struct defer_work;
6c621a22
JS		 153};
154
dea3101e 155struct lpfc_dma_pool {
156 struct lpfc_dmabuf *elements;
157 uint32_t max_count;
158 uint32_t current_count;
159};
160
ed957684 161struct hbq_dmabuf {
da0436e9 162 struct lpfc_dmabuf hbuf;
ed957684 163 struct lpfc_dmabuf dbuf;
895427bd
JS		 164 uint16_t total_size;
165 uint16_t bytes_recv;
ed957684 166 uint32_t tag;
4d9ab994 167 struct lpfc_cq_event cq_event;
45ed1190 168 unsigned long time_stamp;
895427bd
JS		 169 void *context;
170};
171
172struct rqb_dmabuf {
173 struct lpfc_dmabuf hbuf;
174 struct lpfc_dmabuf dbuf;
175 uint16_t total_size;
176 uint16_t bytes_recv;
a8cf5dfe 177 uint16_t idx;
895427bd
JS		 178 struct lpfc_queue *hrq; /* ptr to associated Header RQ */
179 struct lpfc_queue *drq; /* ptr to associated Data RQ */
ed957684
JS		 180};
181
dea3101e 182/* Priority bit. Set value to exceed low water mark in lpfc_mem. */
183#define MEM_PRI 0x100
184
185
186/****************************************************************************/
187/* Device VPD save area */
188/****************************************************************************/
189typedef struct lpfc_vpd {
190 uint32_t status; /* vpd status value */
191 uint32_t length; /* number of bytes actually returned */
192 struct {
193 uint32_t rsvd1; /* Revision numbers */
194 uint32_t biuRev;
195 uint32_t smRev;
196 uint32_t smFwRev;
197 uint32_t endecRev;
198 uint16_t rBit;
199 uint8_t fcphHigh;
200 uint8_t fcphLow;
201 uint8_t feaLevelHigh;
202 uint8_t feaLevelLow;
203 uint32_t postKernRev;
204 uint32_t opFwRev;
205 uint8_t opFwName[16];
206 uint32_t sli1FwRev;
207 uint8_t sli1FwName[16];
208 uint32_t sli2FwRev;
209 uint8_t sli2FwName[16];
210 } rev;
92d7f7b0
JS		 211 struct {
212#ifdef __BIG_ENDIAN_BITFIELD
0e75461a 213 uint32_t rsvd3 :20; /* Reserved */
da0436e9
JS		 214 uint32_t rsvd2 : 3; /* Reserved */
215 uint32_t cbg : 1; /* Configure BlockGuard */
92d7f7b0
JS		 216 uint32_t cmv : 1; /* Configure Max VPIs */
217 uint32_t ccrp : 1; /* Config Command Ring Polling */
218 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
219 uint32_t chbs : 1; /* Cofigure Host Backing store */
220 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
221 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
222 uint32_t cmx : 1; /* Configure Max XRIs */
223 uint32_t cmr : 1; /* Configure Max RPIs */
224#else /* __LITTLE_ENDIAN */
225 uint32_t cmr : 1; /* Configure Max RPIs */
226 uint32_t cmx : 1; /* Configure Max XRIs */
227 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
228 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
229 uint32_t chbs : 1; /* Cofigure Host Backing store */
230 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
231 uint32_t ccrp : 1; /* Config Command Ring Polling */
232 uint32_t cmv : 1; /* Configure Max VPIs */
da0436e9
JS		 233 uint32_t cbg : 1; /* Configure BlockGuard */
234 uint32_t rsvd2 : 3; /* Reserved */
0e75461a 235 uint32_t rsvd3 :20; /* Reserved */
92d7f7b0
JS		 236#endif
237 } sli3Feat;
dea3101e 238} lpfc_vpd_t;
239
dea3101e 240
241/*
242 * lpfc stat counters
243 */
244struct lpfc_stats {
245 /* Statistics for ELS commands */
246 uint32_t elsLogiCol;
247 uint32_t elsRetryExceeded;
248 uint32_t elsXmitRetry;
249 uint32_t elsDelayRetry;
250 uint32_t elsRcvDrop;
251 uint32_t elsRcvFrame;
252 uint32_t elsRcvRSCN;
253 uint32_t elsRcvRNID;
254 uint32_t elsRcvFARP;
255 uint32_t elsRcvFARPR;
256 uint32_t elsRcvFLOGI;
257 uint32_t elsRcvPLOGI;
258 uint32_t elsRcvADISC;
259 uint32_t elsRcvPDISC;
260 uint32_t elsRcvFAN;
261 uint32_t elsRcvLOGO;
262 uint32_t elsRcvPRLO;
263 uint32_t elsRcvPRLI;
7bb3b137 264 uint32_t elsRcvLIRR;
12265f68 265 uint32_t elsRcvRLS;
7bb3b137 266 uint32_t elsRcvRPL;
5ffc266e 267 uint32_t elsRcvRRQ;
12265f68
JS		 268 uint32_t elsRcvRTV;
269 uint32_t elsRcvECHO;
8b017a30 270 uint32_t elsRcvLCB;
86478875 271 uint32_t elsRcvRDP;
8eced807 272 uint32_t elsRcvRDF;
dea3101e 273 uint32_t elsXmitFLOGI;
92d7f7b0 274 uint32_t elsXmitFDISC;
dea3101e 275 uint32_t elsXmitPLOGI;
276 uint32_t elsXmitPRLI;
277 uint32_t elsXmitADISC;
278 uint32_t elsXmitLOGO;
279 uint32_t elsXmitSCR;
f60cb93b 280 uint32_t elsXmitRSCN;
dea3101e 281 uint32_t elsXmitRNID;
282 uint32_t elsXmitFARP;
283 uint32_t elsXmitFARPR;
284 uint32_t elsXmitACC;
285 uint32_t elsXmitLSRJT;
286
287 uint32_t frameRcvBcast;
288 uint32_t frameRcvMulti;
289 uint32_t strayXmitCmpl;
290 uint32_t frameXmitDelay;
291 uint32_t xriCmdCmpl;
292 uint32_t xriStatErr;
293 uint32_t LinkUp;
294 uint32_t LinkDown;
295 uint32_t LinkMultiEvent;
296 uint32_t NoRcvBuf;
297 uint32_t fcpCmd;
298 uint32_t fcpCmpl;
299 uint32_t fcpRspErr;
300 uint32_t fcpRemoteStop;
301 uint32_t fcpPortRjt;
302 uint32_t fcpPortBusy;
303 uint32_t fcpError;
304 uint32_t fcpLocalErr;
305};
306
2e0fef85
JS		 307struct lpfc_hba;
308
92d7f7b0 309
02169e84
GS		 310#define LPFC_VMID_TIMER 300 /* timer interval in seconds */
311
312#define LPFC_MAX_VMID_SIZE 256
02169e84
GS		 313
314union lpfc_vmid_io_tag {
315 u32 app_id; /* App Id vmid */
316 u8 cs_ctl_vmid; /* Priority tag vmid */
317};
318
319#define JIFFIES_PER_HR (HZ * 60 * 60)
320
321struct lpfc_vmid {
322 u8 flag;
323#define LPFC_VMID_SLOT_FREE 0x0
324#define LPFC_VMID_SLOT_USED 0x1
325#define LPFC_VMID_REQ_REGISTER 0x2
326#define LPFC_VMID_REGISTERED 0x4
327#define LPFC_VMID_DE_REGISTER 0x8
328 char host_vmid[LPFC_MAX_VMID_SIZE];
329 union lpfc_vmid_io_tag un;
330 struct hlist_node hnode;
331 u64 io_rd_cnt;
332 u64 io_wr_cnt;
333 u8 vmid_len;
334 u8 delete_inactive; /* Delete if inactive flag 0 = no, 1 = yes */
335 u32 hash_index;
336 u64 __percpu *last_io_time;
337};
338
339#define lpfc_vmid_is_type_priority_tag(vport)\
340 (vport->vmid_priority_tagging ? 1 : 0)
341
342#define LPFC_VMID_HASH_SIZE 256
343#define LPFC_VMID_HASH_MASK 255
344#define LPFC_VMID_HASH_SHIFT 6
345
346struct lpfc_vmid_context {
347 struct lpfc_vmid *vmp;
348 struct lpfc_nodelist *nlp;
349 bool instantiated;
350};
351
352struct lpfc_vmid_priority_range {
353 u8 low;
354 u8 high;
355 u8 qos;
356};
357
358struct lpfc_vmid_priority_info {
359 u32 num_descriptors;
360 struct lpfc_vmid_priority_range *vmid_range;
361};
362
363#define QFPA_EVEN_ONLY 0x01
364#define QFPA_ODD_ONLY 0x02
365#define QFPA_EVEN_ODD 0x03
366
2e0fef85 367enum discovery_state {
92d7f7b0
JS		 368 LPFC_VPORT_UNKNOWN = 0, /* vport state is unknown */
369 LPFC_VPORT_FAILED = 1, /* vport has failed */
370 LPFC_LOCAL_CFG_LINK = 6, /* local NPORT Id configured */
371 LPFC_FLOGI = 7, /* FLOGI sent to Fabric */
372 LPFC_FDISC = 8, /* FDISC sent for vport */
373 LPFC_FABRIC_CFG_LINK = 9, /* Fabric assigned NPORT Id
374 * configured */
375 LPFC_NS_REG = 10, /* Register with NameServer */
376 LPFC_NS_QRY = 11, /* Query NameServer for NPort ID list */
377 LPFC_BUILD_DISC_LIST = 12, /* Build ADISC and PLOGI lists for
378 * device authentication / discovery */
379 LPFC_DISC_AUTH = 13, /* Processing ADISC list */
380 LPFC_VPORT_READY = 32,
2e0fef85
JS		 381};
382
383enum hba_state {
384 LPFC_LINK_UNKNOWN = 0, /* HBA state is unknown */
385 LPFC_WARM_START = 1, /* HBA state after selective reset */
386 LPFC_INIT_START = 2, /* Initial state after board reset */
387 LPFC_INIT_MBX_CMDS = 3, /* Initialize HBA with mbox commands */
388 LPFC_LINK_DOWN = 4, /* HBA initialized, link is down */
389 LPFC_LINK_UP = 5, /* Link is up - issue READ_LA */
92d7f7b0 390 LPFC_CLEAR_LA = 6, /* authentication cmplt - issue
2e0fef85 391 * CLEAR_LA */
92d7f7b0 392 LPFC_HBA_READY = 32,
2e0fef85
JS		 393 LPFC_HBA_ERROR = -1
394};
395
1dc5ec24
JS		 396struct lpfc_trunk_link_state {
397 enum hba_state state;
398 uint8_t fault;
399};
400
401struct lpfc_trunk_link {
402 struct lpfc_trunk_link_state link0,
403 link1,
404 link2,
405 link3;
dbb1e2ff 406 u32 phy_lnk_speed;
1dc5ec24
JS		 407};
408
72df8a45
JS		 409/* Format of congestion module parameters */
410struct lpfc_cgn_param {
411 uint32_t cgn_param_magic;
412 uint8_t cgn_param_version; /* version 1 */
413 uint8_t cgn_param_mode; /* 0=off 1=managed 2=monitor only */
414#define LPFC_CFG_OFF 0
415#define LPFC_CFG_MANAGED 1
416#define LPFC_CFG_MONITOR 2
417 uint8_t cgn_rsvd1;
418 uint8_t cgn_rsvd2;
419 uint8_t cgn_param_level0;
420 uint8_t cgn_param_level1;
421 uint8_t cgn_param_level2;
422 uint8_t byte11;
423 uint8_t byte12;
424 uint8_t byte13;
425 uint8_t byte14;
426 uint8_t byte15;
427};
428
8c42a65c
JS		 429/* Max number of days of congestion data */
430#define LPFC_MAX_CGN_DAYS 10
431
93190ac1
JT		 432struct lpfc_cgn_ts {
433 uint8_t month;
434 uint8_t day;
435 uint8_t year;
436 uint8_t hour;
437 uint8_t minute;
438 uint8_t second;
439};
440
8c42a65c
JS		 441/* Format of congestion buffer info
442 * This structure defines memory thats allocated and registered with
443 * the HBA firmware. When adding or removing fields from this structure
444 * the alignment must match the HBA firmware.
445 */
446
447struct lpfc_cgn_info {
448 /* Header */
449 __le16 cgn_info_size; /* is sizeof(struct lpfc_cgn_info) */
450 uint8_t cgn_info_version; /* represents format of structure */
451#define LPFC_CGN_INFO_V1 1
452#define LPFC_CGN_INFO_V2 2
453#define LPFC_CGN_INFO_V3 3
93190ac1 454#define LPFC_CGN_INFO_V4 4
8c42a65c
JS		 455 uint8_t cgn_info_mode; /* 0=off 1=managed 2=monitor only */
456 uint8_t cgn_info_detect;
457 uint8_t cgn_info_action;
458 uint8_t cgn_info_level0;
459 uint8_t cgn_info_level1;
460 uint8_t cgn_info_level2;
461
462 /* Start Time */
93190ac1 463 struct lpfc_cgn_ts base_time;
8c42a65c
JS		 464
465 /* minute / hours / daily indices */
466 uint8_t cgn_index_minute;
467 uint8_t cgn_index_hour;
468 uint8_t cgn_index_day;
469
470 __le16 cgn_warn_freq;
471 __le16 cgn_alarm_freq;
472 __le16 cgn_lunq;
473 uint8_t cgn_pad1[8];
474
475 /* Driver Information */
476 __le16 cgn_drvr_min[60];
477 __le32 cgn_drvr_hr[24];
478 __le32 cgn_drvr_day[LPFC_MAX_CGN_DAYS];
479
480 /* Congestion Warnings */
481 __le16 cgn_warn_min[60];
482 __le32 cgn_warn_hr[24];
483 __le32 cgn_warn_day[LPFC_MAX_CGN_DAYS];
484
485 /* Latency Information */
486 __le32 cgn_latency_min[60];
487 __le32 cgn_latency_hr[24];
488 __le32 cgn_latency_day[LPFC_MAX_CGN_DAYS];
489
490 /* Bandwidth Information */
491 __le16 cgn_bw_min[60];
492 __le16 cgn_bw_hr[24];
493 __le16 cgn_bw_day[LPFC_MAX_CGN_DAYS];
494
495 /* Congestion Alarms */
496 __le16 cgn_alarm_min[60];
497 __le32 cgn_alarm_hr[24];
498 __le32 cgn_alarm_day[LPFC_MAX_CGN_DAYS];
499
532adda9
KC		 500 struct_group(cgn_stat,
501 uint8_t cgn_stat_npm; /* Notifications per minute */
502
503 /* Start Time */
93190ac1
JT		 504 struct lpfc_cgn_ts stat_start; /* Base time */
505 uint8_t cgn_pad2;
532adda9
KC		 506
507 __le32 cgn_notification;
508 __le32 cgn_peer_notification;
509 __le32 link_integ_notification;
510 __le32 delivery_notification;
93190ac1
JT		 511 struct lpfc_cgn_ts stat_fpin; /* Last congestion notification FPIN */
512 struct lpfc_cgn_ts stat_peer; /* Last peer congestion FPIN */
513 struct lpfc_cgn_ts stat_lnk; /* Last link integrity FPIN */
514 struct lpfc_cgn_ts stat_delivery; /* Last delivery notification FPIN */
532adda9 515 );
8c42a65c
JS		 516
517 __le32 cgn_info_crc;
518#define LPFC_CGN_CRC32_MAGIC_NUMBER 0x1EDC6F41
519#define LPFC_CGN_CRC32_SEED 0xFFFFFFFF
520};
521
522#define LPFC_CGN_INFO_SZ (sizeof(struct lpfc_cgn_info) - \
523 sizeof(uint32_t))
524
02243836
JS		 525struct lpfc_cgn_stat {
526 atomic64_t total_bytes;
527 atomic64_t rcv_bytes;
528 atomic64_t rx_latency;
529#define LPFC_CGN_NOT_SENT 0xFFFFFFFFFFFFFFFFLL
530 atomic_t rx_io_cnt;
531};
532
9064aeb2
JS		 533struct lpfc_cgn_acqe_stat {
534 atomic64_t alarm;
535 atomic64_t warn;
536};
537
a645b8c1
JT		 538enum lpfc_fc_flag {
539 /* Several of these flags are HBA centric and should be moved to
540 * phba->link_flag (e.g. FC_PTP, FC_PUBLIC_LOOP)
541 */
542 FC_PT2PT, /* pt2pt with no fabric */
543 FC_PT2PT_PLOGI, /* pt2pt initiate PLOGI */
544 FC_DISC_TMO, /* Discovery timer running */
545 FC_PUBLIC_LOOP, /* Public loop */
546 FC_LBIT, /* LOGIN bit in loopinit set */
547 FC_RSCN_MODE, /* RSCN cmd rcv'ed */
548 FC_NLP_MORE, /* More node to process in node tbl */
549 FC_OFFLINE_MODE, /* Interface is offline for diag */
550 FC_FABRIC, /* We are fabric attached */
551 FC_VPORT_LOGO_RCVD, /* LOGO received on vport */
552 FC_RSCN_DISCOVERY, /* Auth all devices after RSCN */
553 FC_LOGO_RCVD_DID_CHNG, /* FDISC on phys port detect DID chng */
554 FC_PT2PT_NO_NVME, /* Don't send NVME PRLI */
555 FC_SCSI_SCAN_TMO, /* scsi scan timer running */
556 FC_ABORT_DISCOVERY, /* we want to abort discovery */
557 FC_NDISC_ACTIVE, /* NPort discovery active */
558 FC_BYPASSED_MODE, /* NPort is in bypassed mode */
559 FC_VPORT_NEEDS_REG_VPI, /* Needs to have its vpi registered */
560 FC_RSCN_DEFERRED, /* A deferred RSCN being processed */
561 FC_VPORT_NEEDS_INIT_VPI, /* Need to INIT_VPI before FDISC */
562 FC_VPORT_CVL_RCVD, /* VLink failed due to CVL */
563 FC_VFI_REGISTERED, /* VFI is registered */
564 FC_FDISC_COMPLETED, /* FDISC completed */
565 FC_DISC_DELAYED, /* Delay NPort discovery */
566};
567
e39811be
JT		 568enum lpfc_load_flag {
569 FC_LOADING, /* HBA in process of loading drvr */
570 FC_UNLOADING, /* HBA in process of unloading drvr */
571 FC_ALLOW_FDMI, /* port is ready for FDMI requests */
572 FC_ALLOW_VMID, /* Allow VMID I/Os */
573 FC_DEREGISTER_ALL_APP_ID /* Deregister all VMIDs */
574};
575
2e0fef85 576struct lpfc_vport {
2e0fef85 577 struct lpfc_hba *phba;
3772a991 578 struct list_head listentry;
2e0fef85
JS		 579 uint8_t port_type;
580#define LPFC_PHYSICAL_PORT 1
581#define LPFC_NPIV_PORT 2
582#define LPFC_FABRIC_PORT 3
583 enum discovery_state port_state;
584
92d7f7b0 585 uint16_t vpi;
da0436e9 586 uint16_t vfi;
c868595d
JS		 587 uint8_t vpi_state;
588#define LPFC_VPI_REGISTERED 0x1
2e0fef85 589
a645b8c1 590 unsigned long fc_flag; /* FC flags */
2e0fef85 591
7ee5d43e
JS		 592 uint32_t ct_flags;
593#define FC_CT_RFF_ID 0x1 /* RFF_ID accepted by switch */
594#define FC_CT_RNN_ID 0x2 /* RNN_ID accepted by switch */
595#define FC_CT_RSNN_NN 0x4 /* RSNN_NN accepted by switch */
596#define FC_CT_RSPN_ID 0x8 /* RSPN_ID accepted by switch */
597#define FC_CT_RFT_ID 0x10 /* RFT_ID accepted by switch */
de3ec318 598#define FC_CT_RPRT_DEFER 0x20 /* Defer issuing FDMI RPRT */
7ee5d43e 599
2e0fef85 600 struct list_head fc_nodes;
9bb36777 601 spinlock_t fc_nodes_list_lock; /* spinlock for fc_nodes list */
2e0fef85
JS		 602
603 /* Keep counters for the number of entries in each list. */
0dfd9cbc
JT		 604 atomic_t fc_plogi_cnt;
605 atomic_t fc_adisc_cnt;
606 atomic_t fc_reglogin_cnt;
607 atomic_t fc_prli_cnt;
608 atomic_t fc_unmap_cnt;
609 atomic_t fc_map_cnt;
610 atomic_t fc_npr_cnt;
611 atomic_t fc_unused_cnt;
612
2e0fef85
JS		 613 struct serv_parm fc_sparam; /* buffer for our service parameters */
614
615 uint32_t fc_myDID; /* fibre channel S_ID */
616 uint32_t fc_prevDID; /* previous fibre channel S_ID */
92494144
JS		 617 struct lpfc_name fabric_portname;
618 struct lpfc_name fabric_nodename;
2e0fef85
JS		 619
620 int32_t stopped; /* HBA has not been restarted since last ERATT */
621 uint8_t fc_linkspeed; /* Link speed after last READ_LA */
622
a0f2d3ef
JS		 623 uint32_t num_disc_nodes; /* in addition to hba_state */
624 uint32_t gidft_inp; /* cnt of outstanding GID_FTs */
2e0fef85
JS		 625
626 uint32_t fc_nlp_cnt; /* outstanding NODELIST requests */
627 uint32_t fc_rscn_id_cnt; /* count of RSCNs payloads in list */
7f5f3d0d 628 uint32_t fc_rscn_flush; /* flag use of fc_rscn_id_list */
2e0fef85
JS		 629 struct lpfc_dmabuf *fc_rscn_id_list[FC_MAX_HOLD_RSCN];
630 struct lpfc_name fc_nodename; /* fc nodename */
631 struct lpfc_name fc_portname; /* fc portname */
632
633 struct lpfc_work_evt disc_timeout_evt;
634
635 struct timer_list fc_disctmo; /* Discovery rescue timer */
636 uint8_t fc_ns_retry; /* retries for fabric nameserver */
637 uint32_t fc_prli_sent; /* cntr for outstanding PRLIs */
638
639 spinlock_t work_port_lock;
640 uint32_t work_port_events; /* Timeout to be handled */
858c9f6c
JS		 641#define WORKER_DISC_TMO 0x1 /* vport: Discovery timeout */
642#define WORKER_ELS_TMO 0x2 /* vport: ELS timeout */
92494144 643#define WORKER_DELAYED_DISC_TMO 0x8 /* vport: delayed discovery */
858c9f6c
JS		 644
645#define WORKER_MBOX_TMO 0x100 /* hba: MBOX timeout */
646#define WORKER_HB_TMO 0x200 /* hba: Heart beat timeout */
b1c11812 647#define WORKER_FABRIC_BLOCK_TMO 0x400 /* hba: fabric block timeout */
858c9f6c
JS		 648#define WORKER_RAMP_DOWN_QUEUE 0x800 /* hba: Decrease Q depth */
649#define WORKER_RAMP_UP_QUEUE 0x1000 /* hba: Increase Q depth */
2a9bf3d0 650#define WORKER_SERVICE_TXQ 0x2000 /* hba: IOCBs on the txq */
02169e84
GS		 651#define WORKER_CHECK_INACTIVE_VMID 0x4000 /* hba: check inactive vmids */
652#define WORKER_CHECK_VMID_ISSUE_QFPA 0x8000 /* vport: Check if qfpa needs
653 * to be issued */
2e0fef85 654
2e0fef85 655 struct timer_list els_tmofunc;
92494144 656 struct timer_list delayed_disc_tmo;
2e0fef85 657
e39811be 658 unsigned long load_flag;
3de2a653
JS		 659 /* Vport Config Parameters */
660 uint32_t cfg_scan_down;
661 uint32_t cfg_lun_queue_depth;
662 uint32_t cfg_nodev_tmo;
663 uint32_t cfg_devloss_tmo;
664 uint32_t cfg_restrict_login;
665 uint32_t cfg_peer_port_login;
666 uint32_t cfg_fcp_class;
667 uint32_t cfg_use_adisc;
3de2a653 668 uint32_t cfg_discovery_threads;
e8b62011 669 uint32_t cfg_log_verbose;
f6e84790 670 uint32_t cfg_enable_fc4_type;
3de2a653 671 uint32_t cfg_max_luns;
7ee5d43e 672 uint32_t cfg_enable_da_id;
977b5a0a 673 uint32_t cfg_max_scsicmpl_time;
7dc517df 674 uint32_t cfg_tgt_queue_depth;
3cb01c57 675 uint32_t cfg_first_burst_size;
3de2a653 676 uint32_t dev_loss_tmo_changed;
02169e84 677 /* VMID parameters */
19d7102a 678 u8 lpfc_vmid_host_uuid[16];
02169e84
GS		 679 u32 max_vmid; /* maximum VMIDs allowed per port */
680 u32 cur_vmid_cnt; /* Current VMID count */
681#define LPFC_MIN_VMID 4
682#define LPFC_MAX_VMID 255
683 u32 vmid_inactivity_timeout; /* Time after which the VMID */
684 /* deregisters from switch */
685 u32 vmid_priority_tagging;
686#define LPFC_VMID_PRIO_TAG_DISABLE 0 /* Disable */
687#define LPFC_VMID_PRIO_TAG_SUP_TARGETS 1 /* Allow supported targets only */
688#define LPFC_VMID_PRIO_TAG_ALL_TARGETS 2 /* Allow all targets */
689 unsigned long *vmid_priority_range;
690#define LPFC_VMID_MAX_PRIORITY_RANGE 256
691#define LPFC_VMID_PRIORITY_BITMAP_SIZE 32
692 u8 vmid_flag;
693#define LPFC_VMID_IN_USE 0x1
694#define LPFC_VMID_ISSUE_QFPA 0x2
695#define LPFC_VMID_QFPA_CMPL 0x4
696#define LPFC_VMID_QOS_ENABLED 0x8
697#define LPFC_VMID_TIMER_ENBLD 0x10
5099478e 698#define LPFC_VMID_TYPE_PRIO 0x20
02169e84 699 struct fc_qfpa_res *qfpa_res;
51ef4c26
JS		 700
701 struct fc_vport *fc_vport;
702
02169e84
GS		 703 struct lpfc_vmid *vmid;
704 DECLARE_HASHTABLE(hash_table, 8);
705 rwlock_t vmid_lock;
706 struct lpfc_vmid_priority_info vmid_priority;
707
923e4b6a 708#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
51ef4c26
JS		 709 struct dentry *debug_disc_trc;
710 struct dentry *debug_nodelist;
bd2cdd5e 711 struct dentry *debug_nvmestat;
4c47efc1 712 struct dentry *debug_scsistat;
2fcbc569 713 struct dentry *debug_ioktime;
840eda96 714 struct dentry *debug_hdwqstat;
51ef4c26
JS		 715 struct dentry *vport_debugfs_root;
716 struct lpfc_debugfs_trc *disc_trc;
717 atomic_t disc_trc_cnt;
718#endif
da0436e9 719 struct list_head rcv_buffer_list;
45ed1190 720 unsigned long rcv_buffer_time_stamp;
da0436e9 721 uint32_t vport_flag;
1b6f71f7
JS		 722#define STATIC_VPORT 0x1
723#define FAWWPN_PARAM_CHG 0x2
4258e98e
JS		 724
725 uint16_t fdmi_num_disc;
726 uint32_t fdmi_hba_mask;
727 uint32_t fdmi_port_mask;
895427bd
JS		 728
729 /* There is a single nvme instance per vport. */
730 struct nvme_fc_local_port *localport;
731 uint8_t nvmei_support; /* driver supports NVME Initiator */
732 uint32_t last_fcp_wqidx;
d496b9a7 733 uint32_t rcv_flogi_cnt; /* How many unsol FLOGIs ACK'd. */
2e0fef85
JS		 734};
735
ed957684
JS		 736struct hbq_s {
737 uint16_t entry_count; /* Current number of HBQ slots */
a8adb832 738 uint16_t buffer_count; /* Current number of buffers posted */
ed957684
JS		 739 uint32_t next_hbqPutIdx; /* Index to next HBQ slot to use */
740 uint32_t hbqPutIdx; /* HBQ slot to use */
741 uint32_t local_hbqGetIdx; /* Local copy of Get index from Port */
51ef4c26
JS		 742 void *hbq_virt; /* Virtual ptr to this hbq */
743 struct list_head hbq_buffer_list; /* buffers assigned to this HBQ */
744 /* Callback for HBQ buffer allocation */
745 struct hbq_dmabuf *(*hbq_alloc_buffer) (struct lpfc_hba *);
746 /* Callback for HBQ buffer free */
747 void (*hbq_free_buffer) (struct lpfc_hba *,
748 struct hbq_dmabuf *);
ed957684
JS		 749};
750
51ef4c26 751/* this matches the position in the lpfc_hbq_defs array */
92d7f7b0 752#define LPFC_ELS_HBQ 0
895427bd 753#define LPFC_MAX_HBQS 1
ed957684 754
7af67051
JS		 755enum hba_temp_state {
756 HBA_NORMAL_TEMP,
757 HBA_OVER_TEMP
758};
759
db2378e0
JS		 760enum intr_type_t {
761 NONE = 0,
762 INTx,
763 MSI,
764 MSIX,
765};
766
6dd9e31c 767#define LPFC_CT_CTX_MAX 64
f1c3b0fc
JS		 768struct unsol_rcv_ct_ctx {
769 uint32_t ctxt_id;
770 uint32_t SID;
6dd9e31c
JS		 771 uint32_t valid;
772#define UNSOL_INVALID 0
773#define UNSOL_VALID 1
7851fe2c
JS		 774 uint16_t oxid;
775 uint16_t rxid;
f1c3b0fc
JS		 776};
777
76a95d75
JS		 778#define LPFC_USER_LINK_SPEED_AUTO 0 /* auto select (default)*/
779#define LPFC_USER_LINK_SPEED_1G 1 /* 1 Gigabaud */
780#define LPFC_USER_LINK_SPEED_2G 2 /* 2 Gigabaud */
781#define LPFC_USER_LINK_SPEED_4G 4 /* 4 Gigabaud */
782#define LPFC_USER_LINK_SPEED_8G 8 /* 8 Gigabaud */
783#define LPFC_USER_LINK_SPEED_10G 10 /* 10 Gigabaud */
784#define LPFC_USER_LINK_SPEED_16G 16 /* 16 Gigabaud */
d38dd52c 785#define LPFC_USER_LINK_SPEED_32G 32 /* 32 Gigabaud */
fbd8a6ba
JS		 786#define LPFC_USER_LINK_SPEED_64G 64 /* 64 Gigabaud */
787#define LPFC_USER_LINK_SPEED_MAX LPFC_USER_LINK_SPEED_64G
788
789#define LPFC_LINK_SPEED_STRING "0, 1, 2, 4, 8, 10, 16, 32, 64"
76a95d75 790
7ad20aa9
JS		 791enum nemb_type {
792 nemb_mse = 1,
793 nemb_hbd
794};
795
796enum mbox_type {
797 mbox_rd = 1,
798 mbox_wr
799};
800
801enum dma_type {
802 dma_mbox = 1,
803 dma_ebuf
804};
805
806enum sta_type {
807 sta_pre_addr = 1,
808 sta_pos_addr
809};
810
811struct lpfc_mbox_ext_buf_ctx {
812 uint32_t state;
813#define LPFC_BSG_MBOX_IDLE 0
814#define LPFC_BSG_MBOX_HOST 1
815#define LPFC_BSG_MBOX_PORT 2
816#define LPFC_BSG_MBOX_DONE 3
817#define LPFC_BSG_MBOX_ABTS 4
818 enum nemb_type nembType;
819 enum mbox_type mboxType;
820 uint32_t numBuf;
821 uint32_t mbxTag;
822 uint32_t seqNum;
823 struct lpfc_dmabuf *mbx_dmabuf;
824 struct list_head ext_dmabuf_list;
825};
826
c490850a
JS		 827struct lpfc_epd_pool {
828 /* Expedite pool */
829 struct list_head list;
830 u32 count;
831 spinlock_t lock; /* lock for expedite pool */
832};
833
95bfc6d8
JS		 834enum ras_state {
835 INACTIVE,
836 REG_INPROGRESS,
837 ACTIVE
838};
839
d2cc9bcd
JS		 840struct lpfc_ras_fwlog {
841 uint8_t *fwlog_buff;
842 uint32_t fw_buffcount; /* Buffer size posted to FW */
843#define LPFC_RAS_BUFF_ENTERIES 16 /* Each entry can hold max of 64k */
844#define LPFC_RAS_MAX_ENTRY_SIZE (64 * 1024)
845#define LPFC_RAS_MIN_BUFF_POST_SIZE (256 * 1024)
846#define LPFC_RAS_MAX_BUFF_POST_SIZE (1024 * 1024)
847 uint32_t fw_loglevel; /* Log level set */
848 struct lpfc_dmabuf lwpd;
849 struct list_head fwlog_buff_list;
850
851 /* RAS support status on adapter */
852 bool ras_hwsupport; /* RAS Support available on HW or not */
853 bool ras_enabled; /* Ras Enabled for the function */
854#define LPFC_RAS_DISABLE_LOGGING 0x00
855#define LPFC_RAS_ENABLE_LOGGING 0x01
95bfc6d8 856 enum ras_state state; /* RAS logging running state */
d2cc9bcd
JS		 857};
858
372c187b
DK		 859#define DBG_LOG_STR_SZ 256
860#define DBG_LOG_SZ 256
861
862struct dbg_log_ent {
863 char log[DBG_LOG_STR_SZ];
864 u64 t_ns;
865};
866
3048e3e8
DK		 867enum lpfc_irq_chann_mode {
868 /* Assign IRQs to all possible cpus that have hardware queues */
869 NORMAL_MODE,
870
871 /* Assign IRQs only to cpus on the same numa node as HBA */
872 NUMA_MODE,
873
874 /* Assign IRQs only on non-hyperthreaded CPUs. This is the
875 * same as normal_mode, but assign IRQS only on physical CPUs.
876 */
877 NHT_MODE,
878};
879
35ed9613
JS		 880enum lpfc_hba_bit_flags {
881 FABRIC_COMANDS_BLOCKED,
882 HBA_PCI_ERR,
089ea22e 883 MBX_TMO_ERR,
35ed9613
JS		 884};
885
dea3101e 886struct lpfc_hba {
3772a991 887 /* SCSI interface function jump table entries */
c490850a 888 struct lpfc_io_buf * (*lpfc_get_scsi_buf)
ace44e48
JS		 889 (struct lpfc_hba *phba, struct lpfc_nodelist *ndlp,
890 struct scsi_cmnd *cmnd);
3772a991 891 int (*lpfc_scsi_prep_dma_buf)
c490850a 892 (struct lpfc_hba *, struct lpfc_io_buf *);
3772a991 893 void (*lpfc_scsi_unprep_dma_buf)
c490850a 894 (struct lpfc_hba *, struct lpfc_io_buf *);
3772a991 895 void (*lpfc_release_scsi_buf)
c490850a 896 (struct lpfc_hba *, struct lpfc_io_buf *);
3772a991
JS		 897 void (*lpfc_rampdown_queue_depth)
898 (struct lpfc_hba *);
899 void (*lpfc_scsi_prep_cmnd)
c490850a 900 (struct lpfc_vport *, struct lpfc_io_buf *,
3772a991 901 struct lpfc_nodelist *);
da255e2e
JS		 902 int (*lpfc_scsi_prep_cmnd_buf)
903 (struct lpfc_vport *vport,
904 struct lpfc_io_buf *lpfc_cmd,
905 uint8_t tmo);
3512ac09
JS		 906 int (*lpfc_scsi_prep_task_mgmt_cmd)
907 (struct lpfc_vport *vport,
908 struct lpfc_io_buf *lpfc_cmd,
909 u64 lun, u8 task_mgmt_cmd);
acd6859b 910
3772a991
JS		 911 /* IOCB interface function jump table entries */
912 int (*__lpfc_sli_issue_iocb)
913 (struct lpfc_hba *, uint32_t,
914 struct lpfc_iocbq *, uint32_t);
47ff4c51
JS		 915 int (*__lpfc_sli_issue_fcp_io)
916 (struct lpfc_hba *phba, uint32_t ring_number,
917 struct lpfc_iocbq *piocb, uint32_t flag);
3772a991
JS		 918 void (*__lpfc_sli_release_iocbq)(struct lpfc_hba *,
919 struct lpfc_iocbq *);
920 int (*lpfc_hba_down_post)(struct lpfc_hba *phba);
3772a991
JS		 921
922 /* MBOX interface function jump table entries */
923 int (*lpfc_sli_issue_mbox)
924 (struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t);
acd6859b 925
3772a991
JS		 926 /* Slow-path IOCB process function jump table entries */
927 void (*lpfc_sli_handle_slow_ring_event)
928 (struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
929 uint32_t mask);
acd6859b 930
3772a991
JS		 931 /* INIT device interface function jump table entries */
932 int (*lpfc_sli_hbq_to_firmware)
933 (struct lpfc_hba *, uint32_t, struct hbq_dmabuf *);
934 int (*lpfc_sli_brdrestart)
935 (struct lpfc_hba *);
936 int (*lpfc_sli_brdready)
937 (struct lpfc_hba *, uint32_t);
938 void (*lpfc_handle_eratt)
939 (struct lpfc_hba *);
940 void (*lpfc_stop_port)
941 (struct lpfc_hba *);
84d1b006 942 int (*lpfc_hba_init_link)
6e7288d9 943 (struct lpfc_hba *, uint32_t);
84d1b006 944 int (*lpfc_hba_down_link)
6e7288d9 945 (struct lpfc_hba *, uint32_t);
7f86059a
JS		 946 int (*lpfc_selective_reset)
947 (struct lpfc_hba *);
3772a991 948
acd6859b 949 int (*lpfc_bg_scsi_prep_dma_buf)
c490850a 950 (struct lpfc_hba *, struct lpfc_io_buf *);
6831ce12
JS		 951
952 /* Prep SLI WQE/IOCB jump table entries */
953 void (*__lpfc_sli_prep_els_req_rsp)(struct lpfc_iocbq *cmdiocbq,
954 struct lpfc_vport *vport,
955 struct lpfc_dmabuf *bmp,
956 u16 cmd_size, u32 did, u32 elscmd,
957 u8 tmo, u8 expect_rsp);
61910d6a
JS		 958 void (*__lpfc_sli_prep_gen_req)(struct lpfc_iocbq *cmdiocbq,
959 struct lpfc_dmabuf *bmp, u16 rpi,
960 u32 num_entry, u8 tmo);
961 void (*__lpfc_sli_prep_xmit_seq64)(struct lpfc_iocbq *cmdiocbq,
962 struct lpfc_dmabuf *bmp, u16 rpi,
963 u16 ox_id, u32 num_entry, u8 rctl,
964 u8 last_seq, u8 cr_cx_cmd);
31a59f75
JS		 965 void (*__lpfc_sli_prep_abort_xri)(struct lpfc_iocbq *cmdiocbq,
966 u16 ulp_context, u16 iotag,
b21c9deb
JS		 967 u8 ulp_class, u16 cqid, bool ia,
968 bool wqec);
acd6859b 969
c490850a
JS		 970 /* expedite pool */
971 struct lpfc_epd_pool epd_pool;
972
3772a991
JS		 973 /* SLI4 specific HBA data structure */
974 struct lpfc_sli4_hba sli4_hba;
975
f485c18d 976 struct workqueue_struct *wq;
32517fc0 977 struct delayed_work eq_delay_work;
f485c18d 978
317aeb83
DK		 979#define LPFC_IDLE_STAT_DELAY 1000
980 struct delayed_work idle_stat_delay_work;
981
dea3101e 982 struct lpfc_sli sli;
3772a991
JS		 983 uint8_t pci_dev_grp; /* lpfc PCI dev group: 0x0, 0x1, 0x2,... */
984 uint32_t sli_rev; /* SLI2, SLI3, or SLI4 */
ed957684 985 uint32_t sli3_options; /* Mask of enabled SLI3 options */
34b02dcd
JS		 986#define LPFC_SLI3_HBQ_ENABLED 0x01
987#define LPFC_SLI3_NPIV_ENABLED 0x02
988#define LPFC_SLI3_VPORT_TEARDOWN 0x04
989#define LPFC_SLI3_CRP_ENABLED 0x08
81301a9b 990#define LPFC_SLI3_BG_ENABLED 0x20
da0436e9 991#define LPFC_SLI3_DSS_ENABLED 0x40
fedd3b7b
JS		 992#define LPFC_SLI4_PERFH_ENABLED 0x80
993#define LPFC_SLI4_PHWQ_ENABLED 0x100
ed957684
JS		 994 uint32_t iocb_cmd_size;
995 uint32_t iocb_rsp_size;
2e0fef85 996
1dc5ec24 997 struct lpfc_trunk_link trunk_link;
2e0fef85
JS		 998 enum hba_state link_state;
999 uint32_t link_flag; /* link state flags */
311464ec 1000#define LS_LOOPBACK_MODE 0x1 /* NPort is in Loopback mode */
2e0fef85
JS		 1001 /* This flag is set while issuing */
1002 /* INIT_LINK mailbox command */
92d7f7b0 1003#define LS_NPIV_FAB_SUPPORTED 0x2 /* Fabric supports NPIV */
1b32f6aa 1004#define LS_IGNORE_ERATT 0x4 /* intr handler should ignore ERATT */
ae9e28f3 1005#define LS_MDS_LINK_DOWN 0x8 /* MDS Diagnostics Link Down */
8aaa7bcf
JS		 1006#define LS_MDS_LOOPBACK 0x10 /* MDS Diagnostics Link Up (Loopback) */
1007#define LS_CT_VEN_RPA 0x20 /* Vendor RPA sent to switch */
ead76d4c 1008#define LS_EXTERNAL_LOOPBACK 0x40 /* External loopback plug inserted */
2e0fef85 1009
9399627f
JS		 1010 uint32_t hba_flag; /* hba generic flags */
1011#define HBA_ERATT_HANDLED 0x1 /* This flag is set when eratt handled */
da0436e9 1012#define DEFER_ERATT 0x2 /* Deferred error attention in progress */
76a95d75 1013#define HBA_FCOE_MODE 0x4 /* HBA function in FCoE Mode */
45ed1190 1014#define HBA_SP_QUEUE_EVT 0x8 /* Slow-path qevt posted to worker thread*/
da0436e9 1015#define HBA_POST_RECEIVE_BUFFER 0x10 /* Rcv buffers need to be posted */
83c6cb1a 1016#define HBA_PERSISTENT_TOPO 0x20 /* Persistent topology support in hba */
e7dab164 1017#define ELS_XRI_ABORT_EVENT 0x40 /* ELS_XRI abort event was queued */
da0436e9 1018#define ASYNC_EVENT 0x80
a0c87cbd 1019#define LINK_DISABLED 0x100 /* Link disabled by user */
a93ff37a
JS		 1020#define FCF_TS_INPROG 0x200 /* FCF table scan in progress */
1021#define FCF_RR_INPROG 0x400 /* FCF roundrobin flogi in progress */
1022#define HBA_FIP_SUPPORT 0x800 /* FIP support in HBA */
a93ff37a 1023#define HBA_DEVLOSS_TMO 0x2000 /* HBA in devloss timeout */
19ca7609 1024#define HBA_RRQ_ACTIVE 0x4000 /* process the rrq active list */
c00f62e6 1025#define HBA_IOQ_FLUSH 0x8000 /* FCP/NVME I/O queues being flushed */
65791f1f 1026#define HBA_RECOVERABLE_UE 0x20000 /* Firmware supports recoverable UE */
c691816e
JS		 1027#define HBA_FORCED_LINK_SPEED 0x40000 /*
1028 * Firmware supports Forced Link Speed
1029 * capability
1030 */
0a9e9687 1031#define HBA_FLOGI_ISSUED 0x100000 /* FLOGI was issued */
835214f5 1032#define HBA_DEFER_FLOGI 0x800000 /* Defer FLOGI till read_sparm cmpl */
02243836 1033#define HBA_SETUP 0x1000000 /* Signifies HBA setup is completed */
d2f2547e 1034#define HBA_NEEDS_CFG_PORT 0x2000000 /* SLI3 - needs a CONFIG_PORT mbox */
a22d73b6
JS		 1035#define HBA_HBEAT_INP 0x4000000 /* mbox HBEAT is in progress */
1036#define HBA_HBEAT_TMO 0x8000000 /* HBEAT initiated after timeout */
9dd83f75 1037#define HBA_FLOGI_OUTSTANDING 0x10000000 /* FLOGI is outstanding */
de3ec318 1038#define HBA_RHBA_CMPL 0x20000000 /* RHBA FDMI command is successful */
895427bd 1039
7dd2e2a9 1040 struct completion *fw_dump_cmpl; /* cmpl event tracker for fw_dump */
45ed1190 1041 uint32_t fcp_ring_in_use; /* When polling test if intr-hndlr active*/
34b02dcd
JS		 1042 struct lpfc_dmabuf slim2p;
1043
1044 MAILBOX_t *mbox;
7a470277 1045 uint32_t *mbox_ext;
7ad20aa9 1046 struct lpfc_mbox_ext_buf_ctx mbox_ext_buf_ctx;
9399627f 1047 uint32_t ha_copy;
34b02dcd
JS		 1048 struct _PCB *pcb;
1049 struct _IOCB *IOCBs;
2e0fef85 1050
34b02dcd 1051 struct lpfc_dmabuf hbqslimp;
2e0fef85 1052
dea3101e 1053 uint16_t pci_cfg_value;
1054
dea3101e 1055 uint8_t fc_linkspeed; /* Link speed after last READ_LA */
1056
1057 uint32_t fc_eventTag; /* event tag for link attention */
4d9ab994 1058 uint32_t link_events;
dea3101e 1059
dea3101e 1060 /* These fields used to be binfo */
dea3101e 1061 uint32_t fc_pref_DID; /* preferred D_ID */
92d7f7b0 1062 uint8_t fc_pref_ALPA; /* preferred AL_PA */
12265f68 1063 uint32_t fc_edtovResol; /* E_D_TOV timer resolution */
dea3101e 1064 uint32_t fc_edtov; /* E_D_TOV timer value */
1065 uint32_t fc_arbtov; /* ARB_TOV timer value */
1066 uint32_t fc_ratov; /* R_A_TOV timer value */
1067 uint32_t fc_rttov; /* R_T_TOV timer value */
1068 uint32_t fc_altov; /* AL_TOV timer value */
1069 uint32_t fc_crtov; /* C_R_TOV timer value */
dea3101e 1070
dea3101e 1071 struct serv_parm fc_fabparam; /* fabric service parameters buffer */
1072 uint8_t alpa_map[128]; /* AL_PA map from READ_LA */
1073
dea3101e 1074 uint32_t lmt;
dea3101e 1075
1076 uint32_t fc_topology; /* link topology, from LINK INIT */
e74c03c8 1077 uint32_t fc_topology_changed; /* link topology, from LINK INIT */
dea3101e 1078
1079 struct lpfc_stats fc_stat;
1080
dea3101e 1081 struct lpfc_nodelist fc_fcpnodev; /* nodelist entry for no device */
1082 uint32_t nport_event_cnt; /* timestamp for nlplist entry */
1083
2e0fef85
JS		 1084 uint8_t wwnn[8];
1085 uint8_t wwpn[8];
dea3101e 1086 uint32_t RandomData[7];
7bdedb34 1087 uint8_t fcp_embed_io;
895427bd 1088 uint8_t nvmet_support; /* driver supports NVMET */
f358dd0c 1089#define LPFC_NVMET_MAX_PORTS 32
7bdedb34 1090 uint8_t mds_diags_support;
44fd7fe3 1091 uint8_t bbcredit_support;
c176ffa0 1092 uint8_t enab_exp_wqcq_pages;
0d8af096 1093 u8 nsler; /* Firmware supports FC-NVMe-2 SLER */
dea3101e 1094
3de2a653 1095 /* HBA Config Parameters */
dea3101e 1096 uint32_t cfg_ack0;
c490850a 1097 uint32_t cfg_xri_rebalancing;
d79c9e9d 1098 uint32_t cfg_xpsgl;
78b2d852 1099 uint32_t cfg_enable_npiv;
19ca7609 1100 uint32_t cfg_enable_rrq;
dea3101e 1101 uint32_t cfg_topology;
dea3101e 1102 uint32_t cfg_link_speed;
7d791df7
JS		 1103#define LPFC_FCF_FOV 1 /* Fast fcf failover */
1104#define LPFC_FCF_PRIORITY 2 /* Priority fcf failover */
1105 uint32_t cfg_fcf_failover_policy;
49aa143d 1106 uint32_t cfg_fcp_io_sched;
7ea92eb4 1107 uint32_t cfg_ns_query;
a6571c6e 1108 uint32_t cfg_fcp2_no_tgt_reset;
dea3101e 1109 uint32_t cfg_cr_delay;
1110 uint32_t cfg_cr_count;
cf5bf97e 1111 uint32_t cfg_multi_ring_support;
a4bc3379
JS		 1112 uint32_t cfg_multi_ring_rctl;
1113 uint32_t cfg_multi_ring_type;
875fbdfe
JSEC		 1114 uint32_t cfg_poll;
1115 uint32_t cfg_poll_tmo;
0c411222 1116 uint32_t cfg_task_mgmt_tmo;
4ff43246 1117 uint32_t cfg_use_msi;
0cf07f84 1118 uint32_t cfg_auto_imax;
da0436e9 1119 uint32_t cfg_fcp_imax;
41b194b8 1120 uint32_t cfg_force_rscn;
32517fc0
JS		 1121 uint32_t cfg_cq_poll_threshold;
1122 uint32_t cfg_cq_max_proc_limit;
7bb03bbf 1123 uint32_t cfg_fcp_cpu_map;
77ffd346 1124 uint32_t cfg_fcp_mq_threshold;
cdb42bec 1125 uint32_t cfg_hdw_queue;
6a828b0f 1126 uint32_t cfg_irq_chann;
f358dd0c 1127 uint32_t cfg_suppress_rsp;
895427bd 1128 uint32_t cfg_nvme_oas;
4e565cf0 1129 uint32_t cfg_nvme_embed_cmd;
2448e484 1130 uint32_t cfg_nvmet_mrq_post;
2d7dbc4c 1131 uint32_t cfg_nvmet_mrq;
f358dd0c 1132 uint32_t cfg_enable_nvmet;
895427bd 1133 uint32_t cfg_nvme_enable_fb;
2d7dbc4c 1134 uint32_t cfg_nvmet_fb_size;
96f7077f 1135 uint32_t cfg_total_seg_cnt;
dea3101e 1136 uint32_t cfg_sg_seg_cnt;
4d4c4a4a 1137 uint32_t cfg_nvme_seg_cnt;
5b9e70b2 1138 uint32_t cfg_scsi_seg_cnt;
dea3101e 1139 uint32_t cfg_sg_dma_buf_size;
3de2a653 1140 uint32_t cfg_hba_queue_depth;
13815c83
JS		 1141 uint32_t cfg_enable_hba_reset;
1142 uint32_t cfg_enable_hba_heartbeat;
1ba981fd
JS		 1143 uint32_t cfg_fof;
1144 uint32_t cfg_EnableXLane;
1145 uint8_t cfg_oas_tgt_wwpn[8];
1146 uint8_t cfg_oas_vpt_wwpn[8];
1147 uint32_t cfg_oas_lun_state;
1148#define OAS_LUN_ENABLE 1
1149#define OAS_LUN_DISABLE 0
1150 uint32_t cfg_oas_lun_status;
1151#define OAS_LUN_STATUS_EXISTS 0x01
1152 uint32_t cfg_oas_flags;
1153#define OAS_FIND_ANY_VPORT 0x01
1154#define OAS_FIND_ANY_TARGET 0x02
1155#define OAS_LUN_VALID 0x04
c92c841c 1156 uint32_t cfg_oas_priority;
1ba981fd 1157 uint32_t cfg_XLanePriority;
81301a9b 1158 uint32_t cfg_enable_bg;
b3b98b74
JS		 1159 uint32_t cfg_prot_mask;
1160 uint32_t cfg_prot_guard;
7a470277 1161 uint32_t cfg_hostmem_hgp;
da0436e9 1162 uint32_t cfg_log_verbose;
f6e84790 1163 uint32_t cfg_enable_fc4_type;
c80b27cf
JS		 1164#define LPFC_ENABLE_FCP 1
1165#define LPFC_ENABLE_NVME 2
1166#define LPFC_ENABLE_BOTH 3
1167#if (IS_ENABLED(CONFIG_NVME_FC))
1168#define LPFC_MAX_ENBL_FC4_TYPE LPFC_ENABLE_BOTH
1169#define LPFC_DEF_ENBL_FC4_TYPE LPFC_ENABLE_BOTH
1170#else
1171#define LPFC_MAX_ENBL_FC4_TYPE LPFC_ENABLE_FCP
1172#define LPFC_DEF_ENBL_FC4_TYPE LPFC_ENABLE_FCP
1173#endif
912e3acd 1174 uint32_t cfg_sriov_nr_virtfn;
c71ab861 1175 uint32_t cfg_request_firmware_upgrade;
84d1b006 1176 uint32_t cfg_suppress_link_up;
cff261f6 1177 uint32_t cfg_rrq_xri_bitmap_sz;
3e49af93 1178 u32 cfg_fcp_wait_abts_rsp;
8eb8b960 1179 uint32_t cfg_delay_discovery;
12247e81 1180 uint32_t cfg_sli_mode;
e40a02c1
JS		 1181#define LPFC_INITIALIZE_LINK 0 /* do normal init_link mbox */
1182#define LPFC_DELAY_INIT_LINK 1 /* layered driver hold off */
1183#define LPFC_DELAY_INIT_LINK_INDEFINITELY 2 /* wait, manual intervention */
4258e98e
JS		 1184 uint32_t cfg_fdmi_on;
1185#define LPFC_FDMI_NO_SUPPORT 0 /* FDMI not supported */
1186#define LPFC_FDMI_SUPPORT 1 /* FDMI supported? */
4258e98e 1187 uint32_t cfg_enable_SmartSAN;
7bdedb34 1188 uint32_t cfg_enable_mds_diags;
d2cc9bcd
JS		 1189 uint32_t cfg_ras_fwlog_level;
1190 uint32_t cfg_ras_fwlog_buffsize;
1191 uint32_t cfg_ras_fwlog_func;
1351e69f
JS		 1192 uint32_t cfg_enable_bbcr; /* Enable BB Credit Recovery */
1193 uint32_t cfg_enable_dpp; /* Enable Direct Packet Push */
414abe0a 1194 uint32_t cfg_enable_pbde;
8aaa7bcf 1195 uint32_t cfg_enable_mi;
f358dd0c 1196 struct nvmet_fc_target_port *targetport;
dea3101e 1197 lpfc_vpd_t vpd; /* vital product data */
1198
02169e84
GS		 1199 u32 cfg_max_vmid; /* maximum VMIDs allowed per port */
1200 u32 cfg_vmid_app_header;
1201#define LPFC_VMID_APP_HEADER_DISABLE 0
1202#define LPFC_VMID_APP_HEADER_ENABLE 1
1203 u32 cfg_vmid_priority_tagging;
1204 u32 cfg_vmid_inactivity_timeout; /* Time after which the VMID */
1205 /* deregisters from switch */
dea3101e 1206 struct pci_dev *pcidev;
1207 struct list_head work_list;
1208 uint32_t work_ha; /* Host Attention Bits for WT */
1209 uint32_t work_ha_mask; /* HA Bits owned by WT */
1210 uint32_t work_hs; /* HS stored in case of ERRAT */
1211 uint32_t work_status[2]; /* Extra status from SLIM */
dea3101e 1212
5e9d9b82 1213 wait_queue_head_t work_waitq;
dea3101e 1214 struct task_struct *worker_thread;
d7c255b2 1215 unsigned long data_flags;
d79c9e9d 1216 uint32_t border_sge_num;
dea3101e 1217
3163f725 1218 uint32_t hbq_in_use; /* HBQs in use flag */
ed957684 1219 uint32_t hbq_count; /* Count of configured HBQs */
92d7f7b0 1220 struct hbq_s hbqs[LPFC_MAX_HBQS]; /* local copy of hbq indicies */
ed957684 1221
895427bd
JS		 1222 atomic_t fcp_qidx; /* next FCP WQ (RR Policy) */
1223 atomic_t nvme_qidx; /* next NVME WQ (RR Policy) */
8fa38513 1224
115a4124
JS		 1225 phys_addr_t pci_bar0_map; /* Physical address for PCI BAR0 */
1226 phys_addr_t pci_bar1_map; /* Physical address for PCI BAR1 */
1227 phys_addr_t pci_bar2_map; /* Physical address for PCI BAR2 */
dea3101e 1228 void __iomem *slim_memmap_p; /* Kernel memory mapped address for
1229 PCI BAR0 */
1230 void __iomem *ctrl_regs_memmap_p;/* Kernel memory mapped address for
1231 PCI BAR2 */
1232
962bc51b
JS		 1233 void __iomem *pci_bar0_memmap_p; /* Kernel memory mapped address for
1234 PCI BAR0 with dual-ULP support */
1235 void __iomem *pci_bar2_memmap_p; /* Kernel memory mapped address for
1236 PCI BAR2 with dual-ULP support */
1237 void __iomem *pci_bar4_memmap_p; /* Kernel memory mapped address for
1238 PCI BAR4 with dual-ULP support */
1239#define PCI_64BIT_BAR0 0
1240#define PCI_64BIT_BAR2 2
1241#define PCI_64BIT_BAR4 4
dea3101e 1242 void __iomem *MBslimaddr; /* virtual address for mbox cmds */
1243 void __iomem *HAregaddr; /* virtual address for host attn reg */
1244 void __iomem *CAregaddr; /* virtual address for chip attn reg */
1245 void __iomem *HSregaddr; /* virtual address for host status
1246 reg */
1247 void __iomem *HCregaddr; /* virtual address for host ctl reg */
1248
ed957684 1249 struct lpfc_hgp __iomem *host_gp; /* Host side get/put pointers */
34b02dcd 1250 struct lpfc_pgp *port_gp;
ed957684 1251 uint32_t __iomem *hbq_put; /* Address in SLIM to HBQ put ptrs */
92d7f7b0 1252 uint32_t *hbq_get; /* Host mem address of HBQ get ptrs */
ed957684 1253
dea3101e 1254 int brd_no; /* FC board number */
dea3101e 1255 char SerialNumber[32]; /* adapter Serial Number */
1256 char OptionROMVersion[32]; /* adapter BIOS / Fcode version */
b3b4f3e1 1257 char BIOSVersion[16]; /* Boot BIOS version */
dea3101e 1258 char ModelDesc[256]; /* Model Description */
1259 char ModelName[80]; /* Model Name */
1260 char ProgramType[256]; /* Program Type */
1261 char Port[20]; /* Port No */
1262 uint8_t vpd_flag; /* VPD data flag */
1263
1264#define VPD_MODEL_DESC 0x1 /* valid vpd model description */
1265#define VPD_MODEL_NAME 0x2 /* valid vpd model name */
1266#define VPD_PROGRAM_TYPE 0x4 /* valid vpd program type */
1267#define VPD_PORT 0x8 /* valid vpd port data */
1268#define VPD_MASK 0xf /* mask for any vpd data */
1269
352e5fd1 1270
875fbdfe 1271 struct timer_list fcp_poll_timer;
9399627f 1272 struct timer_list eratt_poll;
65791f1f 1273 uint32_t eratt_poll_interval;
875fbdfe 1274
81301a9b
JS		 1275 uint64_t bg_guard_err_cnt;
1276 uint64_t bg_apptag_err_cnt;
1277 uint64_t bg_reftag_err_cnt;
dea3101e 1278
dea3101e 1279 /* fastpath list. */
a40fc5f0
JS		 1280 spinlock_t scsi_buf_list_get_lock; /* SCSI buf alloc list lock */
1281 spinlock_t scsi_buf_list_put_lock; /* SCSI buf free list lock */
1282 struct list_head lpfc_scsi_buf_list_get;
1283 struct list_head lpfc_scsi_buf_list_put;
dea3101e 1284 uint32_t total_scsi_bufs;
1285 struct list_head lpfc_iocb_list;
1286 uint32_t total_iocbq_bufs;
19ca7609 1287 struct list_head active_rrq_list;
2e0fef85 1288 spinlock_t hbalock;
02243836 1289 struct work_struct unblock_request_work; /* SCSI layer unblock IOs */
dea3101e 1290
771db5c0
RP		 1291 /* dma_mem_pools */
1292 struct dma_pool *lpfc_sg_dma_buf_pool;
1293 struct dma_pool *lpfc_mbuf_pool;
1294 struct dma_pool *lpfc_hrb_pool; /* header receive buffer pool */
1295 struct dma_pool *lpfc_drb_pool; /* data receive buffer pool */
1296 struct dma_pool *lpfc_nvmet_drb_pool; /* data receive buffer pool */
1297 struct dma_pool *lpfc_hbq_pool; /* SLI3 hbq buffer pool */
d79c9e9d 1298 struct dma_pool *lpfc_cmd_rsp_buf_pool;
dea3101e 1299 struct lpfc_dma_pool lpfc_mbuf_safety_pool;
1300
1301 mempool_t *mbox_mem_pool;
1302 mempool_t *nlp_mem_pool;
19ca7609 1303 mempool_t *rrq_pool;
cff261f6 1304 mempool_t *active_rrq_pool;
f888ba3c
JSEC		 1305
1306 struct fc_host_statistics link_stats;
3048e3e8 1307 enum lpfc_irq_chann_mode irq_chann_mode;
db2378e0 1308 enum intr_type_t intr_type;
5b75da2f
JS		 1309 uint32_t intr_mode;
1310#define LPFC_INTR_ERROR 0xFFFFFFFF
2e0fef85 1311 struct list_head port_list;
523128e5 1312 spinlock_t port_list_lock; /* lock for port_list mutations */
549e55cd
JS		 1313 struct lpfc_vport *pport; /* physical lpfc_vport pointer */
1314 uint16_t max_vpi; /* Maximum virtual nports */
8b47ae69
JS		 1315#define LPFC_MAX_VPI 0xFF /* Max number VPI supported 0 - 0xff */
1316#define LPFC_MAX_VPORTS 0x100 /* Max vports per port, with pport */
da0436e9
JS		 1317 uint16_t max_vports; /*
1318 * For IOV HBAs max_vpi can change
1319 * after a reset. max_vports is max
1320 * number of vports present. This can
1321 * be greater than max_vpi.
1322 */
1323 uint16_t vpi_base;
1324 uint16_t vfi_base;
549e55cd 1325 unsigned long *vpi_bmask; /* vpi allocation table */
6d368e53
JS		 1326 uint16_t *vpi_ids;
1327 uint16_t vpi_count;
1328 struct list_head lpfc_vpi_blk_list;
92d7f7b0
JS		 1329
1330 /* Data structure used by fabric iocb scheduler */
1331 struct list_head fabric_iocb_list;
1332 atomic_t fabric_iocb_count;
1333 struct timer_list fabric_block_timer;
1334 unsigned long bit_flags;
92d7f7b0 1335 atomic_t num_rsrc_err;
92d7f7b0
JS		 1336 unsigned long last_rsrc_error_time;
1337 unsigned long last_ramp_down_time;
923e4b6a 1338#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
858c9f6c
JS		 1339 struct dentry *hba_debugfs_root;
1340 atomic_t debugfs_vport_count;
c490850a 1341 struct dentry *debug_multixri_pools;
78b2d852 1342 struct dentry *debug_hbqinfo;
c95d6c6c
JS		 1343 struct dentry *debug_dumpHostSlim;
1344 struct dentry *debug_dumpHBASlim;
f9bb2da1 1345 struct dentry *debug_InjErrLBA; /* LBA to inject errors at */
4ac9b226
JS		 1346 struct dentry *debug_InjErrNPortID; /* NPortID to inject errors at */
1347 struct dentry *debug_InjErrWWPN; /* WWPN to inject errors at */
f9bb2da1
JS		 1348 struct dentry *debug_writeGuard; /* inject write guard_tag errors */
1349 struct dentry *debug_writeApp; /* inject write app_tag errors */
1350 struct dentry *debug_writeRef; /* inject write ref_tag errors */
acd6859b 1351 struct dentry *debug_readGuard; /* inject read guard_tag errors */
f9bb2da1
JS		 1352 struct dentry *debug_readApp; /* inject read app_tag errors */
1353 struct dentry *debug_readRef; /* inject read ref_tag errors */
1354
bd2cdd5e
JS		 1355 struct dentry *debug_nvmeio_trc;
1356 struct lpfc_debugfs_nvmeio_trc *nvmeio_trc;
5e5b511d 1357 struct dentry *debug_hdwqinfo;
6a828b0f
JS		 1358#ifdef LPFC_HDWQ_LOCK_STAT
1359 struct dentry *debug_lockstat;
1360#endif
9f778708
JS		 1361 struct dentry *debug_cgn_buffer;
1362 struct dentry *debug_rx_monitor;
95bfc6d8 1363 struct dentry *debug_ras_log;
bd2cdd5e
JS		 1364 atomic_t nvmeio_trc_cnt;
1365 uint32_t nvmeio_trc_size;
1366 uint32_t nvmeio_trc_output_idx;
1367
f9bb2da1
JS		 1368 /* T10 DIF error injection */
1369 uint32_t lpfc_injerr_wgrd_cnt;
1370 uint32_t lpfc_injerr_wapp_cnt;
1371 uint32_t lpfc_injerr_wref_cnt;
acd6859b 1372 uint32_t lpfc_injerr_rgrd_cnt;
f9bb2da1
JS		 1373 uint32_t lpfc_injerr_rapp_cnt;
1374 uint32_t lpfc_injerr_rref_cnt;
4ac9b226
JS		 1375 uint32_t lpfc_injerr_nportid;
1376 struct lpfc_name lpfc_injerr_wwpn;
f9bb2da1 1377 sector_t lpfc_injerr_lba;
acd6859b 1378#define LPFC_INJERR_LBA_OFF (sector_t)(-1)
f9bb2da1 1379
a58cbd52
JS		 1380 struct dentry *debug_slow_ring_trc;
1381 struct lpfc_debugfs_trc *slow_ring_trc;
1382 atomic_t slow_ring_trc_cnt;
2a622bfb
JS		 1383 /* iDiag debugfs sub-directory */
1384 struct dentry *idiag_root;
1385 struct dentry *idiag_pci_cfg;
b76f2dc9 1386 struct dentry *idiag_bar_acc;
2a622bfb 1387 struct dentry *idiag_que_info;
86a80846
JS		 1388 struct dentry *idiag_que_acc;
1389 struct dentry *idiag_drb_acc;
b76f2dc9
JS		 1390 struct dentry *idiag_ctl_acc;
1391 struct dentry *idiag_mbx_acc;
1392 struct dentry *idiag_ext_acc;
07bcd98e 1393 uint8_t lpfc_idiag_last_eq;
858c9f6c 1394#endif
bd2cdd5e 1395 uint16_t nvmeio_trc_on;
858c9f6c 1396
0ff10d46
JS		 1397 /* Used for deferred freeing of ELS data buffers */
1398 struct list_head elsbuf;
1399 int elsbuf_cnt;
1400 int elsbuf_prev_cnt;
1401
57127f15 1402 uint8_t temp_sensor_support;
858c9f6c
JS		 1403 /* Fields used for heart beat. */
1404 unsigned long last_completion_time;
bc73905a 1405 unsigned long skipped_hb;
858c9f6c 1406 struct timer_list hb_tmofunc;
19ca7609 1407 struct timer_list rrq_tmr;
84774a4d 1408 enum hba_temp_state over_temp_state;
76bb24ef
JS		 1409 /*
1410 * Following bit will be set for all buffer tags which are not
1411 * associated with any HBQ.
1412 */
1413#define QUE_BUFTAG_BIT (1<<31)
1414 uint32_t buffer_tag_count;
ea2151b4
JS		 1415
1416/* Maximum number of events that can be outstanding at any time*/
1417#define LPFC_MAX_EVT_COUNT 512
1418 atomic_t fast_event_count;
32b9793f
JS		 1419 uint32_t fcoe_eventtag;
1420 uint32_t fcoe_eventtag_at_fcf_scan;
80c17849
JS		 1421 uint32_t fcoe_cvl_eventtag;
1422 uint32_t fcoe_cvl_eventtag_attn;
da0436e9
JS		 1423 struct lpfc_fcf fcf;
1424 uint8_t fc_map[3];
1425 uint8_t valid_vlan;
1426 uint16_t vlan_id;
1427 struct list_head fcf_conn_rec_list;
f1c3b0fc 1428
0a9e9687
JS		 1429 bool defer_flogi_acc_flag;
1430 uint16_t defer_flogi_acc_rx_id;
1431 uint16_t defer_flogi_acc_ox_id;
1432
4fede78f 1433 spinlock_t ct_ev_lock; /* synchronize access to ct_ev_waiters */
f1c3b0fc 1434 struct list_head ct_ev_waiters;
6dd9e31c 1435 struct unsol_rcv_ct_ctx ct_ctx[LPFC_CT_CTX_MAX];
f1c3b0fc 1436 uint32_t ctx_idx;
02169e84 1437 struct timer_list inactive_vmid_poll;
e2aed29f 1438
d2cc9bcd 1439 /* RAS Support */
f733a76e 1440 spinlock_t ras_fwlog_lock; /* do not take while holding another lock */
d2cc9bcd
JS		 1441 struct lpfc_ras_fwlog ras_fwlog;
1442
2a9bf3d0
JS		 1443 uint32_t iocb_cnt;
1444 uint32_t iocb_max;
d7c47992 1445 atomic_t sdev_cnt;
1ba981fd
JS		 1446 spinlock_t devicelock; /* lock for luns list */
1447 mempool_t *device_data_mem_pool;
1448 struct list_head luns;
310429ef
JS		 1449#define LPFC_TRANSGRESSION_HIGH_TEMPERATURE 0x0080
1450#define LPFC_TRANSGRESSION_LOW_TEMPERATURE 0x0040
1451#define LPFC_TRANSGRESSION_HIGH_VOLTAGE 0x0020
1452#define LPFC_TRANSGRESSION_LOW_VOLTAGE 0x0010
1453#define LPFC_TRANSGRESSION_HIGH_TXBIAS 0x0008
1454#define LPFC_TRANSGRESSION_LOW_TXBIAS 0x0004
1455#define LPFC_TRANSGRESSION_HIGH_TXPOWER 0x0002
1456#define LPFC_TRANSGRESSION_LOW_TXPOWER 0x0001
1457#define LPFC_TRANSGRESSION_HIGH_RXPOWER 0x8000
1458#define LPFC_TRANSGRESSION_LOW_RXPOWER 0x4000
1459 uint16_t sfp_alarm;
1460 uint16_t sfp_warning;
bd2cdd5e
JS		 1461
1462#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
840eda96 1463 uint16_t hdwqstat_on;
bd2cdd5e
JS		 1464#define LPFC_CHECK_OFF 0
1465#define LPFC_CHECK_NVME_IO 1
840eda96
JS		 1466#define LPFC_CHECK_NVMET_IO 2
1467#define LPFC_CHECK_SCSI_IO 4
bd2cdd5e
JS		 1468 uint16_t ktime_on;
1469 uint64_t ktime_data_samples;
1470 uint64_t ktime_status_samples;
1471 uint64_t ktime_last_cmd;
1472 uint64_t ktime_seg1_total;
1473 uint64_t ktime_seg1_min;
1474 uint64_t ktime_seg1_max;
1475 uint64_t ktime_seg2_total;
1476 uint64_t ktime_seg2_min;
1477 uint64_t ktime_seg2_max;
1478 uint64_t ktime_seg3_total;
1479 uint64_t ktime_seg3_min;
1480 uint64_t ktime_seg3_max;
1481 uint64_t ktime_seg4_total;
1482 uint64_t ktime_seg4_min;
1483 uint64_t ktime_seg4_max;
1484 uint64_t ktime_seg5_total;
1485 uint64_t ktime_seg5_min;
1486 uint64_t ktime_seg5_max;
1487 uint64_t ktime_seg6_total;
1488 uint64_t ktime_seg6_min;
1489 uint64_t ktime_seg6_max;
1490 uint64_t ktime_seg7_total;
1491 uint64_t ktime_seg7_min;
1492 uint64_t ktime_seg7_max;
1493 uint64_t ktime_seg8_total;
1494 uint64_t ktime_seg8_min;
1495 uint64_t ktime_seg8_max;
1496 uint64_t ktime_seg9_total;
1497 uint64_t ktime_seg9_min;
1498 uint64_t ktime_seg9_max;
1499 uint64_t ktime_seg10_total;
1500 uint64_t ktime_seg10_min;
1501 uint64_t ktime_seg10_max;
1502#endif
9064aeb2 1503 /* CMF objects */
02243836
JS		 1504 struct lpfc_cgn_stat __percpu *cmf_stat;
1505 uint32_t cmf_interval_rate; /* timer interval limit in ms */
1506 uint32_t cmf_timer_cnt;
daebf93f 1507#define LPFC_CMF_INTERVAL 90
02243836
JS		 1508 uint64_t cmf_link_byte_count;
1509 uint64_t cmf_max_line_rate;
1510 uint64_t cmf_max_bytes_per_interval;
1511 uint64_t cmf_last_sync_bw;
daebf93f 1512#define LPFC_CMF_BLK_SIZE 512
02243836 1513 struct hrtimer cmf_timer;
93190ac1 1514 struct hrtimer cmf_stats_timer; /* 1 minute stats timer */
02243836
JS		 1515 atomic_t cmf_bw_wait;
1516 atomic_t cmf_busy;
1517 atomic_t cmf_stop_io; /* To block request and stop IO's */
1518 uint32_t cmf_active_mode;
1519 uint32_t cmf_info_per_interval;
daebf93f 1520#define LPFC_MAX_CMF_INFO 32
02243836
JS		 1521 struct timespec64 cmf_latency; /* Interval congestion timestamp */
1522 uint32_t cmf_last_ts; /* Interval congestion time (ms) */
1523 uint32_t cmf_active_info;
daebf93f 1524
9064aeb2
JS		 1525 /* Signal / FPIN handling for Congestion Mgmt */
1526 u8 cgn_reg_fpin; /* Negotiated value from RDF */
1527 u8 cgn_init_reg_fpin; /* Initial value from READ_CONFIG */
1528#define LPFC_CGN_FPIN_NONE 0x0
1529#define LPFC_CGN_FPIN_WARN 0x1
1530#define LPFC_CGN_FPIN_ALARM 0x2
1531#define LPFC_CGN_FPIN_BOTH (LPFC_CGN_FPIN_WARN | LPFC_CGN_FPIN_ALARM)
1532
1533 u8 cgn_reg_signal; /* Negotiated value from EDC */
1534 u8 cgn_init_reg_signal; /* Initial value from READ_CONFIG */
1535 /* cgn_reg_signal and cgn_init_reg_signal use
1536 * enum fc_edc_cg_signal_cap_types
1537 */
71ddeeaf 1538 u16 cgn_fpin_frequency; /* In units of msecs */
9064aeb2
JS		 1539#define LPFC_FPIN_INIT_FREQ 0xffff
1540 u32 cgn_sig_freq;
1541 u32 cgn_acqe_cnt;
1542
17b27ac5 1543 /* RX monitor handling for CMF */
bd269188 1544 struct lpfc_rx_info_monitor *rx_monitor;
17b27ac5 1545 atomic_t rx_max_read_cnt; /* Maximum read bytes */
02243836
JS		 1546 uint64_t rx_block_cnt;
1547
72df8a45
JS		 1548 /* Congestion parameters from flash */
1549 struct lpfc_cgn_param cgn_p;
1550
9064aeb2
JS		 1551 /* Statistics counter for ACQE cgn alarms and warnings */
1552 struct lpfc_cgn_acqe_stat cgn_acqe_stat;
1553
1554 /* Congestion buffer information */
8c42a65c 1555 struct lpfc_dmabuf *cgn_i; /* Congestion Info buffer */
9064aeb2
JS		 1556 atomic_t cgn_fabric_warn_cnt; /* Total warning cgn events for info */
1557 atomic_t cgn_fabric_alarm_cnt; /* Total alarm cgn events for info */
1558 atomic_t cgn_sync_warn_cnt; /* Total warning events for SYNC wqe */
1559 atomic_t cgn_sync_alarm_cnt; /* Total alarm events for SYNC wqe */
8c42a65c
JS		 1560 atomic_t cgn_driver_evt_cnt; /* Total driver cgn events for fmw */
1561 atomic_t cgn_latency_evt_cnt;
8c42a65c
JS		 1562 atomic64_t cgn_latency_evt; /* Avg latency per minute */
1563 unsigned long cgn_evt_timestamp;
1564#define LPFC_CGN_TIMER_TO_MIN 60000 /* ms in a minute */
1565 uint32_t cgn_evt_minute;
93190ac1 1566#define LPFC_SEC_MIN 60UL
8c42a65c
JS		 1567#define LPFC_MIN_HOUR 60
1568#define LPFC_HOUR_DAY 24
1569#define LPFC_MIN_DAY (LPFC_MIN_HOUR * LPFC_HOUR_DAY)
93a4d6f4
JS		 1570
1571 struct hlist_node cpuhp; /* used for cpuhp per hba callback */
1572 struct timer_list cpuhp_poll_timer;
1573 struct list_head poll_list; /* slowpath eq polling list */
1574#define LPFC_POLL_HB 1 /* slowpath heartbeat */
e3ba04c9
JS		 1575
1576 char os_host_name[MAXHOSTNAMELEN];
c90b4480 1577
dbb1e2ff
JS		 1578 /* LD Signaling */
1579 u32 degrade_activate_threshold;
1580 u32 degrade_deactivate_threshold;
1581 u32 fec_degrade_interval;
1582
372c187b
DK		 1583 atomic_t dbg_log_idx;
1584 atomic_t dbg_log_cnt;
1585 atomic_t dbg_log_dmping;
1586 struct dbg_log_ent dbg_log[DBG_LOG_SZ];
dea3101e 1587};
1588
17b27ac5 1589#define LPFC_MAX_RXMONITOR_ENTRY 800
74a7baa2 1590#define LPFC_MAX_RXMONITOR_DUMP 32
bd269188 1591struct rx_info_entry {
a6269f83 1592 uint64_t cmf_bytes; /* Total no of read bytes for CMF_SYNC_WQE */
17b27ac5
JS		 1593 uint64_t total_bytes; /* Total no of read bytes requested */
1594 uint64_t rcv_bytes; /* Total no of read bytes completed */
1595 uint64_t avg_io_size;
1596 uint64_t avg_io_latency;/* Average io latency in microseconds */
1597 uint64_t max_read_cnt; /* Maximum read bytes */
1598 uint64_t max_bytes_per_interval;
1599 uint32_t cmf_busy;
1600 uint32_t cmf_info; /* CMF_SYNC_WQE info */
1601 uint32_t io_cnt;
1602 uint32_t timer_utilization;
1603 uint32_t timer_interval;
1604};
1605
bd269188
JS		 1606struct lpfc_rx_info_monitor {
1607 struct rx_info_entry *ring; /* info organized in a circular buffer */
1608 u32 head_idx, tail_idx; /* index to head/tail of ring */
1609 spinlock_t lock; /* spinlock for ring */
1610 u32 entries; /* storing number entries/size of ring */
1611};
1612
2e0fef85
JS		 1613static inline struct Scsi_Host *
1614lpfc_shost_from_vport(struct lpfc_vport *vport)
1615{
1616 return container_of((void *) vport, struct Scsi_Host, hostdata[0]);
1617}
1618
5b8bd0c9 1619static inline void
2e0fef85
JS		 1620lpfc_set_loopback_flag(struct lpfc_hba *phba)
1621{
5b8bd0c9 1622 if (phba->cfg_topology == FLAGS_LOCAL_LB)
2e0fef85 1623 phba->link_flag |= LS_LOOPBACK_MODE;
5b8bd0c9 1624 else
2e0fef85
JS		 1625 phba->link_flag &= ~LS_LOOPBACK_MODE;
1626}
1627
1628static inline int
1629lpfc_is_link_up(struct lpfc_hba *phba)
1630{
1631 return phba->link_state == LPFC_LINK_UP ||
92d7f7b0
JS		 1632 phba->link_state == LPFC_CLEAR_LA ||
1633 phba->link_state == LPFC_HBA_READY;
5b8bd0c9 1634}
dea3101e 1635
5e9d9b82
JS		 1636static inline void
1637lpfc_worker_wake_up(struct lpfc_hba *phba)
1638{
1639 /* Set the lpfc data pending flag */
1640 set_bit(LPFC_DATA_READY, &phba->data_flags);
1641
1642 /* Wake up worker thread */
1643 wake_up(&phba->work_waitq);
1644 return;
1645}
1646
9940b97b
JS		 1647static inline int
1648lpfc_readl(void __iomem *addr, uint32_t *data)
1649{
1650 uint32_t temp;
1651 temp = readl(addr);
1652 if (temp == 0xffffffff)
1653 return -EIO;
1654 *data = temp;
1655 return 0;
1656}
1657
1658static inline int
9399627f
JS		 1659lpfc_sli_read_hs(struct lpfc_hba *phba)
1660{
1661 /*
1662 * There was a link/board error. Read the status register to retrieve
1663 * the error event and process it.
1664 */
1665 phba->sli.slistat.err_attn_event++;
1666
9940b97b
JS		 1667 /* Save status info and check for unplug error */
1668 if (lpfc_readl(phba->HSregaddr, &phba->work_hs) ||
1669 lpfc_readl(phba->MBslimaddr + 0xa8, &phba->work_status[0]) ||
1670 lpfc_readl(phba->MBslimaddr + 0xac, &phba->work_status[1])) {
1671 return -EIO;
1672 }
9399627f
JS		 1673
1674 /* Clear chip Host Attention error bit */
1675 writel(HA_ERATT, phba->HAregaddr);
1676 readl(phba->HAregaddr); /* flush */
1677 phba->pport->stopped = 1;
1678
9940b97b 1679 return 0;
9399627f 1680}
895427bd
JS		 1681
1682static inline struct lpfc_sli_ring *
1683lpfc_phba_elsring(struct lpfc_hba *phba)
1684{
5a9eeff5
JS		 1685 /* Return NULL if sli_rev has become invalid due to bad fw */
1686 if (phba->sli_rev != LPFC_SLI_REV4 &&
1687 phba->sli_rev != LPFC_SLI_REV3 &&
1688 phba->sli_rev != LPFC_SLI_REV2)
1689 return NULL;
1690
0c9c6a75
JS		 1691 if (phba->sli_rev == LPFC_SLI_REV4) {
1692 if (phba->sli4_hba.els_wq)
1693 return phba->sli4_hba.els_wq->pring;
1694 else
1695 return NULL;
1696 }
895427bd
JS		 1697 return &phba->sli.sli3_ring[LPFC_ELS_RING];
1698}
32517fc0 1699
dcaa2136 1700/**
3048e3e8
DK		 1701 * lpfc_next_online_cpu - Finds next online CPU on cpumask
1702 * @mask: Pointer to phba's cpumask member.
dcaa2136
JS		 1703 * @start: starting cpu index
1704 *
1705 * Note: If no valid cpu found, then nr_cpu_ids is returned.
1706 *
1707 **/
1708static inline unsigned int
3048e3e8 1709lpfc_next_online_cpu(const struct cpumask *mask, unsigned int start)
dcaa2136
JS		 1710{
1711 unsigned int cpu_it;
1712
3048e3e8 1713 for_each_cpu_wrap(cpu_it, mask, start) {
dcaa2136
JS		 1714 if (cpu_online(cpu_it))
1715 break;
1716 }
1717
1718 return cpu_it;
1719}
d668b368
JT		 1720/**
1721 * lpfc_next_present_cpu - Finds next present CPU after n
1722 * @n: the cpu prior to search
1723 *
1724 * Note: If no next present cpu, then fallback to first present cpu.
1725 *
1726 **/
1727static inline unsigned int lpfc_next_present_cpu(int n)
1728{
1729 unsigned int cpu;
1730
1731 cpu = cpumask_next(n, cpu_present_mask);
1732
1733 if (cpu >= nr_cpu_ids)
1734 cpu = cpumask_first(cpu_present_mask);
1735
1736 return cpu;
1737}
1738
32517fc0
JS		 1739/**
1740 * lpfc_sli4_mod_hba_eq_delay - update EQ delay
1741 * @phba: Pointer to HBA context object.
1742 * @q: The Event Queue to update.
1743 * @delay: The delay value (in us) to be written.
1744 *
1745 **/
1746static inline void
1747lpfc_sli4_mod_hba_eq_delay(struct lpfc_hba *phba, struct lpfc_queue *eq,
1748 u32 delay)
1749{
1750 struct lpfc_register reg_data;
1751
1752 reg_data.word0 = 0;
1753 bf_set(lpfc_sliport_eqdelay_id, &reg_data, eq->queue_id);
1754 bf_set(lpfc_sliport_eqdelay_delay, &reg_data, delay);
1755 writel(reg_data.word0, phba->sli4_hba.u.if_type2.EQDregaddr);
1756 eq->q_mode = delay;
1757}
df3fe766
JS		 1758
1759
1760/*
1761 * Macro that declares tables and a routine to perform enum type to
1762 * ascii string lookup.
1763 *
1764 * Defines a <key,value> table for an enum. Uses xxx_INIT defines for
1765 * the enum to populate the table. Macro defines a routine (named
1766 * by caller) that will search all elements of the table for the key
1767 * and return the name string if found or "Unrecognized" if not found.
1768 */
1769#define DECLARE_ENUM2STR_LOOKUP(routine, enum_name, enum_init) \
1770static struct { \
1771 enum enum_name value; \
1772 char *name; \
1773} fc_##enum_name##_e2str_names[] = enum_init; \
1774static const char *routine(enum enum_name table_key) \
1775{ \
1776 int i; \
1777 char *name = "Unrecognized"; \
1778 \
1779 for (i = 0; i < ARRAY_SIZE(fc_##enum_name##_e2str_names); i++) {\
1780 if (fc_##enum_name##_e2str_names[i].value == table_key) {\
1781 name = fc_##enum_name##_e2str_names[i].name; \
1782 break; \
1783 } \
1784 } \
1785 return name; \
1786}
02169e84
GS		 1787
1788/**
1789 * lpfc_is_vmid_enabled - returns if VMID is enabled for either switch types
1790 * @phba: Pointer to HBA context object.
1791 *
1792 * Relationship between the enable, target support and if vmid tag is required
1793 * for the particular combination
1794 * ---------------------------------------------------
1795 * Switch Enable Flag Target Support VMID Needed
1796 * ---------------------------------------------------
1797 * App Id 0 NA N
1798 * App Id 1 0 N
1799 * App Id 1 1 Y
1800 * Pr Tag 0 NA N
1801 * Pr Tag 1 0 N
1802 * Pr Tag 1 1 Y
1803 * Pr Tag 2 * Y
1804 ---------------------------------------------------
1805 *
1806 **/
1807static inline int lpfc_is_vmid_enabled(struct lpfc_hba *phba)
1808{
1809 return phba->cfg_vmid_app_header || phba->cfg_vmid_priority_tagging;
1810}
1b64aa9e
JS		 1811
1812static inline
1813u8 get_job_ulpstatus(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq)
1814{
1815 if (phba->sli_rev == LPFC_SLI_REV4)
1816 return bf_get(lpfc_wcqe_c_status, &iocbq->wcqe_cmpl);
1817 else
1818 return iocbq->iocb.ulpStatus;
1819}
1820
1821static inline
1822u32 get_job_word4(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq)
1823{
1824 if (phba->sli_rev == LPFC_SLI_REV4)
1825 return iocbq->wcqe_cmpl.parameter;
1826 else
1827 return iocbq->iocb.un.ulpWord[4];
1828}
1829
1830static inline
1831u8 get_job_cmnd(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq)
1832{
1833 if (phba->sli_rev == LPFC_SLI_REV4)
1834 return bf_get(wqe_cmnd, &iocbq->wqe.generic.wqe_com);
1835 else
1836 return iocbq->iocb.ulpCommand;
1837}
1838
1839static inline
1840u16 get_job_ulpcontext(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq)
1841{
1842 if (phba->sli_rev == LPFC_SLI_REV4)
1843 return bf_get(wqe_ctxt_tag, &iocbq->wqe.generic.wqe_com);
1844 else
1845 return iocbq->iocb.ulpContext;
1846}
6831ce12 1847
cad93a08
JS		 1848static inline
1849u16 get_job_rcvoxid(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq)
1850{
1851 if (phba->sli_rev == LPFC_SLI_REV4)
1852 return bf_get(wqe_rcvoxid, &iocbq->wqe.generic.wqe_com);
1853 else
1854 return iocbq->iocb.unsli3.rcvsli3.ox_id;
1855}
1856
61910d6a
JS		 1857static inline
1858u32 get_job_data_placed(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq)
1859{
1860 if (phba->sli_rev == LPFC_SLI_REV4)
1861 return iocbq->wcqe_cmpl.total_data_placed;
1862 else
1863 return iocbq->iocb.un.genreq64.bdl.bdeSize;
1864}
1865
31a59f75
JS		 1866static inline
1867u32 get_job_abtsiotag(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq)
1868{
1869 if (phba->sli_rev == LPFC_SLI_REV4)
1870 return iocbq->wqe.abort_cmd.wqe_com.abort_tag;
1871 else
1872 return iocbq->iocb.un.acxri.abortIoTag;
1873}
1874
6831ce12
JS		 1875static inline
1876u32 get_job_els_rsp64_did(struct lpfc_hba *phba, struct lpfc_iocbq *iocbq)
1877{
1878 if (phba->sli_rev == LPFC_SLI_REV4)
1879 return bf_get(wqe_els_did, &iocbq->wqe.els_req.wqe_dest);
1880 else
1881 return iocbq->iocb.un.elsreq64.remoteID;
1882}
Linux 6.x block layer and io_uring tree(s)