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scsi: lpfc: Separate NVMET RQ buffer posting from IO resources SGL/iocbq/context
[linux-2.6-block.git] / drivers / scsi / lpfc / lpfc.h
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dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
d080abe0
JS		 4 * Copyright (C) 2017 Broadcom. All Rights Reserved. The term *
5 * “Broadcom” refers to Broadcom Limited and/or its subsidiaries. *
50611577 6 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
c44ce173 7 * EMULEX and SLI are trademarks of Emulex. *
d080abe0 8 * www.broadcom.com *
c44ce173 9 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e 10 * *
11 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC		 12 * modify it under the terms of version 2 of the GNU General *
13 * Public License as published by the Free Software Foundation. *
14 * This program is distributed in the hope that it will be useful. *
15 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
16 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
17 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
18 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
19 * TO BE LEGALLY INVALID. See the GNU General Public License for *
20 * more details, a copy of which can be found in the file COPYING *
21 * included with this package. *
dea3101e 22 *******************************************************************/
23
2e0fef85 24#include <scsi/scsi_host.h>
895427bd 25#include <linux/ktime.h>
88a2cfbb
JS		 26
27#if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS)
28#define CONFIG_SCSI_LPFC_DEBUG_FS
29#endif
30
dea3101e 31struct lpfc_sli2_slim;
32
5402a315
JS		 33#define ELX_MODEL_NAME_SIZE 80
34
3772a991
JS		 35#define LPFC_PCI_DEV_LP 0x1
36#define LPFC_PCI_DEV_OC 0x2
37
38#define LPFC_SLI_REV2 2
39#define LPFC_SLI_REV3 3
40#define LPFC_SLI_REV4 4
41
97eab634 42#define LPFC_MAX_TARGET 4096 /* max number of targets supported */
e17da18e
JS		 43#define LPFC_MAX_DISC_THREADS 64 /* max outstanding discovery els
44 requests */
45#define LPFC_MAX_NS_RETRY 3 /* Number of retry attempts to contact
46 the NameServer before giving up. */
445cf4f4 47#define LPFC_CMD_PER_LUN 3 /* max outstanding cmds per lun */
81301a9b 48#define LPFC_DEFAULT_SG_SEG_CNT 64 /* sg element count per scsi cmnd */
e2aed29f
JS		 49#define LPFC_DEFAULT_MENLO_SG_SEG_CNT 128 /* sg element count per scsi
50 cmnd for menlo needs nearly twice as for firmware
51 downloads using bsg */
96f7077f
JS		 52
53#define LPFC_MIN_SG_SLI4_BUF_SZ 0x800 /* based on LPFC_DEFAULT_SG_SEG_CNT */
54#define LPFC_MAX_SG_SLI4_SEG_CNT_DIF 128 /* sg element count per scsi cmnd */
55#define LPFC_MAX_SG_SEG_CNT_DIF 512 /* sg element count per scsi cmnd */
81301a9b 56#define LPFC_MAX_SG_SEG_CNT 4096 /* sg element count per scsi cmnd */
09294d46
JS		 57#define LPFC_MAX_SGL_SEG_CNT 512 /* SGL element count per scsi cmnd */
58#define LPFC_MAX_BPL_SEG_CNT 4096 /* BPL element count per scsi cmnd */
4d4c4a4a 59#define LPFC_MAX_NVME_SEG_CNT 128 /* max SGL element cnt per NVME cmnd */
09294d46 60
0558056c 61#define LPFC_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */
dea3101e 62#define LPFC_IOCB_LIST_CNT 2250 /* list of IOCBs for fast-path usage. */
445cf4f4 63#define LPFC_Q_RAMP_UP_INTERVAL 120 /* lun q_depth ramp up interval */
495a714c 64#define LPFC_VNAME_LEN 100 /* vport symbolic name length */
977b5a0a
JS		 65#define LPFC_TGTQ_INTERVAL 40000 /* Min amount of time between tgt
66 queue depth change in millisecs */
67#define LPFC_TGTQ_RAMPUP_PCENT 5 /* Target queue rampup in percentage */
7dc517df 68#define LPFC_MIN_TGT_QDEPTH 10
977b5a0a 69#define LPFC_MAX_TGT_QDEPTH 0xFFFF
dea3101e 70
ea2151b4
JS		 71#define LPFC_MAX_BUCKET_COUNT 20 /* Maximum no. of buckets for stat data
72 collection. */
92d7f7b0
JS		 73/*
74 * Following time intervals are used of adjusting SCSI device
75 * queue depths when there are driver resource error or Firmware
76 * resource error.
77 */
256ec0d0
JS		 78/* 1 Second */
79#define QUEUE_RAMP_DOWN_INTERVAL (msecs_to_jiffies(1000 * 1))
92d7f7b0
JS		 80
81/* Number of exchanges reserved for discovery to complete */
82#define LPFC_DISC_IOCB_BUFF_COUNT 20
83
858c9f6c 84#define LPFC_HB_MBOX_INTERVAL 5 /* Heart beat interval in seconds. */
311464ec 85#define LPFC_HB_MBOX_TIMEOUT 30 /* Heart beat timeout in seconds. */
858c9f6c 86
ba20c853
JS		 87#define LPFC_LOOK_AHEAD_OFF 0 /* Look ahead logic is turned off */
88
9399627f
JS		 89/* Error Attention event polling interval */
90#define LPFC_ERATT_POLL_INTERVAL 5 /* EATT poll interval in seconds */
91
dea3101e 92/* Define macros for 64 bit support */
93#define putPaddrLow(addr) ((uint32_t) (0xffffffff & (u64)(addr)))
94#define putPaddrHigh(addr) ((uint32_t) (0xffffffff & (((u64)(addr))>>32)))
95#define getPaddr(high, low) ((dma_addr_t)( \
96 (( (u64)(high)<<16 ) << 16)|( (u64)(low))))
97/* Provide maximum configuration definitions. */
98#define LPFC_DRVR_TIMEOUT 16 /* driver iocb timeout value in sec */
dea3101e 99#define FC_MAX_ADPTMSG 64
100
101#define MAX_HBAEVT 32
96418b5e 102#define MAX_HBAS_NO_RESET 16
dea3101e 103
9399627f
JS		 104/* Number of MSI-X vectors the driver uses */
105#define LPFC_MSIX_VECTORS 2
106
5e9d9b82 107/* lpfc wait event data ready flag */
2ade92ae 108#define LPFC_DATA_READY 0 /* bit 0 */
5e9d9b82 109
809c7536
JS		 110/* queue dump line buffer size */
111#define LPFC_LBUF_SZ 128
112
618a5230
JS		 113/* mailbox system shutdown options */
114#define LPFC_MBX_NO_WAIT 0
115#define LPFC_MBX_WAIT 1
116
875fbdfe
JSEC		 117enum lpfc_polling_flags {
118 ENABLE_FCP_RING_POLLING = 0x1,
119 DISABLE_FCP_RING_INT = 0x2
120};
121
895427bd
JS		 122struct perf_prof {
123 uint16_t cmd_cpu[40];
124 uint16_t rsp_cpu[40];
125 uint16_t qh_cpu[40];
126 uint16_t wqidx[40];
127};
128
01649561
JS		 129/*
130 * Provide for FC4 TYPE x28 - NVME. The
131 * bit mask for FCP and NVME is 0x8 identically
132 * because they are 32 bit positions distance.
133 */
a0f2d3ef
JS		 134#define LPFC_FC4_TYPE_BITMASK 0x00000100
135
dea3101e 136/* Provide DMA memory definitions the driver uses per port instance. */
137struct lpfc_dmabuf {
138 struct list_head list;
139 void *virt; /* virtual address ptr */
140 dma_addr_t phys; /* mapped address */
76bb24ef 141 uint32_t buffer_tag; /* used for tagged queue ring */
dea3101e 142};
143
6c621a22
JS		 144struct lpfc_nvmet_ctxbuf {
145 struct list_head list;
146 struct lpfc_nvmet_rcv_ctx *context;
147 struct lpfc_iocbq *iocbq;
148 struct lpfc_sglq *sglq;
149};
150
dea3101e 151struct lpfc_dma_pool {
152 struct lpfc_dmabuf *elements;
153 uint32_t max_count;
154 uint32_t current_count;
155};
156
ed957684 157struct hbq_dmabuf {
da0436e9 158 struct lpfc_dmabuf hbuf;
ed957684 159 struct lpfc_dmabuf dbuf;
895427bd
JS		 160 uint16_t total_size;
161 uint16_t bytes_recv;
ed957684 162 uint32_t tag;
4d9ab994 163 struct lpfc_cq_event cq_event;
45ed1190 164 unsigned long time_stamp;
895427bd
JS		 165 void *context;
166};
167
168struct rqb_dmabuf {
169 struct lpfc_dmabuf hbuf;
170 struct lpfc_dmabuf dbuf;
171 uint16_t total_size;
172 uint16_t bytes_recv;
895427bd
JS		 173 struct lpfc_queue *hrq; /* ptr to associated Header RQ */
174 struct lpfc_queue *drq; /* ptr to associated Data RQ */
ed957684
JS		 175};
176
dea3101e 177/* Priority bit. Set value to exceed low water mark in lpfc_mem. */
178#define MEM_PRI 0x100
179
180
181/****************************************************************************/
182/* Device VPD save area */
183/****************************************************************************/
184typedef struct lpfc_vpd {
185 uint32_t status; /* vpd status value */
186 uint32_t length; /* number of bytes actually returned */
187 struct {
188 uint32_t rsvd1; /* Revision numbers */
189 uint32_t biuRev;
190 uint32_t smRev;
191 uint32_t smFwRev;
192 uint32_t endecRev;
193 uint16_t rBit;
194 uint8_t fcphHigh;
195 uint8_t fcphLow;
196 uint8_t feaLevelHigh;
197 uint8_t feaLevelLow;
198 uint32_t postKernRev;
199 uint32_t opFwRev;
200 uint8_t opFwName[16];
201 uint32_t sli1FwRev;
202 uint8_t sli1FwName[16];
203 uint32_t sli2FwRev;
204 uint8_t sli2FwName[16];
205 } rev;
92d7f7b0
JS		 206 struct {
207#ifdef __BIG_ENDIAN_BITFIELD
da0436e9
JS		 208 uint32_t rsvd3 :19; /* Reserved */
209 uint32_t cdss : 1; /* Configure Data Security SLI */
210 uint32_t rsvd2 : 3; /* Reserved */
211 uint32_t cbg : 1; /* Configure BlockGuard */
92d7f7b0
JS		 212 uint32_t cmv : 1; /* Configure Max VPIs */
213 uint32_t ccrp : 1; /* Config Command Ring Polling */
214 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
215 uint32_t chbs : 1; /* Cofigure Host Backing store */
216 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
217 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
218 uint32_t cmx : 1; /* Configure Max XRIs */
219 uint32_t cmr : 1; /* Configure Max RPIs */
220#else /* __LITTLE_ENDIAN */
221 uint32_t cmr : 1; /* Configure Max RPIs */
222 uint32_t cmx : 1; /* Configure Max XRIs */
223 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
224 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
225 uint32_t chbs : 1; /* Cofigure Host Backing store */
226 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
227 uint32_t ccrp : 1; /* Config Command Ring Polling */
228 uint32_t cmv : 1; /* Configure Max VPIs */
da0436e9
JS		 229 uint32_t cbg : 1; /* Configure BlockGuard */
230 uint32_t rsvd2 : 3; /* Reserved */
231 uint32_t cdss : 1; /* Configure Data Security SLI */
232 uint32_t rsvd3 :19; /* Reserved */
92d7f7b0
JS		 233#endif
234 } sli3Feat;
dea3101e 235} lpfc_vpd_t;
236
237struct lpfc_scsi_buf;
238
239
240/*
241 * lpfc stat counters
242 */
243struct lpfc_stats {
244 /* Statistics for ELS commands */
245 uint32_t elsLogiCol;
246 uint32_t elsRetryExceeded;
247 uint32_t elsXmitRetry;
248 uint32_t elsDelayRetry;
249 uint32_t elsRcvDrop;
250 uint32_t elsRcvFrame;
251 uint32_t elsRcvRSCN;
252 uint32_t elsRcvRNID;
253 uint32_t elsRcvFARP;
254 uint32_t elsRcvFARPR;
255 uint32_t elsRcvFLOGI;
256 uint32_t elsRcvPLOGI;
257 uint32_t elsRcvADISC;
258 uint32_t elsRcvPDISC;
259 uint32_t elsRcvFAN;
260 uint32_t elsRcvLOGO;
261 uint32_t elsRcvPRLO;
262 uint32_t elsRcvPRLI;
7bb3b137 263 uint32_t elsRcvLIRR;
12265f68 264 uint32_t elsRcvRLS;
7bb3b137
JW		 265 uint32_t elsRcvRPS;
266 uint32_t elsRcvRPL;
5ffc266e 267 uint32_t elsRcvRRQ;
12265f68
JS		 268 uint32_t elsRcvRTV;
269 uint32_t elsRcvECHO;
8b017a30 270 uint32_t elsRcvLCB;
86478875 271 uint32_t elsRcvRDP;
dea3101e 272 uint32_t elsXmitFLOGI;
92d7f7b0 273 uint32_t elsXmitFDISC;
dea3101e 274 uint32_t elsXmitPLOGI;
275 uint32_t elsXmitPRLI;
276 uint32_t elsXmitADISC;
277 uint32_t elsXmitLOGO;
278 uint32_t elsXmitSCR;
279 uint32_t elsXmitRNID;
280 uint32_t elsXmitFARP;
281 uint32_t elsXmitFARPR;
282 uint32_t elsXmitACC;
283 uint32_t elsXmitLSRJT;
284
285 uint32_t frameRcvBcast;
286 uint32_t frameRcvMulti;
287 uint32_t strayXmitCmpl;
288 uint32_t frameXmitDelay;
289 uint32_t xriCmdCmpl;
290 uint32_t xriStatErr;
291 uint32_t LinkUp;
292 uint32_t LinkDown;
293 uint32_t LinkMultiEvent;
294 uint32_t NoRcvBuf;
295 uint32_t fcpCmd;
296 uint32_t fcpCmpl;
297 uint32_t fcpRspErr;
298 uint32_t fcpRemoteStop;
299 uint32_t fcpPortRjt;
300 uint32_t fcpPortBusy;
301 uint32_t fcpError;
302 uint32_t fcpLocalErr;
303};
304
2e0fef85
JS		 305struct lpfc_hba;
306
92d7f7b0 307
2e0fef85 308enum discovery_state {
92d7f7b0
JS		 309 LPFC_VPORT_UNKNOWN = 0, /* vport state is unknown */
310 LPFC_VPORT_FAILED = 1, /* vport has failed */
311 LPFC_LOCAL_CFG_LINK = 6, /* local NPORT Id configured */
312 LPFC_FLOGI = 7, /* FLOGI sent to Fabric */
313 LPFC_FDISC = 8, /* FDISC sent for vport */
314 LPFC_FABRIC_CFG_LINK = 9, /* Fabric assigned NPORT Id
315 * configured */
316 LPFC_NS_REG = 10, /* Register with NameServer */
317 LPFC_NS_QRY = 11, /* Query NameServer for NPort ID list */
318 LPFC_BUILD_DISC_LIST = 12, /* Build ADISC and PLOGI lists for
319 * device authentication / discovery */
320 LPFC_DISC_AUTH = 13, /* Processing ADISC list */
321 LPFC_VPORT_READY = 32,
2e0fef85
JS		 322};
323
324enum hba_state {
325 LPFC_LINK_UNKNOWN = 0, /* HBA state is unknown */
326 LPFC_WARM_START = 1, /* HBA state after selective reset */
327 LPFC_INIT_START = 2, /* Initial state after board reset */
328 LPFC_INIT_MBX_CMDS = 3, /* Initialize HBA with mbox commands */
329 LPFC_LINK_DOWN = 4, /* HBA initialized, link is down */
330 LPFC_LINK_UP = 5, /* Link is up - issue READ_LA */
92d7f7b0 331 LPFC_CLEAR_LA = 6, /* authentication cmplt - issue
2e0fef85 332 * CLEAR_LA */
92d7f7b0 333 LPFC_HBA_READY = 32,
2e0fef85
JS		 334 LPFC_HBA_ERROR = -1
335};
336
337struct lpfc_vport {
2e0fef85 338 struct lpfc_hba *phba;
3772a991 339 struct list_head listentry;
2e0fef85
JS		 340 uint8_t port_type;
341#define LPFC_PHYSICAL_PORT 1
342#define LPFC_NPIV_PORT 2
343#define LPFC_FABRIC_PORT 3
344 enum discovery_state port_state;
345
92d7f7b0 346 uint16_t vpi;
da0436e9 347 uint16_t vfi;
c868595d
JS		 348 uint8_t vpi_state;
349#define LPFC_VPI_REGISTERED 0x1
2e0fef85
JS		 350
351 uint32_t fc_flag; /* FC flags */
352/* Several of these flags are HBA centric and should be moved to
353 * phba->link_flag (e.g. FC_PTP, FC_PUBLIC_LOOP)
354 */
92d7f7b0
JS		 355#define FC_PT2PT 0x1 /* pt2pt with no fabric */
356#define FC_PT2PT_PLOGI 0x2 /* pt2pt initiate PLOGI */
357#define FC_DISC_TMO 0x4 /* Discovery timer running */
358#define FC_PUBLIC_LOOP 0x8 /* Public loop */
359#define FC_LBIT 0x10 /* LOGIN bit in loopinit set */
360#define FC_RSCN_MODE 0x20 /* RSCN cmd rcv'ed */
361#define FC_NLP_MORE 0x40 /* More node to process in node tbl */
362#define FC_OFFLINE_MODE 0x80 /* Interface is offline for diag */
363#define FC_FABRIC 0x100 /* We are fabric attached */
4b40c59e 364#define FC_VPORT_LOGO_RCVD 0x200 /* LOGO received on vport */
92d7f7b0 365#define FC_RSCN_DISCOVERY 0x400 /* Auth all devices after RSCN */
4b40c59e 366#define FC_LOGO_RCVD_DID_CHNG 0x800 /* FDISC on phys port detect DID chng*/
92d7f7b0
JS		 367#define FC_SCSI_SCAN_TMO 0x4000 /* scsi scan timer running */
368#define FC_ABORT_DISCOVERY 0x8000 /* we want to abort discovery */
369#define FC_NDISC_ACTIVE 0x10000 /* NPort discovery active */
370#define FC_BYPASSED_MODE 0x20000 /* NPort is in bypassed mode */
92d7f7b0
JS		 371#define FC_VPORT_NEEDS_REG_VPI 0x80000 /* Needs to have its vpi registered */
372#define FC_RSCN_DEFERRED 0x100000 /* A deferred RSCN being processed */
1c6834a7 373#define FC_VPORT_NEEDS_INIT_VPI 0x200000 /* Need to INIT_VPI before FDISC */
695a814e
JS		 374#define FC_VPORT_CVL_RCVD 0x400000 /* VLink failed due to CVL */
375#define FC_VFI_REGISTERED 0x800000 /* VFI is registered */
376#define FC_FDISC_COMPLETED 0x1000000/* FDISC completed */
92494144 377#define FC_DISC_DELAYED 0x2000000/* Delay NPort discovery */
2e0fef85 378
7ee5d43e
JS		 379 uint32_t ct_flags;
380#define FC_CT_RFF_ID 0x1 /* RFF_ID accepted by switch */
381#define FC_CT_RNN_ID 0x2 /* RNN_ID accepted by switch */
382#define FC_CT_RSNN_NN 0x4 /* RSNN_NN accepted by switch */
383#define FC_CT_RSPN_ID 0x8 /* RSPN_ID accepted by switch */
384#define FC_CT_RFT_ID 0x10 /* RFT_ID accepted by switch */
385
2e0fef85
JS		 386 struct list_head fc_nodes;
387
388 /* Keep counters for the number of entries in each list. */
389 uint16_t fc_plogi_cnt;
390 uint16_t fc_adisc_cnt;
391 uint16_t fc_reglogin_cnt;
392 uint16_t fc_prli_cnt;
393 uint16_t fc_unmap_cnt;
394 uint16_t fc_map_cnt;
395 uint16_t fc_npr_cnt;
396 uint16_t fc_unused_cnt;
397 struct serv_parm fc_sparam; /* buffer for our service parameters */
398
399 uint32_t fc_myDID; /* fibre channel S_ID */
400 uint32_t fc_prevDID; /* previous fibre channel S_ID */
92494144
JS		 401 struct lpfc_name fabric_portname;
402 struct lpfc_name fabric_nodename;
2e0fef85
JS		 403
404 int32_t stopped; /* HBA has not been restarted since last ERATT */
405 uint8_t fc_linkspeed; /* Link speed after last READ_LA */
406
a0f2d3ef
JS		 407 uint32_t num_disc_nodes; /* in addition to hba_state */
408 uint32_t gidft_inp; /* cnt of outstanding GID_FTs */
2e0fef85
JS		 409
410 uint32_t fc_nlp_cnt; /* outstanding NODELIST requests */
411 uint32_t fc_rscn_id_cnt; /* count of RSCNs payloads in list */
7f5f3d0d 412 uint32_t fc_rscn_flush; /* flag use of fc_rscn_id_list */
2e0fef85
JS		 413 struct lpfc_dmabuf *fc_rscn_id_list[FC_MAX_HOLD_RSCN];
414 struct lpfc_name fc_nodename; /* fc nodename */
415 struct lpfc_name fc_portname; /* fc portname */
416
417 struct lpfc_work_evt disc_timeout_evt;
418
419 struct timer_list fc_disctmo; /* Discovery rescue timer */
420 uint8_t fc_ns_retry; /* retries for fabric nameserver */
421 uint32_t fc_prli_sent; /* cntr for outstanding PRLIs */
422
423 spinlock_t work_port_lock;
424 uint32_t work_port_events; /* Timeout to be handled */
858c9f6c
JS		 425#define WORKER_DISC_TMO 0x1 /* vport: Discovery timeout */
426#define WORKER_ELS_TMO 0x2 /* vport: ELS timeout */
92494144 427#define WORKER_DELAYED_DISC_TMO 0x8 /* vport: delayed discovery */
858c9f6c
JS		 428
429#define WORKER_MBOX_TMO 0x100 /* hba: MBOX timeout */
430#define WORKER_HB_TMO 0x200 /* hba: Heart beat timeout */
b1c11812 431#define WORKER_FABRIC_BLOCK_TMO 0x400 /* hba: fabric block timeout */
858c9f6c
JS		 432#define WORKER_RAMP_DOWN_QUEUE 0x800 /* hba: Decrease Q depth */
433#define WORKER_RAMP_UP_QUEUE 0x1000 /* hba: Increase Q depth */
2a9bf3d0 434#define WORKER_SERVICE_TXQ 0x2000 /* hba: IOCBs on the txq */
2e0fef85 435
2e0fef85 436 struct timer_list els_tmofunc;
92494144 437 struct timer_list delayed_disc_tmo;
2e0fef85
JS		 438
439 int unreg_vpi_cmpl;
440
441 uint8_t load_flag;
442#define FC_LOADING 0x1 /* HBA in process of loading drvr */
443#define FC_UNLOADING 0x2 /* HBA in process of unloading drvr */
4258e98e 444#define FC_ALLOW_FDMI 0x4 /* port is ready for FDMI requests */
3de2a653
JS		 445 /* Vport Config Parameters */
446 uint32_t cfg_scan_down;
447 uint32_t cfg_lun_queue_depth;
448 uint32_t cfg_nodev_tmo;
449 uint32_t cfg_devloss_tmo;
450 uint32_t cfg_restrict_login;
451 uint32_t cfg_peer_port_login;
452 uint32_t cfg_fcp_class;
453 uint32_t cfg_use_adisc;
3de2a653 454 uint32_t cfg_discovery_threads;
e8b62011 455 uint32_t cfg_log_verbose;
3de2a653 456 uint32_t cfg_max_luns;
7ee5d43e 457 uint32_t cfg_enable_da_id;
977b5a0a 458 uint32_t cfg_max_scsicmpl_time;
7dc517df 459 uint32_t cfg_tgt_queue_depth;
3cb01c57 460 uint32_t cfg_first_burst_size;
3de2a653 461 uint32_t dev_loss_tmo_changed;
51ef4c26
JS		 462
463 struct fc_vport *fc_vport;
464
923e4b6a 465#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
51ef4c26
JS		 466 struct dentry *debug_disc_trc;
467 struct dentry *debug_nodelist;
bd2cdd5e
JS		 468 struct dentry *debug_nvmestat;
469 struct dentry *debug_nvmektime;
470 struct dentry *debug_cpucheck;
51ef4c26
JS		 471 struct dentry *vport_debugfs_root;
472 struct lpfc_debugfs_trc *disc_trc;
473 atomic_t disc_trc_cnt;
474#endif
ea2151b4
JS		 475 uint8_t stat_data_enabled;
476 uint8_t stat_data_blocked;
da0436e9 477 struct list_head rcv_buffer_list;
45ed1190 478 unsigned long rcv_buffer_time_stamp;
da0436e9
JS		 479 uint32_t vport_flag;
480#define STATIC_VPORT 1
aeb3c817
JS		 481#define FAWWPN_SET 2
482#define FAWWPN_PARAM_CHG 4
4258e98e
JS		 483
484 uint16_t fdmi_num_disc;
485 uint32_t fdmi_hba_mask;
486 uint32_t fdmi_port_mask;
895427bd
JS		 487
488 /* There is a single nvme instance per vport. */
489 struct nvme_fc_local_port *localport;
490 uint8_t nvmei_support; /* driver supports NVME Initiator */
491 uint32_t last_fcp_wqidx;
2e0fef85
JS		 492};
493
ed957684
JS		 494struct hbq_s {
495 uint16_t entry_count; /* Current number of HBQ slots */
a8adb832 496 uint16_t buffer_count; /* Current number of buffers posted */
ed957684
JS		 497 uint32_t next_hbqPutIdx; /* Index to next HBQ slot to use */
498 uint32_t hbqPutIdx; /* HBQ slot to use */
499 uint32_t local_hbqGetIdx; /* Local copy of Get index from Port */
51ef4c26
JS		 500 void *hbq_virt; /* Virtual ptr to this hbq */
501 struct list_head hbq_buffer_list; /* buffers assigned to this HBQ */
502 /* Callback for HBQ buffer allocation */
503 struct hbq_dmabuf *(*hbq_alloc_buffer) (struct lpfc_hba *);
504 /* Callback for HBQ buffer free */
505 void (*hbq_free_buffer) (struct lpfc_hba *,
506 struct hbq_dmabuf *);
ed957684
JS		 507};
508
51ef4c26 509/* this matches the position in the lpfc_hbq_defs array */
92d7f7b0 510#define LPFC_ELS_HBQ 0
895427bd 511#define LPFC_MAX_HBQS 1
ed957684 512
7af67051
JS		 513enum hba_temp_state {
514 HBA_NORMAL_TEMP,
515 HBA_OVER_TEMP
516};
517
db2378e0
JS		 518enum intr_type_t {
519 NONE = 0,
520 INTx,
521 MSI,
522 MSIX,
523};
524
6dd9e31c 525#define LPFC_CT_CTX_MAX 64
f1c3b0fc
JS		 526struct unsol_rcv_ct_ctx {
527 uint32_t ctxt_id;
528 uint32_t SID;
6dd9e31c
JS		 529 uint32_t valid;
530#define UNSOL_INVALID 0
531#define UNSOL_VALID 1
7851fe2c
JS		 532 uint16_t oxid;
533 uint16_t rxid;
f1c3b0fc
JS		 534};
535
76a95d75
JS		 536#define LPFC_USER_LINK_SPEED_AUTO 0 /* auto select (default)*/
537#define LPFC_USER_LINK_SPEED_1G 1 /* 1 Gigabaud */
538#define LPFC_USER_LINK_SPEED_2G 2 /* 2 Gigabaud */
539#define LPFC_USER_LINK_SPEED_4G 4 /* 4 Gigabaud */
540#define LPFC_USER_LINK_SPEED_8G 8 /* 8 Gigabaud */
541#define LPFC_USER_LINK_SPEED_10G 10 /* 10 Gigabaud */
542#define LPFC_USER_LINK_SPEED_16G 16 /* 16 Gigabaud */
d38dd52c
JS		 543#define LPFC_USER_LINK_SPEED_32G 32 /* 32 Gigabaud */
544#define LPFC_USER_LINK_SPEED_MAX LPFC_USER_LINK_SPEED_32G
545#define LPFC_USER_LINK_SPEED_BITMAP ((1ULL << LPFC_USER_LINK_SPEED_32G) | \
546 (1 << LPFC_USER_LINK_SPEED_16G) | \
76a95d75
JS		 547 (1 << LPFC_USER_LINK_SPEED_10G) | \
548 (1 << LPFC_USER_LINK_SPEED_8G) | \
549 (1 << LPFC_USER_LINK_SPEED_4G) | \
550 (1 << LPFC_USER_LINK_SPEED_2G) | \
551 (1 << LPFC_USER_LINK_SPEED_1G) | \
552 (1 << LPFC_USER_LINK_SPEED_AUTO))
d38dd52c 553#define LPFC_LINK_SPEED_STRING "0, 1, 2, 4, 8, 10, 16, 32"
76a95d75 554
7ad20aa9
JS		 555enum nemb_type {
556 nemb_mse = 1,
557 nemb_hbd
558};
559
560enum mbox_type {
561 mbox_rd = 1,
562 mbox_wr
563};
564
565enum dma_type {
566 dma_mbox = 1,
567 dma_ebuf
568};
569
570enum sta_type {
571 sta_pre_addr = 1,
572 sta_pos_addr
573};
574
575struct lpfc_mbox_ext_buf_ctx {
576 uint32_t state;
577#define LPFC_BSG_MBOX_IDLE 0
578#define LPFC_BSG_MBOX_HOST 1
579#define LPFC_BSG_MBOX_PORT 2
580#define LPFC_BSG_MBOX_DONE 3
581#define LPFC_BSG_MBOX_ABTS 4
582 enum nemb_type nembType;
583 enum mbox_type mboxType;
584 uint32_t numBuf;
585 uint32_t mbxTag;
586 uint32_t seqNum;
587 struct lpfc_dmabuf *mbx_dmabuf;
588 struct list_head ext_dmabuf_list;
589};
590
dea3101e 591struct lpfc_hba {
3772a991
JS		 592 /* SCSI interface function jump table entries */
593 int (*lpfc_new_scsi_buf)
594 (struct lpfc_vport *, int);
595 struct lpfc_scsi_buf * (*lpfc_get_scsi_buf)
19ca7609 596 (struct lpfc_hba *, struct lpfc_nodelist *);
3772a991
JS		 597 int (*lpfc_scsi_prep_dma_buf)
598 (struct lpfc_hba *, struct lpfc_scsi_buf *);
599 void (*lpfc_scsi_unprep_dma_buf)
600 (struct lpfc_hba *, struct lpfc_scsi_buf *);
601 void (*lpfc_release_scsi_buf)
602 (struct lpfc_hba *, struct lpfc_scsi_buf *);
603 void (*lpfc_rampdown_queue_depth)
604 (struct lpfc_hba *);
605 void (*lpfc_scsi_prep_cmnd)
606 (struct lpfc_vport *, struct lpfc_scsi_buf *,
607 struct lpfc_nodelist *);
acd6859b 608
3772a991
JS		 609 /* IOCB interface function jump table entries */
610 int (*__lpfc_sli_issue_iocb)
611 (struct lpfc_hba *, uint32_t,
612 struct lpfc_iocbq *, uint32_t);
613 void (*__lpfc_sli_release_iocbq)(struct lpfc_hba *,
614 struct lpfc_iocbq *);
615 int (*lpfc_hba_down_post)(struct lpfc_hba *phba);
3772a991
JS		 616 IOCB_t * (*lpfc_get_iocb_from_iocbq)
617 (struct lpfc_iocbq *);
618 void (*lpfc_scsi_cmd_iocb_cmpl)
619 (struct lpfc_hba *, struct lpfc_iocbq *, struct lpfc_iocbq *);
620
621 /* MBOX interface function jump table entries */
622 int (*lpfc_sli_issue_mbox)
623 (struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t);
acd6859b 624
3772a991
JS		 625 /* Slow-path IOCB process function jump table entries */
626 void (*lpfc_sli_handle_slow_ring_event)
627 (struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
628 uint32_t mask);
acd6859b 629
3772a991
JS		 630 /* INIT device interface function jump table entries */
631 int (*lpfc_sli_hbq_to_firmware)
632 (struct lpfc_hba *, uint32_t, struct hbq_dmabuf *);
633 int (*lpfc_sli_brdrestart)
634 (struct lpfc_hba *);
635 int (*lpfc_sli_brdready)
636 (struct lpfc_hba *, uint32_t);
637 void (*lpfc_handle_eratt)
638 (struct lpfc_hba *);
639 void (*lpfc_stop_port)
640 (struct lpfc_hba *);
84d1b006 641 int (*lpfc_hba_init_link)
6e7288d9 642 (struct lpfc_hba *, uint32_t);
84d1b006 643 int (*lpfc_hba_down_link)
6e7288d9 644 (struct lpfc_hba *, uint32_t);
7f86059a
JS		 645 int (*lpfc_selective_reset)
646 (struct lpfc_hba *);
3772a991 647
acd6859b
JS		 648 int (*lpfc_bg_scsi_prep_dma_buf)
649 (struct lpfc_hba *, struct lpfc_scsi_buf *);
650 /* Add new entries here */
651
3772a991
JS		 652 /* SLI4 specific HBA data structure */
653 struct lpfc_sli4_hba sli4_hba;
654
dea3101e 655 struct lpfc_sli sli;
3772a991
JS		 656 uint8_t pci_dev_grp; /* lpfc PCI dev group: 0x0, 0x1, 0x2,... */
657 uint32_t sli_rev; /* SLI2, SLI3, or SLI4 */
ed957684 658 uint32_t sli3_options; /* Mask of enabled SLI3 options */
34b02dcd
JS		 659#define LPFC_SLI3_HBQ_ENABLED 0x01
660#define LPFC_SLI3_NPIV_ENABLED 0x02
661#define LPFC_SLI3_VPORT_TEARDOWN 0x04
662#define LPFC_SLI3_CRP_ENABLED 0x08
81301a9b 663#define LPFC_SLI3_BG_ENABLED 0x20
da0436e9 664#define LPFC_SLI3_DSS_ENABLED 0x40
fedd3b7b
JS		 665#define LPFC_SLI4_PERFH_ENABLED 0x80
666#define LPFC_SLI4_PHWQ_ENABLED 0x100
ed957684
JS		 667 uint32_t iocb_cmd_size;
668 uint32_t iocb_rsp_size;
2e0fef85
JS		 669
670 enum hba_state link_state;
671 uint32_t link_flag; /* link state flags */
311464ec 672#define LS_LOOPBACK_MODE 0x1 /* NPort is in Loopback mode */
2e0fef85
JS		 673 /* This flag is set while issuing */
674 /* INIT_LINK mailbox command */
92d7f7b0 675#define LS_NPIV_FAB_SUPPORTED 0x2 /* Fabric supports NPIV */
1b32f6aa 676#define LS_IGNORE_ERATT 0x4 /* intr handler should ignore ERATT */
2e0fef85 677
9399627f
JS		 678 uint32_t hba_flag; /* hba generic flags */
679#define HBA_ERATT_HANDLED 0x1 /* This flag is set when eratt handled */
da0436e9 680#define DEFER_ERATT 0x2 /* Deferred error attention in progress */
76a95d75 681#define HBA_FCOE_MODE 0x4 /* HBA function in FCoE Mode */
45ed1190 682#define HBA_SP_QUEUE_EVT 0x8 /* Slow-path qevt posted to worker thread*/
da0436e9
JS		 683#define HBA_POST_RECEIVE_BUFFER 0x10 /* Rcv buffers need to be posted */
684#define FCP_XRI_ABORT_EVENT 0x20
685#define ELS_XRI_ABORT_EVENT 0x40
686#define ASYNC_EVENT 0x80
a0c87cbd 687#define LINK_DISABLED 0x100 /* Link disabled by user */
a93ff37a
JS		 688#define FCF_TS_INPROG 0x200 /* FCF table scan in progress */
689#define FCF_RR_INPROG 0x400 /* FCF roundrobin flogi in progress */
690#define HBA_FIP_SUPPORT 0x800 /* FIP support in HBA */
691#define HBA_AER_ENABLED 0x1000 /* AER enabled with HBA */
692#define HBA_DEVLOSS_TMO 0x2000 /* HBA in devloss timeout */
19ca7609 693#define HBA_RRQ_ACTIVE 0x4000 /* process the rrq active list */
4f2e66c6 694#define HBA_FCP_IOQ_FLUSH 0x8000 /* FCP I/O queues being flushed */
0293635e 695#define HBA_FW_DUMP_OP 0x10000 /* Skips fn reset before FW dump */
65791f1f 696#define HBA_RECOVERABLE_UE 0x20000 /* Firmware supports recoverable UE */
c691816e
JS		 697#define HBA_FORCED_LINK_SPEED 0x40000 /*
698 * Firmware supports Forced Link Speed
699 * capability
700 */
895427bd 701#define HBA_NVME_IOQ_FLUSH 0x80000 /* NVME IO queues flushed. */
318083ad 702#define NVME_XRI_ABORT_EVENT 0x100000
895427bd 703
45ed1190 704 uint32_t fcp_ring_in_use; /* When polling test if intr-hndlr active*/
34b02dcd
JS		 705 struct lpfc_dmabuf slim2p;
706
707 MAILBOX_t *mbox;
7a470277 708 uint32_t *mbox_ext;
7ad20aa9 709 struct lpfc_mbox_ext_buf_ctx mbox_ext_buf_ctx;
9399627f 710 uint32_t ha_copy;
34b02dcd
JS		 711 struct _PCB *pcb;
712 struct _IOCB *IOCBs;
2e0fef85 713
34b02dcd 714 struct lpfc_dmabuf hbqslimp;
2e0fef85 715
dea3101e 716 uint16_t pci_cfg_value;
717
dea3101e 718 uint8_t fc_linkspeed; /* Link speed after last READ_LA */
719
720 uint32_t fc_eventTag; /* event tag for link attention */
4d9ab994 721 uint32_t link_events;
dea3101e 722
dea3101e 723 /* These fields used to be binfo */
dea3101e 724 uint32_t fc_pref_DID; /* preferred D_ID */
92d7f7b0 725 uint8_t fc_pref_ALPA; /* preferred AL_PA */
12265f68 726 uint32_t fc_edtovResol; /* E_D_TOV timer resolution */
dea3101e 727 uint32_t fc_edtov; /* E_D_TOV timer value */
728 uint32_t fc_arbtov; /* ARB_TOV timer value */
729 uint32_t fc_ratov; /* R_A_TOV timer value */
730 uint32_t fc_rttov; /* R_T_TOV timer value */
731 uint32_t fc_altov; /* AL_TOV timer value */
732 uint32_t fc_crtov; /* C_R_TOV timer value */
733 uint32_t fc_citov; /* C_I_TOV timer value */
dea3101e 734
dea3101e 735 struct serv_parm fc_fabparam; /* fabric service parameters buffer */
736 uint8_t alpa_map[128]; /* AL_PA map from READ_LA */
737
dea3101e 738 uint32_t lmt;
dea3101e 739
740 uint32_t fc_topology; /* link topology, from LINK INIT */
e74c03c8 741 uint32_t fc_topology_changed; /* link topology, from LINK INIT */
dea3101e 742
743 struct lpfc_stats fc_stat;
744
dea3101e 745 struct lpfc_nodelist fc_fcpnodev; /* nodelist entry for no device */
746 uint32_t nport_event_cnt; /* timestamp for nlplist entry */
747
2e0fef85
JS		 748 uint8_t wwnn[8];
749 uint8_t wwpn[8];
dea3101e 750 uint32_t RandomData[7];
7bdedb34 751 uint8_t fcp_embed_io;
895427bd
JS		 752 uint8_t nvme_support; /* Firmware supports NVME */
753 uint8_t nvmet_support; /* driver supports NVMET */
f358dd0c 754#define LPFC_NVMET_MAX_PORTS 32
7bdedb34 755 uint8_t mds_diags_support;
dea3101e 756
3de2a653 757 /* HBA Config Parameters */
dea3101e 758 uint32_t cfg_ack0;
78b2d852 759 uint32_t cfg_enable_npiv;
19ca7609 760 uint32_t cfg_enable_rrq;
dea3101e 761 uint32_t cfg_topology;
dea3101e 762 uint32_t cfg_link_speed;
7d791df7
JS		 763#define LPFC_FCF_FOV 1 /* Fast fcf failover */
764#define LPFC_FCF_PRIORITY 2 /* Priority fcf failover */
765 uint32_t cfg_fcf_failover_policy;
49aa143d 766 uint32_t cfg_fcp_io_sched;
a6571c6e 767 uint32_t cfg_fcp2_no_tgt_reset;
dea3101e 768 uint32_t cfg_cr_delay;
769 uint32_t cfg_cr_count;
cf5bf97e 770 uint32_t cfg_multi_ring_support;
a4bc3379
JS		 771 uint32_t cfg_multi_ring_rctl;
772 uint32_t cfg_multi_ring_type;
875fbdfe
JSEC		 773 uint32_t cfg_poll;
774 uint32_t cfg_poll_tmo;
0c411222 775 uint32_t cfg_task_mgmt_tmo;
4ff43246 776 uint32_t cfg_use_msi;
da0436e9 777 uint32_t cfg_fcp_imax;
7bb03bbf 778 uint32_t cfg_fcp_cpu_map;
67d12733 779 uint32_t cfg_fcp_io_channel;
f358dd0c 780 uint32_t cfg_suppress_rsp;
895427bd
JS		 781 uint32_t cfg_nvme_oas;
782 uint32_t cfg_nvme_io_channel;
2d7dbc4c 783 uint32_t cfg_nvmet_mrq;
f358dd0c 784 uint32_t cfg_enable_nvmet;
895427bd 785 uint32_t cfg_nvme_enable_fb;
2d7dbc4c 786 uint32_t cfg_nvmet_fb_size;
96f7077f 787 uint32_t cfg_total_seg_cnt;
dea3101e 788 uint32_t cfg_sg_seg_cnt;
4d4c4a4a 789 uint32_t cfg_nvme_seg_cnt;
dea3101e 790 uint32_t cfg_sg_dma_buf_size;
352e5fd1
JS		 791 uint64_t cfg_soft_wwnn;
792 uint64_t cfg_soft_wwpn;
3de2a653 793 uint32_t cfg_hba_queue_depth;
13815c83
JS		 794 uint32_t cfg_enable_hba_reset;
795 uint32_t cfg_enable_hba_heartbeat;
1ba981fd
JS		 796 uint32_t cfg_fof;
797 uint32_t cfg_EnableXLane;
798 uint8_t cfg_oas_tgt_wwpn[8];
799 uint8_t cfg_oas_vpt_wwpn[8];
800 uint32_t cfg_oas_lun_state;
801#define OAS_LUN_ENABLE 1
802#define OAS_LUN_DISABLE 0
803 uint32_t cfg_oas_lun_status;
804#define OAS_LUN_STATUS_EXISTS 0x01
805 uint32_t cfg_oas_flags;
806#define OAS_FIND_ANY_VPORT 0x01
807#define OAS_FIND_ANY_TARGET 0x02
808#define OAS_LUN_VALID 0x04
c92c841c 809 uint32_t cfg_oas_priority;
1ba981fd 810 uint32_t cfg_XLanePriority;
81301a9b 811 uint32_t cfg_enable_bg;
b3b98b74
JS		 812 uint32_t cfg_prot_mask;
813 uint32_t cfg_prot_guard;
7a470277 814 uint32_t cfg_hostmem_hgp;
da0436e9 815 uint32_t cfg_log_verbose;
0d878419 816 uint32_t cfg_aer_support;
912e3acd 817 uint32_t cfg_sriov_nr_virtfn;
c71ab861 818 uint32_t cfg_request_firmware_upgrade;
2a9bf3d0 819 uint32_t cfg_iocb_cnt;
84d1b006 820 uint32_t cfg_suppress_link_up;
cff261f6 821 uint32_t cfg_rrq_xri_bitmap_sz;
8eb8b960 822 uint32_t cfg_delay_discovery;
12247e81 823 uint32_t cfg_sli_mode;
e40a02c1
JS		 824#define LPFC_INITIALIZE_LINK 0 /* do normal init_link mbox */
825#define LPFC_DELAY_INIT_LINK 1 /* layered driver hold off */
826#define LPFC_DELAY_INIT_LINK_INDEFINITELY 2 /* wait, manual intervention */
ab56dc2e 827 uint32_t cfg_enable_dss;
4258e98e
JS		 828 uint32_t cfg_fdmi_on;
829#define LPFC_FDMI_NO_SUPPORT 0 /* FDMI not supported */
830#define LPFC_FDMI_SUPPORT 1 /* FDMI supported? */
4258e98e 831 uint32_t cfg_enable_SmartSAN;
7bdedb34 832 uint32_t cfg_enable_mds_diags;
895427bd
JS		 833 uint32_t cfg_enable_fc4_type;
834 uint32_t cfg_xri_split;
835#define LPFC_ENABLE_FCP 1
836#define LPFC_ENABLE_NVME 2
837#define LPFC_ENABLE_BOTH 3
838 uint32_t io_channel_irqs; /* number of irqs for io channels */
f358dd0c 839 struct nvmet_fc_target_port *targetport;
dea3101e 840 lpfc_vpd_t vpd; /* vital product data */
841
dea3101e 842 struct pci_dev *pcidev;
843 struct list_head work_list;
844 uint32_t work_ha; /* Host Attention Bits for WT */
845 uint32_t work_ha_mask; /* HA Bits owned by WT */
846 uint32_t work_hs; /* HS stored in case of ERRAT */
847 uint32_t work_status[2]; /* Extra status from SLIM */
dea3101e 848
5e9d9b82 849 wait_queue_head_t work_waitq;
dea3101e 850 struct task_struct *worker_thread;
d7c255b2 851 unsigned long data_flags;
dea3101e 852
3163f725 853 uint32_t hbq_in_use; /* HBQs in use flag */
ed957684 854 uint32_t hbq_count; /* Count of configured HBQs */
92d7f7b0 855 struct hbq_s hbqs[LPFC_MAX_HBQS]; /* local copy of hbq indicies */
ed957684 856
895427bd
JS		 857 atomic_t fcp_qidx; /* next FCP WQ (RR Policy) */
858 atomic_t nvme_qidx; /* next NVME WQ (RR Policy) */
8fa38513 859
115a4124
JS		 860 phys_addr_t pci_bar0_map; /* Physical address for PCI BAR0 */
861 phys_addr_t pci_bar1_map; /* Physical address for PCI BAR1 */
862 phys_addr_t pci_bar2_map; /* Physical address for PCI BAR2 */
dea3101e 863 void __iomem *slim_memmap_p; /* Kernel memory mapped address for
864 PCI BAR0 */
865 void __iomem *ctrl_regs_memmap_p;/* Kernel memory mapped address for
866 PCI BAR2 */
867
962bc51b
JS		 868 void __iomem *pci_bar0_memmap_p; /* Kernel memory mapped address for
869 PCI BAR0 with dual-ULP support */
870 void __iomem *pci_bar2_memmap_p; /* Kernel memory mapped address for
871 PCI BAR2 with dual-ULP support */
872 void __iomem *pci_bar4_memmap_p; /* Kernel memory mapped address for
873 PCI BAR4 with dual-ULP support */
874#define PCI_64BIT_BAR0 0
875#define PCI_64BIT_BAR2 2
876#define PCI_64BIT_BAR4 4
dea3101e 877 void __iomem *MBslimaddr; /* virtual address for mbox cmds */
878 void __iomem *HAregaddr; /* virtual address for host attn reg */
879 void __iomem *CAregaddr; /* virtual address for chip attn reg */
880 void __iomem *HSregaddr; /* virtual address for host status
881 reg */
882 void __iomem *HCregaddr; /* virtual address for host ctl reg */
883
ed957684 884 struct lpfc_hgp __iomem *host_gp; /* Host side get/put pointers */
34b02dcd 885 struct lpfc_pgp *port_gp;
ed957684 886 uint32_t __iomem *hbq_put; /* Address in SLIM to HBQ put ptrs */
92d7f7b0 887 uint32_t *hbq_get; /* Host mem address of HBQ get ptrs */
ed957684 888
dea3101e 889 int brd_no; /* FC board number */
dea3101e 890 char SerialNumber[32]; /* adapter Serial Number */
891 char OptionROMVersion[32]; /* adapter BIOS / Fcode version */
892 char ModelDesc[256]; /* Model Description */
893 char ModelName[80]; /* Model Name */
894 char ProgramType[256]; /* Program Type */
895 char Port[20]; /* Port No */
896 uint8_t vpd_flag; /* VPD data flag */
897
898#define VPD_MODEL_DESC 0x1 /* valid vpd model description */
899#define VPD_MODEL_NAME 0x2 /* valid vpd model name */
900#define VPD_PROGRAM_TYPE 0x4 /* valid vpd program type */
901#define VPD_PORT 0x8 /* valid vpd port data */
902#define VPD_MASK 0xf /* mask for any vpd data */
903
352e5fd1
JS		 904 uint8_t soft_wwn_enable;
905
875fbdfe 906 struct timer_list fcp_poll_timer;
9399627f 907 struct timer_list eratt_poll;
65791f1f 908 uint32_t eratt_poll_interval;
875fbdfe 909
dea3101e 910 /*
911 * stat counters
912 */
895427bd
JS		 913 uint64_t fc4ScsiInputRequests;
914 uint64_t fc4ScsiOutputRequests;
915 uint64_t fc4ScsiControlRequests;
916 uint64_t fc4ScsiIoCmpls;
917 uint64_t fc4NvmeInputRequests;
918 uint64_t fc4NvmeOutputRequests;
919 uint64_t fc4NvmeControlRequests;
920 uint64_t fc4NvmeIoCmpls;
921 uint64_t fc4NvmeLsRequests;
922 uint64_t fc4NvmeLsCmpls;
923
81301a9b
JS		 924 uint64_t bg_guard_err_cnt;
925 uint64_t bg_apptag_err_cnt;
926 uint64_t bg_reftag_err_cnt;
dea3101e 927
dea3101e 928 /* fastpath list. */
a40fc5f0
JS		 929 spinlock_t scsi_buf_list_get_lock; /* SCSI buf alloc list lock */
930 spinlock_t scsi_buf_list_put_lock; /* SCSI buf free list lock */
931 struct list_head lpfc_scsi_buf_list_get;
932 struct list_head lpfc_scsi_buf_list_put;
dea3101e 933 uint32_t total_scsi_bufs;
895427bd
JS		 934 spinlock_t nvme_buf_list_get_lock; /* NVME buf alloc list lock */
935 spinlock_t nvme_buf_list_put_lock; /* NVME buf free list lock */
936 struct list_head lpfc_nvme_buf_list_get;
937 struct list_head lpfc_nvme_buf_list_put;
938 uint32_t total_nvme_bufs;
dea3101e 939 struct list_head lpfc_iocb_list;
940 uint32_t total_iocbq_bufs;
19ca7609 941 struct list_head active_rrq_list;
2e0fef85 942 spinlock_t hbalock;
dea3101e 943
944 /* pci_mem_pools */
895427bd 945 struct pci_pool *lpfc_sg_dma_buf_pool;
dea3101e 946 struct pci_pool *lpfc_mbuf_pool;
da0436e9
JS		 947 struct pci_pool *lpfc_hrb_pool; /* header receive buffer pool */
948 struct pci_pool *lpfc_drb_pool; /* data receive buffer pool */
3c603be9 949 struct pci_pool *lpfc_nvmet_drb_pool; /* data receive buffer pool */
8568a4d2 950 struct pci_pool *lpfc_hbq_pool; /* SLI3 hbq buffer pool */
895427bd 951 struct pci_pool *txrdy_payload_pool;
dea3101e 952 struct lpfc_dma_pool lpfc_mbuf_safety_pool;
953
954 mempool_t *mbox_mem_pool;
955 mempool_t *nlp_mem_pool;
19ca7609 956 mempool_t *rrq_pool;
cff261f6 957 mempool_t *active_rrq_pool;
f888ba3c
JSEC		 958
959 struct fc_host_statistics link_stats;
db2378e0 960 enum intr_type_t intr_type;
5b75da2f
JS		 961 uint32_t intr_mode;
962#define LPFC_INTR_ERROR 0xFFFFFFFF
2e0fef85 963 struct list_head port_list;
549e55cd
JS		 964 struct lpfc_vport *pport; /* physical lpfc_vport pointer */
965 uint16_t max_vpi; /* Maximum virtual nports */
09372820 966#define LPFC_MAX_VPI 0xFFFF /* Max number of VPI supported */
da0436e9
JS		 967 uint16_t max_vports; /*
968 * For IOV HBAs max_vpi can change
969 * after a reset. max_vports is max
970 * number of vports present. This can
971 * be greater than max_vpi.
972 */
973 uint16_t vpi_base;
974 uint16_t vfi_base;
549e55cd 975 unsigned long *vpi_bmask; /* vpi allocation table */
6d368e53
JS		 976 uint16_t *vpi_ids;
977 uint16_t vpi_count;
978 struct list_head lpfc_vpi_blk_list;
92d7f7b0
JS		 979
980 /* Data structure used by fabric iocb scheduler */
981 struct list_head fabric_iocb_list;
982 atomic_t fabric_iocb_count;
983 struct timer_list fabric_block_timer;
984 unsigned long bit_flags;
985#define FABRIC_COMANDS_BLOCKED 0
986 atomic_t num_rsrc_err;
987 atomic_t num_cmd_success;
988 unsigned long last_rsrc_error_time;
989 unsigned long last_ramp_down_time;
923e4b6a 990#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
858c9f6c
JS		 991 struct dentry *hba_debugfs_root;
992 atomic_t debugfs_vport_count;
78b2d852 993 struct dentry *debug_hbqinfo;
c95d6c6c
JS		 994 struct dentry *debug_dumpHostSlim;
995 struct dentry *debug_dumpHBASlim;
f9bb2da1
JS		 996 struct dentry *debug_dumpData; /* BlockGuard BPL */
997 struct dentry *debug_dumpDif; /* BlockGuard BPL */
998 struct dentry *debug_InjErrLBA; /* LBA to inject errors at */
4ac9b226
JS		 999 struct dentry *debug_InjErrNPortID; /* NPortID to inject errors at */
1000 struct dentry *debug_InjErrWWPN; /* WWPN to inject errors at */
f9bb2da1
JS		 1001 struct dentry *debug_writeGuard; /* inject write guard_tag errors */
1002 struct dentry *debug_writeApp; /* inject write app_tag errors */
1003 struct dentry *debug_writeRef; /* inject write ref_tag errors */
acd6859b 1004 struct dentry *debug_readGuard; /* inject read guard_tag errors */
f9bb2da1
JS		 1005 struct dentry *debug_readApp; /* inject read app_tag errors */
1006 struct dentry *debug_readRef; /* inject read ref_tag errors */
1007
bd2cdd5e
JS		 1008 struct dentry *debug_nvmeio_trc;
1009 struct lpfc_debugfs_nvmeio_trc *nvmeio_trc;
1010 atomic_t nvmeio_trc_cnt;
1011 uint32_t nvmeio_trc_size;
1012 uint32_t nvmeio_trc_output_idx;
1013
f9bb2da1
JS		 1014 /* T10 DIF error injection */
1015 uint32_t lpfc_injerr_wgrd_cnt;
1016 uint32_t lpfc_injerr_wapp_cnt;
1017 uint32_t lpfc_injerr_wref_cnt;
acd6859b 1018 uint32_t lpfc_injerr_rgrd_cnt;
f9bb2da1
JS		 1019 uint32_t lpfc_injerr_rapp_cnt;
1020 uint32_t lpfc_injerr_rref_cnt;
4ac9b226
JS		 1021 uint32_t lpfc_injerr_nportid;
1022 struct lpfc_name lpfc_injerr_wwpn;
f9bb2da1 1023 sector_t lpfc_injerr_lba;
acd6859b 1024#define LPFC_INJERR_LBA_OFF (sector_t)(-1)
f9bb2da1 1025
a58cbd52
JS		 1026 struct dentry *debug_slow_ring_trc;
1027 struct lpfc_debugfs_trc *slow_ring_trc;
1028 atomic_t slow_ring_trc_cnt;
2a622bfb
JS		 1029 /* iDiag debugfs sub-directory */
1030 struct dentry *idiag_root;
1031 struct dentry *idiag_pci_cfg;
b76f2dc9 1032 struct dentry *idiag_bar_acc;
2a622bfb 1033 struct dentry *idiag_que_info;
86a80846
JS		 1034 struct dentry *idiag_que_acc;
1035 struct dentry *idiag_drb_acc;
b76f2dc9
JS		 1036 struct dentry *idiag_ctl_acc;
1037 struct dentry *idiag_mbx_acc;
1038 struct dentry *idiag_ext_acc;
07bcd98e 1039 uint8_t lpfc_idiag_last_eq;
858c9f6c 1040#endif
bd2cdd5e 1041 uint16_t nvmeio_trc_on;
858c9f6c 1042
0ff10d46
JS		 1043 /* Used for deferred freeing of ELS data buffers */
1044 struct list_head elsbuf;
1045 int elsbuf_cnt;
1046 int elsbuf_prev_cnt;
1047
57127f15 1048 uint8_t temp_sensor_support;
858c9f6c
JS		 1049 /* Fields used for heart beat. */
1050 unsigned long last_completion_time;
bc73905a 1051 unsigned long skipped_hb;
858c9f6c
JS		 1052 struct timer_list hb_tmofunc;
1053 uint8_t hb_outstanding;
19ca7609 1054 struct timer_list rrq_tmr;
84774a4d 1055 enum hba_temp_state over_temp_state;
e47c9093
JS		 1056 /* ndlp reference management */
1057 spinlock_t ndlp_lock;
76bb24ef
JS		 1058 /*
1059 * Following bit will be set for all buffer tags which are not
1060 * associated with any HBQ.
1061 */
1062#define QUE_BUFTAG_BIT (1<<31)
1063 uint32_t buffer_tag_count;
84774a4d
JS		 1064 int wait_4_mlo_maint_flg;
1065 wait_queue_head_t wait_4_mlo_m_q;
ea2151b4
JS		 1066 /* data structure used for latency data collection */
1067#define LPFC_NO_BUCKET 0
1068#define LPFC_LINEAR_BUCKET 1
1069#define LPFC_POWER2_BUCKET 2
1070 uint8_t bucket_type;
1071 uint32_t bucket_base;
1072 uint32_t bucket_step;
1073
1074/* Maximum number of events that can be outstanding at any time*/
1075#define LPFC_MAX_EVT_COUNT 512
1076 atomic_t fast_event_count;
32b9793f
JS		 1077 uint32_t fcoe_eventtag;
1078 uint32_t fcoe_eventtag_at_fcf_scan;
80c17849
JS		 1079 uint32_t fcoe_cvl_eventtag;
1080 uint32_t fcoe_cvl_eventtag_attn;
da0436e9
JS		 1081 struct lpfc_fcf fcf;
1082 uint8_t fc_map[3];
1083 uint8_t valid_vlan;
1084 uint16_t vlan_id;
1085 struct list_head fcf_conn_rec_list;
f1c3b0fc 1086
4fede78f 1087 spinlock_t ct_ev_lock; /* synchronize access to ct_ev_waiters */
f1c3b0fc 1088 struct list_head ct_ev_waiters;
6dd9e31c 1089 struct unsol_rcv_ct_ctx ct_ctx[LPFC_CT_CTX_MAX];
f1c3b0fc 1090 uint32_t ctx_idx;
e2aed29f
JS		 1091
1092 uint8_t menlo_flag; /* menlo generic flags */
1093#define HBA_MENLO_SUPPORT 0x1 /* HBA supports menlo commands */
2a9bf3d0
JS		 1094 uint32_t iocb_cnt;
1095 uint32_t iocb_max;
d7c47992 1096 atomic_t sdev_cnt;
bc73905a
JS		 1097 uint8_t fips_spec_rev;
1098 uint8_t fips_level;
1ba981fd
JS		 1099 spinlock_t devicelock; /* lock for luns list */
1100 mempool_t *device_data_mem_pool;
1101 struct list_head luns;
310429ef
JS		 1102#define LPFC_TRANSGRESSION_HIGH_TEMPERATURE 0x0080
1103#define LPFC_TRANSGRESSION_LOW_TEMPERATURE 0x0040
1104#define LPFC_TRANSGRESSION_HIGH_VOLTAGE 0x0020
1105#define LPFC_TRANSGRESSION_LOW_VOLTAGE 0x0010
1106#define LPFC_TRANSGRESSION_HIGH_TXBIAS 0x0008
1107#define LPFC_TRANSGRESSION_LOW_TXBIAS 0x0004
1108#define LPFC_TRANSGRESSION_HIGH_TXPOWER 0x0002
1109#define LPFC_TRANSGRESSION_LOW_TXPOWER 0x0001
1110#define LPFC_TRANSGRESSION_HIGH_RXPOWER 0x8000
1111#define LPFC_TRANSGRESSION_LOW_RXPOWER 0x4000
1112 uint16_t sfp_alarm;
1113 uint16_t sfp_warning;
bd2cdd5e
JS		 1114
1115#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
1116#define LPFC_CHECK_CPU_CNT 32
1117 uint32_t cpucheck_rcv_io[LPFC_CHECK_CPU_CNT];
1118 uint32_t cpucheck_xmt_io[LPFC_CHECK_CPU_CNT];
1119 uint32_t cpucheck_cmpl_io[LPFC_CHECK_CPU_CNT];
1120 uint32_t cpucheck_ccmpl_io[LPFC_CHECK_CPU_CNT];
1121 uint16_t cpucheck_on;
1122#define LPFC_CHECK_OFF 0
1123#define LPFC_CHECK_NVME_IO 1
f358dd0c
JS		 1124#define LPFC_CHECK_NVMET_RCV 2
1125#define LPFC_CHECK_NVMET_IO 4
bd2cdd5e
JS		 1126 uint16_t ktime_on;
1127 uint64_t ktime_data_samples;
1128 uint64_t ktime_status_samples;
1129 uint64_t ktime_last_cmd;
1130 uint64_t ktime_seg1_total;
1131 uint64_t ktime_seg1_min;
1132 uint64_t ktime_seg1_max;
1133 uint64_t ktime_seg2_total;
1134 uint64_t ktime_seg2_min;
1135 uint64_t ktime_seg2_max;
1136 uint64_t ktime_seg3_total;
1137 uint64_t ktime_seg3_min;
1138 uint64_t ktime_seg3_max;
1139 uint64_t ktime_seg4_total;
1140 uint64_t ktime_seg4_min;
1141 uint64_t ktime_seg4_max;
1142 uint64_t ktime_seg5_total;
1143 uint64_t ktime_seg5_min;
1144 uint64_t ktime_seg5_max;
1145 uint64_t ktime_seg6_total;
1146 uint64_t ktime_seg6_min;
1147 uint64_t ktime_seg6_max;
1148 uint64_t ktime_seg7_total;
1149 uint64_t ktime_seg7_min;
1150 uint64_t ktime_seg7_max;
1151 uint64_t ktime_seg8_total;
1152 uint64_t ktime_seg8_min;
1153 uint64_t ktime_seg8_max;
1154 uint64_t ktime_seg9_total;
1155 uint64_t ktime_seg9_min;
1156 uint64_t ktime_seg9_max;
1157 uint64_t ktime_seg10_total;
1158 uint64_t ktime_seg10_min;
1159 uint64_t ktime_seg10_max;
1160#endif
dea3101e 1161};
1162
2e0fef85
JS		 1163static inline struct Scsi_Host *
1164lpfc_shost_from_vport(struct lpfc_vport *vport)
1165{
1166 return container_of((void *) vport, struct Scsi_Host, hostdata[0]);
1167}
1168
5b8bd0c9 1169static inline void
2e0fef85
JS		 1170lpfc_set_loopback_flag(struct lpfc_hba *phba)
1171{
5b8bd0c9 1172 if (phba->cfg_topology == FLAGS_LOCAL_LB)
2e0fef85 1173 phba->link_flag |= LS_LOOPBACK_MODE;
5b8bd0c9 1174 else
2e0fef85
JS		 1175 phba->link_flag &= ~LS_LOOPBACK_MODE;
1176}
1177
1178static inline int
1179lpfc_is_link_up(struct lpfc_hba *phba)
1180{
1181 return phba->link_state == LPFC_LINK_UP ||
92d7f7b0
JS		 1182 phba->link_state == LPFC_CLEAR_LA ||
1183 phba->link_state == LPFC_HBA_READY;
5b8bd0c9 1184}
dea3101e 1185
5e9d9b82
JS		 1186static inline void
1187lpfc_worker_wake_up(struct lpfc_hba *phba)
1188{
1189 /* Set the lpfc data pending flag */
1190 set_bit(LPFC_DATA_READY, &phba->data_flags);
1191
1192 /* Wake up worker thread */
1193 wake_up(&phba->work_waitq);
1194 return;
1195}
1196
9940b97b
JS		 1197static inline int
1198lpfc_readl(void __iomem *addr, uint32_t *data)
1199{
1200 uint32_t temp;
1201 temp = readl(addr);
1202 if (temp == 0xffffffff)
1203 return -EIO;
1204 *data = temp;
1205 return 0;
1206}
1207
1208static inline int
9399627f
JS		 1209lpfc_sli_read_hs(struct lpfc_hba *phba)
1210{
1211 /*
1212 * There was a link/board error. Read the status register to retrieve
1213 * the error event and process it.
1214 */
1215 phba->sli.slistat.err_attn_event++;
1216
9940b97b
JS		 1217 /* Save status info and check for unplug error */
1218 if (lpfc_readl(phba->HSregaddr, &phba->work_hs) ||
1219 lpfc_readl(phba->MBslimaddr + 0xa8, &phba->work_status[0]) ||
1220 lpfc_readl(phba->MBslimaddr + 0xac, &phba->work_status[1])) {
1221 return -EIO;
1222 }
9399627f
JS		 1223
1224 /* Clear chip Host Attention error bit */
1225 writel(HA_ERATT, phba->HAregaddr);
1226 readl(phba->HAregaddr); /* flush */
1227 phba->pport->stopped = 1;
1228
9940b97b 1229 return 0;
9399627f 1230}
895427bd
JS		 1231
1232static inline struct lpfc_sli_ring *
1233lpfc_phba_elsring(struct lpfc_hba *phba)
1234{
0c9c6a75
JS		 1235 if (phba->sli_rev == LPFC_SLI_REV4) {
1236 if (phba->sli4_hba.els_wq)
1237 return phba->sli4_hba.els_wq->pring;
1238 else
1239 return NULL;
1240 }
895427bd
JS		 1241 return &phba->sli.sli3_ring[LPFC_ELS_RING];
1242}
Linux 6.x block layer and io_uring tree(s)