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scsi: lpfc: NVME Initiator: bind to nvme_fc api
[linux-2.6-block.git] / drivers / scsi / lpfc / lpfc.h
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dea3101e 1/*******************************************************************
2 * This file is part of the Emulex Linux Device Driver for *
c44ce173 3 * Fibre Channel Host Bus Adapters. *
50611577 4 * Copyright (C) 2004-2016 Emulex. All rights reserved. *
c44ce173 5 * EMULEX and SLI are trademarks of Emulex. *
dea3101e 6 * www.emulex.com *
c44ce173 7 * Portions Copyright (C) 2004-2005 Christoph Hellwig *
dea3101e 8 * *
9 * This program is free software; you can redistribute it and/or *
c44ce173
JSEC		 10 * modify it under the terms of version 2 of the GNU General *
11 * Public License as published by the Free Software Foundation. *
12 * This program is distributed in the hope that it will be useful. *
13 * ALL EXPRESS OR IMPLIED CONDITIONS, REPRESENTATIONS AND *
14 * WARRANTIES, INCLUDING ANY IMPLIED WARRANTY OF MERCHANTABILITY, *
15 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT, ARE *
16 * DISCLAIMED, EXCEPT TO THE EXTENT THAT SUCH DISCLAIMERS ARE HELD *
17 * TO BE LEGALLY INVALID. See the GNU General Public License for *
18 * more details, a copy of which can be found in the file COPYING *
19 * included with this package. *
dea3101e 20 *******************************************************************/
21
2e0fef85 22#include <scsi/scsi_host.h>
895427bd 23#include <linux/ktime.h>
88a2cfbb
JS		 24
25#if defined(CONFIG_DEBUG_FS) && !defined(CONFIG_SCSI_LPFC_DEBUG_FS)
26#define CONFIG_SCSI_LPFC_DEBUG_FS
27#endif
28
dea3101e 29struct lpfc_sli2_slim;
30
5402a315
JS		 31#define ELX_MODEL_NAME_SIZE 80
32
3772a991
JS		 33#define LPFC_PCI_DEV_LP 0x1
34#define LPFC_PCI_DEV_OC 0x2
35
36#define LPFC_SLI_REV2 2
37#define LPFC_SLI_REV3 3
38#define LPFC_SLI_REV4 4
39
97eab634 40#define LPFC_MAX_TARGET 4096 /* max number of targets supported */
e17da18e
JS		 41#define LPFC_MAX_DISC_THREADS 64 /* max outstanding discovery els
42 requests */
43#define LPFC_MAX_NS_RETRY 3 /* Number of retry attempts to contact
44 the NameServer before giving up. */
445cf4f4 45#define LPFC_CMD_PER_LUN 3 /* max outstanding cmds per lun */
81301a9b 46#define LPFC_DEFAULT_SG_SEG_CNT 64 /* sg element count per scsi cmnd */
e2aed29f
JS		 47#define LPFC_DEFAULT_MENLO_SG_SEG_CNT 128 /* sg element count per scsi
48 cmnd for menlo needs nearly twice as for firmware
49 downloads using bsg */
96f7077f
JS		 50
51#define LPFC_MIN_SG_SLI4_BUF_SZ 0x800 /* based on LPFC_DEFAULT_SG_SEG_CNT */
52#define LPFC_MAX_SG_SLI4_SEG_CNT_DIF 128 /* sg element count per scsi cmnd */
53#define LPFC_MAX_SG_SEG_CNT_DIF 512 /* sg element count per scsi cmnd */
81301a9b 54#define LPFC_MAX_SG_SEG_CNT 4096 /* sg element count per scsi cmnd */
09294d46
JS		 55#define LPFC_MAX_SGL_SEG_CNT 512 /* SGL element count per scsi cmnd */
56#define LPFC_MAX_BPL_SEG_CNT 4096 /* BPL element count per scsi cmnd */
895427bd 57#define LPFC_MIN_NVME_SEG_CNT 254
09294d46 58
0558056c 59#define LPFC_MAX_SGE_SIZE 0x80000000 /* Maximum data allowed in a SGE */
dea3101e 60#define LPFC_IOCB_LIST_CNT 2250 /* list of IOCBs for fast-path usage. */
445cf4f4 61#define LPFC_Q_RAMP_UP_INTERVAL 120 /* lun q_depth ramp up interval */
495a714c 62#define LPFC_VNAME_LEN 100 /* vport symbolic name length */
977b5a0a
JS		 63#define LPFC_TGTQ_INTERVAL 40000 /* Min amount of time between tgt
64 queue depth change in millisecs */
65#define LPFC_TGTQ_RAMPUP_PCENT 5 /* Target queue rampup in percentage */
7dc517df 66#define LPFC_MIN_TGT_QDEPTH 10
977b5a0a 67#define LPFC_MAX_TGT_QDEPTH 0xFFFF
dea3101e 68
ea2151b4
JS		 69#define LPFC_MAX_BUCKET_COUNT 20 /* Maximum no. of buckets for stat data
70 collection. */
92d7f7b0
JS		 71/*
72 * Following time intervals are used of adjusting SCSI device
73 * queue depths when there are driver resource error or Firmware
74 * resource error.
75 */
256ec0d0
JS		 76/* 1 Second */
77#define QUEUE_RAMP_DOWN_INTERVAL (msecs_to_jiffies(1000 * 1))
92d7f7b0
JS		 78
79/* Number of exchanges reserved for discovery to complete */
80#define LPFC_DISC_IOCB_BUFF_COUNT 20
81
858c9f6c 82#define LPFC_HB_MBOX_INTERVAL 5 /* Heart beat interval in seconds. */
311464ec 83#define LPFC_HB_MBOX_TIMEOUT 30 /* Heart beat timeout in seconds. */
858c9f6c 84
ba20c853
JS		 85#define LPFC_LOOK_AHEAD_OFF 0 /* Look ahead logic is turned off */
86
9399627f
JS		 87/* Error Attention event polling interval */
88#define LPFC_ERATT_POLL_INTERVAL 5 /* EATT poll interval in seconds */
89
dea3101e 90/* Define macros for 64 bit support */
91#define putPaddrLow(addr) ((uint32_t) (0xffffffff & (u64)(addr)))
92#define putPaddrHigh(addr) ((uint32_t) (0xffffffff & (((u64)(addr))>>32)))
93#define getPaddr(high, low) ((dma_addr_t)( \
94 (( (u64)(high)<<16 ) << 16)|( (u64)(low))))
95/* Provide maximum configuration definitions. */
96#define LPFC_DRVR_TIMEOUT 16 /* driver iocb timeout value in sec */
dea3101e 97#define FC_MAX_ADPTMSG 64
98
99#define MAX_HBAEVT 32
100
9399627f
JS		 101/* Number of MSI-X vectors the driver uses */
102#define LPFC_MSIX_VECTORS 2
103
5e9d9b82
JS		 104/* lpfc wait event data ready flag */
105#define LPFC_DATA_READY (1<<0)
106
809c7536
JS		 107/* queue dump line buffer size */
108#define LPFC_LBUF_SZ 128
109
618a5230
JS		 110/* mailbox system shutdown options */
111#define LPFC_MBX_NO_WAIT 0
112#define LPFC_MBX_WAIT 1
113
875fbdfe
JSEC		 114enum lpfc_polling_flags {
115 ENABLE_FCP_RING_POLLING = 0x1,
116 DISABLE_FCP_RING_INT = 0x2
117};
118
895427bd
JS		 119struct perf_prof {
120 uint16_t cmd_cpu[40];
121 uint16_t rsp_cpu[40];
122 uint16_t qh_cpu[40];
123 uint16_t wqidx[40];
124};
125
01649561
JS		 126/*
127 * Provide for FC4 TYPE x28 - NVME. The
128 * bit mask for FCP and NVME is 0x8 identically
129 * because they are 32 bit positions distance.
130 */
a0f2d3ef
JS		 131#define LPFC_FC4_TYPE_BITMASK 0x00000100
132
dea3101e 133/* Provide DMA memory definitions the driver uses per port instance. */
134struct lpfc_dmabuf {
135 struct list_head list;
136 void *virt; /* virtual address ptr */
137 dma_addr_t phys; /* mapped address */
76bb24ef 138 uint32_t buffer_tag; /* used for tagged queue ring */
dea3101e 139};
140
141struct lpfc_dma_pool {
142 struct lpfc_dmabuf *elements;
143 uint32_t max_count;
144 uint32_t current_count;
145};
146
ed957684 147struct hbq_dmabuf {
da0436e9 148 struct lpfc_dmabuf hbuf;
ed957684 149 struct lpfc_dmabuf dbuf;
895427bd
JS		 150 uint16_t total_size;
151 uint16_t bytes_recv;
ed957684 152 uint32_t tag;
4d9ab994 153 struct lpfc_cq_event cq_event;
45ed1190 154 unsigned long time_stamp;
895427bd
JS		 155 void *context;
156};
157
158struct rqb_dmabuf {
159 struct lpfc_dmabuf hbuf;
160 struct lpfc_dmabuf dbuf;
161 uint16_t total_size;
162 uint16_t bytes_recv;
163 void *context;
164 struct lpfc_iocbq *iocbq;
165 struct lpfc_sglq *sglq;
166 struct lpfc_queue *hrq; /* ptr to associated Header RQ */
167 struct lpfc_queue *drq; /* ptr to associated Data RQ */
ed957684
JS		 168};
169
dea3101e 170/* Priority bit. Set value to exceed low water mark in lpfc_mem. */
171#define MEM_PRI 0x100
172
173
174/****************************************************************************/
175/* Device VPD save area */
176/****************************************************************************/
177typedef struct lpfc_vpd {
178 uint32_t status; /* vpd status value */
179 uint32_t length; /* number of bytes actually returned */
180 struct {
181 uint32_t rsvd1; /* Revision numbers */
182 uint32_t biuRev;
183 uint32_t smRev;
184 uint32_t smFwRev;
185 uint32_t endecRev;
186 uint16_t rBit;
187 uint8_t fcphHigh;
188 uint8_t fcphLow;
189 uint8_t feaLevelHigh;
190 uint8_t feaLevelLow;
191 uint32_t postKernRev;
192 uint32_t opFwRev;
193 uint8_t opFwName[16];
194 uint32_t sli1FwRev;
195 uint8_t sli1FwName[16];
196 uint32_t sli2FwRev;
197 uint8_t sli2FwName[16];
198 } rev;
92d7f7b0
JS		 199 struct {
200#ifdef __BIG_ENDIAN_BITFIELD
da0436e9
JS		 201 uint32_t rsvd3 :19; /* Reserved */
202 uint32_t cdss : 1; /* Configure Data Security SLI */
203 uint32_t rsvd2 : 3; /* Reserved */
204 uint32_t cbg : 1; /* Configure BlockGuard */
92d7f7b0
JS		 205 uint32_t cmv : 1; /* Configure Max VPIs */
206 uint32_t ccrp : 1; /* Config Command Ring Polling */
207 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
208 uint32_t chbs : 1; /* Cofigure Host Backing store */
209 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
210 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
211 uint32_t cmx : 1; /* Configure Max XRIs */
212 uint32_t cmr : 1; /* Configure Max RPIs */
213#else /* __LITTLE_ENDIAN */
214 uint32_t cmr : 1; /* Configure Max RPIs */
215 uint32_t cmx : 1; /* Configure Max XRIs */
216 uint32_t cerbm : 1; /* Configure Enhanced Receive Buf Mgmt */
217 uint32_t cinb : 1; /* Enable Interrupt Notification Block */
218 uint32_t chbs : 1; /* Cofigure Host Backing store */
219 uint32_t csah : 1; /* Configure Synchronous Abort Handling */
220 uint32_t ccrp : 1; /* Config Command Ring Polling */
221 uint32_t cmv : 1; /* Configure Max VPIs */
da0436e9
JS		 222 uint32_t cbg : 1; /* Configure BlockGuard */
223 uint32_t rsvd2 : 3; /* Reserved */
224 uint32_t cdss : 1; /* Configure Data Security SLI */
225 uint32_t rsvd3 :19; /* Reserved */
92d7f7b0
JS		 226#endif
227 } sli3Feat;
dea3101e 228} lpfc_vpd_t;
229
230struct lpfc_scsi_buf;
231
232
233/*
234 * lpfc stat counters
235 */
236struct lpfc_stats {
237 /* Statistics for ELS commands */
238 uint32_t elsLogiCol;
239 uint32_t elsRetryExceeded;
240 uint32_t elsXmitRetry;
241 uint32_t elsDelayRetry;
242 uint32_t elsRcvDrop;
243 uint32_t elsRcvFrame;
244 uint32_t elsRcvRSCN;
245 uint32_t elsRcvRNID;
246 uint32_t elsRcvFARP;
247 uint32_t elsRcvFARPR;
248 uint32_t elsRcvFLOGI;
249 uint32_t elsRcvPLOGI;
250 uint32_t elsRcvADISC;
251 uint32_t elsRcvPDISC;
252 uint32_t elsRcvFAN;
253 uint32_t elsRcvLOGO;
254 uint32_t elsRcvPRLO;
255 uint32_t elsRcvPRLI;
7bb3b137 256 uint32_t elsRcvLIRR;
12265f68 257 uint32_t elsRcvRLS;
7bb3b137
JW		 258 uint32_t elsRcvRPS;
259 uint32_t elsRcvRPL;
5ffc266e 260 uint32_t elsRcvRRQ;
12265f68
JS		 261 uint32_t elsRcvRTV;
262 uint32_t elsRcvECHO;
8b017a30 263 uint32_t elsRcvLCB;
86478875 264 uint32_t elsRcvRDP;
dea3101e 265 uint32_t elsXmitFLOGI;
92d7f7b0 266 uint32_t elsXmitFDISC;
dea3101e 267 uint32_t elsXmitPLOGI;
268 uint32_t elsXmitPRLI;
269 uint32_t elsXmitADISC;
270 uint32_t elsXmitLOGO;
271 uint32_t elsXmitSCR;
272 uint32_t elsXmitRNID;
273 uint32_t elsXmitFARP;
274 uint32_t elsXmitFARPR;
275 uint32_t elsXmitACC;
276 uint32_t elsXmitLSRJT;
277
278 uint32_t frameRcvBcast;
279 uint32_t frameRcvMulti;
280 uint32_t strayXmitCmpl;
281 uint32_t frameXmitDelay;
282 uint32_t xriCmdCmpl;
283 uint32_t xriStatErr;
284 uint32_t LinkUp;
285 uint32_t LinkDown;
286 uint32_t LinkMultiEvent;
287 uint32_t NoRcvBuf;
288 uint32_t fcpCmd;
289 uint32_t fcpCmpl;
290 uint32_t fcpRspErr;
291 uint32_t fcpRemoteStop;
292 uint32_t fcpPortRjt;
293 uint32_t fcpPortBusy;
294 uint32_t fcpError;
295 uint32_t fcpLocalErr;
296};
297
2e0fef85
JS		 298struct lpfc_hba;
299
92d7f7b0 300
2e0fef85 301enum discovery_state {
92d7f7b0
JS		 302 LPFC_VPORT_UNKNOWN = 0, /* vport state is unknown */
303 LPFC_VPORT_FAILED = 1, /* vport has failed */
304 LPFC_LOCAL_CFG_LINK = 6, /* local NPORT Id configured */
305 LPFC_FLOGI = 7, /* FLOGI sent to Fabric */
306 LPFC_FDISC = 8, /* FDISC sent for vport */
307 LPFC_FABRIC_CFG_LINK = 9, /* Fabric assigned NPORT Id
308 * configured */
309 LPFC_NS_REG = 10, /* Register with NameServer */
310 LPFC_NS_QRY = 11, /* Query NameServer for NPort ID list */
311 LPFC_BUILD_DISC_LIST = 12, /* Build ADISC and PLOGI lists for
312 * device authentication / discovery */
313 LPFC_DISC_AUTH = 13, /* Processing ADISC list */
314 LPFC_VPORT_READY = 32,
2e0fef85
JS		 315};
316
317enum hba_state {
318 LPFC_LINK_UNKNOWN = 0, /* HBA state is unknown */
319 LPFC_WARM_START = 1, /* HBA state after selective reset */
320 LPFC_INIT_START = 2, /* Initial state after board reset */
321 LPFC_INIT_MBX_CMDS = 3, /* Initialize HBA with mbox commands */
322 LPFC_LINK_DOWN = 4, /* HBA initialized, link is down */
323 LPFC_LINK_UP = 5, /* Link is up - issue READ_LA */
92d7f7b0 324 LPFC_CLEAR_LA = 6, /* authentication cmplt - issue
2e0fef85 325 * CLEAR_LA */
92d7f7b0 326 LPFC_HBA_READY = 32,
2e0fef85
JS		 327 LPFC_HBA_ERROR = -1
328};
329
330struct lpfc_vport {
2e0fef85 331 struct lpfc_hba *phba;
3772a991 332 struct list_head listentry;
2e0fef85
JS		 333 uint8_t port_type;
334#define LPFC_PHYSICAL_PORT 1
335#define LPFC_NPIV_PORT 2
336#define LPFC_FABRIC_PORT 3
337 enum discovery_state port_state;
338
92d7f7b0 339 uint16_t vpi;
da0436e9 340 uint16_t vfi;
c868595d
JS		 341 uint8_t vpi_state;
342#define LPFC_VPI_REGISTERED 0x1
2e0fef85
JS		 343
344 uint32_t fc_flag; /* FC flags */
345/* Several of these flags are HBA centric and should be moved to
346 * phba->link_flag (e.g. FC_PTP, FC_PUBLIC_LOOP)
347 */
92d7f7b0
JS		 348#define FC_PT2PT 0x1 /* pt2pt with no fabric */
349#define FC_PT2PT_PLOGI 0x2 /* pt2pt initiate PLOGI */
350#define FC_DISC_TMO 0x4 /* Discovery timer running */
351#define FC_PUBLIC_LOOP 0x8 /* Public loop */
352#define FC_LBIT 0x10 /* LOGIN bit in loopinit set */
353#define FC_RSCN_MODE 0x20 /* RSCN cmd rcv'ed */
354#define FC_NLP_MORE 0x40 /* More node to process in node tbl */
355#define FC_OFFLINE_MODE 0x80 /* Interface is offline for diag */
356#define FC_FABRIC 0x100 /* We are fabric attached */
4b40c59e 357#define FC_VPORT_LOGO_RCVD 0x200 /* LOGO received on vport */
92d7f7b0 358#define FC_RSCN_DISCOVERY 0x400 /* Auth all devices after RSCN */
4b40c59e 359#define FC_LOGO_RCVD_DID_CHNG 0x800 /* FDISC on phys port detect DID chng*/
92d7f7b0
JS		 360#define FC_SCSI_SCAN_TMO 0x4000 /* scsi scan timer running */
361#define FC_ABORT_DISCOVERY 0x8000 /* we want to abort discovery */
362#define FC_NDISC_ACTIVE 0x10000 /* NPort discovery active */
363#define FC_BYPASSED_MODE 0x20000 /* NPort is in bypassed mode */
92d7f7b0
JS		 364#define FC_VPORT_NEEDS_REG_VPI 0x80000 /* Needs to have its vpi registered */
365#define FC_RSCN_DEFERRED 0x100000 /* A deferred RSCN being processed */
1c6834a7 366#define FC_VPORT_NEEDS_INIT_VPI 0x200000 /* Need to INIT_VPI before FDISC */
695a814e
JS		 367#define FC_VPORT_CVL_RCVD 0x400000 /* VLink failed due to CVL */
368#define FC_VFI_REGISTERED 0x800000 /* VFI is registered */
369#define FC_FDISC_COMPLETED 0x1000000/* FDISC completed */
92494144 370#define FC_DISC_DELAYED 0x2000000/* Delay NPort discovery */
2e0fef85 371
7ee5d43e
JS		 372 uint32_t ct_flags;
373#define FC_CT_RFF_ID 0x1 /* RFF_ID accepted by switch */
374#define FC_CT_RNN_ID 0x2 /* RNN_ID accepted by switch */
375#define FC_CT_RSNN_NN 0x4 /* RSNN_NN accepted by switch */
376#define FC_CT_RSPN_ID 0x8 /* RSPN_ID accepted by switch */
377#define FC_CT_RFT_ID 0x10 /* RFT_ID accepted by switch */
378
2e0fef85
JS		 379 struct list_head fc_nodes;
380
381 /* Keep counters for the number of entries in each list. */
382 uint16_t fc_plogi_cnt;
383 uint16_t fc_adisc_cnt;
384 uint16_t fc_reglogin_cnt;
385 uint16_t fc_prli_cnt;
386 uint16_t fc_unmap_cnt;
387 uint16_t fc_map_cnt;
388 uint16_t fc_npr_cnt;
389 uint16_t fc_unused_cnt;
390 struct serv_parm fc_sparam; /* buffer for our service parameters */
391
392 uint32_t fc_myDID; /* fibre channel S_ID */
393 uint32_t fc_prevDID; /* previous fibre channel S_ID */
92494144
JS		 394 struct lpfc_name fabric_portname;
395 struct lpfc_name fabric_nodename;
2e0fef85
JS		 396
397 int32_t stopped; /* HBA has not been restarted since last ERATT */
398 uint8_t fc_linkspeed; /* Link speed after last READ_LA */
399
a0f2d3ef
JS		 400 uint32_t num_disc_nodes; /* in addition to hba_state */
401 uint32_t gidft_inp; /* cnt of outstanding GID_FTs */
2e0fef85
JS		 402
403 uint32_t fc_nlp_cnt; /* outstanding NODELIST requests */
404 uint32_t fc_rscn_id_cnt; /* count of RSCNs payloads in list */
7f5f3d0d 405 uint32_t fc_rscn_flush; /* flag use of fc_rscn_id_list */
2e0fef85
JS		 406 struct lpfc_dmabuf *fc_rscn_id_list[FC_MAX_HOLD_RSCN];
407 struct lpfc_name fc_nodename; /* fc nodename */
408 struct lpfc_name fc_portname; /* fc portname */
409
410 struct lpfc_work_evt disc_timeout_evt;
411
412 struct timer_list fc_disctmo; /* Discovery rescue timer */
413 uint8_t fc_ns_retry; /* retries for fabric nameserver */
414 uint32_t fc_prli_sent; /* cntr for outstanding PRLIs */
415
416 spinlock_t work_port_lock;
417 uint32_t work_port_events; /* Timeout to be handled */
858c9f6c
JS		 418#define WORKER_DISC_TMO 0x1 /* vport: Discovery timeout */
419#define WORKER_ELS_TMO 0x2 /* vport: ELS timeout */
92494144 420#define WORKER_DELAYED_DISC_TMO 0x8 /* vport: delayed discovery */
858c9f6c
JS		 421
422#define WORKER_MBOX_TMO 0x100 /* hba: MBOX timeout */
423#define WORKER_HB_TMO 0x200 /* hba: Heart beat timeout */
b1c11812 424#define WORKER_FABRIC_BLOCK_TMO 0x400 /* hba: fabric block timeout */
858c9f6c
JS		 425#define WORKER_RAMP_DOWN_QUEUE 0x800 /* hba: Decrease Q depth */
426#define WORKER_RAMP_UP_QUEUE 0x1000 /* hba: Increase Q depth */
2a9bf3d0 427#define WORKER_SERVICE_TXQ 0x2000 /* hba: IOCBs on the txq */
2e0fef85 428
2e0fef85 429 struct timer_list els_tmofunc;
92494144 430 struct timer_list delayed_disc_tmo;
2e0fef85
JS		 431
432 int unreg_vpi_cmpl;
433
434 uint8_t load_flag;
435#define FC_LOADING 0x1 /* HBA in process of loading drvr */
436#define FC_UNLOADING 0x2 /* HBA in process of unloading drvr */
4258e98e 437#define FC_ALLOW_FDMI 0x4 /* port is ready for FDMI requests */
3de2a653
JS		 438 /* Vport Config Parameters */
439 uint32_t cfg_scan_down;
440 uint32_t cfg_lun_queue_depth;
441 uint32_t cfg_nodev_tmo;
442 uint32_t cfg_devloss_tmo;
443 uint32_t cfg_restrict_login;
444 uint32_t cfg_peer_port_login;
445 uint32_t cfg_fcp_class;
446 uint32_t cfg_use_adisc;
3de2a653 447 uint32_t cfg_discovery_threads;
e8b62011 448 uint32_t cfg_log_verbose;
3de2a653 449 uint32_t cfg_max_luns;
7ee5d43e 450 uint32_t cfg_enable_da_id;
977b5a0a 451 uint32_t cfg_max_scsicmpl_time;
7dc517df 452 uint32_t cfg_tgt_queue_depth;
3cb01c57 453 uint32_t cfg_first_burst_size;
3de2a653 454 uint32_t dev_loss_tmo_changed;
51ef4c26
JS		 455
456 struct fc_vport *fc_vport;
457
923e4b6a 458#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
51ef4c26
JS		 459 struct dentry *debug_disc_trc;
460 struct dentry *debug_nodelist;
461 struct dentry *vport_debugfs_root;
462 struct lpfc_debugfs_trc *disc_trc;
463 atomic_t disc_trc_cnt;
464#endif
ea2151b4
JS		 465 uint8_t stat_data_enabled;
466 uint8_t stat_data_blocked;
da0436e9 467 struct list_head rcv_buffer_list;
45ed1190 468 unsigned long rcv_buffer_time_stamp;
da0436e9
JS		 469 uint32_t vport_flag;
470#define STATIC_VPORT 1
4258e98e
JS		 471
472 uint16_t fdmi_num_disc;
473 uint32_t fdmi_hba_mask;
474 uint32_t fdmi_port_mask;
895427bd
JS		 475
476 /* There is a single nvme instance per vport. */
477 struct nvme_fc_local_port *localport;
478 uint8_t nvmei_support; /* driver supports NVME Initiator */
479 uint32_t last_fcp_wqidx;
2e0fef85
JS		 480};
481
ed957684
JS		 482struct hbq_s {
483 uint16_t entry_count; /* Current number of HBQ slots */
a8adb832 484 uint16_t buffer_count; /* Current number of buffers posted */
ed957684
JS		 485 uint32_t next_hbqPutIdx; /* Index to next HBQ slot to use */
486 uint32_t hbqPutIdx; /* HBQ slot to use */
487 uint32_t local_hbqGetIdx; /* Local copy of Get index from Port */
51ef4c26
JS		 488 void *hbq_virt; /* Virtual ptr to this hbq */
489 struct list_head hbq_buffer_list; /* buffers assigned to this HBQ */
490 /* Callback for HBQ buffer allocation */
491 struct hbq_dmabuf *(*hbq_alloc_buffer) (struct lpfc_hba *);
492 /* Callback for HBQ buffer free */
493 void (*hbq_free_buffer) (struct lpfc_hba *,
494 struct hbq_dmabuf *);
ed957684
JS		 495};
496
51ef4c26 497/* this matches the position in the lpfc_hbq_defs array */
92d7f7b0 498#define LPFC_ELS_HBQ 0
895427bd 499#define LPFC_MAX_HBQS 1
ed957684 500
7af67051
JS		 501enum hba_temp_state {
502 HBA_NORMAL_TEMP,
503 HBA_OVER_TEMP
504};
505
db2378e0
JS		 506enum intr_type_t {
507 NONE = 0,
508 INTx,
509 MSI,
510 MSIX,
511};
512
6dd9e31c 513#define LPFC_CT_CTX_MAX 64
f1c3b0fc
JS		 514struct unsol_rcv_ct_ctx {
515 uint32_t ctxt_id;
516 uint32_t SID;
6dd9e31c
JS		 517 uint32_t valid;
518#define UNSOL_INVALID 0
519#define UNSOL_VALID 1
7851fe2c
JS		 520 uint16_t oxid;
521 uint16_t rxid;
f1c3b0fc
JS		 522};
523
76a95d75
JS		 524#define LPFC_USER_LINK_SPEED_AUTO 0 /* auto select (default)*/
525#define LPFC_USER_LINK_SPEED_1G 1 /* 1 Gigabaud */
526#define LPFC_USER_LINK_SPEED_2G 2 /* 2 Gigabaud */
527#define LPFC_USER_LINK_SPEED_4G 4 /* 4 Gigabaud */
528#define LPFC_USER_LINK_SPEED_8G 8 /* 8 Gigabaud */
529#define LPFC_USER_LINK_SPEED_10G 10 /* 10 Gigabaud */
530#define LPFC_USER_LINK_SPEED_16G 16 /* 16 Gigabaud */
d38dd52c
JS		 531#define LPFC_USER_LINK_SPEED_32G 32 /* 32 Gigabaud */
532#define LPFC_USER_LINK_SPEED_MAX LPFC_USER_LINK_SPEED_32G
533#define LPFC_USER_LINK_SPEED_BITMAP ((1ULL << LPFC_USER_LINK_SPEED_32G) | \
534 (1 << LPFC_USER_LINK_SPEED_16G) | \
76a95d75
JS		 535 (1 << LPFC_USER_LINK_SPEED_10G) | \
536 (1 << LPFC_USER_LINK_SPEED_8G) | \
537 (1 << LPFC_USER_LINK_SPEED_4G) | \
538 (1 << LPFC_USER_LINK_SPEED_2G) | \
539 (1 << LPFC_USER_LINK_SPEED_1G) | \
540 (1 << LPFC_USER_LINK_SPEED_AUTO))
d38dd52c 541#define LPFC_LINK_SPEED_STRING "0, 1, 2, 4, 8, 10, 16, 32"
76a95d75 542
7ad20aa9
JS		 543enum nemb_type {
544 nemb_mse = 1,
545 nemb_hbd
546};
547
548enum mbox_type {
549 mbox_rd = 1,
550 mbox_wr
551};
552
553enum dma_type {
554 dma_mbox = 1,
555 dma_ebuf
556};
557
558enum sta_type {
559 sta_pre_addr = 1,
560 sta_pos_addr
561};
562
563struct lpfc_mbox_ext_buf_ctx {
564 uint32_t state;
565#define LPFC_BSG_MBOX_IDLE 0
566#define LPFC_BSG_MBOX_HOST 1
567#define LPFC_BSG_MBOX_PORT 2
568#define LPFC_BSG_MBOX_DONE 3
569#define LPFC_BSG_MBOX_ABTS 4
570 enum nemb_type nembType;
571 enum mbox_type mboxType;
572 uint32_t numBuf;
573 uint32_t mbxTag;
574 uint32_t seqNum;
575 struct lpfc_dmabuf *mbx_dmabuf;
576 struct list_head ext_dmabuf_list;
577};
578
dea3101e 579struct lpfc_hba {
3772a991
JS		 580 /* SCSI interface function jump table entries */
581 int (*lpfc_new_scsi_buf)
582 (struct lpfc_vport *, int);
583 struct lpfc_scsi_buf * (*lpfc_get_scsi_buf)
19ca7609 584 (struct lpfc_hba *, struct lpfc_nodelist *);
3772a991
JS		 585 int (*lpfc_scsi_prep_dma_buf)
586 (struct lpfc_hba *, struct lpfc_scsi_buf *);
587 void (*lpfc_scsi_unprep_dma_buf)
588 (struct lpfc_hba *, struct lpfc_scsi_buf *);
589 void (*lpfc_release_scsi_buf)
590 (struct lpfc_hba *, struct lpfc_scsi_buf *);
591 void (*lpfc_rampdown_queue_depth)
592 (struct lpfc_hba *);
593 void (*lpfc_scsi_prep_cmnd)
594 (struct lpfc_vport *, struct lpfc_scsi_buf *,
595 struct lpfc_nodelist *);
acd6859b 596
3772a991
JS		 597 /* IOCB interface function jump table entries */
598 int (*__lpfc_sli_issue_iocb)
599 (struct lpfc_hba *, uint32_t,
600 struct lpfc_iocbq *, uint32_t);
601 void (*__lpfc_sli_release_iocbq)(struct lpfc_hba *,
602 struct lpfc_iocbq *);
603 int (*lpfc_hba_down_post)(struct lpfc_hba *phba);
3772a991
JS		 604 IOCB_t * (*lpfc_get_iocb_from_iocbq)
605 (struct lpfc_iocbq *);
606 void (*lpfc_scsi_cmd_iocb_cmpl)
607 (struct lpfc_hba *, struct lpfc_iocbq *, struct lpfc_iocbq *);
608
609 /* MBOX interface function jump table entries */
610 int (*lpfc_sli_issue_mbox)
611 (struct lpfc_hba *, LPFC_MBOXQ_t *, uint32_t);
acd6859b 612
3772a991
JS		 613 /* Slow-path IOCB process function jump table entries */
614 void (*lpfc_sli_handle_slow_ring_event)
615 (struct lpfc_hba *phba, struct lpfc_sli_ring *pring,
616 uint32_t mask);
acd6859b 617
3772a991
JS		 618 /* INIT device interface function jump table entries */
619 int (*lpfc_sli_hbq_to_firmware)
620 (struct lpfc_hba *, uint32_t, struct hbq_dmabuf *);
621 int (*lpfc_sli_brdrestart)
622 (struct lpfc_hba *);
623 int (*lpfc_sli_brdready)
624 (struct lpfc_hba *, uint32_t);
625 void (*lpfc_handle_eratt)
626 (struct lpfc_hba *);
627 void (*lpfc_stop_port)
628 (struct lpfc_hba *);
84d1b006 629 int (*lpfc_hba_init_link)
6e7288d9 630 (struct lpfc_hba *, uint32_t);
84d1b006 631 int (*lpfc_hba_down_link)
6e7288d9 632 (struct lpfc_hba *, uint32_t);
7f86059a
JS		 633 int (*lpfc_selective_reset)
634 (struct lpfc_hba *);
3772a991 635
acd6859b
JS		 636 int (*lpfc_bg_scsi_prep_dma_buf)
637 (struct lpfc_hba *, struct lpfc_scsi_buf *);
638 /* Add new entries here */
639
3772a991
JS		 640 /* SLI4 specific HBA data structure */
641 struct lpfc_sli4_hba sli4_hba;
642
dea3101e 643 struct lpfc_sli sli;
3772a991
JS		 644 uint8_t pci_dev_grp; /* lpfc PCI dev group: 0x0, 0x1, 0x2,... */
645 uint32_t sli_rev; /* SLI2, SLI3, or SLI4 */
ed957684 646 uint32_t sli3_options; /* Mask of enabled SLI3 options */
34b02dcd
JS		 647#define LPFC_SLI3_HBQ_ENABLED 0x01
648#define LPFC_SLI3_NPIV_ENABLED 0x02
649#define LPFC_SLI3_VPORT_TEARDOWN 0x04
650#define LPFC_SLI3_CRP_ENABLED 0x08
81301a9b 651#define LPFC_SLI3_BG_ENABLED 0x20
da0436e9 652#define LPFC_SLI3_DSS_ENABLED 0x40
fedd3b7b
JS		 653#define LPFC_SLI4_PERFH_ENABLED 0x80
654#define LPFC_SLI4_PHWQ_ENABLED 0x100
ed957684
JS		 655 uint32_t iocb_cmd_size;
656 uint32_t iocb_rsp_size;
2e0fef85
JS		 657
658 enum hba_state link_state;
659 uint32_t link_flag; /* link state flags */
311464ec 660#define LS_LOOPBACK_MODE 0x1 /* NPort is in Loopback mode */
2e0fef85
JS		 661 /* This flag is set while issuing */
662 /* INIT_LINK mailbox command */
92d7f7b0 663#define LS_NPIV_FAB_SUPPORTED 0x2 /* Fabric supports NPIV */
1b32f6aa 664#define LS_IGNORE_ERATT 0x4 /* intr handler should ignore ERATT */
2e0fef85 665
9399627f
JS		 666 uint32_t hba_flag; /* hba generic flags */
667#define HBA_ERATT_HANDLED 0x1 /* This flag is set when eratt handled */
da0436e9 668#define DEFER_ERATT 0x2 /* Deferred error attention in progress */
76a95d75 669#define HBA_FCOE_MODE 0x4 /* HBA function in FCoE Mode */
45ed1190 670#define HBA_SP_QUEUE_EVT 0x8 /* Slow-path qevt posted to worker thread*/
da0436e9
JS		 671#define HBA_POST_RECEIVE_BUFFER 0x10 /* Rcv buffers need to be posted */
672#define FCP_XRI_ABORT_EVENT 0x20
673#define ELS_XRI_ABORT_EVENT 0x40
674#define ASYNC_EVENT 0x80
a0c87cbd 675#define LINK_DISABLED 0x100 /* Link disabled by user */
a93ff37a
JS		 676#define FCF_TS_INPROG 0x200 /* FCF table scan in progress */
677#define FCF_RR_INPROG 0x400 /* FCF roundrobin flogi in progress */
678#define HBA_FIP_SUPPORT 0x800 /* FIP support in HBA */
679#define HBA_AER_ENABLED 0x1000 /* AER enabled with HBA */
680#define HBA_DEVLOSS_TMO 0x2000 /* HBA in devloss timeout */
19ca7609 681#define HBA_RRQ_ACTIVE 0x4000 /* process the rrq active list */
4f2e66c6 682#define HBA_FCP_IOQ_FLUSH 0x8000 /* FCP I/O queues being flushed */
0293635e 683#define HBA_FW_DUMP_OP 0x10000 /* Skips fn reset before FW dump */
65791f1f 684#define HBA_RECOVERABLE_UE 0x20000 /* Firmware supports recoverable UE */
c691816e
JS		 685#define HBA_FORCED_LINK_SPEED 0x40000 /*
686 * Firmware supports Forced Link Speed
687 * capability
688 */
895427bd
JS		 689#define HBA_NVME_IOQ_FLUSH 0x80000 /* NVME IO queues flushed. */
690
45ed1190 691 uint32_t fcp_ring_in_use; /* When polling test if intr-hndlr active*/
34b02dcd
JS		 692 struct lpfc_dmabuf slim2p;
693
694 MAILBOX_t *mbox;
7a470277 695 uint32_t *mbox_ext;
7ad20aa9 696 struct lpfc_mbox_ext_buf_ctx mbox_ext_buf_ctx;
9399627f 697 uint32_t ha_copy;
34b02dcd
JS		 698 struct _PCB *pcb;
699 struct _IOCB *IOCBs;
2e0fef85 700
34b02dcd 701 struct lpfc_dmabuf hbqslimp;
2e0fef85 702
dea3101e 703 uint16_t pci_cfg_value;
704
dea3101e 705 uint8_t fc_linkspeed; /* Link speed after last READ_LA */
706
707 uint32_t fc_eventTag; /* event tag for link attention */
4d9ab994 708 uint32_t link_events;
dea3101e 709
dea3101e 710 /* These fields used to be binfo */
dea3101e 711 uint32_t fc_pref_DID; /* preferred D_ID */
92d7f7b0 712 uint8_t fc_pref_ALPA; /* preferred AL_PA */
12265f68 713 uint32_t fc_edtovResol; /* E_D_TOV timer resolution */
dea3101e 714 uint32_t fc_edtov; /* E_D_TOV timer value */
715 uint32_t fc_arbtov; /* ARB_TOV timer value */
716 uint32_t fc_ratov; /* R_A_TOV timer value */
717 uint32_t fc_rttov; /* R_T_TOV timer value */
718 uint32_t fc_altov; /* AL_TOV timer value */
719 uint32_t fc_crtov; /* C_R_TOV timer value */
720 uint32_t fc_citov; /* C_I_TOV timer value */
dea3101e 721
dea3101e 722 struct serv_parm fc_fabparam; /* fabric service parameters buffer */
723 uint8_t alpa_map[128]; /* AL_PA map from READ_LA */
724
dea3101e 725 uint32_t lmt;
dea3101e 726
727 uint32_t fc_topology; /* link topology, from LINK INIT */
e74c03c8 728 uint32_t fc_topology_changed; /* link topology, from LINK INIT */
dea3101e 729
730 struct lpfc_stats fc_stat;
731
dea3101e 732 struct lpfc_nodelist fc_fcpnodev; /* nodelist entry for no device */
733 uint32_t nport_event_cnt; /* timestamp for nlplist entry */
734
2e0fef85
JS		 735 uint8_t wwnn[8];
736 uint8_t wwpn[8];
dea3101e 737 uint32_t RandomData[7];
7bdedb34 738 uint8_t fcp_embed_io;
895427bd
JS		 739 uint8_t nvme_support; /* Firmware supports NVME */
740 uint8_t nvmet_support; /* driver supports NVMET */
7bdedb34 741 uint8_t mds_diags_support;
dea3101e 742
3de2a653 743 /* HBA Config Parameters */
dea3101e 744 uint32_t cfg_ack0;
78b2d852 745 uint32_t cfg_enable_npiv;
19ca7609 746 uint32_t cfg_enable_rrq;
dea3101e 747 uint32_t cfg_topology;
dea3101e 748 uint32_t cfg_link_speed;
7d791df7
JS		 749#define LPFC_FCF_FOV 1 /* Fast fcf failover */
750#define LPFC_FCF_PRIORITY 2 /* Priority fcf failover */
751 uint32_t cfg_fcf_failover_policy;
49aa143d 752 uint32_t cfg_fcp_io_sched;
a6571c6e 753 uint32_t cfg_fcp2_no_tgt_reset;
dea3101e 754 uint32_t cfg_cr_delay;
755 uint32_t cfg_cr_count;
cf5bf97e 756 uint32_t cfg_multi_ring_support;
a4bc3379
JS		 757 uint32_t cfg_multi_ring_rctl;
758 uint32_t cfg_multi_ring_type;
875fbdfe
JSEC		 759 uint32_t cfg_poll;
760 uint32_t cfg_poll_tmo;
0c411222 761 uint32_t cfg_task_mgmt_tmo;
4ff43246 762 uint32_t cfg_use_msi;
da0436e9 763 uint32_t cfg_fcp_imax;
7bb03bbf 764 uint32_t cfg_fcp_cpu_map;
67d12733 765 uint32_t cfg_fcp_io_channel;
895427bd
JS		 766 uint32_t cfg_nvme_oas;
767 uint32_t cfg_nvme_io_channel;
768 uint32_t cfg_nvme_enable_fb;
96f7077f 769 uint32_t cfg_total_seg_cnt;
dea3101e 770 uint32_t cfg_sg_seg_cnt;
771 uint32_t cfg_sg_dma_buf_size;
352e5fd1
JS		 772 uint64_t cfg_soft_wwnn;
773 uint64_t cfg_soft_wwpn;
3de2a653 774 uint32_t cfg_hba_queue_depth;
13815c83
JS		 775 uint32_t cfg_enable_hba_reset;
776 uint32_t cfg_enable_hba_heartbeat;
1ba981fd
JS		 777 uint32_t cfg_fof;
778 uint32_t cfg_EnableXLane;
779 uint8_t cfg_oas_tgt_wwpn[8];
780 uint8_t cfg_oas_vpt_wwpn[8];
781 uint32_t cfg_oas_lun_state;
782#define OAS_LUN_ENABLE 1
783#define OAS_LUN_DISABLE 0
784 uint32_t cfg_oas_lun_status;
785#define OAS_LUN_STATUS_EXISTS 0x01
786 uint32_t cfg_oas_flags;
787#define OAS_FIND_ANY_VPORT 0x01
788#define OAS_FIND_ANY_TARGET 0x02
789#define OAS_LUN_VALID 0x04
c92c841c 790 uint32_t cfg_oas_priority;
1ba981fd 791 uint32_t cfg_XLanePriority;
81301a9b 792 uint32_t cfg_enable_bg;
b3b98b74
JS		 793 uint32_t cfg_prot_mask;
794 uint32_t cfg_prot_guard;
7a470277 795 uint32_t cfg_hostmem_hgp;
da0436e9 796 uint32_t cfg_log_verbose;
0d878419 797 uint32_t cfg_aer_support;
912e3acd 798 uint32_t cfg_sriov_nr_virtfn;
c71ab861 799 uint32_t cfg_request_firmware_upgrade;
2a9bf3d0 800 uint32_t cfg_iocb_cnt;
84d1b006 801 uint32_t cfg_suppress_link_up;
cff261f6 802 uint32_t cfg_rrq_xri_bitmap_sz;
8eb8b960 803 uint32_t cfg_delay_discovery;
12247e81 804 uint32_t cfg_sli_mode;
e40a02c1
JS		 805#define LPFC_INITIALIZE_LINK 0 /* do normal init_link mbox */
806#define LPFC_DELAY_INIT_LINK 1 /* layered driver hold off */
807#define LPFC_DELAY_INIT_LINK_INDEFINITELY 2 /* wait, manual intervention */
ab56dc2e 808 uint32_t cfg_enable_dss;
4258e98e
JS		 809 uint32_t cfg_fdmi_on;
810#define LPFC_FDMI_NO_SUPPORT 0 /* FDMI not supported */
811#define LPFC_FDMI_SUPPORT 1 /* FDMI supported? */
4258e98e 812 uint32_t cfg_enable_SmartSAN;
7bdedb34 813 uint32_t cfg_enable_mds_diags;
895427bd
JS		 814 uint32_t cfg_enable_fc4_type;
815 uint32_t cfg_xri_split;
816#define LPFC_ENABLE_FCP 1
817#define LPFC_ENABLE_NVME 2
818#define LPFC_ENABLE_BOTH 3
819 uint32_t io_channel_irqs; /* number of irqs for io channels */
dea3101e 820 lpfc_vpd_t vpd; /* vital product data */
821
dea3101e 822 struct pci_dev *pcidev;
823 struct list_head work_list;
824 uint32_t work_ha; /* Host Attention Bits for WT */
825 uint32_t work_ha_mask; /* HA Bits owned by WT */
826 uint32_t work_hs; /* HS stored in case of ERRAT */
827 uint32_t work_status[2]; /* Extra status from SLIM */
dea3101e 828
5e9d9b82 829 wait_queue_head_t work_waitq;
dea3101e 830 struct task_struct *worker_thread;
d7c255b2 831 unsigned long data_flags;
dea3101e 832
3163f725 833 uint32_t hbq_in_use; /* HBQs in use flag */
ed957684 834 uint32_t hbq_count; /* Count of configured HBQs */
92d7f7b0 835 struct hbq_s hbqs[LPFC_MAX_HBQS]; /* local copy of hbq indicies */
ed957684 836
895427bd
JS		 837 atomic_t fcp_qidx; /* next FCP WQ (RR Policy) */
838 atomic_t nvme_qidx; /* next NVME WQ (RR Policy) */
8fa38513 839
115a4124
JS		 840 phys_addr_t pci_bar0_map; /* Physical address for PCI BAR0 */
841 phys_addr_t pci_bar1_map; /* Physical address for PCI BAR1 */
842 phys_addr_t pci_bar2_map; /* Physical address for PCI BAR2 */
dea3101e 843 void __iomem *slim_memmap_p; /* Kernel memory mapped address for
844 PCI BAR0 */
845 void __iomem *ctrl_regs_memmap_p;/* Kernel memory mapped address for
846 PCI BAR2 */
847
962bc51b
JS		 848 void __iomem *pci_bar0_memmap_p; /* Kernel memory mapped address for
849 PCI BAR0 with dual-ULP support */
850 void __iomem *pci_bar2_memmap_p; /* Kernel memory mapped address for
851 PCI BAR2 with dual-ULP support */
852 void __iomem *pci_bar4_memmap_p; /* Kernel memory mapped address for
853 PCI BAR4 with dual-ULP support */
854#define PCI_64BIT_BAR0 0
855#define PCI_64BIT_BAR2 2
856#define PCI_64BIT_BAR4 4
dea3101e 857 void __iomem *MBslimaddr; /* virtual address for mbox cmds */
858 void __iomem *HAregaddr; /* virtual address for host attn reg */
859 void __iomem *CAregaddr; /* virtual address for chip attn reg */
860 void __iomem *HSregaddr; /* virtual address for host status
861 reg */
862 void __iomem *HCregaddr; /* virtual address for host ctl reg */
863
ed957684 864 struct lpfc_hgp __iomem *host_gp; /* Host side get/put pointers */
34b02dcd 865 struct lpfc_pgp *port_gp;
ed957684 866 uint32_t __iomem *hbq_put; /* Address in SLIM to HBQ put ptrs */
92d7f7b0 867 uint32_t *hbq_get; /* Host mem address of HBQ get ptrs */
ed957684 868
dea3101e 869 int brd_no; /* FC board number */
dea3101e 870 char SerialNumber[32]; /* adapter Serial Number */
871 char OptionROMVersion[32]; /* adapter BIOS / Fcode version */
872 char ModelDesc[256]; /* Model Description */
873 char ModelName[80]; /* Model Name */
874 char ProgramType[256]; /* Program Type */
875 char Port[20]; /* Port No */
876 uint8_t vpd_flag; /* VPD data flag */
877
878#define VPD_MODEL_DESC 0x1 /* valid vpd model description */
879#define VPD_MODEL_NAME 0x2 /* valid vpd model name */
880#define VPD_PROGRAM_TYPE 0x4 /* valid vpd program type */
881#define VPD_PORT 0x8 /* valid vpd port data */
882#define VPD_MASK 0xf /* mask for any vpd data */
883
352e5fd1
JS		 884 uint8_t soft_wwn_enable;
885
875fbdfe 886 struct timer_list fcp_poll_timer;
9399627f 887 struct timer_list eratt_poll;
65791f1f 888 uint32_t eratt_poll_interval;
875fbdfe 889
dea3101e 890 /*
891 * stat counters
892 */
895427bd
JS		 893 uint64_t fc4ScsiInputRequests;
894 uint64_t fc4ScsiOutputRequests;
895 uint64_t fc4ScsiControlRequests;
896 uint64_t fc4ScsiIoCmpls;
897 uint64_t fc4NvmeInputRequests;
898 uint64_t fc4NvmeOutputRequests;
899 uint64_t fc4NvmeControlRequests;
900 uint64_t fc4NvmeIoCmpls;
901 uint64_t fc4NvmeLsRequests;
902 uint64_t fc4NvmeLsCmpls;
903
81301a9b
JS		 904 uint64_t bg_guard_err_cnt;
905 uint64_t bg_apptag_err_cnt;
906 uint64_t bg_reftag_err_cnt;
dea3101e 907
dea3101e 908 /* fastpath list. */
a40fc5f0
JS		 909 spinlock_t scsi_buf_list_get_lock; /* SCSI buf alloc list lock */
910 spinlock_t scsi_buf_list_put_lock; /* SCSI buf free list lock */
911 struct list_head lpfc_scsi_buf_list_get;
912 struct list_head lpfc_scsi_buf_list_put;
dea3101e 913 uint32_t total_scsi_bufs;
895427bd
JS		 914 spinlock_t nvme_buf_list_get_lock; /* NVME buf alloc list lock */
915 spinlock_t nvme_buf_list_put_lock; /* NVME buf free list lock */
916 struct list_head lpfc_nvme_buf_list_get;
917 struct list_head lpfc_nvme_buf_list_put;
918 uint32_t total_nvme_bufs;
dea3101e 919 struct list_head lpfc_iocb_list;
920 uint32_t total_iocbq_bufs;
19ca7609 921 struct list_head active_rrq_list;
2e0fef85 922 spinlock_t hbalock;
dea3101e 923
924 /* pci_mem_pools */
895427bd 925 struct pci_pool *lpfc_sg_dma_buf_pool;
dea3101e 926 struct pci_pool *lpfc_mbuf_pool;
da0436e9
JS		 927 struct pci_pool *lpfc_hrb_pool; /* header receive buffer pool */
928 struct pci_pool *lpfc_drb_pool; /* data receive buffer pool */
8568a4d2 929 struct pci_pool *lpfc_hbq_pool; /* SLI3 hbq buffer pool */
895427bd 930 struct pci_pool *txrdy_payload_pool;
dea3101e 931 struct lpfc_dma_pool lpfc_mbuf_safety_pool;
932
933 mempool_t *mbox_mem_pool;
934 mempool_t *nlp_mem_pool;
19ca7609 935 mempool_t *rrq_pool;
cff261f6 936 mempool_t *active_rrq_pool;
f888ba3c
JSEC		 937
938 struct fc_host_statistics link_stats;
db2378e0 939 enum intr_type_t intr_type;
5b75da2f
JS		 940 uint32_t intr_mode;
941#define LPFC_INTR_ERROR 0xFFFFFFFF
2e0fef85 942 struct list_head port_list;
549e55cd
JS		 943 struct lpfc_vport *pport; /* physical lpfc_vport pointer */
944 uint16_t max_vpi; /* Maximum virtual nports */
09372820 945#define LPFC_MAX_VPI 0xFFFF /* Max number of VPI supported */
da0436e9
JS		 946 uint16_t max_vports; /*
947 * For IOV HBAs max_vpi can change
948 * after a reset. max_vports is max
949 * number of vports present. This can
950 * be greater than max_vpi.
951 */
952 uint16_t vpi_base;
953 uint16_t vfi_base;
549e55cd 954 unsigned long *vpi_bmask; /* vpi allocation table */
6d368e53
JS		 955 uint16_t *vpi_ids;
956 uint16_t vpi_count;
957 struct list_head lpfc_vpi_blk_list;
92d7f7b0
JS		 958
959 /* Data structure used by fabric iocb scheduler */
960 struct list_head fabric_iocb_list;
961 atomic_t fabric_iocb_count;
962 struct timer_list fabric_block_timer;
963 unsigned long bit_flags;
964#define FABRIC_COMANDS_BLOCKED 0
965 atomic_t num_rsrc_err;
966 atomic_t num_cmd_success;
967 unsigned long last_rsrc_error_time;
968 unsigned long last_ramp_down_time;
923e4b6a 969#ifdef CONFIG_SCSI_LPFC_DEBUG_FS
858c9f6c
JS		 970 struct dentry *hba_debugfs_root;
971 atomic_t debugfs_vport_count;
78b2d852 972 struct dentry *debug_hbqinfo;
c95d6c6c
JS		 973 struct dentry *debug_dumpHostSlim;
974 struct dentry *debug_dumpHBASlim;
f9bb2da1
JS		 975 struct dentry *debug_dumpData; /* BlockGuard BPL */
976 struct dentry *debug_dumpDif; /* BlockGuard BPL */
977 struct dentry *debug_InjErrLBA; /* LBA to inject errors at */
4ac9b226
JS		 978 struct dentry *debug_InjErrNPortID; /* NPortID to inject errors at */
979 struct dentry *debug_InjErrWWPN; /* WWPN to inject errors at */
f9bb2da1
JS		 980 struct dentry *debug_writeGuard; /* inject write guard_tag errors */
981 struct dentry *debug_writeApp; /* inject write app_tag errors */
982 struct dentry *debug_writeRef; /* inject write ref_tag errors */
acd6859b 983 struct dentry *debug_readGuard; /* inject read guard_tag errors */
f9bb2da1
JS		 984 struct dentry *debug_readApp; /* inject read app_tag errors */
985 struct dentry *debug_readRef; /* inject read ref_tag errors */
986
987 /* T10 DIF error injection */
988 uint32_t lpfc_injerr_wgrd_cnt;
989 uint32_t lpfc_injerr_wapp_cnt;
990 uint32_t lpfc_injerr_wref_cnt;
acd6859b 991 uint32_t lpfc_injerr_rgrd_cnt;
f9bb2da1
JS		 992 uint32_t lpfc_injerr_rapp_cnt;
993 uint32_t lpfc_injerr_rref_cnt;
4ac9b226
JS		 994 uint32_t lpfc_injerr_nportid;
995 struct lpfc_name lpfc_injerr_wwpn;
f9bb2da1 996 sector_t lpfc_injerr_lba;
acd6859b 997#define LPFC_INJERR_LBA_OFF (sector_t)(-1)
f9bb2da1 998
a58cbd52
JS		 999 struct dentry *debug_slow_ring_trc;
1000 struct lpfc_debugfs_trc *slow_ring_trc;
1001 atomic_t slow_ring_trc_cnt;
2a622bfb
JS		 1002 /* iDiag debugfs sub-directory */
1003 struct dentry *idiag_root;
1004 struct dentry *idiag_pci_cfg;
b76f2dc9 1005 struct dentry *idiag_bar_acc;
2a622bfb 1006 struct dentry *idiag_que_info;
86a80846
JS		 1007 struct dentry *idiag_que_acc;
1008 struct dentry *idiag_drb_acc;
b76f2dc9
JS		 1009 struct dentry *idiag_ctl_acc;
1010 struct dentry *idiag_mbx_acc;
1011 struct dentry *idiag_ext_acc;
07bcd98e 1012 uint8_t lpfc_idiag_last_eq;
858c9f6c
JS		 1013#endif
1014
0ff10d46
JS		 1015 /* Used for deferred freeing of ELS data buffers */
1016 struct list_head elsbuf;
1017 int elsbuf_cnt;
1018 int elsbuf_prev_cnt;
1019
57127f15 1020 uint8_t temp_sensor_support;
858c9f6c
JS		 1021 /* Fields used for heart beat. */
1022 unsigned long last_completion_time;
bc73905a 1023 unsigned long skipped_hb;
858c9f6c
JS		 1024 struct timer_list hb_tmofunc;
1025 uint8_t hb_outstanding;
19ca7609 1026 struct timer_list rrq_tmr;
84774a4d 1027 enum hba_temp_state over_temp_state;
e47c9093
JS		 1028 /* ndlp reference management */
1029 spinlock_t ndlp_lock;
76bb24ef
JS		 1030 /*
1031 * Following bit will be set for all buffer tags which are not
1032 * associated with any HBQ.
1033 */
1034#define QUE_BUFTAG_BIT (1<<31)
1035 uint32_t buffer_tag_count;
84774a4d
JS		 1036 int wait_4_mlo_maint_flg;
1037 wait_queue_head_t wait_4_mlo_m_q;
ea2151b4
JS		 1038 /* data structure used for latency data collection */
1039#define LPFC_NO_BUCKET 0
1040#define LPFC_LINEAR_BUCKET 1
1041#define LPFC_POWER2_BUCKET 2
1042 uint8_t bucket_type;
1043 uint32_t bucket_base;
1044 uint32_t bucket_step;
1045
1046/* Maximum number of events that can be outstanding at any time*/
1047#define LPFC_MAX_EVT_COUNT 512
1048 atomic_t fast_event_count;
32b9793f
JS		 1049 uint32_t fcoe_eventtag;
1050 uint32_t fcoe_eventtag_at_fcf_scan;
80c17849
JS		 1051 uint32_t fcoe_cvl_eventtag;
1052 uint32_t fcoe_cvl_eventtag_attn;
da0436e9
JS		 1053 struct lpfc_fcf fcf;
1054 uint8_t fc_map[3];
1055 uint8_t valid_vlan;
1056 uint16_t vlan_id;
1057 struct list_head fcf_conn_rec_list;
f1c3b0fc 1058
4fede78f 1059 spinlock_t ct_ev_lock; /* synchronize access to ct_ev_waiters */
f1c3b0fc 1060 struct list_head ct_ev_waiters;
6dd9e31c 1061 struct unsol_rcv_ct_ctx ct_ctx[LPFC_CT_CTX_MAX];
f1c3b0fc 1062 uint32_t ctx_idx;
e2aed29f
JS		 1063
1064 uint8_t menlo_flag; /* menlo generic flags */
1065#define HBA_MENLO_SUPPORT 0x1 /* HBA supports menlo commands */
2a9bf3d0
JS		 1066 uint32_t iocb_cnt;
1067 uint32_t iocb_max;
d7c47992 1068 atomic_t sdev_cnt;
bc73905a
JS		 1069 uint8_t fips_spec_rev;
1070 uint8_t fips_level;
1ba981fd
JS		 1071 spinlock_t devicelock; /* lock for luns list */
1072 mempool_t *device_data_mem_pool;
1073 struct list_head luns;
310429ef
JS		 1074#define LPFC_TRANSGRESSION_HIGH_TEMPERATURE 0x0080
1075#define LPFC_TRANSGRESSION_LOW_TEMPERATURE 0x0040
1076#define LPFC_TRANSGRESSION_HIGH_VOLTAGE 0x0020
1077#define LPFC_TRANSGRESSION_LOW_VOLTAGE 0x0010
1078#define LPFC_TRANSGRESSION_HIGH_TXBIAS 0x0008
1079#define LPFC_TRANSGRESSION_LOW_TXBIAS 0x0004
1080#define LPFC_TRANSGRESSION_HIGH_TXPOWER 0x0002
1081#define LPFC_TRANSGRESSION_LOW_TXPOWER 0x0001
1082#define LPFC_TRANSGRESSION_HIGH_RXPOWER 0x8000
1083#define LPFC_TRANSGRESSION_LOW_RXPOWER 0x4000
1084 uint16_t sfp_alarm;
1085 uint16_t sfp_warning;
dea3101e 1086};
1087
2e0fef85
JS		 1088static inline struct Scsi_Host *
1089lpfc_shost_from_vport(struct lpfc_vport *vport)
1090{
1091 return container_of((void *) vport, struct Scsi_Host, hostdata[0]);
1092}
1093
5b8bd0c9 1094static inline void
2e0fef85
JS		 1095lpfc_set_loopback_flag(struct lpfc_hba *phba)
1096{
5b8bd0c9 1097 if (phba->cfg_topology == FLAGS_LOCAL_LB)
2e0fef85 1098 phba->link_flag |= LS_LOOPBACK_MODE;
5b8bd0c9 1099 else
2e0fef85
JS		 1100 phba->link_flag &= ~LS_LOOPBACK_MODE;
1101}
1102
1103static inline int
1104lpfc_is_link_up(struct lpfc_hba *phba)
1105{
1106 return phba->link_state == LPFC_LINK_UP ||
92d7f7b0
JS		 1107 phba->link_state == LPFC_CLEAR_LA ||
1108 phba->link_state == LPFC_HBA_READY;
5b8bd0c9 1109}
dea3101e 1110
5e9d9b82
JS		 1111static inline void
1112lpfc_worker_wake_up(struct lpfc_hba *phba)
1113{
1114 /* Set the lpfc data pending flag */
1115 set_bit(LPFC_DATA_READY, &phba->data_flags);
1116
1117 /* Wake up worker thread */
1118 wake_up(&phba->work_waitq);
1119 return;
1120}
1121
9940b97b
JS		 1122static inline int
1123lpfc_readl(void __iomem *addr, uint32_t *data)
1124{
1125 uint32_t temp;
1126 temp = readl(addr);
1127 if (temp == 0xffffffff)
1128 return -EIO;
1129 *data = temp;
1130 return 0;
1131}
1132
1133static inline int
9399627f
JS		 1134lpfc_sli_read_hs(struct lpfc_hba *phba)
1135{
1136 /*
1137 * There was a link/board error. Read the status register to retrieve
1138 * the error event and process it.
1139 */
1140 phba->sli.slistat.err_attn_event++;
1141
9940b97b
JS		 1142 /* Save status info and check for unplug error */
1143 if (lpfc_readl(phba->HSregaddr, &phba->work_hs) ||
1144 lpfc_readl(phba->MBslimaddr + 0xa8, &phba->work_status[0]) ||
1145 lpfc_readl(phba->MBslimaddr + 0xac, &phba->work_status[1])) {
1146 return -EIO;
1147 }
9399627f
JS		 1148
1149 /* Clear chip Host Attention error bit */
1150 writel(HA_ERATT, phba->HAregaddr);
1151 readl(phba->HAregaddr); /* flush */
1152 phba->pport->stopped = 1;
1153
9940b97b 1154 return 0;
9399627f 1155}
895427bd
JS		 1156
1157static inline struct lpfc_sli_ring *
1158lpfc_phba_elsring(struct lpfc_hba *phba)
1159{
1160 if (phba->sli_rev == LPFC_SLI_REV4)
1161 return phba->sli4_hba.els_wq->pring;
1162 return &phba->sli.sli3_ring[LPFC_ELS_RING];
1163}
Linux 6.x block layer and io_uring tree(s)