[SCSI] ipr: Convert to use kzalloc
[linux-block.git] / drivers / scsi / ipr.h
CommitLineData
1da177e4
LT
1/*
2 * ipr.h -- driver for IBM Power Linux RAID adapters
3 *
4 * Written By: Brian King <brking@us.ibm.com>, IBM Corporation
5 *
6 * Copyright (C) 2003, 2004 IBM Corporation
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 *
22 * Alan Cox <alan@redhat.com> - Removed several careless u32/dma_addr_t errors
23 * that broke 64bit platforms.
24 */
25
26#ifndef _IPR_H
27#define _IPR_H
28
29#include <linux/types.h>
30#include <linux/completion.h>
31#include <linux/list.h>
32#include <linux/kref.h>
33#include <scsi/scsi.h>
34#include <scsi/scsi_cmnd.h>
35
36/*
37 * Literals
38 */
f80ed139 39#define IPR_DRIVER_VERSION "2.0.14"
40#define IPR_DRIVER_DATE "(May 2, 2005)"
1da177e4
LT
41
42/*
43 * IPR_DBG_TRACE: Setting this to 1 will turn on some general function tracing
44 * resulting in a bunch of extra debugging printks to the console
45 *
46 * IPR_DEBUG: Setting this to 1 will turn on some error path tracing.
47 * Enables the ipr_trace macro.
48 */
49#ifdef IPR_DEBUG_ALL
50#define IPR_DEBUG 1
51#define IPR_DBG_TRACE 1
52#else
53#define IPR_DEBUG 0
54#define IPR_DBG_TRACE 0
55#endif
56
57/*
58 * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding
59 * ops per device for devices not running tagged command queuing.
60 * This can be adjusted at runtime through sysfs device attributes.
61 */
62#define IPR_MAX_CMD_PER_LUN 6
63
64/*
65 * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of
66 * ops the mid-layer can send to the adapter.
67 */
68#define IPR_NUM_BASE_CMD_BLKS 100
69
70#define IPR_SUBS_DEV_ID_2780 0x0264
71#define IPR_SUBS_DEV_ID_5702 0x0266
72#define IPR_SUBS_DEV_ID_5703 0x0278
73#define IPR_SUBS_DEV_ID_572E 0x028D
74#define IPR_SUBS_DEV_ID_573E 0x02D3
75#define IPR_SUBS_DEV_ID_573D 0x02D4
76#define IPR_SUBS_DEV_ID_571A 0x02C0
77#define IPR_SUBS_DEV_ID_571B 0x02BE
78#define IPR_SUBS_DEV_ID_571E 0x02BF
79
80#define IPR_NAME "ipr"
81
82/*
83 * Return codes
84 */
85#define IPR_RC_JOB_CONTINUE 1
86#define IPR_RC_JOB_RETURN 2
87
88/*
89 * IOASCs
90 */
91#define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200
92#define IPR_IOASC_SYNC_REQUIRED 0x023f0000
93#define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00
94#define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000
95#define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500
96#define IPR_IOASC_IOASC_MASK 0xFFFFFF00
97#define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF
98#define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000
99#define IPR_IOASC_BUS_WAS_RESET 0x06290000
100#define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000
101#define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000
102
103#define IPR_FIRST_DRIVER_IOASC 0x10000000
104#define IPR_IOASC_IOA_WAS_RESET 0x10000001
105#define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002
106
107#define IPR_NUM_LOG_HCAMS 2
108#define IPR_NUM_CFG_CHG_HCAMS 2
109#define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS)
110#define IPR_MAX_NUM_TARGETS_PER_BUS 0x10
111#define IPR_MAX_NUM_LUNS_PER_TARGET 256
112#define IPR_MAX_NUM_VSET_LUNS_PER_TARGET 8
113#define IPR_VSET_BUS 0xff
114#define IPR_IOA_BUS 0xff
115#define IPR_IOA_TARGET 0xff
116#define IPR_IOA_LUN 0xff
117#define IPR_MAX_NUM_BUSES 4
118#define IPR_MAX_BUS_TO_SCAN IPR_MAX_NUM_BUSES
119
120#define IPR_NUM_RESET_RELOAD_RETRIES 3
121
122/* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */
123#define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \
124 ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 3)
125
126#define IPR_MAX_COMMANDS IPR_NUM_BASE_CMD_BLKS
127#define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \
128 IPR_NUM_INTERNAL_CMD_BLKS)
129
130#define IPR_MAX_PHYSICAL_DEVS 192
131
132#define IPR_MAX_SGLIST 64
133#define IPR_IOA_MAX_SECTORS 32767
134#define IPR_VSET_MAX_SECTORS 512
135#define IPR_MAX_CDB_LEN 16
136
137#define IPR_DEFAULT_BUS_WIDTH 16
138#define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
139#define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
140#define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8))
141#define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8))
142
143#define IPR_IOA_RES_HANDLE 0xffffffff
144#define IPR_IOA_RES_ADDR 0x00ffffff
145
146/*
147 * Adapter Commands
148 */
149#define IPR_QUERY_RSRC_STATE 0xC2
150#define IPR_RESET_DEVICE 0xC3
151#define IPR_RESET_TYPE_SELECT 0x80
152#define IPR_LUN_RESET 0x40
153#define IPR_TARGET_RESET 0x20
154#define IPR_BUS_RESET 0x10
155#define IPR_ID_HOST_RR_Q 0xC4
156#define IPR_QUERY_IOA_CONFIG 0xC5
157#define IPR_CANCEL_ALL_REQUESTS 0xCE
158#define IPR_HOST_CONTROLLED_ASYNC 0xCF
159#define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01
160#define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02
161#define IPR_SET_SUPPORTED_DEVICES 0xFB
162#define IPR_IOA_SHUTDOWN 0xF7
163#define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05
164
165/*
166 * Timeouts
167 */
168#define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ)
169#define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ)
170#define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ)
171#define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
172#define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
173#define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
174#define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ)
175#define IPR_WRITE_BUFFER_TIMEOUT (10 * 60 * HZ)
176#define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ)
177#define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ)
178#define IPR_OPERATIONAL_TIMEOUT (5 * 60)
179#define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ)
180#define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10)
181#define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ)
182#define IPR_DUMP_TIMEOUT (15 * HZ)
183
184/*
185 * SCSI Literals
186 */
187#define IPR_VENDOR_ID_LEN 8
188#define IPR_PROD_ID_LEN 16
189#define IPR_SERIAL_NUM_LEN 8
190
191/*
192 * Hardware literals
193 */
194#define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff
195#define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000
196#define IPR_FMT2_MKR_BAR_SEL_SHIFT 28
197#define IPR_GET_FMT2_BAR_SEL(mbx) \
198(((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT)
199#define IPR_SDT_FMT2_BAR0_SEL 0x0
200#define IPR_SDT_FMT2_BAR1_SEL 0x1
201#define IPR_SDT_FMT2_BAR2_SEL 0x2
202#define IPR_SDT_FMT2_BAR3_SEL 0x3
203#define IPR_SDT_FMT2_BAR4_SEL 0x4
204#define IPR_SDT_FMT2_BAR5_SEL 0x5
205#define IPR_SDT_FMT2_EXP_ROM_SEL 0x8
206#define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2
207#define IPR_DOORBELL 0x82800000
208
209#define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0)
210#define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3)
211#define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4)
212#define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5)
213#define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6)
214#define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7)
215#define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27)
216#define IPR_PCII_MMIO_ERROR (0x80000000 >> 28)
217#define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29)
218#define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30)
219#define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31)
220
221#define IPR_PCII_ERROR_INTERRUPTS \
222(IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \
223IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR)
224
225#define IPR_PCII_OPER_INTERRUPTS \
226(IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER)
227
228#define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7)
229#define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9)
230
231#define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */
232#define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */
233
234/*
235 * Dump literals
236 */
237#define IPR_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024)
238#define IPR_NUM_SDT_ENTRIES 511
239#define IPR_MAX_NUM_DUMP_PAGES ((IPR_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1)
240
241/*
242 * Misc literals
243 */
244#define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST
245
246/*
247 * Adapter interface types
248 */
249
250struct ipr_res_addr {
251 u8 reserved;
252 u8 bus;
253 u8 target;
254 u8 lun;
255#define IPR_GET_PHYS_LOC(res_addr) \
256 (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun)
257}__attribute__((packed, aligned (4)));
258
259struct ipr_std_inq_vpids {
260 u8 vendor_id[IPR_VENDOR_ID_LEN];
261 u8 product_id[IPR_PROD_ID_LEN];
262}__attribute__((packed));
263
cfc32139 264struct ipr_vpd {
265 struct ipr_std_inq_vpids vpids;
266 u8 sn[IPR_SERIAL_NUM_LEN];
267}__attribute__((packed));
268
1da177e4
LT
269struct ipr_std_inq_data {
270 u8 peri_qual_dev_type;
271#define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5)
272#define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F)
273
274 u8 removeable_medium_rsvd;
275#define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80
276
277#define IPR_IS_DASD_DEVICE(std_inq) \
278((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \
279!(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM))
280
281#define IPR_IS_SES_DEVICE(std_inq) \
282(IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE)
283
284 u8 version;
285 u8 aen_naca_fmt;
286 u8 additional_len;
287 u8 sccs_rsvd;
288 u8 bq_enc_multi;
289 u8 sync_cmdq_flags;
290
291 struct ipr_std_inq_vpids vpids;
292
293 u8 ros_rsvd_ram_rsvd[4];
294
295 u8 serial_num[IPR_SERIAL_NUM_LEN];
296}__attribute__ ((packed));
297
298struct ipr_config_table_entry {
299 u8 service_level;
300 u8 array_id;
301 u8 flags;
302#define IPR_IS_IOA_RESOURCE 0x80
303#define IPR_IS_ARRAY_MEMBER 0x20
304#define IPR_IS_HOT_SPARE 0x10
305
306 u8 rsvd_subtype;
307#define IPR_RES_SUBTYPE(res) (((res)->cfgte.rsvd_subtype) & 0x0f)
308#define IPR_SUBTYPE_AF_DASD 0
309#define IPR_SUBTYPE_GENERIC_SCSI 1
310#define IPR_SUBTYPE_VOLUME_SET 2
311
312 struct ipr_res_addr res_addr;
313 __be32 res_handle;
314 __be32 reserved4[2];
315 struct ipr_std_inq_data std_inq_data;
316}__attribute__ ((packed, aligned (4)));
317
318struct ipr_config_table_hdr {
319 u8 num_entries;
320 u8 flags;
321#define IPR_UCODE_DOWNLOAD_REQ 0x10
322 __be16 reserved;
323}__attribute__((packed, aligned (4)));
324
325struct ipr_config_table {
326 struct ipr_config_table_hdr hdr;
327 struct ipr_config_table_entry dev[IPR_MAX_PHYSICAL_DEVS];
328}__attribute__((packed, aligned (4)));
329
330struct ipr_hostrcb_cfg_ch_not {
331 struct ipr_config_table_entry cfgte;
332 u8 reserved[936];
333}__attribute__((packed, aligned (4)));
334
335struct ipr_supported_device {
336 __be16 data_length;
337 u8 reserved;
338 u8 num_records;
339 struct ipr_std_inq_vpids vpids;
340 u8 reserved2[16];
341}__attribute__((packed, aligned (4)));
342
343/* Command packet structure */
344struct ipr_cmd_pkt {
345 __be16 reserved; /* Reserved by IOA */
346 u8 request_type;
347#define IPR_RQTYPE_SCSICDB 0x00
348#define IPR_RQTYPE_IOACMD 0x01
349#define IPR_RQTYPE_HCAM 0x02
350
351 u8 luntar_luntrn;
352
353 u8 flags_hi;
354#define IPR_FLAGS_HI_WRITE_NOT_READ 0x80
355#define IPR_FLAGS_HI_NO_ULEN_CHK 0x20
356#define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10
357#define IPR_FLAGS_HI_SYNC_COMPLETE 0x08
358#define IPR_FLAGS_HI_NO_LINK_DESC 0x04
359
360 u8 flags_lo;
361#define IPR_FLAGS_LO_ALIGNED_BFR 0x20
362#define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10
363#define IPR_FLAGS_LO_UNTAGGED_TASK 0x00
364#define IPR_FLAGS_LO_SIMPLE_TASK 0x02
365#define IPR_FLAGS_LO_ORDERED_TASK 0x04
366#define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06
367#define IPR_FLAGS_LO_ACA_TASK 0x08
368
369 u8 cdb[16];
370 __be16 timeout;
371}__attribute__ ((packed, aligned(4)));
372
373/* IOA Request Control Block 128 bytes */
374struct ipr_ioarcb {
375 __be32 ioarcb_host_pci_addr;
376 __be32 reserved;
377 __be32 res_handle;
378 __be32 host_response_handle;
379 __be32 reserved1;
380 __be32 reserved2;
381 __be32 reserved3;
382
383 __be32 write_data_transfer_length;
384 __be32 read_data_transfer_length;
385 __be32 write_ioadl_addr;
386 __be32 write_ioadl_len;
387 __be32 read_ioadl_addr;
388 __be32 read_ioadl_len;
389
390 __be32 ioasa_host_pci_addr;
391 __be16 ioasa_len;
392 __be16 reserved4;
393
394 struct ipr_cmd_pkt cmd_pkt;
395
396 __be32 add_cmd_parms_len;
397 __be32 add_cmd_parms[10];
398}__attribute__((packed, aligned (4)));
399
400struct ipr_ioadl_desc {
401 __be32 flags_and_data_len;
402#define IPR_IOADL_FLAGS_MASK 0xff000000
403#define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK)
404#define IPR_IOADL_DATA_LEN_MASK 0x00ffffff
405#define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK)
406#define IPR_IOADL_FLAGS_READ 0x48000000
407#define IPR_IOADL_FLAGS_READ_LAST 0x49000000
408#define IPR_IOADL_FLAGS_WRITE 0x68000000
409#define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000
410#define IPR_IOADL_FLAGS_LAST 0x01000000
411
412 __be32 address;
413}__attribute__((packed, aligned (8)));
414
415struct ipr_ioasa_vset {
416 __be32 failing_lba_hi;
417 __be32 failing_lba_lo;
418 __be32 ioa_data[22];
419}__attribute__((packed, aligned (4)));
420
421struct ipr_ioasa_af_dasd {
422 __be32 failing_lba;
423}__attribute__((packed, aligned (4)));
424
425struct ipr_ioasa_gpdd {
426 u8 end_state;
427 u8 bus_phase;
428 __be16 reserved;
429 __be32 ioa_data[23];
430}__attribute__((packed, aligned (4)));
431
432struct ipr_ioasa_raw {
433 __be32 ioa_data[24];
434}__attribute__((packed, aligned (4)));
435
436struct ipr_ioasa {
437 __be32 ioasc;
438#define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24)
439#define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16)
440#define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8)
441#define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff)
442
443 __be16 ret_stat_len; /* Length of the returned IOASA */
444
445 __be16 avail_stat_len; /* Total Length of status available. */
446
447 __be32 residual_data_len; /* number of bytes in the host data */
448 /* buffers that were not used by the IOARCB command. */
449
450 __be32 ilid;
451#define IPR_NO_ILID 0
452#define IPR_DRIVER_ILID 0xffffffff
453
454 __be32 fd_ioasc;
455
456 __be32 fd_phys_locator;
457
458 __be32 fd_res_handle;
459
460 __be32 ioasc_specific; /* status code specific field */
461#define IPR_IOASC_SPECIFIC_MASK 0x00ffffff
462#define IPR_FIELD_POINTER_VALID (0x80000000 >> 8)
463#define IPR_FIELD_POINTER_MASK 0x0000ffff
464
465 union {
466 struct ipr_ioasa_vset vset;
467 struct ipr_ioasa_af_dasd dasd;
468 struct ipr_ioasa_gpdd gpdd;
469 struct ipr_ioasa_raw raw;
470 } u;
471}__attribute__((packed, aligned (4)));
472
473struct ipr_mode_parm_hdr {
474 u8 length;
475 u8 medium_type;
476 u8 device_spec_parms;
477 u8 block_desc_len;
478}__attribute__((packed));
479
480struct ipr_mode_pages {
481 struct ipr_mode_parm_hdr hdr;
482 u8 data[255 - sizeof(struct ipr_mode_parm_hdr)];
483}__attribute__((packed));
484
485struct ipr_mode_page_hdr {
486 u8 ps_page_code;
487#define IPR_MODE_PAGE_PS 0x80
488#define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F)
489 u8 page_length;
490}__attribute__ ((packed));
491
492struct ipr_dev_bus_entry {
493 struct ipr_res_addr res_addr;
494 u8 flags;
495#define IPR_SCSI_ATTR_ENABLE_QAS 0x80
496#define IPR_SCSI_ATTR_DISABLE_QAS 0x40
497#define IPR_SCSI_ATTR_QAS_MASK 0xC0
498#define IPR_SCSI_ATTR_ENABLE_TM 0x20
499#define IPR_SCSI_ATTR_NO_TERM_PWR 0x10
500#define IPR_SCSI_ATTR_TM_SUPPORTED 0x08
501#define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04
502
503 u8 scsi_id;
504 u8 bus_width;
505 u8 extended_reset_delay;
506#define IPR_EXTENDED_RESET_DELAY 7
507
508 __be32 max_xfer_rate;
509
510 u8 spinup_delay;
511 u8 reserved3;
512 __be16 reserved4;
513}__attribute__((packed, aligned (4)));
514
515struct ipr_mode_page28 {
516 struct ipr_mode_page_hdr hdr;
517 u8 num_entries;
518 u8 entry_length;
519 struct ipr_dev_bus_entry bus[0];
520}__attribute__((packed));
521
522struct ipr_ioa_vpd {
523 struct ipr_std_inq_data std_inq_data;
524 u8 ascii_part_num[12];
525 u8 reserved[40];
526 u8 ascii_plant_code[4];
527}__attribute__((packed));
528
529struct ipr_inquiry_page3 {
530 u8 peri_qual_dev_type;
531 u8 page_code;
532 u8 reserved1;
533 u8 page_length;
534 u8 ascii_len;
535 u8 reserved2[3];
536 u8 load_id[4];
537 u8 major_release;
538 u8 card_type;
539 u8 minor_release[2];
540 u8 ptf_number[4];
541 u8 patch_number[4];
542}__attribute__((packed));
543
62275040 544#define IPR_INQUIRY_PAGE0_ENTRIES 20
545struct ipr_inquiry_page0 {
546 u8 peri_qual_dev_type;
547 u8 page_code;
548 u8 reserved1;
549 u8 len;
550 u8 page[IPR_INQUIRY_PAGE0_ENTRIES];
551}__attribute__((packed));
552
1da177e4 553struct ipr_hostrcb_device_data_entry {
cfc32139 554 struct ipr_vpd vpd;
1da177e4 555 struct ipr_res_addr dev_res_addr;
cfc32139 556 struct ipr_vpd new_vpd;
557 struct ipr_vpd ioa_last_with_dev_vpd;
558 struct ipr_vpd cfc_last_with_dev_vpd;
1da177e4
LT
559 __be32 ioa_data[5];
560}__attribute__((packed, aligned (4)));
561
562struct ipr_hostrcb_array_data_entry {
cfc32139 563 struct ipr_vpd vpd;
1da177e4
LT
564 struct ipr_res_addr expected_dev_res_addr;
565 struct ipr_res_addr dev_res_addr;
566}__attribute__((packed, aligned (4)));
567
568struct ipr_hostrcb_type_ff_error {
569 __be32 ioa_data[246];
570}__attribute__((packed, aligned (4)));
571
572struct ipr_hostrcb_type_01_error {
573 __be32 seek_counter;
574 __be32 read_counter;
575 u8 sense_data[32];
576 __be32 ioa_data[236];
577}__attribute__((packed, aligned (4)));
578
579struct ipr_hostrcb_type_02_error {
cfc32139 580 struct ipr_vpd ioa_vpd;
581 struct ipr_vpd cfc_vpd;
582 struct ipr_vpd ioa_last_attached_to_cfc_vpd;
583 struct ipr_vpd cfc_last_attached_to_ioa_vpd;
1da177e4 584 __be32 ioa_data[3];
1da177e4
LT
585}__attribute__((packed, aligned (4)));
586
587struct ipr_hostrcb_type_03_error {
cfc32139 588 struct ipr_vpd ioa_vpd;
589 struct ipr_vpd cfc_vpd;
1da177e4
LT
590 __be32 errors_detected;
591 __be32 errors_logged;
592 u8 ioa_data[12];
cfc32139 593 struct ipr_hostrcb_device_data_entry dev[3];
1da177e4
LT
594}__attribute__((packed, aligned (4)));
595
596struct ipr_hostrcb_type_04_error {
cfc32139 597 struct ipr_vpd ioa_vpd;
598 struct ipr_vpd cfc_vpd;
1da177e4
LT
599 u8 ioa_data[12];
600 struct ipr_hostrcb_array_data_entry array_member[10];
601 __be32 exposed_mode_adn;
602 __be32 array_id;
cfc32139 603 struct ipr_vpd incomp_dev_vpd;
1da177e4
LT
604 __be32 ioa_data2;
605 struct ipr_hostrcb_array_data_entry array_member2[8];
606 struct ipr_res_addr last_func_vset_res_addr;
607 u8 vset_serial_num[IPR_SERIAL_NUM_LEN];
608 u8 protection_level[8];
1da177e4
LT
609}__attribute__((packed, aligned (4)));
610
611struct ipr_hostrcb_error {
612 __be32 failing_dev_ioasc;
613 struct ipr_res_addr failing_dev_res_addr;
614 __be32 failing_dev_res_handle;
615 __be32 prc;
616 union {
617 struct ipr_hostrcb_type_ff_error type_ff_error;
618 struct ipr_hostrcb_type_01_error type_01_error;
619 struct ipr_hostrcb_type_02_error type_02_error;
620 struct ipr_hostrcb_type_03_error type_03_error;
621 struct ipr_hostrcb_type_04_error type_04_error;
622 } u;
623}__attribute__((packed, aligned (4)));
624
625struct ipr_hostrcb_raw {
626 __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)];
627}__attribute__((packed, aligned (4)));
628
629struct ipr_hcam {
630 u8 op_code;
631#define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1
632#define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2
633
634 u8 notify_type;
635#define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00
636#define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01
637#define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02
638#define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10
639#define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11
640
641 u8 notifications_lost;
642#define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0
643#define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80
644
645 u8 flags;
646#define IPR_HOSTRCB_INTERNAL_OPER 0x80
647#define IPR_HOSTRCB_ERR_RESP_SENT 0x40
648
649 u8 overlay_id;
650#define IPR_HOST_RCB_OVERLAY_ID_1 0x01
651#define IPR_HOST_RCB_OVERLAY_ID_2 0x02
652#define IPR_HOST_RCB_OVERLAY_ID_3 0x03
653#define IPR_HOST_RCB_OVERLAY_ID_4 0x04
654#define IPR_HOST_RCB_OVERLAY_ID_6 0x06
655#define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF
656
657 u8 reserved1[3];
658 __be32 ilid;
659 __be32 time_since_last_ioa_reset;
660 __be32 reserved2;
661 __be32 length;
662
663 union {
664 struct ipr_hostrcb_error error;
665 struct ipr_hostrcb_cfg_ch_not ccn;
666 struct ipr_hostrcb_raw raw;
667 } u;
668}__attribute__((packed, aligned (4)));
669
670struct ipr_hostrcb {
671 struct ipr_hcam hcam;
672 dma_addr_t hostrcb_dma;
673 struct list_head queue;
674};
675
676/* IPR smart dump table structures */
677struct ipr_sdt_entry {
678 __be32 bar_str_offset;
679 __be32 end_offset;
680 u8 entry_byte;
681 u8 reserved[3];
682
683 u8 flags;
684#define IPR_SDT_ENDIAN 0x80
685#define IPR_SDT_VALID_ENTRY 0x20
686
687 u8 resv;
688 __be16 priority;
689}__attribute__((packed, aligned (4)));
690
691struct ipr_sdt_header {
692 __be32 state;
693 __be32 num_entries;
694 __be32 num_entries_used;
695 __be32 dump_size;
696}__attribute__((packed, aligned (4)));
697
698struct ipr_sdt {
699 struct ipr_sdt_header hdr;
700 struct ipr_sdt_entry entry[IPR_NUM_SDT_ENTRIES];
701}__attribute__((packed, aligned (4)));
702
703struct ipr_uc_sdt {
704 struct ipr_sdt_header hdr;
705 struct ipr_sdt_entry entry[1];
706}__attribute__((packed, aligned (4)));
707
708/*
709 * Driver types
710 */
711struct ipr_bus_attributes {
712 u8 bus;
713 u8 qas_enabled;
714 u8 bus_width;
715 u8 reserved;
716 u32 max_xfer_rate;
717};
718
719struct ipr_resource_entry {
720 struct ipr_config_table_entry cfgte;
721 u8 needs_sync_complete:1;
722 u8 in_erp:1;
723 u8 add_to_ml:1;
724 u8 del_from_ml:1;
725 u8 resetting_device:1;
726
727 struct scsi_device *sdev;
728 struct list_head queue;
729};
730
731struct ipr_resource_hdr {
732 u16 num_entries;
733 u16 reserved;
734};
735
736struct ipr_resource_table {
737 struct ipr_resource_hdr hdr;
738 struct ipr_resource_entry dev[IPR_MAX_PHYSICAL_DEVS];
739};
740
741struct ipr_misc_cbs {
742 struct ipr_ioa_vpd ioa_vpd;
62275040 743 struct ipr_inquiry_page0 page0_data;
1da177e4
LT
744 struct ipr_inquiry_page3 page3_data;
745 struct ipr_mode_pages mode_pages;
746 struct ipr_supported_device supp_dev;
747};
748
749struct ipr_interrupt_offsets {
750 unsigned long set_interrupt_mask_reg;
751 unsigned long clr_interrupt_mask_reg;
752 unsigned long sense_interrupt_mask_reg;
753 unsigned long clr_interrupt_reg;
754
755 unsigned long sense_interrupt_reg;
756 unsigned long ioarrin_reg;
757 unsigned long sense_uproc_interrupt_reg;
758 unsigned long set_uproc_interrupt_reg;
759 unsigned long clr_uproc_interrupt_reg;
760};
761
762struct ipr_interrupts {
763 void __iomem *set_interrupt_mask_reg;
764 void __iomem *clr_interrupt_mask_reg;
765 void __iomem *sense_interrupt_mask_reg;
766 void __iomem *clr_interrupt_reg;
767
768 void __iomem *sense_interrupt_reg;
769 void __iomem *ioarrin_reg;
770 void __iomem *sense_uproc_interrupt_reg;
771 void __iomem *set_uproc_interrupt_reg;
772 void __iomem *clr_uproc_interrupt_reg;
773};
774
775struct ipr_chip_cfg_t {
776 u32 mailbox;
777 u8 cache_line_size;
778 struct ipr_interrupt_offsets regs;
779};
780
781struct ipr_chip_t {
782 u16 vendor;
783 u16 device;
784 const struct ipr_chip_cfg_t *cfg;
785};
786
787enum ipr_shutdown_type {
788 IPR_SHUTDOWN_NORMAL = 0x00,
789 IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40,
790 IPR_SHUTDOWN_ABBREV = 0x80,
791 IPR_SHUTDOWN_NONE = 0x100
792};
793
794struct ipr_trace_entry {
795 u32 time;
796
797 u8 op_code;
798 u8 type;
799#define IPR_TRACE_START 0x00
800#define IPR_TRACE_FINISH 0xff
801 u16 cmd_index;
802
803 __be32 res_handle;
804 union {
805 u32 ioasc;
806 u32 add_data;
807 u32 res_addr;
808 } u;
809};
810
811struct ipr_sglist {
812 u32 order;
813 u32 num_sg;
814 u32 buffer_len;
815 struct scatterlist scatterlist[1];
816};
817
818enum ipr_sdt_state {
819 INACTIVE,
820 WAIT_FOR_DUMP,
821 GET_DUMP,
822 ABORT_DUMP,
823 DUMP_OBTAINED
824};
825
62275040 826enum ipr_cache_state {
827 CACHE_NONE,
828 CACHE_DISABLED,
829 CACHE_ENABLED,
830 CACHE_INVALID
831};
832
1da177e4
LT
833/* Per-controller data */
834struct ipr_ioa_cfg {
835 char eye_catcher[8];
836#define IPR_EYECATCHER "iprcfg"
837
838 struct list_head queue;
839
840 u8 allow_interrupts:1;
841 u8 in_reset_reload:1;
842 u8 in_ioa_bringdown:1;
843 u8 ioa_unit_checked:1;
844 u8 ioa_is_dead:1;
845 u8 dump_taken:1;
846 u8 allow_cmds:1;
847 u8 allow_ml_add_del:1;
848
62275040 849 enum ipr_cache_state cache_state;
1da177e4
LT
850 u16 type; /* CCIN of the card */
851
852 u8 log_level;
853#define IPR_MAX_LOG_LEVEL 4
854#define IPR_DEFAULT_LOG_LEVEL 2
855
856#define IPR_NUM_TRACE_INDEX_BITS 8
857#define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS)
858#define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES)
859 char trace_start[8];
860#define IPR_TRACE_START_LABEL "trace"
861 struct ipr_trace_entry *trace;
862 u32 trace_index:IPR_NUM_TRACE_INDEX_BITS;
863
864 /*
865 * Queue for free command blocks
866 */
867 char ipr_free_label[8];
868#define IPR_FREEQ_LABEL "free-q"
869 struct list_head free_q;
870
871 /*
872 * Queue for command blocks outstanding to the adapter
873 */
874 char ipr_pending_label[8];
875#define IPR_PENDQ_LABEL "pend-q"
876 struct list_head pending_q;
877
878 char cfg_table_start[8];
879#define IPR_CFG_TBL_START "cfg"
880 struct ipr_config_table *cfg_table;
881 dma_addr_t cfg_table_dma;
882
883 char resource_table_label[8];
884#define IPR_RES_TABLE_LABEL "res_tbl"
885 struct ipr_resource_entry *res_entries;
886 struct list_head free_res_q;
887 struct list_head used_res_q;
888
889 char ipr_hcam_label[8];
890#define IPR_HCAM_LABEL "hcams"
891 struct ipr_hostrcb *hostrcb[IPR_NUM_HCAMS];
892 dma_addr_t hostrcb_dma[IPR_NUM_HCAMS];
893 struct list_head hostrcb_free_q;
894 struct list_head hostrcb_pending_q;
895
896 __be32 *host_rrq;
897 dma_addr_t host_rrq_dma;
898#define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc
899#define IPR_HRRQ_RESP_BIT_SET 0x00000002
900#define IPR_HRRQ_TOGGLE_BIT 0x00000001
901#define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2
902 volatile __be32 *hrrq_start;
903 volatile __be32 *hrrq_end;
904 volatile __be32 *hrrq_curr;
905 volatile u32 toggle_bit;
906
907 struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES];
908
909 const struct ipr_chip_cfg_t *chip_cfg;
910
911 void __iomem *hdw_dma_regs; /* iomapped PCI memory space */
912 unsigned long hdw_dma_regs_pci; /* raw PCI memory space */
913 void __iomem *ioa_mailbox;
914 struct ipr_interrupts regs;
915
916 u16 saved_pcix_cmd_reg;
917 u16 reset_retries;
918
919 u32 errors_logged;
920
921 struct Scsi_Host *host;
922 struct pci_dev *pdev;
923 struct ipr_sglist *ucode_sglist;
924 struct ipr_mode_pages *saved_mode_pages;
925 u8 saved_mode_page_len;
926
927 struct work_struct work_q;
928
929 wait_queue_head_t reset_wait_q;
930
931 struct ipr_dump *dump;
932 enum ipr_sdt_state sdt_state;
933
934 struct ipr_misc_cbs *vpd_cbs;
935 dma_addr_t vpd_cbs_dma;
936
937 struct pci_pool *ipr_cmd_pool;
938
939 struct ipr_cmnd *reset_cmd;
940
941 char ipr_cmd_label[8];
942#define IPR_CMD_LABEL "ipr_cmnd"
943 struct ipr_cmnd *ipr_cmnd_list[IPR_NUM_CMD_BLKS];
944 u32 ipr_cmnd_list_dma[IPR_NUM_CMD_BLKS];
945};
946
947struct ipr_cmnd {
948 struct ipr_ioarcb ioarcb;
949 struct ipr_ioasa ioasa;
950 struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES];
951 struct list_head queue;
952 struct scsi_cmnd *scsi_cmd;
953 struct completion completion;
954 struct timer_list timer;
955 void (*done) (struct ipr_cmnd *);
956 int (*job_step) (struct ipr_cmnd *);
957 u16 cmd_index;
958 u8 sense_buffer[SCSI_SENSE_BUFFERSIZE];
959 dma_addr_t sense_buffer_dma;
960 unsigned short dma_use_sg;
961 dma_addr_t dma_handle;
962 struct ipr_cmnd *sibling;
963 union {
964 enum ipr_shutdown_type shutdown_type;
965 struct ipr_hostrcb *hostrcb;
966 unsigned long time_left;
967 unsigned long scratch;
968 struct ipr_resource_entry *res;
969 struct scsi_device *sdev;
970 } u;
971
972 struct ipr_ioa_cfg *ioa_cfg;
973};
974
975struct ipr_ses_table_entry {
976 char product_id[17];
977 char compare_product_id_byte[17];
978 u32 max_bus_speed_limit; /* MB/sec limit for this backplane */
979};
980
981struct ipr_dump_header {
982 u32 eye_catcher;
983#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
984 u32 len;
985 u32 num_entries;
986 u32 first_entry_offset;
987 u32 status;
988#define IPR_DUMP_STATUS_SUCCESS 0
989#define IPR_DUMP_STATUS_QUAL_SUCCESS 2
990#define IPR_DUMP_STATUS_FAILED 0xffffffff
991 u32 os;
992#define IPR_DUMP_OS_LINUX 0x4C4E5558
993 u32 driver_name;
994#define IPR_DUMP_DRIVER_NAME 0x49505232
995}__attribute__((packed, aligned (4)));
996
997struct ipr_dump_entry_header {
998 u32 eye_catcher;
999#define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2
1000 u32 len;
1001 u32 num_elems;
1002 u32 offset;
1003 u32 data_type;
1004#define IPR_DUMP_DATA_TYPE_ASCII 0x41534349
1005#define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41
1006 u32 id;
1007#define IPR_DUMP_IOA_DUMP_ID 0x494F4131
1008#define IPR_DUMP_LOCATION_ID 0x4C4F4341
1009#define IPR_DUMP_TRACE_ID 0x54524143
1010#define IPR_DUMP_DRIVER_VERSION_ID 0x44525652
1011#define IPR_DUMP_DRIVER_TYPE_ID 0x54595045
1012#define IPR_DUMP_IOA_CTRL_BLK 0x494F4342
1013#define IPR_DUMP_PEND_OPS 0x414F5053
1014 u32 status;
1015}__attribute__((packed, aligned (4)));
1016
1017struct ipr_dump_location_entry {
1018 struct ipr_dump_entry_header hdr;
1019 u8 location[BUS_ID_SIZE];
1020}__attribute__((packed));
1021
1022struct ipr_dump_trace_entry {
1023 struct ipr_dump_entry_header hdr;
1024 u32 trace[IPR_TRACE_SIZE / sizeof(u32)];
1025}__attribute__((packed, aligned (4)));
1026
1027struct ipr_dump_version_entry {
1028 struct ipr_dump_entry_header hdr;
1029 u8 version[sizeof(IPR_DRIVER_VERSION)];
1030};
1031
1032struct ipr_dump_ioa_type_entry {
1033 struct ipr_dump_entry_header hdr;
1034 u32 type;
1035 u32 fw_version;
1036};
1037
1038struct ipr_driver_dump {
1039 struct ipr_dump_header hdr;
1040 struct ipr_dump_version_entry version_entry;
1041 struct ipr_dump_location_entry location_entry;
1042 struct ipr_dump_ioa_type_entry ioa_type_entry;
1043 struct ipr_dump_trace_entry trace_entry;
1044}__attribute__((packed));
1045
1046struct ipr_ioa_dump {
1047 struct ipr_dump_entry_header hdr;
1048 struct ipr_sdt sdt;
1049 __be32 *ioa_data[IPR_MAX_NUM_DUMP_PAGES];
1050 u32 reserved;
1051 u32 next_page_index;
1052 u32 page_offset;
1053 u32 format;
1054#define IPR_SDT_FMT2 2
1055#define IPR_SDT_UNKNOWN 3
1056}__attribute__((packed, aligned (4)));
1057
1058struct ipr_dump {
1059 struct kref kref;
1060 struct ipr_ioa_cfg *ioa_cfg;
1061 struct ipr_driver_dump driver_dump;
1062 struct ipr_ioa_dump ioa_dump;
1063};
1064
1065struct ipr_error_table_t {
1066 u32 ioasc;
1067 int log_ioasa;
1068 int log_hcam;
1069 char *error;
1070};
1071
1072struct ipr_software_inq_lid_info {
1073 __be32 load_id;
1074 __be32 timestamp[3];
1075}__attribute__((packed, aligned (4)));
1076
1077struct ipr_ucode_image_header {
1078 __be32 header_length;
1079 __be32 lid_table_offset;
1080 u8 major_release;
1081 u8 card_type;
1082 u8 minor_release[2];
1083 u8 reserved[20];
1084 char eyecatcher[16];
1085 __be32 num_lids;
1086 struct ipr_software_inq_lid_info lid[1];
1087}__attribute__((packed, aligned (4)));
1088
1089/*
1090 * Macros
1091 */
1092#if IPR_DEBUG
1093#define IPR_DBG_CMD(CMD) do { CMD; } while (0)
1094#else
1095#define IPR_DBG_CMD(CMD)
1096#endif
1097
1098#ifdef CONFIG_SCSI_IPR_TRACE
1099#define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1100#define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1101#else
1102#define ipr_create_trace_file(kobj, attr) 0
1103#define ipr_remove_trace_file(kobj, attr) do { } while(0)
1104#endif
1105
1106#ifdef CONFIG_SCSI_IPR_DUMP
1107#define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr)
1108#define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr)
1109#else
1110#define ipr_create_dump_file(kobj, attr) 0
1111#define ipr_remove_dump_file(kobj, attr) do { } while(0)
1112#endif
1113
1114/*
1115 * Error logging macros
1116 */
1117#define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__)
1118#define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)
1119#define ipr_crit(...) printk(KERN_CRIT IPR_NAME ": "__VA_ARGS__)
1120#define ipr_warn(...) printk(KERN_WARNING IPR_NAME": "__VA_ARGS__)
1121#define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__))
1122
017560fc
JG
1123#define ipr_sdev_printk(level, sdev, fmt, args...) \
1124 sdev_printk(level, sdev, fmt, ## args)
1da177e4
LT
1125
1126#define ipr_sdev_err(sdev, fmt, ...) \
1127 ipr_sdev_printk(KERN_ERR, sdev, fmt, ##__VA_ARGS__)
1128
1129#define ipr_sdev_info(sdev, fmt, ...) \
1130 ipr_sdev_printk(KERN_INFO, sdev, fmt, ##__VA_ARGS__)
1131
1132#define ipr_sdev_dbg(sdev, fmt, ...) \
1133 IPR_DBG_CMD(ipr_sdev_printk(KERN_INFO, sdev, fmt, ##__VA_ARGS__))
1134
1135#define ipr_res_printk(level, ioa_cfg, res, fmt, ...) \
1136 printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, ioa_cfg->host->host_no, \
1137 res.bus, res.target, res.lun, ##__VA_ARGS__)
1138
1139#define ipr_res_err(ioa_cfg, res, fmt, ...) \
1140 ipr_res_printk(KERN_ERR, ioa_cfg, res, fmt, ##__VA_ARGS__)
1141#define ipr_res_dbg(ioa_cfg, res, fmt, ...) \
1142 IPR_DBG_CMD(ipr_res_printk(KERN_INFO, ioa_cfg, res, fmt, ##__VA_ARGS__))
1143
fa15b1f6 1144#define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \
1145{ \
1146 if ((res).bus >= IPR_MAX_NUM_BUSES) { \
1147 ipr_err(fmt": unknown\n", ##__VA_ARGS__); \
1148 } else { \
1149 ipr_err(fmt": %d:%d:%d:%d\n", \
1150 ##__VA_ARGS__, (ioa_cfg)->host->host_no, \
1151 (res).bus, (res).target, (res).lun); \
1152 } \
1153}
1154
1da177e4
LT
1155#define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\
1156 __FILE__, __FUNCTION__, __LINE__)
1157
1158#if IPR_DBG_TRACE
1159#define ENTER printk(KERN_INFO IPR_NAME": Entering %s\n", __FUNCTION__)
1160#define LEAVE printk(KERN_INFO IPR_NAME": Leaving %s\n", __FUNCTION__)
1161#else
1162#define ENTER
1163#define LEAVE
1164#endif
1165
1166#define ipr_err_separator \
1167ipr_err("----------------------------------------------------------\n")
1168
1169
1170/*
1171 * Inlines
1172 */
1173
1174/**
1175 * ipr_is_ioa_resource - Determine if a resource is the IOA
1176 * @res: resource entry struct
1177 *
1178 * Return value:
1179 * 1 if IOA / 0 if not IOA
1180 **/
1181static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res)
1182{
1183 return (res->cfgte.flags & IPR_IS_IOA_RESOURCE) ? 1 : 0;
1184}
1185
1186/**
1187 * ipr_is_af_dasd_device - Determine if a resource is an AF DASD
1188 * @res: resource entry struct
1189 *
1190 * Return value:
1191 * 1 if AF DASD / 0 if not AF DASD
1192 **/
1193static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res)
1194{
1195 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1196 !ipr_is_ioa_resource(res) &&
1197 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_AF_DASD)
1198 return 1;
1199 else
1200 return 0;
1201}
1202
1203/**
1204 * ipr_is_vset_device - Determine if a resource is a VSET
1205 * @res: resource entry struct
1206 *
1207 * Return value:
1208 * 1 if VSET / 0 if not VSET
1209 **/
1210static inline int ipr_is_vset_device(struct ipr_resource_entry *res)
1211{
1212 if (IPR_IS_DASD_DEVICE(res->cfgte.std_inq_data) &&
1213 !ipr_is_ioa_resource(res) &&
1214 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_VOLUME_SET)
1215 return 1;
1216 else
1217 return 0;
1218}
1219
1220/**
1221 * ipr_is_gscsi - Determine if a resource is a generic scsi resource
1222 * @res: resource entry struct
1223 *
1224 * Return value:
1225 * 1 if GSCSI / 0 if not GSCSI
1226 **/
1227static inline int ipr_is_gscsi(struct ipr_resource_entry *res)
1228{
1229 if (!ipr_is_ioa_resource(res) &&
1230 IPR_RES_SUBTYPE(res) == IPR_SUBTYPE_GENERIC_SCSI)
1231 return 1;
1232 else
1233 return 0;
1234}
1235
1236/**
1237 * ipr_is_device - Determine if resource address is that of a device
1238 * @res_addr: resource address struct
1239 *
1240 * Return value:
1241 * 1 if AF / 0 if not AF
1242 **/
1243static inline int ipr_is_device(struct ipr_res_addr *res_addr)
1244{
1245 if ((res_addr->bus < IPR_MAX_NUM_BUSES) &&
1246 (res_addr->target < IPR_MAX_NUM_TARGETS_PER_BUS))
1247 return 1;
1248
1249 return 0;
1250}
1251
1252/**
1253 * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2
1254 * @sdt_word: SDT address
1255 *
1256 * Return value:
1257 * 1 if format 2 / 0 if not
1258 **/
1259static inline int ipr_sdt_is_fmt2(u32 sdt_word)
1260{
1261 u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word);
1262
1263 switch (bar_sel) {
1264 case IPR_SDT_FMT2_BAR0_SEL:
1265 case IPR_SDT_FMT2_BAR1_SEL:
1266 case IPR_SDT_FMT2_BAR2_SEL:
1267 case IPR_SDT_FMT2_BAR3_SEL:
1268 case IPR_SDT_FMT2_BAR4_SEL:
1269 case IPR_SDT_FMT2_BAR5_SEL:
1270 case IPR_SDT_FMT2_EXP_ROM_SEL:
1271 return 1;
1272 };
1273
1274 return 0;
1275}
1276
1277#endif