Commit | Line | Data |
---|---|---|
1a59d1b8 | 1 | /* SPDX-License-Identifier: GPL-2.0-or-later */ |
1da177e4 LT |
2 | /* |
3 | * ipr.h -- driver for IBM Power Linux RAID adapters | |
4 | * | |
5 | * Written By: Brian King <brking@us.ibm.com>, IBM Corporation | |
6 | * | |
7 | * Copyright (C) 2003, 2004 IBM Corporation | |
8 | * | |
fa195afe | 9 | * Alan Cox <alan@lxorguk.ukuu.org.uk> - Removed several careless u32/dma_addr_t errors |
1da177e4 LT |
10 | * that broke 64bit platforms. |
11 | */ | |
12 | ||
13 | #ifndef _IPR_H | |
14 | #define _IPR_H | |
15 | ||
46d74563 | 16 | #include <asm/unaligned.h> |
1da177e4 LT |
17 | #include <linux/types.h> |
18 | #include <linux/completion.h> | |
19 | #include <linux/list.h> | |
20 | #include <linux/kref.h> | |
511cbce2 | 21 | #include <linux/irq_poll.h> |
1da177e4 LT |
22 | #include <scsi/scsi.h> |
23 | #include <scsi/scsi_cmnd.h> | |
24 | ||
25 | /* | |
26 | * Literals | |
27 | */ | |
16a20b52 BK |
28 | #define IPR_DRIVER_VERSION "2.6.4" |
29 | #define IPR_DRIVER_DATE "(March 14, 2017)" | |
1da177e4 | 30 | |
1da177e4 LT |
31 | /* |
32 | * IPR_MAX_CMD_PER_LUN: This defines the maximum number of outstanding | |
33 | * ops per device for devices not running tagged command queuing. | |
34 | * This can be adjusted at runtime through sysfs device attributes. | |
35 | */ | |
36 | #define IPR_MAX_CMD_PER_LUN 6 | |
37 | ||
38 | /* | |
39 | * IPR_NUM_BASE_CMD_BLKS: This defines the maximum number of | |
40 | * ops the mid-layer can send to the adapter. | |
41 | */ | |
89aad428 | 42 | #define IPR_NUM_BASE_CMD_BLKS (ioa_cfg->max_cmds) |
1da177e4 | 43 | |
60e7486b | 44 | #define PCI_DEVICE_ID_IBM_OBSIDIAN_E 0x0339 |
d7b4627f WB |
45 | |
46 | #define PCI_DEVICE_ID_IBM_CROC_FPGA_E2 0x033D | |
cd9b3d04 | 47 | #define PCI_DEVICE_ID_IBM_CROCODILE 0x034A |
00da9ffa | 48 | #define PCI_DEVICE_ID_IBM_RATTLESNAKE 0x04DA |
60e7486b | 49 | |
1da177e4 LT |
50 | #define IPR_SUBS_DEV_ID_2780 0x0264 |
51 | #define IPR_SUBS_DEV_ID_5702 0x0266 | |
52 | #define IPR_SUBS_DEV_ID_5703 0x0278 | |
b0f56d3d WB |
53 | #define IPR_SUBS_DEV_ID_572E 0x028D |
54 | #define IPR_SUBS_DEV_ID_573E 0x02D3 | |
55 | #define IPR_SUBS_DEV_ID_573D 0x02D4 | |
1da177e4 LT |
56 | #define IPR_SUBS_DEV_ID_571A 0x02C0 |
57 | #define IPR_SUBS_DEV_ID_571B 0x02BE | |
b0f56d3d | 58 | #define IPR_SUBS_DEV_ID_571E 0x02BF |
86f51436 | 59 | #define IPR_SUBS_DEV_ID_571F 0x02D5 |
60 | #define IPR_SUBS_DEV_ID_572A 0x02C1 | |
61 | #define IPR_SUBS_DEV_ID_572B 0x02C2 | |
60e7486b | 62 | #define IPR_SUBS_DEV_ID_572F 0x02C3 |
185eb31c | 63 | #define IPR_SUBS_DEV_ID_574E 0x030A |
86f51436 | 64 | #define IPR_SUBS_DEV_ID_575B 0x030D |
60e7486b | 65 | #define IPR_SUBS_DEV_ID_575C 0x0338 |
185eb31c | 66 | #define IPR_SUBS_DEV_ID_57B3 0x033A |
60e7486b BK |
67 | #define IPR_SUBS_DEV_ID_57B7 0x0360 |
68 | #define IPR_SUBS_DEV_ID_57B8 0x02C2 | |
1da177e4 | 69 | |
d7b4627f WB |
70 | #define IPR_SUBS_DEV_ID_57B4 0x033B |
71 | #define IPR_SUBS_DEV_ID_57B2 0x035F | |
b8d5d568 | 72 | #define IPR_SUBS_DEV_ID_57C0 0x0352 |
5a918353 | 73 | #define IPR_SUBS_DEV_ID_57C3 0x0353 |
32622bde | 74 | #define IPR_SUBS_DEV_ID_57C4 0x0354 |
d7b4627f | 75 | #define IPR_SUBS_DEV_ID_57C6 0x0357 |
b0f56d3d | 76 | #define IPR_SUBS_DEV_ID_57CC 0x035C |
d7b4627f WB |
77 | |
78 | #define IPR_SUBS_DEV_ID_57B5 0x033C | |
79 | #define IPR_SUBS_DEV_ID_57CE 0x035E | |
80 | #define IPR_SUBS_DEV_ID_57B1 0x0355 | |
81 | ||
82 | #define IPR_SUBS_DEV_ID_574D 0x0356 | |
cd9b3d04 | 83 | #define IPR_SUBS_DEV_ID_57C8 0x035D |
d7b4627f | 84 | |
b8d5d568 | 85 | #define IPR_SUBS_DEV_ID_57D5 0x03FB |
86 | #define IPR_SUBS_DEV_ID_57D6 0x03FC | |
87 | #define IPR_SUBS_DEV_ID_57D7 0x03FF | |
88 | #define IPR_SUBS_DEV_ID_57D8 0x03FE | |
43c5fdaf | 89 | #define IPR_SUBS_DEV_ID_57D9 0x046D |
f94d9964 | 90 | #define IPR_SUBS_DEV_ID_57DA 0x04CA |
43c5fdaf | 91 | #define IPR_SUBS_DEV_ID_57EB 0x0474 |
92 | #define IPR_SUBS_DEV_ID_57EC 0x0475 | |
93 | #define IPR_SUBS_DEV_ID_57ED 0x0499 | |
94 | #define IPR_SUBS_DEV_ID_57EE 0x049A | |
95 | #define IPR_SUBS_DEV_ID_57EF 0x049B | |
96 | #define IPR_SUBS_DEV_ID_57F0 0x049C | |
5eeac3e9 WX |
97 | #define IPR_SUBS_DEV_ID_2CCA 0x04C7 |
98 | #define IPR_SUBS_DEV_ID_2CD2 0x04C8 | |
99 | #define IPR_SUBS_DEV_ID_2CCD 0x04C9 | |
00da9ffa WX |
100 | #define IPR_SUBS_DEV_ID_580A 0x04FC |
101 | #define IPR_SUBS_DEV_ID_580B 0x04FB | |
1da177e4 LT |
102 | #define IPR_NAME "ipr" |
103 | ||
104 | /* | |
105 | * Return codes | |
106 | */ | |
107 | #define IPR_RC_JOB_CONTINUE 1 | |
108 | #define IPR_RC_JOB_RETURN 2 | |
109 | ||
110 | /* | |
111 | * IOASCs | |
112 | */ | |
113 | #define IPR_IOASC_NR_INIT_CMD_REQUIRED 0x02040200 | |
65f56475 | 114 | #define IPR_IOASC_NR_IOA_RESET_REQUIRED 0x02048000 |
1da177e4 LT |
115 | #define IPR_IOASC_SYNC_REQUIRED 0x023f0000 |
116 | #define IPR_IOASC_MED_DO_NOT_REALLOC 0x03110C00 | |
117 | #define IPR_IOASC_HW_SEL_TIMEOUT 0x04050000 | |
118 | #define IPR_IOASC_HW_DEV_BUS_STATUS 0x04448500 | |
119 | #define IPR_IOASC_IOASC_MASK 0xFFFFFF00 | |
120 | #define IPR_IOASC_SCSI_STATUS_MASK 0x000000FF | |
d247a70a | 121 | #define IPR_IOASC_HW_CMD_FAILED 0x046E0000 |
dfed823e | 122 | #define IPR_IOASC_IR_INVALID_REQ_TYPE_OR_PKT 0x05240000 |
1da177e4 | 123 | #define IPR_IOASC_IR_RESOURCE_HANDLE 0x05250000 |
b0df54bb | 124 | #define IPR_IOASC_IR_NO_CMDS_TO_2ND_IOA 0x05258100 |
125 | #define IPR_IOASA_IR_DUAL_IOA_DISABLED 0x052C8000 | |
1da177e4 LT |
126 | #define IPR_IOASC_BUS_WAS_RESET 0x06290000 |
127 | #define IPR_IOASC_BUS_WAS_RESET_BY_OTHER 0x06298000 | |
128 | #define IPR_IOASC_ABORTED_CMD_TERM_BY_HOST 0x0B5A0000 | |
f8ee25d7 | 129 | #define IPR_IOASC_IR_NON_OPTIMIZED 0x05258200 |
1da177e4 LT |
130 | |
131 | #define IPR_FIRST_DRIVER_IOASC 0x10000000 | |
132 | #define IPR_IOASC_IOA_WAS_RESET 0x10000001 | |
133 | #define IPR_IOASC_PCI_ACCESS_ERROR 0x10000002 | |
134 | ||
5469cb5b BK |
135 | /* Driver data flags */ |
136 | #define IPR_USE_LONG_TRANSOP_TIMEOUT 0x00000001 | |
463fc696 | 137 | #define IPR_USE_PCI_WARM_RESET 0x00000002 |
5469cb5b | 138 | |
ac719aba | 139 | #define IPR_DEFAULT_MAX_ERROR_DUMP 984 |
1da177e4 LT |
140 | #define IPR_NUM_LOG_HCAMS 2 |
141 | #define IPR_NUM_CFG_CHG_HCAMS 2 | |
afc3f83c | 142 | #define IPR_NUM_HCAM_QUEUE 12 |
1da177e4 | 143 | #define IPR_NUM_HCAMS (IPR_NUM_LOG_HCAMS + IPR_NUM_CFG_CHG_HCAMS) |
afc3f83c | 144 | #define IPR_MAX_HCAMS (IPR_NUM_HCAMS + IPR_NUM_HCAM_QUEUE) |
3e7ebdfa WB |
145 | |
146 | #define IPR_MAX_SIS64_TARGETS_PER_BUS 1024 | |
147 | #define IPR_MAX_SIS64_LUNS_PER_TARGET 0xffffffff | |
148 | ||
d71a8b0c | 149 | #define IPR_MAX_NUM_TARGETS_PER_BUS 256 |
1da177e4 | 150 | #define IPR_MAX_NUM_LUNS_PER_TARGET 256 |
1da177e4 LT |
151 | #define IPR_VSET_BUS 0xff |
152 | #define IPR_IOA_BUS 0xff | |
153 | #define IPR_IOA_TARGET 0xff | |
154 | #define IPR_IOA_LUN 0xff | |
b5145d25 | 155 | #define IPR_MAX_NUM_BUSES 16 |
1da177e4 LT |
156 | |
157 | #define IPR_NUM_RESET_RELOAD_RETRIES 3 | |
158 | ||
159 | /* We need resources for HCAMS, IOA reset, IOA bringdown, and ERP */ | |
160 | #define IPR_NUM_INTERNAL_CMD_BLKS (IPR_NUM_HCAMS + \ | |
f72919ec | 161 | ((IPR_NUM_RESET_RELOAD_RETRIES + 1) * 2) + 4) |
1da177e4 | 162 | |
89aad428 | 163 | #define IPR_MAX_COMMANDS 100 |
1da177e4 LT |
164 | #define IPR_NUM_CMD_BLKS (IPR_NUM_BASE_CMD_BLKS + \ |
165 | IPR_NUM_INTERNAL_CMD_BLKS) | |
166 | ||
167 | #define IPR_MAX_PHYSICAL_DEVS 192 | |
3e7ebdfa WB |
168 | #define IPR_DEFAULT_SIS64_DEVS 1024 |
169 | #define IPR_MAX_SIS64_DEVS 4096 | |
1da177e4 LT |
170 | |
171 | #define IPR_MAX_SGLIST 64 | |
172 | #define IPR_IOA_MAX_SECTORS 32767 | |
173 | #define IPR_VSET_MAX_SECTORS 512 | |
174 | #define IPR_MAX_CDB_LEN 16 | |
3feeb89d | 175 | #define IPR_MAX_HRRQ_RETRIES 3 |
1da177e4 LT |
176 | |
177 | #define IPR_DEFAULT_BUS_WIDTH 16 | |
178 | #define IPR_80MBs_SCSI_RATE ((80 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) | |
179 | #define IPR_U160_SCSI_RATE ((160 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) | |
180 | #define IPR_U320_SCSI_RATE ((320 * 10) / (IPR_DEFAULT_BUS_WIDTH / 8)) | |
181 | #define IPR_MAX_SCSI_RATE(width) ((320 * 10) / ((width) / 8)) | |
182 | ||
183 | #define IPR_IOA_RES_HANDLE 0xffffffff | |
1121b794 | 184 | #define IPR_INVALID_RES_HANDLE 0 |
1da177e4 LT |
185 | #define IPR_IOA_RES_ADDR 0x00ffffff |
186 | ||
187 | /* | |
188 | * Adapter Commands | |
189 | */ | |
4fdd7c7a BK |
190 | #define IPR_CANCEL_REQUEST 0xC0 |
191 | #define IPR_CANCEL_64BIT_IOARCB 0x01 | |
1da177e4 LT |
192 | #define IPR_QUERY_RSRC_STATE 0xC2 |
193 | #define IPR_RESET_DEVICE 0xC3 | |
194 | #define IPR_RESET_TYPE_SELECT 0x80 | |
195 | #define IPR_LUN_RESET 0x40 | |
196 | #define IPR_TARGET_RESET 0x20 | |
197 | #define IPR_BUS_RESET 0x10 | |
198 | #define IPR_ID_HOST_RR_Q 0xC4 | |
199 | #define IPR_QUERY_IOA_CONFIG 0xC5 | |
200 | #define IPR_CANCEL_ALL_REQUESTS 0xCE | |
201 | #define IPR_HOST_CONTROLLED_ASYNC 0xCF | |
202 | #define IPR_HCAM_CDB_OP_CODE_CONFIG_CHANGE 0x01 | |
203 | #define IPR_HCAM_CDB_OP_CODE_LOG_DATA 0x02 | |
204 | #define IPR_SET_SUPPORTED_DEVICES 0xFB | |
3e7ebdfa | 205 | #define IPR_SET_ALL_SUPPORTED_DEVICES 0x80 |
1da177e4 LT |
206 | #define IPR_IOA_SHUTDOWN 0xF7 |
207 | #define IPR_WR_BUF_DOWNLOAD_AND_SAVE 0x05 | |
1a47af26 GKB |
208 | #define IPR_IOA_SERVICE_ACTION 0xD2 |
209 | ||
210 | /* IOA Service Actions */ | |
211 | #define IPR_IOA_SA_CHANGE_CACHE_PARAMS 0x14 | |
1da177e4 LT |
212 | |
213 | /* | |
214 | * Timeouts | |
215 | */ | |
216 | #define IPR_SHUTDOWN_TIMEOUT (ipr_fastfail ? 60 * HZ : 10 * 60 * HZ) | |
217 | #define IPR_VSET_RW_TIMEOUT (ipr_fastfail ? 30 * HZ : 2 * 60 * HZ) | |
218 | #define IPR_ABBREV_SHUTDOWN_TIMEOUT (10 * HZ) | |
ac09c349 | 219 | #define IPR_DUAL_IOA_ABBR_SHUTDOWN_TO (2 * 60 * HZ) |
1da177e4 | 220 | #define IPR_DEVICE_RESET_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) |
4fdd7c7a | 221 | #define IPR_CANCEL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) |
1da177e4 LT |
222 | #define IPR_CANCEL_ALL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) |
223 | #define IPR_ABORT_TASK_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) | |
224 | #define IPR_INTERNAL_TIMEOUT (ipr_fastfail ? 10 * HZ : 30 * HZ) | |
14ed9cc7 | 225 | #define IPR_WRITE_BUFFER_TIMEOUT (30 * 60 * HZ) |
1da177e4 LT |
226 | #define IPR_SET_SUP_DEVICE_TIMEOUT (2 * 60 * HZ) |
227 | #define IPR_REQUEST_SENSE_TIMEOUT (10 * HZ) | |
228 | #define IPR_OPERATIONAL_TIMEOUT (5 * 60) | |
5469cb5b | 229 | #define IPR_LONG_OPERATIONAL_TIMEOUT (12 * 60) |
1da177e4 LT |
230 | #define IPR_WAIT_FOR_RESET_TIMEOUT (2 * HZ) |
231 | #define IPR_CHECK_FOR_RESET_TIMEOUT (HZ / 10) | |
232 | #define IPR_WAIT_FOR_BIST_TIMEOUT (2 * HZ) | |
6270e593 | 233 | #define IPR_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ) |
463fc696 | 234 | #define IPR_PCI_RESET_TIMEOUT (HZ / 2) |
4d4dd706 KSS |
235 | #define IPR_SIS32_DUMP_TIMEOUT (15 * HZ) |
236 | #define IPR_SIS64_DUMP_TIMEOUT (40 * HZ) | |
110def85 WB |
237 | #define IPR_DUMP_DELAY_SECONDS 4 |
238 | #define IPR_DUMP_DELAY_TIMEOUT (IPR_DUMP_DELAY_SECONDS * HZ) | |
1da177e4 LT |
239 | |
240 | /* | |
241 | * SCSI Literals | |
242 | */ | |
243 | #define IPR_VENDOR_ID_LEN 8 | |
244 | #define IPR_PROD_ID_LEN 16 | |
245 | #define IPR_SERIAL_NUM_LEN 8 | |
246 | ||
247 | /* | |
248 | * Hardware literals | |
249 | */ | |
250 | #define IPR_FMT2_MBX_ADDR_MASK 0x0fffffff | |
251 | #define IPR_FMT2_MBX_BAR_SEL_MASK 0xf0000000 | |
252 | #define IPR_FMT2_MKR_BAR_SEL_SHIFT 28 | |
253 | #define IPR_GET_FMT2_BAR_SEL(mbx) \ | |
254 | (((mbx) & IPR_FMT2_MBX_BAR_SEL_MASK) >> IPR_FMT2_MKR_BAR_SEL_SHIFT) | |
255 | #define IPR_SDT_FMT2_BAR0_SEL 0x0 | |
256 | #define IPR_SDT_FMT2_BAR1_SEL 0x1 | |
257 | #define IPR_SDT_FMT2_BAR2_SEL 0x2 | |
258 | #define IPR_SDT_FMT2_BAR3_SEL 0x3 | |
259 | #define IPR_SDT_FMT2_BAR4_SEL 0x4 | |
260 | #define IPR_SDT_FMT2_BAR5_SEL 0x5 | |
261 | #define IPR_SDT_FMT2_EXP_ROM_SEL 0x8 | |
262 | #define IPR_FMT2_SDT_READY_TO_USE 0xC4D4E3F2 | |
dcbad00e | 263 | #define IPR_FMT3_SDT_READY_TO_USE 0xC4D4E3F3 |
1da177e4 | 264 | #define IPR_DOORBELL 0x82800000 |
3d1d0da6 | 265 | #define IPR_RUNTIME_RESET 0x40000000 |
1da177e4 | 266 | |
214777ba | 267 | #define IPR_IPL_INIT_MIN_STAGE_TIME 5 |
45c44b5f | 268 | #define IPR_IPL_INIT_DEFAULT_STAGE_TIME 30 |
214777ba WB |
269 | #define IPR_IPL_INIT_STAGE_UNKNOWN 0x0 |
270 | #define IPR_IPL_INIT_STAGE_TRANSOP 0xB0000000 | |
271 | #define IPR_IPL_INIT_STAGE_MASK 0xff000000 | |
272 | #define IPR_IPL_INIT_STAGE_TIME_MASK 0x0000ffff | |
273 | #define IPR_PCII_IPL_STAGE_CHANGE (0x80000000 >> 0) | |
274 | ||
f41f1d99 GKB |
275 | #define IPR_PCII_MAILBOX_STABLE (0x80000000 >> 4) |
276 | #define IPR_WAIT_FOR_MAILBOX (2 * HZ) | |
277 | ||
1da177e4 LT |
278 | #define IPR_PCII_IOA_TRANS_TO_OPER (0x80000000 >> 0) |
279 | #define IPR_PCII_IOARCB_XFER_FAILED (0x80000000 >> 3) | |
280 | #define IPR_PCII_IOA_UNIT_CHECKED (0x80000000 >> 4) | |
281 | #define IPR_PCII_NO_HOST_RRQ (0x80000000 >> 5) | |
282 | #define IPR_PCII_CRITICAL_OPERATION (0x80000000 >> 6) | |
283 | #define IPR_PCII_IO_DEBUG_ACKNOWLEDGE (0x80000000 >> 7) | |
284 | #define IPR_PCII_IOARRIN_LOST (0x80000000 >> 27) | |
285 | #define IPR_PCII_MMIO_ERROR (0x80000000 >> 28) | |
286 | #define IPR_PCII_PROC_ERR_STATE (0x80000000 >> 29) | |
287 | #define IPR_PCII_HRRQ_UPDATED (0x80000000 >> 30) | |
288 | #define IPR_PCII_CORE_ISSUED_RST_REQ (0x80000000 >> 31) | |
289 | ||
290 | #define IPR_PCII_ERROR_INTERRUPTS \ | |
291 | (IPR_PCII_IOARCB_XFER_FAILED | IPR_PCII_IOA_UNIT_CHECKED | \ | |
292 | IPR_PCII_NO_HOST_RRQ | IPR_PCII_IOARRIN_LOST | IPR_PCII_MMIO_ERROR) | |
293 | ||
294 | #define IPR_PCII_OPER_INTERRUPTS \ | |
295 | (IPR_PCII_ERROR_INTERRUPTS | IPR_PCII_HRRQ_UPDATED | IPR_PCII_IOA_TRANS_TO_OPER) | |
296 | ||
297 | #define IPR_UPROCI_RESET_ALERT (0x80000000 >> 7) | |
298 | #define IPR_UPROCI_IO_DEBUG_ALERT (0x80000000 >> 9) | |
cb237ef7 | 299 | #define IPR_UPROCI_SIS64_START_BIST (0x80000000 >> 23) |
1da177e4 LT |
300 | |
301 | #define IPR_LDUMP_MAX_LONG_ACK_DELAY_IN_USEC 200000 /* 200 ms */ | |
302 | #define IPR_LDUMP_MAX_SHORT_ACK_DELAY_IN_USEC 200000 /* 200 ms */ | |
303 | ||
304 | /* | |
305 | * Dump literals | |
306 | */ | |
4d4dd706 | 307 | #define IPR_FMT2_MAX_IOA_DUMP_SIZE (4 * 1024 * 1024) |
95d8a25b | 308 | #define IPR_FMT3_MAX_IOA_DUMP_SIZE (80 * 1024 * 1024) |
4d4dd706 KSS |
309 | #define IPR_FMT2_NUM_SDT_ENTRIES 511 |
310 | #define IPR_FMT3_NUM_SDT_ENTRIES 0xFFF | |
311 | #define IPR_FMT2_MAX_NUM_DUMP_PAGES ((IPR_FMT2_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1) | |
312 | #define IPR_FMT3_MAX_NUM_DUMP_PAGES ((IPR_FMT3_MAX_IOA_DUMP_SIZE / PAGE_SIZE) + 1) | |
1da177e4 LT |
313 | |
314 | /* | |
315 | * Misc literals | |
316 | */ | |
317 | #define IPR_NUM_IOADL_ENTRIES IPR_MAX_SGLIST | |
6634ff7c | 318 | #define IPR_MAX_MSIX_VECTORS 0x10 |
05a6538a | 319 | #define IPR_MAX_HRRQ_NUM 0x10 |
320 | #define IPR_INIT_HRRQ 0x0 | |
1da177e4 LT |
321 | |
322 | /* | |
323 | * Adapter interface types | |
324 | */ | |
325 | ||
326 | struct ipr_res_addr { | |
327 | u8 reserved; | |
328 | u8 bus; | |
329 | u8 target; | |
330 | u8 lun; | |
331 | #define IPR_GET_PHYS_LOC(res_addr) \ | |
332 | (((res_addr).bus << 16) | ((res_addr).target << 8) | (res_addr).lun) | |
333 | }__attribute__((packed, aligned (4))); | |
334 | ||
335 | struct ipr_std_inq_vpids { | |
336 | u8 vendor_id[IPR_VENDOR_ID_LEN]; | |
337 | u8 product_id[IPR_PROD_ID_LEN]; | |
338 | }__attribute__((packed)); | |
339 | ||
cfc32139 | 340 | struct ipr_vpd { |
341 | struct ipr_std_inq_vpids vpids; | |
342 | u8 sn[IPR_SERIAL_NUM_LEN]; | |
343 | }__attribute__((packed)); | |
344 | ||
ee0f05b8 | 345 | struct ipr_ext_vpd { |
346 | struct ipr_vpd vpd; | |
347 | __be32 wwid[2]; | |
348 | }__attribute__((packed)); | |
349 | ||
7262026f WB |
350 | struct ipr_ext_vpd64 { |
351 | struct ipr_vpd vpd; | |
352 | __be32 wwid[4]; | |
353 | }__attribute__((packed)); | |
354 | ||
1da177e4 LT |
355 | struct ipr_std_inq_data { |
356 | u8 peri_qual_dev_type; | |
357 | #define IPR_STD_INQ_PERI_QUAL(peri) ((peri) >> 5) | |
358 | #define IPR_STD_INQ_PERI_DEV_TYPE(peri) ((peri) & 0x1F) | |
359 | ||
360 | u8 removeable_medium_rsvd; | |
361 | #define IPR_STD_INQ_REMOVEABLE_MEDIUM 0x80 | |
362 | ||
363 | #define IPR_IS_DASD_DEVICE(std_inq) \ | |
364 | ((IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_DISK) && \ | |
365 | !(((std_inq).removeable_medium_rsvd) & IPR_STD_INQ_REMOVEABLE_MEDIUM)) | |
366 | ||
367 | #define IPR_IS_SES_DEVICE(std_inq) \ | |
368 | (IPR_STD_INQ_PERI_DEV_TYPE((std_inq).peri_qual_dev_type) == TYPE_ENCLOSURE) | |
369 | ||
370 | u8 version; | |
371 | u8 aen_naca_fmt; | |
372 | u8 additional_len; | |
373 | u8 sccs_rsvd; | |
374 | u8 bq_enc_multi; | |
375 | u8 sync_cmdq_flags; | |
376 | ||
377 | struct ipr_std_inq_vpids vpids; | |
378 | ||
379 | u8 ros_rsvd_ram_rsvd[4]; | |
380 | ||
381 | u8 serial_num[IPR_SERIAL_NUM_LEN]; | |
382 | }__attribute__ ((packed)); | |
383 | ||
3e7ebdfa WB |
384 | #define IPR_RES_TYPE_AF_DASD 0x00 |
385 | #define IPR_RES_TYPE_GENERIC_SCSI 0x01 | |
386 | #define IPR_RES_TYPE_VOLUME_SET 0x02 | |
387 | #define IPR_RES_TYPE_REMOTE_AF_DASD 0x03 | |
388 | #define IPR_RES_TYPE_GENERIC_ATA 0x04 | |
389 | #define IPR_RES_TYPE_ARRAY 0x05 | |
390 | #define IPR_RES_TYPE_IOAFP 0xff | |
391 | ||
1da177e4 | 392 | struct ipr_config_table_entry { |
b5145d25 BK |
393 | u8 proto; |
394 | #define IPR_PROTO_SATA 0x02 | |
395 | #define IPR_PROTO_SATA_ATAPI 0x03 | |
396 | #define IPR_PROTO_SAS_STP 0x06 | |
3e7ebdfa | 397 | #define IPR_PROTO_SAS_STP_ATAPI 0x07 |
1da177e4 LT |
398 | u8 array_id; |
399 | u8 flags; | |
3e7ebdfa | 400 | #define IPR_IS_IOA_RESOURCE 0x80 |
1da177e4 | 401 | u8 rsvd_subtype; |
3e7ebdfa WB |
402 | |
403 | #define IPR_QUEUEING_MODEL(res) ((((res)->flags) & 0x70) >> 4) | |
404 | #define IPR_QUEUE_FROZEN_MODEL 0 | |
ee0a90fa | 405 | #define IPR_QUEUE_NACA_MODEL 1 |
406 | ||
1da177e4 LT |
407 | struct ipr_res_addr res_addr; |
408 | __be32 res_handle; | |
46d74563 | 409 | __be32 lun_wwn[2]; |
1da177e4 LT |
410 | struct ipr_std_inq_data std_inq_data; |
411 | }__attribute__ ((packed, aligned (4))); | |
412 | ||
3e7ebdfa WB |
413 | struct ipr_config_table_entry64 { |
414 | u8 res_type; | |
415 | u8 proto; | |
416 | u8 vset_num; | |
417 | u8 array_id; | |
418 | __be16 flags; | |
419 | __be16 res_flags; | |
420 | #define IPR_QUEUEING_MODEL64(res) ((((res)->res_flags) & 0x7000) >> 12) | |
421 | __be32 res_handle; | |
422 | u8 dev_id_type; | |
423 | u8 reserved[3]; | |
424 | __be64 dev_id; | |
425 | __be64 lun; | |
426 | __be64 lun_wwn[2]; | |
b3b3b407 | 427 | #define IPR_MAX_RES_PATH_LENGTH 48 |
7df47cdf | 428 | #define IPR_RES_PATH_BYTES 8 |
3e7ebdfa WB |
429 | __be64 res_path; |
430 | struct ipr_std_inq_data std_inq_data; | |
431 | u8 reserved2[4]; | |
7262026f | 432 | __be64 reserved3[2]; |
3e7ebdfa WB |
433 | u8 reserved4[8]; |
434 | }__attribute__ ((packed, aligned (8))); | |
435 | ||
1da177e4 LT |
436 | struct ipr_config_table_hdr { |
437 | u8 num_entries; | |
438 | u8 flags; | |
439 | #define IPR_UCODE_DOWNLOAD_REQ 0x10 | |
440 | __be16 reserved; | |
441 | }__attribute__((packed, aligned (4))); | |
442 | ||
3e7ebdfa WB |
443 | struct ipr_config_table_hdr64 { |
444 | __be16 num_entries; | |
445 | __be16 reserved; | |
446 | u8 flags; | |
447 | u8 reserved2[11]; | |
448 | }__attribute__((packed, aligned (4))); | |
449 | ||
1da177e4 LT |
450 | struct ipr_config_table { |
451 | struct ipr_config_table_hdr hdr; | |
5febf6d6 | 452 | struct ipr_config_table_entry dev[]; |
1da177e4 LT |
453 | }__attribute__((packed, aligned (4))); |
454 | ||
3e7ebdfa WB |
455 | struct ipr_config_table64 { |
456 | struct ipr_config_table_hdr64 hdr64; | |
5febf6d6 | 457 | struct ipr_config_table_entry64 dev[]; |
3e7ebdfa WB |
458 | }__attribute__((packed, aligned (8))); |
459 | ||
460 | struct ipr_config_table_entry_wrapper { | |
461 | union { | |
462 | struct ipr_config_table_entry *cfgte; | |
463 | struct ipr_config_table_entry64 *cfgte64; | |
464 | } u; | |
465 | }; | |
466 | ||
1da177e4 | 467 | struct ipr_hostrcb_cfg_ch_not { |
3e7ebdfa WB |
468 | union { |
469 | struct ipr_config_table_entry cfgte; | |
470 | struct ipr_config_table_entry64 cfgte64; | |
471 | } u; | |
1da177e4 LT |
472 | u8 reserved[936]; |
473 | }__attribute__((packed, aligned (4))); | |
474 | ||
475 | struct ipr_supported_device { | |
476 | __be16 data_length; | |
477 | u8 reserved; | |
478 | u8 num_records; | |
479 | struct ipr_std_inq_vpids vpids; | |
480 | u8 reserved2[16]; | |
481 | }__attribute__((packed, aligned (4))); | |
482 | ||
05a6538a | 483 | struct ipr_hrr_queue { |
484 | struct ipr_ioa_cfg *ioa_cfg; | |
485 | __be32 *host_rrq; | |
486 | dma_addr_t host_rrq_dma; | |
487 | #define IPR_HRRQ_REQ_RESP_HANDLE_MASK 0xfffffffc | |
488 | #define IPR_HRRQ_RESP_BIT_SET 0x00000002 | |
489 | #define IPR_HRRQ_TOGGLE_BIT 0x00000001 | |
490 | #define IPR_HRRQ_REQ_RESP_HANDLE_SHIFT 2 | |
491 | #define IPR_ID_HRRQ_SELE_ENABLE 0x02 | |
492 | volatile __be32 *hrrq_start; | |
493 | volatile __be32 *hrrq_end; | |
494 | volatile __be32 *hrrq_curr; | |
495 | ||
496 | struct list_head hrrq_free_q; | |
497 | struct list_head hrrq_pending_q; | |
56d6aa33 | 498 | spinlock_t _lock; |
499 | spinlock_t *lock; | |
05a6538a | 500 | |
501 | volatile u32 toggle_bit; | |
502 | u32 size; | |
503 | u32 min_cmd_id; | |
504 | u32 max_cmd_id; | |
56d6aa33 | 505 | u8 allow_interrupts:1; |
506 | u8 ioa_is_dead:1; | |
507 | u8 allow_cmds:1; | |
bfae7820 | 508 | u8 removing_ioa:1; |
b53d124a | 509 | |
511cbce2 | 510 | struct irq_poll iopoll; |
05a6538a | 511 | }; |
512 | ||
1da177e4 LT |
513 | /* Command packet structure */ |
514 | struct ipr_cmd_pkt { | |
05a6538a | 515 | u8 reserved; /* Reserved by IOA */ |
516 | u8 hrrq_id; | |
1da177e4 LT |
517 | u8 request_type; |
518 | #define IPR_RQTYPE_SCSICDB 0x00 | |
519 | #define IPR_RQTYPE_IOACMD 0x01 | |
520 | #define IPR_RQTYPE_HCAM 0x02 | |
f8ee25d7 | 521 | #define IPR_RQTYPE_PIPE 0x05 |
1da177e4 | 522 | |
a32c055f | 523 | u8 reserved2; |
1da177e4 LT |
524 | |
525 | u8 flags_hi; | |
526 | #define IPR_FLAGS_HI_WRITE_NOT_READ 0x80 | |
527 | #define IPR_FLAGS_HI_NO_ULEN_CHK 0x20 | |
528 | #define IPR_FLAGS_HI_SYNC_OVERRIDE 0x10 | |
529 | #define IPR_FLAGS_HI_SYNC_COMPLETE 0x08 | |
530 | #define IPR_FLAGS_HI_NO_LINK_DESC 0x04 | |
531 | ||
532 | u8 flags_lo; | |
533 | #define IPR_FLAGS_LO_ALIGNED_BFR 0x20 | |
ab6c10b1 | 534 | #define IPR_FLAGS_LO_DELAY_AFTER_RST 0x10 |
1da177e4 LT |
535 | #define IPR_FLAGS_LO_UNTAGGED_TASK 0x00 |
536 | #define IPR_FLAGS_LO_SIMPLE_TASK 0x02 | |
537 | #define IPR_FLAGS_LO_ORDERED_TASK 0x04 | |
538 | #define IPR_FLAGS_LO_HEAD_OF_Q_TASK 0x06 | |
539 | #define IPR_FLAGS_LO_ACA_TASK 0x08 | |
540 | ||
541 | u8 cdb[16]; | |
542 | __be16 timeout; | |
543 | }__attribute__ ((packed, aligned(4))); | |
544 | ||
51b1c7e1 BK |
545 | struct ipr_ioadl_desc { |
546 | __be32 flags_and_data_len; | |
547 | #define IPR_IOADL_FLAGS_MASK 0xff000000 | |
548 | #define IPR_IOADL_GET_FLAGS(x) (be32_to_cpu(x) & IPR_IOADL_FLAGS_MASK) | |
549 | #define IPR_IOADL_DATA_LEN_MASK 0x00ffffff | |
550 | #define IPR_IOADL_GET_DATA_LEN(x) (be32_to_cpu(x) & IPR_IOADL_DATA_LEN_MASK) | |
551 | #define IPR_IOADL_FLAGS_READ 0x48000000 | |
552 | #define IPR_IOADL_FLAGS_READ_LAST 0x49000000 | |
553 | #define IPR_IOADL_FLAGS_WRITE 0x68000000 | |
554 | #define IPR_IOADL_FLAGS_WRITE_LAST 0x69000000 | |
555 | #define IPR_IOADL_FLAGS_LAST 0x01000000 | |
556 | ||
557 | __be32 address; | |
558 | }__attribute__((packed, aligned (8))); | |
559 | ||
a32c055f WB |
560 | struct ipr_ioadl64_desc { |
561 | __be32 flags; | |
562 | __be32 data_len; | |
563 | __be64 address; | |
564 | }__attribute__((packed, aligned (16))); | |
565 | ||
b5145d25 BK |
566 | struct ipr_ioarcb_add_data { |
567 | union { | |
51b1c7e1 | 568 | struct ipr_ioadl_desc ioadl[5]; |
b5145d25 | 569 | __be32 add_cmd_parms[10]; |
a32c055f WB |
570 | } u; |
571 | }__attribute__ ((packed, aligned (4))); | |
572 | ||
573 | struct ipr_ioarcb_sis64_add_addr_ecb { | |
574 | __be64 ioasa_host_pci_addr; | |
575 | __be64 data_ioadl_addr; | |
576 | __be64 reserved; | |
577 | __be32 ext_control_buf[4]; | |
578 | }__attribute__((packed, aligned (8))); | |
b5145d25 | 579 | |
1da177e4 LT |
580 | /* IOA Request Control Block 128 bytes */ |
581 | struct ipr_ioarcb { | |
a32c055f WB |
582 | union { |
583 | __be32 ioarcb_host_pci_addr; | |
584 | __be64 ioarcb_host_pci_addr64; | |
585 | } a; | |
1da177e4 LT |
586 | __be32 res_handle; |
587 | __be32 host_response_handle; | |
588 | __be32 reserved1; | |
589 | __be32 reserved2; | |
590 | __be32 reserved3; | |
591 | ||
a32c055f | 592 | __be32 data_transfer_length; |
1da177e4 LT |
593 | __be32 read_data_transfer_length; |
594 | __be32 write_ioadl_addr; | |
a32c055f | 595 | __be32 ioadl_len; |
1da177e4 LT |
596 | __be32 read_ioadl_addr; |
597 | __be32 read_ioadl_len; | |
598 | ||
599 | __be32 ioasa_host_pci_addr; | |
600 | __be16 ioasa_len; | |
601 | __be16 reserved4; | |
602 | ||
603 | struct ipr_cmd_pkt cmd_pkt; | |
604 | ||
a32c055f WB |
605 | __be16 add_cmd_parms_offset; |
606 | __be16 add_cmd_parms_len; | |
607 | ||
608 | union { | |
609 | struct ipr_ioarcb_add_data add_data; | |
610 | struct ipr_ioarcb_sis64_add_addr_ecb sis64_addr_data; | |
611 | } u; | |
612 | ||
1da177e4 LT |
613 | }__attribute__((packed, aligned (4))); |
614 | ||
1da177e4 LT |
615 | struct ipr_ioasa_vset { |
616 | __be32 failing_lba_hi; | |
617 | __be32 failing_lba_lo; | |
c8f74892 | 618 | __be32 reserved; |
1da177e4 LT |
619 | }__attribute__((packed, aligned (4))); |
620 | ||
621 | struct ipr_ioasa_af_dasd { | |
622 | __be32 failing_lba; | |
c8f74892 | 623 | __be32 reserved[2]; |
1da177e4 LT |
624 | }__attribute__((packed, aligned (4))); |
625 | ||
626 | struct ipr_ioasa_gpdd { | |
627 | u8 end_state; | |
628 | u8 bus_phase; | |
629 | __be16 reserved; | |
c8f74892 | 630 | __be32 ioa_data[2]; |
1da177e4 LT |
631 | }__attribute__((packed, aligned (4))); |
632 | ||
c8f74892 | 633 | struct ipr_auto_sense { |
634 | __be16 auto_sense_len; | |
635 | __be16 ioa_data_len; | |
636 | __be32 data[SCSI_SENSE_BUFFERSIZE/sizeof(__be32)]; | |
637 | }; | |
1da177e4 | 638 | |
96d21f00 | 639 | struct ipr_ioasa_hdr { |
1da177e4 LT |
640 | __be32 ioasc; |
641 | #define IPR_IOASC_SENSE_KEY(ioasc) ((ioasc) >> 24) | |
642 | #define IPR_IOASC_SENSE_CODE(ioasc) (((ioasc) & 0x00ff0000) >> 16) | |
643 | #define IPR_IOASC_SENSE_QUAL(ioasc) (((ioasc) & 0x0000ff00) >> 8) | |
644 | #define IPR_IOASC_SENSE_STATUS(ioasc) ((ioasc) & 0x000000ff) | |
645 | ||
646 | __be16 ret_stat_len; /* Length of the returned IOASA */ | |
647 | ||
648 | __be16 avail_stat_len; /* Total Length of status available. */ | |
649 | ||
650 | __be32 residual_data_len; /* number of bytes in the host data */ | |
651 | /* buffers that were not used by the IOARCB command. */ | |
652 | ||
653 | __be32 ilid; | |
654 | #define IPR_NO_ILID 0 | |
655 | #define IPR_DRIVER_ILID 0xffffffff | |
656 | ||
657 | __be32 fd_ioasc; | |
658 | ||
659 | __be32 fd_phys_locator; | |
660 | ||
661 | __be32 fd_res_handle; | |
662 | ||
663 | __be32 ioasc_specific; /* status code specific field */ | |
c8f74892 | 664 | #define IPR_ADDITIONAL_STATUS_FMT 0x80000000 |
665 | #define IPR_AUTOSENSE_VALID 0x40000000 | |
1da177e4 LT |
666 | #define IPR_IOASC_SPECIFIC_MASK 0x00ffffff |
667 | #define IPR_FIELD_POINTER_VALID (0x80000000 >> 8) | |
668 | #define IPR_FIELD_POINTER_MASK 0x0000ffff | |
669 | ||
96d21f00 WB |
670 | }__attribute__((packed, aligned (4))); |
671 | ||
672 | struct ipr_ioasa { | |
673 | struct ipr_ioasa_hdr hdr; | |
674 | ||
675 | union { | |
676 | struct ipr_ioasa_vset vset; | |
677 | struct ipr_ioasa_af_dasd dasd; | |
678 | struct ipr_ioasa_gpdd gpdd; | |
96d21f00 WB |
679 | } u; |
680 | ||
681 | struct ipr_auto_sense auto_sense; | |
682 | }__attribute__((packed, aligned (4))); | |
683 | ||
684 | struct ipr_ioasa64 { | |
685 | struct ipr_ioasa_hdr hdr; | |
686 | u8 fd_res_path[8]; | |
687 | ||
1da177e4 LT |
688 | union { |
689 | struct ipr_ioasa_vset vset; | |
690 | struct ipr_ioasa_af_dasd dasd; | |
691 | struct ipr_ioasa_gpdd gpdd; | |
1da177e4 | 692 | } u; |
c8f74892 | 693 | |
694 | struct ipr_auto_sense auto_sense; | |
1da177e4 LT |
695 | }__attribute__((packed, aligned (4))); |
696 | ||
697 | struct ipr_mode_parm_hdr { | |
698 | u8 length; | |
699 | u8 medium_type; | |
700 | u8 device_spec_parms; | |
701 | u8 block_desc_len; | |
702 | }__attribute__((packed)); | |
703 | ||
704 | struct ipr_mode_pages { | |
705 | struct ipr_mode_parm_hdr hdr; | |
706 | u8 data[255 - sizeof(struct ipr_mode_parm_hdr)]; | |
707 | }__attribute__((packed)); | |
708 | ||
709 | struct ipr_mode_page_hdr { | |
710 | u8 ps_page_code; | |
711 | #define IPR_MODE_PAGE_PS 0x80 | |
712 | #define IPR_GET_MODE_PAGE_CODE(hdr) ((hdr)->ps_page_code & 0x3F) | |
713 | u8 page_length; | |
714 | }__attribute__ ((packed)); | |
715 | ||
716 | struct ipr_dev_bus_entry { | |
717 | struct ipr_res_addr res_addr; | |
718 | u8 flags; | |
719 | #define IPR_SCSI_ATTR_ENABLE_QAS 0x80 | |
720 | #define IPR_SCSI_ATTR_DISABLE_QAS 0x40 | |
721 | #define IPR_SCSI_ATTR_QAS_MASK 0xC0 | |
722 | #define IPR_SCSI_ATTR_ENABLE_TM 0x20 | |
723 | #define IPR_SCSI_ATTR_NO_TERM_PWR 0x10 | |
724 | #define IPR_SCSI_ATTR_TM_SUPPORTED 0x08 | |
725 | #define IPR_SCSI_ATTR_LVD_TO_SE_NOT_ALLOWED 0x04 | |
726 | ||
727 | u8 scsi_id; | |
728 | u8 bus_width; | |
729 | u8 extended_reset_delay; | |
730 | #define IPR_EXTENDED_RESET_DELAY 7 | |
731 | ||
732 | __be32 max_xfer_rate; | |
733 | ||
734 | u8 spinup_delay; | |
735 | u8 reserved3; | |
736 | __be16 reserved4; | |
737 | }__attribute__((packed, aligned (4))); | |
738 | ||
739 | struct ipr_mode_page28 { | |
740 | struct ipr_mode_page_hdr hdr; | |
741 | u8 num_entries; | |
742 | u8 entry_length; | |
5febf6d6 | 743 | struct ipr_dev_bus_entry bus[]; |
1da177e4 LT |
744 | }__attribute__((packed)); |
745 | ||
ac09c349 BK |
746 | struct ipr_mode_page24 { |
747 | struct ipr_mode_page_hdr hdr; | |
748 | u8 flags; | |
749 | #define IPR_ENABLE_DUAL_IOA_AF 0x80 | |
750 | }__attribute__((packed)); | |
751 | ||
1da177e4 LT |
752 | struct ipr_ioa_vpd { |
753 | struct ipr_std_inq_data std_inq_data; | |
754 | u8 ascii_part_num[12]; | |
755 | u8 reserved[40]; | |
756 | u8 ascii_plant_code[4]; | |
757 | }__attribute__((packed)); | |
758 | ||
759 | struct ipr_inquiry_page3 { | |
760 | u8 peri_qual_dev_type; | |
761 | u8 page_code; | |
762 | u8 reserved1; | |
763 | u8 page_length; | |
764 | u8 ascii_len; | |
765 | u8 reserved2[3]; | |
766 | u8 load_id[4]; | |
767 | u8 major_release; | |
768 | u8 card_type; | |
769 | u8 minor_release[2]; | |
770 | u8 ptf_number[4]; | |
771 | u8 patch_number[4]; | |
772 | }__attribute__((packed)); | |
773 | ||
ac09c349 BK |
774 | struct ipr_inquiry_cap { |
775 | u8 peri_qual_dev_type; | |
776 | u8 page_code; | |
777 | u8 reserved1; | |
778 | u8 page_length; | |
779 | u8 ascii_len; | |
780 | u8 reserved2; | |
781 | u8 sis_version[2]; | |
782 | u8 cap; | |
783 | #define IPR_CAP_DUAL_IOA_RAID 0x80 | |
784 | u8 reserved3[15]; | |
785 | }__attribute__((packed)); | |
786 | ||
62275040 | 787 | #define IPR_INQUIRY_PAGE0_ENTRIES 20 |
788 | struct ipr_inquiry_page0 { | |
789 | u8 peri_qual_dev_type; | |
790 | u8 page_code; | |
791 | u8 reserved1; | |
792 | u8 len; | |
793 | u8 page[IPR_INQUIRY_PAGE0_ENTRIES]; | |
794 | }__attribute__((packed)); | |
795 | ||
1021b3ff GKB |
796 | struct ipr_inquiry_pageC4 { |
797 | u8 peri_qual_dev_type; | |
798 | u8 page_code; | |
799 | u8 reserved1; | |
800 | u8 len; | |
801 | u8 cache_cap[4]; | |
802 | #define IPR_CAP_SYNC_CACHE 0x08 | |
803 | u8 reserved2[20]; | |
804 | } __packed; | |
805 | ||
1da177e4 | 806 | struct ipr_hostrcb_device_data_entry { |
cfc32139 | 807 | struct ipr_vpd vpd; |
1da177e4 | 808 | struct ipr_res_addr dev_res_addr; |
cfc32139 | 809 | struct ipr_vpd new_vpd; |
810 | struct ipr_vpd ioa_last_with_dev_vpd; | |
811 | struct ipr_vpd cfc_last_with_dev_vpd; | |
1da177e4 LT |
812 | __be32 ioa_data[5]; |
813 | }__attribute__((packed, aligned (4))); | |
814 | ||
ee0f05b8 | 815 | struct ipr_hostrcb_device_data_entry_enhanced { |
816 | struct ipr_ext_vpd vpd; | |
817 | u8 ccin[4]; | |
818 | struct ipr_res_addr dev_res_addr; | |
819 | struct ipr_ext_vpd new_vpd; | |
820 | u8 new_ccin[4]; | |
821 | struct ipr_ext_vpd ioa_last_with_dev_vpd; | |
822 | struct ipr_ext_vpd cfc_last_with_dev_vpd; | |
823 | }__attribute__((packed, aligned (4))); | |
824 | ||
4565e370 WB |
825 | struct ipr_hostrcb64_device_data_entry_enhanced { |
826 | struct ipr_ext_vpd vpd; | |
827 | u8 ccin[4]; | |
828 | u8 res_path[8]; | |
829 | struct ipr_ext_vpd new_vpd; | |
830 | u8 new_ccin[4]; | |
831 | struct ipr_ext_vpd ioa_last_with_dev_vpd; | |
832 | struct ipr_ext_vpd cfc_last_with_dev_vpd; | |
833 | }__attribute__((packed, aligned (4))); | |
834 | ||
1da177e4 | 835 | struct ipr_hostrcb_array_data_entry { |
cfc32139 | 836 | struct ipr_vpd vpd; |
1da177e4 LT |
837 | struct ipr_res_addr expected_dev_res_addr; |
838 | struct ipr_res_addr dev_res_addr; | |
839 | }__attribute__((packed, aligned (4))); | |
840 | ||
4565e370 WB |
841 | struct ipr_hostrcb64_array_data_entry { |
842 | struct ipr_ext_vpd vpd; | |
843 | u8 ccin[4]; | |
844 | u8 expected_res_path[8]; | |
845 | u8 res_path[8]; | |
846 | }__attribute__((packed, aligned (4))); | |
847 | ||
ee0f05b8 | 848 | struct ipr_hostrcb_array_data_entry_enhanced { |
849 | struct ipr_ext_vpd vpd; | |
850 | u8 ccin[4]; | |
851 | struct ipr_res_addr expected_dev_res_addr; | |
852 | struct ipr_res_addr dev_res_addr; | |
853 | }__attribute__((packed, aligned (4))); | |
854 | ||
1da177e4 | 855 | struct ipr_hostrcb_type_ff_error { |
438b0331 | 856 | __be32 ioa_data[758]; |
1da177e4 LT |
857 | }__attribute__((packed, aligned (4))); |
858 | ||
859 | struct ipr_hostrcb_type_01_error { | |
860 | __be32 seek_counter; | |
861 | __be32 read_counter; | |
862 | u8 sense_data[32]; | |
863 | __be32 ioa_data[236]; | |
864 | }__attribute__((packed, aligned (4))); | |
865 | ||
169b9ec8 WX |
866 | struct ipr_hostrcb_type_21_error { |
867 | __be32 wwn[4]; | |
868 | u8 res_path[8]; | |
869 | u8 primary_problem_desc[32]; | |
870 | u8 second_problem_desc[32]; | |
871 | __be32 sense_data[8]; | |
872 | __be32 cdb[4]; | |
873 | __be32 residual_trans_length; | |
874 | __be32 length_of_error; | |
875 | __be32 ioa_data[236]; | |
876 | }__attribute__((packed, aligned (4))); | |
877 | ||
1da177e4 | 878 | struct ipr_hostrcb_type_02_error { |
cfc32139 | 879 | struct ipr_vpd ioa_vpd; |
880 | struct ipr_vpd cfc_vpd; | |
881 | struct ipr_vpd ioa_last_attached_to_cfc_vpd; | |
882 | struct ipr_vpd cfc_last_attached_to_ioa_vpd; | |
1da177e4 | 883 | __be32 ioa_data[3]; |
1da177e4 LT |
884 | }__attribute__((packed, aligned (4))); |
885 | ||
ee0f05b8 | 886 | struct ipr_hostrcb_type_12_error { |
887 | struct ipr_ext_vpd ioa_vpd; | |
888 | struct ipr_ext_vpd cfc_vpd; | |
889 | struct ipr_ext_vpd ioa_last_attached_to_cfc_vpd; | |
890 | struct ipr_ext_vpd cfc_last_attached_to_ioa_vpd; | |
891 | __be32 ioa_data[3]; | |
892 | }__attribute__((packed, aligned (4))); | |
893 | ||
1da177e4 | 894 | struct ipr_hostrcb_type_03_error { |
cfc32139 | 895 | struct ipr_vpd ioa_vpd; |
896 | struct ipr_vpd cfc_vpd; | |
1da177e4 LT |
897 | __be32 errors_detected; |
898 | __be32 errors_logged; | |
899 | u8 ioa_data[12]; | |
cfc32139 | 900 | struct ipr_hostrcb_device_data_entry dev[3]; |
1da177e4 LT |
901 | }__attribute__((packed, aligned (4))); |
902 | ||
ee0f05b8 | 903 | struct ipr_hostrcb_type_13_error { |
904 | struct ipr_ext_vpd ioa_vpd; | |
905 | struct ipr_ext_vpd cfc_vpd; | |
906 | __be32 errors_detected; | |
907 | __be32 errors_logged; | |
908 | struct ipr_hostrcb_device_data_entry_enhanced dev[3]; | |
909 | }__attribute__((packed, aligned (4))); | |
910 | ||
4565e370 WB |
911 | struct ipr_hostrcb_type_23_error { |
912 | struct ipr_ext_vpd ioa_vpd; | |
913 | struct ipr_ext_vpd cfc_vpd; | |
914 | __be32 errors_detected; | |
915 | __be32 errors_logged; | |
916 | struct ipr_hostrcb64_device_data_entry_enhanced dev[3]; | |
917 | }__attribute__((packed, aligned (4))); | |
918 | ||
1da177e4 | 919 | struct ipr_hostrcb_type_04_error { |
cfc32139 | 920 | struct ipr_vpd ioa_vpd; |
921 | struct ipr_vpd cfc_vpd; | |
1da177e4 LT |
922 | u8 ioa_data[12]; |
923 | struct ipr_hostrcb_array_data_entry array_member[10]; | |
924 | __be32 exposed_mode_adn; | |
925 | __be32 array_id; | |
cfc32139 | 926 | struct ipr_vpd incomp_dev_vpd; |
1da177e4 LT |
927 | __be32 ioa_data2; |
928 | struct ipr_hostrcb_array_data_entry array_member2[8]; | |
929 | struct ipr_res_addr last_func_vset_res_addr; | |
930 | u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; | |
931 | u8 protection_level[8]; | |
1da177e4 LT |
932 | }__attribute__((packed, aligned (4))); |
933 | ||
ee0f05b8 | 934 | struct ipr_hostrcb_type_14_error { |
935 | struct ipr_ext_vpd ioa_vpd; | |
936 | struct ipr_ext_vpd cfc_vpd; | |
937 | __be32 exposed_mode_adn; | |
938 | __be32 array_id; | |
939 | struct ipr_res_addr last_func_vset_res_addr; | |
940 | u8 vset_serial_num[IPR_SERIAL_NUM_LEN]; | |
941 | u8 protection_level[8]; | |
942 | __be32 num_entries; | |
943 | struct ipr_hostrcb_array_data_entry_enhanced array_member[18]; | |
944 | }__attribute__((packed, aligned (4))); | |
945 | ||
4565e370 WB |
946 | struct ipr_hostrcb_type_24_error { |
947 | struct ipr_ext_vpd ioa_vpd; | |
948 | struct ipr_ext_vpd cfc_vpd; | |
949 | u8 reserved[2]; | |
950 | u8 exposed_mode_adn; | |
951 | #define IPR_INVALID_ARRAY_DEV_NUM 0xff | |
952 | u8 array_id; | |
953 | u8 last_res_path[8]; | |
954 | u8 protection_level[8]; | |
7262026f | 955 | struct ipr_ext_vpd64 array_vpd; |
4565e370 WB |
956 | u8 description[16]; |
957 | u8 reserved2[3]; | |
958 | u8 num_entries; | |
959 | struct ipr_hostrcb64_array_data_entry array_member[32]; | |
960 | }__attribute__((packed, aligned (4))); | |
961 | ||
b0df54bb | 962 | struct ipr_hostrcb_type_07_error { |
963 | u8 failure_reason[64]; | |
964 | struct ipr_vpd vpd; | |
359d96e7 | 965 | __be32 data[222]; |
b0df54bb | 966 | }__attribute__((packed, aligned (4))); |
967 | ||
ee0f05b8 | 968 | struct ipr_hostrcb_type_17_error { |
969 | u8 failure_reason[64]; | |
970 | struct ipr_ext_vpd vpd; | |
359d96e7 | 971 | __be32 data[476]; |
ee0f05b8 | 972 | }__attribute__((packed, aligned (4))); |
973 | ||
49dc6a18 BK |
974 | struct ipr_hostrcb_config_element { |
975 | u8 type_status; | |
976 | #define IPR_PATH_CFG_TYPE_MASK 0xF0 | |
977 | #define IPR_PATH_CFG_NOT_EXIST 0x00 | |
978 | #define IPR_PATH_CFG_IOA_PORT 0x10 | |
979 | #define IPR_PATH_CFG_EXP_PORT 0x20 | |
980 | #define IPR_PATH_CFG_DEVICE_PORT 0x30 | |
981 | #define IPR_PATH_CFG_DEVICE_LUN 0x40 | |
982 | ||
983 | #define IPR_PATH_CFG_STATUS_MASK 0x0F | |
984 | #define IPR_PATH_CFG_NO_PROB 0x00 | |
985 | #define IPR_PATH_CFG_DEGRADED 0x01 | |
986 | #define IPR_PATH_CFG_FAILED 0x02 | |
987 | #define IPR_PATH_CFG_SUSPECT 0x03 | |
988 | #define IPR_PATH_NOT_DETECTED 0x04 | |
989 | #define IPR_PATH_INCORRECT_CONN 0x05 | |
990 | ||
991 | u8 cascaded_expander; | |
992 | u8 phy; | |
993 | u8 link_rate; | |
994 | #define IPR_PHY_LINK_RATE_MASK 0x0F | |
995 | ||
996 | __be32 wwid[2]; | |
997 | }__attribute__((packed, aligned (4))); | |
998 | ||
4565e370 WB |
999 | struct ipr_hostrcb64_config_element { |
1000 | __be16 length; | |
1001 | u8 descriptor_id; | |
1002 | #define IPR_DESCRIPTOR_MASK 0xC0 | |
1003 | #define IPR_DESCRIPTOR_SIS64 0x00 | |
1004 | ||
1005 | u8 reserved; | |
1006 | u8 type_status; | |
1007 | ||
1008 | u8 reserved2[2]; | |
1009 | u8 link_rate; | |
1010 | ||
1011 | u8 res_path[8]; | |
1012 | __be32 wwid[2]; | |
1013 | }__attribute__((packed, aligned (8))); | |
1014 | ||
49dc6a18 BK |
1015 | struct ipr_hostrcb_fabric_desc { |
1016 | __be16 length; | |
1017 | u8 ioa_port; | |
1018 | u8 cascaded_expander; | |
1019 | u8 phy; | |
1020 | u8 path_state; | |
1021 | #define IPR_PATH_ACTIVE_MASK 0xC0 | |
1022 | #define IPR_PATH_NO_INFO 0x00 | |
1023 | #define IPR_PATH_ACTIVE 0x40 | |
1024 | #define IPR_PATH_NOT_ACTIVE 0x80 | |
1025 | ||
1026 | #define IPR_PATH_STATE_MASK 0x0F | |
1027 | #define IPR_PATH_STATE_NO_INFO 0x00 | |
1028 | #define IPR_PATH_HEALTHY 0x01 | |
1029 | #define IPR_PATH_DEGRADED 0x02 | |
1030 | #define IPR_PATH_FAILED 0x03 | |
1031 | ||
1032 | __be16 num_entries; | |
1033 | struct ipr_hostrcb_config_element elem[1]; | |
1034 | }__attribute__((packed, aligned (4))); | |
1035 | ||
4565e370 WB |
1036 | struct ipr_hostrcb64_fabric_desc { |
1037 | __be16 length; | |
1038 | u8 descriptor_id; | |
1039 | ||
8701f185 | 1040 | u8 reserved[2]; |
4565e370 WB |
1041 | u8 path_state; |
1042 | ||
1043 | u8 reserved2[2]; | |
1044 | u8 res_path[8]; | |
1045 | u8 reserved3[6]; | |
1046 | __be16 num_entries; | |
1047 | struct ipr_hostrcb64_config_element elem[1]; | |
1048 | }__attribute__((packed, aligned (8))); | |
1049 | ||
56d6aa33 | 1050 | #define for_each_hrrq(hrrq, ioa_cfg) \ |
1051 | for (hrrq = (ioa_cfg)->hrrq; \ | |
1052 | hrrq < ((ioa_cfg)->hrrq + (ioa_cfg)->hrrq_num); hrrq++) | |
1053 | ||
49dc6a18 BK |
1054 | #define for_each_fabric_cfg(fabric, cfg) \ |
1055 | for (cfg = (fabric)->elem; \ | |
1056 | cfg < ((fabric)->elem + be16_to_cpu((fabric)->num_entries)); \ | |
1057 | cfg++) | |
1058 | ||
1059 | struct ipr_hostrcb_type_20_error { | |
1060 | u8 failure_reason[64]; | |
1061 | u8 reserved[3]; | |
1062 | u8 num_entries; | |
1063 | struct ipr_hostrcb_fabric_desc desc[1]; | |
1064 | }__attribute__((packed, aligned (4))); | |
1065 | ||
4565e370 WB |
1066 | struct ipr_hostrcb_type_30_error { |
1067 | u8 failure_reason[64]; | |
1068 | u8 reserved[3]; | |
1069 | u8 num_entries; | |
1070 | struct ipr_hostrcb64_fabric_desc desc[1]; | |
1071 | }__attribute__((packed, aligned (4))); | |
1072 | ||
15c5a5e0 WX |
1073 | struct ipr_hostrcb_type_41_error { |
1074 | u8 failure_reason[64]; | |
1075 | __be32 data[200]; | |
1076 | }__attribute__((packed, aligned (4))); | |
1077 | ||
1da177e4 | 1078 | struct ipr_hostrcb_error { |
4565e370 WB |
1079 | __be32 fd_ioasc; |
1080 | struct ipr_res_addr fd_res_addr; | |
1081 | __be32 fd_res_handle; | |
1da177e4 LT |
1082 | __be32 prc; |
1083 | union { | |
1084 | struct ipr_hostrcb_type_ff_error type_ff_error; | |
1085 | struct ipr_hostrcb_type_01_error type_01_error; | |
1086 | struct ipr_hostrcb_type_02_error type_02_error; | |
1087 | struct ipr_hostrcb_type_03_error type_03_error; | |
1088 | struct ipr_hostrcb_type_04_error type_04_error; | |
b0df54bb | 1089 | struct ipr_hostrcb_type_07_error type_07_error; |
ee0f05b8 | 1090 | struct ipr_hostrcb_type_12_error type_12_error; |
1091 | struct ipr_hostrcb_type_13_error type_13_error; | |
1092 | struct ipr_hostrcb_type_14_error type_14_error; | |
1093 | struct ipr_hostrcb_type_17_error type_17_error; | |
49dc6a18 | 1094 | struct ipr_hostrcb_type_20_error type_20_error; |
1da177e4 LT |
1095 | } u; |
1096 | }__attribute__((packed, aligned (4))); | |
1097 | ||
4565e370 WB |
1098 | struct ipr_hostrcb64_error { |
1099 | __be32 fd_ioasc; | |
1100 | __be32 ioa_fw_level; | |
1101 | __be32 fd_res_handle; | |
1102 | __be32 prc; | |
1103 | __be64 fd_dev_id; | |
1104 | __be64 fd_lun; | |
1105 | u8 fd_res_path[8]; | |
1106 | __be64 time_stamp; | |
8701f185 | 1107 | u8 reserved[16]; |
4565e370 WB |
1108 | union { |
1109 | struct ipr_hostrcb_type_ff_error type_ff_error; | |
1110 | struct ipr_hostrcb_type_12_error type_12_error; | |
1111 | struct ipr_hostrcb_type_17_error type_17_error; | |
169b9ec8 | 1112 | struct ipr_hostrcb_type_21_error type_21_error; |
4565e370 WB |
1113 | struct ipr_hostrcb_type_23_error type_23_error; |
1114 | struct ipr_hostrcb_type_24_error type_24_error; | |
1115 | struct ipr_hostrcb_type_30_error type_30_error; | |
15c5a5e0 | 1116 | struct ipr_hostrcb_type_41_error type_41_error; |
4565e370 WB |
1117 | } u; |
1118 | }__attribute__((packed, aligned (8))); | |
1119 | ||
1da177e4 LT |
1120 | struct ipr_hostrcb_raw { |
1121 | __be32 data[sizeof(struct ipr_hostrcb_error)/sizeof(__be32)]; | |
1122 | }__attribute__((packed, aligned (4))); | |
1123 | ||
1124 | struct ipr_hcam { | |
1125 | u8 op_code; | |
1126 | #define IPR_HOST_RCB_OP_CODE_CONFIG_CHANGE 0xE1 | |
1127 | #define IPR_HOST_RCB_OP_CODE_LOG_DATA 0xE2 | |
1128 | ||
1129 | u8 notify_type; | |
1130 | #define IPR_HOST_RCB_NOTIF_TYPE_EXISTING_CHANGED 0x00 | |
1131 | #define IPR_HOST_RCB_NOTIF_TYPE_NEW_ENTRY 0x01 | |
1132 | #define IPR_HOST_RCB_NOTIF_TYPE_REM_ENTRY 0x02 | |
1133 | #define IPR_HOST_RCB_NOTIF_TYPE_ERROR_LOG_ENTRY 0x10 | |
1134 | #define IPR_HOST_RCB_NOTIF_TYPE_INFORMATION_ENTRY 0x11 | |
1135 | ||
1136 | u8 notifications_lost; | |
1137 | #define IPR_HOST_RCB_NO_NOTIFICATIONS_LOST 0 | |
1138 | #define IPR_HOST_RCB_NOTIFICATIONS_LOST 0x80 | |
1139 | ||
1140 | u8 flags; | |
1141 | #define IPR_HOSTRCB_INTERNAL_OPER 0x80 | |
1142 | #define IPR_HOSTRCB_ERR_RESP_SENT 0x40 | |
1143 | ||
1144 | u8 overlay_id; | |
1145 | #define IPR_HOST_RCB_OVERLAY_ID_1 0x01 | |
1146 | #define IPR_HOST_RCB_OVERLAY_ID_2 0x02 | |
1147 | #define IPR_HOST_RCB_OVERLAY_ID_3 0x03 | |
1148 | #define IPR_HOST_RCB_OVERLAY_ID_4 0x04 | |
1149 | #define IPR_HOST_RCB_OVERLAY_ID_6 0x06 | |
b0df54bb | 1150 | #define IPR_HOST_RCB_OVERLAY_ID_7 0x07 |
ee0f05b8 | 1151 | #define IPR_HOST_RCB_OVERLAY_ID_12 0x12 |
1152 | #define IPR_HOST_RCB_OVERLAY_ID_13 0x13 | |
1153 | #define IPR_HOST_RCB_OVERLAY_ID_14 0x14 | |
1154 | #define IPR_HOST_RCB_OVERLAY_ID_16 0x16 | |
1155 | #define IPR_HOST_RCB_OVERLAY_ID_17 0x17 | |
49dc6a18 | 1156 | #define IPR_HOST_RCB_OVERLAY_ID_20 0x20 |
169b9ec8 | 1157 | #define IPR_HOST_RCB_OVERLAY_ID_21 0x21 |
4565e370 WB |
1158 | #define IPR_HOST_RCB_OVERLAY_ID_23 0x23 |
1159 | #define IPR_HOST_RCB_OVERLAY_ID_24 0x24 | |
1160 | #define IPR_HOST_RCB_OVERLAY_ID_26 0x26 | |
1161 | #define IPR_HOST_RCB_OVERLAY_ID_30 0x30 | |
15c5a5e0 | 1162 | #define IPR_HOST_RCB_OVERLAY_ID_41 0x41 |
4565e370 | 1163 | #define IPR_HOST_RCB_OVERLAY_ID_DEFAULT 0xFF |
1da177e4 LT |
1164 | |
1165 | u8 reserved1[3]; | |
1166 | __be32 ilid; | |
1167 | __be32 time_since_last_ioa_reset; | |
1168 | __be32 reserved2; | |
1169 | __be32 length; | |
1170 | ||
1171 | union { | |
1172 | struct ipr_hostrcb_error error; | |
4565e370 | 1173 | struct ipr_hostrcb64_error error64; |
1da177e4 LT |
1174 | struct ipr_hostrcb_cfg_ch_not ccn; |
1175 | struct ipr_hostrcb_raw raw; | |
1176 | } u; | |
1177 | }__attribute__((packed, aligned (4))); | |
1178 | ||
1179 | struct ipr_hostrcb { | |
1180 | struct ipr_hcam hcam; | |
1181 | dma_addr_t hostrcb_dma; | |
1182 | struct list_head queue; | |
49dc6a18 | 1183 | struct ipr_ioa_cfg *ioa_cfg; |
4565e370 | 1184 | char rp_buffer[IPR_MAX_RES_PATH_LENGTH]; |
1da177e4 LT |
1185 | }; |
1186 | ||
1187 | /* IPR smart dump table structures */ | |
1188 | struct ipr_sdt_entry { | |
dcbad00e WB |
1189 | __be32 start_token; |
1190 | __be32 end_token; | |
1191 | u8 reserved[4]; | |
1da177e4 LT |
1192 | |
1193 | u8 flags; | |
1194 | #define IPR_SDT_ENDIAN 0x80 | |
1195 | #define IPR_SDT_VALID_ENTRY 0x20 | |
1196 | ||
1197 | u8 resv; | |
1198 | __be16 priority; | |
1199 | }__attribute__((packed, aligned (4))); | |
1200 | ||
1201 | struct ipr_sdt_header { | |
1202 | __be32 state; | |
1203 | __be32 num_entries; | |
1204 | __be32 num_entries_used; | |
1205 | __be32 dump_size; | |
1206 | }__attribute__((packed, aligned (4))); | |
1207 | ||
1208 | struct ipr_sdt { | |
1209 | struct ipr_sdt_header hdr; | |
4d4dd706 | 1210 | struct ipr_sdt_entry entry[IPR_FMT3_NUM_SDT_ENTRIES]; |
1da177e4 LT |
1211 | }__attribute__((packed, aligned (4))); |
1212 | ||
1213 | struct ipr_uc_sdt { | |
1214 | struct ipr_sdt_header hdr; | |
1215 | struct ipr_sdt_entry entry[1]; | |
1216 | }__attribute__((packed, aligned (4))); | |
1217 | ||
1218 | /* | |
1219 | * Driver types | |
1220 | */ | |
1221 | struct ipr_bus_attributes { | |
1222 | u8 bus; | |
1223 | u8 qas_enabled; | |
1224 | u8 bus_width; | |
1225 | u8 reserved; | |
1226 | u32 max_xfer_rate; | |
1227 | }; | |
1228 | ||
1229 | struct ipr_resource_entry { | |
1da177e4 LT |
1230 | u8 needs_sync_complete:1; |
1231 | u8 in_erp:1; | |
1232 | u8 add_to_ml:1; | |
1233 | u8 del_from_ml:1; | |
1234 | u8 resetting_device:1; | |
0b1f8d44 | 1235 | u8 reset_occurred:1; |
f8ee25d7 | 1236 | u8 raw_mode:1; |
1da177e4 | 1237 | |
3e7ebdfa WB |
1238 | u32 bus; /* AKA channel */ |
1239 | u32 target; /* AKA id */ | |
1240 | u32 lun; | |
1241 | #define IPR_ARRAY_VIRTUAL_BUS 0x1 | |
1242 | #define IPR_VSET_VIRTUAL_BUS 0x2 | |
1243 | #define IPR_IOAFP_VIRTUAL_BUS 0x3 | |
394b6171 | 1244 | #define IPR_MAX_SIS64_BUSES 0x4 |
3e7ebdfa WB |
1245 | |
1246 | #define IPR_GET_RES_PHYS_LOC(res) \ | |
1247 | (((res)->bus << 24) | ((res)->target << 8) | (res)->lun) | |
1248 | ||
1249 | u8 ata_class; | |
7be96900 | 1250 | u8 type; |
3e7ebdfa | 1251 | |
359d96e7 BK |
1252 | u16 flags; |
1253 | u16 res_flags; | |
1254 | ||
3e7ebdfa WB |
1255 | u8 qmodel; |
1256 | struct ipr_std_inq_data std_inq_data; | |
1257 | ||
1258 | __be32 res_handle; | |
1259 | __be64 dev_id; | |
359d96e7 | 1260 | u64 lun_wwn; |
3e7ebdfa WB |
1261 | struct scsi_lun dev_lun; |
1262 | u8 res_path[8]; | |
1263 | ||
1264 | struct ipr_ioa_cfg *ioa_cfg; | |
1da177e4 LT |
1265 | struct scsi_device *sdev; |
1266 | struct list_head queue; | |
3e7ebdfa | 1267 | }; /* struct ipr_resource_entry */ |
1da177e4 LT |
1268 | |
1269 | struct ipr_resource_hdr { | |
1270 | u16 num_entries; | |
1271 | u16 reserved; | |
1272 | }; | |
1273 | ||
1da177e4 LT |
1274 | struct ipr_misc_cbs { |
1275 | struct ipr_ioa_vpd ioa_vpd; | |
62275040 | 1276 | struct ipr_inquiry_page0 page0_data; |
1da177e4 | 1277 | struct ipr_inquiry_page3 page3_data; |
ac09c349 | 1278 | struct ipr_inquiry_cap cap; |
1021b3ff | 1279 | struct ipr_inquiry_pageC4 pageC4_data; |
1da177e4 LT |
1280 | struct ipr_mode_pages mode_pages; |
1281 | struct ipr_supported_device supp_dev; | |
1282 | }; | |
1283 | ||
1284 | struct ipr_interrupt_offsets { | |
1285 | unsigned long set_interrupt_mask_reg; | |
1286 | unsigned long clr_interrupt_mask_reg; | |
214777ba | 1287 | unsigned long clr_interrupt_mask_reg32; |
1da177e4 | 1288 | unsigned long sense_interrupt_mask_reg; |
214777ba | 1289 | unsigned long sense_interrupt_mask_reg32; |
1da177e4 | 1290 | unsigned long clr_interrupt_reg; |
214777ba | 1291 | unsigned long clr_interrupt_reg32; |
1da177e4 LT |
1292 | |
1293 | unsigned long sense_interrupt_reg; | |
214777ba | 1294 | unsigned long sense_interrupt_reg32; |
1da177e4 LT |
1295 | unsigned long ioarrin_reg; |
1296 | unsigned long sense_uproc_interrupt_reg; | |
214777ba | 1297 | unsigned long sense_uproc_interrupt_reg32; |
1da177e4 | 1298 | unsigned long set_uproc_interrupt_reg; |
214777ba | 1299 | unsigned long set_uproc_interrupt_reg32; |
1da177e4 | 1300 | unsigned long clr_uproc_interrupt_reg; |
214777ba WB |
1301 | unsigned long clr_uproc_interrupt_reg32; |
1302 | ||
1303 | unsigned long init_feedback_reg; | |
dcbad00e WB |
1304 | |
1305 | unsigned long dump_addr_reg; | |
1306 | unsigned long dump_data_reg; | |
8701f185 | 1307 | |
4289a086 | 1308 | #define IPR_ENDIAN_SWAP_KEY 0x00080800 |
8701f185 | 1309 | unsigned long endian_swap_reg; |
1da177e4 LT |
1310 | }; |
1311 | ||
1312 | struct ipr_interrupts { | |
1313 | void __iomem *set_interrupt_mask_reg; | |
1314 | void __iomem *clr_interrupt_mask_reg; | |
214777ba | 1315 | void __iomem *clr_interrupt_mask_reg32; |
1da177e4 | 1316 | void __iomem *sense_interrupt_mask_reg; |
214777ba | 1317 | void __iomem *sense_interrupt_mask_reg32; |
1da177e4 | 1318 | void __iomem *clr_interrupt_reg; |
214777ba | 1319 | void __iomem *clr_interrupt_reg32; |
1da177e4 LT |
1320 | |
1321 | void __iomem *sense_interrupt_reg; | |
214777ba | 1322 | void __iomem *sense_interrupt_reg32; |
1da177e4 LT |
1323 | void __iomem *ioarrin_reg; |
1324 | void __iomem *sense_uproc_interrupt_reg; | |
214777ba | 1325 | void __iomem *sense_uproc_interrupt_reg32; |
1da177e4 | 1326 | void __iomem *set_uproc_interrupt_reg; |
214777ba | 1327 | void __iomem *set_uproc_interrupt_reg32; |
1da177e4 | 1328 | void __iomem *clr_uproc_interrupt_reg; |
214777ba WB |
1329 | void __iomem *clr_uproc_interrupt_reg32; |
1330 | ||
1331 | void __iomem *init_feedback_reg; | |
dcbad00e WB |
1332 | |
1333 | void __iomem *dump_addr_reg; | |
1334 | void __iomem *dump_data_reg; | |
8701f185 WB |
1335 | |
1336 | void __iomem *endian_swap_reg; | |
1da177e4 LT |
1337 | }; |
1338 | ||
1339 | struct ipr_chip_cfg_t { | |
1340 | u32 mailbox; | |
89aad428 | 1341 | u16 max_cmds; |
1da177e4 | 1342 | u8 cache_line_size; |
7dd21308 | 1343 | u8 clear_isr; |
b53d124a | 1344 | u32 iopoll_weight; |
1da177e4 LT |
1345 | struct ipr_interrupt_offsets regs; |
1346 | }; | |
1347 | ||
1348 | struct ipr_chip_t { | |
1349 | u16 vendor; | |
1350 | u16 device; | |
a299ee62 | 1351 | bool has_msi; |
a32c055f WB |
1352 | u16 sis_type; |
1353 | #define IPR_SIS32 0x00 | |
1354 | #define IPR_SIS64 0x01 | |
cb237ef7 WB |
1355 | u16 bist_method; |
1356 | #define IPR_PCI_CFG 0x00 | |
1357 | #define IPR_MMIO 0x01 | |
1da177e4 LT |
1358 | const struct ipr_chip_cfg_t *cfg; |
1359 | }; | |
1360 | ||
1361 | enum ipr_shutdown_type { | |
1362 | IPR_SHUTDOWN_NORMAL = 0x00, | |
1363 | IPR_SHUTDOWN_PREPARE_FOR_NORMAL = 0x40, | |
1364 | IPR_SHUTDOWN_ABBREV = 0x80, | |
4fdd7c7a BK |
1365 | IPR_SHUTDOWN_NONE = 0x100, |
1366 | IPR_SHUTDOWN_QUIESCE = 0x101, | |
1da177e4 LT |
1367 | }; |
1368 | ||
1369 | struct ipr_trace_entry { | |
1370 | u32 time; | |
1371 | ||
1372 | u8 op_code; | |
35a39691 | 1373 | u8 ata_op_code; |
1da177e4 LT |
1374 | u8 type; |
1375 | #define IPR_TRACE_START 0x00 | |
1376 | #define IPR_TRACE_FINISH 0xff | |
35a39691 | 1377 | u8 cmd_index; |
1da177e4 LT |
1378 | |
1379 | __be32 res_handle; | |
1380 | union { | |
1381 | u32 ioasc; | |
1382 | u32 add_data; | |
1383 | u32 res_addr; | |
1384 | } u; | |
1385 | }; | |
1386 | ||
1387 | struct ipr_sglist { | |
1388 | u32 order; | |
1389 | u32 num_sg; | |
12baa420 | 1390 | u32 num_dma_sg; |
1da177e4 | 1391 | u32 buffer_len; |
f95dc1bb | 1392 | struct scatterlist *scatterlist; |
1da177e4 LT |
1393 | }; |
1394 | ||
1395 | enum ipr_sdt_state { | |
1396 | INACTIVE, | |
1397 | WAIT_FOR_DUMP, | |
1398 | GET_DUMP, | |
41e9a696 | 1399 | READ_DUMP, |
1da177e4 LT |
1400 | ABORT_DUMP, |
1401 | DUMP_OBTAINED | |
1402 | }; | |
1403 | ||
1404 | /* Per-controller data */ | |
1405 | struct ipr_ioa_cfg { | |
1406 | char eye_catcher[8]; | |
1407 | #define IPR_EYECATCHER "iprcfg" | |
1408 | ||
1409 | struct list_head queue; | |
1410 | ||
1da177e4 LT |
1411 | u8 in_reset_reload:1; |
1412 | u8 in_ioa_bringdown:1; | |
1413 | u8 ioa_unit_checked:1; | |
1da177e4 | 1414 | u8 dump_taken:1; |
b195d5e2 | 1415 | u8 scan_enabled:1; |
f688f96d | 1416 | u8 scan_done:1; |
ce155cce | 1417 | u8 needs_hard_reset:1; |
ac09c349 | 1418 | u8 dual_raid:1; |
463fc696 | 1419 | u8 needs_warm_reset:1; |
95fecd90 | 1420 | u8 msi_received:1; |
a32c055f | 1421 | u8 sis64:1; |
4c647e90 | 1422 | u8 dump_timeout:1; |
fb51ccbf | 1423 | u8 cfg_locked:1; |
7dd21308 | 1424 | u8 clear_isr:1; |
6270e593 | 1425 | u8 probe_done:1; |
b0e17a9b BK |
1426 | u8 scsi_unblock:1; |
1427 | u8 scsi_blocked:1; | |
463fc696 BK |
1428 | |
1429 | u8 revid; | |
1da177e4 | 1430 | |
3e7ebdfa WB |
1431 | /* |
1432 | * Bitmaps for SIS64 generated target values | |
1433 | */ | |
222ab594 | 1434 | unsigned long target_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)]; |
1435 | unsigned long array_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)]; | |
1436 | unsigned long vset_ids[BITS_TO_LONGS(IPR_MAX_SIS64_DEVS)]; | |
3e7ebdfa | 1437 | |
1da177e4 LT |
1438 | u16 type; /* CCIN of the card */ |
1439 | ||
1440 | u8 log_level; | |
1441 | #define IPR_MAX_LOG_LEVEL 4 | |
1442 | #define IPR_DEFAULT_LOG_LEVEL 2 | |
7b3871fd | 1443 | #define IPR_DEBUG_LOG_LEVEL 3 |
1da177e4 LT |
1444 | |
1445 | #define IPR_NUM_TRACE_INDEX_BITS 8 | |
1446 | #define IPR_NUM_TRACE_ENTRIES (1 << IPR_NUM_TRACE_INDEX_BITS) | |
bb7c5433 | 1447 | #define IPR_TRACE_INDEX_MASK (IPR_NUM_TRACE_ENTRIES - 1) |
1da177e4 LT |
1448 | #define IPR_TRACE_SIZE (sizeof(struct ipr_trace_entry) * IPR_NUM_TRACE_ENTRIES) |
1449 | char trace_start[8]; | |
1450 | #define IPR_TRACE_START_LABEL "trace" | |
1451 | struct ipr_trace_entry *trace; | |
56d6aa33 | 1452 | atomic_t trace_index; |
1da177e4 | 1453 | |
1da177e4 LT |
1454 | char cfg_table_start[8]; |
1455 | #define IPR_CFG_TBL_START "cfg" | |
3e7ebdfa WB |
1456 | union { |
1457 | struct ipr_config_table *cfg_table; | |
1458 | struct ipr_config_table64 *cfg_table64; | |
1459 | } u; | |
1da177e4 | 1460 | dma_addr_t cfg_table_dma; |
3e7ebdfa WB |
1461 | u32 cfg_table_size; |
1462 | u32 max_devs_supported; | |
1da177e4 LT |
1463 | |
1464 | char resource_table_label[8]; | |
1465 | #define IPR_RES_TABLE_LABEL "res_tbl" | |
1466 | struct ipr_resource_entry *res_entries; | |
1467 | struct list_head free_res_q; | |
1468 | struct list_head used_res_q; | |
1469 | ||
1470 | char ipr_hcam_label[8]; | |
1471 | #define IPR_HCAM_LABEL "hcams" | |
afc3f83c BK |
1472 | struct ipr_hostrcb *hostrcb[IPR_MAX_HCAMS]; |
1473 | dma_addr_t hostrcb_dma[IPR_MAX_HCAMS]; | |
1da177e4 LT |
1474 | struct list_head hostrcb_free_q; |
1475 | struct list_head hostrcb_pending_q; | |
afc3f83c | 1476 | struct list_head hostrcb_report_q; |
1da177e4 | 1477 | |
05a6538a | 1478 | struct ipr_hrr_queue hrrq[IPR_MAX_HRRQ_NUM]; |
1479 | u32 hrrq_num; | |
56d6aa33 | 1480 | atomic_t hrrq_index; |
1481 | u16 identify_hrrq_index; | |
1da177e4 LT |
1482 | |
1483 | struct ipr_bus_attributes bus_attr[IPR_MAX_NUM_BUSES]; | |
1484 | ||
5469cb5b | 1485 | unsigned int transop_timeout; |
1da177e4 | 1486 | const struct ipr_chip_cfg_t *chip_cfg; |
1be7bd82 | 1487 | const struct ipr_chip_t *ipr_chip; |
1da177e4 LT |
1488 | |
1489 | void __iomem *hdw_dma_regs; /* iomapped PCI memory space */ | |
1490 | unsigned long hdw_dma_regs_pci; /* raw PCI memory space */ | |
1491 | void __iomem *ioa_mailbox; | |
1492 | struct ipr_interrupts regs; | |
1493 | ||
1494 | u16 saved_pcix_cmd_reg; | |
1495 | u16 reset_retries; | |
1496 | ||
1497 | u32 errors_logged; | |
3d1d0da6 | 1498 | u32 doorbell; |
1da177e4 LT |
1499 | |
1500 | struct Scsi_Host *host; | |
1501 | struct pci_dev *pdev; | |
1502 | struct ipr_sglist *ucode_sglist; | |
1da177e4 LT |
1503 | u8 saved_mode_page_len; |
1504 | ||
1505 | struct work_struct work_q; | |
318ddb34 | 1506 | struct work_struct scsi_add_work_q; |
2796ca5e | 1507 | struct workqueue_struct *reset_work_q; |
1da177e4 LT |
1508 | |
1509 | wait_queue_head_t reset_wait_q; | |
95fecd90 | 1510 | wait_queue_head_t msi_wait_q; |
6270e593 | 1511 | wait_queue_head_t eeh_wait_q; |
1da177e4 LT |
1512 | |
1513 | struct ipr_dump *dump; | |
1514 | enum ipr_sdt_state sdt_state; | |
1515 | ||
1516 | struct ipr_misc_cbs *vpd_cbs; | |
1517 | dma_addr_t vpd_cbs_dma; | |
1518 | ||
d73341bf | 1519 | struct dma_pool *ipr_cmd_pool; |
1da177e4 LT |
1520 | |
1521 | struct ipr_cmnd *reset_cmd; | |
463fc696 | 1522 | int (*reset) (struct ipr_cmnd *); |
1da177e4 LT |
1523 | |
1524 | char ipr_cmd_label[8]; | |
0124ca9d | 1525 | #define IPR_CMD_LABEL "ipr_cmd" |
89aad428 BK |
1526 | u32 max_cmds; |
1527 | struct ipr_cmnd **ipr_cmnd_list; | |
1528 | dma_addr_t *ipr_cmnd_list_dma; | |
05a6538a | 1529 | |
05a6538a | 1530 | unsigned int nvectors; |
1531 | ||
1532 | struct { | |
05a6538a | 1533 | char desc[22]; |
1534 | } vectors_info[IPR_MAX_MSIX_VECTORS]; | |
1535 | ||
b53d124a | 1536 | u32 iopoll_weight; |
1537 | ||
3e7ebdfa | 1538 | }; /* struct ipr_ioa_cfg */ |
1da177e4 LT |
1539 | |
1540 | struct ipr_cmnd { | |
1541 | struct ipr_ioarcb ioarcb; | |
a32c055f WB |
1542 | union { |
1543 | struct ipr_ioadl_desc ioadl[IPR_NUM_IOADL_ENTRIES]; | |
1544 | struct ipr_ioadl64_desc ioadl64[IPR_NUM_IOADL_ENTRIES]; | |
a32c055f | 1545 | } i; |
96d21f00 WB |
1546 | union { |
1547 | struct ipr_ioasa ioasa; | |
1548 | struct ipr_ioasa64 ioasa64; | |
1549 | } s; | |
1da177e4 LT |
1550 | struct list_head queue; |
1551 | struct scsi_cmnd *scsi_cmd; | |
1552 | struct completion completion; | |
1553 | struct timer_list timer; | |
2796ca5e | 1554 | struct work_struct work; |
172cd6e1 | 1555 | void (*fast_done) (struct ipr_cmnd *); |
1da177e4 LT |
1556 | void (*done) (struct ipr_cmnd *); |
1557 | int (*job_step) (struct ipr_cmnd *); | |
dfed823e | 1558 | int (*job_step_failed) (struct ipr_cmnd *); |
1da177e4 LT |
1559 | u16 cmd_index; |
1560 | u8 sense_buffer[SCSI_SENSE_BUFFERSIZE]; | |
1561 | dma_addr_t sense_buffer_dma; | |
1562 | unsigned short dma_use_sg; | |
a32c055f | 1563 | dma_addr_t dma_addr; |
1da177e4 LT |
1564 | struct ipr_cmnd *sibling; |
1565 | union { | |
1566 | enum ipr_shutdown_type shutdown_type; | |
1567 | struct ipr_hostrcb *hostrcb; | |
1568 | unsigned long time_left; | |
1569 | unsigned long scratch; | |
1570 | struct ipr_resource_entry *res; | |
1571 | struct scsi_device *sdev; | |
1572 | } u; | |
1573 | ||
6cdb0817 | 1574 | struct completion *eh_comp; |
05a6538a | 1575 | struct ipr_hrr_queue *hrrq; |
1da177e4 LT |
1576 | struct ipr_ioa_cfg *ioa_cfg; |
1577 | }; | |
1578 | ||
1579 | struct ipr_ses_table_entry { | |
1580 | char product_id[17]; | |
1581 | char compare_product_id_byte[17]; | |
1582 | u32 max_bus_speed_limit; /* MB/sec limit for this backplane */ | |
1583 | }; | |
1584 | ||
1585 | struct ipr_dump_header { | |
1586 | u32 eye_catcher; | |
1587 | #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 | |
1588 | u32 len; | |
1589 | u32 num_entries; | |
1590 | u32 first_entry_offset; | |
1591 | u32 status; | |
1592 | #define IPR_DUMP_STATUS_SUCCESS 0 | |
1593 | #define IPR_DUMP_STATUS_QUAL_SUCCESS 2 | |
1594 | #define IPR_DUMP_STATUS_FAILED 0xffffffff | |
1595 | u32 os; | |
1596 | #define IPR_DUMP_OS_LINUX 0x4C4E5558 | |
1597 | u32 driver_name; | |
1598 | #define IPR_DUMP_DRIVER_NAME 0x49505232 | |
1599 | }__attribute__((packed, aligned (4))); | |
1600 | ||
1601 | struct ipr_dump_entry_header { | |
1602 | u32 eye_catcher; | |
1603 | #define IPR_DUMP_EYE_CATCHER 0xC5D4E3F2 | |
1604 | u32 len; | |
1605 | u32 num_elems; | |
1606 | u32 offset; | |
1607 | u32 data_type; | |
1608 | #define IPR_DUMP_DATA_TYPE_ASCII 0x41534349 | |
1609 | #define IPR_DUMP_DATA_TYPE_BINARY 0x42494E41 | |
1610 | u32 id; | |
1611 | #define IPR_DUMP_IOA_DUMP_ID 0x494F4131 | |
1612 | #define IPR_DUMP_LOCATION_ID 0x4C4F4341 | |
1613 | #define IPR_DUMP_TRACE_ID 0x54524143 | |
1614 | #define IPR_DUMP_DRIVER_VERSION_ID 0x44525652 | |
1615 | #define IPR_DUMP_DRIVER_TYPE_ID 0x54595045 | |
1616 | #define IPR_DUMP_IOA_CTRL_BLK 0x494F4342 | |
1617 | #define IPR_DUMP_PEND_OPS 0x414F5053 | |
1618 | u32 status; | |
1619 | }__attribute__((packed, aligned (4))); | |
1620 | ||
1621 | struct ipr_dump_location_entry { | |
1622 | struct ipr_dump_entry_header hdr; | |
71610f55 | 1623 | u8 location[20]; |
f3bdc59f | 1624 | }__attribute__((packed, aligned (4))); |
1da177e4 LT |
1625 | |
1626 | struct ipr_dump_trace_entry { | |
1627 | struct ipr_dump_entry_header hdr; | |
1628 | u32 trace[IPR_TRACE_SIZE / sizeof(u32)]; | |
1629 | }__attribute__((packed, aligned (4))); | |
1630 | ||
1631 | struct ipr_dump_version_entry { | |
1632 | struct ipr_dump_entry_header hdr; | |
1633 | u8 version[sizeof(IPR_DRIVER_VERSION)]; | |
1634 | }; | |
1635 | ||
1636 | struct ipr_dump_ioa_type_entry { | |
1637 | struct ipr_dump_entry_header hdr; | |
1638 | u32 type; | |
1639 | u32 fw_version; | |
1640 | }; | |
1641 | ||
1642 | struct ipr_driver_dump { | |
1643 | struct ipr_dump_header hdr; | |
1644 | struct ipr_dump_version_entry version_entry; | |
1645 | struct ipr_dump_location_entry location_entry; | |
1646 | struct ipr_dump_ioa_type_entry ioa_type_entry; | |
1647 | struct ipr_dump_trace_entry trace_entry; | |
f3bdc59f | 1648 | }__attribute__((packed, aligned (4))); |
1da177e4 LT |
1649 | |
1650 | struct ipr_ioa_dump { | |
1651 | struct ipr_dump_entry_header hdr; | |
1652 | struct ipr_sdt sdt; | |
4d4dd706 | 1653 | __be32 **ioa_data; |
1da177e4 LT |
1654 | u32 reserved; |
1655 | u32 next_page_index; | |
1656 | u32 page_offset; | |
1657 | u32 format; | |
1da177e4 LT |
1658 | }__attribute__((packed, aligned (4))); |
1659 | ||
1660 | struct ipr_dump { | |
1661 | struct kref kref; | |
1662 | struct ipr_ioa_cfg *ioa_cfg; | |
1663 | struct ipr_driver_dump driver_dump; | |
1664 | struct ipr_ioa_dump ioa_dump; | |
1665 | }; | |
1666 | ||
1667 | struct ipr_error_table_t { | |
1668 | u32 ioasc; | |
1669 | int log_ioasa; | |
1670 | int log_hcam; | |
1671 | char *error; | |
1672 | }; | |
1673 | ||
1674 | struct ipr_software_inq_lid_info { | |
1675 | __be32 load_id; | |
1676 | __be32 timestamp[3]; | |
1677 | }__attribute__((packed, aligned (4))); | |
1678 | ||
1679 | struct ipr_ucode_image_header { | |
1680 | __be32 header_length; | |
1681 | __be32 lid_table_offset; | |
1682 | u8 major_release; | |
1683 | u8 card_type; | |
1684 | u8 minor_release[2]; | |
1685 | u8 reserved[20]; | |
1686 | char eyecatcher[16]; | |
1687 | __be32 num_lids; | |
1688 | struct ipr_software_inq_lid_info lid[1]; | |
1689 | }__attribute__((packed, aligned (4))); | |
1690 | ||
1691 | /* | |
1692 | * Macros | |
1693 | */ | |
d3c74871 | 1694 | #define IPR_DBG_CMD(CMD) if (ipr_debug) { CMD; } |
1da177e4 LT |
1695 | |
1696 | #ifdef CONFIG_SCSI_IPR_TRACE | |
1697 | #define ipr_create_trace_file(kobj, attr) sysfs_create_bin_file(kobj, attr) | |
1698 | #define ipr_remove_trace_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) | |
1699 | #else | |
1700 | #define ipr_create_trace_file(kobj, attr) 0 | |
1701 | #define ipr_remove_trace_file(kobj, attr) do { } while(0) | |
1702 | #endif | |
1703 | ||
1704 | #ifdef CONFIG_SCSI_IPR_DUMP | |
1705 | #define ipr_create_dump_file(kobj, attr) sysfs_create_bin_file(kobj, attr) | |
1706 | #define ipr_remove_dump_file(kobj, attr) sysfs_remove_bin_file(kobj, attr) | |
1707 | #else | |
1708 | #define ipr_create_dump_file(kobj, attr) 0 | |
1709 | #define ipr_remove_dump_file(kobj, attr) do { } while(0) | |
1710 | #endif | |
1711 | ||
1712 | /* | |
1713 | * Error logging macros | |
1714 | */ | |
1715 | #define ipr_err(...) printk(KERN_ERR IPR_NAME ": "__VA_ARGS__) | |
1716 | #define ipr_info(...) printk(KERN_INFO IPR_NAME ": "__VA_ARGS__) | |
1da177e4 LT |
1717 | #define ipr_dbg(...) IPR_DBG_CMD(printk(KERN_INFO IPR_NAME ": "__VA_ARGS__)) |
1718 | ||
3e7ebdfa WB |
1719 | #define ipr_res_printk(level, ioa_cfg, bus, target, lun, fmt, ...) \ |
1720 | printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ | |
1721 | bus, target, lun, ##__VA_ARGS__) | |
1722 | ||
1723 | #define ipr_res_err(ioa_cfg, res, fmt, ...) \ | |
1724 | ipr_res_printk(KERN_ERR, ioa_cfg, (res)->bus, (res)->target, (res)->lun, fmt, ##__VA_ARGS__) | |
1725 | ||
fb3ed3cb BK |
1726 | #define ipr_ra_printk(level, ioa_cfg, ra, fmt, ...) \ |
1727 | printk(level IPR_NAME ": %d:%d:%d:%d: " fmt, (ioa_cfg)->host->host_no, \ | |
1728 | (ra).bus, (ra).target, (ra).lun, ##__VA_ARGS__) | |
1da177e4 | 1729 | |
fb3ed3cb BK |
1730 | #define ipr_ra_err(ioa_cfg, ra, fmt, ...) \ |
1731 | ipr_ra_printk(KERN_ERR, ioa_cfg, ra, fmt, ##__VA_ARGS__) | |
1da177e4 | 1732 | |
fa15b1f6 | 1733 | #define ipr_phys_res_err(ioa_cfg, res, fmt, ...) \ |
1734 | { \ | |
1735 | if ((res).bus >= IPR_MAX_NUM_BUSES) { \ | |
1736 | ipr_err(fmt": unknown\n", ##__VA_ARGS__); \ | |
1737 | } else { \ | |
1738 | ipr_err(fmt": %d:%d:%d:%d\n", \ | |
1739 | ##__VA_ARGS__, (ioa_cfg)->host->host_no, \ | |
1740 | (res).bus, (res).target, (res).lun); \ | |
1741 | } \ | |
1742 | } | |
1743 | ||
49dc6a18 | 1744 | #define ipr_hcam_err(hostrcb, fmt, ...) \ |
4565e370 WB |
1745 | { \ |
1746 | if (ipr_is_device(hostrcb)) { \ | |
1747 | if ((hostrcb)->ioa_cfg->sis64) { \ | |
1748 | printk(KERN_ERR IPR_NAME ": %s: " fmt, \ | |
b3b3b407 BK |
1749 | ipr_format_res_path(hostrcb->ioa_cfg, \ |
1750 | hostrcb->hcam.u.error64.fd_res_path, \ | |
5adcbeb3 WB |
1751 | hostrcb->rp_buffer, \ |
1752 | sizeof(hostrcb->rp_buffer)), \ | |
4565e370 WB |
1753 | __VA_ARGS__); \ |
1754 | } else { \ | |
1755 | ipr_ra_err((hostrcb)->ioa_cfg, \ | |
1756 | (hostrcb)->hcam.u.error.fd_res_addr, \ | |
1757 | fmt, __VA_ARGS__); \ | |
1758 | } \ | |
1759 | } else { \ | |
1760 | dev_err(&(hostrcb)->ioa_cfg->pdev->dev, fmt, __VA_ARGS__); \ | |
1761 | } \ | |
49dc6a18 BK |
1762 | } |
1763 | ||
1da177e4 | 1764 | #define ipr_trace ipr_dbg("%s: %s: Line: %d\n",\ |
cadbd4a5 | 1765 | __FILE__, __func__, __LINE__) |
1da177e4 | 1766 | |
cadbd4a5 HH |
1767 | #define ENTER IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Entering %s\n", __func__)) |
1768 | #define LEAVE IPR_DBG_CMD(printk(KERN_INFO IPR_NAME": Leaving %s\n", __func__)) | |
1da177e4 LT |
1769 | |
1770 | #define ipr_err_separator \ | |
1771 | ipr_err("----------------------------------------------------------\n") | |
1772 | ||
1773 | ||
1774 | /* | |
1775 | * Inlines | |
1776 | */ | |
1777 | ||
1778 | /** | |
1779 | * ipr_is_ioa_resource - Determine if a resource is the IOA | |
1780 | * @res: resource entry struct | |
1781 | * | |
1782 | * Return value: | |
1783 | * 1 if IOA / 0 if not IOA | |
1784 | **/ | |
1785 | static inline int ipr_is_ioa_resource(struct ipr_resource_entry *res) | |
1786 | { | |
3e7ebdfa | 1787 | return res->type == IPR_RES_TYPE_IOAFP; |
1da177e4 LT |
1788 | } |
1789 | ||
1790 | /** | |
1791 | * ipr_is_af_dasd_device - Determine if a resource is an AF DASD | |
1792 | * @res: resource entry struct | |
1793 | * | |
1794 | * Return value: | |
1795 | * 1 if AF DASD / 0 if not AF DASD | |
1796 | **/ | |
1797 | static inline int ipr_is_af_dasd_device(struct ipr_resource_entry *res) | |
1798 | { | |
3e7ebdfa WB |
1799 | return res->type == IPR_RES_TYPE_AF_DASD || |
1800 | res->type == IPR_RES_TYPE_REMOTE_AF_DASD; | |
1da177e4 LT |
1801 | } |
1802 | ||
1803 | /** | |
1804 | * ipr_is_vset_device - Determine if a resource is a VSET | |
1805 | * @res: resource entry struct | |
1806 | * | |
1807 | * Return value: | |
1808 | * 1 if VSET / 0 if not VSET | |
1809 | **/ | |
1810 | static inline int ipr_is_vset_device(struct ipr_resource_entry *res) | |
1811 | { | |
3e7ebdfa | 1812 | return res->type == IPR_RES_TYPE_VOLUME_SET; |
1da177e4 LT |
1813 | } |
1814 | ||
1815 | /** | |
1816 | * ipr_is_gscsi - Determine if a resource is a generic scsi resource | |
1817 | * @res: resource entry struct | |
1818 | * | |
1819 | * Return value: | |
1820 | * 1 if GSCSI / 0 if not GSCSI | |
1821 | **/ | |
1822 | static inline int ipr_is_gscsi(struct ipr_resource_entry *res) | |
1823 | { | |
3e7ebdfa | 1824 | return res->type == IPR_RES_TYPE_GENERIC_SCSI; |
1da177e4 LT |
1825 | } |
1826 | ||
e4fbf44e BK |
1827 | /** |
1828 | * ipr_is_scsi_disk - Determine if a resource is a SCSI disk | |
1829 | * @res: resource entry struct | |
1830 | * | |
1831 | * Return value: | |
1832 | * 1 if SCSI disk / 0 if not SCSI disk | |
1833 | **/ | |
1834 | static inline int ipr_is_scsi_disk(struct ipr_resource_entry *res) | |
1835 | { | |
1836 | if (ipr_is_af_dasd_device(res) || | |
3e7ebdfa | 1837 | (ipr_is_gscsi(res) && IPR_IS_DASD_DEVICE(res->std_inq_data))) |
e4fbf44e BK |
1838 | return 1; |
1839 | else | |
1840 | return 0; | |
1841 | } | |
1842 | ||
b5145d25 BK |
1843 | /** |
1844 | * ipr_is_gata - Determine if a resource is a generic ATA resource | |
1845 | * @res: resource entry struct | |
1846 | * | |
1847 | * Return value: | |
1848 | * 1 if GATA / 0 if not GATA | |
1849 | **/ | |
1850 | static inline int ipr_is_gata(struct ipr_resource_entry *res) | |
1851 | { | |
3e7ebdfa | 1852 | return res->type == IPR_RES_TYPE_GENERIC_ATA; |
b5145d25 BK |
1853 | } |
1854 | ||
ee0a90fa | 1855 | /** |
1856 | * ipr_is_naca_model - Determine if a resource is using NACA queueing model | |
1857 | * @res: resource entry struct | |
1858 | * | |
1859 | * Return value: | |
1860 | * 1 if NACA queueing model / 0 if not NACA queueing model | |
1861 | **/ | |
1862 | static inline int ipr_is_naca_model(struct ipr_resource_entry *res) | |
1863 | { | |
3e7ebdfa | 1864 | if (ipr_is_gscsi(res) && res->qmodel == IPR_QUEUE_NACA_MODEL) |
ee0a90fa | 1865 | return 1; |
1866 | return 0; | |
1867 | } | |
1868 | ||
1da177e4 | 1869 | /** |
4565e370 WB |
1870 | * ipr_is_device - Determine if the hostrcb structure is related to a device |
1871 | * @hostrcb: host resource control blocks struct | |
1da177e4 LT |
1872 | * |
1873 | * Return value: | |
1874 | * 1 if AF / 0 if not AF | |
1875 | **/ | |
4565e370 | 1876 | static inline int ipr_is_device(struct ipr_hostrcb *hostrcb) |
1da177e4 | 1877 | { |
4565e370 WB |
1878 | struct ipr_res_addr *res_addr; |
1879 | u8 *res_path; | |
1880 | ||
1881 | if (hostrcb->ioa_cfg->sis64) { | |
1882 | res_path = &hostrcb->hcam.u.error64.fd_res_path[0]; | |
1883 | if ((res_path[0] == 0x00 || res_path[0] == 0x80 || | |
1884 | res_path[0] == 0x81) && res_path[2] != 0xFF) | |
1885 | return 1; | |
1886 | } else { | |
1887 | res_addr = &hostrcb->hcam.u.error.fd_res_addr; | |
1888 | ||
1889 | if ((res_addr->bus < IPR_MAX_NUM_BUSES) && | |
1890 | (res_addr->target < (IPR_MAX_NUM_TARGETS_PER_BUS - 1))) | |
1891 | return 1; | |
1892 | } | |
1da177e4 LT |
1893 | return 0; |
1894 | } | |
1895 | ||
1896 | /** | |
1897 | * ipr_sdt_is_fmt2 - Determine if a SDT address is in format 2 | |
1898 | * @sdt_word: SDT address | |
1899 | * | |
1900 | * Return value: | |
1901 | * 1 if format 2 / 0 if not | |
1902 | **/ | |
1903 | static inline int ipr_sdt_is_fmt2(u32 sdt_word) | |
1904 | { | |
1905 | u32 bar_sel = IPR_GET_FMT2_BAR_SEL(sdt_word); | |
1906 | ||
1907 | switch (bar_sel) { | |
1908 | case IPR_SDT_FMT2_BAR0_SEL: | |
1909 | case IPR_SDT_FMT2_BAR1_SEL: | |
1910 | case IPR_SDT_FMT2_BAR2_SEL: | |
1911 | case IPR_SDT_FMT2_BAR3_SEL: | |
1912 | case IPR_SDT_FMT2_BAR4_SEL: | |
1913 | case IPR_SDT_FMT2_BAR5_SEL: | |
1914 | case IPR_SDT_FMT2_EXP_ROM_SEL: | |
1915 | return 1; | |
1916 | }; | |
1917 | ||
1918 | return 0; | |
1919 | } | |
1920 | ||
c5f10187 WB |
1921 | #ifndef writeq |
1922 | static inline void writeq(u64 val, void __iomem *addr) | |
1923 | { | |
1924 | writel(((u32) (val >> 32)), addr); | |
1925 | writel(((u32) (val)), (addr + 4)); | |
1926 | } | |
1da177e4 | 1927 | #endif |
c5f10187 WB |
1928 | |
1929 | #endif /* _IPR_H */ |