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edd16368 SC |
1 | /* |
2 | * Disk Array driver for HP Smart Array SAS controllers | |
51c35139 | 3 | * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P. |
edd16368 SC |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; version 2 of the License. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
12 | * NON INFRINGEMENT. See the GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | * | |
18 | * Questions/Comments/Bugfixes to iss_storagedev@hp.com | |
19 | * | |
20 | */ | |
21 | #ifndef HPSA_H | |
22 | #define HPSA_H | |
23 | ||
24 | #include <scsi/scsicam.h> | |
25 | ||
26 | #define IO_OK 0 | |
27 | #define IO_ERROR 1 | |
28 | ||
29 | struct ctlr_info; | |
30 | ||
31 | struct access_method { | |
32 | void (*submit_command)(struct ctlr_info *h, | |
33 | struct CommandList *c); | |
34 | void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); | |
900c5440 | 35 | bool (*intr_pending)(struct ctlr_info *h); |
254f796b | 36 | unsigned long (*command_completed)(struct ctlr_info *h, u8 q); |
edd16368 SC |
37 | }; |
38 | ||
39 | struct hpsa_scsi_dev_t { | |
40 | int devtype; | |
41 | int bus, target, lun; /* as presented to the OS */ | |
42 | unsigned char scsi3addr[8]; /* as presented to the HW */ | |
43 | #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" | |
44 | unsigned char device_id[16]; /* from inquiry pg. 0x83 */ | |
45 | unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ | |
46 | unsigned char model[16]; /* bytes 16-31 of inquiry data */ | |
edd16368 | 47 | unsigned char raid_level; /* from inquiry page 0xC1 */ |
9846590e | 48 | unsigned char volume_offline; /* discovered via TUR or VPD */ |
03383736 DB |
49 | u16 queue_depth; /* max queue_depth for this device */ |
50 | atomic_t ioaccel_cmds_out; /* Only used for physical devices | |
51 | * counts commands sent to physical | |
52 | * device via "ioaccel" path. | |
53 | */ | |
e1f7de0c | 54 | u32 ioaccel_handle; |
283b4a9b SC |
55 | int offload_config; /* I/O accel RAID offload configured */ |
56 | int offload_enabled; /* I/O accel RAID offload enabled */ | |
41ce4c35 | 57 | int offload_to_be_enabled; |
a3144e0b | 58 | int hba_ioaccel_enabled; |
283b4a9b SC |
59 | int offload_to_mirror; /* Send next I/O accelerator RAID |
60 | * offload request to mirror drive | |
61 | */ | |
62 | struct raid_map_data raid_map; /* I/O accelerator RAID map */ | |
63 | ||
03383736 DB |
64 | /* |
65 | * Pointers from logical drive map indices to the phys drives that | |
66 | * make those logical drives. Note, multiple logical drives may | |
67 | * share physical drives. You can have for instance 5 physical | |
68 | * drives with 3 logical drives each using those same 5 physical | |
69 | * disks. We need these pointers for counting i/o's out to physical | |
70 | * devices in order to honor physical device queue depth limits. | |
71 | */ | |
72 | struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES]; | |
9b5c48c2 | 73 | int supports_aborts; |
41ce4c35 SC |
74 | #define HPSA_DO_NOT_EXPOSE 0x0 |
75 | #define HPSA_SG_ATTACH 0x1 | |
76 | #define HPSA_ULD_ATTACH 0x2 | |
77 | #define HPSA_SCSI_ADD (HPSA_SG_ATTACH | HPSA_ULD_ATTACH) | |
78 | u8 expose_state; | |
edd16368 SC |
79 | }; |
80 | ||
072b0518 | 81 | struct reply_queue_buffer { |
254f796b MG |
82 | u64 *head; |
83 | size_t size; | |
84 | u8 wraparound; | |
85 | u32 current_entry; | |
072b0518 | 86 | dma_addr_t busaddr; |
254f796b MG |
87 | }; |
88 | ||
316b221a SC |
89 | #pragma pack(1) |
90 | struct bmic_controller_parameters { | |
91 | u8 led_flags; | |
92 | u8 enable_command_list_verification; | |
93 | u8 backed_out_write_drives; | |
94 | u16 stripes_for_parity; | |
95 | u8 parity_distribution_mode_flags; | |
96 | u16 max_driver_requests; | |
97 | u16 elevator_trend_count; | |
98 | u8 disable_elevator; | |
99 | u8 force_scan_complete; | |
100 | u8 scsi_transfer_mode; | |
101 | u8 force_narrow; | |
102 | u8 rebuild_priority; | |
103 | u8 expand_priority; | |
104 | u8 host_sdb_asic_fix; | |
105 | u8 pdpi_burst_from_host_disabled; | |
106 | char software_name[64]; | |
107 | char hardware_name[32]; | |
108 | u8 bridge_revision; | |
109 | u8 snapshot_priority; | |
110 | u32 os_specific; | |
111 | u8 post_prompt_timeout; | |
112 | u8 automatic_drive_slamming; | |
113 | u8 reserved1; | |
114 | u8 nvram_flags; | |
6e8e8088 | 115 | #define HBA_MODE_ENABLED_FLAG (1 << 3) |
316b221a SC |
116 | u8 cache_nvram_flags; |
117 | u8 drive_config_flags; | |
118 | u16 reserved2; | |
119 | u8 temp_warning_level; | |
120 | u8 temp_shutdown_level; | |
121 | u8 temp_condition_reset; | |
122 | u8 max_coalesce_commands; | |
123 | u32 max_coalesce_delay; | |
124 | u8 orca_password[4]; | |
125 | u8 access_id[16]; | |
126 | u8 reserved[356]; | |
127 | }; | |
128 | #pragma pack() | |
129 | ||
edd16368 SC |
130 | struct ctlr_info { |
131 | int ctlr; | |
132 | char devname[8]; | |
133 | char *product_name; | |
edd16368 | 134 | struct pci_dev *pdev; |
01a02ffc | 135 | u32 board_id; |
edd16368 SC |
136 | void __iomem *vaddr; |
137 | unsigned long paddr; | |
138 | int nr_cmds; /* Number of commands allowed on this controller */ | |
d54c5c24 SC |
139 | #define HPSA_CMDS_RESERVED_FOR_ABORTS 2 |
140 | #define HPSA_CMDS_RESERVED_FOR_DRIVER 1 | |
edd16368 SC |
141 | struct CfgTable __iomem *cfgtable; |
142 | int interrupts_enabled; | |
edd16368 | 143 | int max_commands; |
33811026 | 144 | int last_allocation; |
0cbf768e | 145 | atomic_t commands_outstanding; |
303932fd DB |
146 | # define PERF_MODE_INT 0 |
147 | # define DOORBELL_INT 1 | |
edd16368 SC |
148 | # define SIMPLE_MODE_INT 2 |
149 | # define MEMQ_MODE_INT 3 | |
254f796b | 150 | unsigned int intr[MAX_REPLY_QUEUES]; |
edd16368 SC |
151 | unsigned int msix_vector; |
152 | unsigned int msi_vector; | |
a9a3a273 | 153 | int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ |
edd16368 | 154 | struct access_method access; |
316b221a | 155 | char hba_mode_enabled; |
edd16368 SC |
156 | |
157 | /* queue and queue Info */ | |
edd16368 | 158 | unsigned int Qdepth; |
edd16368 SC |
159 | unsigned int maxSG; |
160 | spinlock_t lock; | |
33a2ffce SC |
161 | int maxsgentries; |
162 | u8 max_cmd_sg_entries; | |
163 | int chainsize; | |
164 | struct SGDescriptor **cmd_sg_list; | |
d9a729f3 | 165 | struct ioaccel2_sg_element **ioaccel2_cmd_sg_list; |
edd16368 SC |
166 | |
167 | /* pointers to command and error info pool */ | |
168 | struct CommandList *cmd_pool; | |
169 | dma_addr_t cmd_pool_dhandle; | |
e1f7de0c MG |
170 | struct io_accel1_cmd *ioaccel_cmd_pool; |
171 | dma_addr_t ioaccel_cmd_pool_dhandle; | |
aca9012a SC |
172 | struct io_accel2_cmd *ioaccel2_cmd_pool; |
173 | dma_addr_t ioaccel2_cmd_pool_dhandle; | |
edd16368 SC |
174 | struct ErrorInfo *errinfo_pool; |
175 | dma_addr_t errinfo_pool_dhandle; | |
176 | unsigned long *cmd_pool_bits; | |
a08a8471 SC |
177 | int scan_finished; |
178 | spinlock_t scan_lock; | |
179 | wait_queue_head_t scan_wait_queue; | |
edd16368 SC |
180 | |
181 | struct Scsi_Host *scsi_host; | |
182 | spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ | |
183 | int ndevices; /* number of used elements in .dev[] array. */ | |
cfe5badc | 184 | struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; |
303932fd DB |
185 | /* |
186 | * Performant mode tables. | |
187 | */ | |
188 | u32 trans_support; | |
189 | u32 trans_offset; | |
42a91641 | 190 | struct TransTable_struct __iomem *transtable; |
303932fd DB |
191 | unsigned long transMethod; |
192 | ||
0390f0c0 | 193 | /* cap concurrent passthrus at some reasonable maximum */ |
45fcb86e | 194 | #define HPSA_MAX_CONCURRENT_PASSTHRUS (10) |
34f0c627 | 195 | atomic_t passthru_cmds_avail; |
0390f0c0 | 196 | |
303932fd | 197 | /* |
254f796b | 198 | * Performant mode completion buffers |
303932fd | 199 | */ |
072b0518 SC |
200 | size_t reply_queue_size; |
201 | struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES]; | |
254f796b | 202 | u8 nreply_queues; |
303932fd | 203 | u32 *blockFetchTable; |
e1f7de0c | 204 | u32 *ioaccel1_blockFetchTable; |
aca9012a | 205 | u32 *ioaccel2_blockFetchTable; |
42a91641 | 206 | u32 __iomem *ioaccel2_bft2_regs; |
339b2b14 | 207 | unsigned char *hba_inquiry_data; |
283b4a9b SC |
208 | u32 driver_support; |
209 | u32 fw_support; | |
210 | int ioaccel_support; | |
211 | int ioaccel_maxsg; | |
a0c12413 SC |
212 | u64 last_intr_timestamp; |
213 | u32 last_heartbeat; | |
214 | u64 last_heartbeat_timestamp; | |
e85c5974 SC |
215 | u32 heartbeat_sample_interval; |
216 | atomic_t firmware_flash_in_progress; | |
42a91641 | 217 | u32 __percpu *lockup_detected; |
8a98db73 | 218 | struct delayed_work monitor_ctlr_work; |
6636e7f4 | 219 | struct delayed_work rescan_ctlr_work; |
8a98db73 | 220 | int remove_in_progress; |
254f796b MG |
221 | /* Address of h->q[x] is passed to intr handler to know which queue */ |
222 | u8 q[MAX_REPLY_QUEUES]; | |
75167d2c SC |
223 | u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ |
224 | #define HPSATMF_BITS_SUPPORTED (1 << 0) | |
225 | #define HPSATMF_PHYS_LUN_RESET (1 << 1) | |
226 | #define HPSATMF_PHYS_NEX_RESET (1 << 2) | |
227 | #define HPSATMF_PHYS_TASK_ABORT (1 << 3) | |
228 | #define HPSATMF_PHYS_TSET_ABORT (1 << 4) | |
229 | #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) | |
230 | #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) | |
231 | #define HPSATMF_PHYS_QRY_TASK (1 << 7) | |
232 | #define HPSATMF_PHYS_QRY_TSET (1 << 8) | |
233 | #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) | |
234 | #define HPSATMF_MASK_SUPPORTED (1 << 16) | |
235 | #define HPSATMF_LOG_LUN_RESET (1 << 17) | |
236 | #define HPSATMF_LOG_NEX_RESET (1 << 18) | |
237 | #define HPSATMF_LOG_TASK_ABORT (1 << 19) | |
238 | #define HPSATMF_LOG_TSET_ABORT (1 << 20) | |
239 | #define HPSATMF_LOG_CLEAR_ACA (1 << 21) | |
240 | #define HPSATMF_LOG_CLEAR_TSET (1 << 22) | |
241 | #define HPSATMF_LOG_QRY_TASK (1 << 23) | |
242 | #define HPSATMF_LOG_QRY_TSET (1 << 24) | |
243 | #define HPSATMF_LOG_QRY_ASYNC (1 << 25) | |
76438d08 | 244 | u32 events; |
faff6ee0 SC |
245 | #define CTLR_STATE_CHANGE_EVENT (1 << 0) |
246 | #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) | |
247 | #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) | |
248 | #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) | |
249 | #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) | |
250 | #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) | |
251 | #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) | |
252 | ||
253 | #define RESCAN_REQUIRED_EVENT_BITS \ | |
7b2c46ee | 254 | (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ |
faff6ee0 SC |
255 | CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ |
256 | CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ | |
faff6ee0 SC |
257 | CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ |
258 | CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) | |
9846590e SC |
259 | spinlock_t offline_device_lock; |
260 | struct list_head offline_device_list; | |
da0697bd | 261 | int acciopath_status; |
2ba8bfc8 | 262 | int raid_offload_debug; |
9b5c48c2 | 263 | int needs_abort_tags_swizzled; |
080ef1cc | 264 | struct workqueue_struct *resubmit_wq; |
6636e7f4 | 265 | struct workqueue_struct *rescan_ctlr_wq; |
9b5c48c2 SC |
266 | atomic_t abort_cmds_available; |
267 | wait_queue_head_t abort_cmd_wait_queue; | |
edd16368 | 268 | }; |
9846590e SC |
269 | |
270 | struct offline_device_entry { | |
271 | unsigned char scsi3addr[8]; | |
272 | struct list_head offline_list; | |
273 | }; | |
274 | ||
edd16368 SC |
275 | #define HPSA_ABORT_MSG 0 |
276 | #define HPSA_DEVICE_RESET_MSG 1 | |
64670ac8 SC |
277 | #define HPSA_RESET_TYPE_CONTROLLER 0x00 |
278 | #define HPSA_RESET_TYPE_BUS 0x01 | |
279 | #define HPSA_RESET_TYPE_TARGET 0x03 | |
280 | #define HPSA_RESET_TYPE_LUN 0x04 | |
edd16368 | 281 | #define HPSA_MSG_SEND_RETRY_LIMIT 10 |
516fda49 | 282 | #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) |
edd16368 SC |
283 | |
284 | /* Maximum time in seconds driver will wait for command completions | |
285 | * when polling before giving up. | |
286 | */ | |
287 | #define HPSA_MAX_POLL_TIME_SECS (20) | |
288 | ||
289 | /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines | |
290 | * how many times to retry TEST UNIT READY on a device | |
291 | * while waiting for it to become ready before giving up. | |
292 | * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval | |
293 | * between sending TURs while waiting for a device | |
294 | * to become ready. | |
295 | */ | |
296 | #define HPSA_TUR_RETRY_LIMIT (20) | |
297 | #define HPSA_MAX_WAIT_INTERVAL_SECS (30) | |
298 | ||
299 | /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board | |
300 | * to become ready, in seconds, before giving up on it. | |
301 | * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait | |
302 | * between polling the board to see if it is ready, in | |
303 | * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and | |
304 | * HPSA_BOARD_READY_ITERATIONS are derived from those. | |
305 | */ | |
306 | #define HPSA_BOARD_READY_WAIT_SECS (120) | |
2ed7127b | 307 | #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) |
edd16368 SC |
308 | #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) |
309 | #define HPSA_BOARD_READY_POLL_INTERVAL \ | |
310 | ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) | |
311 | #define HPSA_BOARD_READY_ITERATIONS \ | |
312 | ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ | |
313 | HPSA_BOARD_READY_POLL_INTERVAL_MSECS) | |
fe5389c8 SC |
314 | #define HPSA_BOARD_NOT_READY_ITERATIONS \ |
315 | ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ | |
316 | HPSA_BOARD_READY_POLL_INTERVAL_MSECS) | |
edd16368 SC |
317 | #define HPSA_POST_RESET_PAUSE_MSECS (3000) |
318 | #define HPSA_POST_RESET_NOOP_RETRIES (12) | |
319 | ||
320 | /* Defining the diffent access_menthods */ | |
321 | /* | |
322 | * Memory mapped FIFO interface (SMART 53xx cards) | |
323 | */ | |
324 | #define SA5_DOORBELL 0x20 | |
325 | #define SA5_REQUEST_PORT_OFFSET 0x40 | |
281a7fd0 WS |
326 | #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0 |
327 | #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4 | |
edd16368 SC |
328 | #define SA5_REPLY_INTR_MASK_OFFSET 0x34 |
329 | #define SA5_REPLY_PORT_OFFSET 0x44 | |
330 | #define SA5_INTR_STATUS 0x30 | |
331 | #define SA5_SCRATCHPAD_OFFSET 0xB0 | |
332 | ||
333 | #define SA5_CTCFG_OFFSET 0xB4 | |
334 | #define SA5_CTMEM_OFFSET 0xB8 | |
335 | ||
336 | #define SA5_INTR_OFF 0x08 | |
337 | #define SA5B_INTR_OFF 0x04 | |
338 | #define SA5_INTR_PENDING 0x08 | |
339 | #define SA5B_INTR_PENDING 0x04 | |
340 | #define FIFO_EMPTY 0xffffffff | |
341 | #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ | |
342 | ||
343 | #define HPSA_ERROR_BIT 0x02 | |
edd16368 | 344 | |
303932fd DB |
345 | /* Performant mode flags */ |
346 | #define SA5_PERF_INTR_PENDING 0x04 | |
347 | #define SA5_PERF_INTR_OFF 0x05 | |
348 | #define SA5_OUTDB_STATUS_PERF_BIT 0x01 | |
349 | #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 | |
350 | #define SA5_OUTDB_CLEAR 0xA0 | |
351 | #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 | |
352 | #define SA5_OUTDB_STATUS 0x9C | |
353 | ||
354 | ||
edd16368 SC |
355 | #define HPSA_INTR_ON 1 |
356 | #define HPSA_INTR_OFF 0 | |
b66cc250 MM |
357 | |
358 | /* | |
359 | * Inbound Post Queue offsets for IO Accelerator Mode 2 | |
360 | */ | |
361 | #define IOACCEL2_INBOUND_POSTQ_32 0x48 | |
362 | #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 | |
363 | #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 | |
364 | ||
edd16368 SC |
365 | /* |
366 | Send the command to the hardware | |
367 | */ | |
368 | static void SA5_submit_command(struct ctlr_info *h, | |
369 | struct CommandList *c) | |
370 | { | |
edd16368 | 371 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
fec62c36 | 372 | (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); |
edd16368 SC |
373 | } |
374 | ||
b3a52e79 SC |
375 | static void SA5_submit_command_no_read(struct ctlr_info *h, |
376 | struct CommandList *c) | |
377 | { | |
378 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); | |
379 | } | |
380 | ||
c349775e ST |
381 | static void SA5_submit_command_ioaccel2(struct ctlr_info *h, |
382 | struct CommandList *c) | |
383 | { | |
c05e8866 | 384 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
c349775e ST |
385 | } |
386 | ||
edd16368 SC |
387 | /* |
388 | * This card is the opposite of the other cards. | |
389 | * 0 turns interrupts on... | |
390 | * 0x08 turns them off... | |
391 | */ | |
392 | static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) | |
393 | { | |
394 | if (val) { /* Turn interrupts on */ | |
395 | h->interrupts_enabled = 1; | |
396 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
8cd21da7 | 397 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
edd16368 SC |
398 | } else { /* Turn them off */ |
399 | h->interrupts_enabled = 0; | |
400 | writel(SA5_INTR_OFF, | |
401 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
8cd21da7 | 402 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
edd16368 SC |
403 | } |
404 | } | |
303932fd DB |
405 | |
406 | static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) | |
407 | { | |
408 | if (val) { /* turn on interrupts */ | |
409 | h->interrupts_enabled = 1; | |
410 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
8cd21da7 | 411 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
303932fd DB |
412 | } else { |
413 | h->interrupts_enabled = 0; | |
414 | writel(SA5_PERF_INTR_OFF, | |
415 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
8cd21da7 | 416 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
303932fd DB |
417 | } |
418 | } | |
419 | ||
254f796b | 420 | static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) |
303932fd | 421 | { |
072b0518 | 422 | struct reply_queue_buffer *rq = &h->reply_queue[q]; |
0cbf768e | 423 | unsigned long register_value = FIFO_EMPTY; |
303932fd | 424 | |
303932fd | 425 | /* msi auto clears the interrupt pending bit. */ |
bee266a6 | 426 | if (unlikely(!(h->msi_vector || h->msix_vector))) { |
2c17d2da SC |
427 | /* flush the controller write of the reply queue by reading |
428 | * outbound doorbell status register. | |
429 | */ | |
bee266a6 | 430 | (void) readl(h->vaddr + SA5_OUTDB_STATUS); |
303932fd DB |
431 | writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); |
432 | /* Do a read in order to flush the write to the controller | |
433 | * (as per spec.) | |
434 | */ | |
bee266a6 | 435 | (void) readl(h->vaddr + SA5_OUTDB_STATUS); |
303932fd DB |
436 | } |
437 | ||
bee266a6 | 438 | if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) { |
254f796b MG |
439 | register_value = rq->head[rq->current_entry]; |
440 | rq->current_entry++; | |
0cbf768e | 441 | atomic_dec(&h->commands_outstanding); |
303932fd DB |
442 | } else { |
443 | register_value = FIFO_EMPTY; | |
444 | } | |
445 | /* Check for wraparound */ | |
254f796b MG |
446 | if (rq->current_entry == h->max_commands) { |
447 | rq->current_entry = 0; | |
448 | rq->wraparound ^= 1; | |
303932fd | 449 | } |
303932fd DB |
450 | return register_value; |
451 | } | |
452 | ||
edd16368 SC |
453 | /* |
454 | * returns value read from hardware. | |
455 | * returns FIFO_EMPTY if there is nothing to read | |
456 | */ | |
254f796b MG |
457 | static unsigned long SA5_completed(struct ctlr_info *h, |
458 | __attribute__((unused)) u8 q) | |
edd16368 SC |
459 | { |
460 | unsigned long register_value | |
461 | = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); | |
462 | ||
0cbf768e SC |
463 | if (register_value != FIFO_EMPTY) |
464 | atomic_dec(&h->commands_outstanding); | |
edd16368 SC |
465 | |
466 | #ifdef HPSA_DEBUG | |
467 | if (register_value != FIFO_EMPTY) | |
84ca0be2 | 468 | dev_dbg(&h->pdev->dev, "Read %lx back from board\n", |
edd16368 SC |
469 | register_value); |
470 | else | |
f79cfec6 | 471 | dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); |
edd16368 SC |
472 | #endif |
473 | ||
474 | return register_value; | |
475 | } | |
476 | /* | |
477 | * Returns true if an interrupt is pending.. | |
478 | */ | |
900c5440 | 479 | static bool SA5_intr_pending(struct ctlr_info *h) |
edd16368 SC |
480 | { |
481 | unsigned long register_value = | |
482 | readl(h->vaddr + SA5_INTR_STATUS); | |
900c5440 | 483 | return register_value & SA5_INTR_PENDING; |
edd16368 SC |
484 | } |
485 | ||
303932fd DB |
486 | static bool SA5_performant_intr_pending(struct ctlr_info *h) |
487 | { | |
488 | unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); | |
489 | ||
490 | if (!register_value) | |
491 | return false; | |
492 | ||
303932fd DB |
493 | /* Read outbound doorbell to flush */ |
494 | register_value = readl(h->vaddr + SA5_OUTDB_STATUS); | |
495 | return register_value & SA5_OUTDB_STATUS_PERF_BIT; | |
496 | } | |
edd16368 | 497 | |
e1f7de0c MG |
498 | #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 |
499 | ||
500 | static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) | |
501 | { | |
502 | unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); | |
503 | ||
504 | return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? | |
505 | true : false; | |
506 | } | |
507 | ||
508 | #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 | |
509 | #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 | |
510 | #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC | |
511 | #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL | |
512 | ||
283b4a9b | 513 | static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) |
e1f7de0c MG |
514 | { |
515 | u64 register_value; | |
072b0518 | 516 | struct reply_queue_buffer *rq = &h->reply_queue[q]; |
e1f7de0c MG |
517 | |
518 | BUG_ON(q >= h->nreply_queues); | |
519 | ||
520 | register_value = rq->head[rq->current_entry]; | |
521 | if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { | |
522 | rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; | |
523 | if (++rq->current_entry == rq->size) | |
524 | rq->current_entry = 0; | |
283b4a9b SC |
525 | /* |
526 | * @todo | |
527 | * | |
528 | * Don't really need to write the new index after each command, | |
529 | * but with current driver design this is easiest. | |
530 | */ | |
531 | wmb(); | |
532 | writel((q << 24) | rq->current_entry, h->vaddr + | |
533 | IOACCEL_MODE1_CONSUMER_INDEX); | |
0cbf768e | 534 | atomic_dec(&h->commands_outstanding); |
e1f7de0c MG |
535 | } |
536 | return (unsigned long) register_value; | |
537 | } | |
538 | ||
edd16368 SC |
539 | static struct access_method SA5_access = { |
540 | SA5_submit_command, | |
541 | SA5_intr_mask, | |
edd16368 SC |
542 | SA5_intr_pending, |
543 | SA5_completed, | |
544 | }; | |
545 | ||
e1f7de0c MG |
546 | static struct access_method SA5_ioaccel_mode1_access = { |
547 | SA5_submit_command, | |
548 | SA5_performant_intr_mask, | |
e1f7de0c MG |
549 | SA5_ioaccel_mode1_intr_pending, |
550 | SA5_ioaccel_mode1_completed, | |
551 | }; | |
552 | ||
c349775e ST |
553 | static struct access_method SA5_ioaccel_mode2_access = { |
554 | SA5_submit_command_ioaccel2, | |
555 | SA5_performant_intr_mask, | |
c349775e ST |
556 | SA5_performant_intr_pending, |
557 | SA5_performant_completed, | |
558 | }; | |
559 | ||
303932fd DB |
560 | static struct access_method SA5_performant_access = { |
561 | SA5_submit_command, | |
562 | SA5_performant_intr_mask, | |
303932fd DB |
563 | SA5_performant_intr_pending, |
564 | SA5_performant_completed, | |
565 | }; | |
566 | ||
b3a52e79 SC |
567 | static struct access_method SA5_performant_access_no_read = { |
568 | SA5_submit_command_no_read, | |
569 | SA5_performant_intr_mask, | |
b3a52e79 SC |
570 | SA5_performant_intr_pending, |
571 | SA5_performant_completed, | |
572 | }; | |
573 | ||
edd16368 | 574 | struct board_type { |
01a02ffc | 575 | u32 board_id; |
edd16368 SC |
576 | char *product_name; |
577 | struct access_method *access; | |
578 | }; | |
579 | ||
edd16368 SC |
580 | #endif /* HPSA_H */ |
581 |