[linux-block.git] / drivers / scsi / hpsa.h

/*
 *    Disk Array driver for HP Smart Array SAS controllers
 *    Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
 *
 *    This program is free software; you can redistribute it and/or modify
 *    it under the terms of the GNU General Public License as published by
 *    the Free Software Foundation; version 2 of the License.
 *
 *    This program is distributed in the hope that it will be useful,
 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
 *    MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
 *    NON INFRINGEMENT.  See the GNU General Public License for more details.
 *
 *    You should have received a copy of the GNU General Public License
 *    along with this program; if not, write to the Free Software
 *    Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
 *
 *    Questions/Comments/Bugfixes to iss_storagedev@hp.com
 *
 */
#ifndef HPSA_H
#define HPSA_H

#include <scsi/scsicam.h>

#define IO_OK		0
#define IO_ERROR	1

struct ctlr_info;

struct access_method {
	void (*submit_command)(struct ctlr_info *h,
		struct CommandList *c);
	void (*set_intr_mask)(struct ctlr_info *h, unsigned long val);
	unsigned long (*fifo_full)(struct ctlr_info *h);
	bool (*intr_pending)(struct ctlr_info *h);
	unsigned long (*command_completed)(struct ctlr_info *h, u8 q);
};

struct hpsa_scsi_dev_t {
	int devtype;
	int bus, target, lun;		/* as presented to the OS */
	unsigned char scsi3addr[8];	/* as presented to the HW */
#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
	unsigned char device_id[16];    /* from inquiry pg. 0x83 */
	unsigned char vendor[8];        /* bytes 8-15 of inquiry data */
	unsigned char model[16];        /* bytes 16-31 of inquiry data */
	unsigned char raid_level;	/* from inquiry page 0xC1 */
	u32 ioaccel_handle;
	int offload_config;		/* I/O accel RAID offload configured */
	int offload_enabled;		/* I/O accel RAID offload enabled */
	int offload_to_mirror;		/* Send next I/O accelerator RAID
					 * offload request to mirror drive
					 */
	struct raid_map_data raid_map;	/* I/O accelerator RAID map */

};

struct reply_pool {
	u64 *head;
	size_t size;
	u8 wraparound;
	u32 current_entry;
};

struct ctlr_info {
	int	ctlr;
	char	devname[8];
	char    *product_name;
	struct pci_dev *pdev;
	u32	board_id;
	void __iomem *vaddr;
	unsigned long paddr;
	int 	nr_cmds; /* Number of commands allowed on this controller */
	struct CfgTable __iomem *cfgtable;
	int	interrupts_enabled;
	int	major;
	int 	max_commands;
	int	commands_outstanding;
	int 	max_outstanding; /* Debug */
	int	usage_count;  /* number of opens all all minor devices */
#	define PERF_MODE_INT	0
#	define DOORBELL_INT	1
#	define SIMPLE_MODE_INT	2
#	define MEMQ_MODE_INT	3
	unsigned int intr[MAX_REPLY_QUEUES];
	unsigned int msix_vector;
	unsigned int msi_vector;
	int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
	struct access_method access;

	/* queue and queue Info */
	struct list_head reqQ;
	struct list_head cmpQ;
	unsigned int Qdepth;
	unsigned int maxSG;
	spinlock_t lock;
	int maxsgentries;
	u8 max_cmd_sg_entries;
	int chainsize;
	struct SGDescriptor **cmd_sg_list;

	/* pointers to command and error info pool */
	struct CommandList 	*cmd_pool;
	dma_addr_t		cmd_pool_dhandle;
	struct io_accel1_cmd	*ioaccel_cmd_pool;
	dma_addr_t		ioaccel_cmd_pool_dhandle;
	struct io_accel2_cmd	*ioaccel2_cmd_pool;
	dma_addr_t		ioaccel2_cmd_pool_dhandle;
	struct ErrorInfo 	*errinfo_pool;
	dma_addr_t		errinfo_pool_dhandle;
	unsigned long  		*cmd_pool_bits;
	int			scan_finished;
	spinlock_t		scan_lock;
	wait_queue_head_t	scan_wait_queue;

	struct Scsi_Host *scsi_host;
	spinlock_t devlock; /* to protect hba[ctlr]->dev[];  */
	int ndevices; /* number of used elements in .dev[] array. */
	struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
	/*
	 * Performant mode tables.
	 */
	u32 trans_support;
	u32 trans_offset;
	struct TransTable_struct *transtable;
	unsigned long transMethod;

	/* cap concurrent passthrus at some reasonable maximum */
#define HPSA_MAX_CONCURRENT_PASSTHRUS (20)
	spinlock_t passthru_count_lock; /* protects passthru_count */
	int passthru_count;

	/*
	 * Performant mode completion buffers
	 */
	u64 *reply_pool;
	size_t reply_pool_size;
	struct reply_pool reply_queue[MAX_REPLY_QUEUES];
	u8 nreply_queues;
	dma_addr_t reply_pool_dhandle;
	u32 *blockFetchTable;
	u32 *ioaccel1_blockFetchTable;
	u32 *ioaccel2_blockFetchTable;
	u32 *ioaccel2_bft2_regs;
	unsigned char *hba_inquiry_data;
	u32 driver_support;
	u32 fw_support;
	int ioaccel_support;
	int ioaccel_maxsg;
	u64 last_intr_timestamp;
	u32 last_heartbeat;
	u64 last_heartbeat_timestamp;
	u32 heartbeat_sample_interval;
	atomic_t firmware_flash_in_progress;
	u32 lockup_detected;
	struct delayed_work monitor_ctlr_work;
	int remove_in_progress;
	u32 fifo_recently_full;
	/* Address of h->q[x] is passed to intr handler to know which queue */
	u8 q[MAX_REPLY_QUEUES];
	u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
#define HPSATMF_BITS_SUPPORTED  (1 << 0)
#define HPSATMF_PHYS_LUN_RESET  (1 << 1)
#define HPSATMF_PHYS_NEX_RESET  (1 << 2)
#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
#define HPSATMF_PHYS_CLEAR_ACA  (1 << 5)
#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
#define HPSATMF_PHYS_QRY_TASK   (1 << 7)
#define HPSATMF_PHYS_QRY_TSET   (1 << 8)
#define HPSATMF_PHYS_QRY_ASYNC  (1 << 9)
#define HPSATMF_MASK_SUPPORTED  (1 << 16)
#define HPSATMF_LOG_LUN_RESET   (1 << 17)
#define HPSATMF_LOG_NEX_RESET   (1 << 18)
#define HPSATMF_LOG_TASK_ABORT  (1 << 19)
#define HPSATMF_LOG_TSET_ABORT  (1 << 20)
#define HPSATMF_LOG_CLEAR_ACA   (1 << 21)
#define HPSATMF_LOG_CLEAR_TSET  (1 << 22)
#define HPSATMF_LOG_QRY_TASK    (1 << 23)
#define HPSATMF_LOG_QRY_TSET    (1 << 24)
#define HPSATMF_LOG_QRY_ASYNC   (1 << 25)
	u32 events;
};
#define HPSA_ABORT_MSG 0
#define HPSA_DEVICE_RESET_MSG 1
#define HPSA_RESET_TYPE_CONTROLLER 0x00
#define HPSA_RESET_TYPE_BUS 0x01
#define HPSA_RESET_TYPE_TARGET 0x03
#define HPSA_RESET_TYPE_LUN 0x04
#define HPSA_MSG_SEND_RETRY_LIMIT 10
#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)

/* Maximum time in seconds driver will wait for command completions
 * when polling before giving up.
 */
#define HPSA_MAX_POLL_TIME_SECS (20)

/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
 * how many times to retry TEST UNIT READY on a device
 * while waiting for it to become ready before giving up.
 * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
 * between sending TURs while waiting for a device
 * to become ready.
 */
#define HPSA_TUR_RETRY_LIMIT (20)
#define HPSA_MAX_WAIT_INTERVAL_SECS (30)

/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
 * to become ready, in seconds, before giving up on it.
 * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
 * between polling the board to see if it is ready, in
 * milliseconds.  HPSA_BOARD_READY_POLL_INTERVAL and
 * HPSA_BOARD_READY_ITERATIONS are derived from those.
 */
#define HPSA_BOARD_READY_WAIT_SECS (120)
#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
#define HPSA_BOARD_READY_POLL_INTERVAL \
	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
#define HPSA_BOARD_READY_ITERATIONS \
	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
#define HPSA_BOARD_NOT_READY_ITERATIONS \
	((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
		HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
#define HPSA_POST_RESET_PAUSE_MSECS (3000)
#define HPSA_POST_RESET_NOOP_RETRIES (12)

/*  Defining the diffent access_menthods */
/*
 * Memory mapped FIFO interface (SMART 53xx cards)
 */
#define SA5_DOORBELL	0x20
#define SA5_REQUEST_PORT_OFFSET	0x40
#define SA5_REPLY_INTR_MASK_OFFSET	0x34
#define SA5_REPLY_PORT_OFFSET		0x44
#define SA5_INTR_STATUS		0x30
#define SA5_SCRATCHPAD_OFFSET	0xB0

#define SA5_CTCFG_OFFSET	0xB4
#define SA5_CTMEM_OFFSET	0xB8

#define SA5_INTR_OFF		0x08
#define SA5B_INTR_OFF		0x04
#define SA5_INTR_PENDING	0x08
#define SA5B_INTR_PENDING	0x04
#define FIFO_EMPTY		0xffffffff
#define HPSA_FIRMWARE_READY	0xffff0000 /* value in scratchpad register */

#define HPSA_ERROR_BIT		0x02

/* Performant mode flags */
#define SA5_PERF_INTR_PENDING   0x04
#define SA5_PERF_INTR_OFF       0x05
#define SA5_OUTDB_STATUS_PERF_BIT       0x01
#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
#define SA5_OUTDB_CLEAR         0xA0
#define SA5_OUTDB_CLEAR_PERF_BIT        0x01
#define SA5_OUTDB_STATUS        0x9C


#define HPSA_INTR_ON 	1
#define HPSA_INTR_OFF	0

/*
 * Inbound Post Queue offsets for IO Accelerator Mode 2
 */
#define IOACCEL2_INBOUND_POSTQ_32	0x48
#define IOACCEL2_INBOUND_POSTQ_64_LOW	0xd0
#define IOACCEL2_INBOUND_POSTQ_64_HI	0xd4

/*
	Send the command to the hardware
*/
static void SA5_submit_command(struct ctlr_info *h,
	struct CommandList *c)
{
	dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
		c->Header.Tag.lower);
	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
}

static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
	struct CommandList *c)
{
	dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
		c->Header.Tag.lower);
	if (c->cmd_type == CMD_IOACCEL2)
		writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
	else
		writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
}

/*
 *  This card is the opposite of the other cards.
 *   0 turns interrupts on...
 *   0x08 turns them off...
 */
static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
{
	if (val) { /* Turn interrupts on */
		h->interrupts_enabled = 1;
		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	} else { /* Turn them off */
		h->interrupts_enabled = 0;
		writel(SA5_INTR_OFF,
			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	}
}

static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
{
	if (val) { /* turn on interrupts */
		h->interrupts_enabled = 1;
		writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	} else {
		h->interrupts_enabled = 0;
		writel(SA5_PERF_INTR_OFF,
			h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
		(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
	}
}

static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
{
	struct reply_pool *rq = &h->reply_queue[q];
	unsigned long flags, register_value = FIFO_EMPTY;

	/* msi auto clears the interrupt pending bit. */
	if (!(h->msi_vector || h->msix_vector)) {
		/* flush the controller write of the reply queue by reading
		 * outbound doorbell status register.
		 */
		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
		writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
		/* Do a read in order to flush the write to the controller
		 * (as per spec.)
		 */
		register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	}

	if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
		register_value = rq->head[rq->current_entry];
		rq->current_entry++;
		spin_lock_irqsave(&h->lock, flags);
		h->commands_outstanding--;
		spin_unlock_irqrestore(&h->lock, flags);
	} else {
		register_value = FIFO_EMPTY;
	}
	/* Check for wraparound */
	if (rq->current_entry == h->max_commands) {
		rq->current_entry = 0;
		rq->wraparound ^= 1;
	}
	return register_value;
}

/*
 *  Returns true if fifo is full.
 *
 */
static unsigned long SA5_fifo_full(struct ctlr_info *h)
{
	if (h->commands_outstanding >= h->max_commands)
		return 1;
	else
		return 0;

}
/*
 *   returns value read from hardware.
 *     returns FIFO_EMPTY if there is nothing to read
 */
static unsigned long SA5_completed(struct ctlr_info *h,
	__attribute__((unused)) u8 q)
{
	unsigned long register_value
		= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
	unsigned long flags;

	if (register_value != FIFO_EMPTY) {
		spin_lock_irqsave(&h->lock, flags);
		h->commands_outstanding--;
		spin_unlock_irqrestore(&h->lock, flags);
	}

#ifdef HPSA_DEBUG
	if (register_value != FIFO_EMPTY)
		dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
			register_value);
	else
		dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
#endif

	return register_value;
}
/*
 *	Returns true if an interrupt is pending..
 */
static bool SA5_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value  =
		readl(h->vaddr + SA5_INTR_STATUS);
	dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
	return register_value & SA5_INTR_PENDING;
}

static bool SA5_performant_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);

	if (!register_value)
		return false;

	if (h->msi_vector || h->msix_vector)
		return true;

	/* Read outbound doorbell to flush */
	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
}

#define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT    0x100

static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
{
	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);

	return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
		true : false;
}

#define IOACCEL_MODE1_REPLY_QUEUE_INDEX  0x1A0
#define IOACCEL_MODE1_PRODUCER_INDEX     0x1B8
#define IOACCEL_MODE1_CONSUMER_INDEX     0x1BC
#define IOACCEL_MODE1_REPLY_UNUSED       0xFFFFFFFFFFFFFFFFULL

static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
{
	u64 register_value;
	struct reply_pool *rq = &h->reply_queue[q];
	unsigned long flags;

	BUG_ON(q >= h->nreply_queues);

	register_value = rq->head[rq->current_entry];
	if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
		rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
		if (++rq->current_entry == rq->size)
			rq->current_entry = 0;
		/*
		 * @todo
		 *
		 * Don't really need to write the new index after each command,
		 * but with current driver design this is easiest.
		 */
		wmb();
		writel((q << 24) | rq->current_entry, h->vaddr +
				IOACCEL_MODE1_CONSUMER_INDEX);
		spin_lock_irqsave(&h->lock, flags);
		h->commands_outstanding--;
		spin_unlock_irqrestore(&h->lock, flags);
	}
	return (unsigned long) register_value;
}

static struct access_method SA5_access = {
	SA5_submit_command,
	SA5_intr_mask,
	SA5_fifo_full,
	SA5_intr_pending,
	SA5_completed,
};

static struct access_method SA5_ioaccel_mode1_access = {
	SA5_submit_command,
	SA5_performant_intr_mask,
	SA5_fifo_full,
	SA5_ioaccel_mode1_intr_pending,
	SA5_ioaccel_mode1_completed,
};

static struct access_method SA5_ioaccel_mode2_access = {
	SA5_submit_command_ioaccel2,
	SA5_performant_intr_mask,
	SA5_fifo_full,
	SA5_performant_intr_pending,
	SA5_performant_completed,
};

static struct access_method SA5_performant_access = {
	SA5_submit_command,
	SA5_performant_intr_mask,
	SA5_fifo_full,
	SA5_performant_intr_pending,
	SA5_performant_completed,
};

struct board_type {
	u32	board_id;
	char	*product_name;
	struct access_method *access;
};

#endif /* HPSA_H */
Commit	Line	Data
edd16368 SC	1	/*
	2	* Disk Array driver for HP Smart Array SAS controllers
	3	* Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
	4	*
	5	* This program is free software; you can redistribute it and/or modify
	6	* it under the terms of the GNU General Public License as published by
	7	* the Free Software Foundation; version 2 of the License.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
	12	* NON INFRINGEMENT. See the GNU General Public License for more details.
	13	*
	14	* You should have received a copy of the GNU General Public License
	15	* along with this program; if not, write to the Free Software
	16	* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
	17	*
	18	* Questions/Comments/Bugfixes to iss_storagedev@hp.com
	19	*
	20	*/
	21	#ifndef HPSA_H
	22	#define HPSA_H
	23
	24	#include <scsi/scsicam.h>
	25
	26	#define IO_OK 0
	27	#define IO_ERROR 1
	28
	29	struct ctlr_info;
	30
	31	struct access_method {
	32	void (submit_command)(struct ctlr_info h,
	33	struct CommandList *c);
	34	void (set_intr_mask)(struct ctlr_info h, unsigned long val);
	35	unsigned long (fifo_full)(struct ctlr_info h);
900c5440	36	bool (intr_pending)(struct ctlr_info h);
254f796b	37	unsigned long (command_completed)(struct ctlr_info h, u8 q);
edd16368 SC	38	};
	39
	40	struct hpsa_scsi_dev_t {
	41	int devtype;
	42	int bus, target, lun; /* as presented to the OS */
	43	unsigned char scsi3addr[8]; /* as presented to the HW */
	44	#define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0"
	45	unsigned char device_id[16]; /* from inquiry pg. 0x83 */
	46	unsigned char vendor[8]; /* bytes 8-15 of inquiry data */
	47	unsigned char model[16]; /* bytes 16-31 of inquiry data */
edd16368	48	unsigned char raid_level; /* from inquiry page 0xC1 */
e1f7de0c	49	u32 ioaccel_handle;
283b4a9b SC	50	int offload_config; /* I/O accel RAID offload configured */
	51	int offload_enabled; /* I/O accel RAID offload enabled */
	52	int offload_to_mirror; /* Send next I/O accelerator RAID
	53	* offload request to mirror drive
	54	*/
	55	struct raid_map_data raid_map; /* I/O accelerator RAID map */
	56
edd16368 SC	57	};
edd16368 SC	58
254f796b MG	59	struct reply_pool {
	60	u64 *head;
	61	size_t size;
	62	u8 wraparound;
	63	u32 current_entry;
	64	};
	65
edd16368 SC	66	struct ctlr_info {
	67	int ctlr;
	68	char devname[8];
	69	char *product_name;
edd16368	70	struct pci_dev *pdev;
01a02ffc	71	u32 board_id;
edd16368 SC	72	void __iomem *vaddr;
	73	unsigned long paddr;
	74	int nr_cmds; /* Number of commands allowed on this controller */
	75	struct CfgTable __iomem *cfgtable;
	76	int interrupts_enabled;
	77	int major;
	78	int max_commands;
	79	int commands_outstanding;
	80	int max_outstanding; /* Debug */
	81	int usage_count; /* number of opens all all minor devices */
303932fd DB	82	# define PERF_MODE_INT 0
303932fd DB	83	# define DOORBELL_INT 1
edd16368 SC	84	# define SIMPLE_MODE_INT 2
edd16368 SC	85	# define MEMQ_MODE_INT 3
254f796b	86	unsigned int intr[MAX_REPLY_QUEUES];
edd16368 SC	87	unsigned int msix_vector;
edd16368 SC	88	unsigned int msi_vector;
a9a3a273	89	int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */
edd16368 SC	90	struct access_method access;
	91
	92	/* queue and queue Info */
9e0fc764 SC	93	struct list_head reqQ;
9e0fc764 SC	94	struct list_head cmpQ;
edd16368	95	unsigned int Qdepth;
edd16368 SC	96	unsigned int maxSG;
edd16368 SC	97	spinlock_t lock;
33a2ffce SC	98	int maxsgentries;
	99	u8 max_cmd_sg_entries;
	100	int chainsize;
	101	struct SGDescriptor **cmd_sg_list;
edd16368 SC	102
	103	/* pointers to command and error info pool */
	104	struct CommandList *cmd_pool;
	105	dma_addr_t cmd_pool_dhandle;
e1f7de0c MG	106	struct io_accel1_cmd *ioaccel_cmd_pool;
e1f7de0c MG	107	dma_addr_t ioaccel_cmd_pool_dhandle;
aca9012a SC	108	struct io_accel2_cmd *ioaccel2_cmd_pool;
aca9012a SC	109	dma_addr_t ioaccel2_cmd_pool_dhandle;
edd16368 SC	110	struct ErrorInfo *errinfo_pool;
	111	dma_addr_t errinfo_pool_dhandle;
	112	unsigned long *cmd_pool_bits;
a08a8471 SC	113	int scan_finished;
	114	spinlock_t scan_lock;
	115	wait_queue_head_t scan_wait_queue;
edd16368 SC	116
	117	struct Scsi_Host *scsi_host;
	118	spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */
	119	int ndevices; /* number of used elements in .dev[] array. */
cfe5badc	120	struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES];
303932fd DB	121	/*
	122	* Performant mode tables.
	123	*/
	124	u32 trans_support;
	125	u32 trans_offset;
	126	struct TransTable_struct *transtable;
	127	unsigned long transMethod;
	128
0390f0c0 SC	129	/* cap concurrent passthrus at some reasonable maximum */
	130	#define HPSA_MAX_CONCURRENT_PASSTHRUS (20)
	131	spinlock_t passthru_count_lock; /* protects passthru_count */
	132	int passthru_count;
	133
303932fd	134	/*
254f796b	135	* Performant mode completion buffers
303932fd DB	136	*/
303932fd DB	137	u64 *reply_pool;
303932fd	138	size_t reply_pool_size;
254f796b MG	139	struct reply_pool reply_queue[MAX_REPLY_QUEUES];
	140	u8 nreply_queues;
	141	dma_addr_t reply_pool_dhandle;
303932fd	142	u32 *blockFetchTable;
e1f7de0c	143	u32 *ioaccel1_blockFetchTable;
aca9012a	144	u32 *ioaccel2_blockFetchTable;
b9af4937	145	u32 *ioaccel2_bft2_regs;
339b2b14	146	unsigned char *hba_inquiry_data;
283b4a9b SC	147	u32 driver_support;
	148	u32 fw_support;
	149	int ioaccel_support;
	150	int ioaccel_maxsg;
a0c12413 SC	151	u64 last_intr_timestamp;
	152	u32 last_heartbeat;
	153	u64 last_heartbeat_timestamp;
e85c5974 SC	154	u32 heartbeat_sample_interval;
e85c5974 SC	155	atomic_t firmware_flash_in_progress;
a0c12413	156	u32 lockup_detected;
8a98db73 SC	157	struct delayed_work monitor_ctlr_work;
8a98db73 SC	158	int remove_in_progress;
396883e2	159	u32 fifo_recently_full;
254f796b MG	160	/* Address of h->q[x] is passed to intr handler to know which queue */
254f796b MG	161	u8 q[MAX_REPLY_QUEUES];
75167d2c SC	162	u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */
	163	#define HPSATMF_BITS_SUPPORTED (1 << 0)
	164	#define HPSATMF_PHYS_LUN_RESET (1 << 1)
	165	#define HPSATMF_PHYS_NEX_RESET (1 << 2)
	166	#define HPSATMF_PHYS_TASK_ABORT (1 << 3)
	167	#define HPSATMF_PHYS_TSET_ABORT (1 << 4)
	168	#define HPSATMF_PHYS_CLEAR_ACA (1 << 5)
	169	#define HPSATMF_PHYS_CLEAR_TSET (1 << 6)
	170	#define HPSATMF_PHYS_QRY_TASK (1 << 7)
	171	#define HPSATMF_PHYS_QRY_TSET (1 << 8)
	172	#define HPSATMF_PHYS_QRY_ASYNC (1 << 9)
	173	#define HPSATMF_MASK_SUPPORTED (1 << 16)
	174	#define HPSATMF_LOG_LUN_RESET (1 << 17)
	175	#define HPSATMF_LOG_NEX_RESET (1 << 18)
	176	#define HPSATMF_LOG_TASK_ABORT (1 << 19)
	177	#define HPSATMF_LOG_TSET_ABORT (1 << 20)
	178	#define HPSATMF_LOG_CLEAR_ACA (1 << 21)
	179	#define HPSATMF_LOG_CLEAR_TSET (1 << 22)
	180	#define HPSATMF_LOG_QRY_TASK (1 << 23)
	181	#define HPSATMF_LOG_QRY_TSET (1 << 24)
	182	#define HPSATMF_LOG_QRY_ASYNC (1 << 25)
76438d08	183	u32 events;
edd16368 SC	184	};
	185	#define HPSA_ABORT_MSG 0
	186	#define HPSA_DEVICE_RESET_MSG 1
64670ac8 SC	187	#define HPSA_RESET_TYPE_CONTROLLER 0x00
	188	#define HPSA_RESET_TYPE_BUS 0x01
	189	#define HPSA_RESET_TYPE_TARGET 0x03
	190	#define HPSA_RESET_TYPE_LUN 0x04
edd16368	191	#define HPSA_MSG_SEND_RETRY_LIMIT 10
516fda49	192	#define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000)
edd16368 SC	193
	194	/* Maximum time in seconds driver will wait for command completions
	195	* when polling before giving up.
	196	*/
	197	#define HPSA_MAX_POLL_TIME_SECS (20)
	198
	199	/* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines
	200	* how many times to retry TEST UNIT READY on a device
	201	* while waiting for it to become ready before giving up.
	202	* HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval
	203	* between sending TURs while waiting for a device
	204	* to become ready.
	205	*/
	206	#define HPSA_TUR_RETRY_LIMIT (20)
	207	#define HPSA_MAX_WAIT_INTERVAL_SECS (30)
	208
	209	/* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board
	210	* to become ready, in seconds, before giving up on it.
	211	* HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait
	212	* between polling the board to see if it is ready, in
	213	* milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and
	214	* HPSA_BOARD_READY_ITERATIONS are derived from those.
	215	*/
	216	#define HPSA_BOARD_READY_WAIT_SECS (120)
2ed7127b	217	#define HPSA_BOARD_NOT_READY_WAIT_SECS (100)
edd16368 SC	218	#define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100)
	219	#define HPSA_BOARD_READY_POLL_INTERVAL \
	220	((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000)
	221	#define HPSA_BOARD_READY_ITERATIONS \
	222	((HPSA_BOARD_READY_WAIT_SECS * 1000) / \
	223	HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
fe5389c8 SC	224	#define HPSA_BOARD_NOT_READY_ITERATIONS \
	225	((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \
	226	HPSA_BOARD_READY_POLL_INTERVAL_MSECS)
edd16368 SC	227	#define HPSA_POST_RESET_PAUSE_MSECS (3000)
	228	#define HPSA_POST_RESET_NOOP_RETRIES (12)
	229
	230	/* Defining the diffent access_menthods */
	231	/*
	232	* Memory mapped FIFO interface (SMART 53xx cards)
	233	*/
	234	#define SA5_DOORBELL 0x20
	235	#define SA5_REQUEST_PORT_OFFSET 0x40
	236	#define SA5_REPLY_INTR_MASK_OFFSET 0x34
	237	#define SA5_REPLY_PORT_OFFSET 0x44
	238	#define SA5_INTR_STATUS 0x30
	239	#define SA5_SCRATCHPAD_OFFSET 0xB0
	240
	241	#define SA5_CTCFG_OFFSET 0xB4
	242	#define SA5_CTMEM_OFFSET 0xB8
	243
	244	#define SA5_INTR_OFF 0x08
	245	#define SA5B_INTR_OFF 0x04
	246	#define SA5_INTR_PENDING 0x08
	247	#define SA5B_INTR_PENDING 0x04
	248	#define FIFO_EMPTY 0xffffffff
	249	#define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */
	250
	251	#define HPSA_ERROR_BIT 0x02
edd16368	252
303932fd DB	253	/* Performant mode flags */
	254	#define SA5_PERF_INTR_PENDING 0x04
	255	#define SA5_PERF_INTR_OFF 0x05
	256	#define SA5_OUTDB_STATUS_PERF_BIT 0x01
	257	#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
	258	#define SA5_OUTDB_CLEAR 0xA0
	259	#define SA5_OUTDB_CLEAR_PERF_BIT 0x01
	260	#define SA5_OUTDB_STATUS 0x9C
	261
	262
edd16368 SC	263	#define HPSA_INTR_ON 1
edd16368 SC	264	#define HPSA_INTR_OFF 0
b66cc250 MM	265
	266	/*
	267	* Inbound Post Queue offsets for IO Accelerator Mode 2
	268	*/
	269	#define IOACCEL2_INBOUND_POSTQ_32 0x48
	270	#define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0
	271	#define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4
	272
edd16368 SC	273	/*
	274	Send the command to the hardware
	275	*/
	276	static void SA5_submit_command(struct ctlr_info *h,
	277	struct CommandList *c)
	278	{
303932fd DB	279	dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
303932fd DB	280	c->Header.Tag.lower);
edd16368	281	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
fec62c36	282	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
edd16368 SC	283	}
edd16368 SC	284
c349775e ST	285	static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
	286	struct CommandList *c)
	287	{
	288	dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
	289	c->Header.Tag.lower);
	290	if (c->cmd_type == CMD_IOACCEL2)
	291	writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
	292	else
	293	writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
	294	(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
	295	}
	296
edd16368 SC	297	/*
	298	* This card is the opposite of the other cards.
	299	* 0 turns interrupts on...
	300	* 0x08 turns them off...
	301	*/
	302	static void SA5_intr_mask(struct ctlr_info *h, unsigned long val)
	303	{
	304	if (val) { /* Turn interrupts on */
	305	h->interrupts_enabled = 1;
	306	writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	307	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
edd16368 SC	308	} else { /* Turn them off */
	309	h->interrupts_enabled = 0;
	310	writel(SA5_INTR_OFF,
	311	h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	312	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
edd16368 SC	313	}
edd16368 SC	314	}
303932fd DB	315
	316	static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val)
	317	{
	318	if (val) { /* turn on interrupts */
	319	h->interrupts_enabled = 1;
	320	writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	321	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
303932fd DB	322	} else {
	323	h->interrupts_enabled = 0;
	324	writel(SA5_PERF_INTR_OFF,
	325	h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
8cd21da7	326	(void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET);
303932fd DB	327	}
	328	}
	329
254f796b	330	static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q)
303932fd	331	{
254f796b	332	struct reply_pool *rq = &h->reply_queue[q];
e16a33ad	333	unsigned long flags, register_value = FIFO_EMPTY;
303932fd	334
303932fd DB	335	/* msi auto clears the interrupt pending bit. */
303932fd DB	336	if (!(h->msi_vector \|\| h->msix_vector)) {
2c17d2da SC	337	/* flush the controller write of the reply queue by reading
	338	* outbound doorbell status register.
	339	*/
	340	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
303932fd DB	341	writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR);
	342	/* Do a read in order to flush the write to the controller
	343	* (as per spec.)
	344	*/
	345	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	346	}
	347
254f796b MG	348	if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
	349	register_value = rq->head[rq->current_entry];
	350	rq->current_entry++;
e16a33ad	351	spin_lock_irqsave(&h->lock, flags);
303932fd	352	h->commands_outstanding--;
e16a33ad	353	spin_unlock_irqrestore(&h->lock, flags);
303932fd DB	354	} else {
	355	register_value = FIFO_EMPTY;
	356	}
	357	/* Check for wraparound */
254f796b MG	358	if (rq->current_entry == h->max_commands) {
	359	rq->current_entry = 0;
	360	rq->wraparound ^= 1;
303932fd	361	}
303932fd DB	362	return register_value;
	363	}
	364
edd16368 SC	365	/*
	366	* Returns true if fifo is full.
	367	*
	368	*/
	369	static unsigned long SA5_fifo_full(struct ctlr_info *h)
	370	{
	371	if (h->commands_outstanding >= h->max_commands)
	372	return 1;
	373	else
	374	return 0;
	375
	376	}
	377	/*
	378	* returns value read from hardware.
	379	* returns FIFO_EMPTY if there is nothing to read
	380	*/
254f796b MG	381	static unsigned long SA5_completed(struct ctlr_info *h,
254f796b MG	382	__attribute__((unused)) u8 q)
edd16368 SC	383	{
	384	unsigned long register_value
	385	= readl(h->vaddr + SA5_REPLY_PORT_OFFSET);
e16a33ad	386	unsigned long flags;
edd16368	387
e16a33ad MG	388	if (register_value != FIFO_EMPTY) {
e16a33ad MG	389	spin_lock_irqsave(&h->lock, flags);
edd16368	390	h->commands_outstanding--;
e16a33ad MG	391	spin_unlock_irqrestore(&h->lock, flags);
e16a33ad MG	392	}
edd16368 SC	393
	394	#ifdef HPSA_DEBUG
	395	if (register_value != FIFO_EMPTY)
84ca0be2	396	dev_dbg(&h->pdev->dev, "Read %lx back from board\n",
edd16368 SC	397	register_value);
edd16368 SC	398	else
f79cfec6	399	dev_dbg(&h->pdev->dev, "FIFO Empty read\n");
edd16368 SC	400	#endif
	401
	402	return register_value;
	403	}
	404	/*
	405	* Returns true if an interrupt is pending..
	406	*/
900c5440	407	static bool SA5_intr_pending(struct ctlr_info *h)
edd16368 SC	408	{
	409	unsigned long register_value =
	410	readl(h->vaddr + SA5_INTR_STATUS);
84ca0be2	411	dev_dbg(&h->pdev->dev, "intr_pending %lx\n", register_value);
900c5440	412	return register_value & SA5_INTR_PENDING;
edd16368 SC	413	}
edd16368 SC	414
303932fd DB	415	static bool SA5_performant_intr_pending(struct ctlr_info *h)
	416	{
	417	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
	418
	419	if (!register_value)
	420	return false;
	421
	422	if (h->msi_vector \|\| h->msix_vector)
	423	return true;
	424
	425	/* Read outbound doorbell to flush */
	426	register_value = readl(h->vaddr + SA5_OUTDB_STATUS);
	427	return register_value & SA5_OUTDB_STATUS_PERF_BIT;
	428	}
edd16368	429
e1f7de0c MG	430	#define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100
	431
	432	static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h)
	433	{
	434	unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS);
	435
	436	return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ?
	437	true : false;
	438	}
	439
	440	#define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0
	441	#define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8
	442	#define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC
	443	#define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL
	444
283b4a9b	445	static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q)
e1f7de0c MG	446	{
	447	u64 register_value;
	448	struct reply_pool *rq = &h->reply_queue[q];
	449	unsigned long flags;
	450
	451	BUG_ON(q >= h->nreply_queues);
	452
	453	register_value = rq->head[rq->current_entry];
	454	if (register_value != IOACCEL_MODE1_REPLY_UNUSED) {
	455	rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED;
	456	if (++rq->current_entry == rq->size)
	457	rq->current_entry = 0;
283b4a9b SC	458	/*
	459	* @todo
	460	*
	461	* Don't really need to write the new index after each command,
	462	* but with current driver design this is easiest.
	463	*/
	464	wmb();
	465	writel((q << 24) \| rq->current_entry, h->vaddr +
	466	IOACCEL_MODE1_CONSUMER_INDEX);
e1f7de0c MG	467	spin_lock_irqsave(&h->lock, flags);
	468	h->commands_outstanding--;
	469	spin_unlock_irqrestore(&h->lock, flags);
e1f7de0c MG	470	}
	471	return (unsigned long) register_value;
	472	}
	473
edd16368 SC	474	static struct access_method SA5_access = {
	475	SA5_submit_command,
	476	SA5_intr_mask,
	477	SA5_fifo_full,
	478	SA5_intr_pending,
	479	SA5_completed,
	480	};
	481
e1f7de0c MG	482	static struct access_method SA5_ioaccel_mode1_access = {
	483	SA5_submit_command,
	484	SA5_performant_intr_mask,
	485	SA5_fifo_full,
	486	SA5_ioaccel_mode1_intr_pending,
	487	SA5_ioaccel_mode1_completed,
	488	};
	489
c349775e ST	490	static struct access_method SA5_ioaccel_mode2_access = {
	491	SA5_submit_command_ioaccel2,
	492	SA5_performant_intr_mask,
	493	SA5_fifo_full,
	494	SA5_performant_intr_pending,
	495	SA5_performant_completed,
	496	};
	497
303932fd DB	498	static struct access_method SA5_performant_access = {
	499	SA5_submit_command,
	500	SA5_performant_intr_mask,
	501	SA5_fifo_full,
	502	SA5_performant_intr_pending,
	503	SA5_performant_completed,
	504	};
	505
edd16368	506	struct board_type {
01a02ffc	507	u32 board_id;
edd16368 SC	508	char *product_name;
	509	struct access_method *access;
	510	};
	511
edd16368 SC	512	#endif /* HPSA_H */
edd16368 SC	513