Commit | Line | Data |
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edd16368 SC |
1 | /* |
2 | * Disk Array driver for HP Smart Array SAS controllers | |
94c7bc31 | 3 | * Copyright 2016 Microsemi Corporation |
1358f6dc DB |
4 | * Copyright 2014-2015 PMC-Sierra, Inc. |
5 | * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P. | |
edd16368 SC |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License as published by | |
9 | * the Free Software Foundation; version 2 of the License. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
14 | * NON INFRINGEMENT. See the GNU General Public License for more details. | |
15 | * | |
94c7bc31 | 16 | * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com |
edd16368 SC |
17 | * |
18 | */ | |
19 | #ifndef HPSA_H | |
20 | #define HPSA_H | |
21 | ||
22 | #include <scsi/scsicam.h> | |
23 | ||
24 | #define IO_OK 0 | |
25 | #define IO_ERROR 1 | |
26 | ||
27 | struct ctlr_info; | |
28 | ||
29 | struct access_method { | |
30 | void (*submit_command)(struct ctlr_info *h, | |
31 | struct CommandList *c); | |
32 | void (*set_intr_mask)(struct ctlr_info *h, unsigned long val); | |
900c5440 | 33 | bool (*intr_pending)(struct ctlr_info *h); |
254f796b | 34 | unsigned long (*command_completed)(struct ctlr_info *h, u8 q); |
edd16368 SC |
35 | }; |
36 | ||
d04e62b9 KB |
37 | /* for SAS hosts and SAS expanders */ |
38 | struct hpsa_sas_node { | |
39 | struct device *parent_dev; | |
40 | struct list_head port_list_head; | |
41 | }; | |
42 | ||
43 | struct hpsa_sas_port { | |
44 | struct list_head port_list_entry; | |
45 | u64 sas_address; | |
46 | struct sas_port *port; | |
47 | int next_phy_index; | |
48 | struct list_head phy_list_head; | |
49 | struct hpsa_sas_node *parent_node; | |
50 | struct sas_rphy *rphy; | |
51 | }; | |
52 | ||
53 | struct hpsa_sas_phy { | |
54 | struct list_head phy_list_entry; | |
55 | struct sas_phy *phy; | |
56 | struct hpsa_sas_port *parent_port; | |
57 | bool added_to_port; | |
58 | }; | |
59 | ||
edd16368 | 60 | struct hpsa_scsi_dev_t { |
3ad7de6b | 61 | unsigned int devtype; |
edd16368 SC |
62 | int bus, target, lun; /* as presented to the OS */ |
63 | unsigned char scsi3addr[8]; /* as presented to the HW */ | |
04fa2f44 | 64 | u8 physical_device : 1; |
2a168208 | 65 | u8 expose_device; |
ba74fdc4 | 66 | u8 removed : 1; /* device is marked for death */ |
edd16368 SC |
67 | #define RAID_CTLR_LUNID "\0\0\0\0\0\0\0\0" |
68 | unsigned char device_id[16]; /* from inquiry pg. 0x83 */ | |
d04e62b9 | 69 | u64 sas_address; |
edd16368 SC |
70 | unsigned char vendor[8]; /* bytes 8-15 of inquiry data */ |
71 | unsigned char model[16]; /* bytes 16-31 of inquiry data */ | |
7630b3a5 | 72 | unsigned char rev; /* byte 2 of inquiry data */ |
edd16368 | 73 | unsigned char raid_level; /* from inquiry page 0xC1 */ |
9846590e | 74 | unsigned char volume_offline; /* discovered via TUR or VPD */ |
03383736 | 75 | u16 queue_depth; /* max queue_depth for this device */ |
d604f533 | 76 | atomic_t reset_cmds_out; /* Count of commands to-be affected */ |
03383736 DB |
77 | atomic_t ioaccel_cmds_out; /* Only used for physical devices |
78 | * counts commands sent to physical | |
79 | * device via "ioaccel" path. | |
80 | */ | |
e1f7de0c | 81 | u32 ioaccel_handle; |
8270b862 JH |
82 | u8 active_path_index; |
83 | u8 path_map; | |
84 | u8 bay; | |
85 | u8 box[8]; | |
86 | u16 phys_connector[8]; | |
283b4a9b SC |
87 | int offload_config; /* I/O accel RAID offload configured */ |
88 | int offload_enabled; /* I/O accel RAID offload enabled */ | |
41ce4c35 | 89 | int offload_to_be_enabled; |
a3144e0b | 90 | int hba_ioaccel_enabled; |
283b4a9b SC |
91 | int offload_to_mirror; /* Send next I/O accelerator RAID |
92 | * offload request to mirror drive | |
93 | */ | |
94 | struct raid_map_data raid_map; /* I/O accelerator RAID map */ | |
95 | ||
03383736 DB |
96 | /* |
97 | * Pointers from logical drive map indices to the phys drives that | |
98 | * make those logical drives. Note, multiple logical drives may | |
99 | * share physical drives. You can have for instance 5 physical | |
100 | * drives with 3 logical drives each using those same 5 physical | |
101 | * disks. We need these pointers for counting i/o's out to physical | |
102 | * devices in order to honor physical device queue depth limits. | |
103 | */ | |
104 | struct hpsa_scsi_dev_t *phys_disk[RAID_MAP_MAX_ENTRIES]; | |
d604f533 | 105 | int nphysical_disks; |
9b5c48c2 | 106 | int supports_aborts; |
d04e62b9 | 107 | struct hpsa_sas_port *sas_port; |
66749d0d | 108 | int external; /* 1-from external array 0-not <0-unknown */ |
edd16368 SC |
109 | }; |
110 | ||
072b0518 | 111 | struct reply_queue_buffer { |
254f796b MG |
112 | u64 *head; |
113 | size_t size; | |
114 | u8 wraparound; | |
115 | u32 current_entry; | |
072b0518 | 116 | dma_addr_t busaddr; |
254f796b MG |
117 | }; |
118 | ||
316b221a SC |
119 | #pragma pack(1) |
120 | struct bmic_controller_parameters { | |
121 | u8 led_flags; | |
122 | u8 enable_command_list_verification; | |
123 | u8 backed_out_write_drives; | |
124 | u16 stripes_for_parity; | |
125 | u8 parity_distribution_mode_flags; | |
126 | u16 max_driver_requests; | |
127 | u16 elevator_trend_count; | |
128 | u8 disable_elevator; | |
129 | u8 force_scan_complete; | |
130 | u8 scsi_transfer_mode; | |
131 | u8 force_narrow; | |
132 | u8 rebuild_priority; | |
133 | u8 expand_priority; | |
134 | u8 host_sdb_asic_fix; | |
135 | u8 pdpi_burst_from_host_disabled; | |
136 | char software_name[64]; | |
137 | char hardware_name[32]; | |
138 | u8 bridge_revision; | |
139 | u8 snapshot_priority; | |
140 | u32 os_specific; | |
141 | u8 post_prompt_timeout; | |
142 | u8 automatic_drive_slamming; | |
143 | u8 reserved1; | |
144 | u8 nvram_flags; | |
145 | u8 cache_nvram_flags; | |
146 | u8 drive_config_flags; | |
147 | u16 reserved2; | |
148 | u8 temp_warning_level; | |
149 | u8 temp_shutdown_level; | |
150 | u8 temp_condition_reset; | |
151 | u8 max_coalesce_commands; | |
152 | u32 max_coalesce_delay; | |
153 | u8 orca_password[4]; | |
154 | u8 access_id[16]; | |
155 | u8 reserved[356]; | |
156 | }; | |
157 | #pragma pack() | |
158 | ||
edd16368 SC |
159 | struct ctlr_info { |
160 | int ctlr; | |
161 | char devname[8]; | |
162 | char *product_name; | |
edd16368 | 163 | struct pci_dev *pdev; |
01a02ffc | 164 | u32 board_id; |
d04e62b9 | 165 | u64 sas_address; |
edd16368 SC |
166 | void __iomem *vaddr; |
167 | unsigned long paddr; | |
168 | int nr_cmds; /* Number of commands allowed on this controller */ | |
d54c5c24 SC |
169 | #define HPSA_CMDS_RESERVED_FOR_ABORTS 2 |
170 | #define HPSA_CMDS_RESERVED_FOR_DRIVER 1 | |
edd16368 SC |
171 | struct CfgTable __iomem *cfgtable; |
172 | int interrupts_enabled; | |
edd16368 | 173 | int max_commands; |
0cbf768e | 174 | atomic_t commands_outstanding; |
303932fd DB |
175 | # define PERF_MODE_INT 0 |
176 | # define DOORBELL_INT 1 | |
edd16368 SC |
177 | # define SIMPLE_MODE_INT 2 |
178 | # define MEMQ_MODE_INT 3 | |
bc2bb154 | 179 | unsigned int msix_vectors; |
a9a3a273 | 180 | int intr_mode; /* either PERF_MODE_INT or SIMPLE_MODE_INT */ |
edd16368 SC |
181 | struct access_method access; |
182 | ||
183 | /* queue and queue Info */ | |
edd16368 | 184 | unsigned int Qdepth; |
edd16368 SC |
185 | unsigned int maxSG; |
186 | spinlock_t lock; | |
33a2ffce SC |
187 | int maxsgentries; |
188 | u8 max_cmd_sg_entries; | |
189 | int chainsize; | |
190 | struct SGDescriptor **cmd_sg_list; | |
d9a729f3 | 191 | struct ioaccel2_sg_element **ioaccel2_cmd_sg_list; |
edd16368 SC |
192 | |
193 | /* pointers to command and error info pool */ | |
194 | struct CommandList *cmd_pool; | |
195 | dma_addr_t cmd_pool_dhandle; | |
e1f7de0c MG |
196 | struct io_accel1_cmd *ioaccel_cmd_pool; |
197 | dma_addr_t ioaccel_cmd_pool_dhandle; | |
aca9012a SC |
198 | struct io_accel2_cmd *ioaccel2_cmd_pool; |
199 | dma_addr_t ioaccel2_cmd_pool_dhandle; | |
edd16368 SC |
200 | struct ErrorInfo *errinfo_pool; |
201 | dma_addr_t errinfo_pool_dhandle; | |
202 | unsigned long *cmd_pool_bits; | |
a08a8471 | 203 | int scan_finished; |
87b9e6aa | 204 | u8 scan_waiting : 1; |
a08a8471 SC |
205 | spinlock_t scan_lock; |
206 | wait_queue_head_t scan_wait_queue; | |
edd16368 SC |
207 | |
208 | struct Scsi_Host *scsi_host; | |
209 | spinlock_t devlock; /* to protect hba[ctlr]->dev[]; */ | |
210 | int ndevices; /* number of used elements in .dev[] array. */ | |
cfe5badc | 211 | struct hpsa_scsi_dev_t *dev[HPSA_MAX_DEVICES]; |
303932fd DB |
212 | /* |
213 | * Performant mode tables. | |
214 | */ | |
215 | u32 trans_support; | |
216 | u32 trans_offset; | |
42a91641 | 217 | struct TransTable_struct __iomem *transtable; |
303932fd DB |
218 | unsigned long transMethod; |
219 | ||
0390f0c0 | 220 | /* cap concurrent passthrus at some reasonable maximum */ |
45fcb86e | 221 | #define HPSA_MAX_CONCURRENT_PASSTHRUS (10) |
34f0c627 | 222 | atomic_t passthru_cmds_avail; |
0390f0c0 | 223 | |
303932fd | 224 | /* |
254f796b | 225 | * Performant mode completion buffers |
303932fd | 226 | */ |
072b0518 SC |
227 | size_t reply_queue_size; |
228 | struct reply_queue_buffer reply_queue[MAX_REPLY_QUEUES]; | |
254f796b | 229 | u8 nreply_queues; |
303932fd | 230 | u32 *blockFetchTable; |
e1f7de0c | 231 | u32 *ioaccel1_blockFetchTable; |
aca9012a | 232 | u32 *ioaccel2_blockFetchTable; |
42a91641 | 233 | u32 __iomem *ioaccel2_bft2_regs; |
339b2b14 | 234 | unsigned char *hba_inquiry_data; |
283b4a9b SC |
235 | u32 driver_support; |
236 | u32 fw_support; | |
237 | int ioaccel_support; | |
238 | int ioaccel_maxsg; | |
a0c12413 SC |
239 | u64 last_intr_timestamp; |
240 | u32 last_heartbeat; | |
241 | u64 last_heartbeat_timestamp; | |
e85c5974 SC |
242 | u32 heartbeat_sample_interval; |
243 | atomic_t firmware_flash_in_progress; | |
42a91641 | 244 | u32 __percpu *lockup_detected; |
8a98db73 | 245 | struct delayed_work monitor_ctlr_work; |
6636e7f4 | 246 | struct delayed_work rescan_ctlr_work; |
8a98db73 | 247 | int remove_in_progress; |
254f796b MG |
248 | /* Address of h->q[x] is passed to intr handler to know which queue */ |
249 | u8 q[MAX_REPLY_QUEUES]; | |
8b47004a | 250 | char intrname[MAX_REPLY_QUEUES][16]; /* "hpsa0-msix00" names */ |
75167d2c SC |
251 | u32 TMFSupportFlags; /* cache what task mgmt funcs are supported. */ |
252 | #define HPSATMF_BITS_SUPPORTED (1 << 0) | |
253 | #define HPSATMF_PHYS_LUN_RESET (1 << 1) | |
254 | #define HPSATMF_PHYS_NEX_RESET (1 << 2) | |
255 | #define HPSATMF_PHYS_TASK_ABORT (1 << 3) | |
256 | #define HPSATMF_PHYS_TSET_ABORT (1 << 4) | |
257 | #define HPSATMF_PHYS_CLEAR_ACA (1 << 5) | |
258 | #define HPSATMF_PHYS_CLEAR_TSET (1 << 6) | |
259 | #define HPSATMF_PHYS_QRY_TASK (1 << 7) | |
260 | #define HPSATMF_PHYS_QRY_TSET (1 << 8) | |
261 | #define HPSATMF_PHYS_QRY_ASYNC (1 << 9) | |
8be986cc | 262 | #define HPSATMF_IOACCEL_ENABLED (1 << 15) |
75167d2c SC |
263 | #define HPSATMF_MASK_SUPPORTED (1 << 16) |
264 | #define HPSATMF_LOG_LUN_RESET (1 << 17) | |
265 | #define HPSATMF_LOG_NEX_RESET (1 << 18) | |
266 | #define HPSATMF_LOG_TASK_ABORT (1 << 19) | |
267 | #define HPSATMF_LOG_TSET_ABORT (1 << 20) | |
268 | #define HPSATMF_LOG_CLEAR_ACA (1 << 21) | |
269 | #define HPSATMF_LOG_CLEAR_TSET (1 << 22) | |
270 | #define HPSATMF_LOG_QRY_TASK (1 << 23) | |
271 | #define HPSATMF_LOG_QRY_TSET (1 << 24) | |
272 | #define HPSATMF_LOG_QRY_ASYNC (1 << 25) | |
76438d08 | 273 | u32 events; |
faff6ee0 SC |
274 | #define CTLR_STATE_CHANGE_EVENT (1 << 0) |
275 | #define CTLR_ENCLOSURE_HOT_PLUG_EVENT (1 << 1) | |
276 | #define CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV (1 << 4) | |
277 | #define CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV (1 << 5) | |
278 | #define CTLR_STATE_CHANGE_EVENT_REDUNDANT_CNTRL (1 << 6) | |
279 | #define CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED (1 << 30) | |
280 | #define CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE (1 << 31) | |
281 | ||
282 | #define RESCAN_REQUIRED_EVENT_BITS \ | |
7b2c46ee | 283 | (CTLR_ENCLOSURE_HOT_PLUG_EVENT | \ |
faff6ee0 SC |
284 | CTLR_STATE_CHANGE_EVENT_PHYSICAL_DRV | \ |
285 | CTLR_STATE_CHANGE_EVENT_LOGICAL_DRV | \ | |
faff6ee0 SC |
286 | CTLR_STATE_CHANGE_EVENT_AIO_ENABLED_DISABLED | \ |
287 | CTLR_STATE_CHANGE_EVENT_AIO_CONFIG_CHANGE) | |
9846590e SC |
288 | spinlock_t offline_device_lock; |
289 | struct list_head offline_device_list; | |
da0697bd | 290 | int acciopath_status; |
853633e8 | 291 | int drv_req_rescan; |
2ba8bfc8 | 292 | int raid_offload_debug; |
34592254 ST |
293 | int discovery_polling; |
294 | struct ReportLUNdata *lastlogicals; | |
9b5c48c2 | 295 | int needs_abort_tags_swizzled; |
080ef1cc | 296 | struct workqueue_struct *resubmit_wq; |
6636e7f4 | 297 | struct workqueue_struct *rescan_ctlr_wq; |
9b5c48c2 SC |
298 | atomic_t abort_cmds_available; |
299 | wait_queue_head_t abort_cmd_wait_queue; | |
d604f533 WS |
300 | wait_queue_head_t event_sync_wait_queue; |
301 | struct mutex reset_mutex; | |
da03ded0 | 302 | u8 reset_in_progress; |
d04e62b9 | 303 | struct hpsa_sas_node *sas_host; |
edd16368 | 304 | }; |
9846590e SC |
305 | |
306 | struct offline_device_entry { | |
307 | unsigned char scsi3addr[8]; | |
308 | struct list_head offline_list; | |
309 | }; | |
310 | ||
edd16368 SC |
311 | #define HPSA_ABORT_MSG 0 |
312 | #define HPSA_DEVICE_RESET_MSG 1 | |
64670ac8 SC |
313 | #define HPSA_RESET_TYPE_CONTROLLER 0x00 |
314 | #define HPSA_RESET_TYPE_BUS 0x01 | |
64670ac8 | 315 | #define HPSA_RESET_TYPE_LUN 0x04 |
0b9b7b6e | 316 | #define HPSA_PHYS_TARGET_RESET 0x99 /* not defined by cciss spec */ |
edd16368 | 317 | #define HPSA_MSG_SEND_RETRY_LIMIT 10 |
516fda49 | 318 | #define HPSA_MSG_SEND_RETRY_INTERVAL_MSECS (10000) |
edd16368 SC |
319 | |
320 | /* Maximum time in seconds driver will wait for command completions | |
321 | * when polling before giving up. | |
322 | */ | |
323 | #define HPSA_MAX_POLL_TIME_SECS (20) | |
324 | ||
325 | /* During SCSI error recovery, HPSA_TUR_RETRY_LIMIT defines | |
326 | * how many times to retry TEST UNIT READY on a device | |
327 | * while waiting for it to become ready before giving up. | |
328 | * HPSA_MAX_WAIT_INTERVAL_SECS is the max wait interval | |
329 | * between sending TURs while waiting for a device | |
330 | * to become ready. | |
331 | */ | |
332 | #define HPSA_TUR_RETRY_LIMIT (20) | |
333 | #define HPSA_MAX_WAIT_INTERVAL_SECS (30) | |
334 | ||
335 | /* HPSA_BOARD_READY_WAIT_SECS is how long to wait for a board | |
336 | * to become ready, in seconds, before giving up on it. | |
337 | * HPSA_BOARD_READY_POLL_INTERVAL_MSECS * is how long to wait | |
338 | * between polling the board to see if it is ready, in | |
339 | * milliseconds. HPSA_BOARD_READY_POLL_INTERVAL and | |
340 | * HPSA_BOARD_READY_ITERATIONS are derived from those. | |
341 | */ | |
342 | #define HPSA_BOARD_READY_WAIT_SECS (120) | |
2ed7127b | 343 | #define HPSA_BOARD_NOT_READY_WAIT_SECS (100) |
edd16368 SC |
344 | #define HPSA_BOARD_READY_POLL_INTERVAL_MSECS (100) |
345 | #define HPSA_BOARD_READY_POLL_INTERVAL \ | |
346 | ((HPSA_BOARD_READY_POLL_INTERVAL_MSECS * HZ) / 1000) | |
347 | #define HPSA_BOARD_READY_ITERATIONS \ | |
348 | ((HPSA_BOARD_READY_WAIT_SECS * 1000) / \ | |
349 | HPSA_BOARD_READY_POLL_INTERVAL_MSECS) | |
fe5389c8 SC |
350 | #define HPSA_BOARD_NOT_READY_ITERATIONS \ |
351 | ((HPSA_BOARD_NOT_READY_WAIT_SECS * 1000) / \ | |
352 | HPSA_BOARD_READY_POLL_INTERVAL_MSECS) | |
edd16368 SC |
353 | #define HPSA_POST_RESET_PAUSE_MSECS (3000) |
354 | #define HPSA_POST_RESET_NOOP_RETRIES (12) | |
355 | ||
356 | /* Defining the diffent access_menthods */ | |
357 | /* | |
358 | * Memory mapped FIFO interface (SMART 53xx cards) | |
359 | */ | |
360 | #define SA5_DOORBELL 0x20 | |
361 | #define SA5_REQUEST_PORT_OFFSET 0x40 | |
281a7fd0 WS |
362 | #define SA5_REQUEST_PORT64_LO_OFFSET 0xC0 |
363 | #define SA5_REQUEST_PORT64_HI_OFFSET 0xC4 | |
edd16368 SC |
364 | #define SA5_REPLY_INTR_MASK_OFFSET 0x34 |
365 | #define SA5_REPLY_PORT_OFFSET 0x44 | |
366 | #define SA5_INTR_STATUS 0x30 | |
367 | #define SA5_SCRATCHPAD_OFFSET 0xB0 | |
368 | ||
369 | #define SA5_CTCFG_OFFSET 0xB4 | |
370 | #define SA5_CTMEM_OFFSET 0xB8 | |
371 | ||
372 | #define SA5_INTR_OFF 0x08 | |
373 | #define SA5B_INTR_OFF 0x04 | |
374 | #define SA5_INTR_PENDING 0x08 | |
375 | #define SA5B_INTR_PENDING 0x04 | |
376 | #define FIFO_EMPTY 0xffffffff | |
377 | #define HPSA_FIRMWARE_READY 0xffff0000 /* value in scratchpad register */ | |
378 | ||
379 | #define HPSA_ERROR_BIT 0x02 | |
edd16368 | 380 | |
303932fd DB |
381 | /* Performant mode flags */ |
382 | #define SA5_PERF_INTR_PENDING 0x04 | |
383 | #define SA5_PERF_INTR_OFF 0x05 | |
384 | #define SA5_OUTDB_STATUS_PERF_BIT 0x01 | |
385 | #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 | |
386 | #define SA5_OUTDB_CLEAR 0xA0 | |
387 | #define SA5_OUTDB_CLEAR_PERF_BIT 0x01 | |
388 | #define SA5_OUTDB_STATUS 0x9C | |
389 | ||
390 | ||
edd16368 SC |
391 | #define HPSA_INTR_ON 1 |
392 | #define HPSA_INTR_OFF 0 | |
b66cc250 MM |
393 | |
394 | /* | |
395 | * Inbound Post Queue offsets for IO Accelerator Mode 2 | |
396 | */ | |
397 | #define IOACCEL2_INBOUND_POSTQ_32 0x48 | |
398 | #define IOACCEL2_INBOUND_POSTQ_64_LOW 0xd0 | |
399 | #define IOACCEL2_INBOUND_POSTQ_64_HI 0xd4 | |
400 | ||
c795505a KB |
401 | #define HPSA_PHYSICAL_DEVICE_BUS 0 |
402 | #define HPSA_RAID_VOLUME_BUS 1 | |
403 | #define HPSA_EXTERNAL_RAID_VOLUME_BUS 2 | |
09371d62 | 404 | #define HPSA_HBA_BUS 0 |
7630b3a5 | 405 | #define HPSA_LEGACY_HBA_BUS 3 |
c795505a | 406 | |
edd16368 SC |
407 | /* |
408 | Send the command to the hardware | |
409 | */ | |
410 | static void SA5_submit_command(struct ctlr_info *h, | |
411 | struct CommandList *c) | |
412 | { | |
edd16368 | 413 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
fec62c36 | 414 | (void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); |
edd16368 SC |
415 | } |
416 | ||
b3a52e79 SC |
417 | static void SA5_submit_command_no_read(struct ctlr_info *h, |
418 | struct CommandList *c) | |
419 | { | |
420 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); | |
421 | } | |
422 | ||
c349775e ST |
423 | static void SA5_submit_command_ioaccel2(struct ctlr_info *h, |
424 | struct CommandList *c) | |
425 | { | |
c05e8866 | 426 | writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET); |
c349775e ST |
427 | } |
428 | ||
edd16368 SC |
429 | /* |
430 | * This card is the opposite of the other cards. | |
431 | * 0 turns interrupts on... | |
432 | * 0x08 turns them off... | |
433 | */ | |
434 | static void SA5_intr_mask(struct ctlr_info *h, unsigned long val) | |
435 | { | |
436 | if (val) { /* Turn interrupts on */ | |
437 | h->interrupts_enabled = 1; | |
438 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
8cd21da7 | 439 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
edd16368 SC |
440 | } else { /* Turn them off */ |
441 | h->interrupts_enabled = 0; | |
442 | writel(SA5_INTR_OFF, | |
443 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
8cd21da7 | 444 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
edd16368 SC |
445 | } |
446 | } | |
303932fd DB |
447 | |
448 | static void SA5_performant_intr_mask(struct ctlr_info *h, unsigned long val) | |
449 | { | |
450 | if (val) { /* turn on interrupts */ | |
451 | h->interrupts_enabled = 1; | |
452 | writel(0, h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
8cd21da7 | 453 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
303932fd DB |
454 | } else { |
455 | h->interrupts_enabled = 0; | |
456 | writel(SA5_PERF_INTR_OFF, | |
457 | h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
8cd21da7 | 458 | (void) readl(h->vaddr + SA5_REPLY_INTR_MASK_OFFSET); |
303932fd DB |
459 | } |
460 | } | |
461 | ||
254f796b | 462 | static unsigned long SA5_performant_completed(struct ctlr_info *h, u8 q) |
303932fd | 463 | { |
072b0518 | 464 | struct reply_queue_buffer *rq = &h->reply_queue[q]; |
0cbf768e | 465 | unsigned long register_value = FIFO_EMPTY; |
303932fd | 466 | |
303932fd | 467 | /* msi auto clears the interrupt pending bit. */ |
bc2bb154 | 468 | if (unlikely(!(h->pdev->msi_enabled || h->msix_vectors))) { |
2c17d2da SC |
469 | /* flush the controller write of the reply queue by reading |
470 | * outbound doorbell status register. | |
471 | */ | |
bee266a6 | 472 | (void) readl(h->vaddr + SA5_OUTDB_STATUS); |
303932fd DB |
473 | writel(SA5_OUTDB_CLEAR_PERF_BIT, h->vaddr + SA5_OUTDB_CLEAR); |
474 | /* Do a read in order to flush the write to the controller | |
475 | * (as per spec.) | |
476 | */ | |
bee266a6 | 477 | (void) readl(h->vaddr + SA5_OUTDB_STATUS); |
303932fd DB |
478 | } |
479 | ||
bee266a6 | 480 | if ((((u32) rq->head[rq->current_entry]) & 1) == rq->wraparound) { |
254f796b MG |
481 | register_value = rq->head[rq->current_entry]; |
482 | rq->current_entry++; | |
0cbf768e | 483 | atomic_dec(&h->commands_outstanding); |
303932fd DB |
484 | } else { |
485 | register_value = FIFO_EMPTY; | |
486 | } | |
487 | /* Check for wraparound */ | |
254f796b MG |
488 | if (rq->current_entry == h->max_commands) { |
489 | rq->current_entry = 0; | |
490 | rq->wraparound ^= 1; | |
303932fd | 491 | } |
303932fd DB |
492 | return register_value; |
493 | } | |
494 | ||
edd16368 SC |
495 | /* |
496 | * returns value read from hardware. | |
497 | * returns FIFO_EMPTY if there is nothing to read | |
498 | */ | |
254f796b MG |
499 | static unsigned long SA5_completed(struct ctlr_info *h, |
500 | __attribute__((unused)) u8 q) | |
edd16368 SC |
501 | { |
502 | unsigned long register_value | |
503 | = readl(h->vaddr + SA5_REPLY_PORT_OFFSET); | |
504 | ||
0cbf768e SC |
505 | if (register_value != FIFO_EMPTY) |
506 | atomic_dec(&h->commands_outstanding); | |
edd16368 SC |
507 | |
508 | #ifdef HPSA_DEBUG | |
509 | if (register_value != FIFO_EMPTY) | |
84ca0be2 | 510 | dev_dbg(&h->pdev->dev, "Read %lx back from board\n", |
edd16368 SC |
511 | register_value); |
512 | else | |
f79cfec6 | 513 | dev_dbg(&h->pdev->dev, "FIFO Empty read\n"); |
edd16368 SC |
514 | #endif |
515 | ||
516 | return register_value; | |
517 | } | |
518 | /* | |
519 | * Returns true if an interrupt is pending.. | |
520 | */ | |
900c5440 | 521 | static bool SA5_intr_pending(struct ctlr_info *h) |
edd16368 SC |
522 | { |
523 | unsigned long register_value = | |
524 | readl(h->vaddr + SA5_INTR_STATUS); | |
900c5440 | 525 | return register_value & SA5_INTR_PENDING; |
edd16368 SC |
526 | } |
527 | ||
303932fd DB |
528 | static bool SA5_performant_intr_pending(struct ctlr_info *h) |
529 | { | |
530 | unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); | |
531 | ||
532 | if (!register_value) | |
533 | return false; | |
534 | ||
303932fd DB |
535 | /* Read outbound doorbell to flush */ |
536 | register_value = readl(h->vaddr + SA5_OUTDB_STATUS); | |
537 | return register_value & SA5_OUTDB_STATUS_PERF_BIT; | |
538 | } | |
edd16368 | 539 | |
e1f7de0c MG |
540 | #define SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT 0x100 |
541 | ||
542 | static bool SA5_ioaccel_mode1_intr_pending(struct ctlr_info *h) | |
543 | { | |
544 | unsigned long register_value = readl(h->vaddr + SA5_INTR_STATUS); | |
545 | ||
546 | return (register_value & SA5_IOACCEL_MODE1_INTR_STATUS_CMP_BIT) ? | |
547 | true : false; | |
548 | } | |
549 | ||
550 | #define IOACCEL_MODE1_REPLY_QUEUE_INDEX 0x1A0 | |
551 | #define IOACCEL_MODE1_PRODUCER_INDEX 0x1B8 | |
552 | #define IOACCEL_MODE1_CONSUMER_INDEX 0x1BC | |
553 | #define IOACCEL_MODE1_REPLY_UNUSED 0xFFFFFFFFFFFFFFFFULL | |
554 | ||
283b4a9b | 555 | static unsigned long SA5_ioaccel_mode1_completed(struct ctlr_info *h, u8 q) |
e1f7de0c MG |
556 | { |
557 | u64 register_value; | |
072b0518 | 558 | struct reply_queue_buffer *rq = &h->reply_queue[q]; |
e1f7de0c MG |
559 | |
560 | BUG_ON(q >= h->nreply_queues); | |
561 | ||
562 | register_value = rq->head[rq->current_entry]; | |
563 | if (register_value != IOACCEL_MODE1_REPLY_UNUSED) { | |
564 | rq->head[rq->current_entry] = IOACCEL_MODE1_REPLY_UNUSED; | |
565 | if (++rq->current_entry == rq->size) | |
566 | rq->current_entry = 0; | |
283b4a9b SC |
567 | /* |
568 | * @todo | |
569 | * | |
570 | * Don't really need to write the new index after each command, | |
571 | * but with current driver design this is easiest. | |
572 | */ | |
573 | wmb(); | |
574 | writel((q << 24) | rq->current_entry, h->vaddr + | |
575 | IOACCEL_MODE1_CONSUMER_INDEX); | |
0cbf768e | 576 | atomic_dec(&h->commands_outstanding); |
e1f7de0c MG |
577 | } |
578 | return (unsigned long) register_value; | |
579 | } | |
580 | ||
edd16368 | 581 | static struct access_method SA5_access = { |
93380123 KC |
582 | .submit_command = SA5_submit_command, |
583 | .set_intr_mask = SA5_intr_mask, | |
584 | .intr_pending = SA5_intr_pending, | |
585 | .command_completed = SA5_completed, | |
edd16368 SC |
586 | }; |
587 | ||
e1f7de0c | 588 | static struct access_method SA5_ioaccel_mode1_access = { |
93380123 KC |
589 | .submit_command = SA5_submit_command, |
590 | .set_intr_mask = SA5_performant_intr_mask, | |
591 | .intr_pending = SA5_ioaccel_mode1_intr_pending, | |
592 | .command_completed = SA5_ioaccel_mode1_completed, | |
e1f7de0c MG |
593 | }; |
594 | ||
c349775e | 595 | static struct access_method SA5_ioaccel_mode2_access = { |
93380123 KC |
596 | .submit_command = SA5_submit_command_ioaccel2, |
597 | .set_intr_mask = SA5_performant_intr_mask, | |
598 | .intr_pending = SA5_performant_intr_pending, | |
599 | .command_completed = SA5_performant_completed, | |
c349775e ST |
600 | }; |
601 | ||
303932fd | 602 | static struct access_method SA5_performant_access = { |
93380123 KC |
603 | .submit_command = SA5_submit_command, |
604 | .set_intr_mask = SA5_performant_intr_mask, | |
605 | .intr_pending = SA5_performant_intr_pending, | |
606 | .command_completed = SA5_performant_completed, | |
303932fd DB |
607 | }; |
608 | ||
b3a52e79 | 609 | static struct access_method SA5_performant_access_no_read = { |
93380123 KC |
610 | .submit_command = SA5_submit_command_no_read, |
611 | .set_intr_mask = SA5_performant_intr_mask, | |
612 | .intr_pending = SA5_performant_intr_pending, | |
613 | .command_completed = SA5_performant_completed, | |
b3a52e79 SC |
614 | }; |
615 | ||
edd16368 | 616 | struct board_type { |
01a02ffc | 617 | u32 board_id; |
edd16368 SC |
618 | char *product_name; |
619 | struct access_method *access; | |
620 | }; | |
621 | ||
edd16368 SC |
622 | #endif /* HPSA_H */ |
623 |