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[SCSI] hpsa: remove unused kthread.h header
[linux-block.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
51c35139 3 * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P.
edd16368
SC		 4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
a0c12413 50#include <linux/jiffies.h>
283b4a9b 51#include <asm/div64.h>
edd16368
SC		 52#include "hpsa_cmd.h"
53#include "hpsa.h"
54
55/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
e481cce8 56#define HPSA_DRIVER_VERSION "3.4.0-1"
edd16368 57#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 58#define HPSA "hpsa"
edd16368
SC		 59
60/* How long to wait (in milliseconds) for board to go into simple mode */
61#define MAX_CONFIG_WAIT 30000
62#define MAX_IOCTL_CONFIG_WAIT 1000
63
64/*define how many times we will try a command because of bus resets */
65#define MAX_CMD_RETRIES 3
66
67/* Embedded module documentation macros - see modules.h */
68MODULE_AUTHOR("Hewlett-Packard Company");
69MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
70 HPSA_DRIVER_VERSION);
71MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
72MODULE_VERSION(HPSA_DRIVER_VERSION);
73MODULE_LICENSE("GPL");
74
75static int hpsa_allow_any;
76module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
77MODULE_PARM_DESC(hpsa_allow_any,
78 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 79static int hpsa_simple_mode;
80module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
81MODULE_PARM_DESC(hpsa_simple_mode,
82 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 83
84/* define the PCI info for the cards we can control */
85static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 86 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
8e616a5e
SC		 121 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
122 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
123 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
124 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
125 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 126 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 127 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 128 {0,}
129};
130
131MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
132
133/* board_id = Subsystem Device ID & Vendor ID
134 * product = Marketing Name for the board
135 * access = Address of the struct of function pointers
136 */
137static struct board_type products[] = {
edd16368
SC		 138 {0x3241103C, "Smart Array P212", &SA5_access},
139 {0x3243103C, "Smart Array P410", &SA5_access},
140 {0x3245103C, "Smart Array P410i", &SA5_access},
141 {0x3247103C, "Smart Array P411", &SA5_access},
142 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 143 {0x324A103C, "Smart Array P712m", &SA5_access},
144 {0x324B103C, "Smart Array P711m", &SA5_access},
fe0c9610
MM		 145 {0x3350103C, "Smart Array P222", &SA5_access},
146 {0x3351103C, "Smart Array P420", &SA5_access},
147 {0x3352103C, "Smart Array P421", &SA5_access},
148 {0x3353103C, "Smart Array P822", &SA5_access},
149 {0x3354103C, "Smart Array P420i", &SA5_access},
150 {0x3355103C, "Smart Array P220i", &SA5_access},
151 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 152 {0x1921103C, "Smart Array P830i", &SA5_access},
153 {0x1922103C, "Smart Array P430", &SA5_access},
154 {0x1923103C, "Smart Array P431", &SA5_access},
155 {0x1924103C, "Smart Array P830", &SA5_access},
156 {0x1926103C, "Smart Array P731m", &SA5_access},
157 {0x1928103C, "Smart Array P230i", &SA5_access},
158 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 159 {0x21BD103C, "Smart Array", &SA5_access},
160 {0x21BE103C, "Smart Array", &SA5_access},
161 {0x21BF103C, "Smart Array", &SA5_access},
162 {0x21C0103C, "Smart Array", &SA5_access},
163 {0x21C1103C, "Smart Array", &SA5_access},
164 {0x21C2103C, "Smart Array", &SA5_access},
165 {0x21C3103C, "Smart Array", &SA5_access},
166 {0x21C4103C, "Smart Array", &SA5_access},
167 {0x21C5103C, "Smart Array", &SA5_access},
168 {0x21C7103C, "Smart Array", &SA5_access},
169 {0x21C8103C, "Smart Array", &SA5_access},
170 {0x21C9103C, "Smart Array", &SA5_access},
8e616a5e
SC		 171 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
172 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
173 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
174 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
175 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 176 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
177};
178
179static int number_of_controllers;
180
10f66018
SC		 181static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
182static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
edd16368
SC		 183static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
184static void start_io(struct ctlr_info *h);
185
186#ifdef CONFIG_COMPAT
187static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
188#endif
189
190static void cmd_free(struct ctlr_info *h, struct CommandList *c);
191static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
192static struct CommandList *cmd_alloc(struct ctlr_info *h);
193static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 194static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 195 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 196 int cmd_type);
b7bb24eb 197#define VPD_PAGE (1 << 8)
edd16368 198
f281233d 199static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 200static void hpsa_scan_start(struct Scsi_Host *);
201static int hpsa_scan_finished(struct Scsi_Host *sh,
202 unsigned long elapsed_time);
667e23d4
SC		 203static int hpsa_change_queue_depth(struct scsi_device *sdev,
204 int qdepth, int reason);
edd16368
SC		 205
206static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 207static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 208static int hpsa_slave_alloc(struct scsi_device *sdev);
209static void hpsa_slave_destroy(struct scsi_device *sdev);
210
edd16368 211static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 212static int check_for_unit_attention(struct ctlr_info *h,
213 struct CommandList *c);
214static void check_ioctl_unit_attention(struct ctlr_info *h,
215 struct CommandList *c);
303932fd
DB		 216/* performant mode helper functions */
217static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 218 int nsgs, int min_blocks, int *bucket_map);
6f039790 219static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 220static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 221static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
222 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
223 u64 *cfg_offset);
224static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
225 unsigned long *memory_bar);
226static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
227static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
228 int wait_for_ready);
75167d2c 229static inline void finish_cmd(struct CommandList *c);
283b4a9b 230static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 231#define BOARD_NOT_READY 0
232#define BOARD_READY 1
23100dd9 233static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 234static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 235static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
236 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
237 u8 *scsi3addr);
edd16368 238
edd16368
SC		 239static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
240{
241 unsigned long *priv = shost_priv(sdev->host);
242 return (struct ctlr_info *) *priv;
243}
244
a23513e8
SC		 245static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
246{
247 unsigned long *priv = shost_priv(sh);
248 return (struct ctlr_info *) *priv;
249}
250
edd16368
SC		 251static int check_for_unit_attention(struct ctlr_info *h,
252 struct CommandList *c)
253{
254 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
255 return 0;
256
257 switch (c->err_info->SenseInfo[12]) {
258 case STATE_CHANGED:
f79cfec6 259 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 260 "detected, command retried\n", h->ctlr);
261 break;
262 case LUN_FAILED:
f79cfec6 263 dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
edd16368
SC		 264 "detected, action required\n", h->ctlr);
265 break;
266 case REPORT_LUNS_CHANGED:
f79cfec6 267 dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
31468401 268 "changed, action required\n", h->ctlr);
edd16368 269 /*
4f4eb9f1
ST		 270 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
271 * target (array) devices.
edd16368
SC		 272 */
273 break;
274 case POWER_OR_RESET:
f79cfec6 275 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 276 "or device reset detected\n", h->ctlr);
277 break;
278 case UNIT_ATTENTION_CLEARED:
f79cfec6 279 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 280 "cleared by another initiator\n", h->ctlr);
281 break;
282 default:
f79cfec6 283 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 284 "unit attention detected\n", h->ctlr);
285 break;
286 }
287 return 1;
288}
289
852af20a
MB		 290static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
291{
292 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
293 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
294 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
295 return 0;
296 dev_warn(&h->pdev->dev, HPSA "device busy");
297 return 1;
298}
299
da0697bd
ST		 300static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
301 struct device_attribute *attr,
302 const char *buf, size_t count)
303{
304 int status, len;
305 struct ctlr_info *h;
306 struct Scsi_Host *shost = class_to_shost(dev);
307 char tmpbuf[10];
308
309 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
310 return -EACCES;
311 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
312 strncpy(tmpbuf, buf, len);
313 tmpbuf[len] = '\0';
314 if (sscanf(tmpbuf, "%d", &status) != 1)
315 return -EINVAL;
316 h = shost_to_hba(shost);
317 h->acciopath_status = !!status;
318 dev_warn(&h->pdev->dev,
319 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
320 h->acciopath_status ? "enabled" : "disabled");
321 return count;
322}
323
2ba8bfc8
SC		 324static ssize_t host_store_raid_offload_debug(struct device *dev,
325 struct device_attribute *attr,
326 const char *buf, size_t count)
327{
328 int debug_level, len;
329 struct ctlr_info *h;
330 struct Scsi_Host *shost = class_to_shost(dev);
331 char tmpbuf[10];
332
333 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
334 return -EACCES;
335 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
336 strncpy(tmpbuf, buf, len);
337 tmpbuf[len] = '\0';
338 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
339 return -EINVAL;
340 if (debug_level < 0)
341 debug_level = 0;
342 h = shost_to_hba(shost);
343 h->raid_offload_debug = debug_level;
344 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
345 h->raid_offload_debug);
346 return count;
347}
348
edd16368
SC		 349static ssize_t host_store_rescan(struct device *dev,
350 struct device_attribute *attr,
351 const char *buf, size_t count)
352{
353 struct ctlr_info *h;
354 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 355 h = shost_to_hba(shost);
31468401 356 hpsa_scan_start(h->scsi_host);
edd16368
SC		 357 return count;
358}
359
d28ce020
SC		 360static ssize_t host_show_firmware_revision(struct device *dev,
361 struct device_attribute *attr, char *buf)
362{
363 struct ctlr_info *h;
364 struct Scsi_Host *shost = class_to_shost(dev);
365 unsigned char *fwrev;
366
367 h = shost_to_hba(shost);
368 if (!h->hba_inquiry_data)
369 return 0;
370 fwrev = &h->hba_inquiry_data[32];
371 return snprintf(buf, 20, "%c%c%c%c\n",
372 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
373}
374
94a13649
SC		 375static ssize_t host_show_commands_outstanding(struct device *dev,
376 struct device_attribute *attr, char *buf)
377{
378 struct Scsi_Host *shost = class_to_shost(dev);
379 struct ctlr_info *h = shost_to_hba(shost);
380
381 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
382}
383
745a7a25
SC		 384static ssize_t host_show_transport_mode(struct device *dev,
385 struct device_attribute *attr, char *buf)
386{
387 struct ctlr_info *h;
388 struct Scsi_Host *shost = class_to_shost(dev);
389
390 h = shost_to_hba(shost);
391 return snprintf(buf, 20, "%s\n",
960a30e7 392 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 393 "performant" : "simple");
394}
395
da0697bd
ST		 396static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
397 struct device_attribute *attr, char *buf)
398{
399 struct ctlr_info *h;
400 struct Scsi_Host *shost = class_to_shost(dev);
401
402 h = shost_to_hba(shost);
403 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
404 (h->acciopath_status == 1) ? "enabled" : "disabled");
405}
406
46380786 407/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 408static u32 unresettable_controller[] = {
409 0x324a103C, /* Smart Array P712m */
410 0x324b103C, /* SmartArray P711m */
411 0x3223103C, /* Smart Array P800 */
412 0x3234103C, /* Smart Array P400 */
413 0x3235103C, /* Smart Array P400i */
414 0x3211103C, /* Smart Array E200i */
415 0x3212103C, /* Smart Array E200 */
416 0x3213103C, /* Smart Array E200i */
417 0x3214103C, /* Smart Array E200i */
418 0x3215103C, /* Smart Array E200i */
419 0x3237103C, /* Smart Array E500 */
420 0x323D103C, /* Smart Array P700m */
7af0abbc 421 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 422 0x409C0E11, /* Smart Array 6400 */
423 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 424 0x40700E11, /* Smart Array 5300 */
425 0x40820E11, /* Smart Array 532 */
426 0x40830E11, /* Smart Array 5312 */
427 0x409A0E11, /* Smart Array 641 */
428 0x409B0E11, /* Smart Array 642 */
429 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 430};
431
46380786
SC		 432/* List of controllers which cannot even be soft reset */
433static u32 soft_unresettable_controller[] = {
7af0abbc 434 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 435 0x40700E11, /* Smart Array 5300 */
436 0x40820E11, /* Smart Array 532 */
437 0x40830E11, /* Smart Array 5312 */
438 0x409A0E11, /* Smart Array 641 */
439 0x409B0E11, /* Smart Array 642 */
440 0x40910E11, /* Smart Array 6i */
46380786
SC		 441 /* Exclude 640x boards. These are two pci devices in one slot
442 * which share a battery backed cache module. One controls the
443 * cache, the other accesses the cache through the one that controls
444 * it. If we reset the one controlling the cache, the other will
445 * likely not be happy. Just forbid resetting this conjoined mess.
446 * The 640x isn't really supported by hpsa anyway.
447 */
448 0x409C0E11, /* Smart Array 6400 */
449 0x409D0E11, /* Smart Array 6400 EM */
450};
451
452static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 453{
454 int i;
455
456 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 457 if (unresettable_controller[i] == board_id)
458 return 0;
459 return 1;
460}
461
462static int ctlr_is_soft_resettable(u32 board_id)
463{
464 int i;
465
466 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
467 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 468 return 0;
469 return 1;
470}
471
46380786
SC		 472static int ctlr_is_resettable(u32 board_id)
473{
474 return ctlr_is_hard_resettable(board_id) ||
475 ctlr_is_soft_resettable(board_id);
476}
477
941b1cda
SC		 478static ssize_t host_show_resettable(struct device *dev,
479 struct device_attribute *attr, char *buf)
480{
481 struct ctlr_info *h;
482 struct Scsi_Host *shost = class_to_shost(dev);
483
484 h = shost_to_hba(shost);
46380786 485 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 486}
487
edd16368
SC		 488static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
489{
490 return (scsi3addr[3] & 0xC0) == 0x40;
491}
492
493static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 494 "1(ADM)", "UNKNOWN"
edd16368 495};
6b80b18f
ST		 496#define HPSA_RAID_0 0
497#define HPSA_RAID_4 1
498#define HPSA_RAID_1 2 /* also used for RAID 10 */
499#define HPSA_RAID_5 3 /* also used for RAID 50 */
500#define HPSA_RAID_51 4
501#define HPSA_RAID_6 5 /* also used for RAID 60 */
502#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 503#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
504
505static ssize_t raid_level_show(struct device *dev,
506 struct device_attribute *attr, char *buf)
507{
508 ssize_t l = 0;
82a72c0a 509 unsigned char rlevel;
edd16368
SC		 510 struct ctlr_info *h;
511 struct scsi_device *sdev;
512 struct hpsa_scsi_dev_t *hdev;
513 unsigned long flags;
514
515 sdev = to_scsi_device(dev);
516 h = sdev_to_hba(sdev);
517 spin_lock_irqsave(&h->lock, flags);
518 hdev = sdev->hostdata;
519 if (!hdev) {
520 spin_unlock_irqrestore(&h->lock, flags);
521 return -ENODEV;
522 }
523
524 /* Is this even a logical drive? */
525 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
526 spin_unlock_irqrestore(&h->lock, flags);
527 l = snprintf(buf, PAGE_SIZE, "N/A\n");
528 return l;
529 }
530
531 rlevel = hdev->raid_level;
532 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 533 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 534 rlevel = RAID_UNKNOWN;
535 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
536 return l;
537}
538
539static ssize_t lunid_show(struct device *dev,
540 struct device_attribute *attr, char *buf)
541{
542 struct ctlr_info *h;
543 struct scsi_device *sdev;
544 struct hpsa_scsi_dev_t *hdev;
545 unsigned long flags;
546 unsigned char lunid[8];
547
548 sdev = to_scsi_device(dev);
549 h = sdev_to_hba(sdev);
550 spin_lock_irqsave(&h->lock, flags);
551 hdev = sdev->hostdata;
552 if (!hdev) {
553 spin_unlock_irqrestore(&h->lock, flags);
554 return -ENODEV;
555 }
556 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
557 spin_unlock_irqrestore(&h->lock, flags);
558 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
559 lunid[0], lunid[1], lunid[2], lunid[3],
560 lunid[4], lunid[5], lunid[6], lunid[7]);
561}
562
563static ssize_t unique_id_show(struct device *dev,
564 struct device_attribute *attr, char *buf)
565{
566 struct ctlr_info *h;
567 struct scsi_device *sdev;
568 struct hpsa_scsi_dev_t *hdev;
569 unsigned long flags;
570 unsigned char sn[16];
571
572 sdev = to_scsi_device(dev);
573 h = sdev_to_hba(sdev);
574 spin_lock_irqsave(&h->lock, flags);
575 hdev = sdev->hostdata;
576 if (!hdev) {
577 spin_unlock_irqrestore(&h->lock, flags);
578 return -ENODEV;
579 }
580 memcpy(sn, hdev->device_id, sizeof(sn));
581 spin_unlock_irqrestore(&h->lock, flags);
582 return snprintf(buf, 16 * 2 + 2,
583 "%02X%02X%02X%02X%02X%02X%02X%02X"
584 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
585 sn[0], sn[1], sn[2], sn[3],
586 sn[4], sn[5], sn[6], sn[7],
587 sn[8], sn[9], sn[10], sn[11],
588 sn[12], sn[13], sn[14], sn[15]);
589}
590
c1988684
ST		 591static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
592 struct device_attribute *attr, char *buf)
593{
594 struct ctlr_info *h;
595 struct scsi_device *sdev;
596 struct hpsa_scsi_dev_t *hdev;
597 unsigned long flags;
598 int offload_enabled;
599
600 sdev = to_scsi_device(dev);
601 h = sdev_to_hba(sdev);
602 spin_lock_irqsave(&h->lock, flags);
603 hdev = sdev->hostdata;
604 if (!hdev) {
605 spin_unlock_irqrestore(&h->lock, flags);
606 return -ENODEV;
607 }
608 offload_enabled = hdev->offload_enabled;
609 spin_unlock_irqrestore(&h->lock, flags);
610 return snprintf(buf, 20, "%d\n", offload_enabled);
611}
612
3f5eac3a
SC		 613static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
614static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
615static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
616static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 617static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
618 host_show_hp_ssd_smart_path_enabled, NULL);
da0697bd
ST		 619static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
620 host_show_hp_ssd_smart_path_status,
621 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 622static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
623 host_store_raid_offload_debug);
3f5eac3a
SC		 624static DEVICE_ATTR(firmware_revision, S_IRUGO,
625 host_show_firmware_revision, NULL);
626static DEVICE_ATTR(commands_outstanding, S_IRUGO,
627 host_show_commands_outstanding, NULL);
628static DEVICE_ATTR(transport_mode, S_IRUGO,
629 host_show_transport_mode, NULL);
941b1cda
SC		 630static DEVICE_ATTR(resettable, S_IRUGO,
631 host_show_resettable, NULL);
3f5eac3a
SC		 632
633static struct device_attribute *hpsa_sdev_attrs[] = {
634 &dev_attr_raid_level,
635 &dev_attr_lunid,
636 &dev_attr_unique_id,
c1988684 637 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 638 NULL,
639};
640
641static struct device_attribute *hpsa_shost_attrs[] = {
642 &dev_attr_rescan,
643 &dev_attr_firmware_revision,
644 &dev_attr_commands_outstanding,
645 &dev_attr_transport_mode,
941b1cda 646 &dev_attr_resettable,
da0697bd 647 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 648 &dev_attr_raid_offload_debug,
3f5eac3a
SC		 649 NULL,
650};
651
652static struct scsi_host_template hpsa_driver_template = {
653 .module = THIS_MODULE,
f79cfec6
SC		 654 .name = HPSA,
655 .proc_name = HPSA,
3f5eac3a
SC		 656 .queuecommand = hpsa_scsi_queue_command,
657 .scan_start = hpsa_scan_start,
658 .scan_finished = hpsa_scan_finished,
659 .change_queue_depth = hpsa_change_queue_depth,
660 .this_id = -1,
661 .use_clustering = ENABLE_CLUSTERING,
75167d2c 662 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 663 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
664 .ioctl = hpsa_ioctl,
665 .slave_alloc = hpsa_slave_alloc,
666 .slave_destroy = hpsa_slave_destroy,
667#ifdef CONFIG_COMPAT
668 .compat_ioctl = hpsa_compat_ioctl,
669#endif
670 .sdev_attrs = hpsa_sdev_attrs,
671 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 672 .max_sectors = 8192,
54b2b50c 673 .no_write_same = 1,
3f5eac3a
SC		 674};
675
676
677/* Enqueuing and dequeuing functions for cmdlists. */
678static inline void addQ(struct list_head *list, struct CommandList *c)
679{
680 list_add_tail(&c->list, list);
681}
682
254f796b 683static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 684{
685 u32 a;
254f796b 686 struct reply_pool *rq = &h->reply_queue[q];
e16a33ad 687 unsigned long flags;
3f5eac3a 688
e1f7de0c
MG		 689 if (h->transMethod & CFGTBL_Trans_io_accel1)
690 return h->access.command_completed(h, q);
691
3f5eac3a 692 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 693 return h->access.command_completed(h, q);
3f5eac3a 694
254f796b
MG		 695 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
696 a = rq->head[rq->current_entry];
697 rq->current_entry++;
e16a33ad 698 spin_lock_irqsave(&h->lock, flags);
3f5eac3a 699 h->commands_outstanding--;
e16a33ad 700 spin_unlock_irqrestore(&h->lock, flags);
3f5eac3a
SC		 701 } else {
702 a = FIFO_EMPTY;
703 }
704 /* Check for wraparound */
254f796b
MG		 705 if (rq->current_entry == h->max_commands) {
706 rq->current_entry = 0;
707 rq->wraparound ^= 1;
3f5eac3a
SC		 708 }
709 return a;
710}
711
c349775e
ST		 712/*
713 * There are some special bits in the bus address of the
714 * command that we have to set for the controller to know
715 * how to process the command:
716 *
717 * Normal performant mode:
718 * bit 0: 1 means performant mode, 0 means simple mode.
719 * bits 1-3 = block fetch table entry
720 * bits 4-6 = command type (== 0)
721 *
722 * ioaccel1 mode:
723 * bit 0 = "performant mode" bit.
724 * bits 1-3 = block fetch table entry
725 * bits 4-6 = command type (== 110)
726 * (command type is needed because ioaccel1 mode
727 * commands are submitted through the same register as normal
728 * mode commands, so this is how the controller knows whether
729 * the command is normal mode or ioaccel1 mode.)
730 *
731 * ioaccel2 mode:
732 * bit 0 = "performant mode" bit.
733 * bits 1-4 = block fetch table entry (note extra bit)
734 * bits 4-6 = not needed, because ioaccel2 mode has
735 * a separate special register for submitting commands.
736 */
737
3f5eac3a
SC		 738/* set_performant_mode: Modify the tag for cciss performant
739 * set bit 0 for pull model, bits 3-1 for block fetch
740 * register number
741 */
742static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
743{
254f796b 744 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 745 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 746 if (likely(h->msix_vector > 0))
254f796b 747 c->Header.ReplyQueue =
804a5cb5 748 raw_smp_processor_id() % h->nreply_queues;
254f796b 749 }
3f5eac3a
SC		 750}
751
c349775e
ST		 752static void set_ioaccel1_performant_mode(struct ctlr_info *h,
753 struct CommandList *c)
754{
755 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
756
757 /* Tell the controller to post the reply to the queue for this
758 * processor. This seems to give the best I/O throughput.
759 */
760 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
761 /* Set the bits in the address sent down to include:
762 * - performant mode bit (bit 0)
763 * - pull count (bits 1-3)
764 * - command type (bits 4-6)
765 */
766 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
767 IOACCEL1_BUSADDR_CMDTYPE;
768}
769
770static void set_ioaccel2_performant_mode(struct ctlr_info *h,
771 struct CommandList *c)
772{
773 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
774
775 /* Tell the controller to post the reply to the queue for this
776 * processor. This seems to give the best I/O throughput.
777 */
778 cp->reply_queue = smp_processor_id() % h->nreply_queues;
779 /* Set the bits in the address sent down to include:
780 * - performant mode bit not used in ioaccel mode 2
781 * - pull count (bits 0-3)
782 * - command type isn't needed for ioaccel2
783 */
784 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
785}
786
e85c5974
SC		 787static int is_firmware_flash_cmd(u8 *cdb)
788{
789 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
790}
791
792/*
793 * During firmware flash, the heartbeat register may not update as frequently
794 * as it should. So we dial down lockup detection during firmware flash. and
795 * dial it back up when firmware flash completes.
796 */
797#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
798#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
799static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
800 struct CommandList *c)
801{
802 if (!is_firmware_flash_cmd(c->Request.CDB))
803 return;
804 atomic_inc(&h->firmware_flash_in_progress);
805 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
806}
807
808static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
809 struct CommandList *c)
810{
811 if (is_firmware_flash_cmd(c->Request.CDB) &&
812 atomic_dec_and_test(&h->firmware_flash_in_progress))
813 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
814}
815
3f5eac3a
SC		 816static void enqueue_cmd_and_start_io(struct ctlr_info *h,
817 struct CommandList *c)
818{
819 unsigned long flags;
820
c349775e
ST		 821 switch (c->cmd_type) {
822 case CMD_IOACCEL1:
823 set_ioaccel1_performant_mode(h, c);
824 break;
825 case CMD_IOACCEL2:
826 set_ioaccel2_performant_mode(h, c);
827 break;
828 default:
829 set_performant_mode(h, c);
830 }
e85c5974 831 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 832 spin_lock_irqsave(&h->lock, flags);
833 addQ(&h->reqQ, c);
834 h->Qdepth++;
3f5eac3a 835 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 836 start_io(h);
3f5eac3a
SC		 837}
838
839static inline void removeQ(struct CommandList *c)
840{
841 if (WARN_ON(list_empty(&c->list)))
842 return;
843 list_del_init(&c->list);
844}
845
846static inline int is_hba_lunid(unsigned char scsi3addr[])
847{
848 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
849}
850
851static inline int is_scsi_rev_5(struct ctlr_info *h)
852{
853 if (!h->hba_inquiry_data)
854 return 0;
855 if ((h->hba_inquiry_data[2] & 0x07) == 5)
856 return 1;
857 return 0;
858}
859
edd16368
SC		 860static int hpsa_find_target_lun(struct ctlr_info *h,
861 unsigned char scsi3addr[], int bus, int *target, int *lun)
862{
863 /* finds an unused bus, target, lun for a new physical device
864 * assumes h->devlock is held
865 */
866 int i, found = 0;
cfe5badc 867 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 868
263d9401 869 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 870
871 for (i = 0; i < h->ndevices; i++) {
872 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 873 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 874 }
875
263d9401
AM		 876 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
877 if (i < HPSA_MAX_DEVICES) {
878 /* *bus = 1; */
879 *target = i;
880 *lun = 0;
881 found = 1;
edd16368
SC		 882 }
883 return !found;
884}
885
886/* Add an entry into h->dev[] array. */
887static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
888 struct hpsa_scsi_dev_t *device,
889 struct hpsa_scsi_dev_t *added[], int *nadded)
890{
891 /* assumes h->devlock is held */
892 int n = h->ndevices;
893 int i;
894 unsigned char addr1[8], addr2[8];
895 struct hpsa_scsi_dev_t *sd;
896
cfe5badc 897 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 898 dev_err(&h->pdev->dev, "too many devices, some will be "
899 "inaccessible.\n");
900 return -1;
901 }
902
903 /* physical devices do not have lun or target assigned until now. */
904 if (device->lun != -1)
905 /* Logical device, lun is already assigned. */
906 goto lun_assigned;
907
908 /* If this device a non-zero lun of a multi-lun device
909 * byte 4 of the 8-byte LUN addr will contain the logical
910 * unit no, zero otherise.
911 */
912 if (device->scsi3addr[4] == 0) {
913 /* This is not a non-zero lun of a multi-lun device */
914 if (hpsa_find_target_lun(h, device->scsi3addr,
915 device->bus, &device->target, &device->lun) != 0)
916 return -1;
917 goto lun_assigned;
918 }
919
920 /* This is a non-zero lun of a multi-lun device.
921 * Search through our list and find the device which
922 * has the same 8 byte LUN address, excepting byte 4.
923 * Assign the same bus and target for this new LUN.
924 * Use the logical unit number from the firmware.
925 */
926 memcpy(addr1, device->scsi3addr, 8);
927 addr1[4] = 0;
928 for (i = 0; i < n; i++) {
929 sd = h->dev[i];
930 memcpy(addr2, sd->scsi3addr, 8);
931 addr2[4] = 0;
932 /* differ only in byte 4? */
933 if (memcmp(addr1, addr2, 8) == 0) {
934 device->bus = sd->bus;
935 device->target = sd->target;
936 device->lun = device->scsi3addr[4];
937 break;
938 }
939 }
940 if (device->lun == -1) {
941 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
942 " suspect firmware bug or unsupported hardware "
943 "configuration.\n");
944 return -1;
945 }
946
947lun_assigned:
948
949 h->dev[n] = device;
950 h->ndevices++;
951 added[*nadded] = device;
952 (*nadded)++;
953
954 /* initially, (before registering with scsi layer) we don't
955 * know our hostno and we don't want to print anything first
956 * time anyway (the scsi layer's inquiries will show that info)
957 */
958 /* if (hostno != -1) */
959 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
960 scsi_device_type(device->devtype), hostno,
961 device->bus, device->target, device->lun);
962 return 0;
963}
964
bd9244f7
ST		 965/* Update an entry in h->dev[] array. */
966static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
967 int entry, struct hpsa_scsi_dev_t *new_entry)
968{
969 /* assumes h->devlock is held */
970 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
971
972 /* Raid level changed. */
973 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 974
975 /* Raid offload parameters changed. */
976 h->dev[entry]->offload_config = new_entry->offload_config;
977 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
9fb0de2d
SC		 978 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
979 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
980 h->dev[entry]->raid_map = new_entry->raid_map;
250fb125 981
bd9244f7
ST		 982 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
983 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
984 new_entry->target, new_entry->lun);
985}
986
2a8ccf31
SC		 987/* Replace an entry from h->dev[] array. */
988static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
989 int entry, struct hpsa_scsi_dev_t *new_entry,
990 struct hpsa_scsi_dev_t *added[], int *nadded,
991 struct hpsa_scsi_dev_t *removed[], int *nremoved)
992{
993 /* assumes h->devlock is held */
cfe5badc 994 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 995 removed[*nremoved] = h->dev[entry];
996 (*nremoved)++;
01350d05
SC		 997
998 /*
999 * New physical devices won't have target/lun assigned yet
1000 * so we need to preserve the values in the slot we are replacing.
1001 */
1002 if (new_entry->target == -1) {
1003 new_entry->target = h->dev[entry]->target;
1004 new_entry->lun = h->dev[entry]->lun;
1005 }
1006
2a8ccf31
SC		 1007 h->dev[entry] = new_entry;
1008 added[*nadded] = new_entry;
1009 (*nadded)++;
1010 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
1011 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
1012 new_entry->target, new_entry->lun);
1013}
1014
edd16368
SC		 1015/* Remove an entry from h->dev[] array. */
1016static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
1017 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1018{
1019 /* assumes h->devlock is held */
1020 int i;
1021 struct hpsa_scsi_dev_t *sd;
1022
cfe5badc 1023 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1024
1025 sd = h->dev[entry];
1026 removed[*nremoved] = h->dev[entry];
1027 (*nremoved)++;
1028
1029 for (i = entry; i < h->ndevices-1; i++)
1030 h->dev[i] = h->dev[i+1];
1031 h->ndevices--;
1032 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
1033 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
1034 sd->lun);
1035}
1036
1037#define SCSI3ADDR_EQ(a, b) ( \
1038 (a)[7] == (b)[7] && \
1039 (a)[6] == (b)[6] && \
1040 (a)[5] == (b)[5] && \
1041 (a)[4] == (b)[4] && \
1042 (a)[3] == (b)[3] && \
1043 (a)[2] == (b)[2] && \
1044 (a)[1] == (b)[1] && \
1045 (a)[0] == (b)[0])
1046
1047static void fixup_botched_add(struct ctlr_info *h,
1048 struct hpsa_scsi_dev_t *added)
1049{
1050 /* called when scsi_add_device fails in order to re-adjust
1051 * h->dev[] to match the mid layer's view.
1052 */
1053 unsigned long flags;
1054 int i, j;
1055
1056 spin_lock_irqsave(&h->lock, flags);
1057 for (i = 0; i < h->ndevices; i++) {
1058 if (h->dev[i] == added) {
1059 for (j = i; j < h->ndevices-1; j++)
1060 h->dev[j] = h->dev[j+1];
1061 h->ndevices--;
1062 break;
1063 }
1064 }
1065 spin_unlock_irqrestore(&h->lock, flags);
1066 kfree(added);
1067}
1068
1069static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1070 struct hpsa_scsi_dev_t *dev2)
1071{
edd16368
SC		 1072 /* we compare everything except lun and target as these
1073 * are not yet assigned. Compare parts likely
1074 * to differ first
1075 */
1076 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1077 sizeof(dev1->scsi3addr)) != 0)
1078 return 0;
1079 if (memcmp(dev1->device_id, dev2->device_id,
1080 sizeof(dev1->device_id)) != 0)
1081 return 0;
1082 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1083 return 0;
1084 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1085 return 0;
edd16368
SC		 1086 if (dev1->devtype != dev2->devtype)
1087 return 0;
edd16368
SC		 1088 if (dev1->bus != dev2->bus)
1089 return 0;
1090 return 1;
1091}
1092
bd9244f7
ST		 1093static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1094 struct hpsa_scsi_dev_t *dev2)
1095{
1096 /* Device attributes that can change, but don't mean
1097 * that the device is a different device, nor that the OS
1098 * needs to be told anything about the change.
1099 */
1100 if (dev1->raid_level != dev2->raid_level)
1101 return 1;
250fb125
SC		 1102 if (dev1->offload_config != dev2->offload_config)
1103 return 1;
1104 if (dev1->offload_enabled != dev2->offload_enabled)
1105 return 1;
bd9244f7
ST		 1106 return 0;
1107}
1108
edd16368
SC		 1109/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1110 * and return needle location in *index. If scsi3addr matches, but not
1111 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1112 * location in *index.
1113 * In the case of a minor device attribute change, such as RAID level, just
1114 * return DEVICE_UPDATED, along with the updated device's location in index.
1115 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1116 */
1117static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1118 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1119 int *index)
1120{
1121 int i;
1122#define DEVICE_NOT_FOUND 0
1123#define DEVICE_CHANGED 1
1124#define DEVICE_SAME 2
bd9244f7 1125#define DEVICE_UPDATED 3
edd16368 1126 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1127 if (haystack[i] == NULL) /* previously removed. */
1128 continue;
edd16368
SC		 1129 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1130 *index = i;
bd9244f7
ST		 1131 if (device_is_the_same(needle, haystack[i])) {
1132 if (device_updated(needle, haystack[i]))
1133 return DEVICE_UPDATED;
edd16368 1134 return DEVICE_SAME;
bd9244f7 1135 } else {
edd16368 1136 return DEVICE_CHANGED;
bd9244f7 1137 }
edd16368
SC		 1138 }
1139 }
1140 *index = -1;
1141 return DEVICE_NOT_FOUND;
1142}
1143
4967bd3e 1144static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1145 struct hpsa_scsi_dev_t *sd[], int nsds)
1146{
1147 /* sd contains scsi3 addresses and devtypes, and inquiry
1148 * data. This function takes what's in sd to be the current
1149 * reality and updates h->dev[] to reflect that reality.
1150 */
1151 int i, entry, device_change, changes = 0;
1152 struct hpsa_scsi_dev_t *csd;
1153 unsigned long flags;
1154 struct hpsa_scsi_dev_t **added, **removed;
1155 int nadded, nremoved;
1156 struct Scsi_Host *sh = NULL;
1157
cfe5badc
ST		 1158 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1159 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1160
1161 if (!added || !removed) {
1162 dev_warn(&h->pdev->dev, "out of memory in "
1163 "adjust_hpsa_scsi_table\n");
1164 goto free_and_out;
1165 }
1166
1167 spin_lock_irqsave(&h->devlock, flags);
1168
1169 /* find any devices in h->dev[] that are not in
1170 * sd[] and remove them from h->dev[], and for any
1171 * devices which have changed, remove the old device
1172 * info and add the new device info.
bd9244f7
ST		 1173 * If minor device attributes change, just update
1174 * the existing device structure.
edd16368
SC		 1175 */
1176 i = 0;
1177 nremoved = 0;
1178 nadded = 0;
1179 while (i < h->ndevices) {
1180 csd = h->dev[i];
1181 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1182 if (device_change == DEVICE_NOT_FOUND) {
1183 changes++;
1184 hpsa_scsi_remove_entry(h, hostno, i,
1185 removed, &nremoved);
1186 continue; /* remove ^^^, hence i not incremented */
1187 } else if (device_change == DEVICE_CHANGED) {
1188 changes++;
2a8ccf31
SC		 1189 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1190 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1191 /* Set it to NULL to prevent it from being freed
1192 * at the bottom of hpsa_update_scsi_devices()
1193 */
1194 sd[entry] = NULL;
bd9244f7
ST		 1195 } else if (device_change == DEVICE_UPDATED) {
1196 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1197 }
1198 i++;
1199 }
1200
1201 /* Now, make sure every device listed in sd[] is also
1202 * listed in h->dev[], adding them if they aren't found
1203 */
1204
1205 for (i = 0; i < nsds; i++) {
1206 if (!sd[i]) /* if already added above. */
1207 continue;
1208 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1209 h->ndevices, &entry);
1210 if (device_change == DEVICE_NOT_FOUND) {
1211 changes++;
1212 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1213 added, &nadded) != 0)
1214 break;
1215 sd[i] = NULL; /* prevent from being freed later. */
1216 } else if (device_change == DEVICE_CHANGED) {
1217 /* should never happen... */
1218 changes++;
1219 dev_warn(&h->pdev->dev,
1220 "device unexpectedly changed.\n");
1221 /* but if it does happen, we just ignore that device */
1222 }
1223 }
1224 spin_unlock_irqrestore(&h->devlock, flags);
1225
1226 /* Don't notify scsi mid layer of any changes the first time through
1227 * (or if there are no changes) scsi_scan_host will do it later the
1228 * first time through.
1229 */
1230 if (hostno == -1 || !changes)
1231 goto free_and_out;
1232
1233 sh = h->scsi_host;
1234 /* Notify scsi mid layer of any removed devices */
1235 for (i = 0; i < nremoved; i++) {
1236 struct scsi_device *sdev =
1237 scsi_device_lookup(sh, removed[i]->bus,
1238 removed[i]->target, removed[i]->lun);
1239 if (sdev != NULL) {
1240 scsi_remove_device(sdev);
1241 scsi_device_put(sdev);
1242 } else {
1243 /* We don't expect to get here.
1244 * future cmds to this device will get selection
1245 * timeout as if the device was gone.
1246 */
1247 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1248 " for removal.", hostno, removed[i]->bus,
1249 removed[i]->target, removed[i]->lun);
1250 }
1251 kfree(removed[i]);
1252 removed[i] = NULL;
1253 }
1254
1255 /* Notify scsi mid layer of any added devices */
1256 for (i = 0; i < nadded; i++) {
1257 if (scsi_add_device(sh, added[i]->bus,
1258 added[i]->target, added[i]->lun) == 0)
1259 continue;
1260 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1261 "device not added.\n", hostno, added[i]->bus,
1262 added[i]->target, added[i]->lun);
1263 /* now we have to remove it from h->dev,
1264 * since it didn't get added to scsi mid layer
1265 */
1266 fixup_botched_add(h, added[i]);
1267 }
1268
1269free_and_out:
1270 kfree(added);
1271 kfree(removed);
edd16368
SC		 1272}
1273
1274/*
9e03aa2f 1275 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1276 * Assume's h->devlock is held.
1277 */
1278static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1279 int bus, int target, int lun)
1280{
1281 int i;
1282 struct hpsa_scsi_dev_t *sd;
1283
1284 for (i = 0; i < h->ndevices; i++) {
1285 sd = h->dev[i];
1286 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1287 return sd;
1288 }
1289 return NULL;
1290}
1291
1292/* link sdev->hostdata to our per-device structure. */
1293static int hpsa_slave_alloc(struct scsi_device *sdev)
1294{
1295 struct hpsa_scsi_dev_t *sd;
1296 unsigned long flags;
1297 struct ctlr_info *h;
1298
1299 h = sdev_to_hba(sdev);
1300 spin_lock_irqsave(&h->devlock, flags);
1301 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1302 sdev_id(sdev), sdev->lun);
1303 if (sd != NULL)
1304 sdev->hostdata = sd;
1305 spin_unlock_irqrestore(&h->devlock, flags);
1306 return 0;
1307}
1308
1309static void hpsa_slave_destroy(struct scsi_device *sdev)
1310{
bcc44255 1311 /* nothing to do. */
edd16368
SC		 1312}
1313
33a2ffce
SC		 1314static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1315{
1316 int i;
1317
1318 if (!h->cmd_sg_list)
1319 return;
1320 for (i = 0; i < h->nr_cmds; i++) {
1321 kfree(h->cmd_sg_list[i]);
1322 h->cmd_sg_list[i] = NULL;
1323 }
1324 kfree(h->cmd_sg_list);
1325 h->cmd_sg_list = NULL;
1326}
1327
1328static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1329{
1330 int i;
1331
1332 if (h->chainsize <= 0)
1333 return 0;
1334
1335 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1336 GFP_KERNEL);
1337 if (!h->cmd_sg_list)
1338 return -ENOMEM;
1339 for (i = 0; i < h->nr_cmds; i++) {
1340 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1341 h->chainsize, GFP_KERNEL);
1342 if (!h->cmd_sg_list[i])
1343 goto clean;
1344 }
1345 return 0;
1346
1347clean:
1348 hpsa_free_sg_chain_blocks(h);
1349 return -ENOMEM;
1350}
1351
e2bea6df 1352static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1353 struct CommandList *c)
1354{
1355 struct SGDescriptor *chain_sg, *chain_block;
1356 u64 temp64;
1357
1358 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1359 chain_block = h->cmd_sg_list[c->cmdindex];
1360 chain_sg->Ext = HPSA_SG_CHAIN;
1361 chain_sg->Len = sizeof(*chain_sg) *
1362 (c->Header.SGTotal - h->max_cmd_sg_entries);
1363 temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
1364 PCI_DMA_TODEVICE);
e2bea6df
SC		 1365 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1366 /* prevent subsequent unmapping */
1367 chain_sg->Addr.lower = 0;
1368 chain_sg->Addr.upper = 0;
1369 return -1;
1370 }
33a2ffce
SC		 1371 chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
1372 chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
e2bea6df 1373 return 0;
33a2ffce
SC		 1374}
1375
1376static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1377 struct CommandList *c)
1378{
1379 struct SGDescriptor *chain_sg;
1380 union u64bit temp64;
1381
1382 if (c->Header.SGTotal <= h->max_cmd_sg_entries)
1383 return;
1384
1385 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1386 temp64.val32.lower = chain_sg->Addr.lower;
1387 temp64.val32.upper = chain_sg->Addr.upper;
1388 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
1389}
1390
a09c1441
ST		 1391
1392/* Decode the various types of errors on ioaccel2 path.
1393 * Return 1 for any error that should generate a RAID path retry.
1394 * Return 0 for errors that don't require a RAID path retry.
1395 */
1396static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 1397 struct CommandList *c,
1398 struct scsi_cmnd *cmd,
1399 struct io_accel2_cmd *c2)
1400{
1401 int data_len;
a09c1441 1402 int retry = 0;
c349775e
ST		 1403
1404 switch (c2->error_data.serv_response) {
1405 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1406 switch (c2->error_data.status) {
1407 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1408 break;
1409 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1410 dev_warn(&h->pdev->dev,
1411 "%s: task complete with check condition.\n",
1412 "HP SSD Smart Path");
1413 if (c2->error_data.data_present !=
1414 IOACCEL2_SENSE_DATA_PRESENT)
1415 break;
1416 /* copy the sense data */
1417 data_len = c2->error_data.sense_data_len;
1418 if (data_len > SCSI_SENSE_BUFFERSIZE)
1419 data_len = SCSI_SENSE_BUFFERSIZE;
1420 if (data_len > sizeof(c2->error_data.sense_data_buff))
1421 data_len =
1422 sizeof(c2->error_data.sense_data_buff);
1423 memcpy(cmd->sense_buffer,
1424 c2->error_data.sense_data_buff, data_len);
1425 cmd->result |= SAM_STAT_CHECK_CONDITION;
a09c1441 1426 retry = 1;
c349775e
ST		 1427 break;
1428 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1429 dev_warn(&h->pdev->dev,
1430 "%s: task complete with BUSY status.\n",
1431 "HP SSD Smart Path");
a09c1441 1432 retry = 1;
c349775e
ST		 1433 break;
1434 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1435 dev_warn(&h->pdev->dev,
1436 "%s: task complete with reservation conflict.\n",
1437 "HP SSD Smart Path");
a09c1441 1438 retry = 1;
c349775e
ST		 1439 break;
1440 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1441 /* Make scsi midlayer do unlimited retries */
1442 cmd->result = DID_IMM_RETRY << 16;
1443 break;
1444 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1445 dev_warn(&h->pdev->dev,
1446 "%s: task complete with aborted status.\n",
1447 "HP SSD Smart Path");
a09c1441 1448 retry = 1;
c349775e
ST		 1449 break;
1450 default:
1451 dev_warn(&h->pdev->dev,
1452 "%s: task complete with unrecognized status: 0x%02x\n",
1453 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1454 retry = 1;
c349775e
ST		 1455 break;
1456 }
1457 break;
1458 case IOACCEL2_SERV_RESPONSE_FAILURE:
1459 /* don't expect to get here. */
1460 dev_warn(&h->pdev->dev,
1461 "unexpected delivery or target failure, status = 0x%02x\n",
1462 c2->error_data.status);
a09c1441 1463 retry = 1;
c349775e
ST		 1464 break;
1465 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1466 break;
1467 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1468 break;
1469 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1470 dev_warn(&h->pdev->dev, "task management function rejected.\n");
a09c1441 1471 retry = 1;
c349775e
ST		 1472 break;
1473 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1474 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1475 break;
1476 default:
1477 dev_warn(&h->pdev->dev,
1478 "%s: Unrecognized server response: 0x%02x\n",
a09c1441
ST		 1479 "HP SSD Smart Path",
1480 c2->error_data.serv_response);
1481 retry = 1;
c349775e
ST		 1482 break;
1483 }
a09c1441
ST		 1484
1485 return retry; /* retry on raid path? */
c349775e
ST		 1486}
1487
1488static void process_ioaccel2_completion(struct ctlr_info *h,
1489 struct CommandList *c, struct scsi_cmnd *cmd,
1490 struct hpsa_scsi_dev_t *dev)
1491{
1492 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
a09c1441 1493 int raid_retry = 0;
c349775e
ST		 1494
1495 /* check for good status */
1496 if (likely(c2->error_data.serv_response == 0 &&
1497 c2->error_data.status == 0)) {
1498 cmd_free(h, c);
1499 cmd->scsi_done(cmd);
1500 return;
1501 }
1502
1503 /* Any RAID offload error results in retry which will use
1504 * the normal I/O path so the controller can handle whatever's
1505 * wrong.
1506 */
1507 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1508 c2->error_data.serv_response ==
1509 IOACCEL2_SERV_RESPONSE_FAILURE) {
a09c1441
ST		 1510 if (c2->error_data.status ==
1511 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1512 dev_warn(&h->pdev->dev,
1513 "%s: Path is unavailable, retrying on standard path.\n",
1514 "HP SSD Smart Path");
1515 else
c349775e 1516 dev_warn(&h->pdev->dev,
a09c1441 1517 "%s: Error 0x%02x, retrying on standard path.\n",
c349775e 1518 "HP SSD Smart Path", c2->error_data.status);
a09c1441 1519
c349775e 1520 dev->offload_enabled = 0;
e863d68e 1521 h->drv_req_rescan = 1; /* schedule controller for a rescan */
c349775e
ST		 1522 cmd->result = DID_SOFT_ERROR << 16;
1523 cmd_free(h, c);
1524 cmd->scsi_done(cmd);
1525 return;
1526 }
a09c1441
ST		 1527 raid_retry = handle_ioaccel_mode2_error(h, c, cmd, c2);
1528 /* If error found, disable Smart Path, schedule a rescan,
1529 * and force a retry on the standard path.
1530 */
1531 if (raid_retry) {
1532 dev_warn(&h->pdev->dev, "%s: Retrying on standard path.\n",
1533 "HP SSD Smart Path");
1534 dev->offload_enabled = 0; /* Disable Smart Path */
1535 h->drv_req_rescan = 1; /* schedule controller rescan */
1536 cmd->result = DID_SOFT_ERROR << 16;
1537 }
c349775e
ST		 1538 cmd_free(h, c);
1539 cmd->scsi_done(cmd);
1540}
1541
1fb011fb 1542static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1543{
1544 struct scsi_cmnd *cmd;
1545 struct ctlr_info *h;
1546 struct ErrorInfo *ei;
283b4a9b 1547 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1548
1549 unsigned char sense_key;
1550 unsigned char asc; /* additional sense code */
1551 unsigned char ascq; /* additional sense code qualifier */
db111e18 1552 unsigned long sense_data_size;
edd16368
SC		 1553
1554 ei = cp->err_info;
1555 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1556 h = cp->h;
283b4a9b 1557 dev = cmd->device->hostdata;
edd16368
SC		 1558
1559 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1560 if ((cp->cmd_type == CMD_SCSI) &&
1561 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1562 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1563
1564 cmd->result = (DID_OK << 16); /* host byte */
1565 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1566
1567 if (cp->cmd_type == CMD_IOACCEL2)
1568 return process_ioaccel2_completion(h, cp, cmd, dev);
1569
5512672f 1570 cmd->result |= ei->ScsiStatus;
edd16368
SC		 1571
1572 /* copy the sense data whether we need to or not. */
db111e18
SC		 1573 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1574 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1575 else
1576 sense_data_size = sizeof(ei->SenseInfo);
1577 if (ei->SenseLen < sense_data_size)
1578 sense_data_size = ei->SenseLen;
1579
1580 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368
SC		 1581 scsi_set_resid(cmd, ei->ResidualCnt);
1582
1583 if (ei->CommandStatus == 0) {
edd16368 1584 cmd_free(h, cp);
2cc5bfaf 1585 cmd->scsi_done(cmd);
edd16368
SC		 1586 return;
1587 }
1588
e1f7de0c
MG		 1589 /* For I/O accelerator commands, copy over some fields to the normal
1590 * CISS header used below for error handling.
1591 */
1592 if (cp->cmd_type == CMD_IOACCEL1) {
1593 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1594 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1595 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
1596 cp->Header.Tag.lower = c->Tag.lower;
1597 cp->Header.Tag.upper = c->Tag.upper;
1598 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1599 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1600
1601 /* Any RAID offload error results in retry which will use
1602 * the normal I/O path so the controller can handle whatever's
1603 * wrong.
1604 */
1605 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1606 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1607 dev->offload_enabled = 0;
1608 cmd->result = DID_SOFT_ERROR << 16;
1609 cmd_free(h, cp);
1610 cmd->scsi_done(cmd);
1611 return;
1612 }
e1f7de0c
MG		 1613 }
1614
edd16368
SC		 1615 /* an error has occurred */
1616 switch (ei->CommandStatus) {
1617
1618 case CMD_TARGET_STATUS:
1619 if (ei->ScsiStatus) {
1620 /* Get sense key */
1621 sense_key = 0xf & ei->SenseInfo[2];
1622 /* Get additional sense code */
1623 asc = ei->SenseInfo[12];
1624 /* Get addition sense code qualifier */
1625 ascq = ei->SenseInfo[13];
1626 }
1627
1628 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
3ce438df 1629 if (check_for_unit_attention(h, cp))
edd16368 1630 break;
edd16368
SC		 1631 if (sense_key == ILLEGAL_REQUEST) {
1632 /*
1633 * SCSI REPORT_LUNS is commonly unsupported on
1634 * Smart Array. Suppress noisy complaint.
1635 */
1636 if (cp->Request.CDB[0] == REPORT_LUNS)
1637 break;
1638
1639 /* If ASC/ASCQ indicate Logical Unit
1640 * Not Supported condition,
1641 */
1642 if ((asc == 0x25) && (ascq == 0x0)) {
1643 dev_warn(&h->pdev->dev, "cp %p "
1644 "has check condition\n", cp);
1645 break;
1646 }
1647 }
1648
1649 if (sense_key == NOT_READY) {
1650 /* If Sense is Not Ready, Logical Unit
1651 * Not ready, Manual Intervention
1652 * required
1653 */
1654 if ((asc == 0x04) && (ascq == 0x03)) {
edd16368
SC		 1655 dev_warn(&h->pdev->dev, "cp %p "
1656 "has check condition: unit "
1657 "not ready, manual "
1658 "intervention required\n", cp);
1659 break;
1660 }
1661 }
1d3b3609
MG		 1662 if (sense_key == ABORTED_COMMAND) {
1663 /* Aborted command is retryable */
1664 dev_warn(&h->pdev->dev, "cp %p "
1665 "has check condition: aborted command: "
1666 "ASC: 0x%x, ASCQ: 0x%x\n",
1667 cp, asc, ascq);
2e311fba 1668 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1669 break;
1670 }
edd16368 1671 /* Must be some other type of check condition */
21b8e4ef 1672 dev_dbg(&h->pdev->dev, "cp %p has check condition: "
edd16368
SC		 1673 "unknown type: "
1674 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1675 "Returning result: 0x%x, "
1676 "cmd=[%02x %02x %02x %02x %02x "
807be732 1677 "%02x %02x %02x %02x %02x %02x "
edd16368
SC		 1678 "%02x %02x %02x %02x %02x]\n",
1679 cp, sense_key, asc, ascq,
1680 cmd->result,
1681 cmd->cmnd[0], cmd->cmnd[1],
1682 cmd->cmnd[2], cmd->cmnd[3],
1683 cmd->cmnd[4], cmd->cmnd[5],
1684 cmd->cmnd[6], cmd->cmnd[7],
807be732
MM		 1685 cmd->cmnd[8], cmd->cmnd[9],
1686 cmd->cmnd[10], cmd->cmnd[11],
1687 cmd->cmnd[12], cmd->cmnd[13],
1688 cmd->cmnd[14], cmd->cmnd[15]);
edd16368
SC		 1689 break;
1690 }
1691
1692
1693 /* Problem was not a check condition
1694 * Pass it up to the upper layers...
1695 */
1696 if (ei->ScsiStatus) {
1697 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1698 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1699 "Returning result: 0x%x\n",
1700 cp, ei->ScsiStatus,
1701 sense_key, asc, ascq,
1702 cmd->result);
1703 } else { /* scsi status is zero??? How??? */
1704 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1705 "Returning no connection.\n", cp),
1706
1707 /* Ordinarily, this case should never happen,
1708 * but there is a bug in some released firmware
1709 * revisions that allows it to happen if, for
1710 * example, a 4100 backplane loses power and
1711 * the tape drive is in it. We assume that
1712 * it's a fatal error of some kind because we
1713 * can't show that it wasn't. We will make it
1714 * look like selection timeout since that is
1715 * the most common reason for this to occur,
1716 * and it's severe enough.
1717 */
1718
1719 cmd->result = DID_NO_CONNECT << 16;
1720 }
1721 break;
1722
1723 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1724 break;
1725 case CMD_DATA_OVERRUN:
1726 dev_warn(&h->pdev->dev, "cp %p has"
1727 " completed with data overrun "
1728 "reported\n", cp);
1729 break;
1730 case CMD_INVALID: {
1731 /* print_bytes(cp, sizeof(*cp), 1, 0);
1732 print_cmd(cp); */
1733 /* We get CMD_INVALID if you address a non-existent device
1734 * instead of a selection timeout (no response). You will
1735 * see this if you yank out a drive, then try to access it.
1736 * This is kind of a shame because it means that any other
1737 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1738 * missing target. */
1739 cmd->result = DID_NO_CONNECT << 16;
1740 }
1741 break;
1742 case CMD_PROTOCOL_ERR:
256d0eaa 1743 cmd->result = DID_ERROR << 16;
edd16368 1744 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1745 "protocol error\n", cp);
edd16368
SC		 1746 break;
1747 case CMD_HARDWARE_ERR:
1748 cmd->result = DID_ERROR << 16;
1749 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1750 break;
1751 case CMD_CONNECTION_LOST:
1752 cmd->result = DID_ERROR << 16;
1753 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1754 break;
1755 case CMD_ABORTED:
1756 cmd->result = DID_ABORT << 16;
1757 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1758 cp, ei->ScsiStatus);
1759 break;
1760 case CMD_ABORT_FAILED:
1761 cmd->result = DID_ERROR << 16;
1762 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1763 break;
1764 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1765 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1766 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1767 "abort\n", cp);
1768 break;
1769 case CMD_TIMEOUT:
1770 cmd->result = DID_TIME_OUT << 16;
1771 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1772 break;
1d5e2ed0
SC		 1773 case CMD_UNABORTABLE:
1774 cmd->result = DID_ERROR << 16;
1775 dev_warn(&h->pdev->dev, "Command unabortable\n");
1776 break;
283b4a9b
SC		 1777 case CMD_IOACCEL_DISABLED:
1778 /* This only handles the direct pass-through case since RAID
1779 * offload is handled above. Just attempt a retry.
1780 */
1781 cmd->result = DID_SOFT_ERROR << 16;
1782 dev_warn(&h->pdev->dev,
1783 "cp %p had HP SSD Smart Path error\n", cp);
1784 break;
edd16368
SC		 1785 default:
1786 cmd->result = DID_ERROR << 16;
1787 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1788 cp, ei->CommandStatus);
1789 }
edd16368 1790 cmd_free(h, cp);
2cc5bfaf 1791 cmd->scsi_done(cmd);
edd16368
SC		 1792}
1793
edd16368
SC		 1794static void hpsa_pci_unmap(struct pci_dev *pdev,
1795 struct CommandList *c, int sg_used, int data_direction)
1796{
1797 int i;
1798 union u64bit addr64;
1799
1800 for (i = 0; i < sg_used; i++) {
1801 addr64.val32.lower = c->SG[i].Addr.lower;
1802 addr64.val32.upper = c->SG[i].Addr.upper;
1803 pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
1804 data_direction);
1805 }
1806}
1807
a2dac136 1808static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1809 struct CommandList *cp,
1810 unsigned char *buf,
1811 size_t buflen,
1812 int data_direction)
1813{
01a02ffc 1814 u64 addr64;
edd16368
SC		 1815
1816 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1817 cp->Header.SGList = 0;
1818 cp->Header.SGTotal = 0;
a2dac136 1819 return 0;
edd16368
SC		 1820 }
1821
01a02ffc 1822 addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1823 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1824 /* Prevent subsequent unmap of something never mapped */
eceaae18
SK		 1825 cp->Header.SGList = 0;
1826 cp->Header.SGTotal = 0;
a2dac136 1827 return -1;
eceaae18 1828 }
edd16368 1829 cp->SG[0].Addr.lower =
01a02ffc 1830 (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
edd16368 1831 cp->SG[0].Addr.upper =
01a02ffc 1832 (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
edd16368 1833 cp->SG[0].Len = buflen;
e1d9cbfa 1834 cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */
01a02ffc
SC		 1835 cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
1836 cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
a2dac136 1837 return 0;
edd16368
SC		 1838}
1839
1840static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1841 struct CommandList *c)
1842{
1843 DECLARE_COMPLETION_ONSTACK(wait);
1844
1845 c->waiting = &wait;
1846 enqueue_cmd_and_start_io(h, c);
1847 wait_for_completion(&wait);
1848}
1849
a0c12413
SC		 1850static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1851 struct CommandList *c)
1852{
1853 unsigned long flags;
1854
1855 /* If controller lockup detected, fake a hardware error. */
1856 spin_lock_irqsave(&h->lock, flags);
1857 if (unlikely(h->lockup_detected)) {
1858 spin_unlock_irqrestore(&h->lock, flags);
1859 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
1860 } else {
1861 spin_unlock_irqrestore(&h->lock, flags);
1862 hpsa_scsi_do_simple_cmd_core(h, c);
1863 }
1864}
1865
9c2fc160 1866#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1867static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
1868 struct CommandList *c, int data_direction)
1869{
9c2fc160 1870 int backoff_time = 10, retry_count = 0;
edd16368
SC		 1871
1872 do {
7630abd0 1873 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 1874 hpsa_scsi_do_simple_cmd_core(h, c);
1875 retry_count++;
9c2fc160
SC		 1876 if (retry_count > 3) {
1877 msleep(backoff_time);
1878 if (backoff_time < 1000)
1879 backoff_time *= 2;
1880 }
852af20a 1881 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 1882 check_for_busy(h, c)) &&
1883 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 1884 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
1885}
1886
d1e8beac
SC		 1887static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
1888 struct CommandList *c)
edd16368 1889{
d1e8beac
SC		 1890 const u8 *cdb = c->Request.CDB;
1891 const u8 *lun = c->Header.LUN.LunAddrBytes;
1892
1893 dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
1894 " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
1895 txt, lun[0], lun[1], lun[2], lun[3],
1896 lun[4], lun[5], lun[6], lun[7],
1897 cdb[0], cdb[1], cdb[2], cdb[3],
1898 cdb[4], cdb[5], cdb[6], cdb[7],
1899 cdb[8], cdb[9], cdb[10], cdb[11],
1900 cdb[12], cdb[13], cdb[14], cdb[15]);
1901}
1902
1903static void hpsa_scsi_interpret_error(struct ctlr_info *h,
1904 struct CommandList *cp)
1905{
1906 const struct ErrorInfo *ei = cp->err_info;
edd16368 1907 struct device *d = &cp->h->pdev->dev;
d1e8beac 1908 const u8 *sd = ei->SenseInfo;
edd16368 1909
edd16368
SC		 1910 switch (ei->CommandStatus) {
1911 case CMD_TARGET_STATUS:
d1e8beac
SC		 1912 hpsa_print_cmd(h, "SCSI status", cp);
1913 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
1914 dev_warn(d, "SCSI Status = 02, Sense key = %02x, ASC = %02x, ASCQ = %02x\n",
1915 sd[2] & 0x0f, sd[12], sd[13]);
1916 else
1917 dev_warn(d, "SCSI Status = %02x\n", ei->ScsiStatus);
edd16368
SC		 1918 if (ei->ScsiStatus == 0)
1919 dev_warn(d, "SCSI status is abnormally zero. "
1920 "(probably indicates selection timeout "
1921 "reported incorrectly due to a known "
1922 "firmware bug, circa July, 2001.)\n");
1923 break;
1924 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 1925 break;
1926 case CMD_DATA_OVERRUN:
d1e8beac 1927 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 1928 break;
1929 case CMD_INVALID: {
1930 /* controller unfortunately reports SCSI passthru's
1931 * to non-existent targets as invalid commands.
1932 */
d1e8beac
SC		 1933 hpsa_print_cmd(h, "invalid command", cp);
1934 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 1935 }
1936 break;
1937 case CMD_PROTOCOL_ERR:
d1e8beac 1938 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 1939 break;
1940 case CMD_HARDWARE_ERR:
d1e8beac 1941 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 1942 break;
1943 case CMD_CONNECTION_LOST:
d1e8beac 1944 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 1945 break;
1946 case CMD_ABORTED:
d1e8beac 1947 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 1948 break;
1949 case CMD_ABORT_FAILED:
d1e8beac 1950 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 1951 break;
1952 case CMD_UNSOLICITED_ABORT:
d1e8beac 1953 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 1954 break;
1955 case CMD_TIMEOUT:
d1e8beac 1956 hpsa_print_cmd(h, "timed out", cp);
edd16368 1957 break;
1d5e2ed0 1958 case CMD_UNABORTABLE:
d1e8beac 1959 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 1960 break;
edd16368 1961 default:
d1e8beac
SC		 1962 hpsa_print_cmd(h, "unknown status", cp);
1963 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 1964 ei->CommandStatus);
1965 }
1966}
1967
1968static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 1969 u16 page, unsigned char *buf,
edd16368
SC		 1970 unsigned char bufsize)
1971{
1972 int rc = IO_OK;
1973 struct CommandList *c;
1974 struct ErrorInfo *ei;
1975
1976 c = cmd_special_alloc(h);
1977
1978 if (c == NULL) { /* trouble... */
1979 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 1980 return -ENOMEM;
edd16368
SC		 1981 }
1982
a2dac136
SC		 1983 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
1984 page, scsi3addr, TYPE_CMD)) {
1985 rc = -1;
1986 goto out;
1987 }
edd16368
SC		 1988 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1989 ei = c->err_info;
1990 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 1991 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 1992 rc = -1;
1993 }
a2dac136 1994out:
edd16368
SC		 1995 cmd_special_free(h, c);
1996 return rc;
1997}
1998
bf711ac6
ST		 1999static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
2000 u8 reset_type)
edd16368
SC		 2001{
2002 int rc = IO_OK;
2003 struct CommandList *c;
2004 struct ErrorInfo *ei;
2005
2006 c = cmd_special_alloc(h);
2007
2008 if (c == NULL) { /* trouble... */
2009 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 2010 return -ENOMEM;
edd16368
SC		 2011 }
2012
a2dac136 2013 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 2014 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
2015 scsi3addr, TYPE_MSG);
2016 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 2017 hpsa_scsi_do_simple_cmd_core(h, c);
2018 /* no unmap needed here because no data xfer. */
2019
2020 ei = c->err_info;
2021 if (ei->CommandStatus != 0) {
d1e8beac 2022 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 2023 rc = -1;
2024 }
2025 cmd_special_free(h, c);
2026 return rc;
2027}
2028
2029static void hpsa_get_raid_level(struct ctlr_info *h,
2030 unsigned char *scsi3addr, unsigned char *raid_level)
2031{
2032 int rc;
2033 unsigned char *buf;
2034
2035 *raid_level = RAID_UNKNOWN;
2036 buf = kzalloc(64, GFP_KERNEL);
2037 if (!buf)
2038 return;
b7bb24eb 2039 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
edd16368
SC		 2040 if (rc == 0)
2041 *raid_level = buf[8];
2042 if (*raid_level > RAID_UNKNOWN)
2043 *raid_level = RAID_UNKNOWN;
2044 kfree(buf);
2045 return;
2046}
2047
283b4a9b
SC		 2048#define HPSA_MAP_DEBUG
2049#ifdef HPSA_MAP_DEBUG
2050static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
2051 struct raid_map_data *map_buff)
2052{
2053 struct raid_map_disk_data *dd = &map_buff->data[0];
2054 int map, row, col;
2055 u16 map_cnt, row_cnt, disks_per_row;
2056
2057 if (rc != 0)
2058 return;
2059
2ba8bfc8
SC		 2060 /* Show details only if debugging has been activated. */
2061 if (h->raid_offload_debug < 2)
2062 return;
2063
283b4a9b
SC		 2064 dev_info(&h->pdev->dev, "structure_size = %u\n",
2065 le32_to_cpu(map_buff->structure_size));
2066 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
2067 le32_to_cpu(map_buff->volume_blk_size));
2068 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
2069 le64_to_cpu(map_buff->volume_blk_cnt));
2070 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
2071 map_buff->phys_blk_shift);
2072 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
2073 map_buff->parity_rotation_shift);
2074 dev_info(&h->pdev->dev, "strip_size = %u\n",
2075 le16_to_cpu(map_buff->strip_size));
2076 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
2077 le64_to_cpu(map_buff->disk_starting_blk));
2078 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
2079 le64_to_cpu(map_buff->disk_blk_cnt));
2080 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
2081 le16_to_cpu(map_buff->data_disks_per_row));
2082 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
2083 le16_to_cpu(map_buff->metadata_disks_per_row));
2084 dev_info(&h->pdev->dev, "row_cnt = %u\n",
2085 le16_to_cpu(map_buff->row_cnt));
2086 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
2087 le16_to_cpu(map_buff->layout_map_count));
dd0e19f3
ST		 2088 dev_info(&h->pdev->dev, "flags = %u\n",
2089 le16_to_cpu(map_buff->flags));
2090 if (map_buff->flags & RAID_MAP_FLAG_ENCRYPT_ON)
2091 dev_info(&h->pdev->dev, "encrypytion = ON\n");
2092 else
2093 dev_info(&h->pdev->dev, "encrypytion = OFF\n");
2094 dev_info(&h->pdev->dev, "dekindex = %u\n",
2095 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 2096
2097 map_cnt = le16_to_cpu(map_buff->layout_map_count);
2098 for (map = 0; map < map_cnt; map++) {
2099 dev_info(&h->pdev->dev, "Map%u:\n", map);
2100 row_cnt = le16_to_cpu(map_buff->row_cnt);
2101 for (row = 0; row < row_cnt; row++) {
2102 dev_info(&h->pdev->dev, " Row%u:\n", row);
2103 disks_per_row =
2104 le16_to_cpu(map_buff->data_disks_per_row);
2105 for (col = 0; col < disks_per_row; col++, dd++)
2106 dev_info(&h->pdev->dev,
2107 " D%02u: h=0x%04x xor=%u,%u\n",
2108 col, dd->ioaccel_handle,
2109 dd->xor_mult[0], dd->xor_mult[1]);
2110 disks_per_row =
2111 le16_to_cpu(map_buff->metadata_disks_per_row);
2112 for (col = 0; col < disks_per_row; col++, dd++)
2113 dev_info(&h->pdev->dev,
2114 " M%02u: h=0x%04x xor=%u,%u\n",
2115 col, dd->ioaccel_handle,
2116 dd->xor_mult[0], dd->xor_mult[1]);
2117 }
2118 }
2119}
2120#else
2121static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
2122 __attribute__((unused)) int rc,
2123 __attribute__((unused)) struct raid_map_data *map_buff)
2124{
2125}
2126#endif
2127
2128static int hpsa_get_raid_map(struct ctlr_info *h,
2129 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2130{
2131 int rc = 0;
2132 struct CommandList *c;
2133 struct ErrorInfo *ei;
2134
2135 c = cmd_special_alloc(h);
2136 if (c == NULL) {
2137 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2138 return -ENOMEM;
2139 }
2140 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2141 sizeof(this_device->raid_map), 0,
2142 scsi3addr, TYPE_CMD)) {
2143 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
2144 cmd_special_free(h, c);
2145 return -ENOMEM;
2146 }
2147 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2148 ei = c->err_info;
2149 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2150 hpsa_scsi_interpret_error(h, c);
283b4a9b
SC		 2151 cmd_special_free(h, c);
2152 return -1;
2153 }
2154 cmd_special_free(h, c);
2155
2156 /* @todo in the future, dynamically allocate RAID map memory */
2157 if (le32_to_cpu(this_device->raid_map.structure_size) >
2158 sizeof(this_device->raid_map)) {
2159 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2160 rc = -1;
2161 }
2162 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2163 return rc;
2164}
2165
1b70150a
SC		 2166static int hpsa_vpd_page_supported(struct ctlr_info *h,
2167 unsigned char scsi3addr[], u8 page)
2168{
2169 int rc;
2170 int i;
2171 int pages;
2172 unsigned char *buf, bufsize;
2173
2174 buf = kzalloc(256, GFP_KERNEL);
2175 if (!buf)
2176 return 0;
2177
2178 /* Get the size of the page list first */
2179 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2180 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2181 buf, HPSA_VPD_HEADER_SZ);
2182 if (rc != 0)
2183 goto exit_unsupported;
2184 pages = buf[3];
2185 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
2186 bufsize = pages + HPSA_VPD_HEADER_SZ;
2187 else
2188 bufsize = 255;
2189
2190 /* Get the whole VPD page list */
2191 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2192 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
2193 buf, bufsize);
2194 if (rc != 0)
2195 goto exit_unsupported;
2196
2197 pages = buf[3];
2198 for (i = 1; i <= pages; i++)
2199 if (buf[3 + i] == page)
2200 goto exit_supported;
2201exit_unsupported:
2202 kfree(buf);
2203 return 0;
2204exit_supported:
2205 kfree(buf);
2206 return 1;
2207}
2208
283b4a9b
SC		 2209static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2210 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2211{
2212 int rc;
2213 unsigned char *buf;
2214 u8 ioaccel_status;
2215
2216 this_device->offload_config = 0;
2217 this_device->offload_enabled = 0;
2218
2219 buf = kzalloc(64, GFP_KERNEL);
2220 if (!buf)
2221 return;
1b70150a
SC		 2222 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
2223 goto out;
283b4a9b 2224 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 2225 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 2226 if (rc != 0)
2227 goto out;
2228
2229#define IOACCEL_STATUS_BYTE 4
2230#define OFFLOAD_CONFIGURED_BIT 0x01
2231#define OFFLOAD_ENABLED_BIT 0x02
2232 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2233 this_device->offload_config =
2234 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2235 if (this_device->offload_config) {
2236 this_device->offload_enabled =
2237 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2238 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2239 this_device->offload_enabled = 0;
2240 }
2241out:
2242 kfree(buf);
2243 return;
2244}
2245
edd16368
SC		 2246/* Get the device id from inquiry page 0x83 */
2247static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2248 unsigned char *device_id, int buflen)
2249{
2250 int rc;
2251 unsigned char *buf;
2252
2253 if (buflen > 16)
2254 buflen = 16;
2255 buf = kzalloc(64, GFP_KERNEL);
2256 if (!buf)
2257 return -1;
b7bb24eb 2258 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
edd16368
SC		 2259 if (rc == 0)
2260 memcpy(device_id, &buf[8], buflen);
2261 kfree(buf);
2262 return rc != 0;
2263}
2264
2265static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2266 struct ReportLUNdata *buf, int bufsize,
2267 int extended_response)
2268{
2269 int rc = IO_OK;
2270 struct CommandList *c;
2271 unsigned char scsi3addr[8];
2272 struct ErrorInfo *ei;
2273
2274 c = cmd_special_alloc(h);
2275 if (c == NULL) { /* trouble... */
2276 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2277 return -1;
2278 }
e89c0ae7
SC		 2279 /* address the controller */
2280 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2281 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2282 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2283 rc = -1;
2284 goto out;
2285 }
edd16368
SC		 2286 if (extended_response)
2287 c->Request.CDB[1] = extended_response;
2288 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2289 ei = c->err_info;
2290 if (ei->CommandStatus != 0 &&
2291 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 2292 hpsa_scsi_interpret_error(h, c);
edd16368 2293 rc = -1;
283b4a9b
SC		 2294 } else {
2295 if (buf->extended_response_flag != extended_response) {
2296 dev_err(&h->pdev->dev,
2297 "report luns requested format %u, got %u\n",
2298 extended_response,
2299 buf->extended_response_flag);
2300 rc = -1;
2301 }
edd16368 2302 }
a2dac136 2303out:
edd16368
SC		 2304 cmd_special_free(h, c);
2305 return rc;
2306}
2307
2308static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2309 struct ReportLUNdata *buf,
2310 int bufsize, int extended_response)
2311{
2312 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2313}
2314
2315static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2316 struct ReportLUNdata *buf, int bufsize)
2317{
2318 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2319}
2320
2321static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2322 int bus, int target, int lun)
2323{
2324 device->bus = bus;
2325 device->target = target;
2326 device->lun = lun;
2327}
2328
2329static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2330 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2331 unsigned char *is_OBDR_device)
edd16368 2332{
0b0e1d6c
SC		 2333
2334#define OBDR_SIG_OFFSET 43
2335#define OBDR_TAPE_SIG "$DR-10"
2336#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2337#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2338
ea6d3bc3 2339 unsigned char *inq_buff;
0b0e1d6c 2340 unsigned char *obdr_sig;
edd16368 2341
ea6d3bc3 2342 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2343 if (!inq_buff)
2344 goto bail_out;
2345
edd16368
SC		 2346 /* Do an inquiry to the device to see what it is. */
2347 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2348 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2349 /* Inquiry failed (msg printed already) */
2350 dev_err(&h->pdev->dev,
2351 "hpsa_update_device_info: inquiry failed\n");
2352 goto bail_out;
2353 }
2354
edd16368
SC		 2355 this_device->devtype = (inq_buff[0] & 0x1f);
2356 memcpy(this_device->scsi3addr, scsi3addr, 8);
2357 memcpy(this_device->vendor, &inq_buff[8],
2358 sizeof(this_device->vendor));
2359 memcpy(this_device->model, &inq_buff[16],
2360 sizeof(this_device->model));
edd16368
SC		 2361 memset(this_device->device_id, 0,
2362 sizeof(this_device->device_id));
2363 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2364 sizeof(this_device->device_id));
2365
2366 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2367 is_logical_dev_addr_mode(scsi3addr)) {
edd16368 2368 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2369 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2370 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
2371 } else {
edd16368 2372 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2373 this_device->offload_config = 0;
2374 this_device->offload_enabled = 0;
2375 }
edd16368 2376
0b0e1d6c
SC		 2377 if (is_OBDR_device) {
2378 /* See if this is a One-Button-Disaster-Recovery device
2379 * by looking for "$DR-10" at offset 43 in inquiry data.
2380 */
2381 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2382 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2383 strncmp(obdr_sig, OBDR_TAPE_SIG,
2384 OBDR_SIG_LEN) == 0);
2385 }
2386
edd16368
SC		 2387 kfree(inq_buff);
2388 return 0;
2389
2390bail_out:
2391 kfree(inq_buff);
2392 return 1;
2393}
2394
4f4eb9f1 2395static unsigned char *ext_target_model[] = {
edd16368
SC		 2396 "MSA2012",
2397 "MSA2024",
2398 "MSA2312",
2399 "MSA2324",
fda38518 2400 "P2000 G3 SAS",
e06c8e5c 2401 "MSA 2040 SAS",
edd16368
SC		 2402 NULL,
2403};
2404
4f4eb9f1 2405static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2406{
2407 int i;
2408
4f4eb9f1
ST		 2409 for (i = 0; ext_target_model[i]; i++)
2410 if (strncmp(device->model, ext_target_model[i],
2411 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2412 return 1;
2413 return 0;
2414}
2415
2416/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2417 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2418 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2419 * Logical drive target and lun are assigned at this time, but
2420 * physical device lun and target assignment are deferred (assigned
2421 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2422 */
2423static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2424 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2425{
1f310bde
SC		 2426 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2427
2428 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2429 /* physical device, target and lun filled in later */
edd16368 2430 if (is_hba_lunid(lunaddrbytes))
1f310bde 2431 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2432 else
1f310bde
SC		 2433 /* defer target, lun assignment for physical devices */
2434 hpsa_set_bus_target_lun(device, 2, -1, -1);
2435 return;
2436 }
2437 /* It's a logical device */
4f4eb9f1
ST		 2438 if (is_ext_target(h, device)) {
2439 /* external target way, put logicals on bus 1
1f310bde
SC		 2440 * and match target/lun numbers box
2441 * reports, other smart array, bus 0, target 0, match lunid
2442 */
2443 hpsa_set_bus_target_lun(device,
2444 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2445 return;
edd16368 2446 }
1f310bde 2447 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2448}
2449
2450/*
2451 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2452 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2453 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2454 * it for some reason. *tmpdevice is the target we're adding,
2455 * this_device is a pointer into the current element of currentsd[]
2456 * that we're building up in update_scsi_devices(), below.
2457 * lunzerobits is a bitmap that tracks which targets already have a
2458 * lun 0 assigned.
2459 * Returns 1 if an enclosure was added, 0 if not.
2460 */
4f4eb9f1 2461static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2462 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2463 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2464 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2465{
2466 unsigned char scsi3addr[8];
2467
1f310bde 2468 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2469 return 0; /* There is already a lun 0 on this target. */
2470
2471 if (!is_logical_dev_addr_mode(lunaddrbytes))
2472 return 0; /* It's the logical targets that may lack lun 0. */
2473
4f4eb9f1
ST		 2474 if (!is_ext_target(h, tmpdevice))
2475 return 0; /* Only external target devices have this problem. */
edd16368 2476
1f310bde 2477 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2478 return 0;
2479
c4f8a299 2480 memset(scsi3addr, 0, 8);
1f310bde 2481 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2482 if (is_hba_lunid(scsi3addr))
2483 return 0; /* Don't add the RAID controller here. */
2484
339b2b14
SC		 2485 if (is_scsi_rev_5(h))
2486 return 0; /* p1210m doesn't need to do this. */
2487
4f4eb9f1 2488 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2489 dev_warn(&h->pdev->dev, "Maximum number of external "
2490 "target devices exceeded. Check your hardware "
edd16368
SC		 2491 "configuration.");
2492 return 0;
2493 }
2494
0b0e1d6c 2495 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2496 return 0;
4f4eb9f1 2497 (*n_ext_target_devs)++;
1f310bde
SC		 2498 hpsa_set_bus_target_lun(this_device,
2499 tmpdevice->bus, tmpdevice->target, 0);
2500 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2501 return 1;
2502}
2503
54b6e9e9
ST		 2504/*
2505 * Get address of physical disk used for an ioaccel2 mode command:
2506 * 1. Extract ioaccel2 handle from the command.
2507 * 2. Find a matching ioaccel2 handle from list of physical disks.
2508 * 3. Return:
2509 * 1 and set scsi3addr to address of matching physical
2510 * 0 if no matching physical disk was found.
2511 */
2512static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2513 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2514{
2515 struct ReportExtendedLUNdata *physicals = NULL;
2516 int responsesize = 24; /* size of physical extended response */
2517 int extended = 2; /* flag forces reporting 'other dev info'. */
2518 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2519 u32 nphysicals = 0; /* number of reported physical devs */
2520 int found = 0; /* found match (1) or not (0) */
2521 u32 find; /* handle we need to match */
2522 int i;
2523 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2524 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2525 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2526 u32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2527 u32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2528
2529 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2530 return 0; /* no match */
2531
2532 /* point to the ioaccel2 device handle */
2533 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2534 if (c2a == NULL)
2535 return 0; /* no match */
2536
2537 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2538 if (scmd == NULL)
2539 return 0; /* no match */
2540
2541 d = scmd->device->hostdata;
2542 if (d == NULL)
2543 return 0; /* no match */
2544
2545 it_nexus = cpu_to_le32((u32) d->ioaccel_handle);
2546 scsi_nexus = cpu_to_le32((u32) c2a->scsi_nexus);
2547 find = c2a->scsi_nexus;
2548
2ba8bfc8
SC		 2549 if (h->raid_offload_debug > 0)
2550 dev_info(&h->pdev->dev,
2551 "%s: scsi_nexus:0x%08x device id: 0x%02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n",
2552 __func__, scsi_nexus,
2553 d->device_id[0], d->device_id[1], d->device_id[2],
2554 d->device_id[3], d->device_id[4], d->device_id[5],
2555 d->device_id[6], d->device_id[7], d->device_id[8],
2556 d->device_id[9], d->device_id[10], d->device_id[11],
2557 d->device_id[12], d->device_id[13], d->device_id[14],
2558 d->device_id[15]);
2559
54b6e9e9
ST		 2560 /* Get the list of physical devices */
2561 physicals = kzalloc(reportsize, GFP_KERNEL);
2562 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2563 reportsize, extended)) {
2564 dev_err(&h->pdev->dev,
2565 "Can't lookup %s device handle: report physical LUNs failed.\n",
2566 "HP SSD Smart Path");
2567 kfree(physicals);
2568 return 0;
2569 }
2570 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2571 responsesize;
2572
2573
2574 /* find ioaccel2 handle in list of physicals: */
2575 for (i = 0; i < nphysicals; i++) {
2576 /* handle is in bytes 28-31 of each lun */
2577 if (memcmp(&((struct ReportExtendedLUNdata *)
2578 physicals)->LUN[i][20], &find, 4) != 0) {
2579 continue; /* didn't match */
2580 }
2581 found = 1;
2582 memcpy(scsi3addr, &((struct ReportExtendedLUNdata *)
2583 physicals)->LUN[i][0], 8);
2ba8bfc8
SC		 2584 if (h->raid_offload_debug > 0)
2585 dev_info(&h->pdev->dev,
2586 "%s: Searched h=0x%08x, Found h=0x%08x, scsiaddr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
2587 __func__, find,
2588 ((struct ReportExtendedLUNdata *)
2589 physicals)->LUN[i][20],
2590 scsi3addr[0], scsi3addr[1], scsi3addr[2],
2591 scsi3addr[3], scsi3addr[4], scsi3addr[5],
2592 scsi3addr[6], scsi3addr[7]);
54b6e9e9
ST		 2593 break; /* found it */
2594 }
2595
2596 kfree(physicals);
2597 if (found)
2598 return 1;
2599 else
2600 return 0;
2601
2602}
edd16368
SC		 2603/*
2604 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2605 * logdev. The number of luns in physdev and logdev are returned in
2606 * *nphysicals and *nlogicals, respectively.
2607 * Returns 0 on success, -1 otherwise.
2608 */
2609static int hpsa_gather_lun_info(struct ctlr_info *h,
2610 int reportlunsize,
283b4a9b 2611 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2612 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2613{
283b4a9b
SC		 2614 int physical_entry_size = 8;
2615
2616 *physical_mode = 0;
2617
2618 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2619 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2620 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2621 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2622 physical_entry_size = 24;
2623 }
a93aa1fe 2624 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize,
283b4a9b 2625 *physical_mode)) {
edd16368
SC		 2626 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2627 return -1;
2628 }
283b4a9b
SC		 2629 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2630 physical_entry_size;
edd16368
SC		 2631 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2632 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2633 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2634 *nphysicals - HPSA_MAX_PHYS_LUN);
2635 *nphysicals = HPSA_MAX_PHYS_LUN;
2636 }
2637 if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
2638 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2639 return -1;
2640 }
6df1e954 2641 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2642 /* Reject Logicals in excess of our max capability. */
2643 if (*nlogicals > HPSA_MAX_LUN) {
2644 dev_warn(&h->pdev->dev,
2645 "maximum logical LUNs (%d) exceeded. "
2646 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2647 *nlogicals - HPSA_MAX_LUN);
2648 *nlogicals = HPSA_MAX_LUN;
2649 }
2650 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2651 dev_warn(&h->pdev->dev,
2652 "maximum logical + physical LUNs (%d) exceeded. "
2653 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2654 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2655 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2656 }
2657 return 0;
2658}
2659
339b2b14 2660u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
a93aa1fe
MG		 2661 int nphysicals, int nlogicals,
2662 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2663 struct ReportLUNdata *logdev_list)
2664{
2665 /* Helper function, figure out where the LUN ID info is coming from
2666 * given index i, lists of physical and logical devices, where in
2667 * the list the raid controller is supposed to appear (first or last)
2668 */
2669
2670 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2671 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2672
2673 if (i == raid_ctlr_position)
2674 return RAID_CTLR_LUNID;
2675
2676 if (i < logicals_start)
2677 return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
2678
2679 if (i < last_device)
2680 return &logdev_list->LUN[i - nphysicals -
2681 (raid_ctlr_position == 0)][0];
2682 BUG();
2683 return NULL;
2684}
2685
edd16368
SC		 2686static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2687{
2688 /* the idea here is we could get notified
2689 * that some devices have changed, so we do a report
2690 * physical luns and report logical luns cmd, and adjust
2691 * our list of devices accordingly.
2692 *
2693 * The scsi3addr's of devices won't change so long as the
2694 * adapter is not reset. That means we can rescan and
2695 * tell which devices we already know about, vs. new
2696 * devices, vs. disappearing devices.
2697 */
a93aa1fe 2698 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2699 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2700 u32 nphysicals = 0;
2701 u32 nlogicals = 0;
283b4a9b 2702 int physical_mode = 0;
01a02ffc 2703 u32 ndev_allocated = 0;
edd16368
SC		 2704 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
2705 int ncurrent = 0;
283b4a9b 2706 int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24;
4f4eb9f1 2707 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 2708 int raid_ctlr_position;
aca4a520 2709 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 2710
cfe5badc 2711 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 2712 physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
2713 logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
edd16368
SC		 2714 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
2715
0b0e1d6c 2716 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 2717 dev_err(&h->pdev->dev, "out of memory\n");
2718 goto out;
2719 }
2720 memset(lunzerobits, 0, sizeof(lunzerobits));
2721
a93aa1fe
MG		 2722 if (hpsa_gather_lun_info(h, reportlunsize,
2723 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 2724 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 2725 goto out;
2726
aca4a520
ST		 2727 /* We might see up to the maximum number of logical and physical disks
2728 * plus external target devices, and a device for the local RAID
2729 * controller.
edd16368 2730 */
aca4a520 2731 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 2732
2733 /* Allocate the per device structures */
2734 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 2735 if (i >= HPSA_MAX_DEVICES) {
2736 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
2737 " %d devices ignored.\n", HPSA_MAX_DEVICES,
2738 ndevs_to_allocate - HPSA_MAX_DEVICES);
2739 break;
2740 }
2741
edd16368
SC		 2742 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
2743 if (!currentsd[i]) {
2744 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
2745 __FILE__, __LINE__);
2746 goto out;
2747 }
2748 ndev_allocated++;
2749 }
2750
339b2b14
SC		 2751 if (unlikely(is_scsi_rev_5(h)))
2752 raid_ctlr_position = 0;
2753 else
2754 raid_ctlr_position = nphysicals + nlogicals;
2755
edd16368 2756 /* adjust our table of devices */
4f4eb9f1 2757 n_ext_target_devs = 0;
edd16368 2758 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 2759 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 2760
2761 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 2762 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
2763 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 2764 /* skip masked physical devices. */
339b2b14
SC		 2765 if (lunaddrbytes[3] & 0xC0 &&
2766 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 2767 continue;
2768
2769 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 2770 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
2771 &is_OBDR))
edd16368 2772 continue; /* skip it if we can't talk to it. */
1f310bde 2773 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 2774 this_device = currentsd[ncurrent];
2775
2776 /*
4f4eb9f1 2777 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 2778 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
2779 * is nonetheless an enclosure device there. We have to
2780 * present that otherwise linux won't find anything if
2781 * there is no lun 0.
2782 */
4f4eb9f1 2783 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 2784 lunaddrbytes, lunzerobits,
4f4eb9f1 2785 &n_ext_target_devs)) {
edd16368
SC		 2786 ncurrent++;
2787 this_device = currentsd[ncurrent];
2788 }
2789
2790 *this_device = *tmpdevice;
edd16368
SC		 2791
2792 switch (this_device->devtype) {
0b0e1d6c 2793 case TYPE_ROM:
edd16368
SC		 2794 /* We don't *really* support actual CD-ROM devices,
2795 * just "One Button Disaster Recovery" tape drive
2796 * which temporarily pretends to be a CD-ROM drive.
2797 * So we check that the device is really an OBDR tape
2798 * device by checking for "$DR-10" in bytes 43-48 of
2799 * the inquiry data.
2800 */
0b0e1d6c
SC		 2801 if (is_OBDR)
2802 ncurrent++;
edd16368
SC		 2803 break;
2804 case TYPE_DISK:
283b4a9b
SC		 2805 if (i >= nphysicals) {
2806 ncurrent++;
edd16368 2807 break;
283b4a9b
SC		 2808 }
2809 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
2810 memcpy(&this_device->ioaccel_handle,
2811 &lunaddrbytes[20],
2812 sizeof(this_device->ioaccel_handle));
2813 ncurrent++;
2814 }
edd16368
SC		 2815 break;
2816 case TYPE_TAPE:
2817 case TYPE_MEDIUM_CHANGER:
2818 ncurrent++;
2819 break;
2820 case TYPE_RAID:
2821 /* Only present the Smartarray HBA as a RAID controller.
2822 * If it's a RAID controller other than the HBA itself
2823 * (an external RAID controller, MSA500 or similar)
2824 * don't present it.
2825 */
2826 if (!is_hba_lunid(lunaddrbytes))
2827 break;
2828 ncurrent++;
2829 break;
2830 default:
2831 break;
2832 }
cfe5badc 2833 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 2834 break;
2835 }
2836 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
2837out:
2838 kfree(tmpdevice);
2839 for (i = 0; i < ndev_allocated; i++)
2840 kfree(currentsd[i]);
2841 kfree(currentsd);
edd16368
SC		 2842 kfree(physdev_list);
2843 kfree(logdev_list);
edd16368
SC		 2844}
2845
2846/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
2847 * dma mapping and fills in the scatter gather entries of the
2848 * hpsa command, cp.
2849 */
33a2ffce 2850static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 2851 struct CommandList *cp,
2852 struct scsi_cmnd *cmd)
2853{
2854 unsigned int len;
2855 struct scatterlist *sg;
01a02ffc 2856 u64 addr64;
33a2ffce
SC		 2857 int use_sg, i, sg_index, chained;
2858 struct SGDescriptor *curr_sg;
edd16368 2859
33a2ffce 2860 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 2861
2862 use_sg = scsi_dma_map(cmd);
2863 if (use_sg < 0)
2864 return use_sg;
2865
2866 if (!use_sg)
2867 goto sglist_finished;
2868
33a2ffce
SC		 2869 curr_sg = cp->SG;
2870 chained = 0;
2871 sg_index = 0;
edd16368 2872 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 2873 if (i == h->max_cmd_sg_entries - 1 &&
2874 use_sg > h->max_cmd_sg_entries) {
2875 chained = 1;
2876 curr_sg = h->cmd_sg_list[cp->cmdindex];
2877 sg_index = 0;
2878 }
01a02ffc 2879 addr64 = (u64) sg_dma_address(sg);
edd16368 2880 len = sg_dma_len(sg);
33a2ffce
SC		 2881 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2882 curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2883 curr_sg->Len = len;
e1d9cbfa 2884 curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST;
33a2ffce
SC		 2885 curr_sg++;
2886 }
2887
2888 if (use_sg + chained > h->maxSG)
2889 h->maxSG = use_sg + chained;
2890
2891 if (chained) {
2892 cp->Header.SGList = h->max_cmd_sg_entries;
2893 cp->Header.SGTotal = (u16) (use_sg + 1);
e2bea6df
SC		 2894 if (hpsa_map_sg_chain_block(h, cp)) {
2895 scsi_dma_unmap(cmd);
2896 return -1;
2897 }
33a2ffce 2898 return 0;
edd16368
SC		 2899 }
2900
2901sglist_finished:
2902
01a02ffc
SC		 2903 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
2904 cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
edd16368
SC		 2905 return 0;
2906}
2907
283b4a9b
SC		 2908#define IO_ACCEL_INELIGIBLE (1)
2909static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
2910{
2911 int is_write = 0;
2912 u32 block;
2913 u32 block_cnt;
2914
2915 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
2916 switch (cdb[0]) {
2917 case WRITE_6:
2918 case WRITE_12:
2919 is_write = 1;
2920 case READ_6:
2921 case READ_12:
2922 if (*cdb_len == 6) {
2923 block = (((u32) cdb[2]) << 8) | cdb[3];
2924 block_cnt = cdb[4];
2925 } else {
2926 BUG_ON(*cdb_len != 12);
2927 block = (((u32) cdb[2]) << 24) |
2928 (((u32) cdb[3]) << 16) |
2929 (((u32) cdb[4]) << 8) |
2930 cdb[5];
2931 block_cnt =
2932 (((u32) cdb[6]) << 24) |
2933 (((u32) cdb[7]) << 16) |
2934 (((u32) cdb[8]) << 8) |
2935 cdb[9];
2936 }
2937 if (block_cnt > 0xffff)
2938 return IO_ACCEL_INELIGIBLE;
2939
2940 cdb[0] = is_write ? WRITE_10 : READ_10;
2941 cdb[1] = 0;
2942 cdb[2] = (u8) (block >> 24);
2943 cdb[3] = (u8) (block >> 16);
2944 cdb[4] = (u8) (block >> 8);
2945 cdb[5] = (u8) (block);
2946 cdb[6] = 0;
2947 cdb[7] = (u8) (block_cnt >> 8);
2948 cdb[8] = (u8) (block_cnt);
2949 cdb[9] = 0;
2950 *cdb_len = 10;
2951 break;
2952 }
2953 return 0;
2954}
2955
c349775e 2956static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 2957 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2958 u8 *scsi3addr)
e1f7de0c
MG		 2959{
2960 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 2961 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
2962 unsigned int len;
2963 unsigned int total_len = 0;
2964 struct scatterlist *sg;
2965 u64 addr64;
2966 int use_sg, i;
2967 struct SGDescriptor *curr_sg;
2968 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
2969
283b4a9b
SC		 2970 /* TODO: implement chaining support */
2971 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
2972 return IO_ACCEL_INELIGIBLE;
2973
e1f7de0c
MG		 2974 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
2975
283b4a9b
SC		 2976 if (fixup_ioaccel_cdb(cdb, &cdb_len))
2977 return IO_ACCEL_INELIGIBLE;
2978
e1f7de0c
MG		 2979 c->cmd_type = CMD_IOACCEL1;
2980
2981 /* Adjust the DMA address to point to the accelerated command buffer */
2982 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
2983 (c->cmdindex * sizeof(*cp));
2984 BUG_ON(c->busaddr & 0x0000007F);
2985
2986 use_sg = scsi_dma_map(cmd);
2987 if (use_sg < 0)
2988 return use_sg;
2989
2990 if (use_sg) {
2991 curr_sg = cp->SG;
2992 scsi_for_each_sg(cmd, sg, use_sg, i) {
2993 addr64 = (u64) sg_dma_address(sg);
2994 len = sg_dma_len(sg);
2995 total_len += len;
2996 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2997 curr_sg->Addr.upper =
2998 (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2999 curr_sg->Len = len;
3000
3001 if (i == (scsi_sg_count(cmd) - 1))
3002 curr_sg->Ext = HPSA_SG_LAST;
3003 else
3004 curr_sg->Ext = 0; /* we are not chaining */
3005 curr_sg++;
3006 }
3007
3008 switch (cmd->sc_data_direction) {
3009 case DMA_TO_DEVICE:
3010 control |= IOACCEL1_CONTROL_DATA_OUT;
3011 break;
3012 case DMA_FROM_DEVICE:
3013 control |= IOACCEL1_CONTROL_DATA_IN;
3014 break;
3015 case DMA_NONE:
3016 control |= IOACCEL1_CONTROL_NODATAXFER;
3017 break;
3018 default:
3019 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3020 cmd->sc_data_direction);
3021 BUG();
3022 break;
3023 }
3024 } else {
3025 control |= IOACCEL1_CONTROL_NODATAXFER;
3026 }
3027
c349775e 3028 c->Header.SGList = use_sg;
e1f7de0c 3029 /* Fill out the command structure to submit */
283b4a9b 3030 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 3031 cp->transfer_len = total_len;
3032 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 3033 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 3034 cp->control = control;
283b4a9b
SC		 3035 memcpy(cp->CDB, cdb, cdb_len);
3036 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 3037 /* Tag was already set at init time. */
283b4a9b 3038 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 3039 return 0;
3040}
edd16368 3041
283b4a9b
SC		 3042/*
3043 * Queue a command directly to a device behind the controller using the
3044 * I/O accelerator path.
3045 */
3046static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
3047 struct CommandList *c)
3048{
3049 struct scsi_cmnd *cmd = c->scsi_cmd;
3050 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3051
3052 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
3053 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
3054}
3055
dd0e19f3
ST		 3056/*
3057 * Set encryption parameters for the ioaccel2 request
3058 */
3059static void set_encrypt_ioaccel2(struct ctlr_info *h,
3060 struct CommandList *c, struct io_accel2_cmd *cp)
3061{
3062 struct scsi_cmnd *cmd = c->scsi_cmd;
3063 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3064 struct raid_map_data *map = &dev->raid_map;
3065 u64 first_block;
3066
3067 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3068
3069 /* Are we doing encryption on this device */
3070 if (!(map->flags & RAID_MAP_FLAG_ENCRYPT_ON))
3071 return;
3072 /* Set the data encryption key index. */
3073 cp->dekindex = map->dekindex;
3074
3075 /* Set the encryption enable flag, encoded into direction field. */
3076 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
3077
3078 /* Set encryption tweak values based on logical block address
3079 * If block size is 512, tweak value is LBA.
3080 * For other block sizes, tweak is (LBA * block size)/ 512)
3081 */
3082 switch (cmd->cmnd[0]) {
3083 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
3084 case WRITE_6:
3085 case READ_6:
3086 if (map->volume_blk_size == 512) {
3087 cp->tweak_lower =
3088 (((u32) cmd->cmnd[2]) << 8) |
3089 cmd->cmnd[3];
3090 cp->tweak_upper = 0;
3091 } else {
3092 first_block =
3093 (((u64) cmd->cmnd[2]) << 8) |
3094 cmd->cmnd[3];
3095 first_block = (first_block * map->volume_blk_size)/512;
3096 cp->tweak_lower = (u32)first_block;
3097 cp->tweak_upper = (u32)(first_block >> 32);
3098 }
3099 break;
3100 case WRITE_10:
3101 case READ_10:
3102 if (map->volume_blk_size == 512) {
3103 cp->tweak_lower =
3104 (((u32) cmd->cmnd[2]) << 24) |
3105 (((u32) cmd->cmnd[3]) << 16) |
3106 (((u32) cmd->cmnd[4]) << 8) |
3107 cmd->cmnd[5];
3108 cp->tweak_upper = 0;
3109 } else {
3110 first_block =
3111 (((u64) cmd->cmnd[2]) << 24) |
3112 (((u64) cmd->cmnd[3]) << 16) |
3113 (((u64) cmd->cmnd[4]) << 8) |
3114 cmd->cmnd[5];
3115 first_block = (first_block * map->volume_blk_size)/512;
3116 cp->tweak_lower = (u32)first_block;
3117 cp->tweak_upper = (u32)(first_block >> 32);
3118 }
3119 break;
3120 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
3121 case WRITE_12:
3122 case READ_12:
3123 if (map->volume_blk_size == 512) {
3124 cp->tweak_lower =
3125 (((u32) cmd->cmnd[2]) << 24) |
3126 (((u32) cmd->cmnd[3]) << 16) |
3127 (((u32) cmd->cmnd[4]) << 8) |
3128 cmd->cmnd[5];
3129 cp->tweak_upper = 0;
3130 } else {
3131 first_block =
3132 (((u64) cmd->cmnd[2]) << 24) |
3133 (((u64) cmd->cmnd[3]) << 16) |
3134 (((u64) cmd->cmnd[4]) << 8) |
3135 cmd->cmnd[5];
3136 first_block = (first_block * map->volume_blk_size)/512;
3137 cp->tweak_lower = (u32)first_block;
3138 cp->tweak_upper = (u32)(first_block >> 32);
3139 }
3140 break;
3141 case WRITE_16:
3142 case READ_16:
3143 if (map->volume_blk_size == 512) {
3144 cp->tweak_lower =
3145 (((u32) cmd->cmnd[6]) << 24) |
3146 (((u32) cmd->cmnd[7]) << 16) |
3147 (((u32) cmd->cmnd[8]) << 8) |
3148 cmd->cmnd[9];
3149 cp->tweak_upper =
3150 (((u32) cmd->cmnd[2]) << 24) |
3151 (((u32) cmd->cmnd[3]) << 16) |
3152 (((u32) cmd->cmnd[4]) << 8) |
3153 cmd->cmnd[5];
3154 } else {
3155 first_block =
3156 (((u64) cmd->cmnd[2]) << 56) |
3157 (((u64) cmd->cmnd[3]) << 48) |
3158 (((u64) cmd->cmnd[4]) << 40) |
3159 (((u64) cmd->cmnd[5]) << 32) |
3160 (((u64) cmd->cmnd[6]) << 24) |
3161 (((u64) cmd->cmnd[7]) << 16) |
3162 (((u64) cmd->cmnd[8]) << 8) |
3163 cmd->cmnd[9];
3164 first_block = (first_block * map->volume_blk_size)/512;
3165 cp->tweak_lower = (u32)first_block;
3166 cp->tweak_upper = (u32)(first_block >> 32);
3167 }
3168 break;
3169 default:
3170 dev_err(&h->pdev->dev,
3171 "ERROR: %s: IOACCEL request CDB size not supported for encryption\n",
3172 __func__);
3173 BUG();
3174 break;
3175 }
3176}
3177
c349775e
ST		 3178static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
3179 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3180 u8 *scsi3addr)
3181{
3182 struct scsi_cmnd *cmd = c->scsi_cmd;
3183 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
3184 struct ioaccel2_sg_element *curr_sg;
3185 int use_sg, i;
3186 struct scatterlist *sg;
3187 u64 addr64;
3188 u32 len;
3189 u32 total_len = 0;
3190
3191 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
3192 return IO_ACCEL_INELIGIBLE;
3193
3194 if (fixup_ioaccel_cdb(cdb, &cdb_len))
3195 return IO_ACCEL_INELIGIBLE;
3196 c->cmd_type = CMD_IOACCEL2;
3197 /* Adjust the DMA address to point to the accelerated command buffer */
3198 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
3199 (c->cmdindex * sizeof(*cp));
3200 BUG_ON(c->busaddr & 0x0000007F);
3201
3202 memset(cp, 0, sizeof(*cp));
3203 cp->IU_type = IOACCEL2_IU_TYPE;
3204
3205 use_sg = scsi_dma_map(cmd);
3206 if (use_sg < 0)
3207 return use_sg;
3208
3209 if (use_sg) {
3210 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
3211 curr_sg = cp->sg;
3212 scsi_for_each_sg(cmd, sg, use_sg, i) {
3213 addr64 = (u64) sg_dma_address(sg);
3214 len = sg_dma_len(sg);
3215 total_len += len;
3216 curr_sg->address = cpu_to_le64(addr64);
3217 curr_sg->length = cpu_to_le32(len);
3218 curr_sg->reserved[0] = 0;
3219 curr_sg->reserved[1] = 0;
3220 curr_sg->reserved[2] = 0;
3221 curr_sg->chain_indicator = 0;
3222 curr_sg++;
3223 }
3224
3225 switch (cmd->sc_data_direction) {
3226 case DMA_TO_DEVICE:
dd0e19f3
ST		 3227 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3228 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 3229 break;
3230 case DMA_FROM_DEVICE:
dd0e19f3
ST		 3231 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3232 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 3233 break;
3234 case DMA_NONE:
dd0e19f3
ST		 3235 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3236 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 3237 break;
3238 default:
3239 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3240 cmd->sc_data_direction);
3241 BUG();
3242 break;
3243 }
3244 } else {
dd0e19f3
ST		 3245 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
3246 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 3247 }
dd0e19f3
ST		 3248
3249 /* Set encryption parameters, if necessary */
3250 set_encrypt_ioaccel2(h, c, cp);
3251
c349775e 3252 cp->scsi_nexus = ioaccel_handle;
dd0e19f3 3253 cp->Tag = (c->cmdindex << DIRECT_LOOKUP_SHIFT) |
c349775e
ST		 3254 DIRECT_LOOKUP_BIT;
3255 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
3256 memset(cp->cciss_lun, 0, sizeof(cp->cciss_lun));
3257 cp->cmd_priority_task_attr = 0;
3258
3259 /* fill in sg elements */
3260 cp->sg_count = (u8) use_sg;
3261
3262 cp->data_len = cpu_to_le32(total_len);
3263 cp->err_ptr = cpu_to_le64(c->busaddr +
3264 offsetof(struct io_accel2_cmd, error_data));
3265 cp->err_len = cpu_to_le32((u32) sizeof(cp->error_data));
3266
3267 enqueue_cmd_and_start_io(h, c);
3268 return 0;
3269}
3270
3271/*
3272 * Queue a command to the correct I/O accelerator path.
3273 */
3274static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
3275 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
3276 u8 *scsi3addr)
3277{
3278 if (h->transMethod & CFGTBL_Trans_io_accel1)
3279 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
3280 cdb, cdb_len, scsi3addr);
3281 else
3282 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
3283 cdb, cdb_len, scsi3addr);
3284}
3285
6b80b18f
ST		 3286static void raid_map_helper(struct raid_map_data *map,
3287 int offload_to_mirror, u32 *map_index, u32 *current_group)
3288{
3289 if (offload_to_mirror == 0) {
3290 /* use physical disk in the first mirrored group. */
3291 *map_index %= map->data_disks_per_row;
3292 return;
3293 }
3294 do {
3295 /* determine mirror group that *map_index indicates */
3296 *current_group = *map_index / map->data_disks_per_row;
3297 if (offload_to_mirror == *current_group)
3298 continue;
3299 if (*current_group < (map->layout_map_count - 1)) {
3300 /* select map index from next group */
3301 *map_index += map->data_disks_per_row;
3302 (*current_group)++;
3303 } else {
3304 /* select map index from first group */
3305 *map_index %= map->data_disks_per_row;
3306 *current_group = 0;
3307 }
3308 } while (offload_to_mirror != *current_group);
3309}
3310
283b4a9b
SC		 3311/*
3312 * Attempt to perform offload RAID mapping for a logical volume I/O.
3313 */
3314static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
3315 struct CommandList *c)
3316{
3317 struct scsi_cmnd *cmd = c->scsi_cmd;
3318 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
3319 struct raid_map_data *map = &dev->raid_map;
3320 struct raid_map_disk_data *dd = &map->data[0];
3321 int is_write = 0;
3322 u32 map_index;
3323 u64 first_block, last_block;
3324 u32 block_cnt;
3325 u32 blocks_per_row;
3326 u64 first_row, last_row;
3327 u32 first_row_offset, last_row_offset;
3328 u32 first_column, last_column;
6b80b18f
ST		 3329 u64 r0_first_row, r0_last_row;
3330 u32 r5or6_blocks_per_row;
3331 u64 r5or6_first_row, r5or6_last_row;
3332 u32 r5or6_first_row_offset, r5or6_last_row_offset;
3333 u32 r5or6_first_column, r5or6_last_column;
3334 u32 total_disks_per_row;
3335 u32 stripesize;
3336 u32 first_group, last_group, current_group;
283b4a9b
SC		 3337 u32 map_row;
3338 u32 disk_handle;
3339 u64 disk_block;
3340 u32 disk_block_cnt;
3341 u8 cdb[16];
3342 u8 cdb_len;
3343#if BITS_PER_LONG == 32
3344 u64 tmpdiv;
3345#endif
6b80b18f 3346 int offload_to_mirror;
283b4a9b
SC		 3347
3348 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3349
3350 /* check for valid opcode, get LBA and block count */
3351 switch (cmd->cmnd[0]) {
3352 case WRITE_6:
3353 is_write = 1;
3354 case READ_6:
3355 first_block =
3356 (((u64) cmd->cmnd[2]) << 8) |
3357 cmd->cmnd[3];
3358 block_cnt = cmd->cmnd[4];
3359 break;
3360 case WRITE_10:
3361 is_write = 1;
3362 case READ_10:
3363 first_block =
3364 (((u64) cmd->cmnd[2]) << 24) |
3365 (((u64) cmd->cmnd[3]) << 16) |
3366 (((u64) cmd->cmnd[4]) << 8) |
3367 cmd->cmnd[5];
3368 block_cnt =
3369 (((u32) cmd->cmnd[7]) << 8) |
3370 cmd->cmnd[8];
3371 break;
3372 case WRITE_12:
3373 is_write = 1;
3374 case READ_12:
3375 first_block =
3376 (((u64) cmd->cmnd[2]) << 24) |
3377 (((u64) cmd->cmnd[3]) << 16) |
3378 (((u64) cmd->cmnd[4]) << 8) |
3379 cmd->cmnd[5];
3380 block_cnt =
3381 (((u32) cmd->cmnd[6]) << 24) |
3382 (((u32) cmd->cmnd[7]) << 16) |
3383 (((u32) cmd->cmnd[8]) << 8) |
3384 cmd->cmnd[9];
3385 break;
3386 case WRITE_16:
3387 is_write = 1;
3388 case READ_16:
3389 first_block =
3390 (((u64) cmd->cmnd[2]) << 56) |
3391 (((u64) cmd->cmnd[3]) << 48) |
3392 (((u64) cmd->cmnd[4]) << 40) |
3393 (((u64) cmd->cmnd[5]) << 32) |
3394 (((u64) cmd->cmnd[6]) << 24) |
3395 (((u64) cmd->cmnd[7]) << 16) |
3396 (((u64) cmd->cmnd[8]) << 8) |
3397 cmd->cmnd[9];
3398 block_cnt =
3399 (((u32) cmd->cmnd[10]) << 24) |
3400 (((u32) cmd->cmnd[11]) << 16) |
3401 (((u32) cmd->cmnd[12]) << 8) |
3402 cmd->cmnd[13];
3403 break;
3404 default:
3405 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3406 }
3407 BUG_ON(block_cnt == 0);
3408 last_block = first_block + block_cnt - 1;
3409
3410 /* check for write to non-RAID-0 */
3411 if (is_write && dev->raid_level != 0)
3412 return IO_ACCEL_INELIGIBLE;
3413
3414 /* check for invalid block or wraparound */
3415 if (last_block >= map->volume_blk_cnt || last_block < first_block)
3416 return IO_ACCEL_INELIGIBLE;
3417
3418 /* calculate stripe information for the request */
3419 blocks_per_row = map->data_disks_per_row * map->strip_size;
3420#if BITS_PER_LONG == 32
3421 tmpdiv = first_block;
3422 (void) do_div(tmpdiv, blocks_per_row);
3423 first_row = tmpdiv;
3424 tmpdiv = last_block;
3425 (void) do_div(tmpdiv, blocks_per_row);
3426 last_row = tmpdiv;
3427 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3428 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3429 tmpdiv = first_row_offset;
3430 (void) do_div(tmpdiv, map->strip_size);
3431 first_column = tmpdiv;
3432 tmpdiv = last_row_offset;
3433 (void) do_div(tmpdiv, map->strip_size);
3434 last_column = tmpdiv;
3435#else
3436 first_row = first_block / blocks_per_row;
3437 last_row = last_block / blocks_per_row;
3438 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3439 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3440 first_column = first_row_offset / map->strip_size;
3441 last_column = last_row_offset / map->strip_size;
3442#endif
3443
3444 /* if this isn't a single row/column then give to the controller */
3445 if ((first_row != last_row) || (first_column != last_column))
3446 return IO_ACCEL_INELIGIBLE;
3447
3448 /* proceeding with driver mapping */
6b80b18f
ST		 3449 total_disks_per_row = map->data_disks_per_row +
3450 map->metadata_disks_per_row;
283b4a9b
SC		 3451 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3452 map->row_cnt;
6b80b18f
ST		 3453 map_index = (map_row * total_disks_per_row) + first_column;
3454
3455 switch (dev->raid_level) {
3456 case HPSA_RAID_0:
3457 break; /* nothing special to do */
3458 case HPSA_RAID_1:
3459 /* Handles load balance across RAID 1 members.
3460 * (2-drive R1 and R10 with even # of drives.)
3461 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3462 */
6b80b18f 3463 BUG_ON(map->layout_map_count != 2);
283b4a9b
SC		 3464 if (dev->offload_to_mirror)
3465 map_index += map->data_disks_per_row;
3466 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3467 break;
3468 case HPSA_RAID_ADM:
3469 /* Handles N-way mirrors (R1-ADM)
3470 * and R10 with # of drives divisible by 3.)
3471 */
3472 BUG_ON(map->layout_map_count != 3);
3473
3474 offload_to_mirror = dev->offload_to_mirror;
3475 raid_map_helper(map, offload_to_mirror,
3476 &map_index, &current_group);
3477 /* set mirror group to use next time */
3478 offload_to_mirror =
3479 (offload_to_mirror >= map->layout_map_count - 1)
3480 ? 0 : offload_to_mirror + 1;
3481 /* FIXME: remove after debug/dev */
3482 BUG_ON(offload_to_mirror >= map->layout_map_count);
3483 dev_warn(&h->pdev->dev,
3484 "DEBUG: Using physical disk map index %d from mirror group %d\n",
3485 map_index, offload_to_mirror);
3486 dev->offload_to_mirror = offload_to_mirror;
3487 /* Avoid direct use of dev->offload_to_mirror within this
3488 * function since multiple threads might simultaneously
3489 * increment it beyond the range of dev->layout_map_count -1.
3490 */
3491 break;
3492 case HPSA_RAID_5:
3493 case HPSA_RAID_6:
3494 if (map->layout_map_count <= 1)
3495 break;
3496
3497 /* Verify first and last block are in same RAID group */
3498 r5or6_blocks_per_row =
3499 map->strip_size * map->data_disks_per_row;
3500 BUG_ON(r5or6_blocks_per_row == 0);
3501 stripesize = r5or6_blocks_per_row * map->layout_map_count;
3502#if BITS_PER_LONG == 32
3503 tmpdiv = first_block;
3504 first_group = do_div(tmpdiv, stripesize);
3505 tmpdiv = first_group;
3506 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3507 first_group = tmpdiv;
3508 tmpdiv = last_block;
3509 last_group = do_div(tmpdiv, stripesize);
3510 tmpdiv = last_group;
3511 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3512 last_group = tmpdiv;
3513#else
3514 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3515 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
3516 if (first_group != last_group)
3517#endif
3518 return IO_ACCEL_INELIGIBLE;
3519
3520 /* Verify request is in a single row of RAID 5/6 */
3521#if BITS_PER_LONG == 32
3522 tmpdiv = first_block;
3523 (void) do_div(tmpdiv, stripesize);
3524 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3525 tmpdiv = last_block;
3526 (void) do_div(tmpdiv, stripesize);
3527 r5or6_last_row = r0_last_row = tmpdiv;
3528#else
3529 first_row = r5or6_first_row = r0_first_row =
3530 first_block / stripesize;
3531 r5or6_last_row = r0_last_row = last_block / stripesize;
3532#endif
3533 if (r5or6_first_row != r5or6_last_row)
3534 return IO_ACCEL_INELIGIBLE;
3535
3536
3537 /* Verify request is in a single column */
3538#if BITS_PER_LONG == 32
3539 tmpdiv = first_block;
3540 first_row_offset = do_div(tmpdiv, stripesize);
3541 tmpdiv = first_row_offset;
3542 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3543 r5or6_first_row_offset = first_row_offset;
3544 tmpdiv = last_block;
3545 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3546 tmpdiv = r5or6_last_row_offset;
3547 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3548 tmpdiv = r5or6_first_row_offset;
3549 (void) do_div(tmpdiv, map->strip_size);
3550 first_column = r5or6_first_column = tmpdiv;
3551 tmpdiv = r5or6_last_row_offset;
3552 (void) do_div(tmpdiv, map->strip_size);
3553 r5or6_last_column = tmpdiv;
3554#else
3555 first_row_offset = r5or6_first_row_offset =
3556 (u32)((first_block % stripesize) %
3557 r5or6_blocks_per_row);
3558
3559 r5or6_last_row_offset =
3560 (u32)((last_block % stripesize) %
3561 r5or6_blocks_per_row);
3562
3563 first_column = r5or6_first_column =
3564 r5or6_first_row_offset / map->strip_size;
3565 r5or6_last_column =
3566 r5or6_last_row_offset / map->strip_size;
3567#endif
3568 if (r5or6_first_column != r5or6_last_column)
3569 return IO_ACCEL_INELIGIBLE;
3570
3571 /* Request is eligible */
3572 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3573 map->row_cnt;
3574
3575 map_index = (first_group *
3576 (map->row_cnt * total_disks_per_row)) +
3577 (map_row * total_disks_per_row) + first_column;
3578 break;
3579 default:
3580 return IO_ACCEL_INELIGIBLE;
283b4a9b 3581 }
6b80b18f 3582
283b4a9b
SC		 3583 disk_handle = dd[map_index].ioaccel_handle;
3584 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
3585 (first_row_offset - (first_column * map->strip_size));
3586 disk_block_cnt = block_cnt;
3587
3588 /* handle differing logical/physical block sizes */
3589 if (map->phys_blk_shift) {
3590 disk_block <<= map->phys_blk_shift;
3591 disk_block_cnt <<= map->phys_blk_shift;
3592 }
3593 BUG_ON(disk_block_cnt > 0xffff);
3594
3595 /* build the new CDB for the physical disk I/O */
3596 if (disk_block > 0xffffffff) {
3597 cdb[0] = is_write ? WRITE_16 : READ_16;
3598 cdb[1] = 0;
3599 cdb[2] = (u8) (disk_block >> 56);
3600 cdb[3] = (u8) (disk_block >> 48);
3601 cdb[4] = (u8) (disk_block >> 40);
3602 cdb[5] = (u8) (disk_block >> 32);
3603 cdb[6] = (u8) (disk_block >> 24);
3604 cdb[7] = (u8) (disk_block >> 16);
3605 cdb[8] = (u8) (disk_block >> 8);
3606 cdb[9] = (u8) (disk_block);
3607 cdb[10] = (u8) (disk_block_cnt >> 24);
3608 cdb[11] = (u8) (disk_block_cnt >> 16);
3609 cdb[12] = (u8) (disk_block_cnt >> 8);
3610 cdb[13] = (u8) (disk_block_cnt);
3611 cdb[14] = 0;
3612 cdb[15] = 0;
3613 cdb_len = 16;
3614 } else {
3615 cdb[0] = is_write ? WRITE_10 : READ_10;
3616 cdb[1] = 0;
3617 cdb[2] = (u8) (disk_block >> 24);
3618 cdb[3] = (u8) (disk_block >> 16);
3619 cdb[4] = (u8) (disk_block >> 8);
3620 cdb[5] = (u8) (disk_block);
3621 cdb[6] = 0;
3622 cdb[7] = (u8) (disk_block_cnt >> 8);
3623 cdb[8] = (u8) (disk_block_cnt);
3624 cdb[9] = 0;
3625 cdb_len = 10;
3626 }
3627 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3628 dev->scsi3addr);
3629}
3630
f281233d 3631static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
edd16368
SC		 3632 void (*done)(struct scsi_cmnd *))
3633{
3634 struct ctlr_info *h;
3635 struct hpsa_scsi_dev_t *dev;
3636 unsigned char scsi3addr[8];
3637 struct CommandList *c;
3638 unsigned long flags;
283b4a9b 3639 int rc = 0;
edd16368
SC		 3640
3641 /* Get the ptr to our adapter structure out of cmd->host. */
3642 h = sdev_to_hba(cmd->device);
3643 dev = cmd->device->hostdata;
3644 if (!dev) {
3645 cmd->result = DID_NO_CONNECT << 16;
3646 done(cmd);
3647 return 0;
3648 }
3649 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3650
edd16368 3651 spin_lock_irqsave(&h->lock, flags);
a0c12413
SC		 3652 if (unlikely(h->lockup_detected)) {
3653 spin_unlock_irqrestore(&h->lock, flags);
3654 cmd->result = DID_ERROR << 16;
3655 done(cmd);
3656 return 0;
3657 }
edd16368 3658 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 3659 c = cmd_alloc(h);
edd16368
SC		 3660 if (c == NULL) { /* trouble... */
3661 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
3662 return SCSI_MLQUEUE_HOST_BUSY;
3663 }
3664
3665 /* Fill in the command list header */
3666
3667 cmd->scsi_done = done; /* save this for use by completion code */
3668
3669 /* save c in case we have to abort it */
3670 cmd->host_scribble = (unsigned char *) c;
3671
3672 c->cmd_type = CMD_SCSI;
3673 c->scsi_cmd = cmd;
e1f7de0c 3674
283b4a9b
SC		 3675 /* Call alternate submit routine for I/O accelerated commands.
3676 * Retries always go down the normal I/O path.
3677 */
3678 if (likely(cmd->retries == 0 &&
da0697bd
ST		 3679 cmd->request->cmd_type == REQ_TYPE_FS &&
3680 h->acciopath_status)) {
283b4a9b
SC		 3681 if (dev->offload_enabled) {
3682 rc = hpsa_scsi_ioaccel_raid_map(h, c);
3683 if (rc == 0)
3684 return 0; /* Sent on ioaccel path */
3685 if (rc < 0) { /* scsi_dma_map failed. */
3686 cmd_free(h, c);
3687 return SCSI_MLQUEUE_HOST_BUSY;
3688 }
3689 } else if (dev->ioaccel_handle) {
3690 rc = hpsa_scsi_ioaccel_direct_map(h, c);
3691 if (rc == 0)
3692 return 0; /* Sent on direct map path */
3693 if (rc < 0) { /* scsi_dma_map failed. */
3694 cmd_free(h, c);
3695 return SCSI_MLQUEUE_HOST_BUSY;
3696 }
3697 }
3698 }
e1f7de0c 3699
edd16368
SC		 3700 c->Header.ReplyQueue = 0; /* unused in simple mode */
3701 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
303932fd
DB		 3702 c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
3703 c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
edd16368
SC		 3704
3705 /* Fill in the request block... */
3706
3707 c->Request.Timeout = 0;
3708 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
3709 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
3710 c->Request.CDBLen = cmd->cmd_len;
3711 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
3712 c->Request.Type.Type = TYPE_CMD;
3713 c->Request.Type.Attribute = ATTR_SIMPLE;
3714 switch (cmd->sc_data_direction) {
3715 case DMA_TO_DEVICE:
3716 c->Request.Type.Direction = XFER_WRITE;
3717 break;
3718 case DMA_FROM_DEVICE:
3719 c->Request.Type.Direction = XFER_READ;
3720 break;
3721 case DMA_NONE:
3722 c->Request.Type.Direction = XFER_NONE;
3723 break;
3724 case DMA_BIDIRECTIONAL:
3725 /* This can happen if a buggy application does a scsi passthru
3726 * and sets both inlen and outlen to non-zero. ( see
3727 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
3728 */
3729
3730 c->Request.Type.Direction = XFER_RSVD;
3731 /* This is technically wrong, and hpsa controllers should
3732 * reject it with CMD_INVALID, which is the most correct
3733 * response, but non-fibre backends appear to let it
3734 * slide by, and give the same results as if this field
3735 * were set correctly. Either way is acceptable for
3736 * our purposes here.
3737 */
3738
3739 break;
3740
3741 default:
3742 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3743 cmd->sc_data_direction);
3744 BUG();
3745 break;
3746 }
3747
33a2ffce 3748 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 3749 cmd_free(h, c);
3750 return SCSI_MLQUEUE_HOST_BUSY;
3751 }
3752 enqueue_cmd_and_start_io(h, c);
3753 /* the cmd'll come back via intr handler in complete_scsi_command() */
3754 return 0;
3755}
3756
f281233d
JG		 3757static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
3758
5f389360
SC		 3759static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
3760{
3761 unsigned long flags;
3762
3763 /*
3764 * Don't let rescans be initiated on a controller known
3765 * to be locked up. If the controller locks up *during*
3766 * a rescan, that thread is probably hosed, but at least
3767 * we can prevent new rescan threads from piling up on a
3768 * locked up controller.
3769 */
3770 spin_lock_irqsave(&h->lock, flags);
3771 if (unlikely(h->lockup_detected)) {
3772 spin_unlock_irqrestore(&h->lock, flags);
3773 spin_lock_irqsave(&h->scan_lock, flags);
3774 h->scan_finished = 1;
3775 wake_up_all(&h->scan_wait_queue);
3776 spin_unlock_irqrestore(&h->scan_lock, flags);
3777 return 1;
3778 }
3779 spin_unlock_irqrestore(&h->lock, flags);
3780 return 0;
3781}
3782
a08a8471
SC		 3783static void hpsa_scan_start(struct Scsi_Host *sh)
3784{
3785 struct ctlr_info *h = shost_to_hba(sh);
3786 unsigned long flags;
3787
5f389360
SC		 3788 if (do_not_scan_if_controller_locked_up(h))
3789 return;
3790
a08a8471
SC		 3791 /* wait until any scan already in progress is finished. */
3792 while (1) {
3793 spin_lock_irqsave(&h->scan_lock, flags);
3794 if (h->scan_finished)
3795 break;
3796 spin_unlock_irqrestore(&h->scan_lock, flags);
3797 wait_event(h->scan_wait_queue, h->scan_finished);
3798 /* Note: We don't need to worry about a race between this
3799 * thread and driver unload because the midlayer will
3800 * have incremented the reference count, so unload won't
3801 * happen if we're in here.
3802 */
3803 }
3804 h->scan_finished = 0; /* mark scan as in progress */
3805 spin_unlock_irqrestore(&h->scan_lock, flags);
3806
5f389360
SC		 3807 if (do_not_scan_if_controller_locked_up(h))
3808 return;
3809
a08a8471
SC		 3810 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
3811
3812 spin_lock_irqsave(&h->scan_lock, flags);
3813 h->scan_finished = 1; /* mark scan as finished. */
3814 wake_up_all(&h->scan_wait_queue);
3815 spin_unlock_irqrestore(&h->scan_lock, flags);
3816}
3817
3818static int hpsa_scan_finished(struct Scsi_Host *sh,
3819 unsigned long elapsed_time)
3820{
3821 struct ctlr_info *h = shost_to_hba(sh);
3822 unsigned long flags;
3823 int finished;
3824
3825 spin_lock_irqsave(&h->scan_lock, flags);
3826 finished = h->scan_finished;
3827 spin_unlock_irqrestore(&h->scan_lock, flags);
3828 return finished;
3829}
3830
667e23d4
SC		 3831static int hpsa_change_queue_depth(struct scsi_device *sdev,
3832 int qdepth, int reason)
3833{
3834 struct ctlr_info *h = sdev_to_hba(sdev);
3835
3836 if (reason != SCSI_QDEPTH_DEFAULT)
3837 return -ENOTSUPP;
3838
3839 if (qdepth < 1)
3840 qdepth = 1;
3841 else
3842 if (qdepth > h->nr_cmds)
3843 qdepth = h->nr_cmds;
3844 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
3845 return sdev->queue_depth;
3846}
3847
edd16368
SC		 3848static void hpsa_unregister_scsi(struct ctlr_info *h)
3849{
3850 /* we are being forcibly unloaded, and may not refuse. */
3851 scsi_remove_host(h->scsi_host);
3852 scsi_host_put(h->scsi_host);
3853 h->scsi_host = NULL;
3854}
3855
3856static int hpsa_register_scsi(struct ctlr_info *h)
3857{
b705690d
SC		 3858 struct Scsi_Host *sh;
3859 int error;
edd16368 3860
b705690d
SC		 3861 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
3862 if (sh == NULL)
3863 goto fail;
3864
3865 sh->io_port = 0;
3866 sh->n_io_port = 0;
3867 sh->this_id = -1;
3868 sh->max_channel = 3;
3869 sh->max_cmd_len = MAX_COMMAND_SIZE;
3870 sh->max_lun = HPSA_MAX_LUN;
3871 sh->max_id = HPSA_MAX_LUN;
3872 sh->can_queue = h->nr_cmds;
3873 sh->cmd_per_lun = h->nr_cmds;
3874 sh->sg_tablesize = h->maxsgentries;
3875 h->scsi_host = sh;
3876 sh->hostdata[0] = (unsigned long) h;
3877 sh->irq = h->intr[h->intr_mode];
3878 sh->unique_id = sh->irq;
3879 error = scsi_add_host(sh, &h->pdev->dev);
3880 if (error)
3881 goto fail_host_put;
3882 scsi_scan_host(sh);
3883 return 0;
3884
3885 fail_host_put:
3886 dev_err(&h->pdev->dev, "%s: scsi_add_host"
3887 " failed for controller %d\n", __func__, h->ctlr);
3888 scsi_host_put(sh);
3889 return error;
3890 fail:
3891 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
3892 " failed for controller %d\n", __func__, h->ctlr);
3893 return -ENOMEM;
edd16368
SC		 3894}
3895
3896static int wait_for_device_to_become_ready(struct ctlr_info *h,
3897 unsigned char lunaddr[])
3898{
3899 int rc = 0;
3900 int count = 0;
3901 int waittime = 1; /* seconds */
3902 struct CommandList *c;
3903
3904 c = cmd_special_alloc(h);
3905 if (!c) {
3906 dev_warn(&h->pdev->dev, "out of memory in "
3907 "wait_for_device_to_become_ready.\n");
3908 return IO_ERROR;
3909 }
3910
3911 /* Send test unit ready until device ready, or give up. */
3912 while (count < HPSA_TUR_RETRY_LIMIT) {
3913
3914 /* Wait for a bit. do this first, because if we send
3915 * the TUR right away, the reset will just abort it.
3916 */
3917 msleep(1000 * waittime);
3918 count++;
3919
3920 /* Increase wait time with each try, up to a point. */
3921 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
3922 waittime = waittime * 2;
3923
a2dac136
SC		 3924 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
3925 (void) fill_cmd(c, TEST_UNIT_READY, h,
3926 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 3927 hpsa_scsi_do_simple_cmd_core(h, c);
3928 /* no unmap needed here because no data xfer. */
3929
3930 if (c->err_info->CommandStatus == CMD_SUCCESS)
3931 break;
3932
3933 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
3934 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
3935 (c->err_info->SenseInfo[2] == NO_SENSE ||
3936 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
3937 break;
3938
3939 dev_warn(&h->pdev->dev, "waiting %d secs "
3940 "for device to become ready.\n", waittime);
3941 rc = 1; /* device not ready. */
3942 }
3943
3944 if (rc)
3945 dev_warn(&h->pdev->dev, "giving up on device.\n");
3946 else
3947 dev_warn(&h->pdev->dev, "device is ready.\n");
3948
3949 cmd_special_free(h, c);
3950 return rc;
3951}
3952
3953/* Need at least one of these error handlers to keep ../scsi/hosts.c from
3954 * complaining. Doing a host- or bus-reset can't do anything good here.
3955 */
3956static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
3957{
3958 int rc;
3959 struct ctlr_info *h;
3960 struct hpsa_scsi_dev_t *dev;
3961
3962 /* find the controller to which the command to be aborted was sent */
3963 h = sdev_to_hba(scsicmd->device);
3964 if (h == NULL) /* paranoia */
3965 return FAILED;
edd16368
SC		 3966 dev = scsicmd->device->hostdata;
3967 if (!dev) {
3968 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
3969 "device lookup failed.\n");
3970 return FAILED;
3971 }
d416b0c7
SC		 3972 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
3973 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 3974 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 3975 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 3976 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
3977 return SUCCESS;
3978
3979 dev_warn(&h->pdev->dev, "resetting device failed.\n");
3980 return FAILED;
3981}
3982
6cba3f19
SC		 3983static void swizzle_abort_tag(u8 *tag)
3984{
3985 u8 original_tag[8];
3986
3987 memcpy(original_tag, tag, 8);
3988 tag[0] = original_tag[3];
3989 tag[1] = original_tag[2];
3990 tag[2] = original_tag[1];
3991 tag[3] = original_tag[0];
3992 tag[4] = original_tag[7];
3993 tag[5] = original_tag[6];
3994 tag[6] = original_tag[5];
3995 tag[7] = original_tag[4];
3996}
3997
17eb87d2
ST		 3998static void hpsa_get_tag(struct ctlr_info *h,
3999 struct CommandList *c, u32 *taglower, u32 *tagupper)
4000{
4001 if (c->cmd_type == CMD_IOACCEL1) {
4002 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
4003 &h->ioaccel_cmd_pool[c->cmdindex];
4004 *tagupper = cm1->Tag.upper;
4005 *taglower = cm1->Tag.lower;
54b6e9e9
ST		 4006 return;
4007 }
4008 if (c->cmd_type == CMD_IOACCEL2) {
4009 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
4010 &h->ioaccel2_cmd_pool[c->cmdindex];
dd0e19f3
ST		 4011 /* upper tag not used in ioaccel2 mode */
4012 memset(tagupper, 0, sizeof(*tagupper));
4013 *taglower = cm2->Tag;
54b6e9e9 4014 return;
17eb87d2 4015 }
54b6e9e9
ST		 4016 *tagupper = c->Header.Tag.upper;
4017 *taglower = c->Header.Tag.lower;
17eb87d2
ST		 4018}
4019
54b6e9e9 4020
75167d2c 4021static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 4022 struct CommandList *abort, int swizzle)
75167d2c
SC		 4023{
4024 int rc = IO_OK;
4025 struct CommandList *c;
4026 struct ErrorInfo *ei;
17eb87d2 4027 u32 tagupper, taglower;
75167d2c
SC		 4028
4029 c = cmd_special_alloc(h);
4030 if (c == NULL) { /* trouble... */
4031 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
4032 return -ENOMEM;
4033 }
4034
a2dac136
SC		 4035 /* fill_cmd can't fail here, no buffer to map */
4036 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
4037 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 4038 if (swizzle)
4039 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 4040 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 4041 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 4042 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 4043 __func__, tagupper, taglower);
75167d2c
SC		 4044 /* no unmap needed here because no data xfer. */
4045
4046 ei = c->err_info;
4047 switch (ei->CommandStatus) {
4048 case CMD_SUCCESS:
4049 break;
4050 case CMD_UNABORTABLE: /* Very common, don't make noise. */
4051 rc = -1;
4052 break;
4053 default:
4054 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 4055 __func__, tagupper, taglower);
d1e8beac 4056 hpsa_scsi_interpret_error(h, c);
75167d2c
SC		 4057 rc = -1;
4058 break;
4059 }
4060 cmd_special_free(h, c);
dd0e19f3
ST		 4061 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
4062 __func__, tagupper, taglower);
75167d2c
SC		 4063 return rc;
4064}
4065
4066/*
4067 * hpsa_find_cmd_in_queue
4068 *
4069 * Used to determine whether a command (find) is still present
4070 * in queue_head. Optionally excludes the last element of queue_head.
4071 *
4072 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
4073 * not yet been submitted, and so can be aborted by the driver without
4074 * sending an abort to the hardware.
4075 *
4076 * Returns pointer to command if found in queue, NULL otherwise.
4077 */
4078static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
4079 struct scsi_cmnd *find, struct list_head *queue_head)
4080{
4081 unsigned long flags;
4082 struct CommandList *c = NULL; /* ptr into cmpQ */
4083
4084 if (!find)
4085 return 0;
4086 spin_lock_irqsave(&h->lock, flags);
4087 list_for_each_entry(c, queue_head, list) {
4088 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
4089 continue;
4090 if (c->scsi_cmd == find) {
4091 spin_unlock_irqrestore(&h->lock, flags);
4092 return c;
4093 }
4094 }
4095 spin_unlock_irqrestore(&h->lock, flags);
4096 return NULL;
4097}
4098
6cba3f19
SC		 4099static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
4100 u8 *tag, struct list_head *queue_head)
4101{
4102 unsigned long flags;
4103 struct CommandList *c;
4104
4105 spin_lock_irqsave(&h->lock, flags);
4106 list_for_each_entry(c, queue_head, list) {
4107 if (memcmp(&c->Header.Tag, tag, 8) != 0)
4108 continue;
4109 spin_unlock_irqrestore(&h->lock, flags);
4110 return c;
4111 }
4112 spin_unlock_irqrestore(&h->lock, flags);
4113 return NULL;
4114}
4115
54b6e9e9
ST		 4116/* ioaccel2 path firmware cannot handle abort task requests.
4117 * Change abort requests to physical target reset, and send to the
4118 * address of the physical disk used for the ioaccel 2 command.
4119 * Return 0 on success (IO_OK)
4120 * -1 on failure
4121 */
4122
4123static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
4124 unsigned char *scsi3addr, struct CommandList *abort)
4125{
4126 int rc = IO_OK;
4127 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
4128 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
4129 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
4130 unsigned char *psa = &phys_scsi3addr[0];
4131
4132 /* Get a pointer to the hpsa logical device. */
4133 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
4134 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
4135 if (dev == NULL) {
4136 dev_warn(&h->pdev->dev,
4137 "Cannot abort: no device pointer for command.\n");
4138 return -1; /* not abortable */
4139 }
4140
2ba8bfc8
SC		 4141 if (h->raid_offload_debug > 0)
4142 dev_info(&h->pdev->dev,
4143 "Reset as abort: Abort requested on C%d:B%d:T%d:L%d scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4144 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
4145 scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
4146 scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
4147
54b6e9e9
ST		 4148 if (!dev->offload_enabled) {
4149 dev_warn(&h->pdev->dev,
4150 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
4151 return -1; /* not abortable */
4152 }
4153
4154 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
4155 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
4156 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
4157 return -1; /* not abortable */
4158 }
4159
4160 /* send the reset */
2ba8bfc8
SC		 4161 if (h->raid_offload_debug > 0)
4162 dev_info(&h->pdev->dev,
4163 "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4164 psa[0], psa[1], psa[2], psa[3],
4165 psa[4], psa[5], psa[6], psa[7]);
54b6e9e9
ST		 4166 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
4167 if (rc != 0) {
4168 dev_warn(&h->pdev->dev,
4169 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4170 psa[0], psa[1], psa[2], psa[3],
4171 psa[4], psa[5], psa[6], psa[7]);
4172 return rc; /* failed to reset */
4173 }
4174
4175 /* wait for device to recover */
4176 if (wait_for_device_to_become_ready(h, psa) != 0) {
4177 dev_warn(&h->pdev->dev,
4178 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4179 psa[0], psa[1], psa[2], psa[3],
4180 psa[4], psa[5], psa[6], psa[7]);
4181 return -1; /* failed to recover */
4182 }
4183
4184 /* device recovered */
4185 dev_info(&h->pdev->dev,
4186 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
4187 psa[0], psa[1], psa[2], psa[3],
4188 psa[4], psa[5], psa[6], psa[7]);
4189
4190 return rc; /* success */
4191}
4192
6cba3f19
SC		 4193/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
4194 * tell which kind we're dealing with, so we send the abort both ways. There
4195 * shouldn't be any collisions between swizzled and unswizzled tags due to the
4196 * way we construct our tags but we check anyway in case the assumptions which
4197 * make this true someday become false.
4198 */
4199static int hpsa_send_abort_both_ways(struct ctlr_info *h,
4200 unsigned char *scsi3addr, struct CommandList *abort)
4201{
4202 u8 swizzled_tag[8];
4203 struct CommandList *c;
4204 int rc = 0, rc2 = 0;
4205
54b6e9e9
ST		 4206 /* ioccelerator mode 2 commands should be aborted via the
4207 * accelerated path, since RAID path is unaware of these commands,
4208 * but underlying firmware can't handle abort TMF.
4209 * Change abort to physical device reset.
4210 */
4211 if (abort->cmd_type == CMD_IOACCEL2)
4212 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
4213
6cba3f19
SC		 4214 /* we do not expect to find the swizzled tag in our queue, but
4215 * check anyway just to be sure the assumptions which make this
4216 * the case haven't become wrong.
4217 */
4218 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
4219 swizzle_abort_tag(swizzled_tag);
4220 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
4221 if (c != NULL) {
4222 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
4223 return hpsa_send_abort(h, scsi3addr, abort, 0);
4224 }
4225 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
4226
4227 /* if the command is still in our queue, we can't conclude that it was
4228 * aborted (it might have just completed normally) but in any case
4229 * we don't need to try to abort it another way.
4230 */
4231 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
4232 if (c)
4233 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
4234 return rc && rc2;
4235}
4236
75167d2c
SC		 4237/* Send an abort for the specified command.
4238 * If the device and controller support it,
4239 * send a task abort request.
4240 */
4241static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
4242{
4243
4244 int i, rc;
4245 struct ctlr_info *h;
4246 struct hpsa_scsi_dev_t *dev;
4247 struct CommandList *abort; /* pointer to command to be aborted */
4248 struct CommandList *found;
4249 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
4250 char msg[256]; /* For debug messaging. */
4251 int ml = 0;
17eb87d2 4252 u32 tagupper, taglower;
75167d2c
SC		 4253
4254 /* Find the controller of the command to be aborted */
4255 h = sdev_to_hba(sc->device);
4256 if (WARN(h == NULL,
4257 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
4258 return FAILED;
4259
4260 /* Check that controller supports some kind of task abort */
4261 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
4262 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
4263 return FAILED;
4264
4265 memset(msg, 0, sizeof(msg));
4266 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
4267 h->scsi_host->host_no, sc->device->channel,
4268 sc->device->id, sc->device->lun);
4269
4270 /* Find the device of the command to be aborted */
4271 dev = sc->device->hostdata;
4272 if (!dev) {
4273 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
4274 msg);
4275 return FAILED;
4276 }
4277
4278 /* Get SCSI command to be aborted */
4279 abort = (struct CommandList *) sc->host_scribble;
4280 if (abort == NULL) {
4281 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
4282 msg);
4283 return FAILED;
4284 }
17eb87d2
ST		 4285 hpsa_get_tag(h, abort, &taglower, &tagupper);
4286 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 4287 as = (struct scsi_cmnd *) abort->scsi_cmd;
4288 if (as != NULL)
4289 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
4290 as->cmnd[0], as->serial_number);
4291 dev_dbg(&h->pdev->dev, "%s\n", msg);
4292 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
4293 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
4294
4295 /* Search reqQ to See if command is queued but not submitted,
4296 * if so, complete the command with aborted status and remove
4297 * it from the reqQ.
4298 */
4299 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
4300 if (found) {
4301 found->err_info->CommandStatus = CMD_ABORTED;
4302 finish_cmd(found);
4303 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
4304 msg);
4305 return SUCCESS;
4306 }
4307
4308 /* not in reqQ, if also not in cmpQ, must have already completed */
4309 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4310 if (!found) {
d6ebd0f7 4311 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 4312 msg);
4313 return SUCCESS;
4314 }
4315
4316 /*
4317 * Command is in flight, or possibly already completed
4318 * by the firmware (but not to the scsi mid layer) but we can't
4319 * distinguish which. Send the abort down.
4320 */
6cba3f19 4321 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 4322 if (rc != 0) {
4323 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
4324 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
4325 h->scsi_host->host_no,
4326 dev->bus, dev->target, dev->lun);
4327 return FAILED;
4328 }
4329 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
4330
4331 /* If the abort(s) above completed and actually aborted the
4332 * command, then the command to be aborted should already be
4333 * completed. If not, wait around a bit more to see if they
4334 * manage to complete normally.
4335 */
4336#define ABORT_COMPLETE_WAIT_SECS 30
4337 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
4338 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
4339 if (!found)
4340 return SUCCESS;
4341 msleep(100);
4342 }
4343 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
4344 msg, ABORT_COMPLETE_WAIT_SECS);
4345 return FAILED;
4346}
4347
4348
edd16368
SC		 4349/*
4350 * For operations that cannot sleep, a command block is allocated at init,
4351 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4352 * which ones are free or in use. Lock must be held when calling this.
4353 * cmd_free() is the complement.
4354 */
4355static struct CommandList *cmd_alloc(struct ctlr_info *h)
4356{
4357 struct CommandList *c;
4358 int i;
4359 union u64bit temp64;
4360 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 4361 unsigned long flags;
edd16368 4362
e16a33ad 4363 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4364 do {
4365 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 4366 if (i == h->nr_cmds) {
4367 spin_unlock_irqrestore(&h->lock, flags);
edd16368 4368 return NULL;
e16a33ad 4369 }
edd16368
SC		 4370 } while (test_and_set_bit
4371 (i & (BITS_PER_LONG - 1),
4372 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 4373 spin_unlock_irqrestore(&h->lock, flags);
4374
edd16368
SC		 4375 c = h->cmd_pool + i;
4376 memset(c, 0, sizeof(*c));
4377 cmd_dma_handle = h->cmd_pool_dhandle
4378 + i * sizeof(*c);
4379 c->err_info = h->errinfo_pool + i;
4380 memset(c->err_info, 0, sizeof(*c->err_info));
4381 err_dma_handle = h->errinfo_pool_dhandle
4382 + i * sizeof(*c->err_info);
edd16368
SC		 4383
4384 c->cmdindex = i;
4385
9e0fc764 4386 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4387 c->busaddr = (u32) cmd_dma_handle;
4388 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4389 c->ErrDesc.Addr.lower = temp64.val32.lower;
4390 c->ErrDesc.Addr.upper = temp64.val32.upper;
4391 c->ErrDesc.Len = sizeof(*c->err_info);
4392
4393 c->h = h;
4394 return c;
4395}
4396
4397/* For operations that can wait for kmalloc to possibly sleep,
4398 * this routine can be called. Lock need not be held to call
4399 * cmd_special_alloc. cmd_special_free() is the complement.
4400 */
4401static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
4402{
4403 struct CommandList *c;
4404 union u64bit temp64;
4405 dma_addr_t cmd_dma_handle, err_dma_handle;
4406
4407 c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
4408 if (c == NULL)
4409 return NULL;
4410 memset(c, 0, sizeof(*c));
4411
e1f7de0c 4412 c->cmd_type = CMD_SCSI;
edd16368
SC		 4413 c->cmdindex = -1;
4414
4415 c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
4416 &err_dma_handle);
4417
4418 if (c->err_info == NULL) {
4419 pci_free_consistent(h->pdev,
4420 sizeof(*c), c, cmd_dma_handle);
4421 return NULL;
4422 }
4423 memset(c->err_info, 0, sizeof(*c->err_info));
4424
9e0fc764 4425 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4426 c->busaddr = (u32) cmd_dma_handle;
4427 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4428 c->ErrDesc.Addr.lower = temp64.val32.lower;
4429 c->ErrDesc.Addr.upper = temp64.val32.upper;
4430 c->ErrDesc.Len = sizeof(*c->err_info);
4431
4432 c->h = h;
4433 return c;
4434}
4435
4436static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4437{
4438 int i;
e16a33ad 4439 unsigned long flags;
edd16368
SC		 4440
4441 i = c - h->cmd_pool;
e16a33ad 4442 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4443 clear_bit(i & (BITS_PER_LONG - 1),
4444 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 4445 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4446}
4447
4448static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
4449{
4450 union u64bit temp64;
4451
4452 temp64.val32.lower = c->ErrDesc.Addr.lower;
4453 temp64.val32.upper = c->ErrDesc.Addr.upper;
4454 pci_free_consistent(h->pdev, sizeof(*c->err_info),
4455 c->err_info, (dma_addr_t) temp64.val);
4456 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 4457 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 4458}
4459
4460#ifdef CONFIG_COMPAT
4461
edd16368
SC		 4462static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
4463{
4464 IOCTL32_Command_struct __user *arg32 =
4465 (IOCTL32_Command_struct __user *) arg;
4466 IOCTL_Command_struct arg64;
4467 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4468 int err;
4469 u32 cp;
4470
938abd84 4471 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4472 err = 0;
4473 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4474 sizeof(arg64.LUN_info));
4475 err |= copy_from_user(&arg64.Request, &arg32->Request,
4476 sizeof(arg64.Request));
4477 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4478 sizeof(arg64.error_info));
4479 err |= get_user(arg64.buf_size, &arg32->buf_size);
4480 err |= get_user(cp, &arg32->buf);
4481 arg64.buf = compat_ptr(cp);
4482 err |= copy_to_user(p, &arg64, sizeof(arg64));
4483
4484 if (err)
4485 return -EFAULT;
4486
e39eeaed 4487 err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
edd16368
SC		 4488 if (err)
4489 return err;
4490 err |= copy_in_user(&arg32->error_info, &p->error_info,
4491 sizeof(arg32->error_info));
4492 if (err)
4493 return -EFAULT;
4494 return err;
4495}
4496
4497static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
4498 int cmd, void *arg)
4499{
4500 BIG_IOCTL32_Command_struct __user *arg32 =
4501 (BIG_IOCTL32_Command_struct __user *) arg;
4502 BIG_IOCTL_Command_struct arg64;
4503 BIG_IOCTL_Command_struct __user *p =
4504 compat_alloc_user_space(sizeof(arg64));
4505 int err;
4506 u32 cp;
4507
938abd84 4508 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4509 err = 0;
4510 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4511 sizeof(arg64.LUN_info));
4512 err |= copy_from_user(&arg64.Request, &arg32->Request,
4513 sizeof(arg64.Request));
4514 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4515 sizeof(arg64.error_info));
4516 err |= get_user(arg64.buf_size, &arg32->buf_size);
4517 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4518 err |= get_user(cp, &arg32->buf);
4519 arg64.buf = compat_ptr(cp);
4520 err |= copy_to_user(p, &arg64, sizeof(arg64));
4521
4522 if (err)
4523 return -EFAULT;
4524
e39eeaed 4525 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
edd16368
SC		 4526 if (err)
4527 return err;
4528 err |= copy_in_user(&arg32->error_info, &p->error_info,
4529 sizeof(arg32->error_info));
4530 if (err)
4531 return -EFAULT;
4532 return err;
4533}
71fe75a7
SC		 4534
4535static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
4536{
4537 switch (cmd) {
4538 case CCISS_GETPCIINFO:
4539 case CCISS_GETINTINFO:
4540 case CCISS_SETINTINFO:
4541 case CCISS_GETNODENAME:
4542 case CCISS_SETNODENAME:
4543 case CCISS_GETHEARTBEAT:
4544 case CCISS_GETBUSTYPES:
4545 case CCISS_GETFIRMVER:
4546 case CCISS_GETDRIVVER:
4547 case CCISS_REVALIDVOLS:
4548 case CCISS_DEREGDISK:
4549 case CCISS_REGNEWDISK:
4550 case CCISS_REGNEWD:
4551 case CCISS_RESCANDISK:
4552 case CCISS_GETLUNINFO:
4553 return hpsa_ioctl(dev, cmd, arg);
4554
4555 case CCISS_PASSTHRU32:
4556 return hpsa_ioctl32_passthru(dev, cmd, arg);
4557 case CCISS_BIG_PASSTHRU32:
4558 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4559
4560 default:
4561 return -ENOIOCTLCMD;
4562 }
4563}
edd16368
SC		 4564#endif
4565
4566static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4567{
4568 struct hpsa_pci_info pciinfo;
4569
4570 if (!argp)
4571 return -EINVAL;
4572 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4573 pciinfo.bus = h->pdev->bus->number;
4574 pciinfo.dev_fn = h->pdev->devfn;
4575 pciinfo.board_id = h->board_id;
4576 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4577 return -EFAULT;
4578 return 0;
4579}
4580
4581static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4582{
4583 DriverVer_type DriverVer;
4584 unsigned char vmaj, vmin, vsubmin;
4585 int rc;
4586
4587 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4588 &vmaj, &vmin, &vsubmin);
4589 if (rc != 3) {
4590 dev_info(&h->pdev->dev, "driver version string '%s' "
4591 "unrecognized.", HPSA_DRIVER_VERSION);
4592 vmaj = 0;
4593 vmin = 0;
4594 vsubmin = 0;
4595 }
4596 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4597 if (!argp)
4598 return -EINVAL;
4599 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4600 return -EFAULT;
4601 return 0;
4602}
4603
4604static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4605{
4606 IOCTL_Command_struct iocommand;
4607 struct CommandList *c;
4608 char *buff = NULL;
4609 union u64bit temp64;
c1f63c8f 4610 int rc = 0;
edd16368
SC		 4611
4612 if (!argp)
4613 return -EINVAL;
4614 if (!capable(CAP_SYS_RAWIO))
4615 return -EPERM;
4616 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4617 return -EFAULT;
4618 if ((iocommand.buf_size < 1) &&
4619 (iocommand.Request.Type.Direction != XFER_NONE)) {
4620 return -EINVAL;
4621 }
4622 if (iocommand.buf_size > 0) {
4623 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4624 if (buff == NULL)
4625 return -EFAULT;
b03a7771
SC		 4626 if (iocommand.Request.Type.Direction == XFER_WRITE) {
4627 /* Copy the data into the buffer we created */
4628 if (copy_from_user(buff, iocommand.buf,
4629 iocommand.buf_size)) {
c1f63c8f
SC		 4630 rc = -EFAULT;
4631 goto out_kfree;
b03a7771
SC		 4632 }
4633 } else {
4634 memset(buff, 0, iocommand.buf_size);
edd16368 4635 }
b03a7771 4636 }
edd16368
SC		 4637 c = cmd_special_alloc(h);
4638 if (c == NULL) {
c1f63c8f
SC		 4639 rc = -ENOMEM;
4640 goto out_kfree;
edd16368
SC		 4641 }
4642 /* Fill in the command type */
4643 c->cmd_type = CMD_IOCTL_PEND;
4644 /* Fill in Command Header */
4645 c->Header.ReplyQueue = 0; /* unused in simple mode */
4646 if (iocommand.buf_size > 0) { /* buffer to fill */
4647 c->Header.SGList = 1;
4648 c->Header.SGTotal = 1;
4649 } else { /* no buffers to fill */
4650 c->Header.SGList = 0;
4651 c->Header.SGTotal = 0;
4652 }
4653 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
4654 /* use the kernel address the cmd block for tag */
4655 c->Header.Tag.lower = c->busaddr;
4656
4657 /* Fill in Request block */
4658 memcpy(&c->Request, &iocommand.Request,
4659 sizeof(c->Request));
4660
4661 /* Fill in the scatter gather information */
4662 if (iocommand.buf_size > 0) {
4663 temp64.val = pci_map_single(h->pdev, buff,
4664 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4665 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4666 c->SG[0].Addr.lower = 0;
4667 c->SG[0].Addr.upper = 0;
4668 c->SG[0].Len = 0;
4669 rc = -ENOMEM;
4670 goto out;
4671 }
edd16368
SC		 4672 c->SG[0].Addr.lower = temp64.val32.lower;
4673 c->SG[0].Addr.upper = temp64.val32.upper;
4674 c->SG[0].Len = iocommand.buf_size;
e1d9cbfa 4675 c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/
edd16368 4676 }
a0c12413 4677 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 4678 if (iocommand.buf_size > 0)
4679 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4680 check_ioctl_unit_attention(h, c);
4681
4682 /* Copy the error information out */
4683 memcpy(&iocommand.error_info, c->err_info,
4684 sizeof(iocommand.error_info));
4685 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 4686 rc = -EFAULT;
4687 goto out;
edd16368 4688 }
b03a7771
SC		 4689 if (iocommand.Request.Type.Direction == XFER_READ &&
4690 iocommand.buf_size > 0) {
edd16368
SC		 4691 /* Copy the data out of the buffer we created */
4692 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 4693 rc = -EFAULT;
4694 goto out;
edd16368
SC		 4695 }
4696 }
c1f63c8f 4697out:
edd16368 4698 cmd_special_free(h, c);
c1f63c8f
SC		 4699out_kfree:
4700 kfree(buff);
4701 return rc;
edd16368
SC		 4702}
4703
4704static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4705{
4706 BIG_IOCTL_Command_struct *ioc;
4707 struct CommandList *c;
4708 unsigned char **buff = NULL;
4709 int *buff_size = NULL;
4710 union u64bit temp64;
4711 BYTE sg_used = 0;
4712 int status = 0;
4713 int i;
01a02ffc
SC		 4714 u32 left;
4715 u32 sz;
edd16368
SC		 4716 BYTE __user *data_ptr;
4717
4718 if (!argp)
4719 return -EINVAL;
4720 if (!capable(CAP_SYS_RAWIO))
4721 return -EPERM;
4722 ioc = (BIG_IOCTL_Command_struct *)
4723 kmalloc(sizeof(*ioc), GFP_KERNEL);
4724 if (!ioc) {
4725 status = -ENOMEM;
4726 goto cleanup1;
4727 }
4728 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
4729 status = -EFAULT;
4730 goto cleanup1;
4731 }
4732 if ((ioc->buf_size < 1) &&
4733 (ioc->Request.Type.Direction != XFER_NONE)) {
4734 status = -EINVAL;
4735 goto cleanup1;
4736 }
4737 /* Check kmalloc limits using all SGs */
4738 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
4739 status = -EINVAL;
4740 goto cleanup1;
4741 }
d66ae08b 4742 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 4743 status = -EINVAL;
4744 goto cleanup1;
4745 }
d66ae08b 4746 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 4747 if (!buff) {
4748 status = -ENOMEM;
4749 goto cleanup1;
4750 }
d66ae08b 4751 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 4752 if (!buff_size) {
4753 status = -ENOMEM;
4754 goto cleanup1;
4755 }
4756 left = ioc->buf_size;
4757 data_ptr = ioc->buf;
4758 while (left) {
4759 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
4760 buff_size[sg_used] = sz;
4761 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
4762 if (buff[sg_used] == NULL) {
4763 status = -ENOMEM;
4764 goto cleanup1;
4765 }
4766 if (ioc->Request.Type.Direction == XFER_WRITE) {
4767 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
4768 status = -ENOMEM;
4769 goto cleanup1;
4770 }
4771 } else
4772 memset(buff[sg_used], 0, sz);
4773 left -= sz;
4774 data_ptr += sz;
4775 sg_used++;
4776 }
4777 c = cmd_special_alloc(h);
4778 if (c == NULL) {
4779 status = -ENOMEM;
4780 goto cleanup1;
4781 }
4782 c->cmd_type = CMD_IOCTL_PEND;
4783 c->Header.ReplyQueue = 0;
b03a7771 4784 c->Header.SGList = c->Header.SGTotal = sg_used;
edd16368
SC		 4785 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
4786 c->Header.Tag.lower = c->busaddr;
4787 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
4788 if (ioc->buf_size > 0) {
4789 int i;
4790 for (i = 0; i < sg_used; i++) {
4791 temp64.val = pci_map_single(h->pdev, buff[i],
4792 buff_size[i], PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4793 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4794 c->SG[i].Addr.lower = 0;
4795 c->SG[i].Addr.upper = 0;
4796 c->SG[i].Len = 0;
4797 hpsa_pci_unmap(h->pdev, c, i,
4798 PCI_DMA_BIDIRECTIONAL);
4799 status = -ENOMEM;
e2d4a1f6 4800 goto cleanup0;
bcc48ffa 4801 }
edd16368
SC		 4802 c->SG[i].Addr.lower = temp64.val32.lower;
4803 c->SG[i].Addr.upper = temp64.val32.upper;
4804 c->SG[i].Len = buff_size[i];
e1d9cbfa 4805 c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST;
edd16368
SC		 4806 }
4807 }
a0c12413 4808 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 4809 if (sg_used)
4810 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4811 check_ioctl_unit_attention(h, c);
4812 /* Copy the error information out */
4813 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
4814 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 4815 status = -EFAULT;
e2d4a1f6 4816 goto cleanup0;
edd16368 4817 }
b03a7771 4818 if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
edd16368
SC		 4819 /* Copy the data out of the buffer we created */
4820 BYTE __user *ptr = ioc->buf;
4821 for (i = 0; i < sg_used; i++) {
4822 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 4823 status = -EFAULT;
e2d4a1f6 4824 goto cleanup0;
edd16368
SC		 4825 }
4826 ptr += buff_size[i];
4827 }
4828 }
edd16368 4829 status = 0;
e2d4a1f6
SC		 4830cleanup0:
4831 cmd_special_free(h, c);
edd16368
SC		 4832cleanup1:
4833 if (buff) {
4834 for (i = 0; i < sg_used; i++)
4835 kfree(buff[i]);
4836 kfree(buff);
4837 }
4838 kfree(buff_size);
4839 kfree(ioc);
4840 return status;
4841}
4842
4843static void check_ioctl_unit_attention(struct ctlr_info *h,
4844 struct CommandList *c)
4845{
4846 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4847 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
4848 (void) check_for_unit_attention(h, c);
4849}
0390f0c0
SC		 4850
4851static int increment_passthru_count(struct ctlr_info *h)
4852{
4853 unsigned long flags;
4854
4855 spin_lock_irqsave(&h->passthru_count_lock, flags);
4856 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
4857 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4858 return -1;
4859 }
4860 h->passthru_count++;
4861 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4862 return 0;
4863}
4864
4865static void decrement_passthru_count(struct ctlr_info *h)
4866{
4867 unsigned long flags;
4868
4869 spin_lock_irqsave(&h->passthru_count_lock, flags);
4870 if (h->passthru_count <= 0) {
4871 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4872 /* not expecting to get here. */
4873 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
4874 return;
4875 }
4876 h->passthru_count--;
4877 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4878}
4879
edd16368
SC		 4880/*
4881 * ioctl
4882 */
4883static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
4884{
4885 struct ctlr_info *h;
4886 void __user *argp = (void __user *)arg;
0390f0c0 4887 int rc;
edd16368
SC		 4888
4889 h = sdev_to_hba(dev);
4890
4891 switch (cmd) {
4892 case CCISS_DEREGDISK:
4893 case CCISS_REGNEWDISK:
4894 case CCISS_REGNEWD:
a08a8471 4895 hpsa_scan_start(h->scsi_host);
edd16368
SC		 4896 return 0;
4897 case CCISS_GETPCIINFO:
4898 return hpsa_getpciinfo_ioctl(h, argp);
4899 case CCISS_GETDRIVVER:
4900 return hpsa_getdrivver_ioctl(h, argp);
4901 case CCISS_PASSTHRU:
0390f0c0
SC		 4902 if (increment_passthru_count(h))
4903 return -EAGAIN;
4904 rc = hpsa_passthru_ioctl(h, argp);
4905 decrement_passthru_count(h);
4906 return rc;
edd16368 4907 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 4908 if (increment_passthru_count(h))
4909 return -EAGAIN;
4910 rc = hpsa_big_passthru_ioctl(h, argp);
4911 decrement_passthru_count(h);
4912 return rc;
edd16368
SC		 4913 default:
4914 return -ENOTTY;
4915 }
4916}
4917
6f039790
GKH		 4918static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
4919 u8 reset_type)
64670ac8
SC		 4920{
4921 struct CommandList *c;
4922
4923 c = cmd_alloc(h);
4924 if (!c)
4925 return -ENOMEM;
a2dac136
SC		 4926 /* fill_cmd can't fail here, no data buffer to map */
4927 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 4928 RAID_CTLR_LUNID, TYPE_MSG);
4929 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
4930 c->waiting = NULL;
4931 enqueue_cmd_and_start_io(h, c);
4932 /* Don't wait for completion, the reset won't complete. Don't free
4933 * the command either. This is the last command we will send before
4934 * re-initializing everything, so it doesn't matter and won't leak.
4935 */
4936 return 0;
4937}
4938
a2dac136 4939static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 4940 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 4941 int cmd_type)
4942{
4943 int pci_dir = XFER_NONE;
75167d2c 4944 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 4945
4946 c->cmd_type = CMD_IOCTL_PEND;
4947 c->Header.ReplyQueue = 0;
4948 if (buff != NULL && size > 0) {
4949 c->Header.SGList = 1;
4950 c->Header.SGTotal = 1;
4951 } else {
4952 c->Header.SGList = 0;
4953 c->Header.SGTotal = 0;
4954 }
4955 c->Header.Tag.lower = c->busaddr;
4956 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
4957
4958 c->Request.Type.Type = cmd_type;
4959 if (cmd_type == TYPE_CMD) {
4960 switch (cmd) {
4961 case HPSA_INQUIRY:
4962 /* are we trying to read a vital product page */
b7bb24eb 4963 if (page_code & VPD_PAGE) {
edd16368 4964 c->Request.CDB[1] = 0x01;
b7bb24eb 4965 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 4966 }
4967 c->Request.CDBLen = 6;
4968 c->Request.Type.Attribute = ATTR_SIMPLE;
4969 c->Request.Type.Direction = XFER_READ;
4970 c->Request.Timeout = 0;
4971 c->Request.CDB[0] = HPSA_INQUIRY;
4972 c->Request.CDB[4] = size & 0xFF;
4973 break;
4974 case HPSA_REPORT_LOG:
4975 case HPSA_REPORT_PHYS:
4976 /* Talking to controller so It's a physical command
4977 mode = 00 target = 0. Nothing to write.
4978 */
4979 c->Request.CDBLen = 12;
4980 c->Request.Type.Attribute = ATTR_SIMPLE;
4981 c->Request.Type.Direction = XFER_READ;
4982 c->Request.Timeout = 0;
4983 c->Request.CDB[0] = cmd;
4984 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
4985 c->Request.CDB[7] = (size >> 16) & 0xFF;
4986 c->Request.CDB[8] = (size >> 8) & 0xFF;
4987 c->Request.CDB[9] = size & 0xFF;
4988 break;
edd16368
SC		 4989 case HPSA_CACHE_FLUSH:
4990 c->Request.CDBLen = 12;
4991 c->Request.Type.Attribute = ATTR_SIMPLE;
4992 c->Request.Type.Direction = XFER_WRITE;
4993 c->Request.Timeout = 0;
4994 c->Request.CDB[0] = BMIC_WRITE;
4995 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 4996 c->Request.CDB[7] = (size >> 8) & 0xFF;
4997 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 4998 break;
4999 case TEST_UNIT_READY:
5000 c->Request.CDBLen = 6;
5001 c->Request.Type.Attribute = ATTR_SIMPLE;
5002 c->Request.Type.Direction = XFER_NONE;
5003 c->Request.Timeout = 0;
5004 break;
283b4a9b
SC		 5005 case HPSA_GET_RAID_MAP:
5006 c->Request.CDBLen = 12;
5007 c->Request.Type.Attribute = ATTR_SIMPLE;
5008 c->Request.Type.Direction = XFER_READ;
5009 c->Request.Timeout = 0;
5010 c->Request.CDB[0] = HPSA_CISS_READ;
5011 c->Request.CDB[1] = cmd;
5012 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
5013 c->Request.CDB[7] = (size >> 16) & 0xFF;
5014 c->Request.CDB[8] = (size >> 8) & 0xFF;
5015 c->Request.CDB[9] = size & 0xFF;
5016 break;
edd16368
SC		 5017 default:
5018 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
5019 BUG();
a2dac136 5020 return -1;
edd16368
SC		 5021 }
5022 } else if (cmd_type == TYPE_MSG) {
5023 switch (cmd) {
5024
5025 case HPSA_DEVICE_RESET_MSG:
5026 c->Request.CDBLen = 16;
5027 c->Request.Type.Type = 1; /* It is a MSG not a CMD */
5028 c->Request.Type.Attribute = ATTR_SIMPLE;
5029 c->Request.Type.Direction = XFER_NONE;
5030 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 5031 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
5032 c->Request.CDB[0] = cmd;
21e89afd 5033 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 5034 /* If bytes 4-7 are zero, it means reset the */
5035 /* LunID device */
5036 c->Request.CDB[4] = 0x00;
5037 c->Request.CDB[5] = 0x00;
5038 c->Request.CDB[6] = 0x00;
5039 c->Request.CDB[7] = 0x00;
75167d2c
SC		 5040 break;
5041 case HPSA_ABORT_MSG:
5042 a = buff; /* point to command to be aborted */
5043 dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
5044 a->Header.Tag.upper, a->Header.Tag.lower,
5045 c->Header.Tag.upper, c->Header.Tag.lower);
5046 c->Request.CDBLen = 16;
5047 c->Request.Type.Type = TYPE_MSG;
5048 c->Request.Type.Attribute = ATTR_SIMPLE;
5049 c->Request.Type.Direction = XFER_WRITE;
5050 c->Request.Timeout = 0; /* Don't time out */
5051 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
5052 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
5053 c->Request.CDB[2] = 0x00; /* reserved */
5054 c->Request.CDB[3] = 0x00; /* reserved */
5055 /* Tag to abort goes in CDB[4]-CDB[11] */
5056 c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
5057 c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
5058 c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
5059 c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
5060 c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
5061 c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
5062 c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
5063 c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
5064 c->Request.CDB[12] = 0x00; /* reserved */
5065 c->Request.CDB[13] = 0x00; /* reserved */
5066 c->Request.CDB[14] = 0x00; /* reserved */
5067 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 5068 break;
edd16368
SC		 5069 default:
5070 dev_warn(&h->pdev->dev, "unknown message type %d\n",
5071 cmd);
5072 BUG();
5073 }
5074 } else {
5075 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
5076 BUG();
5077 }
5078
5079 switch (c->Request.Type.Direction) {
5080 case XFER_READ:
5081 pci_dir = PCI_DMA_FROMDEVICE;
5082 break;
5083 case XFER_WRITE:
5084 pci_dir = PCI_DMA_TODEVICE;
5085 break;
5086 case XFER_NONE:
5087 pci_dir = PCI_DMA_NONE;
5088 break;
5089 default:
5090 pci_dir = PCI_DMA_BIDIRECTIONAL;
5091 }
a2dac136
SC		 5092 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
5093 return -1;
5094 return 0;
edd16368
SC		 5095}
5096
5097/*
5098 * Map (physical) PCI mem into (virtual) kernel space
5099 */
5100static void __iomem *remap_pci_mem(ulong base, ulong size)
5101{
5102 ulong page_base = ((ulong) base) & PAGE_MASK;
5103 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 5104 void __iomem *page_remapped = ioremap_nocache(page_base,
5105 page_offs + size);
edd16368
SC		 5106
5107 return page_remapped ? (page_remapped + page_offs) : NULL;
5108}
5109
5110/* Takes cmds off the submission queue and sends them to the hardware,
5111 * then puts them on the queue of cmds waiting for completion.
5112 */
5113static void start_io(struct ctlr_info *h)
5114{
5115 struct CommandList *c;
e16a33ad 5116 unsigned long flags;
edd16368 5117
e16a33ad 5118 spin_lock_irqsave(&h->lock, flags);
9e0fc764
SC		 5119 while (!list_empty(&h->reqQ)) {
5120 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 5121 /* can't do anything if fifo is full */
5122 if ((h->access.fifo_full(h))) {
396883e2 5123 h->fifo_recently_full = 1;
edd16368
SC		 5124 dev_warn(&h->pdev->dev, "fifo full\n");
5125 break;
5126 }
396883e2 5127 h->fifo_recently_full = 0;
edd16368
SC		 5128
5129 /* Get the first entry from the Request Q */
5130 removeQ(c);
5131 h->Qdepth--;
5132
edd16368
SC		 5133 /* Put job onto the completed Q */
5134 addQ(&h->cmpQ, c);
e16a33ad
MG		 5135
5136 /* Must increment commands_outstanding before unlocking
5137 * and submitting to avoid race checking for fifo full
5138 * condition.
5139 */
5140 h->commands_outstanding++;
5141 if (h->commands_outstanding > h->max_outstanding)
5142 h->max_outstanding = h->commands_outstanding;
5143
5144 /* Tell the controller execute command */
5145 spin_unlock_irqrestore(&h->lock, flags);
5146 h->access.submit_command(h, c);
5147 spin_lock_irqsave(&h->lock, flags);
edd16368 5148 }
e16a33ad 5149 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 5150}
5151
254f796b 5152static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 5153{
254f796b 5154 return h->access.command_completed(h, q);
edd16368
SC		 5155}
5156
900c5440 5157static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 5158{
5159 return h->access.intr_pending(h);
5160}
5161
5162static inline long interrupt_not_for_us(struct ctlr_info *h)
5163{
10f66018
SC		 5164 return (h->access.intr_pending(h) == 0) ||
5165 (h->interrupts_enabled == 0);
edd16368
SC		 5166}
5167
01a02ffc
SC		 5168static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
5169 u32 raw_tag)
edd16368
SC		 5170{
5171 if (unlikely(tag_index >= h->nr_cmds)) {
5172 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
5173 return 1;
5174 }
5175 return 0;
5176}
5177
5a3d16f5 5178static inline void finish_cmd(struct CommandList *c)
edd16368 5179{
e16a33ad 5180 unsigned long flags;
396883e2
SC		 5181 int io_may_be_stalled = 0;
5182 struct ctlr_info *h = c->h;
e16a33ad 5183
396883e2 5184 spin_lock_irqsave(&h->lock, flags);
edd16368 5185 removeQ(c);
396883e2
SC		 5186
5187 /*
5188 * Check for possibly stalled i/o.
5189 *
5190 * If a fifo_full condition is encountered, requests will back up
5191 * in h->reqQ. This queue is only emptied out by start_io which is
5192 * only called when a new i/o request comes in. If no i/o's are
5193 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
5194 * start_io from here if we detect such a danger.
5195 *
5196 * Normally, we shouldn't hit this case, but pounding on the
5197 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
5198 * commands_outstanding is low. We want to avoid calling
5199 * start_io from in here as much as possible, and esp. don't
5200 * want to get in a cycle where we call start_io every time
5201 * through here.
5202 */
5203 if (unlikely(h->fifo_recently_full) &&
5204 h->commands_outstanding < 5)
5205 io_may_be_stalled = 1;
5206
5207 spin_unlock_irqrestore(&h->lock, flags);
5208
e85c5974 5209 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 5210 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
5211 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 5212 complete_scsi_command(c);
edd16368
SC		 5213 else if (c->cmd_type == CMD_IOCTL_PEND)
5214 complete(c->waiting);
396883e2
SC		 5215 if (unlikely(io_may_be_stalled))
5216 start_io(h);
edd16368
SC		 5217}
5218
a104c99f
SC		 5219static inline u32 hpsa_tag_contains_index(u32 tag)
5220{
a104c99f
SC		 5221 return tag & DIRECT_LOOKUP_BIT;
5222}
5223
5224static inline u32 hpsa_tag_to_index(u32 tag)
5225{
a104c99f
SC		 5226 return tag >> DIRECT_LOOKUP_SHIFT;
5227}
5228
a9a3a273
SC		 5229
5230static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 5231{
a9a3a273
SC		 5232#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
5233#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 5234 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 5235 return tag & ~HPSA_SIMPLE_ERROR_BITS;
5236 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 5237}
5238
303932fd 5239/* process completion of an indexed ("direct lookup") command */
1d94f94d 5240static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 5241 u32 raw_tag)
5242{
5243 u32 tag_index;
5244 struct CommandList *c;
5245
5246 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 5247 if (!bad_tag(h, tag_index, raw_tag)) {
5248 c = h->cmd_pool + tag_index;
5249 finish_cmd(c);
5250 }
303932fd
DB		 5251}
5252
5253/* process completion of a non-indexed command */
1d94f94d 5254static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 5255 u32 raw_tag)
5256{
5257 u32 tag;
5258 struct CommandList *c = NULL;
e16a33ad 5259 unsigned long flags;
303932fd 5260
a9a3a273 5261 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 5262 spin_lock_irqsave(&h->lock, flags);
9e0fc764 5263 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 5264 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 5265 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 5266 finish_cmd(c);
1d94f94d 5267 return;
303932fd
DB		 5268 }
5269 }
e16a33ad 5270 spin_unlock_irqrestore(&h->lock, flags);
303932fd 5271 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 5272}
5273
64670ac8
SC		 5274/* Some controllers, like p400, will give us one interrupt
5275 * after a soft reset, even if we turned interrupts off.
5276 * Only need to check for this in the hpsa_xxx_discard_completions
5277 * functions.
5278 */
5279static int ignore_bogus_interrupt(struct ctlr_info *h)
5280{
5281 if (likely(!reset_devices))
5282 return 0;
5283
5284 if (likely(h->interrupts_enabled))
5285 return 0;
5286
5287 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
5288 "(known firmware bug.) Ignoring.\n");
5289
5290 return 1;
5291}
5292
254f796b
MG		 5293/*
5294 * Convert &h->q[x] (passed to interrupt handlers) back to h.
5295 * Relies on (h-q[x] == x) being true for x such that
5296 * 0 <= x < MAX_REPLY_QUEUES.
5297 */
5298static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 5299{
254f796b
MG		 5300 return container_of((queue - *queue), struct ctlr_info, q[0]);
5301}
5302
5303static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
5304{
5305 struct ctlr_info *h = queue_to_hba(queue);
5306 u8 q = *(u8 *) queue;
64670ac8
SC		 5307 u32 raw_tag;
5308
5309 if (ignore_bogus_interrupt(h))
5310 return IRQ_NONE;
5311
5312 if (interrupt_not_for_us(h))
5313 return IRQ_NONE;
a0c12413 5314 h->last_intr_timestamp = get_jiffies_64();
64670ac8 5315 while (interrupt_pending(h)) {
254f796b 5316 raw_tag = get_next_completion(h, q);
64670ac8 5317 while (raw_tag != FIFO_EMPTY)
254f796b 5318 raw_tag = next_command(h, q);
64670ac8 5319 }
64670ac8
SC		 5320 return IRQ_HANDLED;
5321}
5322
254f796b 5323static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 5324{
254f796b 5325 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 5326 u32 raw_tag;
254f796b 5327 u8 q = *(u8 *) queue;
64670ac8
SC		 5328
5329 if (ignore_bogus_interrupt(h))
5330 return IRQ_NONE;
5331
a0c12413 5332 h->last_intr_timestamp = get_jiffies_64();
254f796b 5333 raw_tag = get_next_completion(h, q);
64670ac8 5334 while (raw_tag != FIFO_EMPTY)
254f796b 5335 raw_tag = next_command(h, q);
64670ac8
SC		 5336 return IRQ_HANDLED;
5337}
5338
254f796b 5339static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 5340{
254f796b 5341 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 5342 u32 raw_tag;
254f796b 5343 u8 q = *(u8 *) queue;
edd16368
SC		 5344
5345 if (interrupt_not_for_us(h))
5346 return IRQ_NONE;
a0c12413 5347 h->last_intr_timestamp = get_jiffies_64();
10f66018 5348 while (interrupt_pending(h)) {
254f796b 5349 raw_tag = get_next_completion(h, q);
10f66018 5350 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5351 if (likely(hpsa_tag_contains_index(raw_tag)))
5352 process_indexed_cmd(h, raw_tag);
10f66018 5353 else
1d94f94d 5354 process_nonindexed_cmd(h, raw_tag);
254f796b 5355 raw_tag = next_command(h, q);
10f66018
SC		 5356 }
5357 }
10f66018
SC		 5358 return IRQ_HANDLED;
5359}
5360
254f796b 5361static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5362{
254f796b 5363 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5364 u32 raw_tag;
254f796b 5365 u8 q = *(u8 *) queue;
10f66018 5366
a0c12413 5367 h->last_intr_timestamp = get_jiffies_64();
254f796b 5368 raw_tag = get_next_completion(h, q);
303932fd 5369 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5370 if (likely(hpsa_tag_contains_index(raw_tag)))
5371 process_indexed_cmd(h, raw_tag);
303932fd 5372 else
1d94f94d 5373 process_nonindexed_cmd(h, raw_tag);
254f796b 5374 raw_tag = next_command(h, q);
edd16368 5375 }
edd16368
SC		 5376 return IRQ_HANDLED;
5377}
5378
a9a3a273
SC		 5379/* Send a message CDB to the firmware. Careful, this only works
5380 * in simple mode, not performant mode due to the tag lookup.
5381 * We only ever use this immediately after a controller reset.
5382 */
6f039790
GKH		 5383static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5384 unsigned char type)
edd16368
SC		 5385{
5386 struct Command {
5387 struct CommandListHeader CommandHeader;
5388 struct RequestBlock Request;
5389 struct ErrDescriptor ErrorDescriptor;
5390 };
5391 struct Command *cmd;
5392 static const size_t cmd_sz = sizeof(*cmd) +
5393 sizeof(cmd->ErrorDescriptor);
5394 dma_addr_t paddr64;
5395 uint32_t paddr32, tag;
5396 void __iomem *vaddr;
5397 int i, err;
5398
5399 vaddr = pci_ioremap_bar(pdev, 0);
5400 if (vaddr == NULL)
5401 return -ENOMEM;
5402
5403 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5404 * CCISS commands, so they must be allocated from the lower 4GiB of
5405 * memory.
5406 */
5407 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5408 if (err) {
5409 iounmap(vaddr);
5410 return -ENOMEM;
5411 }
5412
5413 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5414 if (cmd == NULL) {
5415 iounmap(vaddr);
5416 return -ENOMEM;
5417 }
5418
5419 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5420 * although there's no guarantee, we assume that the address is at
5421 * least 4-byte aligned (most likely, it's page-aligned).
5422 */
5423 paddr32 = paddr64;
5424
5425 cmd->CommandHeader.ReplyQueue = 0;
5426 cmd->CommandHeader.SGList = 0;
5427 cmd->CommandHeader.SGTotal = 0;
5428 cmd->CommandHeader.Tag.lower = paddr32;
5429 cmd->CommandHeader.Tag.upper = 0;
5430 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5431
5432 cmd->Request.CDBLen = 16;
5433 cmd->Request.Type.Type = TYPE_MSG;
5434 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
5435 cmd->Request.Type.Direction = XFER_NONE;
5436 cmd->Request.Timeout = 0; /* Don't time out */
5437 cmd->Request.CDB[0] = opcode;
5438 cmd->Request.CDB[1] = type;
5439 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
5440 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
5441 cmd->ErrorDescriptor.Addr.upper = 0;
5442 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
5443
5444 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
5445
5446 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5447 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 5448 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 5449 break;
5450 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5451 }
5452
5453 iounmap(vaddr);
5454
5455 /* we leak the DMA buffer here ... no choice since the controller could
5456 * still complete the command.
5457 */
5458 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5459 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5460 opcode, type);
5461 return -ETIMEDOUT;
5462 }
5463
5464 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5465
5466 if (tag & HPSA_ERROR_BIT) {
5467 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5468 opcode, type);
5469 return -EIO;
5470 }
5471
5472 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5473 opcode, type);
5474 return 0;
5475}
5476
edd16368
SC		 5477#define hpsa_noop(p) hpsa_message(p, 3, 0)
5478
1df8552a 5479static int hpsa_controller_hard_reset(struct pci_dev *pdev,
cf0b08d0 5480 void * __iomem vaddr, u32 use_doorbell)
1df8552a
SC		 5481{
5482 u16 pmcsr;
5483 int pos;
5484
5485 if (use_doorbell) {
5486 /* For everything after the P600, the PCI power state method
5487 * of resetting the controller doesn't work, so we have this
5488 * other way using the doorbell register.
5489 */
5490 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5491 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239
SC		 5492
5493 /* PMC hardware guys tell us we need a 5 second delay after
5494 * doorbell reset and before any attempt to talk to the board
5495 * at all to ensure that this actually works and doesn't fall
5496 * over in some weird corner cases.
5497 */
5498 msleep(5000);
1df8552a
SC		 5499 } else { /* Try to do it the PCI power state way */
5500
5501 /* Quoting from the Open CISS Specification: "The Power
5502 * Management Control/Status Register (CSR) controls the power
5503 * state of the device. The normal operating state is D0,
5504 * CSR=00h. The software off state is D3, CSR=03h. To reset
5505 * the controller, place the interface device in D3 then to D0,
5506 * this causes a secondary PCI reset which will reset the
5507 * controller." */
5508
5509 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
5510 if (pos == 0) {
5511 dev_err(&pdev->dev,
5512 "hpsa_reset_controller: "
5513 "PCI PM not supported\n");
5514 return -ENODEV;
5515 }
5516 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
5517 /* enter the D3hot power management state */
5518 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
5519 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5520 pmcsr |= PCI_D3hot;
5521 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
5522
5523 msleep(500);
5524
5525 /* enter the D0 power management state */
5526 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5527 pmcsr |= PCI_D0;
5528 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 5529
5530 /*
5531 * The P600 requires a small delay when changing states.
5532 * Otherwise we may think the board did not reset and we bail.
5533 * This for kdump only and is particular to the P600.
5534 */
5535 msleep(500);
1df8552a
SC		 5536 }
5537 return 0;
5538}
5539
6f039790 5540static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5541{
5542 memset(driver_version, 0, len);
f79cfec6 5543 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5544}
5545
6f039790 5546static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5547{
5548 char *driver_version;
5549 int i, size = sizeof(cfgtable->driver_version);
5550
5551 driver_version = kmalloc(size, GFP_KERNEL);
5552 if (!driver_version)
5553 return -ENOMEM;
5554
5555 init_driver_version(driver_version, size);
5556 for (i = 0; i < size; i++)
5557 writeb(driver_version[i], &cfgtable->driver_version[i]);
5558 kfree(driver_version);
5559 return 0;
5560}
5561
6f039790
GKH		 5562static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5563 unsigned char *driver_ver)
580ada3c
SC		 5564{
5565 int i;
5566
5567 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5568 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5569}
5570
6f039790 5571static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5572{
5573
5574 char *driver_ver, *old_driver_ver;
5575 int rc, size = sizeof(cfgtable->driver_version);
5576
5577 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5578 if (!old_driver_ver)
5579 return -ENOMEM;
5580 driver_ver = old_driver_ver + size;
5581
5582 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5583 * should have been changed, otherwise we know the reset failed.
5584 */
5585 init_driver_version(old_driver_ver, size);
5586 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5587 rc = !memcmp(driver_ver, old_driver_ver, size);
5588 kfree(old_driver_ver);
5589 return rc;
5590}
edd16368 5591/* This does a hard reset of the controller using PCI power management
1df8552a 5592 * states or the using the doorbell register.
edd16368 5593 */
6f039790 5594static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5595{
1df8552a
SC		 5596 u64 cfg_offset;
5597 u32 cfg_base_addr;
5598 u64 cfg_base_addr_index;
5599 void __iomem *vaddr;
5600 unsigned long paddr;
580ada3c 5601 u32 misc_fw_support;
270d05de 5602 int rc;
1df8552a 5603 struct CfgTable __iomem *cfgtable;
cf0b08d0 5604 u32 use_doorbell;
18867659 5605 u32 board_id;
270d05de 5606 u16 command_register;
edd16368 5607
1df8552a
SC		 5608 /* For controllers as old as the P600, this is very nearly
5609 * the same thing as
edd16368
SC		 5610 *
5611 * pci_save_state(pci_dev);
5612 * pci_set_power_state(pci_dev, PCI_D3hot);
5613 * pci_set_power_state(pci_dev, PCI_D0);
5614 * pci_restore_state(pci_dev);
5615 *
1df8552a
SC		 5616 * For controllers newer than the P600, the pci power state
5617 * method of resetting doesn't work so we have another way
5618 * using the doorbell register.
edd16368 5619 */
18867659 5620
25c1e56a 5621 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 5622 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 5623 dev_warn(&pdev->dev, "Not resetting device.\n");
5624 return -ENODEV;
5625 }
46380786
SC		 5626
5627 /* if controller is soft- but not hard resettable... */
5628 if (!ctlr_is_hard_resettable(board_id))
5629 return -ENOTSUPP; /* try soft reset later. */
18867659 5630
270d05de
SC		 5631 /* Save the PCI command register */
5632 pci_read_config_word(pdev, 4, &command_register);
5633 /* Turn the board off. This is so that later pci_restore_state()
5634 * won't turn the board on before the rest of config space is ready.
5635 */
5636 pci_disable_device(pdev);
5637 pci_save_state(pdev);
edd16368 5638
1df8552a
SC		 5639 /* find the first memory BAR, so we can find the cfg table */
5640 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5641 if (rc)
5642 return rc;
5643 vaddr = remap_pci_mem(paddr, 0x250);
5644 if (!vaddr)
5645 return -ENOMEM;
edd16368 5646
1df8552a
SC		 5647 /* find cfgtable in order to check if reset via doorbell is supported */
5648 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5649 &cfg_base_addr_index, &cfg_offset);
5650 if (rc)
5651 goto unmap_vaddr;
5652 cfgtable = remap_pci_mem(pci_resource_start(pdev,
5653 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
5654 if (!cfgtable) {
5655 rc = -ENOMEM;
5656 goto unmap_vaddr;
5657 }
580ada3c
SC		 5658 rc = write_driver_ver_to_cfgtable(cfgtable);
5659 if (rc)
5660 goto unmap_vaddr;
edd16368 5661
cf0b08d0
SC		 5662 /* If reset via doorbell register is supported, use that.
5663 * There are two such methods. Favor the newest method.
5664 */
1df8552a 5665 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 5666 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
5667 if (use_doorbell) {
5668 use_doorbell = DOORBELL_CTLR_RESET2;
5669 } else {
5670 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
5671 if (use_doorbell) {
fba63097
MM		 5672 dev_warn(&pdev->dev, "Soft reset not supported. "
5673 "Firmware update is required.\n");
64670ac8 5674 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 5675 goto unmap_cfgtable;
5676 }
5677 }
edd16368 5678
1df8552a
SC		 5679 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
5680 if (rc)
5681 goto unmap_cfgtable;
edd16368 5682
270d05de
SC		 5683 pci_restore_state(pdev);
5684 rc = pci_enable_device(pdev);
5685 if (rc) {
5686 dev_warn(&pdev->dev, "failed to enable device.\n");
5687 goto unmap_cfgtable;
edd16368 5688 }
270d05de 5689 pci_write_config_word(pdev, 4, command_register);
edd16368 5690
1df8552a
SC		 5691 /* Some devices (notably the HP Smart Array 5i Controller)
5692 need a little pause here */
5693 msleep(HPSA_POST_RESET_PAUSE_MSECS);
5694
fe5389c8
SC		 5695 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
5696 if (rc) {
5697 dev_warn(&pdev->dev,
64670ac8
SC		 5698 "failed waiting for board to become ready "
5699 "after hard reset\n");
fe5389c8
SC		 5700 goto unmap_cfgtable;
5701 }
fe5389c8 5702
580ada3c
SC		 5703 rc = controller_reset_failed(vaddr);
5704 if (rc < 0)
5705 goto unmap_cfgtable;
5706 if (rc) {
64670ac8
SC		 5707 dev_warn(&pdev->dev, "Unable to successfully reset "
5708 "controller. Will try soft reset.\n");
5709 rc = -ENOTSUPP;
580ada3c 5710 } else {
64670ac8 5711 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 5712 }
5713
5714unmap_cfgtable:
5715 iounmap(cfgtable);
5716
5717unmap_vaddr:
5718 iounmap(vaddr);
5719 return rc;
edd16368
SC		 5720}
5721
5722/*
5723 * We cannot read the structure directly, for portability we must use
5724 * the io functions.
5725 * This is for debug only.
5726 */
edd16368
SC		 5727static void print_cfg_table(struct device *dev, struct CfgTable *tb)
5728{
58f8665c 5729#ifdef HPSA_DEBUG
edd16368
SC		 5730 int i;
5731 char temp_name[17];
5732
5733 dev_info(dev, "Controller Configuration information\n");
5734 dev_info(dev, "------------------------------------\n");
5735 for (i = 0; i < 4; i++)
5736 temp_name[i] = readb(&(tb->Signature[i]));
5737 temp_name[4] = '\0';
5738 dev_info(dev, " Signature = %s\n", temp_name);
5739 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
5740 dev_info(dev, " Transport methods supported = 0x%x\n",
5741 readl(&(tb->TransportSupport)));
5742 dev_info(dev, " Transport methods active = 0x%x\n",
5743 readl(&(tb->TransportActive)));
5744 dev_info(dev, " Requested transport Method = 0x%x\n",
5745 readl(&(tb->HostWrite.TransportRequest)));
5746 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
5747 readl(&(tb->HostWrite.CoalIntDelay)));
5748 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
5749 readl(&(tb->HostWrite.CoalIntCount)));
5750 dev_info(dev, " Max outstanding commands = 0x%d\n",
5751 readl(&(tb->CmdsOutMax)));
5752 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
5753 for (i = 0; i < 16; i++)
5754 temp_name[i] = readb(&(tb->ServerName[i]));
5755 temp_name[16] = '\0';
5756 dev_info(dev, " Server Name = %s\n", temp_name);
5757 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
5758 readl(&(tb->HeartBeat)));
edd16368 5759#endif /* HPSA_DEBUG */
58f8665c 5760}
edd16368
SC		 5761
5762static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
5763{
5764 int i, offset, mem_type, bar_type;
5765
5766 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
5767 return 0;
5768 offset = 0;
5769 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5770 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
5771 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
5772 offset += 4;
5773 else {
5774 mem_type = pci_resource_flags(pdev, i) &
5775 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
5776 switch (mem_type) {
5777 case PCI_BASE_ADDRESS_MEM_TYPE_32:
5778 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
5779 offset += 4; /* 32 bit */
5780 break;
5781 case PCI_BASE_ADDRESS_MEM_TYPE_64:
5782 offset += 8;
5783 break;
5784 default: /* reserved in PCI 2.2 */
5785 dev_warn(&pdev->dev,
5786 "base address is invalid\n");
5787 return -1;
5788 break;
5789 }
5790 }
5791 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
5792 return i + 1;
5793 }
5794 return -1;
5795}
5796
5797/* If MSI/MSI-X is supported by the kernel we will try to enable it on
5798 * controllers that are capable. If not, we use IO-APIC mode.
5799 */
5800
6f039790 5801static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 5802{
5803#ifdef CONFIG_PCI_MSI
254f796b
MG		 5804 int err, i;
5805 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
5806
5807 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
5808 hpsa_msix_entries[i].vector = 0;
5809 hpsa_msix_entries[i].entry = i;
5810 }
edd16368
SC		 5811
5812 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 5813 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
5814 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 5815 goto default_int_mode;
55c06c71
SC		 5816 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
5817 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 5818 h->msix_vector = MAX_REPLY_QUEUES;
254f796b 5819 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
eee0f03a 5820 h->msix_vector);
edd16368 5821 if (err > 0) {
55c06c71 5822 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 5823 "available\n", err);
eee0f03a
HR		 5824 h->msix_vector = err;
5825 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
5826 h->msix_vector);
5827 }
5828 if (!err) {
5829 for (i = 0; i < h->msix_vector; i++)
5830 h->intr[i] = hpsa_msix_entries[i].vector;
5831 return;
edd16368 5832 } else {
55c06c71 5833 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
edd16368 5834 err);
eee0f03a 5835 h->msix_vector = 0;
edd16368
SC		 5836 goto default_int_mode;
5837 }
5838 }
55c06c71
SC		 5839 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
5840 dev_info(&h->pdev->dev, "MSI\n");
5841 if (!pci_enable_msi(h->pdev))
edd16368
SC		 5842 h->msi_vector = 1;
5843 else
55c06c71 5844 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 5845 }
5846default_int_mode:
5847#endif /* CONFIG_PCI_MSI */
5848 /* if we get here we're going to use the default interrupt mode */
a9a3a273 5849 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 5850}
5851
6f039790 5852static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 5853{
5854 int i;
5855 u32 subsystem_vendor_id, subsystem_device_id;
5856
5857 subsystem_vendor_id = pdev->subsystem_vendor;
5858 subsystem_device_id = pdev->subsystem_device;
5859 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
5860 subsystem_vendor_id;
5861
5862 for (i = 0; i < ARRAY_SIZE(products); i++)
5863 if (*board_id == products[i].board_id)
5864 return i;
5865
6798cc0a
SC		 5866 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
5867 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
5868 !hpsa_allow_any) {
e5c880d1
SC		 5869 dev_warn(&pdev->dev, "unrecognized board ID: "
5870 "0x%08x, ignoring.\n", *board_id);
5871 return -ENODEV;
5872 }
5873 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
5874}
5875
6f039790
GKH		 5876static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
5877 unsigned long *memory_bar)
3a7774ce
SC		 5878{
5879 int i;
5880
5881 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 5882 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 5883 /* addressing mode bits already removed */
12d2cd47
SC		 5884 *memory_bar = pci_resource_start(pdev, i);
5885 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 5886 *memory_bar);
5887 return 0;
5888 }
12d2cd47 5889 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 5890 return -ENODEV;
5891}
5892
6f039790
GKH		 5893static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
5894 int wait_for_ready)
2c4c8c8b 5895{
fe5389c8 5896 int i, iterations;
2c4c8c8b 5897 u32 scratchpad;
fe5389c8
SC		 5898 if (wait_for_ready)
5899 iterations = HPSA_BOARD_READY_ITERATIONS;
5900 else
5901 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 5902
fe5389c8
SC		 5903 for (i = 0; i < iterations; i++) {
5904 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
5905 if (wait_for_ready) {
5906 if (scratchpad == HPSA_FIRMWARE_READY)
5907 return 0;
5908 } else {
5909 if (scratchpad != HPSA_FIRMWARE_READY)
5910 return 0;
5911 }
2c4c8c8b
SC		 5912 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
5913 }
fe5389c8 5914 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 5915 return -ENODEV;
5916}
5917
6f039790
GKH		 5918static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
5919 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
5920 u64 *cfg_offset)
a51fd47f
SC		 5921{
5922 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
5923 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
5924 *cfg_base_addr &= (u32) 0x0000ffff;
5925 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
5926 if (*cfg_base_addr_index == -1) {
5927 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
5928 return -ENODEV;
5929 }
5930 return 0;
5931}
5932
6f039790 5933static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 5934{
01a02ffc
SC		 5935 u64 cfg_offset;
5936 u32 cfg_base_addr;
5937 u64 cfg_base_addr_index;
303932fd 5938 u32 trans_offset;
a51fd47f 5939 int rc;
77c4495c 5940
a51fd47f
SC		 5941 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
5942 &cfg_base_addr_index, &cfg_offset);
5943 if (rc)
5944 return rc;
77c4495c 5945 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 5946 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 5947 if (!h->cfgtable)
5948 return -ENOMEM;
580ada3c
SC		 5949 rc = write_driver_ver_to_cfgtable(h->cfgtable);
5950 if (rc)
5951 return rc;
77c4495c 5952 /* Find performant mode table. */
a51fd47f 5953 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 5954 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
5955 cfg_base_addr_index)+cfg_offset+trans_offset,
5956 sizeof(*h->transtable));
5957 if (!h->transtable)
5958 return -ENOMEM;
5959 return 0;
5960}
5961
6f039790 5962static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 5963{
5964 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 5965
5966 /* Limit commands in memory limited kdump scenario. */
5967 if (reset_devices && h->max_commands > 32)
5968 h->max_commands = 32;
5969
cba3d38b
SC		 5970 if (h->max_commands < 16) {
5971 dev_warn(&h->pdev->dev, "Controller reports "
5972 "max supported commands of %d, an obvious lie. "
5973 "Using 16. Ensure that firmware is up to date.\n",
5974 h->max_commands);
5975 h->max_commands = 16;
5976 }
5977}
5978
b93d7536
SC		 5979/* Interrogate the hardware for some limits:
5980 * max commands, max SG elements without chaining, and with chaining,
5981 * SG chain block size, etc.
5982 */
6f039790 5983static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 5984{
cba3d38b 5985 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 5986 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
5987 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 5988 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 5989 /*
5990 * Limit in-command s/g elements to 32 save dma'able memory.
5991 * Howvever spec says if 0, use 31
5992 */
5993 h->max_cmd_sg_entries = 31;
5994 if (h->maxsgentries > 512) {
5995 h->max_cmd_sg_entries = 32;
5996 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
5997 h->maxsgentries--; /* save one for chain pointer */
5998 } else {
5999 h->maxsgentries = 31; /* default to traditional values */
6000 h->chainsize = 0;
6001 }
75167d2c
SC		 6002
6003 /* Find out what task management functions are supported and cache */
6004 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 6005 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
6006 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
6007 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
6008 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 6009}
6010
76c46e49
SC		 6011static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
6012{
0fc9fd40 6013 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 6014 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
6015 return false;
6016 }
6017 return true;
6018}
6019
97a5e98c 6020static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 6021{
97a5e98c 6022 u32 driver_support;
f7c39101 6023
28e13446
SC		 6024#ifdef CONFIG_X86
6025 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
97a5e98c
SC		 6026 driver_support = readl(&(h->cfgtable->driver_support));
6027 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 6028#endif
28e13446
SC		 6029 driver_support |= ENABLE_UNIT_ATTN;
6030 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 6031}
6032
3d0eab67
SC		 6033/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
6034 * in a prefetch beyond physical memory.
6035 */
6036static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
6037{
6038 u32 dma_prefetch;
6039
6040 if (h->board_id != 0x3225103C)
6041 return;
6042 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
6043 dma_prefetch |= 0x8000;
6044 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
6045}
6046
76438d08
SC		 6047static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
6048{
6049 int i;
6050 u32 doorbell_value;
6051 unsigned long flags;
6052 /* wait until the clear_event_notify bit 6 is cleared by controller. */
6053 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6054 spin_lock_irqsave(&h->lock, flags);
6055 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6056 spin_unlock_irqrestore(&h->lock, flags);
6057 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
6058 break;
6059 /* delay and try again */
6060 msleep(20);
6061 }
6062}
6063
6f039790 6064static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 6065{
6066 int i;
6eaf46fd
SC		 6067 u32 doorbell_value;
6068 unsigned long flags;
eb6b2ae9
SC		 6069
6070 /* under certain very rare conditions, this can take awhile.
6071 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
6072 * as we enter this code.)
6073 */
6074 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 6075 spin_lock_irqsave(&h->lock, flags);
6076 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
6077 spin_unlock_irqrestore(&h->lock, flags);
382be668 6078 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 6079 break;
6080 /* delay and try again */
60d3f5b0 6081 usleep_range(10000, 20000);
eb6b2ae9 6082 }
3f4336f3
SC		 6083}
6084
6f039790 6085static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 6086{
6087 u32 trans_support;
6088
6089 trans_support = readl(&(h->cfgtable->TransportSupport));
6090 if (!(trans_support & SIMPLE_MODE))
6091 return -ENOTSUPP;
6092
6093 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 6094
3f4336f3
SC		 6095 /* Update the field, and then ring the doorbell */
6096 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 6097 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 6098 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6099 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 6100 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 6101 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
6102 goto error;
960a30e7 6103 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 6104 return 0;
283b4a9b
SC		 6105error:
6106 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
6107 return -ENODEV;
eb6b2ae9
SC		 6108}
6109
6f039790 6110static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 6111{
eb6b2ae9 6112 int prod_index, err;
edd16368 6113
e5c880d1
SC		 6114 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
6115 if (prod_index < 0)
6116 return -ENODEV;
6117 h->product_name = products[prod_index].product_name;
6118 h->access = *(products[prod_index].access);
edd16368 6119
e5a44df8
MG		 6120 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
6121 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
6122
55c06c71 6123 err = pci_enable_device(h->pdev);
edd16368 6124 if (err) {
55c06c71 6125 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 6126 return err;
6127 }
6128
5cb460a6
SC		 6129 /* Enable bus mastering (pci_disable_device may disable this) */
6130 pci_set_master(h->pdev);
6131
f79cfec6 6132 err = pci_request_regions(h->pdev, HPSA);
edd16368 6133 if (err) {
55c06c71
SC		 6134 dev_err(&h->pdev->dev,
6135 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 6136 return err;
6137 }
6b3f4c52 6138 hpsa_interrupt_mode(h);
12d2cd47 6139 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 6140 if (err)
edd16368 6141 goto err_out_free_res;
edd16368 6142 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 6143 if (!h->vaddr) {
6144 err = -ENOMEM;
6145 goto err_out_free_res;
6146 }
fe5389c8 6147 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 6148 if (err)
edd16368 6149 goto err_out_free_res;
77c4495c
SC		 6150 err = hpsa_find_cfgtables(h);
6151 if (err)
edd16368 6152 goto err_out_free_res;
b93d7536 6153 hpsa_find_board_params(h);
edd16368 6154
76c46e49 6155 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 6156 err = -ENODEV;
6157 goto err_out_free_res;
6158 }
97a5e98c 6159 hpsa_set_driver_support_bits(h);
3d0eab67 6160 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 6161 err = hpsa_enter_simple_mode(h);
6162 if (err)
edd16368 6163 goto err_out_free_res;
edd16368
SC		 6164 return 0;
6165
6166err_out_free_res:
204892e9
SC		 6167 if (h->transtable)
6168 iounmap(h->transtable);
6169 if (h->cfgtable)
6170 iounmap(h->cfgtable);
6171 if (h->vaddr)
6172 iounmap(h->vaddr);
f0bd0b68 6173 pci_disable_device(h->pdev);
55c06c71 6174 pci_release_regions(h->pdev);
edd16368
SC		 6175 return err;
6176}
6177
6f039790 6178static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 6179{
6180 int rc;
6181
6182#define HBA_INQUIRY_BYTE_COUNT 64
6183 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
6184 if (!h->hba_inquiry_data)
6185 return;
6186 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
6187 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
6188 if (rc != 0) {
6189 kfree(h->hba_inquiry_data);
6190 h->hba_inquiry_data = NULL;
6191 }
6192}
6193
6f039790 6194static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 6195{
1df8552a 6196 int rc, i;
4c2a8c40
SC		 6197
6198 if (!reset_devices)
6199 return 0;
6200
1df8552a
SC		 6201 /* Reset the controller with a PCI power-cycle or via doorbell */
6202 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 6203
1df8552a
SC		 6204 /* -ENOTSUPP here means we cannot reset the controller
6205 * but it's already (and still) up and running in
18867659
SC		 6206 * "performant mode". Or, it might be 640x, which can't reset
6207 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a
SC		 6208 */
6209 if (rc == -ENOTSUPP)
64670ac8 6210 return rc; /* just try to do the kdump anyhow. */
1df8552a
SC		 6211 if (rc)
6212 return -ENODEV;
4c2a8c40
SC		 6213
6214 /* Now try to get the controller to respond to a no-op */
2b870cb3 6215 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 6216 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
6217 if (hpsa_noop(pdev) == 0)
6218 break;
6219 else
6220 dev_warn(&pdev->dev, "no-op failed%s\n",
6221 (i < 11 ? "; re-trying" : ""));
6222 }
6223 return 0;
6224}
6225
6f039790 6226static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 6227{
6228 h->cmd_pool_bits = kzalloc(
6229 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
6230 sizeof(unsigned long), GFP_KERNEL);
6231 h->cmd_pool = pci_alloc_consistent(h->pdev,
6232 h->nr_cmds * sizeof(*h->cmd_pool),
6233 &(h->cmd_pool_dhandle));
6234 h->errinfo_pool = pci_alloc_consistent(h->pdev,
6235 h->nr_cmds * sizeof(*h->errinfo_pool),
6236 &(h->errinfo_pool_dhandle));
6237 if ((h->cmd_pool_bits == NULL)
6238 || (h->cmd_pool == NULL)
6239 || (h->errinfo_pool == NULL)) {
6240 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
6241 return -ENOMEM;
6242 }
6243 return 0;
6244}
6245
6246static void hpsa_free_cmd_pool(struct ctlr_info *h)
6247{
6248 kfree(h->cmd_pool_bits);
6249 if (h->cmd_pool)
6250 pci_free_consistent(h->pdev,
6251 h->nr_cmds * sizeof(struct CommandList),
6252 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 6253 if (h->ioaccel2_cmd_pool)
6254 pci_free_consistent(h->pdev,
6255 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6256 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 6257 if (h->errinfo_pool)
6258 pci_free_consistent(h->pdev,
6259 h->nr_cmds * sizeof(struct ErrorInfo),
6260 h->errinfo_pool,
6261 h->errinfo_pool_dhandle);
e1f7de0c
MG		 6262 if (h->ioaccel_cmd_pool)
6263 pci_free_consistent(h->pdev,
6264 h->nr_cmds * sizeof(struct io_accel1_cmd),
6265 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 6266}
6267
0ae01a32
SC		 6268static int hpsa_request_irq(struct ctlr_info *h,
6269 irqreturn_t (*msixhandler)(int, void *),
6270 irqreturn_t (*intxhandler)(int, void *))
6271{
254f796b 6272 int rc, i;
0ae01a32 6273
254f796b
MG		 6274 /*
6275 * initialize h->q[x] = x so that interrupt handlers know which
6276 * queue to process.
6277 */
6278 for (i = 0; i < MAX_REPLY_QUEUES; i++)
6279 h->q[i] = (u8) i;
6280
eee0f03a 6281 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 6282 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 6283 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 6284 rc = request_irq(h->intr[i], msixhandler,
6285 0, h->devname,
6286 &h->q[i]);
6287 } else {
6288 /* Use single reply pool */
eee0f03a 6289 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 6290 rc = request_irq(h->intr[h->intr_mode],
6291 msixhandler, 0, h->devname,
6292 &h->q[h->intr_mode]);
6293 } else {
6294 rc = request_irq(h->intr[h->intr_mode],
6295 intxhandler, IRQF_SHARED, h->devname,
6296 &h->q[h->intr_mode]);
6297 }
6298 }
0ae01a32
SC		 6299 if (rc) {
6300 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
6301 h->intr[h->intr_mode], h->devname);
6302 return -ENODEV;
6303 }
6304 return 0;
6305}
6306
6f039790 6307static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 6308{
6309 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
6310 HPSA_RESET_TYPE_CONTROLLER)) {
6311 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
6312 return -EIO;
6313 }
6314
6315 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
6316 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
6317 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
6318 return -1;
6319 }
6320
6321 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
6322 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
6323 dev_warn(&h->pdev->dev, "Board failed to become ready "
6324 "after soft reset.\n");
6325 return -1;
6326 }
6327
6328 return 0;
6329}
6330
254f796b
MG		 6331static void free_irqs(struct ctlr_info *h)
6332{
6333 int i;
6334
6335 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
6336 /* Single reply queue, only one irq to free */
6337 i = h->intr_mode;
6338 free_irq(h->intr[i], &h->q[i]);
6339 return;
6340 }
6341
eee0f03a 6342 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 6343 free_irq(h->intr[i], &h->q[i]);
6344}
6345
0097f0f4 6346static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 6347{
254f796b 6348 free_irqs(h);
64670ac8 6349#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6350 if (h->msix_vector) {
6351 if (h->pdev->msix_enabled)
6352 pci_disable_msix(h->pdev);
6353 } else if (h->msi_vector) {
6354 if (h->pdev->msi_enabled)
6355 pci_disable_msi(h->pdev);
6356 }
64670ac8 6357#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6358}
6359
6360static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6361{
6362 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6363 hpsa_free_sg_chain_blocks(h);
6364 hpsa_free_cmd_pool(h);
e1f7de0c 6365 kfree(h->ioaccel1_blockFetchTable);
64670ac8
SC		 6366 kfree(h->blockFetchTable);
6367 pci_free_consistent(h->pdev, h->reply_pool_size,
6368 h->reply_pool, h->reply_pool_dhandle);
6369 if (h->vaddr)
6370 iounmap(h->vaddr);
6371 if (h->transtable)
6372 iounmap(h->transtable);
6373 if (h->cfgtable)
6374 iounmap(h->cfgtable);
6375 pci_release_regions(h->pdev);
6376 kfree(h);
6377}
6378
a0c12413
SC		 6379/* Called when controller lockup detected. */
6380static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
6381{
6382 struct CommandList *c = NULL;
6383
6384 assert_spin_locked(&h->lock);
6385 /* Mark all outstanding commands as failed and complete them. */
6386 while (!list_empty(list)) {
6387 c = list_entry(list->next, struct CommandList, list);
6388 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 6389 finish_cmd(c);
a0c12413
SC		 6390 }
6391}
6392
6393static void controller_lockup_detected(struct ctlr_info *h)
6394{
6395 unsigned long flags;
6396
a0c12413
SC		 6397 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6398 spin_lock_irqsave(&h->lock, flags);
6399 h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6400 spin_unlock_irqrestore(&h->lock, flags);
6401 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
6402 h->lockup_detected);
6403 pci_disable_device(h->pdev);
6404 spin_lock_irqsave(&h->lock, flags);
6405 fail_all_cmds_on_list(h, &h->cmpQ);
6406 fail_all_cmds_on_list(h, &h->reqQ);
6407 spin_unlock_irqrestore(&h->lock, flags);
6408}
6409
a0c12413
SC		 6410static void detect_controller_lockup(struct ctlr_info *h)
6411{
6412 u64 now;
6413 u32 heartbeat;
6414 unsigned long flags;
6415
a0c12413
SC		 6416 now = get_jiffies_64();
6417 /* If we've received an interrupt recently, we're ok. */
6418 if (time_after64(h->last_intr_timestamp +
e85c5974 6419 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6420 return;
6421
6422 /*
6423 * If we've already checked the heartbeat recently, we're ok.
6424 * This could happen if someone sends us a signal. We
6425 * otherwise don't care about signals in this thread.
6426 */
6427 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6428 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6429 return;
6430
6431 /* If heartbeat has not changed since we last looked, we're not ok. */
6432 spin_lock_irqsave(&h->lock, flags);
6433 heartbeat = readl(&h->cfgtable->HeartBeat);
6434 spin_unlock_irqrestore(&h->lock, flags);
6435 if (h->last_heartbeat == heartbeat) {
6436 controller_lockup_detected(h);
6437 return;
6438 }
6439
6440 /* We're ok. */
6441 h->last_heartbeat = heartbeat;
6442 h->last_heartbeat_timestamp = now;
6443}
6444
76438d08
SC		 6445static int hpsa_kickoff_rescan(struct ctlr_info *h)
6446{
6447 int i;
6448 char *event_type;
6449
e863d68e
ST		 6450 /* Clear the driver-requested rescan flag */
6451 h->drv_req_rescan = 0;
6452
76438d08 6453 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6454 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6455 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6456 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6457 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6458
6459 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6460 event_type = "state change";
6461 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6462 event_type = "configuration change";
6463 /* Stop sending new RAID offload reqs via the IO accelerator */
6464 scsi_block_requests(h->scsi_host);
6465 for (i = 0; i < h->ndevices; i++)
6466 h->dev[i]->offload_enabled = 0;
23100dd9 6467 hpsa_drain_accel_commands(h);
76438d08
SC		 6468 /* Set 'accelerator path config change' bit */
6469 dev_warn(&h->pdev->dev,
6470 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6471 h->events, event_type);
6472 writel(h->events, &(h->cfgtable->clear_event_notify));
6473 /* Set the "clear event notify field update" bit 6 */
6474 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6475 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6476 hpsa_wait_for_clear_event_notify_ack(h);
6477 scsi_unblock_requests(h->scsi_host);
6478 } else {
6479 /* Acknowledge controller notification events. */
6480 writel(h->events, &(h->cfgtable->clear_event_notify));
6481 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6482 hpsa_wait_for_clear_event_notify_ack(h);
6483#if 0
6484 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6485 hpsa_wait_for_mode_change_ack(h);
6486#endif
6487 }
6488
6489 /* Something in the device list may have changed to trigger
6490 * the event, so do a rescan.
6491 */
6492 hpsa_scan_start(h->scsi_host);
6493 /* release reference taken on scsi host in check_controller_events */
6494 scsi_host_put(h->scsi_host);
6495 return 0;
6496}
6497
6498/* Check a register on the controller to see if there are configuration
6499 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 6500 * we should rescan the controller for devices.
6501 * Also check flag for driver-initiated rescan.
6502 * If either flag or controller event indicate rescan, add the controller
76438d08
SC		 6503 * to the list of controllers needing to be rescanned, and gets a
6504 * reference to the associated scsi_host.
6505 */
6506static void hpsa_ctlr_needs_rescan(struct ctlr_info *h)
6507{
6508 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
6509 return;
6510
6511 h->events = readl(&(h->cfgtable->event_notify));
faff6ee0 6512 if (!(h->events & RESCAN_REQUIRED_EVENT_BITS) && !h->drv_req_rescan)
76438d08
SC		 6513 return;
6514
6515 /*
6516 * Take a reference on scsi host for the duration of the scan
6517 * Release in hpsa_kickoff_rescan(). No lock needed for scan_list
6518 * as only a single thread accesses this list.
6519 */
6520 scsi_host_get(h->scsi_host);
6521 hpsa_kickoff_rescan(h);
6522}
6523
8a98db73 6524static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6525{
6526 unsigned long flags;
8a98db73
SC		 6527 struct ctlr_info *h = container_of(to_delayed_work(work),
6528 struct ctlr_info, monitor_ctlr_work);
6529 detect_controller_lockup(h);
6530 if (h->lockup_detected)
6531 return;
76438d08 6532 hpsa_ctlr_needs_rescan(h);
8a98db73
SC		 6533 spin_lock_irqsave(&h->lock, flags);
6534 if (h->remove_in_progress) {
6535 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6536 return;
6537 }
8a98db73
SC		 6538 schedule_delayed_work(&h->monitor_ctlr_work,
6539 h->heartbeat_sample_interval);
6540 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6541}
6542
6f039790 6543static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6544{
4c2a8c40 6545 int dac, rc;
edd16368 6546 struct ctlr_info *h;
64670ac8
SC		 6547 int try_soft_reset = 0;
6548 unsigned long flags;
edd16368
SC		 6549
6550 if (number_of_controllers == 0)
6551 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6552
4c2a8c40 6553 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6554 if (rc) {
6555 if (rc != -ENOTSUPP)
6556 return rc;
6557 /* If the reset fails in a particular way (it has no way to do
6558 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6559 * a soft reset once we get the controller configured up to the
6560 * point that it can accept a command.
6561 */
6562 try_soft_reset = 1;
6563 rc = 0;
6564 }
6565
6566reinit_after_soft_reset:
edd16368 6567
303932fd
DB		 6568 /* Command structures must be aligned on a 32-byte boundary because
6569 * the 5 lower bits of the address are used by the hardware. and by
6570 * the driver. See comments in hpsa.h for more info.
6571 */
283b4a9b 6572#define COMMANDLIST_ALIGNMENT 128
303932fd 6573 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6574 h = kzalloc(sizeof(*h), GFP_KERNEL);
6575 if (!h)
ecd9aad4 6576 return -ENOMEM;
edd16368 6577
55c06c71 6578 h->pdev = pdev;
a9a3a273 6579 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 6580 INIT_LIST_HEAD(&h->cmpQ);
6581 INIT_LIST_HEAD(&h->reqQ);
6eaf46fd
SC		 6582 spin_lock_init(&h->lock);
6583 spin_lock_init(&h->scan_lock);
0390f0c0 6584 spin_lock_init(&h->passthru_count_lock);
55c06c71 6585 rc = hpsa_pci_init(h);
ecd9aad4 6586 if (rc != 0)
edd16368
SC		 6587 goto clean1;
6588
f79cfec6 6589 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 6590 h->ctlr = number_of_controllers;
6591 number_of_controllers++;
edd16368
SC		 6592
6593 /* configure PCI DMA stuff */
ecd9aad4
SC		 6594 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6595 if (rc == 0) {
edd16368 6596 dac = 1;
ecd9aad4
SC		 6597 } else {
6598 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6599 if (rc == 0) {
6600 dac = 0;
6601 } else {
6602 dev_err(&pdev->dev, "no suitable DMA available\n");
6603 goto clean1;
6604 }
edd16368
SC		 6605 }
6606
6607 /* make sure the board interrupts are off */
6608 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 6609
0ae01a32 6610 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 6611 goto clean2;
303932fd
DB		 6612 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
6613 h->devname, pdev->device,
a9a3a273 6614 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 6615 if (hpsa_allocate_cmd_pool(h))
edd16368 6616 goto clean4;
33a2ffce
SC		 6617 if (hpsa_allocate_sg_chain_blocks(h))
6618 goto clean4;
a08a8471
SC		 6619 init_waitqueue_head(&h->scan_wait_queue);
6620 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 6621
6622 pci_set_drvdata(pdev, h);
9a41338e
SC		 6623 h->ndevices = 0;
6624 h->scsi_host = NULL;
6625 spin_lock_init(&h->devlock);
64670ac8
SC		 6626 hpsa_put_ctlr_into_performant_mode(h);
6627
6628 /* At this point, the controller is ready to take commands.
6629 * Now, if reset_devices and the hard reset didn't work, try
6630 * the soft reset and see if that works.
6631 */
6632 if (try_soft_reset) {
6633
6634 /* This is kind of gross. We may or may not get a completion
6635 * from the soft reset command, and if we do, then the value
6636 * from the fifo may or may not be valid. So, we wait 10 secs
6637 * after the reset throwing away any completions we get during
6638 * that time. Unregister the interrupt handler and register
6639 * fake ones to scoop up any residual completions.
6640 */
6641 spin_lock_irqsave(&h->lock, flags);
6642 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6643 spin_unlock_irqrestore(&h->lock, flags);
254f796b 6644 free_irqs(h);
64670ac8
SC		 6645 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
6646 hpsa_intx_discard_completions);
6647 if (rc) {
6648 dev_warn(&h->pdev->dev, "Failed to request_irq after "
6649 "soft reset.\n");
6650 goto clean4;
6651 }
6652
6653 rc = hpsa_kdump_soft_reset(h);
6654 if (rc)
6655 /* Neither hard nor soft reset worked, we're hosed. */
6656 goto clean4;
6657
6658 dev_info(&h->pdev->dev, "Board READY.\n");
6659 dev_info(&h->pdev->dev,
6660 "Waiting for stale completions to drain.\n");
6661 h->access.set_intr_mask(h, HPSA_INTR_ON);
6662 msleep(10000);
6663 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6664
6665 rc = controller_reset_failed(h->cfgtable);
6666 if (rc)
6667 dev_info(&h->pdev->dev,
6668 "Soft reset appears to have failed.\n");
6669
6670 /* since the controller's reset, we have to go back and re-init
6671 * everything. Easiest to just forget what we've done and do it
6672 * all over again.
6673 */
6674 hpsa_undo_allocations_after_kdump_soft_reset(h);
6675 try_soft_reset = 0;
6676 if (rc)
6677 /* don't go to clean4, we already unallocated */
6678 return -ENODEV;
6679
6680 goto reinit_after_soft_reset;
6681 }
edd16368 6682
da0697bd
ST		 6683 /* Enable Accelerated IO path at driver layer */
6684 h->acciopath_status = 1;
6685
e863d68e
ST		 6686 h->drv_req_rescan = 0;
6687
edd16368
SC		 6688 /* Turn the interrupts on so we can service requests */
6689 h->access.set_intr_mask(h, HPSA_INTR_ON);
6690
339b2b14 6691 hpsa_hba_inquiry(h);
edd16368 6692 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 6693
6694 /* Monitor the controller for firmware lockups */
6695 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
6696 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
6697 schedule_delayed_work(&h->monitor_ctlr_work,
6698 h->heartbeat_sample_interval);
88bf6d62 6699 return 0;
edd16368
SC		 6700
6701clean4:
33a2ffce 6702 hpsa_free_sg_chain_blocks(h);
2e9d1b36 6703 hpsa_free_cmd_pool(h);
254f796b 6704 free_irqs(h);
edd16368
SC		 6705clean2:
6706clean1:
edd16368 6707 kfree(h);
ecd9aad4 6708 return rc;
edd16368
SC		 6709}
6710
6711static void hpsa_flush_cache(struct ctlr_info *h)
6712{
6713 char *flush_buf;
6714 struct CommandList *c;
702890e3
SC		 6715 unsigned long flags;
6716
6717 /* Don't bother trying to flush the cache if locked up */
6718 spin_lock_irqsave(&h->lock, flags);
6719 if (unlikely(h->lockup_detected)) {
6720 spin_unlock_irqrestore(&h->lock, flags);
6721 return;
6722 }
6723 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 6724
6725 flush_buf = kzalloc(4, GFP_KERNEL);
6726 if (!flush_buf)
6727 return;
6728
6729 c = cmd_special_alloc(h);
6730 if (!c) {
6731 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
6732 goto out_of_memory;
6733 }
a2dac136
SC		 6734 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
6735 RAID_CTLR_LUNID, TYPE_CMD)) {
6736 goto out;
6737 }
edd16368
SC		 6738 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
6739 if (c->err_info->CommandStatus != 0)
a2dac136 6740out:
edd16368
SC		 6741 dev_warn(&h->pdev->dev,
6742 "error flushing cache on controller\n");
6743 cmd_special_free(h, c);
6744out_of_memory:
6745 kfree(flush_buf);
6746}
6747
6748static void hpsa_shutdown(struct pci_dev *pdev)
6749{
6750 struct ctlr_info *h;
6751
6752 h = pci_get_drvdata(pdev);
6753 /* Turn board interrupts off and send the flush cache command
6754 * sendcmd will turn off interrupt, and send the flush...
6755 * To write all data in the battery backed cache to disks
6756 */
6757 hpsa_flush_cache(h);
6758 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 6759 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 6760}
6761
6f039790 6762static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 6763{
6764 int i;
6765
6766 for (i = 0; i < h->ndevices; i++)
6767 kfree(h->dev[i]);
6768}
6769
6f039790 6770static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 6771{
6772 struct ctlr_info *h;
8a98db73 6773 unsigned long flags;
edd16368
SC		 6774
6775 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 6776 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 6777 return;
6778 }
6779 h = pci_get_drvdata(pdev);
8a98db73
SC		 6780
6781 /* Get rid of any controller monitoring work items */
6782 spin_lock_irqsave(&h->lock, flags);
6783 h->remove_in_progress = 1;
6784 cancel_delayed_work(&h->monitor_ctlr_work);
6785 spin_unlock_irqrestore(&h->lock, flags);
6786
edd16368
SC		 6787 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
6788 hpsa_shutdown(pdev);
6789 iounmap(h->vaddr);
204892e9
SC		 6790 iounmap(h->transtable);
6791 iounmap(h->cfgtable);
55e14e76 6792 hpsa_free_device_info(h);
33a2ffce 6793 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 6794 pci_free_consistent(h->pdev,
6795 h->nr_cmds * sizeof(struct CommandList),
6796 h->cmd_pool, h->cmd_pool_dhandle);
6797 pci_free_consistent(h->pdev,
6798 h->nr_cmds * sizeof(struct ErrorInfo),
6799 h->errinfo_pool, h->errinfo_pool_dhandle);
303932fd
DB		 6800 pci_free_consistent(h->pdev, h->reply_pool_size,
6801 h->reply_pool, h->reply_pool_dhandle);
edd16368 6802 kfree(h->cmd_pool_bits);
303932fd 6803 kfree(h->blockFetchTable);
e1f7de0c 6804 kfree(h->ioaccel1_blockFetchTable);
aca9012a 6805 kfree(h->ioaccel2_blockFetchTable);
339b2b14 6806 kfree(h->hba_inquiry_data);
f0bd0b68 6807 pci_disable_device(pdev);
edd16368 6808 pci_release_regions(pdev);
edd16368
SC		 6809 kfree(h);
6810}
6811
6812static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
6813 __attribute__((unused)) pm_message_t state)
6814{
6815 return -ENOSYS;
6816}
6817
6818static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
6819{
6820 return -ENOSYS;
6821}
6822
6823static struct pci_driver hpsa_pci_driver = {
f79cfec6 6824 .name = HPSA,
edd16368 6825 .probe = hpsa_init_one,
6f039790 6826 .remove = hpsa_remove_one,
edd16368
SC		 6827 .id_table = hpsa_pci_device_id, /* id_table */
6828 .shutdown = hpsa_shutdown,
6829 .suspend = hpsa_suspend,
6830 .resume = hpsa_resume,
6831};
6832
303932fd
DB		 6833/* Fill in bucket_map[], given nsgs (the max number of
6834 * scatter gather elements supported) and bucket[],
6835 * which is an array of 8 integers. The bucket[] array
6836 * contains 8 different DMA transfer sizes (in 16
6837 * byte increments) which the controller uses to fetch
6838 * commands. This function fills in bucket_map[], which
6839 * maps a given number of scatter gather elements to one of
6840 * the 8 DMA transfer sizes. The point of it is to allow the
6841 * controller to only do as much DMA as needed to fetch the
6842 * command, with the DMA transfer size encoded in the lower
6843 * bits of the command address.
6844 */
6845static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 6846 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 6847{
6848 int i, j, b, size;
6849
303932fd
DB		 6850 /* Note, bucket_map must have nsgs+1 entries. */
6851 for (i = 0; i <= nsgs; i++) {
6852 /* Compute size of a command with i SG entries */
e1f7de0c 6853 size = i + min_blocks;
303932fd
DB		 6854 b = num_buckets; /* Assume the biggest bucket */
6855 /* Find the bucket that is just big enough */
e1f7de0c 6856 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 6857 if (bucket[j] >= size) {
6858 b = j;
6859 break;
6860 }
6861 }
6862 /* for a command with i SG entries, use bucket b. */
6863 bucket_map[i] = b;
6864 }
6865}
6866
e1f7de0c 6867static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 6868{
6c311b57
SC		 6869 int i;
6870 unsigned long register_value;
e1f7de0c
MG		 6871 unsigned long transMethod = CFGTBL_Trans_Performant |
6872 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 6873 CFGTBL_Trans_enable_directed_msix |
6874 (trans_support & (CFGTBL_Trans_io_accel1 |
6875 CFGTBL_Trans_io_accel2));
e1f7de0c 6876 struct access_method access = SA5_performant_access;
def342bd
SC		 6877
6878 /* This is a bit complicated. There are 8 registers on
6879 * the controller which we write to to tell it 8 different
6880 * sizes of commands which there may be. It's a way of
6881 * reducing the DMA done to fetch each command. Encoded into
6882 * each command's tag are 3 bits which communicate to the controller
6883 * which of the eight sizes that command fits within. The size of
6884 * each command depends on how many scatter gather entries there are.
6885 * Each SG entry requires 16 bytes. The eight registers are programmed
6886 * with the number of 16-byte blocks a command of that size requires.
6887 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 6888 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 6889 * blocks. Note, this only extends to the SG entries contained
6890 * within the command block, and does not extend to chained blocks
6891 * of SG elements. bft[] contains the eight values we write to
6892 * the registers. They are not evenly distributed, but have more
6893 * sizes for small commands, and fewer sizes for larger commands.
6894 */
d66ae08b 6895 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 6896#define MIN_IOACCEL2_BFT_ENTRY 5
6897#define HPSA_IOACCEL2_HEADER_SZ 4
6898 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
6899 13, 14, 15, 16, 17, 18, 19,
6900 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
6901 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
6902 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
6903 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
6904 16 * MIN_IOACCEL2_BFT_ENTRY);
6905 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 6906 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 6907 /* 5 = 1 s/g entry or 4k
6908 * 6 = 2 s/g entry or 8k
6909 * 8 = 4 s/g entry or 16k
6910 * 10 = 6 s/g entry or 24k
6911 */
303932fd 6912
303932fd
DB		 6913 /* Controller spec: zero out this buffer. */
6914 memset(h->reply_pool, 0, h->reply_pool_size);
303932fd 6915
d66ae08b
SC		 6916 bft[7] = SG_ENTRIES_IN_CMD + 4;
6917 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 6918 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 6919 for (i = 0; i < 8; i++)
6920 writel(bft[i], &h->transtable->BlockFetch[i]);
6921
6922 /* size of controller ring buffer */
6923 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 6924 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 6925 writel(0, &h->transtable->RepQCtrAddrLow32);
6926 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 6927
6928 for (i = 0; i < h->nreply_queues; i++) {
6929 writel(0, &h->transtable->RepQAddr[i].upper);
6930 writel(h->reply_pool_dhandle +
6931 (h->max_commands * sizeof(u64) * i),
6932 &h->transtable->RepQAddr[i].lower);
6933 }
6934
b9af4937 6935 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 6936 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
6937 /*
6938 * enable outbound interrupt coalescing in accelerator mode;
6939 */
6940 if (trans_support & CFGTBL_Trans_io_accel1) {
6941 access = SA5_ioaccel_mode1_access;
6942 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
6943 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 6944 } else {
6945 if (trans_support & CFGTBL_Trans_io_accel2) {
6946 access = SA5_ioaccel_mode2_access;
6947 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
6948 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
6949 }
e1f7de0c 6950 }
303932fd 6951 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 6952 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 6953 register_value = readl(&(h->cfgtable->TransportActive));
6954 if (!(register_value & CFGTBL_Trans_Performant)) {
6955 dev_warn(&h->pdev->dev, "unable to get board into"
6956 " performant mode\n");
6957 return;
6958 }
960a30e7 6959 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 6960 h->access = access;
6961 h->transMethod = transMethod;
6962
b9af4937
SC		 6963 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
6964 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 6965 return;
6966
b9af4937
SC		 6967 if (trans_support & CFGTBL_Trans_io_accel1) {
6968 /* Set up I/O accelerator mode */
6969 for (i = 0; i < h->nreply_queues; i++) {
6970 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
6971 h->reply_queue[i].current_entry =
6972 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
6973 }
6974 bft[7] = h->ioaccel_maxsg + 8;
6975 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
6976 h->ioaccel1_blockFetchTable);
e1f7de0c 6977
b9af4937
SC		 6978 /* initialize all reply queue entries to unused */
6979 memset(h->reply_pool, (u8) IOACCEL_MODE1_REPLY_UNUSED,
6980 h->reply_pool_size);
e1f7de0c 6981
b9af4937
SC		 6982 /* set all the constant fields in the accelerator command
6983 * frames once at init time to save CPU cycles later.
6984 */
6985 for (i = 0; i < h->nr_cmds; i++) {
6986 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
6987
6988 cp->function = IOACCEL1_FUNCTION_SCSIIO;
6989 cp->err_info = (u32) (h->errinfo_pool_dhandle +
6990 (i * sizeof(struct ErrorInfo)));
6991 cp->err_info_len = sizeof(struct ErrorInfo);
6992 cp->sgl_offset = IOACCEL1_SGLOFFSET;
6993 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
6994 cp->timeout_sec = 0;
6995 cp->ReplyQueue = 0;
6996 cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) |
6997 DIRECT_LOOKUP_BIT;
6998 cp->Tag.upper = 0;
6999 cp->host_addr.lower =
7000 (u32) (h->ioaccel_cmd_pool_dhandle +
7001 (i * sizeof(struct io_accel1_cmd)));
7002 cp->host_addr.upper = 0;
7003 }
7004 } else if (trans_support & CFGTBL_Trans_io_accel2) {
7005 u64 cfg_offset, cfg_base_addr_index;
7006 u32 bft2_offset, cfg_base_addr;
7007 int rc;
7008
7009 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7010 &cfg_base_addr_index, &cfg_offset);
7011 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
7012 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
7013 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
7014 4, h->ioaccel2_blockFetchTable);
7015 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
7016 BUILD_BUG_ON(offsetof(struct CfgTable,
7017 io_accel_request_size_offset) != 0xb8);
7018 h->ioaccel2_bft2_regs =
7019 remap_pci_mem(pci_resource_start(h->pdev,
7020 cfg_base_addr_index) +
7021 cfg_offset + bft2_offset,
7022 ARRAY_SIZE(bft2) *
7023 sizeof(*h->ioaccel2_bft2_regs));
7024 for (i = 0; i < ARRAY_SIZE(bft2); i++)
7025 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 7026 }
b9af4937
SC		 7027 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
7028 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 7029}
7030
7031static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
7032{
283b4a9b
SC		 7033 h->ioaccel_maxsg =
7034 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7035 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
7036 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
7037
e1f7de0c
MG		 7038 /* Command structures must be aligned on a 128-byte boundary
7039 * because the 7 lower bits of the address are used by the
7040 * hardware.
7041 */
7042#define IOACCEL1_COMMANDLIST_ALIGNMENT 128
7043 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
7044 IOACCEL1_COMMANDLIST_ALIGNMENT);
7045 h->ioaccel_cmd_pool =
7046 pci_alloc_consistent(h->pdev,
7047 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7048 &(h->ioaccel_cmd_pool_dhandle));
7049
7050 h->ioaccel1_blockFetchTable =
283b4a9b 7051 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 7052 sizeof(u32)), GFP_KERNEL);
7053
7054 if ((h->ioaccel_cmd_pool == NULL) ||
7055 (h->ioaccel1_blockFetchTable == NULL))
7056 goto clean_up;
7057
7058 memset(h->ioaccel_cmd_pool, 0,
7059 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
7060 return 0;
7061
7062clean_up:
7063 if (h->ioaccel_cmd_pool)
7064 pci_free_consistent(h->pdev,
7065 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
7066 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
7067 kfree(h->ioaccel1_blockFetchTable);
7068 return 1;
6c311b57
SC		 7069}
7070
aca9012a
SC		 7071static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
7072{
7073 /* Allocate ioaccel2 mode command blocks and block fetch table */
7074
7075 h->ioaccel_maxsg =
7076 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
7077 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
7078 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
7079
7080#define IOACCEL2_COMMANDLIST_ALIGNMENT 128
7081 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
7082 IOACCEL2_COMMANDLIST_ALIGNMENT);
7083 h->ioaccel2_cmd_pool =
7084 pci_alloc_consistent(h->pdev,
7085 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7086 &(h->ioaccel2_cmd_pool_dhandle));
7087
7088 h->ioaccel2_blockFetchTable =
7089 kmalloc(((h->ioaccel_maxsg + 1) *
7090 sizeof(u32)), GFP_KERNEL);
7091
7092 if ((h->ioaccel2_cmd_pool == NULL) ||
7093 (h->ioaccel2_blockFetchTable == NULL))
7094 goto clean_up;
7095
7096 memset(h->ioaccel2_cmd_pool, 0,
7097 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
7098 return 0;
7099
7100clean_up:
7101 if (h->ioaccel2_cmd_pool)
7102 pci_free_consistent(h->pdev,
7103 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
7104 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
7105 kfree(h->ioaccel2_blockFetchTable);
7106 return 1;
7107}
7108
6f039790 7109static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 7110{
7111 u32 trans_support;
e1f7de0c
MG		 7112 unsigned long transMethod = CFGTBL_Trans_Performant |
7113 CFGTBL_Trans_use_short_tags;
254f796b 7114 int i;
6c311b57 7115
02ec19c8
SC		 7116 if (hpsa_simple_mode)
7117 return;
7118
e1f7de0c
MG		 7119 /* Check for I/O accelerator mode support */
7120 if (trans_support & CFGTBL_Trans_io_accel1) {
7121 transMethod |= CFGTBL_Trans_io_accel1 |
7122 CFGTBL_Trans_enable_directed_msix;
7123 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
7124 goto clean_up;
aca9012a
SC		 7125 } else {
7126 if (trans_support & CFGTBL_Trans_io_accel2) {
7127 transMethod |= CFGTBL_Trans_io_accel2 |
7128 CFGTBL_Trans_enable_directed_msix;
7129 if (ioaccel2_alloc_cmds_and_bft(h))
7130 goto clean_up;
7131 }
e1f7de0c
MG		 7132 }
7133
7134 /* TODO, check that this next line h->nreply_queues is correct */
6c311b57
SC		 7135 trans_support = readl(&(h->cfgtable->TransportSupport));
7136 if (!(trans_support & PERFORMANT_MODE))
7137 return;
7138
eee0f03a 7139 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 7140 hpsa_get_max_perf_mode_cmds(h);
6c311b57 7141 /* Performant mode ring buffer and supporting data structures */
254f796b 7142 h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues;
6c311b57
SC		 7143 h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
7144 &(h->reply_pool_dhandle));
7145
254f796b
MG		 7146 for (i = 0; i < h->nreply_queues; i++) {
7147 h->reply_queue[i].head = &h->reply_pool[h->max_commands * i];
7148 h->reply_queue[i].size = h->max_commands;
7149 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
7150 h->reply_queue[i].current_entry = 0;
7151 }
7152
6c311b57 7153 /* Need a block fetch table for performant mode */
d66ae08b 7154 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57
SC		 7155 sizeof(u32)), GFP_KERNEL);
7156
7157 if ((h->reply_pool == NULL)
7158 || (h->blockFetchTable == NULL))
7159 goto clean_up;
7160
e1f7de0c 7161 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 7162 return;
7163
7164clean_up:
7165 if (h->reply_pool)
7166 pci_free_consistent(h->pdev, h->reply_pool_size,
7167 h->reply_pool, h->reply_pool_dhandle);
7168 kfree(h->blockFetchTable);
7169}
7170
23100dd9 7171static int is_accelerated_cmd(struct CommandList *c)
76438d08 7172{
23100dd9
SC		 7173 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
7174}
7175
7176static void hpsa_drain_accel_commands(struct ctlr_info *h)
7177{
7178 struct CommandList *c = NULL;
76438d08 7179 unsigned long flags;
23100dd9 7180 int accel_cmds_out;
76438d08
SC		 7181
7182 do { /* wait for all outstanding commands to drain out */
23100dd9 7183 accel_cmds_out = 0;
76438d08 7184 spin_lock_irqsave(&h->lock, flags);
23100dd9
SC		 7185 list_for_each_entry(c, &h->cmpQ, list)
7186 accel_cmds_out += is_accelerated_cmd(c);
7187 list_for_each_entry(c, &h->reqQ, list)
7188 accel_cmds_out += is_accelerated_cmd(c);
76438d08 7189 spin_unlock_irqrestore(&h->lock, flags);
23100dd9 7190 if (accel_cmds_out <= 0)
76438d08
SC		 7191 break;
7192 msleep(100);
7193 } while (1);
7194}
7195
edd16368
SC		 7196/*
7197 * This is it. Register the PCI driver information for the cards we control
7198 * the OS will call our registered routines when it finds one of our cards.
7199 */
7200static int __init hpsa_init(void)
7201{
31468401 7202 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 7203}
7204
7205static void __exit hpsa_cleanup(void)
7206{
7207 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 7208}
7209
e1f7de0c
MG		 7210static void __attribute__((unused)) verify_offsets(void)
7211{
dd0e19f3
ST		 7212#define VERIFY_OFFSET(member, offset) \
7213 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
7214
7215 VERIFY_OFFSET(structure_size, 0);
7216 VERIFY_OFFSET(volume_blk_size, 4);
7217 VERIFY_OFFSET(volume_blk_cnt, 8);
7218 VERIFY_OFFSET(phys_blk_shift, 16);
7219 VERIFY_OFFSET(parity_rotation_shift, 17);
7220 VERIFY_OFFSET(strip_size, 18);
7221 VERIFY_OFFSET(disk_starting_blk, 20);
7222 VERIFY_OFFSET(disk_blk_cnt, 28);
7223 VERIFY_OFFSET(data_disks_per_row, 36);
7224 VERIFY_OFFSET(metadata_disks_per_row, 38);
7225 VERIFY_OFFSET(row_cnt, 40);
7226 VERIFY_OFFSET(layout_map_count, 42);
7227 VERIFY_OFFSET(flags, 44);
7228 VERIFY_OFFSET(dekindex, 46);
7229 /* VERIFY_OFFSET(reserved, 48 */
7230 VERIFY_OFFSET(data, 64);
7231
7232#undef VERIFY_OFFSET
7233
b66cc250
MM		 7234#define VERIFY_OFFSET(member, offset) \
7235 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
7236
7237 VERIFY_OFFSET(IU_type, 0);
7238 VERIFY_OFFSET(direction, 1);
7239 VERIFY_OFFSET(reply_queue, 2);
7240 /* VERIFY_OFFSET(reserved1, 3); */
7241 VERIFY_OFFSET(scsi_nexus, 4);
7242 VERIFY_OFFSET(Tag, 8);
7243 VERIFY_OFFSET(cdb, 16);
7244 VERIFY_OFFSET(cciss_lun, 32);
7245 VERIFY_OFFSET(data_len, 40);
7246 VERIFY_OFFSET(cmd_priority_task_attr, 44);
7247 VERIFY_OFFSET(sg_count, 45);
7248 /* VERIFY_OFFSET(reserved3 */
7249 VERIFY_OFFSET(err_ptr, 48);
7250 VERIFY_OFFSET(err_len, 56);
7251 /* VERIFY_OFFSET(reserved4 */
7252 VERIFY_OFFSET(sg, 64);
7253
7254#undef VERIFY_OFFSET
7255
e1f7de0c
MG		 7256#define VERIFY_OFFSET(member, offset) \
7257 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
7258
7259 VERIFY_OFFSET(dev_handle, 0x00);
7260 VERIFY_OFFSET(reserved1, 0x02);
7261 VERIFY_OFFSET(function, 0x03);
7262 VERIFY_OFFSET(reserved2, 0x04);
7263 VERIFY_OFFSET(err_info, 0x0C);
7264 VERIFY_OFFSET(reserved3, 0x10);
7265 VERIFY_OFFSET(err_info_len, 0x12);
7266 VERIFY_OFFSET(reserved4, 0x13);
7267 VERIFY_OFFSET(sgl_offset, 0x14);
7268 VERIFY_OFFSET(reserved5, 0x15);
7269 VERIFY_OFFSET(transfer_len, 0x1C);
7270 VERIFY_OFFSET(reserved6, 0x20);
7271 VERIFY_OFFSET(io_flags, 0x24);
7272 VERIFY_OFFSET(reserved7, 0x26);
7273 VERIFY_OFFSET(LUN, 0x34);
7274 VERIFY_OFFSET(control, 0x3C);
7275 VERIFY_OFFSET(CDB, 0x40);
7276 VERIFY_OFFSET(reserved8, 0x50);
7277 VERIFY_OFFSET(host_context_flags, 0x60);
7278 VERIFY_OFFSET(timeout_sec, 0x62);
7279 VERIFY_OFFSET(ReplyQueue, 0x64);
7280 VERIFY_OFFSET(reserved9, 0x65);
7281 VERIFY_OFFSET(Tag, 0x68);
7282 VERIFY_OFFSET(host_addr, 0x70);
7283 VERIFY_OFFSET(CISS_LUN, 0x78);
7284 VERIFY_OFFSET(SG, 0x78 + 8);
7285#undef VERIFY_OFFSET
7286}
7287
edd16368
SC		 7288module_init(hpsa_init);
7289module_exit(hpsa_cleanup);
Linux 6.x block layer and io_uring tree(s)