Commit | Line | Data |
---|---|---|
edd16368 SC |
1 | /* |
2 | * Disk Array driver for HP Smart Array SAS controllers | |
51c35139 | 3 | * Copyright 2000, 2014 Hewlett-Packard Development Company, L.P. |
edd16368 SC |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; version 2 of the License. | |
8 | * | |
9 | * This program is distributed in the hope that it will be useful, | |
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
11 | * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or | |
12 | * NON INFRINGEMENT. See the GNU General Public License for more details. | |
13 | * | |
14 | * You should have received a copy of the GNU General Public License | |
15 | * along with this program; if not, write to the Free Software | |
16 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
17 | * | |
18 | * Questions/Comments/Bugfixes to iss_storagedev@hp.com | |
19 | * | |
20 | */ | |
21 | ||
22 | #include <linux/module.h> | |
23 | #include <linux/interrupt.h> | |
24 | #include <linux/types.h> | |
25 | #include <linux/pci.h> | |
e5a44df8 | 26 | #include <linux/pci-aspm.h> |
edd16368 SC |
27 | #include <linux/kernel.h> |
28 | #include <linux/slab.h> | |
29 | #include <linux/delay.h> | |
30 | #include <linux/fs.h> | |
31 | #include <linux/timer.h> | |
edd16368 SC |
32 | #include <linux/init.h> |
33 | #include <linux/spinlock.h> | |
edd16368 SC |
34 | #include <linux/compat.h> |
35 | #include <linux/blktrace_api.h> | |
36 | #include <linux/uaccess.h> | |
37 | #include <linux/io.h> | |
38 | #include <linux/dma-mapping.h> | |
39 | #include <linux/completion.h> | |
40 | #include <linux/moduleparam.h> | |
41 | #include <scsi/scsi.h> | |
42 | #include <scsi/scsi_cmnd.h> | |
43 | #include <scsi/scsi_device.h> | |
44 | #include <scsi/scsi_host.h> | |
667e23d4 | 45 | #include <scsi/scsi_tcq.h> |
edd16368 SC |
46 | #include <linux/cciss_ioctl.h> |
47 | #include <linux/string.h> | |
48 | #include <linux/bitmap.h> | |
60063497 | 49 | #include <linux/atomic.h> |
a0c12413 | 50 | #include <linux/jiffies.h> |
42a91641 | 51 | #include <linux/percpu-defs.h> |
094963da | 52 | #include <linux/percpu.h> |
2b08b3e9 | 53 | #include <asm/unaligned.h> |
283b4a9b | 54 | #include <asm/div64.h> |
edd16368 SC |
55 | #include "hpsa_cmd.h" |
56 | #include "hpsa.h" | |
57 | ||
58 | /* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */ | |
9a993302 | 59 | #define HPSA_DRIVER_VERSION "3.4.4-1" |
edd16368 | 60 | #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")" |
f79cfec6 | 61 | #define HPSA "hpsa" |
edd16368 SC |
62 | |
63 | /* How long to wait (in milliseconds) for board to go into simple mode */ | |
64 | #define MAX_CONFIG_WAIT 30000 | |
65 | #define MAX_IOCTL_CONFIG_WAIT 1000 | |
66 | ||
67 | /*define how many times we will try a command because of bus resets */ | |
68 | #define MAX_CMD_RETRIES 3 | |
69 | ||
70 | /* Embedded module documentation macros - see modules.h */ | |
71 | MODULE_AUTHOR("Hewlett-Packard Company"); | |
72 | MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \ | |
73 | HPSA_DRIVER_VERSION); | |
74 | MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers"); | |
75 | MODULE_VERSION(HPSA_DRIVER_VERSION); | |
76 | MODULE_LICENSE("GPL"); | |
77 | ||
78 | static int hpsa_allow_any; | |
79 | module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR); | |
80 | MODULE_PARM_DESC(hpsa_allow_any, | |
81 | "Allow hpsa driver to access unknown HP Smart Array hardware"); | |
02ec19c8 SC |
82 | static int hpsa_simple_mode; |
83 | module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR); | |
84 | MODULE_PARM_DESC(hpsa_simple_mode, | |
85 | "Use 'simple mode' rather than 'performant mode'"); | |
edd16368 SC |
86 | |
87 | /* define the PCI info for the cards we can control */ | |
88 | static const struct pci_device_id hpsa_pci_device_id[] = { | |
edd16368 SC |
89 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241}, |
90 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243}, | |
91 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245}, | |
92 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247}, | |
93 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249}, | |
163dbcd8 MM |
94 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A}, |
95 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B}, | |
f8b01eb9 | 96 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233}, |
9143a961 | 97 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350}, |
98 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351}, | |
99 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352}, | |
100 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353}, | |
101 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354}, | |
102 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355}, | |
103 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356}, | |
fe0c9610 MM |
104 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921}, |
105 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922}, | |
106 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923}, | |
107 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924}, | |
fe0c9610 MM |
108 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926}, |
109 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928}, | |
97b9f53d MM |
110 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929}, |
111 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD}, | |
112 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE}, | |
113 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF}, | |
114 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0}, | |
115 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1}, | |
116 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2}, | |
117 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3}, | |
118 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4}, | |
119 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5}, | |
3b7a45e5 | 120 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6}, |
97b9f53d MM |
121 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7}, |
122 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8}, | |
123 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9}, | |
3b7a45e5 JH |
124 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA}, |
125 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB}, | |
126 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC}, | |
127 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD}, | |
128 | {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE}, | |
8e616a5e SC |
129 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076}, |
130 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087}, | |
131 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D}, | |
132 | {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088}, | |
133 | {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f}, | |
7c03b870 | 134 | {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, |
6798cc0a | 135 | PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0}, |
edd16368 SC |
136 | {0,} |
137 | }; | |
138 | ||
139 | MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id); | |
140 | ||
141 | /* board_id = Subsystem Device ID & Vendor ID | |
142 | * product = Marketing Name for the board | |
143 | * access = Address of the struct of function pointers | |
144 | */ | |
145 | static struct board_type products[] = { | |
edd16368 SC |
146 | {0x3241103C, "Smart Array P212", &SA5_access}, |
147 | {0x3243103C, "Smart Array P410", &SA5_access}, | |
148 | {0x3245103C, "Smart Array P410i", &SA5_access}, | |
149 | {0x3247103C, "Smart Array P411", &SA5_access}, | |
150 | {0x3249103C, "Smart Array P812", &SA5_access}, | |
163dbcd8 MM |
151 | {0x324A103C, "Smart Array P712m", &SA5_access}, |
152 | {0x324B103C, "Smart Array P711m", &SA5_access}, | |
7d2cce58 | 153 | {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */ |
fe0c9610 MM |
154 | {0x3350103C, "Smart Array P222", &SA5_access}, |
155 | {0x3351103C, "Smart Array P420", &SA5_access}, | |
156 | {0x3352103C, "Smart Array P421", &SA5_access}, | |
157 | {0x3353103C, "Smart Array P822", &SA5_access}, | |
158 | {0x3354103C, "Smart Array P420i", &SA5_access}, | |
159 | {0x3355103C, "Smart Array P220i", &SA5_access}, | |
160 | {0x3356103C, "Smart Array P721m", &SA5_access}, | |
1fd6c8e3 MM |
161 | {0x1921103C, "Smart Array P830i", &SA5_access}, |
162 | {0x1922103C, "Smart Array P430", &SA5_access}, | |
163 | {0x1923103C, "Smart Array P431", &SA5_access}, | |
164 | {0x1924103C, "Smart Array P830", &SA5_access}, | |
165 | {0x1926103C, "Smart Array P731m", &SA5_access}, | |
166 | {0x1928103C, "Smart Array P230i", &SA5_access}, | |
167 | {0x1929103C, "Smart Array P530", &SA5_access}, | |
97b9f53d MM |
168 | {0x21BD103C, "Smart Array", &SA5_access}, |
169 | {0x21BE103C, "Smart Array", &SA5_access}, | |
170 | {0x21BF103C, "Smart Array", &SA5_access}, | |
171 | {0x21C0103C, "Smart Array", &SA5_access}, | |
172 | {0x21C1103C, "Smart Array", &SA5_access}, | |
173 | {0x21C2103C, "Smart Array", &SA5_access}, | |
174 | {0x21C3103C, "Smart Array", &SA5_access}, | |
175 | {0x21C4103C, "Smart Array", &SA5_access}, | |
176 | {0x21C5103C, "Smart Array", &SA5_access}, | |
3b7a45e5 | 177 | {0x21C6103C, "Smart Array", &SA5_access}, |
97b9f53d MM |
178 | {0x21C7103C, "Smart Array", &SA5_access}, |
179 | {0x21C8103C, "Smart Array", &SA5_access}, | |
180 | {0x21C9103C, "Smart Array", &SA5_access}, | |
3b7a45e5 JH |
181 | {0x21CA103C, "Smart Array", &SA5_access}, |
182 | {0x21CB103C, "Smart Array", &SA5_access}, | |
183 | {0x21CC103C, "Smart Array", &SA5_access}, | |
184 | {0x21CD103C, "Smart Array", &SA5_access}, | |
185 | {0x21CE103C, "Smart Array", &SA5_access}, | |
8e616a5e SC |
186 | {0x00761590, "HP Storage P1224 Array Controller", &SA5_access}, |
187 | {0x00871590, "HP Storage P1224e Array Controller", &SA5_access}, | |
188 | {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access}, | |
189 | {0x00881590, "HP Storage P1228e Array Controller", &SA5_access}, | |
190 | {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access}, | |
edd16368 SC |
191 | {0xFFFF103C, "Unknown Smart Array", &SA5_access}, |
192 | }; | |
193 | ||
194 | static int number_of_controllers; | |
195 | ||
10f66018 SC |
196 | static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id); |
197 | static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id); | |
42a91641 | 198 | static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg); |
edd16368 SC |
199 | |
200 | #ifdef CONFIG_COMPAT | |
42a91641 DB |
201 | static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, |
202 | void __user *arg); | |
edd16368 SC |
203 | #endif |
204 | ||
205 | static void cmd_free(struct ctlr_info *h, struct CommandList *c); | |
edd16368 | 206 | static struct CommandList *cmd_alloc(struct ctlr_info *h); |
a2dac136 | 207 | static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, |
b7bb24eb | 208 | void *buff, size_t size, u16 page_code, unsigned char *scsi3addr, |
edd16368 | 209 | int cmd_type); |
2c143342 | 210 | static void hpsa_free_cmd_pool(struct ctlr_info *h); |
b7bb24eb | 211 | #define VPD_PAGE (1 << 8) |
edd16368 | 212 | |
f281233d | 213 | static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd); |
a08a8471 SC |
214 | static void hpsa_scan_start(struct Scsi_Host *); |
215 | static int hpsa_scan_finished(struct Scsi_Host *sh, | |
216 | unsigned long elapsed_time); | |
7c0a0229 | 217 | static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth); |
edd16368 SC |
218 | |
219 | static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd); | |
75167d2c | 220 | static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd); |
edd16368 SC |
221 | static int hpsa_slave_alloc(struct scsi_device *sdev); |
222 | static void hpsa_slave_destroy(struct scsi_device *sdev); | |
223 | ||
edd16368 | 224 | static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno); |
edd16368 SC |
225 | static int check_for_unit_attention(struct ctlr_info *h, |
226 | struct CommandList *c); | |
227 | static void check_ioctl_unit_attention(struct ctlr_info *h, | |
228 | struct CommandList *c); | |
303932fd DB |
229 | /* performant mode helper functions */ |
230 | static void calc_bucket_map(int *bucket, int num_buckets, | |
2b08b3e9 | 231 | int nsgs, int min_blocks, u32 *bucket_map); |
6f039790 | 232 | static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h); |
254f796b | 233 | static inline u32 next_command(struct ctlr_info *h, u8 q); |
6f039790 GKH |
234 | static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, |
235 | u32 *cfg_base_addr, u64 *cfg_base_addr_index, | |
236 | u64 *cfg_offset); | |
237 | static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, | |
238 | unsigned long *memory_bar); | |
239 | static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id); | |
240 | static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, | |
241 | int wait_for_ready); | |
75167d2c | 242 | static inline void finish_cmd(struct CommandList *c); |
283b4a9b | 243 | static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h); |
fe5389c8 SC |
244 | #define BOARD_NOT_READY 0 |
245 | #define BOARD_READY 1 | |
23100dd9 | 246 | static void hpsa_drain_accel_commands(struct ctlr_info *h); |
76438d08 | 247 | static void hpsa_flush_cache(struct ctlr_info *h); |
c349775e ST |
248 | static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, |
249 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
03383736 | 250 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk); |
080ef1cc | 251 | static void hpsa_command_resubmit_worker(struct work_struct *work); |
edd16368 | 252 | |
edd16368 SC |
253 | static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev) |
254 | { | |
255 | unsigned long *priv = shost_priv(sdev->host); | |
256 | return (struct ctlr_info *) *priv; | |
257 | } | |
258 | ||
a23513e8 SC |
259 | static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh) |
260 | { | |
261 | unsigned long *priv = shost_priv(sh); | |
262 | return (struct ctlr_info *) *priv; | |
263 | } | |
264 | ||
edd16368 SC |
265 | static int check_for_unit_attention(struct ctlr_info *h, |
266 | struct CommandList *c) | |
267 | { | |
268 | if (c->err_info->SenseInfo[2] != UNIT_ATTENTION) | |
269 | return 0; | |
270 | ||
271 | switch (c->err_info->SenseInfo[12]) { | |
272 | case STATE_CHANGED: | |
f79cfec6 | 273 | dev_warn(&h->pdev->dev, HPSA "%d: a state change " |
edd16368 SC |
274 | "detected, command retried\n", h->ctlr); |
275 | break; | |
276 | case LUN_FAILED: | |
7f73695a SC |
277 | dev_warn(&h->pdev->dev, |
278 | HPSA "%d: LUN failure detected\n", h->ctlr); | |
edd16368 SC |
279 | break; |
280 | case REPORT_LUNS_CHANGED: | |
7f73695a SC |
281 | dev_warn(&h->pdev->dev, |
282 | HPSA "%d: report LUN data changed\n", h->ctlr); | |
edd16368 | 283 | /* |
4f4eb9f1 ST |
284 | * Note: this REPORT_LUNS_CHANGED condition only occurs on the external |
285 | * target (array) devices. | |
edd16368 SC |
286 | */ |
287 | break; | |
288 | case POWER_OR_RESET: | |
f79cfec6 | 289 | dev_warn(&h->pdev->dev, HPSA "%d: a power on " |
edd16368 SC |
290 | "or device reset detected\n", h->ctlr); |
291 | break; | |
292 | case UNIT_ATTENTION_CLEARED: | |
f79cfec6 | 293 | dev_warn(&h->pdev->dev, HPSA "%d: unit attention " |
edd16368 SC |
294 | "cleared by another initiator\n", h->ctlr); |
295 | break; | |
296 | default: | |
f79cfec6 | 297 | dev_warn(&h->pdev->dev, HPSA "%d: unknown " |
edd16368 SC |
298 | "unit attention detected\n", h->ctlr); |
299 | break; | |
300 | } | |
301 | return 1; | |
302 | } | |
303 | ||
852af20a MB |
304 | static int check_for_busy(struct ctlr_info *h, struct CommandList *c) |
305 | { | |
306 | if (c->err_info->CommandStatus != CMD_TARGET_STATUS || | |
307 | (c->err_info->ScsiStatus != SAM_STAT_BUSY && | |
308 | c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL)) | |
309 | return 0; | |
310 | dev_warn(&h->pdev->dev, HPSA "device busy"); | |
311 | return 1; | |
312 | } | |
313 | ||
da0697bd ST |
314 | static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev, |
315 | struct device_attribute *attr, | |
316 | const char *buf, size_t count) | |
317 | { | |
318 | int status, len; | |
319 | struct ctlr_info *h; | |
320 | struct Scsi_Host *shost = class_to_shost(dev); | |
321 | char tmpbuf[10]; | |
322 | ||
323 | if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) | |
324 | return -EACCES; | |
325 | len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count; | |
326 | strncpy(tmpbuf, buf, len); | |
327 | tmpbuf[len] = '\0'; | |
328 | if (sscanf(tmpbuf, "%d", &status) != 1) | |
329 | return -EINVAL; | |
330 | h = shost_to_hba(shost); | |
331 | h->acciopath_status = !!status; | |
332 | dev_warn(&h->pdev->dev, | |
333 | "hpsa: HP SSD Smart Path %s via sysfs update.\n", | |
334 | h->acciopath_status ? "enabled" : "disabled"); | |
335 | return count; | |
336 | } | |
337 | ||
2ba8bfc8 SC |
338 | static ssize_t host_store_raid_offload_debug(struct device *dev, |
339 | struct device_attribute *attr, | |
340 | const char *buf, size_t count) | |
341 | { | |
342 | int debug_level, len; | |
343 | struct ctlr_info *h; | |
344 | struct Scsi_Host *shost = class_to_shost(dev); | |
345 | char tmpbuf[10]; | |
346 | ||
347 | if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO)) | |
348 | return -EACCES; | |
349 | len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count; | |
350 | strncpy(tmpbuf, buf, len); | |
351 | tmpbuf[len] = '\0'; | |
352 | if (sscanf(tmpbuf, "%d", &debug_level) != 1) | |
353 | return -EINVAL; | |
354 | if (debug_level < 0) | |
355 | debug_level = 0; | |
356 | h = shost_to_hba(shost); | |
357 | h->raid_offload_debug = debug_level; | |
358 | dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n", | |
359 | h->raid_offload_debug); | |
360 | return count; | |
361 | } | |
362 | ||
edd16368 SC |
363 | static ssize_t host_store_rescan(struct device *dev, |
364 | struct device_attribute *attr, | |
365 | const char *buf, size_t count) | |
366 | { | |
367 | struct ctlr_info *h; | |
368 | struct Scsi_Host *shost = class_to_shost(dev); | |
a23513e8 | 369 | h = shost_to_hba(shost); |
31468401 | 370 | hpsa_scan_start(h->scsi_host); |
edd16368 SC |
371 | return count; |
372 | } | |
373 | ||
d28ce020 SC |
374 | static ssize_t host_show_firmware_revision(struct device *dev, |
375 | struct device_attribute *attr, char *buf) | |
376 | { | |
377 | struct ctlr_info *h; | |
378 | struct Scsi_Host *shost = class_to_shost(dev); | |
379 | unsigned char *fwrev; | |
380 | ||
381 | h = shost_to_hba(shost); | |
382 | if (!h->hba_inquiry_data) | |
383 | return 0; | |
384 | fwrev = &h->hba_inquiry_data[32]; | |
385 | return snprintf(buf, 20, "%c%c%c%c\n", | |
386 | fwrev[0], fwrev[1], fwrev[2], fwrev[3]); | |
387 | } | |
388 | ||
94a13649 SC |
389 | static ssize_t host_show_commands_outstanding(struct device *dev, |
390 | struct device_attribute *attr, char *buf) | |
391 | { | |
392 | struct Scsi_Host *shost = class_to_shost(dev); | |
393 | struct ctlr_info *h = shost_to_hba(shost); | |
394 | ||
0cbf768e SC |
395 | return snprintf(buf, 20, "%d\n", |
396 | atomic_read(&h->commands_outstanding)); | |
94a13649 SC |
397 | } |
398 | ||
745a7a25 SC |
399 | static ssize_t host_show_transport_mode(struct device *dev, |
400 | struct device_attribute *attr, char *buf) | |
401 | { | |
402 | struct ctlr_info *h; | |
403 | struct Scsi_Host *shost = class_to_shost(dev); | |
404 | ||
405 | h = shost_to_hba(shost); | |
406 | return snprintf(buf, 20, "%s\n", | |
960a30e7 | 407 | h->transMethod & CFGTBL_Trans_Performant ? |
745a7a25 SC |
408 | "performant" : "simple"); |
409 | } | |
410 | ||
da0697bd ST |
411 | static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev, |
412 | struct device_attribute *attr, char *buf) | |
413 | { | |
414 | struct ctlr_info *h; | |
415 | struct Scsi_Host *shost = class_to_shost(dev); | |
416 | ||
417 | h = shost_to_hba(shost); | |
418 | return snprintf(buf, 30, "HP SSD Smart Path %s\n", | |
419 | (h->acciopath_status == 1) ? "enabled" : "disabled"); | |
420 | } | |
421 | ||
46380786 | 422 | /* List of controllers which cannot be hard reset on kexec with reset_devices */ |
941b1cda SC |
423 | static u32 unresettable_controller[] = { |
424 | 0x324a103C, /* Smart Array P712m */ | |
425 | 0x324b103C, /* SmartArray P711m */ | |
426 | 0x3223103C, /* Smart Array P800 */ | |
427 | 0x3234103C, /* Smart Array P400 */ | |
428 | 0x3235103C, /* Smart Array P400i */ | |
429 | 0x3211103C, /* Smart Array E200i */ | |
430 | 0x3212103C, /* Smart Array E200 */ | |
431 | 0x3213103C, /* Smart Array E200i */ | |
432 | 0x3214103C, /* Smart Array E200i */ | |
433 | 0x3215103C, /* Smart Array E200i */ | |
434 | 0x3237103C, /* Smart Array E500 */ | |
435 | 0x323D103C, /* Smart Array P700m */ | |
7af0abbc | 436 | 0x40800E11, /* Smart Array 5i */ |
941b1cda SC |
437 | 0x409C0E11, /* Smart Array 6400 */ |
438 | 0x409D0E11, /* Smart Array 6400 EM */ | |
5a4f934e TH |
439 | 0x40700E11, /* Smart Array 5300 */ |
440 | 0x40820E11, /* Smart Array 532 */ | |
441 | 0x40830E11, /* Smart Array 5312 */ | |
442 | 0x409A0E11, /* Smart Array 641 */ | |
443 | 0x409B0E11, /* Smart Array 642 */ | |
444 | 0x40910E11, /* Smart Array 6i */ | |
941b1cda SC |
445 | }; |
446 | ||
46380786 SC |
447 | /* List of controllers which cannot even be soft reset */ |
448 | static u32 soft_unresettable_controller[] = { | |
7af0abbc | 449 | 0x40800E11, /* Smart Array 5i */ |
5a4f934e TH |
450 | 0x40700E11, /* Smart Array 5300 */ |
451 | 0x40820E11, /* Smart Array 532 */ | |
452 | 0x40830E11, /* Smart Array 5312 */ | |
453 | 0x409A0E11, /* Smart Array 641 */ | |
454 | 0x409B0E11, /* Smart Array 642 */ | |
455 | 0x40910E11, /* Smart Array 6i */ | |
46380786 SC |
456 | /* Exclude 640x boards. These are two pci devices in one slot |
457 | * which share a battery backed cache module. One controls the | |
458 | * cache, the other accesses the cache through the one that controls | |
459 | * it. If we reset the one controlling the cache, the other will | |
460 | * likely not be happy. Just forbid resetting this conjoined mess. | |
461 | * The 640x isn't really supported by hpsa anyway. | |
462 | */ | |
463 | 0x409C0E11, /* Smart Array 6400 */ | |
464 | 0x409D0E11, /* Smart Array 6400 EM */ | |
465 | }; | |
466 | ||
467 | static int ctlr_is_hard_resettable(u32 board_id) | |
941b1cda SC |
468 | { |
469 | int i; | |
470 | ||
471 | for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++) | |
46380786 SC |
472 | if (unresettable_controller[i] == board_id) |
473 | return 0; | |
474 | return 1; | |
475 | } | |
476 | ||
477 | static int ctlr_is_soft_resettable(u32 board_id) | |
478 | { | |
479 | int i; | |
480 | ||
481 | for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++) | |
482 | if (soft_unresettable_controller[i] == board_id) | |
941b1cda SC |
483 | return 0; |
484 | return 1; | |
485 | } | |
486 | ||
46380786 SC |
487 | static int ctlr_is_resettable(u32 board_id) |
488 | { | |
489 | return ctlr_is_hard_resettable(board_id) || | |
490 | ctlr_is_soft_resettable(board_id); | |
491 | } | |
492 | ||
941b1cda SC |
493 | static ssize_t host_show_resettable(struct device *dev, |
494 | struct device_attribute *attr, char *buf) | |
495 | { | |
496 | struct ctlr_info *h; | |
497 | struct Scsi_Host *shost = class_to_shost(dev); | |
498 | ||
499 | h = shost_to_hba(shost); | |
46380786 | 500 | return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id)); |
941b1cda SC |
501 | } |
502 | ||
edd16368 SC |
503 | static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[]) |
504 | { | |
505 | return (scsi3addr[3] & 0xC0) == 0x40; | |
506 | } | |
507 | ||
f2ef0ce7 RE |
508 | static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6", |
509 | "1(+0)ADM", "UNKNOWN" | |
edd16368 | 510 | }; |
6b80b18f ST |
511 | #define HPSA_RAID_0 0 |
512 | #define HPSA_RAID_4 1 | |
513 | #define HPSA_RAID_1 2 /* also used for RAID 10 */ | |
514 | #define HPSA_RAID_5 3 /* also used for RAID 50 */ | |
515 | #define HPSA_RAID_51 4 | |
516 | #define HPSA_RAID_6 5 /* also used for RAID 60 */ | |
517 | #define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */ | |
edd16368 SC |
518 | #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1) |
519 | ||
520 | static ssize_t raid_level_show(struct device *dev, | |
521 | struct device_attribute *attr, char *buf) | |
522 | { | |
523 | ssize_t l = 0; | |
82a72c0a | 524 | unsigned char rlevel; |
edd16368 SC |
525 | struct ctlr_info *h; |
526 | struct scsi_device *sdev; | |
527 | struct hpsa_scsi_dev_t *hdev; | |
528 | unsigned long flags; | |
529 | ||
530 | sdev = to_scsi_device(dev); | |
531 | h = sdev_to_hba(sdev); | |
532 | spin_lock_irqsave(&h->lock, flags); | |
533 | hdev = sdev->hostdata; | |
534 | if (!hdev) { | |
535 | spin_unlock_irqrestore(&h->lock, flags); | |
536 | return -ENODEV; | |
537 | } | |
538 | ||
539 | /* Is this even a logical drive? */ | |
540 | if (!is_logical_dev_addr_mode(hdev->scsi3addr)) { | |
541 | spin_unlock_irqrestore(&h->lock, flags); | |
542 | l = snprintf(buf, PAGE_SIZE, "N/A\n"); | |
543 | return l; | |
544 | } | |
545 | ||
546 | rlevel = hdev->raid_level; | |
547 | spin_unlock_irqrestore(&h->lock, flags); | |
82a72c0a | 548 | if (rlevel > RAID_UNKNOWN) |
edd16368 SC |
549 | rlevel = RAID_UNKNOWN; |
550 | l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]); | |
551 | return l; | |
552 | } | |
553 | ||
554 | static ssize_t lunid_show(struct device *dev, | |
555 | struct device_attribute *attr, char *buf) | |
556 | { | |
557 | struct ctlr_info *h; | |
558 | struct scsi_device *sdev; | |
559 | struct hpsa_scsi_dev_t *hdev; | |
560 | unsigned long flags; | |
561 | unsigned char lunid[8]; | |
562 | ||
563 | sdev = to_scsi_device(dev); | |
564 | h = sdev_to_hba(sdev); | |
565 | spin_lock_irqsave(&h->lock, flags); | |
566 | hdev = sdev->hostdata; | |
567 | if (!hdev) { | |
568 | spin_unlock_irqrestore(&h->lock, flags); | |
569 | return -ENODEV; | |
570 | } | |
571 | memcpy(lunid, hdev->scsi3addr, sizeof(lunid)); | |
572 | spin_unlock_irqrestore(&h->lock, flags); | |
573 | return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
574 | lunid[0], lunid[1], lunid[2], lunid[3], | |
575 | lunid[4], lunid[5], lunid[6], lunid[7]); | |
576 | } | |
577 | ||
578 | static ssize_t unique_id_show(struct device *dev, | |
579 | struct device_attribute *attr, char *buf) | |
580 | { | |
581 | struct ctlr_info *h; | |
582 | struct scsi_device *sdev; | |
583 | struct hpsa_scsi_dev_t *hdev; | |
584 | unsigned long flags; | |
585 | unsigned char sn[16]; | |
586 | ||
587 | sdev = to_scsi_device(dev); | |
588 | h = sdev_to_hba(sdev); | |
589 | spin_lock_irqsave(&h->lock, flags); | |
590 | hdev = sdev->hostdata; | |
591 | if (!hdev) { | |
592 | spin_unlock_irqrestore(&h->lock, flags); | |
593 | return -ENODEV; | |
594 | } | |
595 | memcpy(sn, hdev->device_id, sizeof(sn)); | |
596 | spin_unlock_irqrestore(&h->lock, flags); | |
597 | return snprintf(buf, 16 * 2 + 2, | |
598 | "%02X%02X%02X%02X%02X%02X%02X%02X" | |
599 | "%02X%02X%02X%02X%02X%02X%02X%02X\n", | |
600 | sn[0], sn[1], sn[2], sn[3], | |
601 | sn[4], sn[5], sn[6], sn[7], | |
602 | sn[8], sn[9], sn[10], sn[11], | |
603 | sn[12], sn[13], sn[14], sn[15]); | |
604 | } | |
605 | ||
c1988684 ST |
606 | static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev, |
607 | struct device_attribute *attr, char *buf) | |
608 | { | |
609 | struct ctlr_info *h; | |
610 | struct scsi_device *sdev; | |
611 | struct hpsa_scsi_dev_t *hdev; | |
612 | unsigned long flags; | |
613 | int offload_enabled; | |
614 | ||
615 | sdev = to_scsi_device(dev); | |
616 | h = sdev_to_hba(sdev); | |
617 | spin_lock_irqsave(&h->lock, flags); | |
618 | hdev = sdev->hostdata; | |
619 | if (!hdev) { | |
620 | spin_unlock_irqrestore(&h->lock, flags); | |
621 | return -ENODEV; | |
622 | } | |
623 | offload_enabled = hdev->offload_enabled; | |
624 | spin_unlock_irqrestore(&h->lock, flags); | |
625 | return snprintf(buf, 20, "%d\n", offload_enabled); | |
626 | } | |
627 | ||
3f5eac3a SC |
628 | static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL); |
629 | static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL); | |
630 | static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL); | |
631 | static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan); | |
c1988684 ST |
632 | static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO, |
633 | host_show_hp_ssd_smart_path_enabled, NULL); | |
da0697bd ST |
634 | static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH, |
635 | host_show_hp_ssd_smart_path_status, | |
636 | host_store_hp_ssd_smart_path_status); | |
2ba8bfc8 SC |
637 | static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL, |
638 | host_store_raid_offload_debug); | |
3f5eac3a SC |
639 | static DEVICE_ATTR(firmware_revision, S_IRUGO, |
640 | host_show_firmware_revision, NULL); | |
641 | static DEVICE_ATTR(commands_outstanding, S_IRUGO, | |
642 | host_show_commands_outstanding, NULL); | |
643 | static DEVICE_ATTR(transport_mode, S_IRUGO, | |
644 | host_show_transport_mode, NULL); | |
941b1cda SC |
645 | static DEVICE_ATTR(resettable, S_IRUGO, |
646 | host_show_resettable, NULL); | |
3f5eac3a SC |
647 | |
648 | static struct device_attribute *hpsa_sdev_attrs[] = { | |
649 | &dev_attr_raid_level, | |
650 | &dev_attr_lunid, | |
651 | &dev_attr_unique_id, | |
c1988684 | 652 | &dev_attr_hp_ssd_smart_path_enabled, |
3f5eac3a SC |
653 | NULL, |
654 | }; | |
655 | ||
656 | static struct device_attribute *hpsa_shost_attrs[] = { | |
657 | &dev_attr_rescan, | |
658 | &dev_attr_firmware_revision, | |
659 | &dev_attr_commands_outstanding, | |
660 | &dev_attr_transport_mode, | |
941b1cda | 661 | &dev_attr_resettable, |
da0697bd | 662 | &dev_attr_hp_ssd_smart_path_status, |
2ba8bfc8 | 663 | &dev_attr_raid_offload_debug, |
3f5eac3a SC |
664 | NULL, |
665 | }; | |
666 | ||
667 | static struct scsi_host_template hpsa_driver_template = { | |
668 | .module = THIS_MODULE, | |
f79cfec6 SC |
669 | .name = HPSA, |
670 | .proc_name = HPSA, | |
3f5eac3a SC |
671 | .queuecommand = hpsa_scsi_queue_command, |
672 | .scan_start = hpsa_scan_start, | |
673 | .scan_finished = hpsa_scan_finished, | |
7c0a0229 | 674 | .change_queue_depth = hpsa_change_queue_depth, |
3f5eac3a SC |
675 | .this_id = -1, |
676 | .use_clustering = ENABLE_CLUSTERING, | |
75167d2c | 677 | .eh_abort_handler = hpsa_eh_abort_handler, |
3f5eac3a SC |
678 | .eh_device_reset_handler = hpsa_eh_device_reset_handler, |
679 | .ioctl = hpsa_ioctl, | |
680 | .slave_alloc = hpsa_slave_alloc, | |
681 | .slave_destroy = hpsa_slave_destroy, | |
682 | #ifdef CONFIG_COMPAT | |
683 | .compat_ioctl = hpsa_compat_ioctl, | |
684 | #endif | |
685 | .sdev_attrs = hpsa_sdev_attrs, | |
686 | .shost_attrs = hpsa_shost_attrs, | |
c0d6a4d1 | 687 | .max_sectors = 8192, |
54b2b50c | 688 | .no_write_same = 1, |
3f5eac3a SC |
689 | }; |
690 | ||
254f796b | 691 | static inline u32 next_command(struct ctlr_info *h, u8 q) |
3f5eac3a SC |
692 | { |
693 | u32 a; | |
072b0518 | 694 | struct reply_queue_buffer *rq = &h->reply_queue[q]; |
3f5eac3a | 695 | |
e1f7de0c MG |
696 | if (h->transMethod & CFGTBL_Trans_io_accel1) |
697 | return h->access.command_completed(h, q); | |
698 | ||
3f5eac3a | 699 | if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant))) |
254f796b | 700 | return h->access.command_completed(h, q); |
3f5eac3a | 701 | |
254f796b MG |
702 | if ((rq->head[rq->current_entry] & 1) == rq->wraparound) { |
703 | a = rq->head[rq->current_entry]; | |
704 | rq->current_entry++; | |
0cbf768e | 705 | atomic_dec(&h->commands_outstanding); |
3f5eac3a SC |
706 | } else { |
707 | a = FIFO_EMPTY; | |
708 | } | |
709 | /* Check for wraparound */ | |
254f796b MG |
710 | if (rq->current_entry == h->max_commands) { |
711 | rq->current_entry = 0; | |
712 | rq->wraparound ^= 1; | |
3f5eac3a SC |
713 | } |
714 | return a; | |
715 | } | |
716 | ||
c349775e ST |
717 | /* |
718 | * There are some special bits in the bus address of the | |
719 | * command that we have to set for the controller to know | |
720 | * how to process the command: | |
721 | * | |
722 | * Normal performant mode: | |
723 | * bit 0: 1 means performant mode, 0 means simple mode. | |
724 | * bits 1-3 = block fetch table entry | |
725 | * bits 4-6 = command type (== 0) | |
726 | * | |
727 | * ioaccel1 mode: | |
728 | * bit 0 = "performant mode" bit. | |
729 | * bits 1-3 = block fetch table entry | |
730 | * bits 4-6 = command type (== 110) | |
731 | * (command type is needed because ioaccel1 mode | |
732 | * commands are submitted through the same register as normal | |
733 | * mode commands, so this is how the controller knows whether | |
734 | * the command is normal mode or ioaccel1 mode.) | |
735 | * | |
736 | * ioaccel2 mode: | |
737 | * bit 0 = "performant mode" bit. | |
738 | * bits 1-4 = block fetch table entry (note extra bit) | |
739 | * bits 4-6 = not needed, because ioaccel2 mode has | |
740 | * a separate special register for submitting commands. | |
741 | */ | |
742 | ||
3f5eac3a SC |
743 | /* set_performant_mode: Modify the tag for cciss performant |
744 | * set bit 0 for pull model, bits 3-1 for block fetch | |
745 | * register number | |
746 | */ | |
747 | static void set_performant_mode(struct ctlr_info *h, struct CommandList *c) | |
748 | { | |
254f796b | 749 | if (likely(h->transMethod & CFGTBL_Trans_Performant)) { |
3f5eac3a | 750 | c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1); |
eee0f03a | 751 | if (likely(h->msix_vector > 0)) |
254f796b | 752 | c->Header.ReplyQueue = |
804a5cb5 | 753 | raw_smp_processor_id() % h->nreply_queues; |
254f796b | 754 | } |
3f5eac3a SC |
755 | } |
756 | ||
c349775e ST |
757 | static void set_ioaccel1_performant_mode(struct ctlr_info *h, |
758 | struct CommandList *c) | |
759 | { | |
760 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; | |
761 | ||
762 | /* Tell the controller to post the reply to the queue for this | |
763 | * processor. This seems to give the best I/O throughput. | |
764 | */ | |
765 | cp->ReplyQueue = smp_processor_id() % h->nreply_queues; | |
766 | /* Set the bits in the address sent down to include: | |
767 | * - performant mode bit (bit 0) | |
768 | * - pull count (bits 1-3) | |
769 | * - command type (bits 4-6) | |
770 | */ | |
771 | c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) | | |
772 | IOACCEL1_BUSADDR_CMDTYPE; | |
773 | } | |
774 | ||
775 | static void set_ioaccel2_performant_mode(struct ctlr_info *h, | |
776 | struct CommandList *c) | |
777 | { | |
778 | struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
779 | ||
780 | /* Tell the controller to post the reply to the queue for this | |
781 | * processor. This seems to give the best I/O throughput. | |
782 | */ | |
783 | cp->reply_queue = smp_processor_id() % h->nreply_queues; | |
784 | /* Set the bits in the address sent down to include: | |
785 | * - performant mode bit not used in ioaccel mode 2 | |
786 | * - pull count (bits 0-3) | |
787 | * - command type isn't needed for ioaccel2 | |
788 | */ | |
789 | c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]); | |
790 | } | |
791 | ||
e85c5974 SC |
792 | static int is_firmware_flash_cmd(u8 *cdb) |
793 | { | |
794 | return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE; | |
795 | } | |
796 | ||
797 | /* | |
798 | * During firmware flash, the heartbeat register may not update as frequently | |
799 | * as it should. So we dial down lockup detection during firmware flash. and | |
800 | * dial it back up when firmware flash completes. | |
801 | */ | |
802 | #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ) | |
803 | #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ) | |
804 | static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h, | |
805 | struct CommandList *c) | |
806 | { | |
807 | if (!is_firmware_flash_cmd(c->Request.CDB)) | |
808 | return; | |
809 | atomic_inc(&h->firmware_flash_in_progress); | |
810 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH; | |
811 | } | |
812 | ||
813 | static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h, | |
814 | struct CommandList *c) | |
815 | { | |
816 | if (is_firmware_flash_cmd(c->Request.CDB) && | |
817 | atomic_dec_and_test(&h->firmware_flash_in_progress)) | |
818 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; | |
819 | } | |
820 | ||
3f5eac3a SC |
821 | static void enqueue_cmd_and_start_io(struct ctlr_info *h, |
822 | struct CommandList *c) | |
823 | { | |
c349775e ST |
824 | switch (c->cmd_type) { |
825 | case CMD_IOACCEL1: | |
826 | set_ioaccel1_performant_mode(h, c); | |
827 | break; | |
828 | case CMD_IOACCEL2: | |
829 | set_ioaccel2_performant_mode(h, c); | |
830 | break; | |
831 | default: | |
832 | set_performant_mode(h, c); | |
833 | } | |
e85c5974 | 834 | dial_down_lockup_detection_during_fw_flash(h, c); |
f2405db8 DB |
835 | atomic_inc(&h->commands_outstanding); |
836 | h->access.submit_command(h, c); | |
3f5eac3a SC |
837 | } |
838 | ||
839 | static inline int is_hba_lunid(unsigned char scsi3addr[]) | |
840 | { | |
841 | return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0; | |
842 | } | |
843 | ||
844 | static inline int is_scsi_rev_5(struct ctlr_info *h) | |
845 | { | |
846 | if (!h->hba_inquiry_data) | |
847 | return 0; | |
848 | if ((h->hba_inquiry_data[2] & 0x07) == 5) | |
849 | return 1; | |
850 | return 0; | |
851 | } | |
852 | ||
edd16368 SC |
853 | static int hpsa_find_target_lun(struct ctlr_info *h, |
854 | unsigned char scsi3addr[], int bus, int *target, int *lun) | |
855 | { | |
856 | /* finds an unused bus, target, lun for a new physical device | |
857 | * assumes h->devlock is held | |
858 | */ | |
859 | int i, found = 0; | |
cfe5badc | 860 | DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES); |
edd16368 | 861 | |
263d9401 | 862 | bitmap_zero(lun_taken, HPSA_MAX_DEVICES); |
edd16368 SC |
863 | |
864 | for (i = 0; i < h->ndevices; i++) { | |
865 | if (h->dev[i]->bus == bus && h->dev[i]->target != -1) | |
263d9401 | 866 | __set_bit(h->dev[i]->target, lun_taken); |
edd16368 SC |
867 | } |
868 | ||
263d9401 AM |
869 | i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES); |
870 | if (i < HPSA_MAX_DEVICES) { | |
871 | /* *bus = 1; */ | |
872 | *target = i; | |
873 | *lun = 0; | |
874 | found = 1; | |
edd16368 SC |
875 | } |
876 | return !found; | |
877 | } | |
878 | ||
879 | /* Add an entry into h->dev[] array. */ | |
880 | static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno, | |
881 | struct hpsa_scsi_dev_t *device, | |
882 | struct hpsa_scsi_dev_t *added[], int *nadded) | |
883 | { | |
884 | /* assumes h->devlock is held */ | |
885 | int n = h->ndevices; | |
886 | int i; | |
887 | unsigned char addr1[8], addr2[8]; | |
888 | struct hpsa_scsi_dev_t *sd; | |
889 | ||
cfe5badc | 890 | if (n >= HPSA_MAX_DEVICES) { |
edd16368 SC |
891 | dev_err(&h->pdev->dev, "too many devices, some will be " |
892 | "inaccessible.\n"); | |
893 | return -1; | |
894 | } | |
895 | ||
896 | /* physical devices do not have lun or target assigned until now. */ | |
897 | if (device->lun != -1) | |
898 | /* Logical device, lun is already assigned. */ | |
899 | goto lun_assigned; | |
900 | ||
901 | /* If this device a non-zero lun of a multi-lun device | |
902 | * byte 4 of the 8-byte LUN addr will contain the logical | |
2b08b3e9 | 903 | * unit no, zero otherwise. |
edd16368 SC |
904 | */ |
905 | if (device->scsi3addr[4] == 0) { | |
906 | /* This is not a non-zero lun of a multi-lun device */ | |
907 | if (hpsa_find_target_lun(h, device->scsi3addr, | |
908 | device->bus, &device->target, &device->lun) != 0) | |
909 | return -1; | |
910 | goto lun_assigned; | |
911 | } | |
912 | ||
913 | /* This is a non-zero lun of a multi-lun device. | |
914 | * Search through our list and find the device which | |
915 | * has the same 8 byte LUN address, excepting byte 4. | |
916 | * Assign the same bus and target for this new LUN. | |
917 | * Use the logical unit number from the firmware. | |
918 | */ | |
919 | memcpy(addr1, device->scsi3addr, 8); | |
920 | addr1[4] = 0; | |
921 | for (i = 0; i < n; i++) { | |
922 | sd = h->dev[i]; | |
923 | memcpy(addr2, sd->scsi3addr, 8); | |
924 | addr2[4] = 0; | |
925 | /* differ only in byte 4? */ | |
926 | if (memcmp(addr1, addr2, 8) == 0) { | |
927 | device->bus = sd->bus; | |
928 | device->target = sd->target; | |
929 | device->lun = device->scsi3addr[4]; | |
930 | break; | |
931 | } | |
932 | } | |
933 | if (device->lun == -1) { | |
934 | dev_warn(&h->pdev->dev, "physical device with no LUN=0," | |
935 | " suspect firmware bug or unsupported hardware " | |
936 | "configuration.\n"); | |
937 | return -1; | |
938 | } | |
939 | ||
940 | lun_assigned: | |
941 | ||
942 | h->dev[n] = device; | |
943 | h->ndevices++; | |
944 | added[*nadded] = device; | |
945 | (*nadded)++; | |
946 | ||
947 | /* initially, (before registering with scsi layer) we don't | |
948 | * know our hostno and we don't want to print anything first | |
949 | * time anyway (the scsi layer's inquiries will show that info) | |
950 | */ | |
951 | /* if (hostno != -1) */ | |
952 | dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n", | |
953 | scsi_device_type(device->devtype), hostno, | |
954 | device->bus, device->target, device->lun); | |
955 | return 0; | |
956 | } | |
957 | ||
bd9244f7 ST |
958 | /* Update an entry in h->dev[] array. */ |
959 | static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno, | |
960 | int entry, struct hpsa_scsi_dev_t *new_entry) | |
961 | { | |
962 | /* assumes h->devlock is held */ | |
963 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); | |
964 | ||
965 | /* Raid level changed. */ | |
966 | h->dev[entry]->raid_level = new_entry->raid_level; | |
250fb125 | 967 | |
03383736 DB |
968 | /* Raid offload parameters changed. Careful about the ordering. */ |
969 | if (new_entry->offload_config && new_entry->offload_enabled) { | |
970 | /* | |
971 | * if drive is newly offload_enabled, we want to copy the | |
972 | * raid map data first. If previously offload_enabled and | |
973 | * offload_config were set, raid map data had better be | |
974 | * the same as it was before. if raid map data is changed | |
975 | * then it had better be the case that | |
976 | * h->dev[entry]->offload_enabled is currently 0. | |
977 | */ | |
978 | h->dev[entry]->raid_map = new_entry->raid_map; | |
979 | h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle; | |
980 | wmb(); /* ensure raid map updated prior to ->offload_enabled */ | |
981 | } | |
250fb125 | 982 | h->dev[entry]->offload_config = new_entry->offload_config; |
9fb0de2d | 983 | h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror; |
03383736 DB |
984 | h->dev[entry]->offload_enabled = new_entry->offload_enabled; |
985 | h->dev[entry]->queue_depth = new_entry->queue_depth; | |
250fb125 | 986 | |
bd9244f7 ST |
987 | dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n", |
988 | scsi_device_type(new_entry->devtype), hostno, new_entry->bus, | |
989 | new_entry->target, new_entry->lun); | |
990 | } | |
991 | ||
2a8ccf31 SC |
992 | /* Replace an entry from h->dev[] array. */ |
993 | static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno, | |
994 | int entry, struct hpsa_scsi_dev_t *new_entry, | |
995 | struct hpsa_scsi_dev_t *added[], int *nadded, | |
996 | struct hpsa_scsi_dev_t *removed[], int *nremoved) | |
997 | { | |
998 | /* assumes h->devlock is held */ | |
cfe5badc | 999 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); |
2a8ccf31 SC |
1000 | removed[*nremoved] = h->dev[entry]; |
1001 | (*nremoved)++; | |
01350d05 SC |
1002 | |
1003 | /* | |
1004 | * New physical devices won't have target/lun assigned yet | |
1005 | * so we need to preserve the values in the slot we are replacing. | |
1006 | */ | |
1007 | if (new_entry->target == -1) { | |
1008 | new_entry->target = h->dev[entry]->target; | |
1009 | new_entry->lun = h->dev[entry]->lun; | |
1010 | } | |
1011 | ||
2a8ccf31 SC |
1012 | h->dev[entry] = new_entry; |
1013 | added[*nadded] = new_entry; | |
1014 | (*nadded)++; | |
1015 | dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n", | |
1016 | scsi_device_type(new_entry->devtype), hostno, new_entry->bus, | |
1017 | new_entry->target, new_entry->lun); | |
1018 | } | |
1019 | ||
edd16368 SC |
1020 | /* Remove an entry from h->dev[] array. */ |
1021 | static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry, | |
1022 | struct hpsa_scsi_dev_t *removed[], int *nremoved) | |
1023 | { | |
1024 | /* assumes h->devlock is held */ | |
1025 | int i; | |
1026 | struct hpsa_scsi_dev_t *sd; | |
1027 | ||
cfe5badc | 1028 | BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES); |
edd16368 SC |
1029 | |
1030 | sd = h->dev[entry]; | |
1031 | removed[*nremoved] = h->dev[entry]; | |
1032 | (*nremoved)++; | |
1033 | ||
1034 | for (i = entry; i < h->ndevices-1; i++) | |
1035 | h->dev[i] = h->dev[i+1]; | |
1036 | h->ndevices--; | |
1037 | dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n", | |
1038 | scsi_device_type(sd->devtype), hostno, sd->bus, sd->target, | |
1039 | sd->lun); | |
1040 | } | |
1041 | ||
1042 | #define SCSI3ADDR_EQ(a, b) ( \ | |
1043 | (a)[7] == (b)[7] && \ | |
1044 | (a)[6] == (b)[6] && \ | |
1045 | (a)[5] == (b)[5] && \ | |
1046 | (a)[4] == (b)[4] && \ | |
1047 | (a)[3] == (b)[3] && \ | |
1048 | (a)[2] == (b)[2] && \ | |
1049 | (a)[1] == (b)[1] && \ | |
1050 | (a)[0] == (b)[0]) | |
1051 | ||
1052 | static void fixup_botched_add(struct ctlr_info *h, | |
1053 | struct hpsa_scsi_dev_t *added) | |
1054 | { | |
1055 | /* called when scsi_add_device fails in order to re-adjust | |
1056 | * h->dev[] to match the mid layer's view. | |
1057 | */ | |
1058 | unsigned long flags; | |
1059 | int i, j; | |
1060 | ||
1061 | spin_lock_irqsave(&h->lock, flags); | |
1062 | for (i = 0; i < h->ndevices; i++) { | |
1063 | if (h->dev[i] == added) { | |
1064 | for (j = i; j < h->ndevices-1; j++) | |
1065 | h->dev[j] = h->dev[j+1]; | |
1066 | h->ndevices--; | |
1067 | break; | |
1068 | } | |
1069 | } | |
1070 | spin_unlock_irqrestore(&h->lock, flags); | |
1071 | kfree(added); | |
1072 | } | |
1073 | ||
1074 | static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1, | |
1075 | struct hpsa_scsi_dev_t *dev2) | |
1076 | { | |
edd16368 SC |
1077 | /* we compare everything except lun and target as these |
1078 | * are not yet assigned. Compare parts likely | |
1079 | * to differ first | |
1080 | */ | |
1081 | if (memcmp(dev1->scsi3addr, dev2->scsi3addr, | |
1082 | sizeof(dev1->scsi3addr)) != 0) | |
1083 | return 0; | |
1084 | if (memcmp(dev1->device_id, dev2->device_id, | |
1085 | sizeof(dev1->device_id)) != 0) | |
1086 | return 0; | |
1087 | if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0) | |
1088 | return 0; | |
1089 | if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0) | |
1090 | return 0; | |
edd16368 SC |
1091 | if (dev1->devtype != dev2->devtype) |
1092 | return 0; | |
edd16368 SC |
1093 | if (dev1->bus != dev2->bus) |
1094 | return 0; | |
1095 | return 1; | |
1096 | } | |
1097 | ||
bd9244f7 ST |
1098 | static inline int device_updated(struct hpsa_scsi_dev_t *dev1, |
1099 | struct hpsa_scsi_dev_t *dev2) | |
1100 | { | |
1101 | /* Device attributes that can change, but don't mean | |
1102 | * that the device is a different device, nor that the OS | |
1103 | * needs to be told anything about the change. | |
1104 | */ | |
1105 | if (dev1->raid_level != dev2->raid_level) | |
1106 | return 1; | |
250fb125 SC |
1107 | if (dev1->offload_config != dev2->offload_config) |
1108 | return 1; | |
1109 | if (dev1->offload_enabled != dev2->offload_enabled) | |
1110 | return 1; | |
03383736 DB |
1111 | if (dev1->queue_depth != dev2->queue_depth) |
1112 | return 1; | |
bd9244f7 ST |
1113 | return 0; |
1114 | } | |
1115 | ||
edd16368 SC |
1116 | /* Find needle in haystack. If exact match found, return DEVICE_SAME, |
1117 | * and return needle location in *index. If scsi3addr matches, but not | |
1118 | * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle | |
bd9244f7 ST |
1119 | * location in *index. |
1120 | * In the case of a minor device attribute change, such as RAID level, just | |
1121 | * return DEVICE_UPDATED, along with the updated device's location in index. | |
1122 | * If needle not found, return DEVICE_NOT_FOUND. | |
edd16368 SC |
1123 | */ |
1124 | static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle, | |
1125 | struct hpsa_scsi_dev_t *haystack[], int haystack_size, | |
1126 | int *index) | |
1127 | { | |
1128 | int i; | |
1129 | #define DEVICE_NOT_FOUND 0 | |
1130 | #define DEVICE_CHANGED 1 | |
1131 | #define DEVICE_SAME 2 | |
bd9244f7 | 1132 | #define DEVICE_UPDATED 3 |
edd16368 | 1133 | for (i = 0; i < haystack_size; i++) { |
23231048 SC |
1134 | if (haystack[i] == NULL) /* previously removed. */ |
1135 | continue; | |
edd16368 SC |
1136 | if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) { |
1137 | *index = i; | |
bd9244f7 ST |
1138 | if (device_is_the_same(needle, haystack[i])) { |
1139 | if (device_updated(needle, haystack[i])) | |
1140 | return DEVICE_UPDATED; | |
edd16368 | 1141 | return DEVICE_SAME; |
bd9244f7 | 1142 | } else { |
9846590e SC |
1143 | /* Keep offline devices offline */ |
1144 | if (needle->volume_offline) | |
1145 | return DEVICE_NOT_FOUND; | |
edd16368 | 1146 | return DEVICE_CHANGED; |
bd9244f7 | 1147 | } |
edd16368 SC |
1148 | } |
1149 | } | |
1150 | *index = -1; | |
1151 | return DEVICE_NOT_FOUND; | |
1152 | } | |
1153 | ||
9846590e SC |
1154 | static void hpsa_monitor_offline_device(struct ctlr_info *h, |
1155 | unsigned char scsi3addr[]) | |
1156 | { | |
1157 | struct offline_device_entry *device; | |
1158 | unsigned long flags; | |
1159 | ||
1160 | /* Check to see if device is already on the list */ | |
1161 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
1162 | list_for_each_entry(device, &h->offline_device_list, offline_list) { | |
1163 | if (memcmp(device->scsi3addr, scsi3addr, | |
1164 | sizeof(device->scsi3addr)) == 0) { | |
1165 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
1166 | return; | |
1167 | } | |
1168 | } | |
1169 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
1170 | ||
1171 | /* Device is not on the list, add it. */ | |
1172 | device = kmalloc(sizeof(*device), GFP_KERNEL); | |
1173 | if (!device) { | |
1174 | dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__); | |
1175 | return; | |
1176 | } | |
1177 | memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr)); | |
1178 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
1179 | list_add_tail(&device->offline_list, &h->offline_device_list); | |
1180 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
1181 | } | |
1182 | ||
1183 | /* Print a message explaining various offline volume states */ | |
1184 | static void hpsa_show_volume_status(struct ctlr_info *h, | |
1185 | struct hpsa_scsi_dev_t *sd) | |
1186 | { | |
1187 | if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED) | |
1188 | dev_info(&h->pdev->dev, | |
1189 | "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n", | |
1190 | h->scsi_host->host_no, | |
1191 | sd->bus, sd->target, sd->lun); | |
1192 | switch (sd->volume_offline) { | |
1193 | case HPSA_LV_OK: | |
1194 | break; | |
1195 | case HPSA_LV_UNDERGOING_ERASE: | |
1196 | dev_info(&h->pdev->dev, | |
1197 | "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n", | |
1198 | h->scsi_host->host_no, | |
1199 | sd->bus, sd->target, sd->lun); | |
1200 | break; | |
1201 | case HPSA_LV_UNDERGOING_RPI: | |
1202 | dev_info(&h->pdev->dev, | |
1203 | "C%d:B%d:T%d:L%d Volume is undergoing rapid parity initialization process.\n", | |
1204 | h->scsi_host->host_no, | |
1205 | sd->bus, sd->target, sd->lun); | |
1206 | break; | |
1207 | case HPSA_LV_PENDING_RPI: | |
1208 | dev_info(&h->pdev->dev, | |
1209 | "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n", | |
1210 | h->scsi_host->host_no, | |
1211 | sd->bus, sd->target, sd->lun); | |
1212 | break; | |
1213 | case HPSA_LV_ENCRYPTED_NO_KEY: | |
1214 | dev_info(&h->pdev->dev, | |
1215 | "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n", | |
1216 | h->scsi_host->host_no, | |
1217 | sd->bus, sd->target, sd->lun); | |
1218 | break; | |
1219 | case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER: | |
1220 | dev_info(&h->pdev->dev, | |
1221 | "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n", | |
1222 | h->scsi_host->host_no, | |
1223 | sd->bus, sd->target, sd->lun); | |
1224 | break; | |
1225 | case HPSA_LV_UNDERGOING_ENCRYPTION: | |
1226 | dev_info(&h->pdev->dev, | |
1227 | "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n", | |
1228 | h->scsi_host->host_no, | |
1229 | sd->bus, sd->target, sd->lun); | |
1230 | break; | |
1231 | case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING: | |
1232 | dev_info(&h->pdev->dev, | |
1233 | "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n", | |
1234 | h->scsi_host->host_no, | |
1235 | sd->bus, sd->target, sd->lun); | |
1236 | break; | |
1237 | case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER: | |
1238 | dev_info(&h->pdev->dev, | |
1239 | "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n", | |
1240 | h->scsi_host->host_no, | |
1241 | sd->bus, sd->target, sd->lun); | |
1242 | break; | |
1243 | case HPSA_LV_PENDING_ENCRYPTION: | |
1244 | dev_info(&h->pdev->dev, | |
1245 | "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n", | |
1246 | h->scsi_host->host_no, | |
1247 | sd->bus, sd->target, sd->lun); | |
1248 | break; | |
1249 | case HPSA_LV_PENDING_ENCRYPTION_REKEYING: | |
1250 | dev_info(&h->pdev->dev, | |
1251 | "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n", | |
1252 | h->scsi_host->host_no, | |
1253 | sd->bus, sd->target, sd->lun); | |
1254 | break; | |
1255 | } | |
1256 | } | |
1257 | ||
03383736 DB |
1258 | /* |
1259 | * Figure the list of physical drive pointers for a logical drive with | |
1260 | * raid offload configured. | |
1261 | */ | |
1262 | static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h, | |
1263 | struct hpsa_scsi_dev_t *dev[], int ndevices, | |
1264 | struct hpsa_scsi_dev_t *logical_drive) | |
1265 | { | |
1266 | struct raid_map_data *map = &logical_drive->raid_map; | |
1267 | struct raid_map_disk_data *dd = &map->data[0]; | |
1268 | int i, j; | |
1269 | int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) + | |
1270 | le16_to_cpu(map->metadata_disks_per_row); | |
1271 | int nraid_map_entries = le16_to_cpu(map->row_cnt) * | |
1272 | le16_to_cpu(map->layout_map_count) * | |
1273 | total_disks_per_row; | |
1274 | int nphys_disk = le16_to_cpu(map->layout_map_count) * | |
1275 | total_disks_per_row; | |
1276 | int qdepth; | |
1277 | ||
1278 | if (nraid_map_entries > RAID_MAP_MAX_ENTRIES) | |
1279 | nraid_map_entries = RAID_MAP_MAX_ENTRIES; | |
1280 | ||
1281 | qdepth = 0; | |
1282 | for (i = 0; i < nraid_map_entries; i++) { | |
1283 | logical_drive->phys_disk[i] = NULL; | |
1284 | if (!logical_drive->offload_config) | |
1285 | continue; | |
1286 | for (j = 0; j < ndevices; j++) { | |
1287 | if (dev[j]->devtype != TYPE_DISK) | |
1288 | continue; | |
1289 | if (is_logical_dev_addr_mode(dev[j]->scsi3addr)) | |
1290 | continue; | |
1291 | if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle) | |
1292 | continue; | |
1293 | ||
1294 | logical_drive->phys_disk[i] = dev[j]; | |
1295 | if (i < nphys_disk) | |
1296 | qdepth = min(h->nr_cmds, qdepth + | |
1297 | logical_drive->phys_disk[i]->queue_depth); | |
1298 | break; | |
1299 | } | |
1300 | ||
1301 | /* | |
1302 | * This can happen if a physical drive is removed and | |
1303 | * the logical drive is degraded. In that case, the RAID | |
1304 | * map data will refer to a physical disk which isn't actually | |
1305 | * present. And in that case offload_enabled should already | |
1306 | * be 0, but we'll turn it off here just in case | |
1307 | */ | |
1308 | if (!logical_drive->phys_disk[i]) { | |
1309 | logical_drive->offload_enabled = 0; | |
1310 | logical_drive->queue_depth = h->nr_cmds; | |
1311 | } | |
1312 | } | |
1313 | if (nraid_map_entries) | |
1314 | /* | |
1315 | * This is correct for reads, too high for full stripe writes, | |
1316 | * way too high for partial stripe writes | |
1317 | */ | |
1318 | logical_drive->queue_depth = qdepth; | |
1319 | else | |
1320 | logical_drive->queue_depth = h->nr_cmds; | |
1321 | } | |
1322 | ||
1323 | static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h, | |
1324 | struct hpsa_scsi_dev_t *dev[], int ndevices) | |
1325 | { | |
1326 | int i; | |
1327 | ||
1328 | for (i = 0; i < ndevices; i++) { | |
1329 | if (dev[i]->devtype != TYPE_DISK) | |
1330 | continue; | |
1331 | if (!is_logical_dev_addr_mode(dev[i]->scsi3addr)) | |
1332 | continue; | |
1333 | hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]); | |
1334 | } | |
1335 | } | |
1336 | ||
4967bd3e | 1337 | static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno, |
edd16368 SC |
1338 | struct hpsa_scsi_dev_t *sd[], int nsds) |
1339 | { | |
1340 | /* sd contains scsi3 addresses and devtypes, and inquiry | |
1341 | * data. This function takes what's in sd to be the current | |
1342 | * reality and updates h->dev[] to reflect that reality. | |
1343 | */ | |
1344 | int i, entry, device_change, changes = 0; | |
1345 | struct hpsa_scsi_dev_t *csd; | |
1346 | unsigned long flags; | |
1347 | struct hpsa_scsi_dev_t **added, **removed; | |
1348 | int nadded, nremoved; | |
1349 | struct Scsi_Host *sh = NULL; | |
1350 | ||
cfe5badc ST |
1351 | added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL); |
1352 | removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL); | |
edd16368 SC |
1353 | |
1354 | if (!added || !removed) { | |
1355 | dev_warn(&h->pdev->dev, "out of memory in " | |
1356 | "adjust_hpsa_scsi_table\n"); | |
1357 | goto free_and_out; | |
1358 | } | |
1359 | ||
1360 | spin_lock_irqsave(&h->devlock, flags); | |
1361 | ||
1362 | /* find any devices in h->dev[] that are not in | |
1363 | * sd[] and remove them from h->dev[], and for any | |
1364 | * devices which have changed, remove the old device | |
1365 | * info and add the new device info. | |
bd9244f7 ST |
1366 | * If minor device attributes change, just update |
1367 | * the existing device structure. | |
edd16368 SC |
1368 | */ |
1369 | i = 0; | |
1370 | nremoved = 0; | |
1371 | nadded = 0; | |
1372 | while (i < h->ndevices) { | |
1373 | csd = h->dev[i]; | |
1374 | device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry); | |
1375 | if (device_change == DEVICE_NOT_FOUND) { | |
1376 | changes++; | |
1377 | hpsa_scsi_remove_entry(h, hostno, i, | |
1378 | removed, &nremoved); | |
1379 | continue; /* remove ^^^, hence i not incremented */ | |
1380 | } else if (device_change == DEVICE_CHANGED) { | |
1381 | changes++; | |
2a8ccf31 SC |
1382 | hpsa_scsi_replace_entry(h, hostno, i, sd[entry], |
1383 | added, &nadded, removed, &nremoved); | |
c7f172dc SC |
1384 | /* Set it to NULL to prevent it from being freed |
1385 | * at the bottom of hpsa_update_scsi_devices() | |
1386 | */ | |
1387 | sd[entry] = NULL; | |
bd9244f7 ST |
1388 | } else if (device_change == DEVICE_UPDATED) { |
1389 | hpsa_scsi_update_entry(h, hostno, i, sd[entry]); | |
edd16368 SC |
1390 | } |
1391 | i++; | |
1392 | } | |
1393 | ||
1394 | /* Now, make sure every device listed in sd[] is also | |
1395 | * listed in h->dev[], adding them if they aren't found | |
1396 | */ | |
1397 | ||
1398 | for (i = 0; i < nsds; i++) { | |
1399 | if (!sd[i]) /* if already added above. */ | |
1400 | continue; | |
9846590e SC |
1401 | |
1402 | /* Don't add devices which are NOT READY, FORMAT IN PROGRESS | |
1403 | * as the SCSI mid-layer does not handle such devices well. | |
1404 | * It relentlessly loops sending TUR at 3Hz, then READ(10) | |
1405 | * at 160Hz, and prevents the system from coming up. | |
1406 | */ | |
1407 | if (sd[i]->volume_offline) { | |
1408 | hpsa_show_volume_status(h, sd[i]); | |
1409 | dev_info(&h->pdev->dev, "c%db%dt%dl%d: temporarily offline\n", | |
1410 | h->scsi_host->host_no, | |
1411 | sd[i]->bus, sd[i]->target, sd[i]->lun); | |
1412 | continue; | |
1413 | } | |
1414 | ||
edd16368 SC |
1415 | device_change = hpsa_scsi_find_entry(sd[i], h->dev, |
1416 | h->ndevices, &entry); | |
1417 | if (device_change == DEVICE_NOT_FOUND) { | |
1418 | changes++; | |
1419 | if (hpsa_scsi_add_entry(h, hostno, sd[i], | |
1420 | added, &nadded) != 0) | |
1421 | break; | |
1422 | sd[i] = NULL; /* prevent from being freed later. */ | |
1423 | } else if (device_change == DEVICE_CHANGED) { | |
1424 | /* should never happen... */ | |
1425 | changes++; | |
1426 | dev_warn(&h->pdev->dev, | |
1427 | "device unexpectedly changed.\n"); | |
1428 | /* but if it does happen, we just ignore that device */ | |
1429 | } | |
1430 | } | |
1431 | spin_unlock_irqrestore(&h->devlock, flags); | |
1432 | ||
9846590e SC |
1433 | /* Monitor devices which are in one of several NOT READY states to be |
1434 | * brought online later. This must be done without holding h->devlock, | |
1435 | * so don't touch h->dev[] | |
1436 | */ | |
1437 | for (i = 0; i < nsds; i++) { | |
1438 | if (!sd[i]) /* if already added above. */ | |
1439 | continue; | |
1440 | if (sd[i]->volume_offline) | |
1441 | hpsa_monitor_offline_device(h, sd[i]->scsi3addr); | |
1442 | } | |
1443 | ||
edd16368 SC |
1444 | /* Don't notify scsi mid layer of any changes the first time through |
1445 | * (or if there are no changes) scsi_scan_host will do it later the | |
1446 | * first time through. | |
1447 | */ | |
1448 | if (hostno == -1 || !changes) | |
1449 | goto free_and_out; | |
1450 | ||
1451 | sh = h->scsi_host; | |
1452 | /* Notify scsi mid layer of any removed devices */ | |
1453 | for (i = 0; i < nremoved; i++) { | |
1454 | struct scsi_device *sdev = | |
1455 | scsi_device_lookup(sh, removed[i]->bus, | |
1456 | removed[i]->target, removed[i]->lun); | |
1457 | if (sdev != NULL) { | |
1458 | scsi_remove_device(sdev); | |
1459 | scsi_device_put(sdev); | |
1460 | } else { | |
1461 | /* We don't expect to get here. | |
1462 | * future cmds to this device will get selection | |
1463 | * timeout as if the device was gone. | |
1464 | */ | |
1465 | dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d " | |
1466 | " for removal.", hostno, removed[i]->bus, | |
1467 | removed[i]->target, removed[i]->lun); | |
1468 | } | |
1469 | kfree(removed[i]); | |
1470 | removed[i] = NULL; | |
1471 | } | |
1472 | ||
1473 | /* Notify scsi mid layer of any added devices */ | |
1474 | for (i = 0; i < nadded; i++) { | |
1475 | if (scsi_add_device(sh, added[i]->bus, | |
1476 | added[i]->target, added[i]->lun) == 0) | |
1477 | continue; | |
1478 | dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, " | |
1479 | "device not added.\n", hostno, added[i]->bus, | |
1480 | added[i]->target, added[i]->lun); | |
1481 | /* now we have to remove it from h->dev, | |
1482 | * since it didn't get added to scsi mid layer | |
1483 | */ | |
1484 | fixup_botched_add(h, added[i]); | |
1485 | } | |
1486 | ||
1487 | free_and_out: | |
1488 | kfree(added); | |
1489 | kfree(removed); | |
edd16368 SC |
1490 | } |
1491 | ||
1492 | /* | |
9e03aa2f | 1493 | * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t * |
edd16368 SC |
1494 | * Assume's h->devlock is held. |
1495 | */ | |
1496 | static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h, | |
1497 | int bus, int target, int lun) | |
1498 | { | |
1499 | int i; | |
1500 | struct hpsa_scsi_dev_t *sd; | |
1501 | ||
1502 | for (i = 0; i < h->ndevices; i++) { | |
1503 | sd = h->dev[i]; | |
1504 | if (sd->bus == bus && sd->target == target && sd->lun == lun) | |
1505 | return sd; | |
1506 | } | |
1507 | return NULL; | |
1508 | } | |
1509 | ||
1510 | /* link sdev->hostdata to our per-device structure. */ | |
1511 | static int hpsa_slave_alloc(struct scsi_device *sdev) | |
1512 | { | |
1513 | struct hpsa_scsi_dev_t *sd; | |
1514 | unsigned long flags; | |
1515 | struct ctlr_info *h; | |
1516 | ||
1517 | h = sdev_to_hba(sdev); | |
1518 | spin_lock_irqsave(&h->devlock, flags); | |
1519 | sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev), | |
1520 | sdev_id(sdev), sdev->lun); | |
03383736 | 1521 | if (sd != NULL) { |
edd16368 | 1522 | sdev->hostdata = sd; |
03383736 DB |
1523 | if (sd->queue_depth) |
1524 | scsi_change_queue_depth(sdev, sd->queue_depth); | |
1525 | atomic_set(&sd->ioaccel_cmds_out, 0); | |
1526 | } | |
edd16368 SC |
1527 | spin_unlock_irqrestore(&h->devlock, flags); |
1528 | return 0; | |
1529 | } | |
1530 | ||
1531 | static void hpsa_slave_destroy(struct scsi_device *sdev) | |
1532 | { | |
bcc44255 | 1533 | /* nothing to do. */ |
edd16368 SC |
1534 | } |
1535 | ||
33a2ffce SC |
1536 | static void hpsa_free_sg_chain_blocks(struct ctlr_info *h) |
1537 | { | |
1538 | int i; | |
1539 | ||
1540 | if (!h->cmd_sg_list) | |
1541 | return; | |
1542 | for (i = 0; i < h->nr_cmds; i++) { | |
1543 | kfree(h->cmd_sg_list[i]); | |
1544 | h->cmd_sg_list[i] = NULL; | |
1545 | } | |
1546 | kfree(h->cmd_sg_list); | |
1547 | h->cmd_sg_list = NULL; | |
1548 | } | |
1549 | ||
1550 | static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h) | |
1551 | { | |
1552 | int i; | |
1553 | ||
1554 | if (h->chainsize <= 0) | |
1555 | return 0; | |
1556 | ||
1557 | h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds, | |
1558 | GFP_KERNEL); | |
3d4e6af8 RE |
1559 | if (!h->cmd_sg_list) { |
1560 | dev_err(&h->pdev->dev, "Failed to allocate SG list\n"); | |
33a2ffce | 1561 | return -ENOMEM; |
3d4e6af8 | 1562 | } |
33a2ffce SC |
1563 | for (i = 0; i < h->nr_cmds; i++) { |
1564 | h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) * | |
1565 | h->chainsize, GFP_KERNEL); | |
3d4e6af8 RE |
1566 | if (!h->cmd_sg_list[i]) { |
1567 | dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n"); | |
33a2ffce | 1568 | goto clean; |
3d4e6af8 | 1569 | } |
33a2ffce SC |
1570 | } |
1571 | return 0; | |
1572 | ||
1573 | clean: | |
1574 | hpsa_free_sg_chain_blocks(h); | |
1575 | return -ENOMEM; | |
1576 | } | |
1577 | ||
e2bea6df | 1578 | static int hpsa_map_sg_chain_block(struct ctlr_info *h, |
33a2ffce SC |
1579 | struct CommandList *c) |
1580 | { | |
1581 | struct SGDescriptor *chain_sg, *chain_block; | |
1582 | u64 temp64; | |
50a0decf | 1583 | u32 chain_len; |
33a2ffce SC |
1584 | |
1585 | chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; | |
1586 | chain_block = h->cmd_sg_list[c->cmdindex]; | |
50a0decf SC |
1587 | chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN); |
1588 | chain_len = sizeof(*chain_sg) * | |
2b08b3e9 | 1589 | (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries); |
50a0decf SC |
1590 | chain_sg->Len = cpu_to_le32(chain_len); |
1591 | temp64 = pci_map_single(h->pdev, chain_block, chain_len, | |
33a2ffce | 1592 | PCI_DMA_TODEVICE); |
e2bea6df SC |
1593 | if (dma_mapping_error(&h->pdev->dev, temp64)) { |
1594 | /* prevent subsequent unmapping */ | |
50a0decf | 1595 | chain_sg->Addr = cpu_to_le64(0); |
e2bea6df SC |
1596 | return -1; |
1597 | } | |
50a0decf | 1598 | chain_sg->Addr = cpu_to_le64(temp64); |
e2bea6df | 1599 | return 0; |
33a2ffce SC |
1600 | } |
1601 | ||
1602 | static void hpsa_unmap_sg_chain_block(struct ctlr_info *h, | |
1603 | struct CommandList *c) | |
1604 | { | |
1605 | struct SGDescriptor *chain_sg; | |
33a2ffce | 1606 | |
50a0decf | 1607 | if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries) |
33a2ffce SC |
1608 | return; |
1609 | ||
1610 | chain_sg = &c->SG[h->max_cmd_sg_entries - 1]; | |
50a0decf SC |
1611 | pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr), |
1612 | le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE); | |
33a2ffce SC |
1613 | } |
1614 | ||
a09c1441 ST |
1615 | |
1616 | /* Decode the various types of errors on ioaccel2 path. | |
1617 | * Return 1 for any error that should generate a RAID path retry. | |
1618 | * Return 0 for errors that don't require a RAID path retry. | |
1619 | */ | |
1620 | static int handle_ioaccel_mode2_error(struct ctlr_info *h, | |
c349775e ST |
1621 | struct CommandList *c, |
1622 | struct scsi_cmnd *cmd, | |
1623 | struct io_accel2_cmd *c2) | |
1624 | { | |
1625 | int data_len; | |
a09c1441 | 1626 | int retry = 0; |
c349775e ST |
1627 | |
1628 | switch (c2->error_data.serv_response) { | |
1629 | case IOACCEL2_SERV_RESPONSE_COMPLETE: | |
1630 | switch (c2->error_data.status) { | |
1631 | case IOACCEL2_STATUS_SR_TASK_COMP_GOOD: | |
1632 | break; | |
1633 | case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND: | |
1634 | dev_warn(&h->pdev->dev, | |
1635 | "%s: task complete with check condition.\n", | |
1636 | "HP SSD Smart Path"); | |
ee6b1889 | 1637 | cmd->result |= SAM_STAT_CHECK_CONDITION; |
c349775e | 1638 | if (c2->error_data.data_present != |
ee6b1889 SC |
1639 | IOACCEL2_SENSE_DATA_PRESENT) { |
1640 | memset(cmd->sense_buffer, 0, | |
1641 | SCSI_SENSE_BUFFERSIZE); | |
c349775e | 1642 | break; |
ee6b1889 | 1643 | } |
c349775e ST |
1644 | /* copy the sense data */ |
1645 | data_len = c2->error_data.sense_data_len; | |
1646 | if (data_len > SCSI_SENSE_BUFFERSIZE) | |
1647 | data_len = SCSI_SENSE_BUFFERSIZE; | |
1648 | if (data_len > sizeof(c2->error_data.sense_data_buff)) | |
1649 | data_len = | |
1650 | sizeof(c2->error_data.sense_data_buff); | |
1651 | memcpy(cmd->sense_buffer, | |
1652 | c2->error_data.sense_data_buff, data_len); | |
a09c1441 | 1653 | retry = 1; |
c349775e ST |
1654 | break; |
1655 | case IOACCEL2_STATUS_SR_TASK_COMP_BUSY: | |
1656 | dev_warn(&h->pdev->dev, | |
1657 | "%s: task complete with BUSY status.\n", | |
1658 | "HP SSD Smart Path"); | |
a09c1441 | 1659 | retry = 1; |
c349775e ST |
1660 | break; |
1661 | case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON: | |
1662 | dev_warn(&h->pdev->dev, | |
1663 | "%s: task complete with reservation conflict.\n", | |
1664 | "HP SSD Smart Path"); | |
a09c1441 | 1665 | retry = 1; |
c349775e ST |
1666 | break; |
1667 | case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL: | |
1668 | /* Make scsi midlayer do unlimited retries */ | |
1669 | cmd->result = DID_IMM_RETRY << 16; | |
1670 | break; | |
1671 | case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED: | |
1672 | dev_warn(&h->pdev->dev, | |
1673 | "%s: task complete with aborted status.\n", | |
1674 | "HP SSD Smart Path"); | |
a09c1441 | 1675 | retry = 1; |
c349775e ST |
1676 | break; |
1677 | default: | |
1678 | dev_warn(&h->pdev->dev, | |
1679 | "%s: task complete with unrecognized status: 0x%02x\n", | |
1680 | "HP SSD Smart Path", c2->error_data.status); | |
a09c1441 | 1681 | retry = 1; |
c349775e ST |
1682 | break; |
1683 | } | |
1684 | break; | |
1685 | case IOACCEL2_SERV_RESPONSE_FAILURE: | |
1686 | /* don't expect to get here. */ | |
1687 | dev_warn(&h->pdev->dev, | |
1688 | "unexpected delivery or target failure, status = 0x%02x\n", | |
1689 | c2->error_data.status); | |
a09c1441 | 1690 | retry = 1; |
c349775e ST |
1691 | break; |
1692 | case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE: | |
1693 | break; | |
1694 | case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS: | |
1695 | break; | |
1696 | case IOACCEL2_SERV_RESPONSE_TMF_REJECTED: | |
1697 | dev_warn(&h->pdev->dev, "task management function rejected.\n"); | |
a09c1441 | 1698 | retry = 1; |
c349775e ST |
1699 | break; |
1700 | case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN: | |
1701 | dev_warn(&h->pdev->dev, "task management function invalid LUN\n"); | |
1702 | break; | |
1703 | default: | |
1704 | dev_warn(&h->pdev->dev, | |
1705 | "%s: Unrecognized server response: 0x%02x\n", | |
a09c1441 ST |
1706 | "HP SSD Smart Path", |
1707 | c2->error_data.serv_response); | |
1708 | retry = 1; | |
c349775e ST |
1709 | break; |
1710 | } | |
a09c1441 ST |
1711 | |
1712 | return retry; /* retry on raid path? */ | |
c349775e ST |
1713 | } |
1714 | ||
1715 | static void process_ioaccel2_completion(struct ctlr_info *h, | |
1716 | struct CommandList *c, struct scsi_cmnd *cmd, | |
1717 | struct hpsa_scsi_dev_t *dev) | |
1718 | { | |
1719 | struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
1720 | ||
1721 | /* check for good status */ | |
1722 | if (likely(c2->error_data.serv_response == 0 && | |
1723 | c2->error_data.status == 0)) { | |
1724 | cmd_free(h, c); | |
1725 | cmd->scsi_done(cmd); | |
1726 | return; | |
1727 | } | |
1728 | ||
1729 | /* Any RAID offload error results in retry which will use | |
1730 | * the normal I/O path so the controller can handle whatever's | |
1731 | * wrong. | |
1732 | */ | |
1733 | if (is_logical_dev_addr_mode(dev->scsi3addr) && | |
1734 | c2->error_data.serv_response == | |
1735 | IOACCEL2_SERV_RESPONSE_FAILURE) { | |
080ef1cc DB |
1736 | if (c2->error_data.status == |
1737 | IOACCEL2_STATUS_SR_IOACCEL_DISABLED) | |
1738 | dev->offload_enabled = 0; | |
1739 | goto retry_cmd; | |
a09c1441 | 1740 | } |
080ef1cc DB |
1741 | |
1742 | if (handle_ioaccel_mode2_error(h, c, cmd, c2)) | |
1743 | goto retry_cmd; | |
1744 | ||
c349775e ST |
1745 | cmd_free(h, c); |
1746 | cmd->scsi_done(cmd); | |
080ef1cc DB |
1747 | return; |
1748 | ||
1749 | retry_cmd: | |
1750 | INIT_WORK(&c->work, hpsa_command_resubmit_worker); | |
1751 | queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work); | |
c349775e ST |
1752 | } |
1753 | ||
1fb011fb | 1754 | static void complete_scsi_command(struct CommandList *cp) |
edd16368 SC |
1755 | { |
1756 | struct scsi_cmnd *cmd; | |
1757 | struct ctlr_info *h; | |
1758 | struct ErrorInfo *ei; | |
283b4a9b | 1759 | struct hpsa_scsi_dev_t *dev; |
edd16368 SC |
1760 | |
1761 | unsigned char sense_key; | |
1762 | unsigned char asc; /* additional sense code */ | |
1763 | unsigned char ascq; /* additional sense code qualifier */ | |
db111e18 | 1764 | unsigned long sense_data_size; |
edd16368 SC |
1765 | |
1766 | ei = cp->err_info; | |
7fa3030c | 1767 | cmd = cp->scsi_cmd; |
edd16368 | 1768 | h = cp->h; |
283b4a9b | 1769 | dev = cmd->device->hostdata; |
edd16368 SC |
1770 | |
1771 | scsi_dma_unmap(cmd); /* undo the DMA mappings */ | |
e1f7de0c | 1772 | if ((cp->cmd_type == CMD_SCSI) && |
2b08b3e9 | 1773 | (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries)) |
33a2ffce | 1774 | hpsa_unmap_sg_chain_block(h, cp); |
edd16368 SC |
1775 | |
1776 | cmd->result = (DID_OK << 16); /* host byte */ | |
1777 | cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */ | |
c349775e | 1778 | |
03383736 DB |
1779 | if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1) |
1780 | atomic_dec(&cp->phys_disk->ioaccel_cmds_out); | |
1781 | ||
c349775e ST |
1782 | if (cp->cmd_type == CMD_IOACCEL2) |
1783 | return process_ioaccel2_completion(h, cp, cmd, dev); | |
1784 | ||
5512672f | 1785 | cmd->result |= ei->ScsiStatus; |
edd16368 | 1786 | |
6aa4c361 RE |
1787 | scsi_set_resid(cmd, ei->ResidualCnt); |
1788 | if (ei->CommandStatus == 0) { | |
03383736 DB |
1789 | if (cp->cmd_type == CMD_IOACCEL1) |
1790 | atomic_dec(&cp->phys_disk->ioaccel_cmds_out); | |
6aa4c361 RE |
1791 | cmd_free(h, cp); |
1792 | cmd->scsi_done(cmd); | |
1793 | return; | |
1794 | } | |
1795 | ||
1796 | /* copy the sense data */ | |
db111e18 SC |
1797 | if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo)) |
1798 | sense_data_size = SCSI_SENSE_BUFFERSIZE; | |
1799 | else | |
1800 | sense_data_size = sizeof(ei->SenseInfo); | |
1801 | if (ei->SenseLen < sense_data_size) | |
1802 | sense_data_size = ei->SenseLen; | |
1803 | ||
1804 | memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size); | |
edd16368 | 1805 | |
e1f7de0c MG |
1806 | /* For I/O accelerator commands, copy over some fields to the normal |
1807 | * CISS header used below for error handling. | |
1808 | */ | |
1809 | if (cp->cmd_type == CMD_IOACCEL1) { | |
1810 | struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex]; | |
2b08b3e9 DB |
1811 | cp->Header.SGList = scsi_sg_count(cmd); |
1812 | cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList); | |
1813 | cp->Request.CDBLen = le16_to_cpu(c->io_flags) & | |
1814 | IOACCEL1_IOFLAGS_CDBLEN_MASK; | |
50a0decf | 1815 | cp->Header.tag = c->tag; |
e1f7de0c MG |
1816 | memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8); |
1817 | memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen); | |
283b4a9b SC |
1818 | |
1819 | /* Any RAID offload error results in retry which will use | |
1820 | * the normal I/O path so the controller can handle whatever's | |
1821 | * wrong. | |
1822 | */ | |
1823 | if (is_logical_dev_addr_mode(dev->scsi3addr)) { | |
1824 | if (ei->CommandStatus == CMD_IOACCEL_DISABLED) | |
1825 | dev->offload_enabled = 0; | |
080ef1cc DB |
1826 | INIT_WORK(&cp->work, hpsa_command_resubmit_worker); |
1827 | queue_work_on(raw_smp_processor_id(), | |
1828 | h->resubmit_wq, &cp->work); | |
283b4a9b SC |
1829 | return; |
1830 | } | |
e1f7de0c MG |
1831 | } |
1832 | ||
edd16368 SC |
1833 | /* an error has occurred */ |
1834 | switch (ei->CommandStatus) { | |
1835 | ||
1836 | case CMD_TARGET_STATUS: | |
1837 | if (ei->ScsiStatus) { | |
1838 | /* Get sense key */ | |
1839 | sense_key = 0xf & ei->SenseInfo[2]; | |
1840 | /* Get additional sense code */ | |
1841 | asc = ei->SenseInfo[12]; | |
1842 | /* Get addition sense code qualifier */ | |
1843 | ascq = ei->SenseInfo[13]; | |
1844 | } | |
edd16368 | 1845 | if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) { |
1d3b3609 | 1846 | if (sense_key == ABORTED_COMMAND) { |
2e311fba | 1847 | cmd->result |= DID_SOFT_ERROR << 16; |
1d3b3609 MG |
1848 | break; |
1849 | } | |
edd16368 SC |
1850 | break; |
1851 | } | |
edd16368 SC |
1852 | /* Problem was not a check condition |
1853 | * Pass it up to the upper layers... | |
1854 | */ | |
1855 | if (ei->ScsiStatus) { | |
1856 | dev_warn(&h->pdev->dev, "cp %p has status 0x%x " | |
1857 | "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, " | |
1858 | "Returning result: 0x%x\n", | |
1859 | cp, ei->ScsiStatus, | |
1860 | sense_key, asc, ascq, | |
1861 | cmd->result); | |
1862 | } else { /* scsi status is zero??? How??? */ | |
1863 | dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. " | |
1864 | "Returning no connection.\n", cp), | |
1865 | ||
1866 | /* Ordinarily, this case should never happen, | |
1867 | * but there is a bug in some released firmware | |
1868 | * revisions that allows it to happen if, for | |
1869 | * example, a 4100 backplane loses power and | |
1870 | * the tape drive is in it. We assume that | |
1871 | * it's a fatal error of some kind because we | |
1872 | * can't show that it wasn't. We will make it | |
1873 | * look like selection timeout since that is | |
1874 | * the most common reason for this to occur, | |
1875 | * and it's severe enough. | |
1876 | */ | |
1877 | ||
1878 | cmd->result = DID_NO_CONNECT << 16; | |
1879 | } | |
1880 | break; | |
1881 | ||
1882 | case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ | |
1883 | break; | |
1884 | case CMD_DATA_OVERRUN: | |
1885 | dev_warn(&h->pdev->dev, "cp %p has" | |
1886 | " completed with data overrun " | |
1887 | "reported\n", cp); | |
1888 | break; | |
1889 | case CMD_INVALID: { | |
1890 | /* print_bytes(cp, sizeof(*cp), 1, 0); | |
1891 | print_cmd(cp); */ | |
1892 | /* We get CMD_INVALID if you address a non-existent device | |
1893 | * instead of a selection timeout (no response). You will | |
1894 | * see this if you yank out a drive, then try to access it. | |
1895 | * This is kind of a shame because it means that any other | |
1896 | * CMD_INVALID (e.g. driver bug) will get interpreted as a | |
1897 | * missing target. */ | |
1898 | cmd->result = DID_NO_CONNECT << 16; | |
1899 | } | |
1900 | break; | |
1901 | case CMD_PROTOCOL_ERR: | |
256d0eaa | 1902 | cmd->result = DID_ERROR << 16; |
edd16368 | 1903 | dev_warn(&h->pdev->dev, "cp %p has " |
256d0eaa | 1904 | "protocol error\n", cp); |
edd16368 SC |
1905 | break; |
1906 | case CMD_HARDWARE_ERR: | |
1907 | cmd->result = DID_ERROR << 16; | |
1908 | dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp); | |
1909 | break; | |
1910 | case CMD_CONNECTION_LOST: | |
1911 | cmd->result = DID_ERROR << 16; | |
1912 | dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp); | |
1913 | break; | |
1914 | case CMD_ABORTED: | |
1915 | cmd->result = DID_ABORT << 16; | |
1916 | dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n", | |
1917 | cp, ei->ScsiStatus); | |
1918 | break; | |
1919 | case CMD_ABORT_FAILED: | |
1920 | cmd->result = DID_ERROR << 16; | |
1921 | dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp); | |
1922 | break; | |
1923 | case CMD_UNSOLICITED_ABORT: | |
f6e76055 SC |
1924 | cmd->result = DID_SOFT_ERROR << 16; /* retry the command */ |
1925 | dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited " | |
edd16368 SC |
1926 | "abort\n", cp); |
1927 | break; | |
1928 | case CMD_TIMEOUT: | |
1929 | cmd->result = DID_TIME_OUT << 16; | |
1930 | dev_warn(&h->pdev->dev, "cp %p timedout\n", cp); | |
1931 | break; | |
1d5e2ed0 SC |
1932 | case CMD_UNABORTABLE: |
1933 | cmd->result = DID_ERROR << 16; | |
1934 | dev_warn(&h->pdev->dev, "Command unabortable\n"); | |
1935 | break; | |
283b4a9b SC |
1936 | case CMD_IOACCEL_DISABLED: |
1937 | /* This only handles the direct pass-through case since RAID | |
1938 | * offload is handled above. Just attempt a retry. | |
1939 | */ | |
1940 | cmd->result = DID_SOFT_ERROR << 16; | |
1941 | dev_warn(&h->pdev->dev, | |
1942 | "cp %p had HP SSD Smart Path error\n", cp); | |
1943 | break; | |
edd16368 SC |
1944 | default: |
1945 | cmd->result = DID_ERROR << 16; | |
1946 | dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n", | |
1947 | cp, ei->CommandStatus); | |
1948 | } | |
edd16368 | 1949 | cmd_free(h, cp); |
2cc5bfaf | 1950 | cmd->scsi_done(cmd); |
edd16368 SC |
1951 | } |
1952 | ||
edd16368 SC |
1953 | static void hpsa_pci_unmap(struct pci_dev *pdev, |
1954 | struct CommandList *c, int sg_used, int data_direction) | |
1955 | { | |
1956 | int i; | |
edd16368 | 1957 | |
50a0decf SC |
1958 | for (i = 0; i < sg_used; i++) |
1959 | pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr), | |
1960 | le32_to_cpu(c->SG[i].Len), | |
1961 | data_direction); | |
edd16368 SC |
1962 | } |
1963 | ||
a2dac136 | 1964 | static int hpsa_map_one(struct pci_dev *pdev, |
edd16368 SC |
1965 | struct CommandList *cp, |
1966 | unsigned char *buf, | |
1967 | size_t buflen, | |
1968 | int data_direction) | |
1969 | { | |
01a02ffc | 1970 | u64 addr64; |
edd16368 SC |
1971 | |
1972 | if (buflen == 0 || data_direction == PCI_DMA_NONE) { | |
1973 | cp->Header.SGList = 0; | |
50a0decf | 1974 | cp->Header.SGTotal = cpu_to_le16(0); |
a2dac136 | 1975 | return 0; |
edd16368 SC |
1976 | } |
1977 | ||
50a0decf | 1978 | addr64 = pci_map_single(pdev, buf, buflen, data_direction); |
eceaae18 | 1979 | if (dma_mapping_error(&pdev->dev, addr64)) { |
a2dac136 | 1980 | /* Prevent subsequent unmap of something never mapped */ |
eceaae18 | 1981 | cp->Header.SGList = 0; |
50a0decf | 1982 | cp->Header.SGTotal = cpu_to_le16(0); |
a2dac136 | 1983 | return -1; |
eceaae18 | 1984 | } |
50a0decf SC |
1985 | cp->SG[0].Addr = cpu_to_le64(addr64); |
1986 | cp->SG[0].Len = cpu_to_le32(buflen); | |
1987 | cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */ | |
1988 | cp->Header.SGList = 1; /* no. SGs contig in this cmd */ | |
1989 | cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */ | |
a2dac136 | 1990 | return 0; |
edd16368 SC |
1991 | } |
1992 | ||
1993 | static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h, | |
1994 | struct CommandList *c) | |
1995 | { | |
1996 | DECLARE_COMPLETION_ONSTACK(wait); | |
1997 | ||
1998 | c->waiting = &wait; | |
1999 | enqueue_cmd_and_start_io(h, c); | |
2000 | wait_for_completion(&wait); | |
2001 | } | |
2002 | ||
094963da SC |
2003 | static u32 lockup_detected(struct ctlr_info *h) |
2004 | { | |
2005 | int cpu; | |
2006 | u32 rc, *lockup_detected; | |
2007 | ||
2008 | cpu = get_cpu(); | |
2009 | lockup_detected = per_cpu_ptr(h->lockup_detected, cpu); | |
2010 | rc = *lockup_detected; | |
2011 | put_cpu(); | |
2012 | return rc; | |
2013 | } | |
2014 | ||
a0c12413 SC |
2015 | static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h, |
2016 | struct CommandList *c) | |
2017 | { | |
a0c12413 | 2018 | /* If controller lockup detected, fake a hardware error. */ |
094963da | 2019 | if (unlikely(lockup_detected(h))) |
a0c12413 | 2020 | c->err_info->CommandStatus = CMD_HARDWARE_ERR; |
094963da | 2021 | else |
a0c12413 | 2022 | hpsa_scsi_do_simple_cmd_core(h, c); |
a0c12413 SC |
2023 | } |
2024 | ||
9c2fc160 | 2025 | #define MAX_DRIVER_CMD_RETRIES 25 |
edd16368 SC |
2026 | static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h, |
2027 | struct CommandList *c, int data_direction) | |
2028 | { | |
9c2fc160 | 2029 | int backoff_time = 10, retry_count = 0; |
edd16368 SC |
2030 | |
2031 | do { | |
7630abd0 | 2032 | memset(c->err_info, 0, sizeof(*c->err_info)); |
edd16368 SC |
2033 | hpsa_scsi_do_simple_cmd_core(h, c); |
2034 | retry_count++; | |
9c2fc160 SC |
2035 | if (retry_count > 3) { |
2036 | msleep(backoff_time); | |
2037 | if (backoff_time < 1000) | |
2038 | backoff_time *= 2; | |
2039 | } | |
852af20a | 2040 | } while ((check_for_unit_attention(h, c) || |
9c2fc160 SC |
2041 | check_for_busy(h, c)) && |
2042 | retry_count <= MAX_DRIVER_CMD_RETRIES); | |
edd16368 SC |
2043 | hpsa_pci_unmap(h->pdev, c, 1, data_direction); |
2044 | } | |
2045 | ||
d1e8beac SC |
2046 | static void hpsa_print_cmd(struct ctlr_info *h, char *txt, |
2047 | struct CommandList *c) | |
edd16368 | 2048 | { |
d1e8beac SC |
2049 | const u8 *cdb = c->Request.CDB; |
2050 | const u8 *lun = c->Header.LUN.LunAddrBytes; | |
2051 | ||
2052 | dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x" | |
2053 | " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
2054 | txt, lun[0], lun[1], lun[2], lun[3], | |
2055 | lun[4], lun[5], lun[6], lun[7], | |
2056 | cdb[0], cdb[1], cdb[2], cdb[3], | |
2057 | cdb[4], cdb[5], cdb[6], cdb[7], | |
2058 | cdb[8], cdb[9], cdb[10], cdb[11], | |
2059 | cdb[12], cdb[13], cdb[14], cdb[15]); | |
2060 | } | |
2061 | ||
2062 | static void hpsa_scsi_interpret_error(struct ctlr_info *h, | |
2063 | struct CommandList *cp) | |
2064 | { | |
2065 | const struct ErrorInfo *ei = cp->err_info; | |
edd16368 | 2066 | struct device *d = &cp->h->pdev->dev; |
d1e8beac | 2067 | const u8 *sd = ei->SenseInfo; |
edd16368 | 2068 | |
edd16368 SC |
2069 | switch (ei->CommandStatus) { |
2070 | case CMD_TARGET_STATUS: | |
d1e8beac SC |
2071 | hpsa_print_cmd(h, "SCSI status", cp); |
2072 | if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) | |
2073 | dev_warn(d, "SCSI Status = 02, Sense key = %02x, ASC = %02x, ASCQ = %02x\n", | |
2074 | sd[2] & 0x0f, sd[12], sd[13]); | |
2075 | else | |
2076 | dev_warn(d, "SCSI Status = %02x\n", ei->ScsiStatus); | |
edd16368 SC |
2077 | if (ei->ScsiStatus == 0) |
2078 | dev_warn(d, "SCSI status is abnormally zero. " | |
2079 | "(probably indicates selection timeout " | |
2080 | "reported incorrectly due to a known " | |
2081 | "firmware bug, circa July, 2001.)\n"); | |
2082 | break; | |
2083 | case CMD_DATA_UNDERRUN: /* let mid layer handle it. */ | |
edd16368 SC |
2084 | break; |
2085 | case CMD_DATA_OVERRUN: | |
d1e8beac | 2086 | hpsa_print_cmd(h, "overrun condition", cp); |
edd16368 SC |
2087 | break; |
2088 | case CMD_INVALID: { | |
2089 | /* controller unfortunately reports SCSI passthru's | |
2090 | * to non-existent targets as invalid commands. | |
2091 | */ | |
d1e8beac SC |
2092 | hpsa_print_cmd(h, "invalid command", cp); |
2093 | dev_warn(d, "probably means device no longer present\n"); | |
edd16368 SC |
2094 | } |
2095 | break; | |
2096 | case CMD_PROTOCOL_ERR: | |
d1e8beac | 2097 | hpsa_print_cmd(h, "protocol error", cp); |
edd16368 SC |
2098 | break; |
2099 | case CMD_HARDWARE_ERR: | |
d1e8beac | 2100 | hpsa_print_cmd(h, "hardware error", cp); |
edd16368 SC |
2101 | break; |
2102 | case CMD_CONNECTION_LOST: | |
d1e8beac | 2103 | hpsa_print_cmd(h, "connection lost", cp); |
edd16368 SC |
2104 | break; |
2105 | case CMD_ABORTED: | |
d1e8beac | 2106 | hpsa_print_cmd(h, "aborted", cp); |
edd16368 SC |
2107 | break; |
2108 | case CMD_ABORT_FAILED: | |
d1e8beac | 2109 | hpsa_print_cmd(h, "abort failed", cp); |
edd16368 SC |
2110 | break; |
2111 | case CMD_UNSOLICITED_ABORT: | |
d1e8beac | 2112 | hpsa_print_cmd(h, "unsolicited abort", cp); |
edd16368 SC |
2113 | break; |
2114 | case CMD_TIMEOUT: | |
d1e8beac | 2115 | hpsa_print_cmd(h, "timed out", cp); |
edd16368 | 2116 | break; |
1d5e2ed0 | 2117 | case CMD_UNABORTABLE: |
d1e8beac | 2118 | hpsa_print_cmd(h, "unabortable", cp); |
1d5e2ed0 | 2119 | break; |
edd16368 | 2120 | default: |
d1e8beac SC |
2121 | hpsa_print_cmd(h, "unknown status", cp); |
2122 | dev_warn(d, "Unknown command status %x\n", | |
edd16368 SC |
2123 | ei->CommandStatus); |
2124 | } | |
2125 | } | |
2126 | ||
2127 | static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr, | |
b7bb24eb | 2128 | u16 page, unsigned char *buf, |
edd16368 SC |
2129 | unsigned char bufsize) |
2130 | { | |
2131 | int rc = IO_OK; | |
2132 | struct CommandList *c; | |
2133 | struct ErrorInfo *ei; | |
2134 | ||
45fcb86e | 2135 | c = cmd_alloc(h); |
edd16368 | 2136 | |
574f05d3 | 2137 | if (c == NULL) { |
45fcb86e | 2138 | dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n"); |
ecd9aad4 | 2139 | return -ENOMEM; |
edd16368 SC |
2140 | } |
2141 | ||
a2dac136 SC |
2142 | if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize, |
2143 | page, scsi3addr, TYPE_CMD)) { | |
2144 | rc = -1; | |
2145 | goto out; | |
2146 | } | |
edd16368 SC |
2147 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE); |
2148 | ei = c->err_info; | |
2149 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
d1e8beac | 2150 | hpsa_scsi_interpret_error(h, c); |
edd16368 SC |
2151 | rc = -1; |
2152 | } | |
a2dac136 | 2153 | out: |
45fcb86e | 2154 | cmd_free(h, c); |
edd16368 SC |
2155 | return rc; |
2156 | } | |
2157 | ||
316b221a SC |
2158 | static int hpsa_bmic_ctrl_mode_sense(struct ctlr_info *h, |
2159 | unsigned char *scsi3addr, unsigned char page, | |
2160 | struct bmic_controller_parameters *buf, size_t bufsize) | |
2161 | { | |
2162 | int rc = IO_OK; | |
2163 | struct CommandList *c; | |
2164 | struct ErrorInfo *ei; | |
2165 | ||
45fcb86e | 2166 | c = cmd_alloc(h); |
316b221a | 2167 | if (c == NULL) { /* trouble... */ |
45fcb86e | 2168 | dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n"); |
316b221a SC |
2169 | return -ENOMEM; |
2170 | } | |
2171 | ||
2172 | if (fill_cmd(c, BMIC_SENSE_CONTROLLER_PARAMETERS, h, buf, bufsize, | |
2173 | page, scsi3addr, TYPE_CMD)) { | |
2174 | rc = -1; | |
2175 | goto out; | |
2176 | } | |
2177 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE); | |
2178 | ei = c->err_info; | |
2179 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
2180 | hpsa_scsi_interpret_error(h, c); | |
2181 | rc = -1; | |
2182 | } | |
2183 | out: | |
45fcb86e | 2184 | cmd_free(h, c); |
316b221a SC |
2185 | return rc; |
2186 | } | |
2187 | ||
bf711ac6 ST |
2188 | static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr, |
2189 | u8 reset_type) | |
edd16368 SC |
2190 | { |
2191 | int rc = IO_OK; | |
2192 | struct CommandList *c; | |
2193 | struct ErrorInfo *ei; | |
2194 | ||
45fcb86e | 2195 | c = cmd_alloc(h); |
edd16368 SC |
2196 | |
2197 | if (c == NULL) { /* trouble... */ | |
45fcb86e | 2198 | dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n"); |
e9ea04a6 | 2199 | return -ENOMEM; |
edd16368 SC |
2200 | } |
2201 | ||
a2dac136 | 2202 | /* fill_cmd can't fail here, no data buffer to map. */ |
bf711ac6 ST |
2203 | (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, |
2204 | scsi3addr, TYPE_MSG); | |
2205 | c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */ | |
edd16368 SC |
2206 | hpsa_scsi_do_simple_cmd_core(h, c); |
2207 | /* no unmap needed here because no data xfer. */ | |
2208 | ||
2209 | ei = c->err_info; | |
2210 | if (ei->CommandStatus != 0) { | |
d1e8beac | 2211 | hpsa_scsi_interpret_error(h, c); |
edd16368 SC |
2212 | rc = -1; |
2213 | } | |
45fcb86e | 2214 | cmd_free(h, c); |
edd16368 SC |
2215 | return rc; |
2216 | } | |
2217 | ||
2218 | static void hpsa_get_raid_level(struct ctlr_info *h, | |
2219 | unsigned char *scsi3addr, unsigned char *raid_level) | |
2220 | { | |
2221 | int rc; | |
2222 | unsigned char *buf; | |
2223 | ||
2224 | *raid_level = RAID_UNKNOWN; | |
2225 | buf = kzalloc(64, GFP_KERNEL); | |
2226 | if (!buf) | |
2227 | return; | |
b7bb24eb | 2228 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64); |
edd16368 SC |
2229 | if (rc == 0) |
2230 | *raid_level = buf[8]; | |
2231 | if (*raid_level > RAID_UNKNOWN) | |
2232 | *raid_level = RAID_UNKNOWN; | |
2233 | kfree(buf); | |
2234 | return; | |
2235 | } | |
2236 | ||
283b4a9b SC |
2237 | #define HPSA_MAP_DEBUG |
2238 | #ifdef HPSA_MAP_DEBUG | |
2239 | static void hpsa_debug_map_buff(struct ctlr_info *h, int rc, | |
2240 | struct raid_map_data *map_buff) | |
2241 | { | |
2242 | struct raid_map_disk_data *dd = &map_buff->data[0]; | |
2243 | int map, row, col; | |
2244 | u16 map_cnt, row_cnt, disks_per_row; | |
2245 | ||
2246 | if (rc != 0) | |
2247 | return; | |
2248 | ||
2ba8bfc8 SC |
2249 | /* Show details only if debugging has been activated. */ |
2250 | if (h->raid_offload_debug < 2) | |
2251 | return; | |
2252 | ||
283b4a9b SC |
2253 | dev_info(&h->pdev->dev, "structure_size = %u\n", |
2254 | le32_to_cpu(map_buff->structure_size)); | |
2255 | dev_info(&h->pdev->dev, "volume_blk_size = %u\n", | |
2256 | le32_to_cpu(map_buff->volume_blk_size)); | |
2257 | dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n", | |
2258 | le64_to_cpu(map_buff->volume_blk_cnt)); | |
2259 | dev_info(&h->pdev->dev, "physicalBlockShift = %u\n", | |
2260 | map_buff->phys_blk_shift); | |
2261 | dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n", | |
2262 | map_buff->parity_rotation_shift); | |
2263 | dev_info(&h->pdev->dev, "strip_size = %u\n", | |
2264 | le16_to_cpu(map_buff->strip_size)); | |
2265 | dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n", | |
2266 | le64_to_cpu(map_buff->disk_starting_blk)); | |
2267 | dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n", | |
2268 | le64_to_cpu(map_buff->disk_blk_cnt)); | |
2269 | dev_info(&h->pdev->dev, "data_disks_per_row = %u\n", | |
2270 | le16_to_cpu(map_buff->data_disks_per_row)); | |
2271 | dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n", | |
2272 | le16_to_cpu(map_buff->metadata_disks_per_row)); | |
2273 | dev_info(&h->pdev->dev, "row_cnt = %u\n", | |
2274 | le16_to_cpu(map_buff->row_cnt)); | |
2275 | dev_info(&h->pdev->dev, "layout_map_count = %u\n", | |
2276 | le16_to_cpu(map_buff->layout_map_count)); | |
2b08b3e9 | 2277 | dev_info(&h->pdev->dev, "flags = 0x%x\n", |
dd0e19f3 | 2278 | le16_to_cpu(map_buff->flags)); |
2b08b3e9 DB |
2279 | dev_info(&h->pdev->dev, "encrypytion = %s\n", |
2280 | le16_to_cpu(map_buff->flags) & | |
2281 | RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF"); | |
dd0e19f3 ST |
2282 | dev_info(&h->pdev->dev, "dekindex = %u\n", |
2283 | le16_to_cpu(map_buff->dekindex)); | |
283b4a9b SC |
2284 | map_cnt = le16_to_cpu(map_buff->layout_map_count); |
2285 | for (map = 0; map < map_cnt; map++) { | |
2286 | dev_info(&h->pdev->dev, "Map%u:\n", map); | |
2287 | row_cnt = le16_to_cpu(map_buff->row_cnt); | |
2288 | for (row = 0; row < row_cnt; row++) { | |
2289 | dev_info(&h->pdev->dev, " Row%u:\n", row); | |
2290 | disks_per_row = | |
2291 | le16_to_cpu(map_buff->data_disks_per_row); | |
2292 | for (col = 0; col < disks_per_row; col++, dd++) | |
2293 | dev_info(&h->pdev->dev, | |
2294 | " D%02u: h=0x%04x xor=%u,%u\n", | |
2295 | col, dd->ioaccel_handle, | |
2296 | dd->xor_mult[0], dd->xor_mult[1]); | |
2297 | disks_per_row = | |
2298 | le16_to_cpu(map_buff->metadata_disks_per_row); | |
2299 | for (col = 0; col < disks_per_row; col++, dd++) | |
2300 | dev_info(&h->pdev->dev, | |
2301 | " M%02u: h=0x%04x xor=%u,%u\n", | |
2302 | col, dd->ioaccel_handle, | |
2303 | dd->xor_mult[0], dd->xor_mult[1]); | |
2304 | } | |
2305 | } | |
2306 | } | |
2307 | #else | |
2308 | static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h, | |
2309 | __attribute__((unused)) int rc, | |
2310 | __attribute__((unused)) struct raid_map_data *map_buff) | |
2311 | { | |
2312 | } | |
2313 | #endif | |
2314 | ||
2315 | static int hpsa_get_raid_map(struct ctlr_info *h, | |
2316 | unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) | |
2317 | { | |
2318 | int rc = 0; | |
2319 | struct CommandList *c; | |
2320 | struct ErrorInfo *ei; | |
2321 | ||
45fcb86e | 2322 | c = cmd_alloc(h); |
283b4a9b | 2323 | if (c == NULL) { |
45fcb86e | 2324 | dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n"); |
283b4a9b SC |
2325 | return -ENOMEM; |
2326 | } | |
2327 | if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map, | |
2328 | sizeof(this_device->raid_map), 0, | |
2329 | scsi3addr, TYPE_CMD)) { | |
2330 | dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n"); | |
45fcb86e | 2331 | cmd_free(h, c); |
283b4a9b SC |
2332 | return -ENOMEM; |
2333 | } | |
2334 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE); | |
2335 | ei = c->err_info; | |
2336 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
d1e8beac | 2337 | hpsa_scsi_interpret_error(h, c); |
45fcb86e | 2338 | cmd_free(h, c); |
283b4a9b SC |
2339 | return -1; |
2340 | } | |
45fcb86e | 2341 | cmd_free(h, c); |
283b4a9b SC |
2342 | |
2343 | /* @todo in the future, dynamically allocate RAID map memory */ | |
2344 | if (le32_to_cpu(this_device->raid_map.structure_size) > | |
2345 | sizeof(this_device->raid_map)) { | |
2346 | dev_warn(&h->pdev->dev, "RAID map size is too large!\n"); | |
2347 | rc = -1; | |
2348 | } | |
2349 | hpsa_debug_map_buff(h, rc, &this_device->raid_map); | |
2350 | return rc; | |
2351 | } | |
2352 | ||
03383736 DB |
2353 | static int hpsa_bmic_id_physical_device(struct ctlr_info *h, |
2354 | unsigned char scsi3addr[], u16 bmic_device_index, | |
2355 | struct bmic_identify_physical_device *buf, size_t bufsize) | |
2356 | { | |
2357 | int rc = IO_OK; | |
2358 | struct CommandList *c; | |
2359 | struct ErrorInfo *ei; | |
2360 | ||
2361 | c = cmd_alloc(h); | |
2362 | rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize, | |
2363 | 0, RAID_CTLR_LUNID, TYPE_CMD); | |
2364 | if (rc) | |
2365 | goto out; | |
2366 | ||
2367 | c->Request.CDB[2] = bmic_device_index & 0xff; | |
2368 | c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff; | |
2369 | ||
2370 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE); | |
2371 | ei = c->err_info; | |
2372 | if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
2373 | hpsa_scsi_interpret_error(h, c); | |
2374 | rc = -1; | |
2375 | } | |
2376 | out: | |
2377 | cmd_free(h, c); | |
2378 | return rc; | |
2379 | } | |
2380 | ||
1b70150a SC |
2381 | static int hpsa_vpd_page_supported(struct ctlr_info *h, |
2382 | unsigned char scsi3addr[], u8 page) | |
2383 | { | |
2384 | int rc; | |
2385 | int i; | |
2386 | int pages; | |
2387 | unsigned char *buf, bufsize; | |
2388 | ||
2389 | buf = kzalloc(256, GFP_KERNEL); | |
2390 | if (!buf) | |
2391 | return 0; | |
2392 | ||
2393 | /* Get the size of the page list first */ | |
2394 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, | |
2395 | VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES, | |
2396 | buf, HPSA_VPD_HEADER_SZ); | |
2397 | if (rc != 0) | |
2398 | goto exit_unsupported; | |
2399 | pages = buf[3]; | |
2400 | if ((pages + HPSA_VPD_HEADER_SZ) <= 255) | |
2401 | bufsize = pages + HPSA_VPD_HEADER_SZ; | |
2402 | else | |
2403 | bufsize = 255; | |
2404 | ||
2405 | /* Get the whole VPD page list */ | |
2406 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, | |
2407 | VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES, | |
2408 | buf, bufsize); | |
2409 | if (rc != 0) | |
2410 | goto exit_unsupported; | |
2411 | ||
2412 | pages = buf[3]; | |
2413 | for (i = 1; i <= pages; i++) | |
2414 | if (buf[3 + i] == page) | |
2415 | goto exit_supported; | |
2416 | exit_unsupported: | |
2417 | kfree(buf); | |
2418 | return 0; | |
2419 | exit_supported: | |
2420 | kfree(buf); | |
2421 | return 1; | |
2422 | } | |
2423 | ||
283b4a9b SC |
2424 | static void hpsa_get_ioaccel_status(struct ctlr_info *h, |
2425 | unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device) | |
2426 | { | |
2427 | int rc; | |
2428 | unsigned char *buf; | |
2429 | u8 ioaccel_status; | |
2430 | ||
2431 | this_device->offload_config = 0; | |
2432 | this_device->offload_enabled = 0; | |
2433 | ||
2434 | buf = kzalloc(64, GFP_KERNEL); | |
2435 | if (!buf) | |
2436 | return; | |
1b70150a SC |
2437 | if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS)) |
2438 | goto out; | |
283b4a9b | 2439 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, |
b7bb24eb | 2440 | VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64); |
283b4a9b SC |
2441 | if (rc != 0) |
2442 | goto out; | |
2443 | ||
2444 | #define IOACCEL_STATUS_BYTE 4 | |
2445 | #define OFFLOAD_CONFIGURED_BIT 0x01 | |
2446 | #define OFFLOAD_ENABLED_BIT 0x02 | |
2447 | ioaccel_status = buf[IOACCEL_STATUS_BYTE]; | |
2448 | this_device->offload_config = | |
2449 | !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT); | |
2450 | if (this_device->offload_config) { | |
2451 | this_device->offload_enabled = | |
2452 | !!(ioaccel_status & OFFLOAD_ENABLED_BIT); | |
2453 | if (hpsa_get_raid_map(h, scsi3addr, this_device)) | |
2454 | this_device->offload_enabled = 0; | |
2455 | } | |
2456 | out: | |
2457 | kfree(buf); | |
2458 | return; | |
2459 | } | |
2460 | ||
edd16368 SC |
2461 | /* Get the device id from inquiry page 0x83 */ |
2462 | static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr, | |
2463 | unsigned char *device_id, int buflen) | |
2464 | { | |
2465 | int rc; | |
2466 | unsigned char *buf; | |
2467 | ||
2468 | if (buflen > 16) | |
2469 | buflen = 16; | |
2470 | buf = kzalloc(64, GFP_KERNEL); | |
2471 | if (!buf) | |
a84d794d | 2472 | return -ENOMEM; |
b7bb24eb | 2473 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64); |
edd16368 SC |
2474 | if (rc == 0) |
2475 | memcpy(device_id, &buf[8], buflen); | |
2476 | kfree(buf); | |
2477 | return rc != 0; | |
2478 | } | |
2479 | ||
2480 | static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical, | |
03383736 | 2481 | void *buf, int bufsize, |
edd16368 SC |
2482 | int extended_response) |
2483 | { | |
2484 | int rc = IO_OK; | |
2485 | struct CommandList *c; | |
2486 | unsigned char scsi3addr[8]; | |
2487 | struct ErrorInfo *ei; | |
2488 | ||
45fcb86e | 2489 | c = cmd_alloc(h); |
edd16368 | 2490 | if (c == NULL) { /* trouble... */ |
45fcb86e | 2491 | dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n"); |
edd16368 SC |
2492 | return -1; |
2493 | } | |
e89c0ae7 SC |
2494 | /* address the controller */ |
2495 | memset(scsi3addr, 0, sizeof(scsi3addr)); | |
a2dac136 SC |
2496 | if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h, |
2497 | buf, bufsize, 0, scsi3addr, TYPE_CMD)) { | |
2498 | rc = -1; | |
2499 | goto out; | |
2500 | } | |
edd16368 SC |
2501 | if (extended_response) |
2502 | c->Request.CDB[1] = extended_response; | |
2503 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE); | |
2504 | ei = c->err_info; | |
2505 | if (ei->CommandStatus != 0 && | |
2506 | ei->CommandStatus != CMD_DATA_UNDERRUN) { | |
d1e8beac | 2507 | hpsa_scsi_interpret_error(h, c); |
edd16368 | 2508 | rc = -1; |
283b4a9b | 2509 | } else { |
03383736 DB |
2510 | struct ReportLUNdata *rld = buf; |
2511 | ||
2512 | if (rld->extended_response_flag != extended_response) { | |
283b4a9b SC |
2513 | dev_err(&h->pdev->dev, |
2514 | "report luns requested format %u, got %u\n", | |
2515 | extended_response, | |
03383736 | 2516 | rld->extended_response_flag); |
283b4a9b SC |
2517 | rc = -1; |
2518 | } | |
edd16368 | 2519 | } |
a2dac136 | 2520 | out: |
45fcb86e | 2521 | cmd_free(h, c); |
edd16368 SC |
2522 | return rc; |
2523 | } | |
2524 | ||
2525 | static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h, | |
03383736 | 2526 | struct ReportExtendedLUNdata *buf, int bufsize) |
edd16368 | 2527 | { |
03383736 DB |
2528 | return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, |
2529 | HPSA_REPORT_PHYS_EXTENDED); | |
edd16368 SC |
2530 | } |
2531 | ||
2532 | static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h, | |
2533 | struct ReportLUNdata *buf, int bufsize) | |
2534 | { | |
2535 | return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0); | |
2536 | } | |
2537 | ||
2538 | static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device, | |
2539 | int bus, int target, int lun) | |
2540 | { | |
2541 | device->bus = bus; | |
2542 | device->target = target; | |
2543 | device->lun = lun; | |
2544 | } | |
2545 | ||
9846590e SC |
2546 | /* Use VPD inquiry to get details of volume status */ |
2547 | static int hpsa_get_volume_status(struct ctlr_info *h, | |
2548 | unsigned char scsi3addr[]) | |
2549 | { | |
2550 | int rc; | |
2551 | int status; | |
2552 | int size; | |
2553 | unsigned char *buf; | |
2554 | ||
2555 | buf = kzalloc(64, GFP_KERNEL); | |
2556 | if (!buf) | |
2557 | return HPSA_VPD_LV_STATUS_UNSUPPORTED; | |
2558 | ||
2559 | /* Does controller have VPD for logical volume status? */ | |
24a4b078 | 2560 | if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS)) |
9846590e | 2561 | goto exit_failed; |
9846590e SC |
2562 | |
2563 | /* Get the size of the VPD return buffer */ | |
2564 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS, | |
2565 | buf, HPSA_VPD_HEADER_SZ); | |
24a4b078 | 2566 | if (rc != 0) |
9846590e | 2567 | goto exit_failed; |
9846590e SC |
2568 | size = buf[3]; |
2569 | ||
2570 | /* Now get the whole VPD buffer */ | |
2571 | rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS, | |
2572 | buf, size + HPSA_VPD_HEADER_SZ); | |
24a4b078 | 2573 | if (rc != 0) |
9846590e | 2574 | goto exit_failed; |
9846590e SC |
2575 | status = buf[4]; /* status byte */ |
2576 | ||
2577 | kfree(buf); | |
2578 | return status; | |
2579 | exit_failed: | |
2580 | kfree(buf); | |
2581 | return HPSA_VPD_LV_STATUS_UNSUPPORTED; | |
2582 | } | |
2583 | ||
2584 | /* Determine offline status of a volume. | |
2585 | * Return either: | |
2586 | * 0 (not offline) | |
67955ba3 | 2587 | * 0xff (offline for unknown reasons) |
9846590e SC |
2588 | * # (integer code indicating one of several NOT READY states |
2589 | * describing why a volume is to be kept offline) | |
2590 | */ | |
67955ba3 | 2591 | static int hpsa_volume_offline(struct ctlr_info *h, |
9846590e SC |
2592 | unsigned char scsi3addr[]) |
2593 | { | |
2594 | struct CommandList *c; | |
2595 | unsigned char *sense, sense_key, asc, ascq; | |
2596 | int ldstat = 0; | |
2597 | u16 cmd_status; | |
2598 | u8 scsi_status; | |
2599 | #define ASC_LUN_NOT_READY 0x04 | |
2600 | #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04 | |
2601 | #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02 | |
2602 | ||
2603 | c = cmd_alloc(h); | |
2604 | if (!c) | |
2605 | return 0; | |
2606 | (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD); | |
2607 | hpsa_scsi_do_simple_cmd_core(h, c); | |
2608 | sense = c->err_info->SenseInfo; | |
2609 | sense_key = sense[2]; | |
2610 | asc = sense[12]; | |
2611 | ascq = sense[13]; | |
2612 | cmd_status = c->err_info->CommandStatus; | |
2613 | scsi_status = c->err_info->ScsiStatus; | |
2614 | cmd_free(h, c); | |
2615 | /* Is the volume 'not ready'? */ | |
2616 | if (cmd_status != CMD_TARGET_STATUS || | |
2617 | scsi_status != SAM_STAT_CHECK_CONDITION || | |
2618 | sense_key != NOT_READY || | |
2619 | asc != ASC_LUN_NOT_READY) { | |
2620 | return 0; | |
2621 | } | |
2622 | ||
2623 | /* Determine the reason for not ready state */ | |
2624 | ldstat = hpsa_get_volume_status(h, scsi3addr); | |
2625 | ||
2626 | /* Keep volume offline in certain cases: */ | |
2627 | switch (ldstat) { | |
2628 | case HPSA_LV_UNDERGOING_ERASE: | |
2629 | case HPSA_LV_UNDERGOING_RPI: | |
2630 | case HPSA_LV_PENDING_RPI: | |
2631 | case HPSA_LV_ENCRYPTED_NO_KEY: | |
2632 | case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER: | |
2633 | case HPSA_LV_UNDERGOING_ENCRYPTION: | |
2634 | case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING: | |
2635 | case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER: | |
2636 | return ldstat; | |
2637 | case HPSA_VPD_LV_STATUS_UNSUPPORTED: | |
2638 | /* If VPD status page isn't available, | |
2639 | * use ASC/ASCQ to determine state | |
2640 | */ | |
2641 | if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) || | |
2642 | (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ)) | |
2643 | return ldstat; | |
2644 | break; | |
2645 | default: | |
2646 | break; | |
2647 | } | |
2648 | return 0; | |
2649 | } | |
2650 | ||
edd16368 | 2651 | static int hpsa_update_device_info(struct ctlr_info *h, |
0b0e1d6c SC |
2652 | unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device, |
2653 | unsigned char *is_OBDR_device) | |
edd16368 | 2654 | { |
0b0e1d6c SC |
2655 | |
2656 | #define OBDR_SIG_OFFSET 43 | |
2657 | #define OBDR_TAPE_SIG "$DR-10" | |
2658 | #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1) | |
2659 | #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN) | |
2660 | ||
ea6d3bc3 | 2661 | unsigned char *inq_buff; |
0b0e1d6c | 2662 | unsigned char *obdr_sig; |
edd16368 | 2663 | |
ea6d3bc3 | 2664 | inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL); |
edd16368 SC |
2665 | if (!inq_buff) |
2666 | goto bail_out; | |
2667 | ||
edd16368 SC |
2668 | /* Do an inquiry to the device to see what it is. */ |
2669 | if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff, | |
2670 | (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) { | |
2671 | /* Inquiry failed (msg printed already) */ | |
2672 | dev_err(&h->pdev->dev, | |
2673 | "hpsa_update_device_info: inquiry failed\n"); | |
2674 | goto bail_out; | |
2675 | } | |
2676 | ||
edd16368 SC |
2677 | this_device->devtype = (inq_buff[0] & 0x1f); |
2678 | memcpy(this_device->scsi3addr, scsi3addr, 8); | |
2679 | memcpy(this_device->vendor, &inq_buff[8], | |
2680 | sizeof(this_device->vendor)); | |
2681 | memcpy(this_device->model, &inq_buff[16], | |
2682 | sizeof(this_device->model)); | |
edd16368 SC |
2683 | memset(this_device->device_id, 0, |
2684 | sizeof(this_device->device_id)); | |
2685 | hpsa_get_device_id(h, scsi3addr, this_device->device_id, | |
2686 | sizeof(this_device->device_id)); | |
2687 | ||
2688 | if (this_device->devtype == TYPE_DISK && | |
283b4a9b | 2689 | is_logical_dev_addr_mode(scsi3addr)) { |
67955ba3 SC |
2690 | int volume_offline; |
2691 | ||
edd16368 | 2692 | hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level); |
283b4a9b SC |
2693 | if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC) |
2694 | hpsa_get_ioaccel_status(h, scsi3addr, this_device); | |
67955ba3 SC |
2695 | volume_offline = hpsa_volume_offline(h, scsi3addr); |
2696 | if (volume_offline < 0 || volume_offline > 0xff) | |
2697 | volume_offline = HPSA_VPD_LV_STATUS_UNSUPPORTED; | |
2698 | this_device->volume_offline = volume_offline & 0xff; | |
283b4a9b | 2699 | } else { |
edd16368 | 2700 | this_device->raid_level = RAID_UNKNOWN; |
283b4a9b SC |
2701 | this_device->offload_config = 0; |
2702 | this_device->offload_enabled = 0; | |
9846590e | 2703 | this_device->volume_offline = 0; |
03383736 | 2704 | this_device->queue_depth = h->nr_cmds; |
283b4a9b | 2705 | } |
edd16368 | 2706 | |
0b0e1d6c SC |
2707 | if (is_OBDR_device) { |
2708 | /* See if this is a One-Button-Disaster-Recovery device | |
2709 | * by looking for "$DR-10" at offset 43 in inquiry data. | |
2710 | */ | |
2711 | obdr_sig = &inq_buff[OBDR_SIG_OFFSET]; | |
2712 | *is_OBDR_device = (this_device->devtype == TYPE_ROM && | |
2713 | strncmp(obdr_sig, OBDR_TAPE_SIG, | |
2714 | OBDR_SIG_LEN) == 0); | |
2715 | } | |
2716 | ||
edd16368 SC |
2717 | kfree(inq_buff); |
2718 | return 0; | |
2719 | ||
2720 | bail_out: | |
2721 | kfree(inq_buff); | |
2722 | return 1; | |
2723 | } | |
2724 | ||
4f4eb9f1 | 2725 | static unsigned char *ext_target_model[] = { |
edd16368 SC |
2726 | "MSA2012", |
2727 | "MSA2024", | |
2728 | "MSA2312", | |
2729 | "MSA2324", | |
fda38518 | 2730 | "P2000 G3 SAS", |
e06c8e5c | 2731 | "MSA 2040 SAS", |
edd16368 SC |
2732 | NULL, |
2733 | }; | |
2734 | ||
4f4eb9f1 | 2735 | static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device) |
edd16368 SC |
2736 | { |
2737 | int i; | |
2738 | ||
4f4eb9f1 ST |
2739 | for (i = 0; ext_target_model[i]; i++) |
2740 | if (strncmp(device->model, ext_target_model[i], | |
2741 | strlen(ext_target_model[i])) == 0) | |
edd16368 SC |
2742 | return 1; |
2743 | return 0; | |
2744 | } | |
2745 | ||
2746 | /* Helper function to assign bus, target, lun mapping of devices. | |
4f4eb9f1 | 2747 | * Puts non-external target logical volumes on bus 0, external target logical |
edd16368 SC |
2748 | * volumes on bus 1, physical devices on bus 2. and the hba on bus 3. |
2749 | * Logical drive target and lun are assigned at this time, but | |
2750 | * physical device lun and target assignment are deferred (assigned | |
2751 | * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.) | |
2752 | */ | |
2753 | static void figure_bus_target_lun(struct ctlr_info *h, | |
1f310bde | 2754 | u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device) |
edd16368 | 2755 | { |
1f310bde SC |
2756 | u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes)); |
2757 | ||
2758 | if (!is_logical_dev_addr_mode(lunaddrbytes)) { | |
2759 | /* physical device, target and lun filled in later */ | |
edd16368 | 2760 | if (is_hba_lunid(lunaddrbytes)) |
1f310bde | 2761 | hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff); |
edd16368 | 2762 | else |
1f310bde SC |
2763 | /* defer target, lun assignment for physical devices */ |
2764 | hpsa_set_bus_target_lun(device, 2, -1, -1); | |
2765 | return; | |
2766 | } | |
2767 | /* It's a logical device */ | |
4f4eb9f1 ST |
2768 | if (is_ext_target(h, device)) { |
2769 | /* external target way, put logicals on bus 1 | |
1f310bde SC |
2770 | * and match target/lun numbers box |
2771 | * reports, other smart array, bus 0, target 0, match lunid | |
2772 | */ | |
2773 | hpsa_set_bus_target_lun(device, | |
2774 | 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff); | |
2775 | return; | |
edd16368 | 2776 | } |
1f310bde | 2777 | hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff); |
edd16368 SC |
2778 | } |
2779 | ||
2780 | /* | |
2781 | * If there is no lun 0 on a target, linux won't find any devices. | |
4f4eb9f1 | 2782 | * For the external targets (arrays), we have to manually detect the enclosure |
edd16368 SC |
2783 | * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report |
2784 | * it for some reason. *tmpdevice is the target we're adding, | |
2785 | * this_device is a pointer into the current element of currentsd[] | |
2786 | * that we're building up in update_scsi_devices(), below. | |
2787 | * lunzerobits is a bitmap that tracks which targets already have a | |
2788 | * lun 0 assigned. | |
2789 | * Returns 1 if an enclosure was added, 0 if not. | |
2790 | */ | |
4f4eb9f1 | 2791 | static int add_ext_target_dev(struct ctlr_info *h, |
edd16368 | 2792 | struct hpsa_scsi_dev_t *tmpdevice, |
01a02ffc | 2793 | struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes, |
4f4eb9f1 | 2794 | unsigned long lunzerobits[], int *n_ext_target_devs) |
edd16368 SC |
2795 | { |
2796 | unsigned char scsi3addr[8]; | |
2797 | ||
1f310bde | 2798 | if (test_bit(tmpdevice->target, lunzerobits)) |
edd16368 SC |
2799 | return 0; /* There is already a lun 0 on this target. */ |
2800 | ||
2801 | if (!is_logical_dev_addr_mode(lunaddrbytes)) | |
2802 | return 0; /* It's the logical targets that may lack lun 0. */ | |
2803 | ||
4f4eb9f1 ST |
2804 | if (!is_ext_target(h, tmpdevice)) |
2805 | return 0; /* Only external target devices have this problem. */ | |
edd16368 | 2806 | |
1f310bde | 2807 | if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */ |
edd16368 SC |
2808 | return 0; |
2809 | ||
c4f8a299 | 2810 | memset(scsi3addr, 0, 8); |
1f310bde | 2811 | scsi3addr[3] = tmpdevice->target; |
edd16368 SC |
2812 | if (is_hba_lunid(scsi3addr)) |
2813 | return 0; /* Don't add the RAID controller here. */ | |
2814 | ||
339b2b14 SC |
2815 | if (is_scsi_rev_5(h)) |
2816 | return 0; /* p1210m doesn't need to do this. */ | |
2817 | ||
4f4eb9f1 | 2818 | if (*n_ext_target_devs >= MAX_EXT_TARGETS) { |
aca4a520 ST |
2819 | dev_warn(&h->pdev->dev, "Maximum number of external " |
2820 | "target devices exceeded. Check your hardware " | |
edd16368 SC |
2821 | "configuration."); |
2822 | return 0; | |
2823 | } | |
2824 | ||
0b0e1d6c | 2825 | if (hpsa_update_device_info(h, scsi3addr, this_device, NULL)) |
edd16368 | 2826 | return 0; |
4f4eb9f1 | 2827 | (*n_ext_target_devs)++; |
1f310bde SC |
2828 | hpsa_set_bus_target_lun(this_device, |
2829 | tmpdevice->bus, tmpdevice->target, 0); | |
2830 | set_bit(tmpdevice->target, lunzerobits); | |
edd16368 SC |
2831 | return 1; |
2832 | } | |
2833 | ||
54b6e9e9 ST |
2834 | /* |
2835 | * Get address of physical disk used for an ioaccel2 mode command: | |
2836 | * 1. Extract ioaccel2 handle from the command. | |
2837 | * 2. Find a matching ioaccel2 handle from list of physical disks. | |
2838 | * 3. Return: | |
2839 | * 1 and set scsi3addr to address of matching physical | |
2840 | * 0 if no matching physical disk was found. | |
2841 | */ | |
2842 | static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h, | |
2843 | struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr) | |
2844 | { | |
2845 | struct ReportExtendedLUNdata *physicals = NULL; | |
2846 | int responsesize = 24; /* size of physical extended response */ | |
54b6e9e9 ST |
2847 | int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize; |
2848 | u32 nphysicals = 0; /* number of reported physical devs */ | |
2849 | int found = 0; /* found match (1) or not (0) */ | |
2850 | u32 find; /* handle we need to match */ | |
2851 | int i; | |
2852 | struct scsi_cmnd *scmd; /* scsi command within request being aborted */ | |
2853 | struct hpsa_scsi_dev_t *d; /* device of request being aborted */ | |
2854 | struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */ | |
2b08b3e9 DB |
2855 | __le32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */ |
2856 | __le32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */ | |
54b6e9e9 ST |
2857 | |
2858 | if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2) | |
2859 | return 0; /* no match */ | |
2860 | ||
2861 | /* point to the ioaccel2 device handle */ | |
2862 | c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex]; | |
2863 | if (c2a == NULL) | |
2864 | return 0; /* no match */ | |
2865 | ||
2866 | scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd; | |
2867 | if (scmd == NULL) | |
2868 | return 0; /* no match */ | |
2869 | ||
2870 | d = scmd->device->hostdata; | |
2871 | if (d == NULL) | |
2872 | return 0; /* no match */ | |
2873 | ||
50a0decf | 2874 | it_nexus = cpu_to_le32(d->ioaccel_handle); |
2b08b3e9 DB |
2875 | scsi_nexus = c2a->scsi_nexus; |
2876 | find = le32_to_cpu(c2a->scsi_nexus); | |
54b6e9e9 | 2877 | |
2ba8bfc8 SC |
2878 | if (h->raid_offload_debug > 0) |
2879 | dev_info(&h->pdev->dev, | |
2880 | "%s: scsi_nexus:0x%08x device id: 0x%02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x %02x%02x%02x%02x\n", | |
2881 | __func__, scsi_nexus, | |
2882 | d->device_id[0], d->device_id[1], d->device_id[2], | |
2883 | d->device_id[3], d->device_id[4], d->device_id[5], | |
2884 | d->device_id[6], d->device_id[7], d->device_id[8], | |
2885 | d->device_id[9], d->device_id[10], d->device_id[11], | |
2886 | d->device_id[12], d->device_id[13], d->device_id[14], | |
2887 | d->device_id[15]); | |
2888 | ||
54b6e9e9 ST |
2889 | /* Get the list of physical devices */ |
2890 | physicals = kzalloc(reportsize, GFP_KERNEL); | |
3b51a7a3 JH |
2891 | if (physicals == NULL) |
2892 | return 0; | |
03383736 | 2893 | if (hpsa_scsi_do_report_phys_luns(h, physicals, reportsize)) { |
54b6e9e9 ST |
2894 | dev_err(&h->pdev->dev, |
2895 | "Can't lookup %s device handle: report physical LUNs failed.\n", | |
2896 | "HP SSD Smart Path"); | |
2897 | kfree(physicals); | |
2898 | return 0; | |
2899 | } | |
2900 | nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) / | |
2901 | responsesize; | |
2902 | ||
54b6e9e9 ST |
2903 | /* find ioaccel2 handle in list of physicals: */ |
2904 | for (i = 0; i < nphysicals; i++) { | |
d5b5d964 SC |
2905 | struct ext_report_lun_entry *entry = &physicals->LUN[i]; |
2906 | ||
54b6e9e9 | 2907 | /* handle is in bytes 28-31 of each lun */ |
d5b5d964 | 2908 | if (entry->ioaccel_handle != find) |
54b6e9e9 | 2909 | continue; /* didn't match */ |
54b6e9e9 | 2910 | found = 1; |
d5b5d964 | 2911 | memcpy(scsi3addr, entry->lunid, 8); |
2ba8bfc8 SC |
2912 | if (h->raid_offload_debug > 0) |
2913 | dev_info(&h->pdev->dev, | |
d5b5d964 | 2914 | "%s: Searched h=0x%08x, Found h=0x%08x, scsiaddr 0x%8phN\n", |
2ba8bfc8 | 2915 | __func__, find, |
d5b5d964 | 2916 | entry->ioaccel_handle, scsi3addr); |
54b6e9e9 ST |
2917 | break; /* found it */ |
2918 | } | |
2919 | ||
2920 | kfree(physicals); | |
2921 | if (found) | |
2922 | return 1; | |
2923 | else | |
2924 | return 0; | |
2925 | ||
2926 | } | |
edd16368 SC |
2927 | /* |
2928 | * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev, | |
2929 | * logdev. The number of luns in physdev and logdev are returned in | |
2930 | * *nphysicals and *nlogicals, respectively. | |
2931 | * Returns 0 on success, -1 otherwise. | |
2932 | */ | |
2933 | static int hpsa_gather_lun_info(struct ctlr_info *h, | |
03383736 | 2934 | struct ReportExtendedLUNdata *physdev, u32 *nphysicals, |
01a02ffc | 2935 | struct ReportLUNdata *logdev, u32 *nlogicals) |
edd16368 | 2936 | { |
03383736 | 2937 | if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) { |
edd16368 SC |
2938 | dev_err(&h->pdev->dev, "report physical LUNs failed.\n"); |
2939 | return -1; | |
2940 | } | |
03383736 | 2941 | *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24; |
edd16368 | 2942 | if (*nphysicals > HPSA_MAX_PHYS_LUN) { |
03383736 DB |
2943 | dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n", |
2944 | HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN); | |
edd16368 SC |
2945 | *nphysicals = HPSA_MAX_PHYS_LUN; |
2946 | } | |
03383736 | 2947 | if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) { |
edd16368 SC |
2948 | dev_err(&h->pdev->dev, "report logical LUNs failed.\n"); |
2949 | return -1; | |
2950 | } | |
6df1e954 | 2951 | *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8; |
edd16368 SC |
2952 | /* Reject Logicals in excess of our max capability. */ |
2953 | if (*nlogicals > HPSA_MAX_LUN) { | |
2954 | dev_warn(&h->pdev->dev, | |
2955 | "maximum logical LUNs (%d) exceeded. " | |
2956 | "%d LUNs ignored.\n", HPSA_MAX_LUN, | |
2957 | *nlogicals - HPSA_MAX_LUN); | |
2958 | *nlogicals = HPSA_MAX_LUN; | |
2959 | } | |
2960 | if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) { | |
2961 | dev_warn(&h->pdev->dev, | |
2962 | "maximum logical + physical LUNs (%d) exceeded. " | |
2963 | "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN, | |
2964 | *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN); | |
2965 | *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals; | |
2966 | } | |
2967 | return 0; | |
2968 | } | |
2969 | ||
42a91641 DB |
2970 | static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, |
2971 | int i, int nphysicals, int nlogicals, | |
a93aa1fe | 2972 | struct ReportExtendedLUNdata *physdev_list, |
339b2b14 SC |
2973 | struct ReportLUNdata *logdev_list) |
2974 | { | |
2975 | /* Helper function, figure out where the LUN ID info is coming from | |
2976 | * given index i, lists of physical and logical devices, where in | |
2977 | * the list the raid controller is supposed to appear (first or last) | |
2978 | */ | |
2979 | ||
2980 | int logicals_start = nphysicals + (raid_ctlr_position == 0); | |
2981 | int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0); | |
2982 | ||
2983 | if (i == raid_ctlr_position) | |
2984 | return RAID_CTLR_LUNID; | |
2985 | ||
2986 | if (i < logicals_start) | |
d5b5d964 SC |
2987 | return &physdev_list->LUN[i - |
2988 | (raid_ctlr_position == 0)].lunid[0]; | |
339b2b14 SC |
2989 | |
2990 | if (i < last_device) | |
2991 | return &logdev_list->LUN[i - nphysicals - | |
2992 | (raid_ctlr_position == 0)][0]; | |
2993 | BUG(); | |
2994 | return NULL; | |
2995 | } | |
2996 | ||
316b221a SC |
2997 | static int hpsa_hba_mode_enabled(struct ctlr_info *h) |
2998 | { | |
2999 | int rc; | |
6e8e8088 | 3000 | int hba_mode_enabled; |
316b221a SC |
3001 | struct bmic_controller_parameters *ctlr_params; |
3002 | ctlr_params = kzalloc(sizeof(struct bmic_controller_parameters), | |
3003 | GFP_KERNEL); | |
3004 | ||
3005 | if (!ctlr_params) | |
96444fbb | 3006 | return -ENOMEM; |
316b221a SC |
3007 | rc = hpsa_bmic_ctrl_mode_sense(h, RAID_CTLR_LUNID, 0, ctlr_params, |
3008 | sizeof(struct bmic_controller_parameters)); | |
96444fbb | 3009 | if (rc) { |
316b221a | 3010 | kfree(ctlr_params); |
96444fbb | 3011 | return rc; |
316b221a | 3012 | } |
6e8e8088 JH |
3013 | |
3014 | hba_mode_enabled = | |
3015 | ((ctlr_params->nvram_flags & HBA_MODE_ENABLED_FLAG) != 0); | |
3016 | kfree(ctlr_params); | |
3017 | return hba_mode_enabled; | |
316b221a SC |
3018 | } |
3019 | ||
03383736 DB |
3020 | /* get physical drive ioaccel handle and queue depth */ |
3021 | static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h, | |
3022 | struct hpsa_scsi_dev_t *dev, | |
3023 | u8 *lunaddrbytes, | |
3024 | struct bmic_identify_physical_device *id_phys) | |
3025 | { | |
3026 | int rc; | |
3027 | struct ext_report_lun_entry *rle = | |
3028 | (struct ext_report_lun_entry *) lunaddrbytes; | |
3029 | ||
3030 | dev->ioaccel_handle = rle->ioaccel_handle; | |
3031 | memset(id_phys, 0, sizeof(*id_phys)); | |
3032 | rc = hpsa_bmic_id_physical_device(h, lunaddrbytes, | |
3033 | GET_BMIC_DRIVE_NUMBER(lunaddrbytes), id_phys, | |
3034 | sizeof(*id_phys)); | |
3035 | if (!rc) | |
3036 | /* Reserve space for FW operations */ | |
3037 | #define DRIVE_CMDS_RESERVED_FOR_FW 2 | |
3038 | #define DRIVE_QUEUE_DEPTH 7 | |
3039 | dev->queue_depth = | |
3040 | le16_to_cpu(id_phys->current_queue_depth_limit) - | |
3041 | DRIVE_CMDS_RESERVED_FOR_FW; | |
3042 | else | |
3043 | dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */ | |
3044 | atomic_set(&dev->ioaccel_cmds_out, 0); | |
3045 | } | |
3046 | ||
edd16368 SC |
3047 | static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno) |
3048 | { | |
3049 | /* the idea here is we could get notified | |
3050 | * that some devices have changed, so we do a report | |
3051 | * physical luns and report logical luns cmd, and adjust | |
3052 | * our list of devices accordingly. | |
3053 | * | |
3054 | * The scsi3addr's of devices won't change so long as the | |
3055 | * adapter is not reset. That means we can rescan and | |
3056 | * tell which devices we already know about, vs. new | |
3057 | * devices, vs. disappearing devices. | |
3058 | */ | |
a93aa1fe | 3059 | struct ReportExtendedLUNdata *physdev_list = NULL; |
edd16368 | 3060 | struct ReportLUNdata *logdev_list = NULL; |
03383736 | 3061 | struct bmic_identify_physical_device *id_phys = NULL; |
01a02ffc SC |
3062 | u32 nphysicals = 0; |
3063 | u32 nlogicals = 0; | |
3064 | u32 ndev_allocated = 0; | |
edd16368 SC |
3065 | struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice; |
3066 | int ncurrent = 0; | |
4f4eb9f1 | 3067 | int i, n_ext_target_devs, ndevs_to_allocate; |
339b2b14 | 3068 | int raid_ctlr_position; |
2bbf5c7f | 3069 | int rescan_hba_mode; |
aca4a520 | 3070 | DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS); |
edd16368 | 3071 | |
cfe5badc | 3072 | currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL); |
92084715 SC |
3073 | physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL); |
3074 | logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL); | |
edd16368 | 3075 | tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL); |
03383736 | 3076 | id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL); |
edd16368 | 3077 | |
03383736 DB |
3078 | if (!currentsd || !physdev_list || !logdev_list || |
3079 | !tmpdevice || !id_phys) { | |
edd16368 SC |
3080 | dev_err(&h->pdev->dev, "out of memory\n"); |
3081 | goto out; | |
3082 | } | |
3083 | memset(lunzerobits, 0, sizeof(lunzerobits)); | |
3084 | ||
316b221a | 3085 | rescan_hba_mode = hpsa_hba_mode_enabled(h); |
96444fbb JH |
3086 | if (rescan_hba_mode < 0) |
3087 | goto out; | |
316b221a SC |
3088 | |
3089 | if (!h->hba_mode_enabled && rescan_hba_mode) | |
3090 | dev_warn(&h->pdev->dev, "HBA mode enabled\n"); | |
3091 | else if (h->hba_mode_enabled && !rescan_hba_mode) | |
3092 | dev_warn(&h->pdev->dev, "HBA mode disabled\n"); | |
3093 | ||
3094 | h->hba_mode_enabled = rescan_hba_mode; | |
3095 | ||
03383736 DB |
3096 | if (hpsa_gather_lun_info(h, physdev_list, &nphysicals, |
3097 | logdev_list, &nlogicals)) | |
edd16368 SC |
3098 | goto out; |
3099 | ||
aca4a520 ST |
3100 | /* We might see up to the maximum number of logical and physical disks |
3101 | * plus external target devices, and a device for the local RAID | |
3102 | * controller. | |
edd16368 | 3103 | */ |
aca4a520 | 3104 | ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1; |
edd16368 SC |
3105 | |
3106 | /* Allocate the per device structures */ | |
3107 | for (i = 0; i < ndevs_to_allocate; i++) { | |
b7ec021f ST |
3108 | if (i >= HPSA_MAX_DEVICES) { |
3109 | dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded." | |
3110 | " %d devices ignored.\n", HPSA_MAX_DEVICES, | |
3111 | ndevs_to_allocate - HPSA_MAX_DEVICES); | |
3112 | break; | |
3113 | } | |
3114 | ||
edd16368 SC |
3115 | currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL); |
3116 | if (!currentsd[i]) { | |
3117 | dev_warn(&h->pdev->dev, "out of memory at %s:%d\n", | |
3118 | __FILE__, __LINE__); | |
3119 | goto out; | |
3120 | } | |
3121 | ndev_allocated++; | |
3122 | } | |
3123 | ||
8645291b | 3124 | if (is_scsi_rev_5(h)) |
339b2b14 SC |
3125 | raid_ctlr_position = 0; |
3126 | else | |
3127 | raid_ctlr_position = nphysicals + nlogicals; | |
3128 | ||
edd16368 | 3129 | /* adjust our table of devices */ |
4f4eb9f1 | 3130 | n_ext_target_devs = 0; |
edd16368 | 3131 | for (i = 0; i < nphysicals + nlogicals + 1; i++) { |
0b0e1d6c | 3132 | u8 *lunaddrbytes, is_OBDR = 0; |
edd16368 SC |
3133 | |
3134 | /* Figure out where the LUN ID info is coming from */ | |
339b2b14 SC |
3135 | lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position, |
3136 | i, nphysicals, nlogicals, physdev_list, logdev_list); | |
edd16368 | 3137 | /* skip masked physical devices. */ |
339b2b14 SC |
3138 | if (lunaddrbytes[3] & 0xC0 && |
3139 | i < nphysicals + (raid_ctlr_position == 0)) | |
edd16368 SC |
3140 | continue; |
3141 | ||
3142 | /* Get device type, vendor, model, device id */ | |
0b0e1d6c SC |
3143 | if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice, |
3144 | &is_OBDR)) | |
edd16368 | 3145 | continue; /* skip it if we can't talk to it. */ |
1f310bde | 3146 | figure_bus_target_lun(h, lunaddrbytes, tmpdevice); |
edd16368 SC |
3147 | this_device = currentsd[ncurrent]; |
3148 | ||
3149 | /* | |
4f4eb9f1 | 3150 | * For external target devices, we have to insert a LUN 0 which |
edd16368 SC |
3151 | * doesn't show up in CCISS_REPORT_PHYSICAL data, but there |
3152 | * is nonetheless an enclosure device there. We have to | |
3153 | * present that otherwise linux won't find anything if | |
3154 | * there is no lun 0. | |
3155 | */ | |
4f4eb9f1 | 3156 | if (add_ext_target_dev(h, tmpdevice, this_device, |
1f310bde | 3157 | lunaddrbytes, lunzerobits, |
4f4eb9f1 | 3158 | &n_ext_target_devs)) { |
edd16368 SC |
3159 | ncurrent++; |
3160 | this_device = currentsd[ncurrent]; | |
3161 | } | |
3162 | ||
3163 | *this_device = *tmpdevice; | |
edd16368 SC |
3164 | |
3165 | switch (this_device->devtype) { | |
0b0e1d6c | 3166 | case TYPE_ROM: |
edd16368 SC |
3167 | /* We don't *really* support actual CD-ROM devices, |
3168 | * just "One Button Disaster Recovery" tape drive | |
3169 | * which temporarily pretends to be a CD-ROM drive. | |
3170 | * So we check that the device is really an OBDR tape | |
3171 | * device by checking for "$DR-10" in bytes 43-48 of | |
3172 | * the inquiry data. | |
3173 | */ | |
0b0e1d6c SC |
3174 | if (is_OBDR) |
3175 | ncurrent++; | |
edd16368 SC |
3176 | break; |
3177 | case TYPE_DISK: | |
316b221a SC |
3178 | if (h->hba_mode_enabled) { |
3179 | /* never use raid mapper in HBA mode */ | |
3180 | this_device->offload_enabled = 0; | |
3181 | ncurrent++; | |
3182 | break; | |
3183 | } else if (h->acciopath_status) { | |
3184 | if (i >= nphysicals) { | |
3185 | ncurrent++; | |
3186 | break; | |
3187 | } | |
3188 | } else { | |
3189 | if (i < nphysicals) | |
3190 | break; | |
283b4a9b | 3191 | ncurrent++; |
edd16368 | 3192 | break; |
283b4a9b | 3193 | } |
03383736 DB |
3194 | if (h->transMethod & CFGTBL_Trans_io_accel1 || |
3195 | h->transMethod & CFGTBL_Trans_io_accel2) { | |
3196 | hpsa_get_ioaccel_drive_info(h, this_device, | |
3197 | lunaddrbytes, id_phys); | |
3198 | atomic_set(&this_device->ioaccel_cmds_out, 0); | |
283b4a9b SC |
3199 | ncurrent++; |
3200 | } | |
edd16368 SC |
3201 | break; |
3202 | case TYPE_TAPE: | |
3203 | case TYPE_MEDIUM_CHANGER: | |
3204 | ncurrent++; | |
3205 | break; | |
3206 | case TYPE_RAID: | |
3207 | /* Only present the Smartarray HBA as a RAID controller. | |
3208 | * If it's a RAID controller other than the HBA itself | |
3209 | * (an external RAID controller, MSA500 or similar) | |
3210 | * don't present it. | |
3211 | */ | |
3212 | if (!is_hba_lunid(lunaddrbytes)) | |
3213 | break; | |
3214 | ncurrent++; | |
3215 | break; | |
3216 | default: | |
3217 | break; | |
3218 | } | |
cfe5badc | 3219 | if (ncurrent >= HPSA_MAX_DEVICES) |
edd16368 SC |
3220 | break; |
3221 | } | |
03383736 | 3222 | hpsa_update_log_drive_phys_drive_ptrs(h, currentsd, ncurrent); |
edd16368 SC |
3223 | adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent); |
3224 | out: | |
3225 | kfree(tmpdevice); | |
3226 | for (i = 0; i < ndev_allocated; i++) | |
3227 | kfree(currentsd[i]); | |
3228 | kfree(currentsd); | |
edd16368 SC |
3229 | kfree(physdev_list); |
3230 | kfree(logdev_list); | |
03383736 | 3231 | kfree(id_phys); |
edd16368 SC |
3232 | } |
3233 | ||
c7ee65b3 WS |
3234 | /* |
3235 | * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci | |
edd16368 SC |
3236 | * dma mapping and fills in the scatter gather entries of the |
3237 | * hpsa command, cp. | |
3238 | */ | |
33a2ffce | 3239 | static int hpsa_scatter_gather(struct ctlr_info *h, |
edd16368 SC |
3240 | struct CommandList *cp, |
3241 | struct scsi_cmnd *cmd) | |
3242 | { | |
3243 | unsigned int len; | |
3244 | struct scatterlist *sg; | |
01a02ffc | 3245 | u64 addr64; |
33a2ffce SC |
3246 | int use_sg, i, sg_index, chained; |
3247 | struct SGDescriptor *curr_sg; | |
edd16368 | 3248 | |
33a2ffce | 3249 | BUG_ON(scsi_sg_count(cmd) > h->maxsgentries); |
edd16368 SC |
3250 | |
3251 | use_sg = scsi_dma_map(cmd); | |
3252 | if (use_sg < 0) | |
3253 | return use_sg; | |
3254 | ||
3255 | if (!use_sg) | |
3256 | goto sglist_finished; | |
3257 | ||
33a2ffce SC |
3258 | curr_sg = cp->SG; |
3259 | chained = 0; | |
3260 | sg_index = 0; | |
edd16368 | 3261 | scsi_for_each_sg(cmd, sg, use_sg, i) { |
33a2ffce SC |
3262 | if (i == h->max_cmd_sg_entries - 1 && |
3263 | use_sg > h->max_cmd_sg_entries) { | |
3264 | chained = 1; | |
3265 | curr_sg = h->cmd_sg_list[cp->cmdindex]; | |
3266 | sg_index = 0; | |
3267 | } | |
01a02ffc | 3268 | addr64 = (u64) sg_dma_address(sg); |
edd16368 | 3269 | len = sg_dma_len(sg); |
50a0decf SC |
3270 | curr_sg->Addr = cpu_to_le64(addr64); |
3271 | curr_sg->Len = cpu_to_le32(len); | |
3272 | curr_sg->Ext = cpu_to_le32(0); | |
33a2ffce SC |
3273 | curr_sg++; |
3274 | } | |
50a0decf | 3275 | (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST); |
33a2ffce SC |
3276 | |
3277 | if (use_sg + chained > h->maxSG) | |
3278 | h->maxSG = use_sg + chained; | |
3279 | ||
3280 | if (chained) { | |
3281 | cp->Header.SGList = h->max_cmd_sg_entries; | |
50a0decf | 3282 | cp->Header.SGTotal = cpu_to_le16(use_sg + 1); |
e2bea6df SC |
3283 | if (hpsa_map_sg_chain_block(h, cp)) { |
3284 | scsi_dma_unmap(cmd); | |
3285 | return -1; | |
3286 | } | |
33a2ffce | 3287 | return 0; |
edd16368 SC |
3288 | } |
3289 | ||
3290 | sglist_finished: | |
3291 | ||
01a02ffc | 3292 | cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */ |
c7ee65b3 | 3293 | cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */ |
edd16368 SC |
3294 | return 0; |
3295 | } | |
3296 | ||
283b4a9b SC |
3297 | #define IO_ACCEL_INELIGIBLE (1) |
3298 | static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len) | |
3299 | { | |
3300 | int is_write = 0; | |
3301 | u32 block; | |
3302 | u32 block_cnt; | |
3303 | ||
3304 | /* Perform some CDB fixups if needed using 10 byte reads/writes only */ | |
3305 | switch (cdb[0]) { | |
3306 | case WRITE_6: | |
3307 | case WRITE_12: | |
3308 | is_write = 1; | |
3309 | case READ_6: | |
3310 | case READ_12: | |
3311 | if (*cdb_len == 6) { | |
3312 | block = (((u32) cdb[2]) << 8) | cdb[3]; | |
3313 | block_cnt = cdb[4]; | |
3314 | } else { | |
3315 | BUG_ON(*cdb_len != 12); | |
3316 | block = (((u32) cdb[2]) << 24) | | |
3317 | (((u32) cdb[3]) << 16) | | |
3318 | (((u32) cdb[4]) << 8) | | |
3319 | cdb[5]; | |
3320 | block_cnt = | |
3321 | (((u32) cdb[6]) << 24) | | |
3322 | (((u32) cdb[7]) << 16) | | |
3323 | (((u32) cdb[8]) << 8) | | |
3324 | cdb[9]; | |
3325 | } | |
3326 | if (block_cnt > 0xffff) | |
3327 | return IO_ACCEL_INELIGIBLE; | |
3328 | ||
3329 | cdb[0] = is_write ? WRITE_10 : READ_10; | |
3330 | cdb[1] = 0; | |
3331 | cdb[2] = (u8) (block >> 24); | |
3332 | cdb[3] = (u8) (block >> 16); | |
3333 | cdb[4] = (u8) (block >> 8); | |
3334 | cdb[5] = (u8) (block); | |
3335 | cdb[6] = 0; | |
3336 | cdb[7] = (u8) (block_cnt >> 8); | |
3337 | cdb[8] = (u8) (block_cnt); | |
3338 | cdb[9] = 0; | |
3339 | *cdb_len = 10; | |
3340 | break; | |
3341 | } | |
3342 | return 0; | |
3343 | } | |
3344 | ||
c349775e | 3345 | static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h, |
283b4a9b | 3346 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, |
03383736 | 3347 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) |
e1f7de0c MG |
3348 | { |
3349 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
e1f7de0c MG |
3350 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex]; |
3351 | unsigned int len; | |
3352 | unsigned int total_len = 0; | |
3353 | struct scatterlist *sg; | |
3354 | u64 addr64; | |
3355 | int use_sg, i; | |
3356 | struct SGDescriptor *curr_sg; | |
3357 | u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE; | |
3358 | ||
283b4a9b | 3359 | /* TODO: implement chaining support */ |
03383736 DB |
3360 | if (scsi_sg_count(cmd) > h->ioaccel_maxsg) { |
3361 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
283b4a9b | 3362 | return IO_ACCEL_INELIGIBLE; |
03383736 | 3363 | } |
283b4a9b | 3364 | |
e1f7de0c MG |
3365 | BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX); |
3366 | ||
03383736 DB |
3367 | if (fixup_ioaccel_cdb(cdb, &cdb_len)) { |
3368 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
283b4a9b | 3369 | return IO_ACCEL_INELIGIBLE; |
03383736 | 3370 | } |
283b4a9b | 3371 | |
e1f7de0c MG |
3372 | c->cmd_type = CMD_IOACCEL1; |
3373 | ||
3374 | /* Adjust the DMA address to point to the accelerated command buffer */ | |
3375 | c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle + | |
3376 | (c->cmdindex * sizeof(*cp)); | |
3377 | BUG_ON(c->busaddr & 0x0000007F); | |
3378 | ||
3379 | use_sg = scsi_dma_map(cmd); | |
03383736 DB |
3380 | if (use_sg < 0) { |
3381 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
e1f7de0c | 3382 | return use_sg; |
03383736 | 3383 | } |
e1f7de0c MG |
3384 | |
3385 | if (use_sg) { | |
3386 | curr_sg = cp->SG; | |
3387 | scsi_for_each_sg(cmd, sg, use_sg, i) { | |
3388 | addr64 = (u64) sg_dma_address(sg); | |
3389 | len = sg_dma_len(sg); | |
3390 | total_len += len; | |
50a0decf SC |
3391 | curr_sg->Addr = cpu_to_le64(addr64); |
3392 | curr_sg->Len = cpu_to_le32(len); | |
3393 | curr_sg->Ext = cpu_to_le32(0); | |
e1f7de0c MG |
3394 | curr_sg++; |
3395 | } | |
50a0decf | 3396 | (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST); |
e1f7de0c MG |
3397 | |
3398 | switch (cmd->sc_data_direction) { | |
3399 | case DMA_TO_DEVICE: | |
3400 | control |= IOACCEL1_CONTROL_DATA_OUT; | |
3401 | break; | |
3402 | case DMA_FROM_DEVICE: | |
3403 | control |= IOACCEL1_CONTROL_DATA_IN; | |
3404 | break; | |
3405 | case DMA_NONE: | |
3406 | control |= IOACCEL1_CONTROL_NODATAXFER; | |
3407 | break; | |
3408 | default: | |
3409 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
3410 | cmd->sc_data_direction); | |
3411 | BUG(); | |
3412 | break; | |
3413 | } | |
3414 | } else { | |
3415 | control |= IOACCEL1_CONTROL_NODATAXFER; | |
3416 | } | |
3417 | ||
c349775e | 3418 | c->Header.SGList = use_sg; |
e1f7de0c | 3419 | /* Fill out the command structure to submit */ |
2b08b3e9 DB |
3420 | cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF); |
3421 | cp->transfer_len = cpu_to_le32(total_len); | |
3422 | cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ | | |
3423 | (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK)); | |
3424 | cp->control = cpu_to_le32(control); | |
283b4a9b SC |
3425 | memcpy(cp->CDB, cdb, cdb_len); |
3426 | memcpy(cp->CISS_LUN, scsi3addr, 8); | |
c349775e | 3427 | /* Tag was already set at init time. */ |
283b4a9b | 3428 | enqueue_cmd_and_start_io(h, c); |
e1f7de0c MG |
3429 | return 0; |
3430 | } | |
edd16368 | 3431 | |
283b4a9b SC |
3432 | /* |
3433 | * Queue a command directly to a device behind the controller using the | |
3434 | * I/O accelerator path. | |
3435 | */ | |
3436 | static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h, | |
3437 | struct CommandList *c) | |
3438 | { | |
3439 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
3440 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
3441 | ||
03383736 DB |
3442 | c->phys_disk = dev; |
3443 | ||
283b4a9b | 3444 | return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle, |
03383736 | 3445 | cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev); |
283b4a9b SC |
3446 | } |
3447 | ||
dd0e19f3 ST |
3448 | /* |
3449 | * Set encryption parameters for the ioaccel2 request | |
3450 | */ | |
3451 | static void set_encrypt_ioaccel2(struct ctlr_info *h, | |
3452 | struct CommandList *c, struct io_accel2_cmd *cp) | |
3453 | { | |
3454 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
3455 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
3456 | struct raid_map_data *map = &dev->raid_map; | |
3457 | u64 first_block; | |
3458 | ||
dd0e19f3 | 3459 | /* Are we doing encryption on this device */ |
2b08b3e9 | 3460 | if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON)) |
dd0e19f3 ST |
3461 | return; |
3462 | /* Set the data encryption key index. */ | |
3463 | cp->dekindex = map->dekindex; | |
3464 | ||
3465 | /* Set the encryption enable flag, encoded into direction field. */ | |
3466 | cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK; | |
3467 | ||
3468 | /* Set encryption tweak values based on logical block address | |
3469 | * If block size is 512, tweak value is LBA. | |
3470 | * For other block sizes, tweak is (LBA * block size)/ 512) | |
3471 | */ | |
3472 | switch (cmd->cmnd[0]) { | |
3473 | /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */ | |
3474 | case WRITE_6: | |
3475 | case READ_6: | |
2b08b3e9 | 3476 | first_block = get_unaligned_be16(&cmd->cmnd[2]); |
dd0e19f3 ST |
3477 | break; |
3478 | case WRITE_10: | |
3479 | case READ_10: | |
dd0e19f3 ST |
3480 | /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */ |
3481 | case WRITE_12: | |
3482 | case READ_12: | |
2b08b3e9 | 3483 | first_block = get_unaligned_be32(&cmd->cmnd[2]); |
dd0e19f3 ST |
3484 | break; |
3485 | case WRITE_16: | |
3486 | case READ_16: | |
2b08b3e9 | 3487 | first_block = get_unaligned_be64(&cmd->cmnd[2]); |
dd0e19f3 ST |
3488 | break; |
3489 | default: | |
3490 | dev_err(&h->pdev->dev, | |
2b08b3e9 DB |
3491 | "ERROR: %s: size (0x%x) not supported for encryption\n", |
3492 | __func__, cmd->cmnd[0]); | |
dd0e19f3 ST |
3493 | BUG(); |
3494 | break; | |
3495 | } | |
2b08b3e9 DB |
3496 | |
3497 | if (le32_to_cpu(map->volume_blk_size) != 512) | |
3498 | first_block = first_block * | |
3499 | le32_to_cpu(map->volume_blk_size)/512; | |
3500 | ||
3501 | cp->tweak_lower = cpu_to_le32(first_block); | |
3502 | cp->tweak_upper = cpu_to_le32(first_block >> 32); | |
dd0e19f3 ST |
3503 | } |
3504 | ||
c349775e ST |
3505 | static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h, |
3506 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
03383736 | 3507 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) |
c349775e ST |
3508 | { |
3509 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
3510 | struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex]; | |
3511 | struct ioaccel2_sg_element *curr_sg; | |
3512 | int use_sg, i; | |
3513 | struct scatterlist *sg; | |
3514 | u64 addr64; | |
3515 | u32 len; | |
3516 | u32 total_len = 0; | |
3517 | ||
03383736 DB |
3518 | if (scsi_sg_count(cmd) > h->ioaccel_maxsg) { |
3519 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
c349775e | 3520 | return IO_ACCEL_INELIGIBLE; |
03383736 | 3521 | } |
c349775e | 3522 | |
03383736 DB |
3523 | if (fixup_ioaccel_cdb(cdb, &cdb_len)) { |
3524 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
c349775e | 3525 | return IO_ACCEL_INELIGIBLE; |
03383736 DB |
3526 | } |
3527 | ||
c349775e ST |
3528 | c->cmd_type = CMD_IOACCEL2; |
3529 | /* Adjust the DMA address to point to the accelerated command buffer */ | |
3530 | c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle + | |
3531 | (c->cmdindex * sizeof(*cp)); | |
3532 | BUG_ON(c->busaddr & 0x0000007F); | |
3533 | ||
3534 | memset(cp, 0, sizeof(*cp)); | |
3535 | cp->IU_type = IOACCEL2_IU_TYPE; | |
3536 | ||
3537 | use_sg = scsi_dma_map(cmd); | |
03383736 DB |
3538 | if (use_sg < 0) { |
3539 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
c349775e | 3540 | return use_sg; |
03383736 | 3541 | } |
c349775e ST |
3542 | |
3543 | if (use_sg) { | |
3544 | BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES); | |
3545 | curr_sg = cp->sg; | |
3546 | scsi_for_each_sg(cmd, sg, use_sg, i) { | |
3547 | addr64 = (u64) sg_dma_address(sg); | |
3548 | len = sg_dma_len(sg); | |
3549 | total_len += len; | |
3550 | curr_sg->address = cpu_to_le64(addr64); | |
3551 | curr_sg->length = cpu_to_le32(len); | |
3552 | curr_sg->reserved[0] = 0; | |
3553 | curr_sg->reserved[1] = 0; | |
3554 | curr_sg->reserved[2] = 0; | |
3555 | curr_sg->chain_indicator = 0; | |
3556 | curr_sg++; | |
3557 | } | |
3558 | ||
3559 | switch (cmd->sc_data_direction) { | |
3560 | case DMA_TO_DEVICE: | |
dd0e19f3 ST |
3561 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
3562 | cp->direction |= IOACCEL2_DIR_DATA_OUT; | |
c349775e ST |
3563 | break; |
3564 | case DMA_FROM_DEVICE: | |
dd0e19f3 ST |
3565 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
3566 | cp->direction |= IOACCEL2_DIR_DATA_IN; | |
c349775e ST |
3567 | break; |
3568 | case DMA_NONE: | |
dd0e19f3 ST |
3569 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
3570 | cp->direction |= IOACCEL2_DIR_NO_DATA; | |
c349775e ST |
3571 | break; |
3572 | default: | |
3573 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
3574 | cmd->sc_data_direction); | |
3575 | BUG(); | |
3576 | break; | |
3577 | } | |
3578 | } else { | |
dd0e19f3 ST |
3579 | cp->direction &= ~IOACCEL2_DIRECTION_MASK; |
3580 | cp->direction |= IOACCEL2_DIR_NO_DATA; | |
c349775e | 3581 | } |
dd0e19f3 ST |
3582 | |
3583 | /* Set encryption parameters, if necessary */ | |
3584 | set_encrypt_ioaccel2(h, c, cp); | |
3585 | ||
2b08b3e9 | 3586 | cp->scsi_nexus = cpu_to_le32(ioaccel_handle); |
f2405db8 | 3587 | cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT); |
c349775e | 3588 | memcpy(cp->cdb, cdb, sizeof(cp->cdb)); |
c349775e ST |
3589 | |
3590 | /* fill in sg elements */ | |
3591 | cp->sg_count = (u8) use_sg; | |
3592 | ||
3593 | cp->data_len = cpu_to_le32(total_len); | |
3594 | cp->err_ptr = cpu_to_le64(c->busaddr + | |
3595 | offsetof(struct io_accel2_cmd, error_data)); | |
50a0decf | 3596 | cp->err_len = cpu_to_le32(sizeof(cp->error_data)); |
c349775e ST |
3597 | |
3598 | enqueue_cmd_and_start_io(h, c); | |
3599 | return 0; | |
3600 | } | |
3601 | ||
3602 | /* | |
3603 | * Queue a command to the correct I/O accelerator path. | |
3604 | */ | |
3605 | static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h, | |
3606 | struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len, | |
03383736 | 3607 | u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk) |
c349775e | 3608 | { |
03383736 DB |
3609 | /* Try to honor the device's queue depth */ |
3610 | if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) > | |
3611 | phys_disk->queue_depth) { | |
3612 | atomic_dec(&phys_disk->ioaccel_cmds_out); | |
3613 | return IO_ACCEL_INELIGIBLE; | |
3614 | } | |
c349775e ST |
3615 | if (h->transMethod & CFGTBL_Trans_io_accel1) |
3616 | return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle, | |
03383736 DB |
3617 | cdb, cdb_len, scsi3addr, |
3618 | phys_disk); | |
c349775e ST |
3619 | else |
3620 | return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle, | |
03383736 DB |
3621 | cdb, cdb_len, scsi3addr, |
3622 | phys_disk); | |
c349775e ST |
3623 | } |
3624 | ||
6b80b18f ST |
3625 | static void raid_map_helper(struct raid_map_data *map, |
3626 | int offload_to_mirror, u32 *map_index, u32 *current_group) | |
3627 | { | |
3628 | if (offload_to_mirror == 0) { | |
3629 | /* use physical disk in the first mirrored group. */ | |
2b08b3e9 | 3630 | *map_index %= le16_to_cpu(map->data_disks_per_row); |
6b80b18f ST |
3631 | return; |
3632 | } | |
3633 | do { | |
3634 | /* determine mirror group that *map_index indicates */ | |
2b08b3e9 DB |
3635 | *current_group = *map_index / |
3636 | le16_to_cpu(map->data_disks_per_row); | |
6b80b18f ST |
3637 | if (offload_to_mirror == *current_group) |
3638 | continue; | |
2b08b3e9 | 3639 | if (*current_group < le16_to_cpu(map->layout_map_count) - 1) { |
6b80b18f | 3640 | /* select map index from next group */ |
2b08b3e9 | 3641 | *map_index += le16_to_cpu(map->data_disks_per_row); |
6b80b18f ST |
3642 | (*current_group)++; |
3643 | } else { | |
3644 | /* select map index from first group */ | |
2b08b3e9 | 3645 | *map_index %= le16_to_cpu(map->data_disks_per_row); |
6b80b18f ST |
3646 | *current_group = 0; |
3647 | } | |
3648 | } while (offload_to_mirror != *current_group); | |
3649 | } | |
3650 | ||
283b4a9b SC |
3651 | /* |
3652 | * Attempt to perform offload RAID mapping for a logical volume I/O. | |
3653 | */ | |
3654 | static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h, | |
3655 | struct CommandList *c) | |
3656 | { | |
3657 | struct scsi_cmnd *cmd = c->scsi_cmd; | |
3658 | struct hpsa_scsi_dev_t *dev = cmd->device->hostdata; | |
3659 | struct raid_map_data *map = &dev->raid_map; | |
3660 | struct raid_map_disk_data *dd = &map->data[0]; | |
3661 | int is_write = 0; | |
3662 | u32 map_index; | |
3663 | u64 first_block, last_block; | |
3664 | u32 block_cnt; | |
3665 | u32 blocks_per_row; | |
3666 | u64 first_row, last_row; | |
3667 | u32 first_row_offset, last_row_offset; | |
3668 | u32 first_column, last_column; | |
6b80b18f ST |
3669 | u64 r0_first_row, r0_last_row; |
3670 | u32 r5or6_blocks_per_row; | |
3671 | u64 r5or6_first_row, r5or6_last_row; | |
3672 | u32 r5or6_first_row_offset, r5or6_last_row_offset; | |
3673 | u32 r5or6_first_column, r5or6_last_column; | |
3674 | u32 total_disks_per_row; | |
3675 | u32 stripesize; | |
3676 | u32 first_group, last_group, current_group; | |
283b4a9b SC |
3677 | u32 map_row; |
3678 | u32 disk_handle; | |
3679 | u64 disk_block; | |
3680 | u32 disk_block_cnt; | |
3681 | u8 cdb[16]; | |
3682 | u8 cdb_len; | |
2b08b3e9 | 3683 | u16 strip_size; |
283b4a9b SC |
3684 | #if BITS_PER_LONG == 32 |
3685 | u64 tmpdiv; | |
3686 | #endif | |
6b80b18f | 3687 | int offload_to_mirror; |
283b4a9b | 3688 | |
283b4a9b SC |
3689 | /* check for valid opcode, get LBA and block count */ |
3690 | switch (cmd->cmnd[0]) { | |
3691 | case WRITE_6: | |
3692 | is_write = 1; | |
3693 | case READ_6: | |
3694 | first_block = | |
3695 | (((u64) cmd->cmnd[2]) << 8) | | |
3696 | cmd->cmnd[3]; | |
3697 | block_cnt = cmd->cmnd[4]; | |
3fa89a04 SC |
3698 | if (block_cnt == 0) |
3699 | block_cnt = 256; | |
283b4a9b SC |
3700 | break; |
3701 | case WRITE_10: | |
3702 | is_write = 1; | |
3703 | case READ_10: | |
3704 | first_block = | |
3705 | (((u64) cmd->cmnd[2]) << 24) | | |
3706 | (((u64) cmd->cmnd[3]) << 16) | | |
3707 | (((u64) cmd->cmnd[4]) << 8) | | |
3708 | cmd->cmnd[5]; | |
3709 | block_cnt = | |
3710 | (((u32) cmd->cmnd[7]) << 8) | | |
3711 | cmd->cmnd[8]; | |
3712 | break; | |
3713 | case WRITE_12: | |
3714 | is_write = 1; | |
3715 | case READ_12: | |
3716 | first_block = | |
3717 | (((u64) cmd->cmnd[2]) << 24) | | |
3718 | (((u64) cmd->cmnd[3]) << 16) | | |
3719 | (((u64) cmd->cmnd[4]) << 8) | | |
3720 | cmd->cmnd[5]; | |
3721 | block_cnt = | |
3722 | (((u32) cmd->cmnd[6]) << 24) | | |
3723 | (((u32) cmd->cmnd[7]) << 16) | | |
3724 | (((u32) cmd->cmnd[8]) << 8) | | |
3725 | cmd->cmnd[9]; | |
3726 | break; | |
3727 | case WRITE_16: | |
3728 | is_write = 1; | |
3729 | case READ_16: | |
3730 | first_block = | |
3731 | (((u64) cmd->cmnd[2]) << 56) | | |
3732 | (((u64) cmd->cmnd[3]) << 48) | | |
3733 | (((u64) cmd->cmnd[4]) << 40) | | |
3734 | (((u64) cmd->cmnd[5]) << 32) | | |
3735 | (((u64) cmd->cmnd[6]) << 24) | | |
3736 | (((u64) cmd->cmnd[7]) << 16) | | |
3737 | (((u64) cmd->cmnd[8]) << 8) | | |
3738 | cmd->cmnd[9]; | |
3739 | block_cnt = | |
3740 | (((u32) cmd->cmnd[10]) << 24) | | |
3741 | (((u32) cmd->cmnd[11]) << 16) | | |
3742 | (((u32) cmd->cmnd[12]) << 8) | | |
3743 | cmd->cmnd[13]; | |
3744 | break; | |
3745 | default: | |
3746 | return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */ | |
3747 | } | |
283b4a9b SC |
3748 | last_block = first_block + block_cnt - 1; |
3749 | ||
3750 | /* check for write to non-RAID-0 */ | |
3751 | if (is_write && dev->raid_level != 0) | |
3752 | return IO_ACCEL_INELIGIBLE; | |
3753 | ||
3754 | /* check for invalid block or wraparound */ | |
2b08b3e9 DB |
3755 | if (last_block >= le64_to_cpu(map->volume_blk_cnt) || |
3756 | last_block < first_block) | |
283b4a9b SC |
3757 | return IO_ACCEL_INELIGIBLE; |
3758 | ||
3759 | /* calculate stripe information for the request */ | |
2b08b3e9 DB |
3760 | blocks_per_row = le16_to_cpu(map->data_disks_per_row) * |
3761 | le16_to_cpu(map->strip_size); | |
3762 | strip_size = le16_to_cpu(map->strip_size); | |
283b4a9b SC |
3763 | #if BITS_PER_LONG == 32 |
3764 | tmpdiv = first_block; | |
3765 | (void) do_div(tmpdiv, blocks_per_row); | |
3766 | first_row = tmpdiv; | |
3767 | tmpdiv = last_block; | |
3768 | (void) do_div(tmpdiv, blocks_per_row); | |
3769 | last_row = tmpdiv; | |
3770 | first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); | |
3771 | last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); | |
3772 | tmpdiv = first_row_offset; | |
2b08b3e9 | 3773 | (void) do_div(tmpdiv, strip_size); |
283b4a9b SC |
3774 | first_column = tmpdiv; |
3775 | tmpdiv = last_row_offset; | |
2b08b3e9 | 3776 | (void) do_div(tmpdiv, strip_size); |
283b4a9b SC |
3777 | last_column = tmpdiv; |
3778 | #else | |
3779 | first_row = first_block / blocks_per_row; | |
3780 | last_row = last_block / blocks_per_row; | |
3781 | first_row_offset = (u32) (first_block - (first_row * blocks_per_row)); | |
3782 | last_row_offset = (u32) (last_block - (last_row * blocks_per_row)); | |
2b08b3e9 DB |
3783 | first_column = first_row_offset / strip_size; |
3784 | last_column = last_row_offset / strip_size; | |
283b4a9b SC |
3785 | #endif |
3786 | ||
3787 | /* if this isn't a single row/column then give to the controller */ | |
3788 | if ((first_row != last_row) || (first_column != last_column)) | |
3789 | return IO_ACCEL_INELIGIBLE; | |
3790 | ||
3791 | /* proceeding with driver mapping */ | |
2b08b3e9 DB |
3792 | total_disks_per_row = le16_to_cpu(map->data_disks_per_row) + |
3793 | le16_to_cpu(map->metadata_disks_per_row); | |
283b4a9b | 3794 | map_row = ((u32)(first_row >> map->parity_rotation_shift)) % |
2b08b3e9 | 3795 | le16_to_cpu(map->row_cnt); |
6b80b18f ST |
3796 | map_index = (map_row * total_disks_per_row) + first_column; |
3797 | ||
3798 | switch (dev->raid_level) { | |
3799 | case HPSA_RAID_0: | |
3800 | break; /* nothing special to do */ | |
3801 | case HPSA_RAID_1: | |
3802 | /* Handles load balance across RAID 1 members. | |
3803 | * (2-drive R1 and R10 with even # of drives.) | |
3804 | * Appropriate for SSDs, not optimal for HDDs | |
283b4a9b | 3805 | */ |
2b08b3e9 | 3806 | BUG_ON(le16_to_cpu(map->layout_map_count) != 2); |
283b4a9b | 3807 | if (dev->offload_to_mirror) |
2b08b3e9 | 3808 | map_index += le16_to_cpu(map->data_disks_per_row); |
283b4a9b | 3809 | dev->offload_to_mirror = !dev->offload_to_mirror; |
6b80b18f ST |
3810 | break; |
3811 | case HPSA_RAID_ADM: | |
3812 | /* Handles N-way mirrors (R1-ADM) | |
3813 | * and R10 with # of drives divisible by 3.) | |
3814 | */ | |
2b08b3e9 | 3815 | BUG_ON(le16_to_cpu(map->layout_map_count) != 3); |
6b80b18f ST |
3816 | |
3817 | offload_to_mirror = dev->offload_to_mirror; | |
3818 | raid_map_helper(map, offload_to_mirror, | |
3819 | &map_index, ¤t_group); | |
3820 | /* set mirror group to use next time */ | |
3821 | offload_to_mirror = | |
2b08b3e9 DB |
3822 | (offload_to_mirror >= |
3823 | le16_to_cpu(map->layout_map_count) - 1) | |
6b80b18f | 3824 | ? 0 : offload_to_mirror + 1; |
6b80b18f ST |
3825 | dev->offload_to_mirror = offload_to_mirror; |
3826 | /* Avoid direct use of dev->offload_to_mirror within this | |
3827 | * function since multiple threads might simultaneously | |
3828 | * increment it beyond the range of dev->layout_map_count -1. | |
3829 | */ | |
3830 | break; | |
3831 | case HPSA_RAID_5: | |
3832 | case HPSA_RAID_6: | |
2b08b3e9 | 3833 | if (le16_to_cpu(map->layout_map_count) <= 1) |
6b80b18f ST |
3834 | break; |
3835 | ||
3836 | /* Verify first and last block are in same RAID group */ | |
3837 | r5or6_blocks_per_row = | |
2b08b3e9 DB |
3838 | le16_to_cpu(map->strip_size) * |
3839 | le16_to_cpu(map->data_disks_per_row); | |
6b80b18f | 3840 | BUG_ON(r5or6_blocks_per_row == 0); |
2b08b3e9 DB |
3841 | stripesize = r5or6_blocks_per_row * |
3842 | le16_to_cpu(map->layout_map_count); | |
6b80b18f ST |
3843 | #if BITS_PER_LONG == 32 |
3844 | tmpdiv = first_block; | |
3845 | first_group = do_div(tmpdiv, stripesize); | |
3846 | tmpdiv = first_group; | |
3847 | (void) do_div(tmpdiv, r5or6_blocks_per_row); | |
3848 | first_group = tmpdiv; | |
3849 | tmpdiv = last_block; | |
3850 | last_group = do_div(tmpdiv, stripesize); | |
3851 | tmpdiv = last_group; | |
3852 | (void) do_div(tmpdiv, r5or6_blocks_per_row); | |
3853 | last_group = tmpdiv; | |
3854 | #else | |
3855 | first_group = (first_block % stripesize) / r5or6_blocks_per_row; | |
3856 | last_group = (last_block % stripesize) / r5or6_blocks_per_row; | |
6b80b18f | 3857 | #endif |
000ff7c2 | 3858 | if (first_group != last_group) |
6b80b18f ST |
3859 | return IO_ACCEL_INELIGIBLE; |
3860 | ||
3861 | /* Verify request is in a single row of RAID 5/6 */ | |
3862 | #if BITS_PER_LONG == 32 | |
3863 | tmpdiv = first_block; | |
3864 | (void) do_div(tmpdiv, stripesize); | |
3865 | first_row = r5or6_first_row = r0_first_row = tmpdiv; | |
3866 | tmpdiv = last_block; | |
3867 | (void) do_div(tmpdiv, stripesize); | |
3868 | r5or6_last_row = r0_last_row = tmpdiv; | |
3869 | #else | |
3870 | first_row = r5or6_first_row = r0_first_row = | |
3871 | first_block / stripesize; | |
3872 | r5or6_last_row = r0_last_row = last_block / stripesize; | |
3873 | #endif | |
3874 | if (r5or6_first_row != r5or6_last_row) | |
3875 | return IO_ACCEL_INELIGIBLE; | |
3876 | ||
3877 | ||
3878 | /* Verify request is in a single column */ | |
3879 | #if BITS_PER_LONG == 32 | |
3880 | tmpdiv = first_block; | |
3881 | first_row_offset = do_div(tmpdiv, stripesize); | |
3882 | tmpdiv = first_row_offset; | |
3883 | first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row); | |
3884 | r5or6_first_row_offset = first_row_offset; | |
3885 | tmpdiv = last_block; | |
3886 | r5or6_last_row_offset = do_div(tmpdiv, stripesize); | |
3887 | tmpdiv = r5or6_last_row_offset; | |
3888 | r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row); | |
3889 | tmpdiv = r5or6_first_row_offset; | |
3890 | (void) do_div(tmpdiv, map->strip_size); | |
3891 | first_column = r5or6_first_column = tmpdiv; | |
3892 | tmpdiv = r5or6_last_row_offset; | |
3893 | (void) do_div(tmpdiv, map->strip_size); | |
3894 | r5or6_last_column = tmpdiv; | |
3895 | #else | |
3896 | first_row_offset = r5or6_first_row_offset = | |
3897 | (u32)((first_block % stripesize) % | |
3898 | r5or6_blocks_per_row); | |
3899 | ||
3900 | r5or6_last_row_offset = | |
3901 | (u32)((last_block % stripesize) % | |
3902 | r5or6_blocks_per_row); | |
3903 | ||
3904 | first_column = r5or6_first_column = | |
2b08b3e9 | 3905 | r5or6_first_row_offset / le16_to_cpu(map->strip_size); |
6b80b18f | 3906 | r5or6_last_column = |
2b08b3e9 | 3907 | r5or6_last_row_offset / le16_to_cpu(map->strip_size); |
6b80b18f ST |
3908 | #endif |
3909 | if (r5or6_first_column != r5or6_last_column) | |
3910 | return IO_ACCEL_INELIGIBLE; | |
3911 | ||
3912 | /* Request is eligible */ | |
3913 | map_row = ((u32)(first_row >> map->parity_rotation_shift)) % | |
2b08b3e9 | 3914 | le16_to_cpu(map->row_cnt); |
6b80b18f ST |
3915 | |
3916 | map_index = (first_group * | |
2b08b3e9 | 3917 | (le16_to_cpu(map->row_cnt) * total_disks_per_row)) + |
6b80b18f ST |
3918 | (map_row * total_disks_per_row) + first_column; |
3919 | break; | |
3920 | default: | |
3921 | return IO_ACCEL_INELIGIBLE; | |
283b4a9b | 3922 | } |
6b80b18f | 3923 | |
07543e0c SC |
3924 | if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES)) |
3925 | return IO_ACCEL_INELIGIBLE; | |
3926 | ||
03383736 DB |
3927 | c->phys_disk = dev->phys_disk[map_index]; |
3928 | ||
283b4a9b | 3929 | disk_handle = dd[map_index].ioaccel_handle; |
2b08b3e9 DB |
3930 | disk_block = le64_to_cpu(map->disk_starting_blk) + |
3931 | first_row * le16_to_cpu(map->strip_size) + | |
3932 | (first_row_offset - first_column * | |
3933 | le16_to_cpu(map->strip_size)); | |
283b4a9b SC |
3934 | disk_block_cnt = block_cnt; |
3935 | ||
3936 | /* handle differing logical/physical block sizes */ | |
3937 | if (map->phys_blk_shift) { | |
3938 | disk_block <<= map->phys_blk_shift; | |
3939 | disk_block_cnt <<= map->phys_blk_shift; | |
3940 | } | |
3941 | BUG_ON(disk_block_cnt > 0xffff); | |
3942 | ||
3943 | /* build the new CDB for the physical disk I/O */ | |
3944 | if (disk_block > 0xffffffff) { | |
3945 | cdb[0] = is_write ? WRITE_16 : READ_16; | |
3946 | cdb[1] = 0; | |
3947 | cdb[2] = (u8) (disk_block >> 56); | |
3948 | cdb[3] = (u8) (disk_block >> 48); | |
3949 | cdb[4] = (u8) (disk_block >> 40); | |
3950 | cdb[5] = (u8) (disk_block >> 32); | |
3951 | cdb[6] = (u8) (disk_block >> 24); | |
3952 | cdb[7] = (u8) (disk_block >> 16); | |
3953 | cdb[8] = (u8) (disk_block >> 8); | |
3954 | cdb[9] = (u8) (disk_block); | |
3955 | cdb[10] = (u8) (disk_block_cnt >> 24); | |
3956 | cdb[11] = (u8) (disk_block_cnt >> 16); | |
3957 | cdb[12] = (u8) (disk_block_cnt >> 8); | |
3958 | cdb[13] = (u8) (disk_block_cnt); | |
3959 | cdb[14] = 0; | |
3960 | cdb[15] = 0; | |
3961 | cdb_len = 16; | |
3962 | } else { | |
3963 | cdb[0] = is_write ? WRITE_10 : READ_10; | |
3964 | cdb[1] = 0; | |
3965 | cdb[2] = (u8) (disk_block >> 24); | |
3966 | cdb[3] = (u8) (disk_block >> 16); | |
3967 | cdb[4] = (u8) (disk_block >> 8); | |
3968 | cdb[5] = (u8) (disk_block); | |
3969 | cdb[6] = 0; | |
3970 | cdb[7] = (u8) (disk_block_cnt >> 8); | |
3971 | cdb[8] = (u8) (disk_block_cnt); | |
3972 | cdb[9] = 0; | |
3973 | cdb_len = 10; | |
3974 | } | |
3975 | return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len, | |
03383736 DB |
3976 | dev->scsi3addr, |
3977 | dev->phys_disk[map_index]); | |
283b4a9b SC |
3978 | } |
3979 | ||
574f05d3 SC |
3980 | /* Submit commands down the "normal" RAID stack path */ |
3981 | static int hpsa_ciss_submit(struct ctlr_info *h, | |
3982 | struct CommandList *c, struct scsi_cmnd *cmd, | |
3983 | unsigned char scsi3addr[]) | |
edd16368 | 3984 | { |
edd16368 | 3985 | cmd->host_scribble = (unsigned char *) c; |
edd16368 SC |
3986 | c->cmd_type = CMD_SCSI; |
3987 | c->scsi_cmd = cmd; | |
3988 | c->Header.ReplyQueue = 0; /* unused in simple mode */ | |
3989 | memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8); | |
f2405db8 | 3990 | c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT)); |
edd16368 SC |
3991 | |
3992 | /* Fill in the request block... */ | |
3993 | ||
3994 | c->Request.Timeout = 0; | |
3995 | memset(c->Request.CDB, 0, sizeof(c->Request.CDB)); | |
3996 | BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB)); | |
3997 | c->Request.CDBLen = cmd->cmd_len; | |
3998 | memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len); | |
edd16368 SC |
3999 | switch (cmd->sc_data_direction) { |
4000 | case DMA_TO_DEVICE: | |
a505b86f SC |
4001 | c->Request.type_attr_dir = |
4002 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE); | |
edd16368 SC |
4003 | break; |
4004 | case DMA_FROM_DEVICE: | |
a505b86f SC |
4005 | c->Request.type_attr_dir = |
4006 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ); | |
edd16368 SC |
4007 | break; |
4008 | case DMA_NONE: | |
a505b86f SC |
4009 | c->Request.type_attr_dir = |
4010 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE); | |
edd16368 SC |
4011 | break; |
4012 | case DMA_BIDIRECTIONAL: | |
4013 | /* This can happen if a buggy application does a scsi passthru | |
4014 | * and sets both inlen and outlen to non-zero. ( see | |
4015 | * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() ) | |
4016 | */ | |
4017 | ||
a505b86f SC |
4018 | c->Request.type_attr_dir = |
4019 | TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD); | |
edd16368 SC |
4020 | /* This is technically wrong, and hpsa controllers should |
4021 | * reject it with CMD_INVALID, which is the most correct | |
4022 | * response, but non-fibre backends appear to let it | |
4023 | * slide by, and give the same results as if this field | |
4024 | * were set correctly. Either way is acceptable for | |
4025 | * our purposes here. | |
4026 | */ | |
4027 | ||
4028 | break; | |
4029 | ||
4030 | default: | |
4031 | dev_err(&h->pdev->dev, "unknown data direction: %d\n", | |
4032 | cmd->sc_data_direction); | |
4033 | BUG(); | |
4034 | break; | |
4035 | } | |
4036 | ||
33a2ffce | 4037 | if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */ |
edd16368 SC |
4038 | cmd_free(h, c); |
4039 | return SCSI_MLQUEUE_HOST_BUSY; | |
4040 | } | |
4041 | enqueue_cmd_and_start_io(h, c); | |
4042 | /* the cmd'll come back via intr handler in complete_scsi_command() */ | |
4043 | return 0; | |
4044 | } | |
4045 | ||
080ef1cc DB |
4046 | static void hpsa_command_resubmit_worker(struct work_struct *work) |
4047 | { | |
4048 | struct scsi_cmnd *cmd; | |
4049 | struct hpsa_scsi_dev_t *dev; | |
4050 | struct CommandList *c = | |
4051 | container_of(work, struct CommandList, work); | |
4052 | ||
4053 | cmd = c->scsi_cmd; | |
4054 | dev = cmd->device->hostdata; | |
4055 | if (!dev) { | |
4056 | cmd->result = DID_NO_CONNECT << 16; | |
4057 | cmd->scsi_done(cmd); | |
4058 | return; | |
4059 | } | |
4060 | if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) { | |
4061 | /* | |
4062 | * If we get here, it means dma mapping failed. Try | |
4063 | * again via scsi mid layer, which will then get | |
4064 | * SCSI_MLQUEUE_HOST_BUSY. | |
4065 | */ | |
4066 | cmd->result = DID_IMM_RETRY << 16; | |
4067 | cmd->scsi_done(cmd); | |
4068 | } | |
4069 | } | |
4070 | ||
574f05d3 SC |
4071 | /* Running in struct Scsi_Host->host_lock less mode */ |
4072 | static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd) | |
4073 | { | |
4074 | struct ctlr_info *h; | |
4075 | struct hpsa_scsi_dev_t *dev; | |
4076 | unsigned char scsi3addr[8]; | |
4077 | struct CommandList *c; | |
4078 | int rc = 0; | |
4079 | ||
4080 | /* Get the ptr to our adapter structure out of cmd->host. */ | |
4081 | h = sdev_to_hba(cmd->device); | |
4082 | dev = cmd->device->hostdata; | |
4083 | if (!dev) { | |
4084 | cmd->result = DID_NO_CONNECT << 16; | |
4085 | cmd->scsi_done(cmd); | |
4086 | return 0; | |
4087 | } | |
4088 | memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr)); | |
4089 | ||
4090 | if (unlikely(lockup_detected(h))) { | |
4091 | cmd->result = DID_ERROR << 16; | |
4092 | cmd->scsi_done(cmd); | |
4093 | return 0; | |
4094 | } | |
4095 | c = cmd_alloc(h); | |
4096 | if (c == NULL) { /* trouble... */ | |
4097 | dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n"); | |
4098 | return SCSI_MLQUEUE_HOST_BUSY; | |
4099 | } | |
407863cb SC |
4100 | if (unlikely(lockup_detected(h))) { |
4101 | cmd->result = DID_ERROR << 16; | |
4102 | cmd_free(h, c); | |
4103 | cmd->scsi_done(cmd); | |
4104 | return 0; | |
4105 | } | |
574f05d3 | 4106 | |
407863cb SC |
4107 | /* |
4108 | * Call alternate submit routine for I/O accelerated commands. | |
574f05d3 SC |
4109 | * Retries always go down the normal I/O path. |
4110 | */ | |
4111 | if (likely(cmd->retries == 0 && | |
4112 | cmd->request->cmd_type == REQ_TYPE_FS && | |
4113 | h->acciopath_status)) { | |
4114 | ||
4115 | cmd->host_scribble = (unsigned char *) c; | |
4116 | c->cmd_type = CMD_SCSI; | |
4117 | c->scsi_cmd = cmd; | |
4118 | ||
4119 | if (dev->offload_enabled) { | |
4120 | rc = hpsa_scsi_ioaccel_raid_map(h, c); | |
4121 | if (rc == 0) | |
4122 | return 0; /* Sent on ioaccel path */ | |
4123 | if (rc < 0) { /* scsi_dma_map failed. */ | |
4124 | cmd_free(h, c); | |
4125 | return SCSI_MLQUEUE_HOST_BUSY; | |
4126 | } | |
4127 | } else if (dev->ioaccel_handle) { | |
4128 | rc = hpsa_scsi_ioaccel_direct_map(h, c); | |
4129 | if (rc == 0) | |
4130 | return 0; /* Sent on direct map path */ | |
4131 | if (rc < 0) { /* scsi_dma_map failed. */ | |
4132 | cmd_free(h, c); | |
4133 | return SCSI_MLQUEUE_HOST_BUSY; | |
4134 | } | |
4135 | } | |
4136 | } | |
4137 | return hpsa_ciss_submit(h, c, cmd, scsi3addr); | |
4138 | } | |
4139 | ||
5f389360 SC |
4140 | static int do_not_scan_if_controller_locked_up(struct ctlr_info *h) |
4141 | { | |
4142 | unsigned long flags; | |
4143 | ||
4144 | /* | |
4145 | * Don't let rescans be initiated on a controller known | |
4146 | * to be locked up. If the controller locks up *during* | |
4147 | * a rescan, that thread is probably hosed, but at least | |
4148 | * we can prevent new rescan threads from piling up on a | |
4149 | * locked up controller. | |
4150 | */ | |
094963da | 4151 | if (unlikely(lockup_detected(h))) { |
5f389360 SC |
4152 | spin_lock_irqsave(&h->scan_lock, flags); |
4153 | h->scan_finished = 1; | |
4154 | wake_up_all(&h->scan_wait_queue); | |
4155 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
4156 | return 1; | |
4157 | } | |
5f389360 SC |
4158 | return 0; |
4159 | } | |
4160 | ||
a08a8471 SC |
4161 | static void hpsa_scan_start(struct Scsi_Host *sh) |
4162 | { | |
4163 | struct ctlr_info *h = shost_to_hba(sh); | |
4164 | unsigned long flags; | |
4165 | ||
5f389360 SC |
4166 | if (do_not_scan_if_controller_locked_up(h)) |
4167 | return; | |
4168 | ||
a08a8471 SC |
4169 | /* wait until any scan already in progress is finished. */ |
4170 | while (1) { | |
4171 | spin_lock_irqsave(&h->scan_lock, flags); | |
4172 | if (h->scan_finished) | |
4173 | break; | |
4174 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
4175 | wait_event(h->scan_wait_queue, h->scan_finished); | |
4176 | /* Note: We don't need to worry about a race between this | |
4177 | * thread and driver unload because the midlayer will | |
4178 | * have incremented the reference count, so unload won't | |
4179 | * happen if we're in here. | |
4180 | */ | |
4181 | } | |
4182 | h->scan_finished = 0; /* mark scan as in progress */ | |
4183 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
4184 | ||
5f389360 SC |
4185 | if (do_not_scan_if_controller_locked_up(h)) |
4186 | return; | |
4187 | ||
a08a8471 SC |
4188 | hpsa_update_scsi_devices(h, h->scsi_host->host_no); |
4189 | ||
4190 | spin_lock_irqsave(&h->scan_lock, flags); | |
4191 | h->scan_finished = 1; /* mark scan as finished. */ | |
4192 | wake_up_all(&h->scan_wait_queue); | |
4193 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
4194 | } | |
4195 | ||
7c0a0229 DB |
4196 | static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth) |
4197 | { | |
03383736 DB |
4198 | struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata; |
4199 | ||
4200 | if (!logical_drive) | |
4201 | return -ENODEV; | |
7c0a0229 DB |
4202 | |
4203 | if (qdepth < 1) | |
4204 | qdepth = 1; | |
03383736 DB |
4205 | else if (qdepth > logical_drive->queue_depth) |
4206 | qdepth = logical_drive->queue_depth; | |
4207 | ||
4208 | return scsi_change_queue_depth(sdev, qdepth); | |
7c0a0229 DB |
4209 | } |
4210 | ||
a08a8471 SC |
4211 | static int hpsa_scan_finished(struct Scsi_Host *sh, |
4212 | unsigned long elapsed_time) | |
4213 | { | |
4214 | struct ctlr_info *h = shost_to_hba(sh); | |
4215 | unsigned long flags; | |
4216 | int finished; | |
4217 | ||
4218 | spin_lock_irqsave(&h->scan_lock, flags); | |
4219 | finished = h->scan_finished; | |
4220 | spin_unlock_irqrestore(&h->scan_lock, flags); | |
4221 | return finished; | |
4222 | } | |
4223 | ||
edd16368 SC |
4224 | static void hpsa_unregister_scsi(struct ctlr_info *h) |
4225 | { | |
4226 | /* we are being forcibly unloaded, and may not refuse. */ | |
4227 | scsi_remove_host(h->scsi_host); | |
4228 | scsi_host_put(h->scsi_host); | |
4229 | h->scsi_host = NULL; | |
4230 | } | |
4231 | ||
4232 | static int hpsa_register_scsi(struct ctlr_info *h) | |
4233 | { | |
b705690d SC |
4234 | struct Scsi_Host *sh; |
4235 | int error; | |
edd16368 | 4236 | |
b705690d SC |
4237 | sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h)); |
4238 | if (sh == NULL) | |
4239 | goto fail; | |
4240 | ||
4241 | sh->io_port = 0; | |
4242 | sh->n_io_port = 0; | |
4243 | sh->this_id = -1; | |
4244 | sh->max_channel = 3; | |
4245 | sh->max_cmd_len = MAX_COMMAND_SIZE; | |
4246 | sh->max_lun = HPSA_MAX_LUN; | |
4247 | sh->max_id = HPSA_MAX_LUN; | |
d54c5c24 SC |
4248 | sh->can_queue = h->nr_cmds - |
4249 | HPSA_CMDS_RESERVED_FOR_ABORTS - | |
4250 | HPSA_CMDS_RESERVED_FOR_DRIVER - | |
4251 | HPSA_MAX_CONCURRENT_PASSTHRUS; | |
03383736 | 4252 | sh->cmd_per_lun = sh->can_queue; |
b705690d SC |
4253 | sh->sg_tablesize = h->maxsgentries; |
4254 | h->scsi_host = sh; | |
4255 | sh->hostdata[0] = (unsigned long) h; | |
4256 | sh->irq = h->intr[h->intr_mode]; | |
4257 | sh->unique_id = sh->irq; | |
4258 | error = scsi_add_host(sh, &h->pdev->dev); | |
4259 | if (error) | |
4260 | goto fail_host_put; | |
4261 | scsi_scan_host(sh); | |
4262 | return 0; | |
4263 | ||
4264 | fail_host_put: | |
4265 | dev_err(&h->pdev->dev, "%s: scsi_add_host" | |
4266 | " failed for controller %d\n", __func__, h->ctlr); | |
4267 | scsi_host_put(sh); | |
4268 | return error; | |
4269 | fail: | |
4270 | dev_err(&h->pdev->dev, "%s: scsi_host_alloc" | |
4271 | " failed for controller %d\n", __func__, h->ctlr); | |
4272 | return -ENOMEM; | |
edd16368 SC |
4273 | } |
4274 | ||
4275 | static int wait_for_device_to_become_ready(struct ctlr_info *h, | |
4276 | unsigned char lunaddr[]) | |
4277 | { | |
8919358e | 4278 | int rc; |
edd16368 SC |
4279 | int count = 0; |
4280 | int waittime = 1; /* seconds */ | |
4281 | struct CommandList *c; | |
4282 | ||
45fcb86e | 4283 | c = cmd_alloc(h); |
edd16368 SC |
4284 | if (!c) { |
4285 | dev_warn(&h->pdev->dev, "out of memory in " | |
4286 | "wait_for_device_to_become_ready.\n"); | |
4287 | return IO_ERROR; | |
4288 | } | |
4289 | ||
4290 | /* Send test unit ready until device ready, or give up. */ | |
4291 | while (count < HPSA_TUR_RETRY_LIMIT) { | |
4292 | ||
4293 | /* Wait for a bit. do this first, because if we send | |
4294 | * the TUR right away, the reset will just abort it. | |
4295 | */ | |
4296 | msleep(1000 * waittime); | |
4297 | count++; | |
8919358e | 4298 | rc = 0; /* Device ready. */ |
edd16368 SC |
4299 | |
4300 | /* Increase wait time with each try, up to a point. */ | |
4301 | if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS) | |
4302 | waittime = waittime * 2; | |
4303 | ||
a2dac136 SC |
4304 | /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */ |
4305 | (void) fill_cmd(c, TEST_UNIT_READY, h, | |
4306 | NULL, 0, 0, lunaddr, TYPE_CMD); | |
edd16368 SC |
4307 | hpsa_scsi_do_simple_cmd_core(h, c); |
4308 | /* no unmap needed here because no data xfer. */ | |
4309 | ||
4310 | if (c->err_info->CommandStatus == CMD_SUCCESS) | |
4311 | break; | |
4312 | ||
4313 | if (c->err_info->CommandStatus == CMD_TARGET_STATUS && | |
4314 | c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION && | |
4315 | (c->err_info->SenseInfo[2] == NO_SENSE || | |
4316 | c->err_info->SenseInfo[2] == UNIT_ATTENTION)) | |
4317 | break; | |
4318 | ||
4319 | dev_warn(&h->pdev->dev, "waiting %d secs " | |
4320 | "for device to become ready.\n", waittime); | |
4321 | rc = 1; /* device not ready. */ | |
4322 | } | |
4323 | ||
4324 | if (rc) | |
4325 | dev_warn(&h->pdev->dev, "giving up on device.\n"); | |
4326 | else | |
4327 | dev_warn(&h->pdev->dev, "device is ready.\n"); | |
4328 | ||
45fcb86e | 4329 | cmd_free(h, c); |
edd16368 SC |
4330 | return rc; |
4331 | } | |
4332 | ||
4333 | /* Need at least one of these error handlers to keep ../scsi/hosts.c from | |
4334 | * complaining. Doing a host- or bus-reset can't do anything good here. | |
4335 | */ | |
4336 | static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd) | |
4337 | { | |
4338 | int rc; | |
4339 | struct ctlr_info *h; | |
4340 | struct hpsa_scsi_dev_t *dev; | |
4341 | ||
4342 | /* find the controller to which the command to be aborted was sent */ | |
4343 | h = sdev_to_hba(scsicmd->device); | |
4344 | if (h == NULL) /* paranoia */ | |
4345 | return FAILED; | |
e345893b DB |
4346 | |
4347 | if (lockup_detected(h)) | |
4348 | return FAILED; | |
4349 | ||
edd16368 SC |
4350 | dev = scsicmd->device->hostdata; |
4351 | if (!dev) { | |
4352 | dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: " | |
4353 | "device lookup failed.\n"); | |
4354 | return FAILED; | |
4355 | } | |
d416b0c7 SC |
4356 | dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n", |
4357 | h->scsi_host->host_no, dev->bus, dev->target, dev->lun); | |
edd16368 | 4358 | /* send a reset to the SCSI LUN which the command was sent to */ |
bf711ac6 | 4359 | rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN); |
edd16368 SC |
4360 | if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0) |
4361 | return SUCCESS; | |
4362 | ||
4363 | dev_warn(&h->pdev->dev, "resetting device failed.\n"); | |
4364 | return FAILED; | |
4365 | } | |
4366 | ||
6cba3f19 SC |
4367 | static void swizzle_abort_tag(u8 *tag) |
4368 | { | |
4369 | u8 original_tag[8]; | |
4370 | ||
4371 | memcpy(original_tag, tag, 8); | |
4372 | tag[0] = original_tag[3]; | |
4373 | tag[1] = original_tag[2]; | |
4374 | tag[2] = original_tag[1]; | |
4375 | tag[3] = original_tag[0]; | |
4376 | tag[4] = original_tag[7]; | |
4377 | tag[5] = original_tag[6]; | |
4378 | tag[6] = original_tag[5]; | |
4379 | tag[7] = original_tag[4]; | |
4380 | } | |
4381 | ||
17eb87d2 | 4382 | static void hpsa_get_tag(struct ctlr_info *h, |
2b08b3e9 | 4383 | struct CommandList *c, __le32 *taglower, __le32 *tagupper) |
17eb87d2 | 4384 | { |
2b08b3e9 | 4385 | u64 tag; |
17eb87d2 ST |
4386 | if (c->cmd_type == CMD_IOACCEL1) { |
4387 | struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *) | |
4388 | &h->ioaccel_cmd_pool[c->cmdindex]; | |
2b08b3e9 DB |
4389 | tag = le64_to_cpu(cm1->tag); |
4390 | *tagupper = cpu_to_le32(tag >> 32); | |
4391 | *taglower = cpu_to_le32(tag); | |
54b6e9e9 ST |
4392 | return; |
4393 | } | |
4394 | if (c->cmd_type == CMD_IOACCEL2) { | |
4395 | struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *) | |
4396 | &h->ioaccel2_cmd_pool[c->cmdindex]; | |
dd0e19f3 ST |
4397 | /* upper tag not used in ioaccel2 mode */ |
4398 | memset(tagupper, 0, sizeof(*tagupper)); | |
4399 | *taglower = cm2->Tag; | |
54b6e9e9 | 4400 | return; |
17eb87d2 | 4401 | } |
2b08b3e9 DB |
4402 | tag = le64_to_cpu(c->Header.tag); |
4403 | *tagupper = cpu_to_le32(tag >> 32); | |
4404 | *taglower = cpu_to_le32(tag); | |
17eb87d2 ST |
4405 | } |
4406 | ||
75167d2c | 4407 | static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr, |
6cba3f19 | 4408 | struct CommandList *abort, int swizzle) |
75167d2c SC |
4409 | { |
4410 | int rc = IO_OK; | |
4411 | struct CommandList *c; | |
4412 | struct ErrorInfo *ei; | |
2b08b3e9 | 4413 | __le32 tagupper, taglower; |
75167d2c | 4414 | |
45fcb86e | 4415 | c = cmd_alloc(h); |
75167d2c | 4416 | if (c == NULL) { /* trouble... */ |
45fcb86e | 4417 | dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n"); |
75167d2c SC |
4418 | return -ENOMEM; |
4419 | } | |
4420 | ||
a2dac136 SC |
4421 | /* fill_cmd can't fail here, no buffer to map */ |
4422 | (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort, | |
4423 | 0, 0, scsi3addr, TYPE_MSG); | |
6cba3f19 SC |
4424 | if (swizzle) |
4425 | swizzle_abort_tag(&c->Request.CDB[4]); | |
75167d2c | 4426 | hpsa_scsi_do_simple_cmd_core(h, c); |
17eb87d2 | 4427 | hpsa_get_tag(h, abort, &taglower, &tagupper); |
75167d2c | 4428 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n", |
17eb87d2 | 4429 | __func__, tagupper, taglower); |
75167d2c SC |
4430 | /* no unmap needed here because no data xfer. */ |
4431 | ||
4432 | ei = c->err_info; | |
4433 | switch (ei->CommandStatus) { | |
4434 | case CMD_SUCCESS: | |
4435 | break; | |
4436 | case CMD_UNABORTABLE: /* Very common, don't make noise. */ | |
4437 | rc = -1; | |
4438 | break; | |
4439 | default: | |
4440 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n", | |
17eb87d2 | 4441 | __func__, tagupper, taglower); |
d1e8beac | 4442 | hpsa_scsi_interpret_error(h, c); |
75167d2c SC |
4443 | rc = -1; |
4444 | break; | |
4445 | } | |
45fcb86e | 4446 | cmd_free(h, c); |
dd0e19f3 ST |
4447 | dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", |
4448 | __func__, tagupper, taglower); | |
75167d2c SC |
4449 | return rc; |
4450 | } | |
4451 | ||
54b6e9e9 ST |
4452 | /* ioaccel2 path firmware cannot handle abort task requests. |
4453 | * Change abort requests to physical target reset, and send to the | |
4454 | * address of the physical disk used for the ioaccel 2 command. | |
4455 | * Return 0 on success (IO_OK) | |
4456 | * -1 on failure | |
4457 | */ | |
4458 | ||
4459 | static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h, | |
4460 | unsigned char *scsi3addr, struct CommandList *abort) | |
4461 | { | |
4462 | int rc = IO_OK; | |
4463 | struct scsi_cmnd *scmd; /* scsi command within request being aborted */ | |
4464 | struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */ | |
4465 | unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */ | |
4466 | unsigned char *psa = &phys_scsi3addr[0]; | |
4467 | ||
4468 | /* Get a pointer to the hpsa logical device. */ | |
7fa3030c | 4469 | scmd = abort->scsi_cmd; |
54b6e9e9 ST |
4470 | dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata); |
4471 | if (dev == NULL) { | |
4472 | dev_warn(&h->pdev->dev, | |
4473 | "Cannot abort: no device pointer for command.\n"); | |
4474 | return -1; /* not abortable */ | |
4475 | } | |
4476 | ||
2ba8bfc8 SC |
4477 | if (h->raid_offload_debug > 0) |
4478 | dev_info(&h->pdev->dev, | |
4479 | "Reset as abort: Abort requested on C%d:B%d:T%d:L%d scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
4480 | h->scsi_host->host_no, dev->bus, dev->target, dev->lun, | |
4481 | scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3], | |
4482 | scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]); | |
4483 | ||
54b6e9e9 ST |
4484 | if (!dev->offload_enabled) { |
4485 | dev_warn(&h->pdev->dev, | |
4486 | "Can't abort: device is not operating in HP SSD Smart Path mode.\n"); | |
4487 | return -1; /* not abortable */ | |
4488 | } | |
4489 | ||
4490 | /* Incoming scsi3addr is logical addr. We need physical disk addr. */ | |
4491 | if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) { | |
4492 | dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n"); | |
4493 | return -1; /* not abortable */ | |
4494 | } | |
4495 | ||
4496 | /* send the reset */ | |
2ba8bfc8 SC |
4497 | if (h->raid_offload_debug > 0) |
4498 | dev_info(&h->pdev->dev, | |
4499 | "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
4500 | psa[0], psa[1], psa[2], psa[3], | |
4501 | psa[4], psa[5], psa[6], psa[7]); | |
54b6e9e9 ST |
4502 | rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET); |
4503 | if (rc != 0) { | |
4504 | dev_warn(&h->pdev->dev, | |
4505 | "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
4506 | psa[0], psa[1], psa[2], psa[3], | |
4507 | psa[4], psa[5], psa[6], psa[7]); | |
4508 | return rc; /* failed to reset */ | |
4509 | } | |
4510 | ||
4511 | /* wait for device to recover */ | |
4512 | if (wait_for_device_to_become_ready(h, psa) != 0) { | |
4513 | dev_warn(&h->pdev->dev, | |
4514 | "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
4515 | psa[0], psa[1], psa[2], psa[3], | |
4516 | psa[4], psa[5], psa[6], psa[7]); | |
4517 | return -1; /* failed to recover */ | |
4518 | } | |
4519 | ||
4520 | /* device recovered */ | |
4521 | dev_info(&h->pdev->dev, | |
4522 | "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n", | |
4523 | psa[0], psa[1], psa[2], psa[3], | |
4524 | psa[4], psa[5], psa[6], psa[7]); | |
4525 | ||
4526 | return rc; /* success */ | |
4527 | } | |
4528 | ||
6cba3f19 SC |
4529 | /* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to |
4530 | * tell which kind we're dealing with, so we send the abort both ways. There | |
4531 | * shouldn't be any collisions between swizzled and unswizzled tags due to the | |
4532 | * way we construct our tags but we check anyway in case the assumptions which | |
4533 | * make this true someday become false. | |
4534 | */ | |
4535 | static int hpsa_send_abort_both_ways(struct ctlr_info *h, | |
4536 | unsigned char *scsi3addr, struct CommandList *abort) | |
4537 | { | |
54b6e9e9 ST |
4538 | /* ioccelerator mode 2 commands should be aborted via the |
4539 | * accelerated path, since RAID path is unaware of these commands, | |
4540 | * but underlying firmware can't handle abort TMF. | |
4541 | * Change abort to physical device reset. | |
4542 | */ | |
4543 | if (abort->cmd_type == CMD_IOACCEL2) | |
4544 | return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort); | |
4545 | ||
f2405db8 DB |
4546 | return hpsa_send_abort(h, scsi3addr, abort, 0) && |
4547 | hpsa_send_abort(h, scsi3addr, abort, 1); | |
6cba3f19 SC |
4548 | } |
4549 | ||
75167d2c SC |
4550 | /* Send an abort for the specified command. |
4551 | * If the device and controller support it, | |
4552 | * send a task abort request. | |
4553 | */ | |
4554 | static int hpsa_eh_abort_handler(struct scsi_cmnd *sc) | |
4555 | { | |
4556 | ||
4557 | int i, rc; | |
4558 | struct ctlr_info *h; | |
4559 | struct hpsa_scsi_dev_t *dev; | |
4560 | struct CommandList *abort; /* pointer to command to be aborted */ | |
75167d2c SC |
4561 | struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */ |
4562 | char msg[256]; /* For debug messaging. */ | |
4563 | int ml = 0; | |
2b08b3e9 | 4564 | __le32 tagupper, taglower; |
281a7fd0 | 4565 | int refcount; |
75167d2c SC |
4566 | |
4567 | /* Find the controller of the command to be aborted */ | |
4568 | h = sdev_to_hba(sc->device); | |
4569 | if (WARN(h == NULL, | |
4570 | "ABORT REQUEST FAILED, Controller lookup failed.\n")) | |
4571 | return FAILED; | |
4572 | ||
e345893b DB |
4573 | if (lockup_detected(h)) |
4574 | return FAILED; | |
4575 | ||
75167d2c SC |
4576 | /* Check that controller supports some kind of task abort */ |
4577 | if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) && | |
4578 | !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags)) | |
4579 | return FAILED; | |
4580 | ||
4581 | memset(msg, 0, sizeof(msg)); | |
9cb78c16 | 4582 | ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%llu ", |
75167d2c SC |
4583 | h->scsi_host->host_no, sc->device->channel, |
4584 | sc->device->id, sc->device->lun); | |
4585 | ||
4586 | /* Find the device of the command to be aborted */ | |
4587 | dev = sc->device->hostdata; | |
4588 | if (!dev) { | |
4589 | dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n", | |
4590 | msg); | |
4591 | return FAILED; | |
4592 | } | |
4593 | ||
4594 | /* Get SCSI command to be aborted */ | |
4595 | abort = (struct CommandList *) sc->host_scribble; | |
4596 | if (abort == NULL) { | |
281a7fd0 WS |
4597 | /* This can happen if the command already completed. */ |
4598 | return SUCCESS; | |
4599 | } | |
4600 | refcount = atomic_inc_return(&abort->refcount); | |
4601 | if (refcount == 1) { /* Command is done already. */ | |
4602 | cmd_free(h, abort); | |
4603 | return SUCCESS; | |
75167d2c | 4604 | } |
17eb87d2 ST |
4605 | hpsa_get_tag(h, abort, &taglower, &tagupper); |
4606 | ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower); | |
7fa3030c | 4607 | as = abort->scsi_cmd; |
75167d2c SC |
4608 | if (as != NULL) |
4609 | ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ", | |
4610 | as->cmnd[0], as->serial_number); | |
4611 | dev_dbg(&h->pdev->dev, "%s\n", msg); | |
4612 | dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n", | |
4613 | h->scsi_host->host_no, dev->bus, dev->target, dev->lun); | |
75167d2c SC |
4614 | /* |
4615 | * Command is in flight, or possibly already completed | |
4616 | * by the firmware (but not to the scsi mid layer) but we can't | |
4617 | * distinguish which. Send the abort down. | |
4618 | */ | |
6cba3f19 | 4619 | rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort); |
75167d2c SC |
4620 | if (rc != 0) { |
4621 | dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg); | |
4622 | dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n", | |
4623 | h->scsi_host->host_no, | |
4624 | dev->bus, dev->target, dev->lun); | |
281a7fd0 | 4625 | cmd_free(h, abort); |
75167d2c SC |
4626 | return FAILED; |
4627 | } | |
4628 | dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg); | |
4629 | ||
4630 | /* If the abort(s) above completed and actually aborted the | |
4631 | * command, then the command to be aborted should already be | |
4632 | * completed. If not, wait around a bit more to see if they | |
4633 | * manage to complete normally. | |
4634 | */ | |
4635 | #define ABORT_COMPLETE_WAIT_SECS 30 | |
4636 | for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) { | |
281a7fd0 WS |
4637 | refcount = atomic_read(&abort->refcount); |
4638 | if (refcount < 2) { | |
4639 | cmd_free(h, abort); | |
75167d2c | 4640 | return SUCCESS; |
281a7fd0 WS |
4641 | } else { |
4642 | msleep(100); | |
4643 | } | |
75167d2c SC |
4644 | } |
4645 | dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n", | |
4646 | msg, ABORT_COMPLETE_WAIT_SECS); | |
281a7fd0 | 4647 | cmd_free(h, abort); |
75167d2c SC |
4648 | return FAILED; |
4649 | } | |
4650 | ||
edd16368 SC |
4651 | /* |
4652 | * For operations that cannot sleep, a command block is allocated at init, | |
4653 | * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track | |
4654 | * which ones are free or in use. Lock must be held when calling this. | |
4655 | * cmd_free() is the complement. | |
4656 | */ | |
281a7fd0 | 4657 | |
edd16368 SC |
4658 | static struct CommandList *cmd_alloc(struct ctlr_info *h) |
4659 | { | |
4660 | struct CommandList *c; | |
4661 | int i; | |
4662 | union u64bit temp64; | |
4663 | dma_addr_t cmd_dma_handle, err_dma_handle; | |
281a7fd0 | 4664 | int refcount; |
33811026 | 4665 | unsigned long offset; |
4c413128 | 4666 | |
33811026 RE |
4667 | /* |
4668 | * There is some *extremely* small but non-zero chance that that | |
4c413128 SC |
4669 | * multiple threads could get in here, and one thread could |
4670 | * be scanning through the list of bits looking for a free | |
4671 | * one, but the free ones are always behind him, and other | |
4672 | * threads sneak in behind him and eat them before he can | |
4673 | * get to them, so that while there is always a free one, a | |
4674 | * very unlucky thread might be starved anyway, never able to | |
4675 | * beat the other threads. In reality, this happens so | |
4676 | * infrequently as to be indistinguishable from never. | |
4677 | */ | |
edd16368 | 4678 | |
33811026 | 4679 | offset = h->last_allocation; /* benignly racy */ |
281a7fd0 WS |
4680 | for (;;) { |
4681 | i = find_next_zero_bit(h->cmd_pool_bits, h->nr_cmds, offset); | |
4682 | if (unlikely(i == h->nr_cmds)) { | |
4683 | offset = 0; | |
4684 | continue; | |
4685 | } | |
4686 | c = h->cmd_pool + i; | |
4687 | refcount = atomic_inc_return(&c->refcount); | |
4688 | if (unlikely(refcount > 1)) { | |
4689 | cmd_free(h, c); /* already in use */ | |
4690 | offset = (i + 1) % h->nr_cmds; | |
4691 | continue; | |
4692 | } | |
4693 | set_bit(i & (BITS_PER_LONG - 1), | |
4694 | h->cmd_pool_bits + (i / BITS_PER_LONG)); | |
4695 | break; /* it's ours now. */ | |
4696 | } | |
33811026 | 4697 | h->last_allocation = i; /* benignly racy */ |
281a7fd0 WS |
4698 | |
4699 | /* Zero out all of commandlist except the last field, refcount */ | |
4700 | memset(c, 0, offsetof(struct CommandList, refcount)); | |
4701 | c->Header.tag = cpu_to_le64((u64) (i << DIRECT_LOOKUP_SHIFT)); | |
f2405db8 | 4702 | cmd_dma_handle = h->cmd_pool_dhandle + i * sizeof(*c); |
edd16368 SC |
4703 | c->err_info = h->errinfo_pool + i; |
4704 | memset(c->err_info, 0, sizeof(*c->err_info)); | |
4705 | err_dma_handle = h->errinfo_pool_dhandle | |
4706 | + i * sizeof(*c->err_info); | |
edd16368 SC |
4707 | |
4708 | c->cmdindex = i; | |
4709 | ||
01a02ffc SC |
4710 | c->busaddr = (u32) cmd_dma_handle; |
4711 | temp64.val = (u64) err_dma_handle; | |
281a7fd0 WS |
4712 | c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle); |
4713 | c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info)); | |
edd16368 SC |
4714 | |
4715 | c->h = h; | |
4716 | return c; | |
4717 | } | |
4718 | ||
edd16368 SC |
4719 | static void cmd_free(struct ctlr_info *h, struct CommandList *c) |
4720 | { | |
281a7fd0 WS |
4721 | if (atomic_dec_and_test(&c->refcount)) { |
4722 | int i; | |
edd16368 | 4723 | |
281a7fd0 WS |
4724 | i = c - h->cmd_pool; |
4725 | clear_bit(i & (BITS_PER_LONG - 1), | |
4726 | h->cmd_pool_bits + (i / BITS_PER_LONG)); | |
4727 | } | |
edd16368 SC |
4728 | } |
4729 | ||
edd16368 SC |
4730 | #ifdef CONFIG_COMPAT |
4731 | ||
42a91641 DB |
4732 | static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, |
4733 | void __user *arg) | |
edd16368 SC |
4734 | { |
4735 | IOCTL32_Command_struct __user *arg32 = | |
4736 | (IOCTL32_Command_struct __user *) arg; | |
4737 | IOCTL_Command_struct arg64; | |
4738 | IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64)); | |
4739 | int err; | |
4740 | u32 cp; | |
4741 | ||
938abd84 | 4742 | memset(&arg64, 0, sizeof(arg64)); |
edd16368 SC |
4743 | err = 0; |
4744 | err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, | |
4745 | sizeof(arg64.LUN_info)); | |
4746 | err |= copy_from_user(&arg64.Request, &arg32->Request, | |
4747 | sizeof(arg64.Request)); | |
4748 | err |= copy_from_user(&arg64.error_info, &arg32->error_info, | |
4749 | sizeof(arg64.error_info)); | |
4750 | err |= get_user(arg64.buf_size, &arg32->buf_size); | |
4751 | err |= get_user(cp, &arg32->buf); | |
4752 | arg64.buf = compat_ptr(cp); | |
4753 | err |= copy_to_user(p, &arg64, sizeof(arg64)); | |
4754 | ||
4755 | if (err) | |
4756 | return -EFAULT; | |
4757 | ||
42a91641 | 4758 | err = hpsa_ioctl(dev, CCISS_PASSTHRU, p); |
edd16368 SC |
4759 | if (err) |
4760 | return err; | |
4761 | err |= copy_in_user(&arg32->error_info, &p->error_info, | |
4762 | sizeof(arg32->error_info)); | |
4763 | if (err) | |
4764 | return -EFAULT; | |
4765 | return err; | |
4766 | } | |
4767 | ||
4768 | static int hpsa_ioctl32_big_passthru(struct scsi_device *dev, | |
42a91641 | 4769 | int cmd, void __user *arg) |
edd16368 SC |
4770 | { |
4771 | BIG_IOCTL32_Command_struct __user *arg32 = | |
4772 | (BIG_IOCTL32_Command_struct __user *) arg; | |
4773 | BIG_IOCTL_Command_struct arg64; | |
4774 | BIG_IOCTL_Command_struct __user *p = | |
4775 | compat_alloc_user_space(sizeof(arg64)); | |
4776 | int err; | |
4777 | u32 cp; | |
4778 | ||
938abd84 | 4779 | memset(&arg64, 0, sizeof(arg64)); |
edd16368 SC |
4780 | err = 0; |
4781 | err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info, | |
4782 | sizeof(arg64.LUN_info)); | |
4783 | err |= copy_from_user(&arg64.Request, &arg32->Request, | |
4784 | sizeof(arg64.Request)); | |
4785 | err |= copy_from_user(&arg64.error_info, &arg32->error_info, | |
4786 | sizeof(arg64.error_info)); | |
4787 | err |= get_user(arg64.buf_size, &arg32->buf_size); | |
4788 | err |= get_user(arg64.malloc_size, &arg32->malloc_size); | |
4789 | err |= get_user(cp, &arg32->buf); | |
4790 | arg64.buf = compat_ptr(cp); | |
4791 | err |= copy_to_user(p, &arg64, sizeof(arg64)); | |
4792 | ||
4793 | if (err) | |
4794 | return -EFAULT; | |
4795 | ||
42a91641 | 4796 | err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p); |
edd16368 SC |
4797 | if (err) |
4798 | return err; | |
4799 | err |= copy_in_user(&arg32->error_info, &p->error_info, | |
4800 | sizeof(arg32->error_info)); | |
4801 | if (err) | |
4802 | return -EFAULT; | |
4803 | return err; | |
4804 | } | |
71fe75a7 | 4805 | |
42a91641 | 4806 | static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg) |
71fe75a7 SC |
4807 | { |
4808 | switch (cmd) { | |
4809 | case CCISS_GETPCIINFO: | |
4810 | case CCISS_GETINTINFO: | |
4811 | case CCISS_SETINTINFO: | |
4812 | case CCISS_GETNODENAME: | |
4813 | case CCISS_SETNODENAME: | |
4814 | case CCISS_GETHEARTBEAT: | |
4815 | case CCISS_GETBUSTYPES: | |
4816 | case CCISS_GETFIRMVER: | |
4817 | case CCISS_GETDRIVVER: | |
4818 | case CCISS_REVALIDVOLS: | |
4819 | case CCISS_DEREGDISK: | |
4820 | case CCISS_REGNEWDISK: | |
4821 | case CCISS_REGNEWD: | |
4822 | case CCISS_RESCANDISK: | |
4823 | case CCISS_GETLUNINFO: | |
4824 | return hpsa_ioctl(dev, cmd, arg); | |
4825 | ||
4826 | case CCISS_PASSTHRU32: | |
4827 | return hpsa_ioctl32_passthru(dev, cmd, arg); | |
4828 | case CCISS_BIG_PASSTHRU32: | |
4829 | return hpsa_ioctl32_big_passthru(dev, cmd, arg); | |
4830 | ||
4831 | default: | |
4832 | return -ENOIOCTLCMD; | |
4833 | } | |
4834 | } | |
edd16368 SC |
4835 | #endif |
4836 | ||
4837 | static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp) | |
4838 | { | |
4839 | struct hpsa_pci_info pciinfo; | |
4840 | ||
4841 | if (!argp) | |
4842 | return -EINVAL; | |
4843 | pciinfo.domain = pci_domain_nr(h->pdev->bus); | |
4844 | pciinfo.bus = h->pdev->bus->number; | |
4845 | pciinfo.dev_fn = h->pdev->devfn; | |
4846 | pciinfo.board_id = h->board_id; | |
4847 | if (copy_to_user(argp, &pciinfo, sizeof(pciinfo))) | |
4848 | return -EFAULT; | |
4849 | return 0; | |
4850 | } | |
4851 | ||
4852 | static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp) | |
4853 | { | |
4854 | DriverVer_type DriverVer; | |
4855 | unsigned char vmaj, vmin, vsubmin; | |
4856 | int rc; | |
4857 | ||
4858 | rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu", | |
4859 | &vmaj, &vmin, &vsubmin); | |
4860 | if (rc != 3) { | |
4861 | dev_info(&h->pdev->dev, "driver version string '%s' " | |
4862 | "unrecognized.", HPSA_DRIVER_VERSION); | |
4863 | vmaj = 0; | |
4864 | vmin = 0; | |
4865 | vsubmin = 0; | |
4866 | } | |
4867 | DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin; | |
4868 | if (!argp) | |
4869 | return -EINVAL; | |
4870 | if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type))) | |
4871 | return -EFAULT; | |
4872 | return 0; | |
4873 | } | |
4874 | ||
4875 | static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp) | |
4876 | { | |
4877 | IOCTL_Command_struct iocommand; | |
4878 | struct CommandList *c; | |
4879 | char *buff = NULL; | |
50a0decf | 4880 | u64 temp64; |
c1f63c8f | 4881 | int rc = 0; |
edd16368 SC |
4882 | |
4883 | if (!argp) | |
4884 | return -EINVAL; | |
4885 | if (!capable(CAP_SYS_RAWIO)) | |
4886 | return -EPERM; | |
4887 | if (copy_from_user(&iocommand, argp, sizeof(iocommand))) | |
4888 | return -EFAULT; | |
4889 | if ((iocommand.buf_size < 1) && | |
4890 | (iocommand.Request.Type.Direction != XFER_NONE)) { | |
4891 | return -EINVAL; | |
4892 | } | |
4893 | if (iocommand.buf_size > 0) { | |
4894 | buff = kmalloc(iocommand.buf_size, GFP_KERNEL); | |
4895 | if (buff == NULL) | |
4896 | return -EFAULT; | |
9233fb10 | 4897 | if (iocommand.Request.Type.Direction & XFER_WRITE) { |
b03a7771 SC |
4898 | /* Copy the data into the buffer we created */ |
4899 | if (copy_from_user(buff, iocommand.buf, | |
4900 | iocommand.buf_size)) { | |
c1f63c8f SC |
4901 | rc = -EFAULT; |
4902 | goto out_kfree; | |
b03a7771 SC |
4903 | } |
4904 | } else { | |
4905 | memset(buff, 0, iocommand.buf_size); | |
edd16368 | 4906 | } |
b03a7771 | 4907 | } |
45fcb86e | 4908 | c = cmd_alloc(h); |
edd16368 | 4909 | if (c == NULL) { |
c1f63c8f SC |
4910 | rc = -ENOMEM; |
4911 | goto out_kfree; | |
edd16368 SC |
4912 | } |
4913 | /* Fill in the command type */ | |
4914 | c->cmd_type = CMD_IOCTL_PEND; | |
4915 | /* Fill in Command Header */ | |
4916 | c->Header.ReplyQueue = 0; /* unused in simple mode */ | |
4917 | if (iocommand.buf_size > 0) { /* buffer to fill */ | |
4918 | c->Header.SGList = 1; | |
50a0decf | 4919 | c->Header.SGTotal = cpu_to_le16(1); |
edd16368 SC |
4920 | } else { /* no buffers to fill */ |
4921 | c->Header.SGList = 0; | |
50a0decf | 4922 | c->Header.SGTotal = cpu_to_le16(0); |
edd16368 SC |
4923 | } |
4924 | memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN)); | |
edd16368 SC |
4925 | |
4926 | /* Fill in Request block */ | |
4927 | memcpy(&c->Request, &iocommand.Request, | |
4928 | sizeof(c->Request)); | |
4929 | ||
4930 | /* Fill in the scatter gather information */ | |
4931 | if (iocommand.buf_size > 0) { | |
50a0decf | 4932 | temp64 = pci_map_single(h->pdev, buff, |
edd16368 | 4933 | iocommand.buf_size, PCI_DMA_BIDIRECTIONAL); |
50a0decf SC |
4934 | if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) { |
4935 | c->SG[0].Addr = cpu_to_le64(0); | |
4936 | c->SG[0].Len = cpu_to_le32(0); | |
bcc48ffa SC |
4937 | rc = -ENOMEM; |
4938 | goto out; | |
4939 | } | |
50a0decf SC |
4940 | c->SG[0].Addr = cpu_to_le64(temp64); |
4941 | c->SG[0].Len = cpu_to_le32(iocommand.buf_size); | |
4942 | c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */ | |
edd16368 | 4943 | } |
a0c12413 | 4944 | hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c); |
c2dd32e0 SC |
4945 | if (iocommand.buf_size > 0) |
4946 | hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL); | |
edd16368 SC |
4947 | check_ioctl_unit_attention(h, c); |
4948 | ||
4949 | /* Copy the error information out */ | |
4950 | memcpy(&iocommand.error_info, c->err_info, | |
4951 | sizeof(iocommand.error_info)); | |
4952 | if (copy_to_user(argp, &iocommand, sizeof(iocommand))) { | |
c1f63c8f SC |
4953 | rc = -EFAULT; |
4954 | goto out; | |
edd16368 | 4955 | } |
9233fb10 | 4956 | if ((iocommand.Request.Type.Direction & XFER_READ) && |
b03a7771 | 4957 | iocommand.buf_size > 0) { |
edd16368 SC |
4958 | /* Copy the data out of the buffer we created */ |
4959 | if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) { | |
c1f63c8f SC |
4960 | rc = -EFAULT; |
4961 | goto out; | |
edd16368 SC |
4962 | } |
4963 | } | |
c1f63c8f | 4964 | out: |
45fcb86e | 4965 | cmd_free(h, c); |
c1f63c8f SC |
4966 | out_kfree: |
4967 | kfree(buff); | |
4968 | return rc; | |
edd16368 SC |
4969 | } |
4970 | ||
4971 | static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp) | |
4972 | { | |
4973 | BIG_IOCTL_Command_struct *ioc; | |
4974 | struct CommandList *c; | |
4975 | unsigned char **buff = NULL; | |
4976 | int *buff_size = NULL; | |
50a0decf | 4977 | u64 temp64; |
edd16368 SC |
4978 | BYTE sg_used = 0; |
4979 | int status = 0; | |
01a02ffc SC |
4980 | u32 left; |
4981 | u32 sz; | |
edd16368 SC |
4982 | BYTE __user *data_ptr; |
4983 | ||
4984 | if (!argp) | |
4985 | return -EINVAL; | |
4986 | if (!capable(CAP_SYS_RAWIO)) | |
4987 | return -EPERM; | |
4988 | ioc = (BIG_IOCTL_Command_struct *) | |
4989 | kmalloc(sizeof(*ioc), GFP_KERNEL); | |
4990 | if (!ioc) { | |
4991 | status = -ENOMEM; | |
4992 | goto cleanup1; | |
4993 | } | |
4994 | if (copy_from_user(ioc, argp, sizeof(*ioc))) { | |
4995 | status = -EFAULT; | |
4996 | goto cleanup1; | |
4997 | } | |
4998 | if ((ioc->buf_size < 1) && | |
4999 | (ioc->Request.Type.Direction != XFER_NONE)) { | |
5000 | status = -EINVAL; | |
5001 | goto cleanup1; | |
5002 | } | |
5003 | /* Check kmalloc limits using all SGs */ | |
5004 | if (ioc->malloc_size > MAX_KMALLOC_SIZE) { | |
5005 | status = -EINVAL; | |
5006 | goto cleanup1; | |
5007 | } | |
d66ae08b | 5008 | if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) { |
edd16368 SC |
5009 | status = -EINVAL; |
5010 | goto cleanup1; | |
5011 | } | |
d66ae08b | 5012 | buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL); |
edd16368 SC |
5013 | if (!buff) { |
5014 | status = -ENOMEM; | |
5015 | goto cleanup1; | |
5016 | } | |
d66ae08b | 5017 | buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL); |
edd16368 SC |
5018 | if (!buff_size) { |
5019 | status = -ENOMEM; | |
5020 | goto cleanup1; | |
5021 | } | |
5022 | left = ioc->buf_size; | |
5023 | data_ptr = ioc->buf; | |
5024 | while (left) { | |
5025 | sz = (left > ioc->malloc_size) ? ioc->malloc_size : left; | |
5026 | buff_size[sg_used] = sz; | |
5027 | buff[sg_used] = kmalloc(sz, GFP_KERNEL); | |
5028 | if (buff[sg_used] == NULL) { | |
5029 | status = -ENOMEM; | |
5030 | goto cleanup1; | |
5031 | } | |
9233fb10 | 5032 | if (ioc->Request.Type.Direction & XFER_WRITE) { |
edd16368 | 5033 | if (copy_from_user(buff[sg_used], data_ptr, sz)) { |
0758f4f7 | 5034 | status = -EFAULT; |
edd16368 SC |
5035 | goto cleanup1; |
5036 | } | |
5037 | } else | |
5038 | memset(buff[sg_used], 0, sz); | |
5039 | left -= sz; | |
5040 | data_ptr += sz; | |
5041 | sg_used++; | |
5042 | } | |
45fcb86e | 5043 | c = cmd_alloc(h); |
edd16368 SC |
5044 | if (c == NULL) { |
5045 | status = -ENOMEM; | |
5046 | goto cleanup1; | |
5047 | } | |
5048 | c->cmd_type = CMD_IOCTL_PEND; | |
5049 | c->Header.ReplyQueue = 0; | |
50a0decf SC |
5050 | c->Header.SGList = (u8) sg_used; |
5051 | c->Header.SGTotal = cpu_to_le16(sg_used); | |
edd16368 | 5052 | memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN)); |
edd16368 SC |
5053 | memcpy(&c->Request, &ioc->Request, sizeof(c->Request)); |
5054 | if (ioc->buf_size > 0) { | |
5055 | int i; | |
5056 | for (i = 0; i < sg_used; i++) { | |
50a0decf | 5057 | temp64 = pci_map_single(h->pdev, buff[i], |
edd16368 | 5058 | buff_size[i], PCI_DMA_BIDIRECTIONAL); |
50a0decf SC |
5059 | if (dma_mapping_error(&h->pdev->dev, |
5060 | (dma_addr_t) temp64)) { | |
5061 | c->SG[i].Addr = cpu_to_le64(0); | |
5062 | c->SG[i].Len = cpu_to_le32(0); | |
bcc48ffa SC |
5063 | hpsa_pci_unmap(h->pdev, c, i, |
5064 | PCI_DMA_BIDIRECTIONAL); | |
5065 | status = -ENOMEM; | |
e2d4a1f6 | 5066 | goto cleanup0; |
bcc48ffa | 5067 | } |
50a0decf SC |
5068 | c->SG[i].Addr = cpu_to_le64(temp64); |
5069 | c->SG[i].Len = cpu_to_le32(buff_size[i]); | |
5070 | c->SG[i].Ext = cpu_to_le32(0); | |
edd16368 | 5071 | } |
50a0decf | 5072 | c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST); |
edd16368 | 5073 | } |
a0c12413 | 5074 | hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c); |
b03a7771 SC |
5075 | if (sg_used) |
5076 | hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL); | |
edd16368 SC |
5077 | check_ioctl_unit_attention(h, c); |
5078 | /* Copy the error information out */ | |
5079 | memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info)); | |
5080 | if (copy_to_user(argp, ioc, sizeof(*ioc))) { | |
edd16368 | 5081 | status = -EFAULT; |
e2d4a1f6 | 5082 | goto cleanup0; |
edd16368 | 5083 | } |
9233fb10 | 5084 | if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) { |
2b08b3e9 DB |
5085 | int i; |
5086 | ||
edd16368 SC |
5087 | /* Copy the data out of the buffer we created */ |
5088 | BYTE __user *ptr = ioc->buf; | |
5089 | for (i = 0; i < sg_used; i++) { | |
5090 | if (copy_to_user(ptr, buff[i], buff_size[i])) { | |
edd16368 | 5091 | status = -EFAULT; |
e2d4a1f6 | 5092 | goto cleanup0; |
edd16368 SC |
5093 | } |
5094 | ptr += buff_size[i]; | |
5095 | } | |
5096 | } | |
edd16368 | 5097 | status = 0; |
e2d4a1f6 | 5098 | cleanup0: |
45fcb86e | 5099 | cmd_free(h, c); |
edd16368 SC |
5100 | cleanup1: |
5101 | if (buff) { | |
2b08b3e9 DB |
5102 | int i; |
5103 | ||
edd16368 SC |
5104 | for (i = 0; i < sg_used; i++) |
5105 | kfree(buff[i]); | |
5106 | kfree(buff); | |
5107 | } | |
5108 | kfree(buff_size); | |
5109 | kfree(ioc); | |
5110 | return status; | |
5111 | } | |
5112 | ||
5113 | static void check_ioctl_unit_attention(struct ctlr_info *h, | |
5114 | struct CommandList *c) | |
5115 | { | |
5116 | if (c->err_info->CommandStatus == CMD_TARGET_STATUS && | |
5117 | c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION) | |
5118 | (void) check_for_unit_attention(h, c); | |
5119 | } | |
0390f0c0 | 5120 | |
edd16368 SC |
5121 | /* |
5122 | * ioctl | |
5123 | */ | |
42a91641 | 5124 | static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg) |
edd16368 SC |
5125 | { |
5126 | struct ctlr_info *h; | |
5127 | void __user *argp = (void __user *)arg; | |
0390f0c0 | 5128 | int rc; |
edd16368 SC |
5129 | |
5130 | h = sdev_to_hba(dev); | |
5131 | ||
5132 | switch (cmd) { | |
5133 | case CCISS_DEREGDISK: | |
5134 | case CCISS_REGNEWDISK: | |
5135 | case CCISS_REGNEWD: | |
a08a8471 | 5136 | hpsa_scan_start(h->scsi_host); |
edd16368 SC |
5137 | return 0; |
5138 | case CCISS_GETPCIINFO: | |
5139 | return hpsa_getpciinfo_ioctl(h, argp); | |
5140 | case CCISS_GETDRIVVER: | |
5141 | return hpsa_getdrivver_ioctl(h, argp); | |
5142 | case CCISS_PASSTHRU: | |
34f0c627 | 5143 | if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) |
0390f0c0 SC |
5144 | return -EAGAIN; |
5145 | rc = hpsa_passthru_ioctl(h, argp); | |
34f0c627 | 5146 | atomic_inc(&h->passthru_cmds_avail); |
0390f0c0 | 5147 | return rc; |
edd16368 | 5148 | case CCISS_BIG_PASSTHRU: |
34f0c627 | 5149 | if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0) |
0390f0c0 SC |
5150 | return -EAGAIN; |
5151 | rc = hpsa_big_passthru_ioctl(h, argp); | |
34f0c627 | 5152 | atomic_inc(&h->passthru_cmds_avail); |
0390f0c0 | 5153 | return rc; |
edd16368 SC |
5154 | default: |
5155 | return -ENOTTY; | |
5156 | } | |
5157 | } | |
5158 | ||
6f039790 GKH |
5159 | static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr, |
5160 | u8 reset_type) | |
64670ac8 SC |
5161 | { |
5162 | struct CommandList *c; | |
5163 | ||
5164 | c = cmd_alloc(h); | |
5165 | if (!c) | |
5166 | return -ENOMEM; | |
a2dac136 SC |
5167 | /* fill_cmd can't fail here, no data buffer to map */ |
5168 | (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0, | |
64670ac8 SC |
5169 | RAID_CTLR_LUNID, TYPE_MSG); |
5170 | c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */ | |
5171 | c->waiting = NULL; | |
5172 | enqueue_cmd_and_start_io(h, c); | |
5173 | /* Don't wait for completion, the reset won't complete. Don't free | |
5174 | * the command either. This is the last command we will send before | |
5175 | * re-initializing everything, so it doesn't matter and won't leak. | |
5176 | */ | |
5177 | return 0; | |
5178 | } | |
5179 | ||
a2dac136 | 5180 | static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h, |
b7bb24eb | 5181 | void *buff, size_t size, u16 page_code, unsigned char *scsi3addr, |
edd16368 SC |
5182 | int cmd_type) |
5183 | { | |
5184 | int pci_dir = XFER_NONE; | |
75167d2c | 5185 | struct CommandList *a; /* for commands to be aborted */ |
edd16368 SC |
5186 | |
5187 | c->cmd_type = CMD_IOCTL_PEND; | |
5188 | c->Header.ReplyQueue = 0; | |
5189 | if (buff != NULL && size > 0) { | |
5190 | c->Header.SGList = 1; | |
50a0decf | 5191 | c->Header.SGTotal = cpu_to_le16(1); |
edd16368 SC |
5192 | } else { |
5193 | c->Header.SGList = 0; | |
50a0decf | 5194 | c->Header.SGTotal = cpu_to_le16(0); |
edd16368 | 5195 | } |
edd16368 SC |
5196 | memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8); |
5197 | ||
edd16368 SC |
5198 | if (cmd_type == TYPE_CMD) { |
5199 | switch (cmd) { | |
5200 | case HPSA_INQUIRY: | |
5201 | /* are we trying to read a vital product page */ | |
b7bb24eb | 5202 | if (page_code & VPD_PAGE) { |
edd16368 | 5203 | c->Request.CDB[1] = 0x01; |
b7bb24eb | 5204 | c->Request.CDB[2] = (page_code & 0xff); |
edd16368 SC |
5205 | } |
5206 | c->Request.CDBLen = 6; | |
a505b86f SC |
5207 | c->Request.type_attr_dir = |
5208 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
edd16368 SC |
5209 | c->Request.Timeout = 0; |
5210 | c->Request.CDB[0] = HPSA_INQUIRY; | |
5211 | c->Request.CDB[4] = size & 0xFF; | |
5212 | break; | |
5213 | case HPSA_REPORT_LOG: | |
5214 | case HPSA_REPORT_PHYS: | |
5215 | /* Talking to controller so It's a physical command | |
5216 | mode = 00 target = 0. Nothing to write. | |
5217 | */ | |
5218 | c->Request.CDBLen = 12; | |
a505b86f SC |
5219 | c->Request.type_attr_dir = |
5220 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
edd16368 SC |
5221 | c->Request.Timeout = 0; |
5222 | c->Request.CDB[0] = cmd; | |
5223 | c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ | |
5224 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
5225 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
5226 | c->Request.CDB[9] = size & 0xFF; | |
5227 | break; | |
edd16368 SC |
5228 | case HPSA_CACHE_FLUSH: |
5229 | c->Request.CDBLen = 12; | |
a505b86f SC |
5230 | c->Request.type_attr_dir = |
5231 | TYPE_ATTR_DIR(cmd_type, | |
5232 | ATTR_SIMPLE, XFER_WRITE); | |
edd16368 SC |
5233 | c->Request.Timeout = 0; |
5234 | c->Request.CDB[0] = BMIC_WRITE; | |
5235 | c->Request.CDB[6] = BMIC_CACHE_FLUSH; | |
bb158eab SC |
5236 | c->Request.CDB[7] = (size >> 8) & 0xFF; |
5237 | c->Request.CDB[8] = size & 0xFF; | |
edd16368 SC |
5238 | break; |
5239 | case TEST_UNIT_READY: | |
5240 | c->Request.CDBLen = 6; | |
a505b86f SC |
5241 | c->Request.type_attr_dir = |
5242 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); | |
edd16368 SC |
5243 | c->Request.Timeout = 0; |
5244 | break; | |
283b4a9b SC |
5245 | case HPSA_GET_RAID_MAP: |
5246 | c->Request.CDBLen = 12; | |
a505b86f SC |
5247 | c->Request.type_attr_dir = |
5248 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
283b4a9b SC |
5249 | c->Request.Timeout = 0; |
5250 | c->Request.CDB[0] = HPSA_CISS_READ; | |
5251 | c->Request.CDB[1] = cmd; | |
5252 | c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */ | |
5253 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
5254 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
5255 | c->Request.CDB[9] = size & 0xFF; | |
5256 | break; | |
316b221a SC |
5257 | case BMIC_SENSE_CONTROLLER_PARAMETERS: |
5258 | c->Request.CDBLen = 10; | |
a505b86f SC |
5259 | c->Request.type_attr_dir = |
5260 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
316b221a SC |
5261 | c->Request.Timeout = 0; |
5262 | c->Request.CDB[0] = BMIC_READ; | |
5263 | c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS; | |
5264 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
5265 | c->Request.CDB[8] = (size >> 8) & 0xFF; | |
5266 | break; | |
03383736 DB |
5267 | case BMIC_IDENTIFY_PHYSICAL_DEVICE: |
5268 | c->Request.CDBLen = 10; | |
5269 | c->Request.type_attr_dir = | |
5270 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ); | |
5271 | c->Request.Timeout = 0; | |
5272 | c->Request.CDB[0] = BMIC_READ; | |
5273 | c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE; | |
5274 | c->Request.CDB[7] = (size >> 16) & 0xFF; | |
5275 | c->Request.CDB[8] = (size >> 8) & 0XFF; | |
5276 | break; | |
edd16368 SC |
5277 | default: |
5278 | dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd); | |
5279 | BUG(); | |
a2dac136 | 5280 | return -1; |
edd16368 SC |
5281 | } |
5282 | } else if (cmd_type == TYPE_MSG) { | |
5283 | switch (cmd) { | |
5284 | ||
5285 | case HPSA_DEVICE_RESET_MSG: | |
5286 | c->Request.CDBLen = 16; | |
a505b86f SC |
5287 | c->Request.type_attr_dir = |
5288 | TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE); | |
edd16368 | 5289 | c->Request.Timeout = 0; /* Don't time out */ |
64670ac8 SC |
5290 | memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB)); |
5291 | c->Request.CDB[0] = cmd; | |
21e89afd | 5292 | c->Request.CDB[1] = HPSA_RESET_TYPE_LUN; |
edd16368 SC |
5293 | /* If bytes 4-7 are zero, it means reset the */ |
5294 | /* LunID device */ | |
5295 | c->Request.CDB[4] = 0x00; | |
5296 | c->Request.CDB[5] = 0x00; | |
5297 | c->Request.CDB[6] = 0x00; | |
5298 | c->Request.CDB[7] = 0x00; | |
75167d2c SC |
5299 | break; |
5300 | case HPSA_ABORT_MSG: | |
5301 | a = buff; /* point to command to be aborted */ | |
2b08b3e9 DB |
5302 | dev_dbg(&h->pdev->dev, |
5303 | "Abort Tag:0x%016llx request Tag:0x%016llx", | |
50a0decf | 5304 | a->Header.tag, c->Header.tag); |
75167d2c | 5305 | c->Request.CDBLen = 16; |
a505b86f SC |
5306 | c->Request.type_attr_dir = |
5307 | TYPE_ATTR_DIR(cmd_type, | |
5308 | ATTR_SIMPLE, XFER_WRITE); | |
75167d2c SC |
5309 | c->Request.Timeout = 0; /* Don't time out */ |
5310 | c->Request.CDB[0] = HPSA_TASK_MANAGEMENT; | |
5311 | c->Request.CDB[1] = HPSA_TMF_ABORT_TASK; | |
5312 | c->Request.CDB[2] = 0x00; /* reserved */ | |
5313 | c->Request.CDB[3] = 0x00; /* reserved */ | |
5314 | /* Tag to abort goes in CDB[4]-CDB[11] */ | |
2b08b3e9 DB |
5315 | memcpy(&c->Request.CDB[4], &a->Header.tag, |
5316 | sizeof(a->Header.tag)); | |
75167d2c SC |
5317 | c->Request.CDB[12] = 0x00; /* reserved */ |
5318 | c->Request.CDB[13] = 0x00; /* reserved */ | |
5319 | c->Request.CDB[14] = 0x00; /* reserved */ | |
5320 | c->Request.CDB[15] = 0x00; /* reserved */ | |
edd16368 | 5321 | break; |
edd16368 SC |
5322 | default: |
5323 | dev_warn(&h->pdev->dev, "unknown message type %d\n", | |
5324 | cmd); | |
5325 | BUG(); | |
5326 | } | |
5327 | } else { | |
5328 | dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type); | |
5329 | BUG(); | |
5330 | } | |
5331 | ||
a505b86f | 5332 | switch (GET_DIR(c->Request.type_attr_dir)) { |
edd16368 SC |
5333 | case XFER_READ: |
5334 | pci_dir = PCI_DMA_FROMDEVICE; | |
5335 | break; | |
5336 | case XFER_WRITE: | |
5337 | pci_dir = PCI_DMA_TODEVICE; | |
5338 | break; | |
5339 | case XFER_NONE: | |
5340 | pci_dir = PCI_DMA_NONE; | |
5341 | break; | |
5342 | default: | |
5343 | pci_dir = PCI_DMA_BIDIRECTIONAL; | |
5344 | } | |
a2dac136 SC |
5345 | if (hpsa_map_one(h->pdev, c, buff, size, pci_dir)) |
5346 | return -1; | |
5347 | return 0; | |
edd16368 SC |
5348 | } |
5349 | ||
5350 | /* | |
5351 | * Map (physical) PCI mem into (virtual) kernel space | |
5352 | */ | |
5353 | static void __iomem *remap_pci_mem(ulong base, ulong size) | |
5354 | { | |
5355 | ulong page_base = ((ulong) base) & PAGE_MASK; | |
5356 | ulong page_offs = ((ulong) base) - page_base; | |
088ba34c SC |
5357 | void __iomem *page_remapped = ioremap_nocache(page_base, |
5358 | page_offs + size); | |
edd16368 SC |
5359 | |
5360 | return page_remapped ? (page_remapped + page_offs) : NULL; | |
5361 | } | |
5362 | ||
254f796b | 5363 | static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q) |
edd16368 | 5364 | { |
254f796b | 5365 | return h->access.command_completed(h, q); |
edd16368 SC |
5366 | } |
5367 | ||
900c5440 | 5368 | static inline bool interrupt_pending(struct ctlr_info *h) |
edd16368 SC |
5369 | { |
5370 | return h->access.intr_pending(h); | |
5371 | } | |
5372 | ||
5373 | static inline long interrupt_not_for_us(struct ctlr_info *h) | |
5374 | { | |
10f66018 SC |
5375 | return (h->access.intr_pending(h) == 0) || |
5376 | (h->interrupts_enabled == 0); | |
edd16368 SC |
5377 | } |
5378 | ||
01a02ffc SC |
5379 | static inline int bad_tag(struct ctlr_info *h, u32 tag_index, |
5380 | u32 raw_tag) | |
edd16368 SC |
5381 | { |
5382 | if (unlikely(tag_index >= h->nr_cmds)) { | |
5383 | dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag); | |
5384 | return 1; | |
5385 | } | |
5386 | return 0; | |
5387 | } | |
5388 | ||
5a3d16f5 | 5389 | static inline void finish_cmd(struct CommandList *c) |
edd16368 | 5390 | { |
e85c5974 | 5391 | dial_up_lockup_detection_on_fw_flash_complete(c->h, c); |
c349775e ST |
5392 | if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI |
5393 | || c->cmd_type == CMD_IOACCEL2)) | |
1fb011fb | 5394 | complete_scsi_command(c); |
edd16368 SC |
5395 | else if (c->cmd_type == CMD_IOCTL_PEND) |
5396 | complete(c->waiting); | |
a104c99f SC |
5397 | } |
5398 | ||
a9a3a273 SC |
5399 | |
5400 | static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag) | |
a104c99f | 5401 | { |
a9a3a273 SC |
5402 | #define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1) |
5403 | #define HPSA_SIMPLE_ERROR_BITS 0x03 | |
960a30e7 | 5404 | if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant))) |
a9a3a273 SC |
5405 | return tag & ~HPSA_SIMPLE_ERROR_BITS; |
5406 | return tag & ~HPSA_PERF_ERROR_BITS; | |
a104c99f SC |
5407 | } |
5408 | ||
303932fd | 5409 | /* process completion of an indexed ("direct lookup") command */ |
1d94f94d | 5410 | static inline void process_indexed_cmd(struct ctlr_info *h, |
303932fd DB |
5411 | u32 raw_tag) |
5412 | { | |
5413 | u32 tag_index; | |
5414 | struct CommandList *c; | |
5415 | ||
f2405db8 | 5416 | tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT; |
1d94f94d SC |
5417 | if (!bad_tag(h, tag_index, raw_tag)) { |
5418 | c = h->cmd_pool + tag_index; | |
5419 | finish_cmd(c); | |
5420 | } | |
303932fd DB |
5421 | } |
5422 | ||
64670ac8 SC |
5423 | /* Some controllers, like p400, will give us one interrupt |
5424 | * after a soft reset, even if we turned interrupts off. | |
5425 | * Only need to check for this in the hpsa_xxx_discard_completions | |
5426 | * functions. | |
5427 | */ | |
5428 | static int ignore_bogus_interrupt(struct ctlr_info *h) | |
5429 | { | |
5430 | if (likely(!reset_devices)) | |
5431 | return 0; | |
5432 | ||
5433 | if (likely(h->interrupts_enabled)) | |
5434 | return 0; | |
5435 | ||
5436 | dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled " | |
5437 | "(known firmware bug.) Ignoring.\n"); | |
5438 | ||
5439 | return 1; | |
5440 | } | |
5441 | ||
254f796b MG |
5442 | /* |
5443 | * Convert &h->q[x] (passed to interrupt handlers) back to h. | |
5444 | * Relies on (h-q[x] == x) being true for x such that | |
5445 | * 0 <= x < MAX_REPLY_QUEUES. | |
5446 | */ | |
5447 | static struct ctlr_info *queue_to_hba(u8 *queue) | |
64670ac8 | 5448 | { |
254f796b MG |
5449 | return container_of((queue - *queue), struct ctlr_info, q[0]); |
5450 | } | |
5451 | ||
5452 | static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue) | |
5453 | { | |
5454 | struct ctlr_info *h = queue_to_hba(queue); | |
5455 | u8 q = *(u8 *) queue; | |
64670ac8 SC |
5456 | u32 raw_tag; |
5457 | ||
5458 | if (ignore_bogus_interrupt(h)) | |
5459 | return IRQ_NONE; | |
5460 | ||
5461 | if (interrupt_not_for_us(h)) | |
5462 | return IRQ_NONE; | |
a0c12413 | 5463 | h->last_intr_timestamp = get_jiffies_64(); |
64670ac8 | 5464 | while (interrupt_pending(h)) { |
254f796b | 5465 | raw_tag = get_next_completion(h, q); |
64670ac8 | 5466 | while (raw_tag != FIFO_EMPTY) |
254f796b | 5467 | raw_tag = next_command(h, q); |
64670ac8 | 5468 | } |
64670ac8 SC |
5469 | return IRQ_HANDLED; |
5470 | } | |
5471 | ||
254f796b | 5472 | static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue) |
64670ac8 | 5473 | { |
254f796b | 5474 | struct ctlr_info *h = queue_to_hba(queue); |
64670ac8 | 5475 | u32 raw_tag; |
254f796b | 5476 | u8 q = *(u8 *) queue; |
64670ac8 SC |
5477 | |
5478 | if (ignore_bogus_interrupt(h)) | |
5479 | return IRQ_NONE; | |
5480 | ||
a0c12413 | 5481 | h->last_intr_timestamp = get_jiffies_64(); |
254f796b | 5482 | raw_tag = get_next_completion(h, q); |
64670ac8 | 5483 | while (raw_tag != FIFO_EMPTY) |
254f796b | 5484 | raw_tag = next_command(h, q); |
64670ac8 SC |
5485 | return IRQ_HANDLED; |
5486 | } | |
5487 | ||
254f796b | 5488 | static irqreturn_t do_hpsa_intr_intx(int irq, void *queue) |
edd16368 | 5489 | { |
254f796b | 5490 | struct ctlr_info *h = queue_to_hba((u8 *) queue); |
303932fd | 5491 | u32 raw_tag; |
254f796b | 5492 | u8 q = *(u8 *) queue; |
edd16368 SC |
5493 | |
5494 | if (interrupt_not_for_us(h)) | |
5495 | return IRQ_NONE; | |
a0c12413 | 5496 | h->last_intr_timestamp = get_jiffies_64(); |
10f66018 | 5497 | while (interrupt_pending(h)) { |
254f796b | 5498 | raw_tag = get_next_completion(h, q); |
10f66018 | 5499 | while (raw_tag != FIFO_EMPTY) { |
f2405db8 | 5500 | process_indexed_cmd(h, raw_tag); |
254f796b | 5501 | raw_tag = next_command(h, q); |
10f66018 SC |
5502 | } |
5503 | } | |
10f66018 SC |
5504 | return IRQ_HANDLED; |
5505 | } | |
5506 | ||
254f796b | 5507 | static irqreturn_t do_hpsa_intr_msi(int irq, void *queue) |
10f66018 | 5508 | { |
254f796b | 5509 | struct ctlr_info *h = queue_to_hba(queue); |
10f66018 | 5510 | u32 raw_tag; |
254f796b | 5511 | u8 q = *(u8 *) queue; |
10f66018 | 5512 | |
a0c12413 | 5513 | h->last_intr_timestamp = get_jiffies_64(); |
254f796b | 5514 | raw_tag = get_next_completion(h, q); |
303932fd | 5515 | while (raw_tag != FIFO_EMPTY) { |
f2405db8 | 5516 | process_indexed_cmd(h, raw_tag); |
254f796b | 5517 | raw_tag = next_command(h, q); |
edd16368 | 5518 | } |
edd16368 SC |
5519 | return IRQ_HANDLED; |
5520 | } | |
5521 | ||
a9a3a273 SC |
5522 | /* Send a message CDB to the firmware. Careful, this only works |
5523 | * in simple mode, not performant mode due to the tag lookup. | |
5524 | * We only ever use this immediately after a controller reset. | |
5525 | */ | |
6f039790 GKH |
5526 | static int hpsa_message(struct pci_dev *pdev, unsigned char opcode, |
5527 | unsigned char type) | |
edd16368 SC |
5528 | { |
5529 | struct Command { | |
5530 | struct CommandListHeader CommandHeader; | |
5531 | struct RequestBlock Request; | |
5532 | struct ErrDescriptor ErrorDescriptor; | |
5533 | }; | |
5534 | struct Command *cmd; | |
5535 | static const size_t cmd_sz = sizeof(*cmd) + | |
5536 | sizeof(cmd->ErrorDescriptor); | |
5537 | dma_addr_t paddr64; | |
2b08b3e9 DB |
5538 | __le32 paddr32; |
5539 | u32 tag; | |
edd16368 SC |
5540 | void __iomem *vaddr; |
5541 | int i, err; | |
5542 | ||
5543 | vaddr = pci_ioremap_bar(pdev, 0); | |
5544 | if (vaddr == NULL) | |
5545 | return -ENOMEM; | |
5546 | ||
5547 | /* The Inbound Post Queue only accepts 32-bit physical addresses for the | |
5548 | * CCISS commands, so they must be allocated from the lower 4GiB of | |
5549 | * memory. | |
5550 | */ | |
5551 | err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); | |
5552 | if (err) { | |
5553 | iounmap(vaddr); | |
1eaec8f3 | 5554 | return err; |
edd16368 SC |
5555 | } |
5556 | ||
5557 | cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64); | |
5558 | if (cmd == NULL) { | |
5559 | iounmap(vaddr); | |
5560 | return -ENOMEM; | |
5561 | } | |
5562 | ||
5563 | /* This must fit, because of the 32-bit consistent DMA mask. Also, | |
5564 | * although there's no guarantee, we assume that the address is at | |
5565 | * least 4-byte aligned (most likely, it's page-aligned). | |
5566 | */ | |
2b08b3e9 | 5567 | paddr32 = cpu_to_le32(paddr64); |
edd16368 SC |
5568 | |
5569 | cmd->CommandHeader.ReplyQueue = 0; | |
5570 | cmd->CommandHeader.SGList = 0; | |
50a0decf | 5571 | cmd->CommandHeader.SGTotal = cpu_to_le16(0); |
2b08b3e9 | 5572 | cmd->CommandHeader.tag = cpu_to_le64(paddr64); |
edd16368 SC |
5573 | memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8); |
5574 | ||
5575 | cmd->Request.CDBLen = 16; | |
a505b86f SC |
5576 | cmd->Request.type_attr_dir = |
5577 | TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE); | |
edd16368 SC |
5578 | cmd->Request.Timeout = 0; /* Don't time out */ |
5579 | cmd->Request.CDB[0] = opcode; | |
5580 | cmd->Request.CDB[1] = type; | |
5581 | memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */ | |
50a0decf | 5582 | cmd->ErrorDescriptor.Addr = |
2b08b3e9 | 5583 | cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd))); |
50a0decf | 5584 | cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo)); |
edd16368 | 5585 | |
2b08b3e9 | 5586 | writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET); |
edd16368 SC |
5587 | |
5588 | for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) { | |
5589 | tag = readl(vaddr + SA5_REPLY_PORT_OFFSET); | |
2b08b3e9 | 5590 | if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64) |
edd16368 SC |
5591 | break; |
5592 | msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS); | |
5593 | } | |
5594 | ||
5595 | iounmap(vaddr); | |
5596 | ||
5597 | /* we leak the DMA buffer here ... no choice since the controller could | |
5598 | * still complete the command. | |
5599 | */ | |
5600 | if (i == HPSA_MSG_SEND_RETRY_LIMIT) { | |
5601 | dev_err(&pdev->dev, "controller message %02x:%02x timed out\n", | |
5602 | opcode, type); | |
5603 | return -ETIMEDOUT; | |
5604 | } | |
5605 | ||
5606 | pci_free_consistent(pdev, cmd_sz, cmd, paddr64); | |
5607 | ||
5608 | if (tag & HPSA_ERROR_BIT) { | |
5609 | dev_err(&pdev->dev, "controller message %02x:%02x failed\n", | |
5610 | opcode, type); | |
5611 | return -EIO; | |
5612 | } | |
5613 | ||
5614 | dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n", | |
5615 | opcode, type); | |
5616 | return 0; | |
5617 | } | |
5618 | ||
edd16368 SC |
5619 | #define hpsa_noop(p) hpsa_message(p, 3, 0) |
5620 | ||
1df8552a | 5621 | static int hpsa_controller_hard_reset(struct pci_dev *pdev, |
42a91641 | 5622 | void __iomem *vaddr, u32 use_doorbell) |
1df8552a | 5623 | { |
1df8552a SC |
5624 | |
5625 | if (use_doorbell) { | |
5626 | /* For everything after the P600, the PCI power state method | |
5627 | * of resetting the controller doesn't work, so we have this | |
5628 | * other way using the doorbell register. | |
5629 | */ | |
5630 | dev_info(&pdev->dev, "using doorbell to reset controller\n"); | |
cf0b08d0 | 5631 | writel(use_doorbell, vaddr + SA5_DOORBELL); |
85009239 | 5632 | |
00701a96 | 5633 | /* PMC hardware guys tell us we need a 10 second delay after |
85009239 SC |
5634 | * doorbell reset and before any attempt to talk to the board |
5635 | * at all to ensure that this actually works and doesn't fall | |
5636 | * over in some weird corner cases. | |
5637 | */ | |
00701a96 | 5638 | msleep(10000); |
1df8552a SC |
5639 | } else { /* Try to do it the PCI power state way */ |
5640 | ||
5641 | /* Quoting from the Open CISS Specification: "The Power | |
5642 | * Management Control/Status Register (CSR) controls the power | |
5643 | * state of the device. The normal operating state is D0, | |
5644 | * CSR=00h. The software off state is D3, CSR=03h. To reset | |
5645 | * the controller, place the interface device in D3 then to D0, | |
5646 | * this causes a secondary PCI reset which will reset the | |
5647 | * controller." */ | |
2662cab8 DB |
5648 | |
5649 | int rc = 0; | |
5650 | ||
1df8552a | 5651 | dev_info(&pdev->dev, "using PCI PM to reset controller\n"); |
2662cab8 | 5652 | |
1df8552a | 5653 | /* enter the D3hot power management state */ |
2662cab8 DB |
5654 | rc = pci_set_power_state(pdev, PCI_D3hot); |
5655 | if (rc) | |
5656 | return rc; | |
1df8552a SC |
5657 | |
5658 | msleep(500); | |
5659 | ||
5660 | /* enter the D0 power management state */ | |
2662cab8 DB |
5661 | rc = pci_set_power_state(pdev, PCI_D0); |
5662 | if (rc) | |
5663 | return rc; | |
c4853efe MM |
5664 | |
5665 | /* | |
5666 | * The P600 requires a small delay when changing states. | |
5667 | * Otherwise we may think the board did not reset and we bail. | |
5668 | * This for kdump only and is particular to the P600. | |
5669 | */ | |
5670 | msleep(500); | |
1df8552a SC |
5671 | } |
5672 | return 0; | |
5673 | } | |
5674 | ||
6f039790 | 5675 | static void init_driver_version(char *driver_version, int len) |
580ada3c SC |
5676 | { |
5677 | memset(driver_version, 0, len); | |
f79cfec6 | 5678 | strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1); |
580ada3c SC |
5679 | } |
5680 | ||
6f039790 | 5681 | static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable) |
580ada3c SC |
5682 | { |
5683 | char *driver_version; | |
5684 | int i, size = sizeof(cfgtable->driver_version); | |
5685 | ||
5686 | driver_version = kmalloc(size, GFP_KERNEL); | |
5687 | if (!driver_version) | |
5688 | return -ENOMEM; | |
5689 | ||
5690 | init_driver_version(driver_version, size); | |
5691 | for (i = 0; i < size; i++) | |
5692 | writeb(driver_version[i], &cfgtable->driver_version[i]); | |
5693 | kfree(driver_version); | |
5694 | return 0; | |
5695 | } | |
5696 | ||
6f039790 GKH |
5697 | static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable, |
5698 | unsigned char *driver_ver) | |
580ada3c SC |
5699 | { |
5700 | int i; | |
5701 | ||
5702 | for (i = 0; i < sizeof(cfgtable->driver_version); i++) | |
5703 | driver_ver[i] = readb(&cfgtable->driver_version[i]); | |
5704 | } | |
5705 | ||
6f039790 | 5706 | static int controller_reset_failed(struct CfgTable __iomem *cfgtable) |
580ada3c SC |
5707 | { |
5708 | ||
5709 | char *driver_ver, *old_driver_ver; | |
5710 | int rc, size = sizeof(cfgtable->driver_version); | |
5711 | ||
5712 | old_driver_ver = kmalloc(2 * size, GFP_KERNEL); | |
5713 | if (!old_driver_ver) | |
5714 | return -ENOMEM; | |
5715 | driver_ver = old_driver_ver + size; | |
5716 | ||
5717 | /* After a reset, the 32 bytes of "driver version" in the cfgtable | |
5718 | * should have been changed, otherwise we know the reset failed. | |
5719 | */ | |
5720 | init_driver_version(old_driver_ver, size); | |
5721 | read_driver_ver_from_cfgtable(cfgtable, driver_ver); | |
5722 | rc = !memcmp(driver_ver, old_driver_ver, size); | |
5723 | kfree(old_driver_ver); | |
5724 | return rc; | |
5725 | } | |
edd16368 | 5726 | /* This does a hard reset of the controller using PCI power management |
1df8552a | 5727 | * states or the using the doorbell register. |
edd16368 | 5728 | */ |
6f039790 | 5729 | static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev) |
edd16368 | 5730 | { |
1df8552a SC |
5731 | u64 cfg_offset; |
5732 | u32 cfg_base_addr; | |
5733 | u64 cfg_base_addr_index; | |
5734 | void __iomem *vaddr; | |
5735 | unsigned long paddr; | |
580ada3c | 5736 | u32 misc_fw_support; |
270d05de | 5737 | int rc; |
1df8552a | 5738 | struct CfgTable __iomem *cfgtable; |
cf0b08d0 | 5739 | u32 use_doorbell; |
18867659 | 5740 | u32 board_id; |
270d05de | 5741 | u16 command_register; |
edd16368 | 5742 | |
1df8552a SC |
5743 | /* For controllers as old as the P600, this is very nearly |
5744 | * the same thing as | |
edd16368 SC |
5745 | * |
5746 | * pci_save_state(pci_dev); | |
5747 | * pci_set_power_state(pci_dev, PCI_D3hot); | |
5748 | * pci_set_power_state(pci_dev, PCI_D0); | |
5749 | * pci_restore_state(pci_dev); | |
5750 | * | |
1df8552a SC |
5751 | * For controllers newer than the P600, the pci power state |
5752 | * method of resetting doesn't work so we have another way | |
5753 | * using the doorbell register. | |
edd16368 | 5754 | */ |
18867659 | 5755 | |
25c1e56a | 5756 | rc = hpsa_lookup_board_id(pdev, &board_id); |
60f923b9 RE |
5757 | if (rc < 0) { |
5758 | dev_warn(&pdev->dev, "Board ID not found\n"); | |
5759 | return rc; | |
5760 | } | |
5761 | if (!ctlr_is_resettable(board_id)) { | |
5762 | dev_warn(&pdev->dev, "Controller not resettable\n"); | |
25c1e56a SC |
5763 | return -ENODEV; |
5764 | } | |
46380786 SC |
5765 | |
5766 | /* if controller is soft- but not hard resettable... */ | |
5767 | if (!ctlr_is_hard_resettable(board_id)) | |
5768 | return -ENOTSUPP; /* try soft reset later. */ | |
18867659 | 5769 | |
270d05de SC |
5770 | /* Save the PCI command register */ |
5771 | pci_read_config_word(pdev, 4, &command_register); | |
270d05de | 5772 | pci_save_state(pdev); |
edd16368 | 5773 | |
1df8552a SC |
5774 | /* find the first memory BAR, so we can find the cfg table */ |
5775 | rc = hpsa_pci_find_memory_BAR(pdev, &paddr); | |
5776 | if (rc) | |
5777 | return rc; | |
5778 | vaddr = remap_pci_mem(paddr, 0x250); | |
5779 | if (!vaddr) | |
5780 | return -ENOMEM; | |
edd16368 | 5781 | |
1df8552a SC |
5782 | /* find cfgtable in order to check if reset via doorbell is supported */ |
5783 | rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr, | |
5784 | &cfg_base_addr_index, &cfg_offset); | |
5785 | if (rc) | |
5786 | goto unmap_vaddr; | |
5787 | cfgtable = remap_pci_mem(pci_resource_start(pdev, | |
5788 | cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable)); | |
5789 | if (!cfgtable) { | |
5790 | rc = -ENOMEM; | |
5791 | goto unmap_vaddr; | |
5792 | } | |
580ada3c SC |
5793 | rc = write_driver_ver_to_cfgtable(cfgtable); |
5794 | if (rc) | |
03741d95 | 5795 | goto unmap_cfgtable; |
edd16368 | 5796 | |
cf0b08d0 SC |
5797 | /* If reset via doorbell register is supported, use that. |
5798 | * There are two such methods. Favor the newest method. | |
5799 | */ | |
1df8552a | 5800 | misc_fw_support = readl(&cfgtable->misc_fw_support); |
cf0b08d0 SC |
5801 | use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2; |
5802 | if (use_doorbell) { | |
5803 | use_doorbell = DOORBELL_CTLR_RESET2; | |
5804 | } else { | |
5805 | use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET; | |
5806 | if (use_doorbell) { | |
050f7147 SC |
5807 | dev_warn(&pdev->dev, |
5808 | "Soft reset not supported. Firmware update is required.\n"); | |
64670ac8 | 5809 | rc = -ENOTSUPP; /* try soft reset */ |
cf0b08d0 SC |
5810 | goto unmap_cfgtable; |
5811 | } | |
5812 | } | |
edd16368 | 5813 | |
1df8552a SC |
5814 | rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell); |
5815 | if (rc) | |
5816 | goto unmap_cfgtable; | |
edd16368 | 5817 | |
270d05de | 5818 | pci_restore_state(pdev); |
270d05de | 5819 | pci_write_config_word(pdev, 4, command_register); |
edd16368 | 5820 | |
1df8552a SC |
5821 | /* Some devices (notably the HP Smart Array 5i Controller) |
5822 | need a little pause here */ | |
5823 | msleep(HPSA_POST_RESET_PAUSE_MSECS); | |
5824 | ||
fe5389c8 SC |
5825 | rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY); |
5826 | if (rc) { | |
5827 | dev_warn(&pdev->dev, | |
050f7147 | 5828 | "Failed waiting for board to become ready after hard reset\n"); |
fe5389c8 SC |
5829 | goto unmap_cfgtable; |
5830 | } | |
fe5389c8 | 5831 | |
580ada3c SC |
5832 | rc = controller_reset_failed(vaddr); |
5833 | if (rc < 0) | |
5834 | goto unmap_cfgtable; | |
5835 | if (rc) { | |
64670ac8 SC |
5836 | dev_warn(&pdev->dev, "Unable to successfully reset " |
5837 | "controller. Will try soft reset.\n"); | |
5838 | rc = -ENOTSUPP; | |
580ada3c | 5839 | } else { |
64670ac8 | 5840 | dev_info(&pdev->dev, "board ready after hard reset.\n"); |
1df8552a SC |
5841 | } |
5842 | ||
5843 | unmap_cfgtable: | |
5844 | iounmap(cfgtable); | |
5845 | ||
5846 | unmap_vaddr: | |
5847 | iounmap(vaddr); | |
5848 | return rc; | |
edd16368 SC |
5849 | } |
5850 | ||
5851 | /* | |
5852 | * We cannot read the structure directly, for portability we must use | |
5853 | * the io functions. | |
5854 | * This is for debug only. | |
5855 | */ | |
42a91641 | 5856 | static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb) |
edd16368 | 5857 | { |
58f8665c | 5858 | #ifdef HPSA_DEBUG |
edd16368 SC |
5859 | int i; |
5860 | char temp_name[17]; | |
5861 | ||
5862 | dev_info(dev, "Controller Configuration information\n"); | |
5863 | dev_info(dev, "------------------------------------\n"); | |
5864 | for (i = 0; i < 4; i++) | |
5865 | temp_name[i] = readb(&(tb->Signature[i])); | |
5866 | temp_name[4] = '\0'; | |
5867 | dev_info(dev, " Signature = %s\n", temp_name); | |
5868 | dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence))); | |
5869 | dev_info(dev, " Transport methods supported = 0x%x\n", | |
5870 | readl(&(tb->TransportSupport))); | |
5871 | dev_info(dev, " Transport methods active = 0x%x\n", | |
5872 | readl(&(tb->TransportActive))); | |
5873 | dev_info(dev, " Requested transport Method = 0x%x\n", | |
5874 | readl(&(tb->HostWrite.TransportRequest))); | |
5875 | dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n", | |
5876 | readl(&(tb->HostWrite.CoalIntDelay))); | |
5877 | dev_info(dev, " Coalesce Interrupt Count = 0x%x\n", | |
5878 | readl(&(tb->HostWrite.CoalIntCount))); | |
69d6e33d | 5879 | dev_info(dev, " Max outstanding commands = %d\n", |
edd16368 SC |
5880 | readl(&(tb->CmdsOutMax))); |
5881 | dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes))); | |
5882 | for (i = 0; i < 16; i++) | |
5883 | temp_name[i] = readb(&(tb->ServerName[i])); | |
5884 | temp_name[16] = '\0'; | |
5885 | dev_info(dev, " Server Name = %s\n", temp_name); | |
5886 | dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n", | |
5887 | readl(&(tb->HeartBeat))); | |
edd16368 | 5888 | #endif /* HPSA_DEBUG */ |
58f8665c | 5889 | } |
edd16368 SC |
5890 | |
5891 | static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr) | |
5892 | { | |
5893 | int i, offset, mem_type, bar_type; | |
5894 | ||
5895 | if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */ | |
5896 | return 0; | |
5897 | offset = 0; | |
5898 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { | |
5899 | bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE; | |
5900 | if (bar_type == PCI_BASE_ADDRESS_SPACE_IO) | |
5901 | offset += 4; | |
5902 | else { | |
5903 | mem_type = pci_resource_flags(pdev, i) & | |
5904 | PCI_BASE_ADDRESS_MEM_TYPE_MASK; | |
5905 | switch (mem_type) { | |
5906 | case PCI_BASE_ADDRESS_MEM_TYPE_32: | |
5907 | case PCI_BASE_ADDRESS_MEM_TYPE_1M: | |
5908 | offset += 4; /* 32 bit */ | |
5909 | break; | |
5910 | case PCI_BASE_ADDRESS_MEM_TYPE_64: | |
5911 | offset += 8; | |
5912 | break; | |
5913 | default: /* reserved in PCI 2.2 */ | |
5914 | dev_warn(&pdev->dev, | |
5915 | "base address is invalid\n"); | |
5916 | return -1; | |
5917 | break; | |
5918 | } | |
5919 | } | |
5920 | if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0) | |
5921 | return i + 1; | |
5922 | } | |
5923 | return -1; | |
5924 | } | |
5925 | ||
5926 | /* If MSI/MSI-X is supported by the kernel we will try to enable it on | |
050f7147 | 5927 | * controllers that are capable. If not, we use legacy INTx mode. |
edd16368 SC |
5928 | */ |
5929 | ||
6f039790 | 5930 | static void hpsa_interrupt_mode(struct ctlr_info *h) |
edd16368 SC |
5931 | { |
5932 | #ifdef CONFIG_PCI_MSI | |
254f796b MG |
5933 | int err, i; |
5934 | struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES]; | |
5935 | ||
5936 | for (i = 0; i < MAX_REPLY_QUEUES; i++) { | |
5937 | hpsa_msix_entries[i].vector = 0; | |
5938 | hpsa_msix_entries[i].entry = i; | |
5939 | } | |
edd16368 SC |
5940 | |
5941 | /* Some boards advertise MSI but don't really support it */ | |
6b3f4c52 SC |
5942 | if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) || |
5943 | (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11)) | |
edd16368 | 5944 | goto default_int_mode; |
55c06c71 | 5945 | if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) { |
050f7147 | 5946 | dev_info(&h->pdev->dev, "MSI-X capable controller\n"); |
eee0f03a | 5947 | h->msix_vector = MAX_REPLY_QUEUES; |
f89439bc SC |
5948 | if (h->msix_vector > num_online_cpus()) |
5949 | h->msix_vector = num_online_cpus(); | |
18fce3c4 AG |
5950 | err = pci_enable_msix_range(h->pdev, hpsa_msix_entries, |
5951 | 1, h->msix_vector); | |
5952 | if (err < 0) { | |
5953 | dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err); | |
5954 | h->msix_vector = 0; | |
5955 | goto single_msi_mode; | |
5956 | } else if (err < h->msix_vector) { | |
55c06c71 | 5957 | dev_warn(&h->pdev->dev, "only %d MSI-X vectors " |
edd16368 | 5958 | "available\n", err); |
edd16368 | 5959 | } |
18fce3c4 AG |
5960 | h->msix_vector = err; |
5961 | for (i = 0; i < h->msix_vector; i++) | |
5962 | h->intr[i] = hpsa_msix_entries[i].vector; | |
5963 | return; | |
edd16368 | 5964 | } |
18fce3c4 | 5965 | single_msi_mode: |
55c06c71 | 5966 | if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) { |
050f7147 | 5967 | dev_info(&h->pdev->dev, "MSI capable controller\n"); |
55c06c71 | 5968 | if (!pci_enable_msi(h->pdev)) |
edd16368 SC |
5969 | h->msi_vector = 1; |
5970 | else | |
55c06c71 | 5971 | dev_warn(&h->pdev->dev, "MSI init failed\n"); |
edd16368 SC |
5972 | } |
5973 | default_int_mode: | |
5974 | #endif /* CONFIG_PCI_MSI */ | |
5975 | /* if we get here we're going to use the default interrupt mode */ | |
a9a3a273 | 5976 | h->intr[h->intr_mode] = h->pdev->irq; |
edd16368 SC |
5977 | } |
5978 | ||
6f039790 | 5979 | static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id) |
e5c880d1 SC |
5980 | { |
5981 | int i; | |
5982 | u32 subsystem_vendor_id, subsystem_device_id; | |
5983 | ||
5984 | subsystem_vendor_id = pdev->subsystem_vendor; | |
5985 | subsystem_device_id = pdev->subsystem_device; | |
5986 | *board_id = ((subsystem_device_id << 16) & 0xffff0000) | | |
5987 | subsystem_vendor_id; | |
5988 | ||
5989 | for (i = 0; i < ARRAY_SIZE(products); i++) | |
5990 | if (*board_id == products[i].board_id) | |
5991 | return i; | |
5992 | ||
6798cc0a SC |
5993 | if ((subsystem_vendor_id != PCI_VENDOR_ID_HP && |
5994 | subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) || | |
5995 | !hpsa_allow_any) { | |
e5c880d1 SC |
5996 | dev_warn(&pdev->dev, "unrecognized board ID: " |
5997 | "0x%08x, ignoring.\n", *board_id); | |
5998 | return -ENODEV; | |
5999 | } | |
6000 | return ARRAY_SIZE(products) - 1; /* generic unknown smart array */ | |
6001 | } | |
6002 | ||
6f039790 GKH |
6003 | static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev, |
6004 | unsigned long *memory_bar) | |
3a7774ce SC |
6005 | { |
6006 | int i; | |
6007 | ||
6008 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) | |
12d2cd47 | 6009 | if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) { |
3a7774ce | 6010 | /* addressing mode bits already removed */ |
12d2cd47 SC |
6011 | *memory_bar = pci_resource_start(pdev, i); |
6012 | dev_dbg(&pdev->dev, "memory BAR = %lx\n", | |
3a7774ce SC |
6013 | *memory_bar); |
6014 | return 0; | |
6015 | } | |
12d2cd47 | 6016 | dev_warn(&pdev->dev, "no memory BAR found\n"); |
3a7774ce SC |
6017 | return -ENODEV; |
6018 | } | |
6019 | ||
6f039790 GKH |
6020 | static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr, |
6021 | int wait_for_ready) | |
2c4c8c8b | 6022 | { |
fe5389c8 | 6023 | int i, iterations; |
2c4c8c8b | 6024 | u32 scratchpad; |
fe5389c8 SC |
6025 | if (wait_for_ready) |
6026 | iterations = HPSA_BOARD_READY_ITERATIONS; | |
6027 | else | |
6028 | iterations = HPSA_BOARD_NOT_READY_ITERATIONS; | |
2c4c8c8b | 6029 | |
fe5389c8 SC |
6030 | for (i = 0; i < iterations; i++) { |
6031 | scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET); | |
6032 | if (wait_for_ready) { | |
6033 | if (scratchpad == HPSA_FIRMWARE_READY) | |
6034 | return 0; | |
6035 | } else { | |
6036 | if (scratchpad != HPSA_FIRMWARE_READY) | |
6037 | return 0; | |
6038 | } | |
2c4c8c8b SC |
6039 | msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS); |
6040 | } | |
fe5389c8 | 6041 | dev_warn(&pdev->dev, "board not ready, timed out.\n"); |
2c4c8c8b SC |
6042 | return -ENODEV; |
6043 | } | |
6044 | ||
6f039790 GKH |
6045 | static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr, |
6046 | u32 *cfg_base_addr, u64 *cfg_base_addr_index, | |
6047 | u64 *cfg_offset) | |
a51fd47f SC |
6048 | { |
6049 | *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET); | |
6050 | *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET); | |
6051 | *cfg_base_addr &= (u32) 0x0000ffff; | |
6052 | *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr); | |
6053 | if (*cfg_base_addr_index == -1) { | |
6054 | dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n"); | |
6055 | return -ENODEV; | |
6056 | } | |
6057 | return 0; | |
6058 | } | |
6059 | ||
6f039790 | 6060 | static int hpsa_find_cfgtables(struct ctlr_info *h) |
edd16368 | 6061 | { |
01a02ffc SC |
6062 | u64 cfg_offset; |
6063 | u32 cfg_base_addr; | |
6064 | u64 cfg_base_addr_index; | |
303932fd | 6065 | u32 trans_offset; |
a51fd47f | 6066 | int rc; |
77c4495c | 6067 | |
a51fd47f SC |
6068 | rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, |
6069 | &cfg_base_addr_index, &cfg_offset); | |
6070 | if (rc) | |
6071 | return rc; | |
77c4495c | 6072 | h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev, |
a51fd47f | 6073 | cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable)); |
cd3c81c4 RE |
6074 | if (!h->cfgtable) { |
6075 | dev_err(&h->pdev->dev, "Failed mapping cfgtable\n"); | |
77c4495c | 6076 | return -ENOMEM; |
cd3c81c4 | 6077 | } |
580ada3c SC |
6078 | rc = write_driver_ver_to_cfgtable(h->cfgtable); |
6079 | if (rc) | |
6080 | return rc; | |
77c4495c | 6081 | /* Find performant mode table. */ |
a51fd47f | 6082 | trans_offset = readl(&h->cfgtable->TransMethodOffset); |
77c4495c SC |
6083 | h->transtable = remap_pci_mem(pci_resource_start(h->pdev, |
6084 | cfg_base_addr_index)+cfg_offset+trans_offset, | |
6085 | sizeof(*h->transtable)); | |
6086 | if (!h->transtable) | |
6087 | return -ENOMEM; | |
6088 | return 0; | |
6089 | } | |
6090 | ||
6f039790 | 6091 | static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h) |
cba3d38b SC |
6092 | { |
6093 | h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands)); | |
72ceeaec SC |
6094 | |
6095 | /* Limit commands in memory limited kdump scenario. */ | |
6096 | if (reset_devices && h->max_commands > 32) | |
6097 | h->max_commands = 32; | |
6098 | ||
cba3d38b SC |
6099 | if (h->max_commands < 16) { |
6100 | dev_warn(&h->pdev->dev, "Controller reports " | |
6101 | "max supported commands of %d, an obvious lie. " | |
6102 | "Using 16. Ensure that firmware is up to date.\n", | |
6103 | h->max_commands); | |
6104 | h->max_commands = 16; | |
6105 | } | |
6106 | } | |
6107 | ||
c7ee65b3 WS |
6108 | /* If the controller reports that the total max sg entries is greater than 512, |
6109 | * then we know that chained SG blocks work. (Original smart arrays did not | |
6110 | * support chained SG blocks and would return zero for max sg entries.) | |
6111 | */ | |
6112 | static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h) | |
6113 | { | |
6114 | return h->maxsgentries > 512; | |
6115 | } | |
6116 | ||
b93d7536 SC |
6117 | /* Interrogate the hardware for some limits: |
6118 | * max commands, max SG elements without chaining, and with chaining, | |
6119 | * SG chain block size, etc. | |
6120 | */ | |
6f039790 | 6121 | static void hpsa_find_board_params(struct ctlr_info *h) |
b93d7536 | 6122 | { |
cba3d38b | 6123 | hpsa_get_max_perf_mode_cmds(h); |
45fcb86e | 6124 | h->nr_cmds = h->max_commands; |
b93d7536 | 6125 | h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements)); |
283b4a9b | 6126 | h->fw_support = readl(&(h->cfgtable->misc_fw_support)); |
c7ee65b3 WS |
6127 | if (hpsa_supports_chained_sg_blocks(h)) { |
6128 | /* Limit in-command s/g elements to 32 save dma'able memory. */ | |
b93d7536 | 6129 | h->max_cmd_sg_entries = 32; |
1a63ea6f | 6130 | h->chainsize = h->maxsgentries - h->max_cmd_sg_entries; |
b93d7536 SC |
6131 | h->maxsgentries--; /* save one for chain pointer */ |
6132 | } else { | |
c7ee65b3 WS |
6133 | /* |
6134 | * Original smart arrays supported at most 31 s/g entries | |
6135 | * embedded inline in the command (trying to use more | |
6136 | * would lock up the controller) | |
6137 | */ | |
6138 | h->max_cmd_sg_entries = 31; | |
1a63ea6f | 6139 | h->maxsgentries = 31; /* default to traditional values */ |
c7ee65b3 | 6140 | h->chainsize = 0; |
b93d7536 | 6141 | } |
75167d2c SC |
6142 | |
6143 | /* Find out what task management functions are supported and cache */ | |
6144 | h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags)); | |
0e7a7fce ST |
6145 | if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags)) |
6146 | dev_warn(&h->pdev->dev, "Physical aborts not supported\n"); | |
6147 | if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags)) | |
6148 | dev_warn(&h->pdev->dev, "Logical aborts not supported\n"); | |
b93d7536 SC |
6149 | } |
6150 | ||
76c46e49 SC |
6151 | static inline bool hpsa_CISS_signature_present(struct ctlr_info *h) |
6152 | { | |
0fc9fd40 | 6153 | if (!check_signature(h->cfgtable->Signature, "CISS", 4)) { |
050f7147 | 6154 | dev_err(&h->pdev->dev, "not a valid CISS config table\n"); |
76c46e49 SC |
6155 | return false; |
6156 | } | |
6157 | return true; | |
6158 | } | |
6159 | ||
97a5e98c | 6160 | static inline void hpsa_set_driver_support_bits(struct ctlr_info *h) |
f7c39101 | 6161 | { |
97a5e98c | 6162 | u32 driver_support; |
f7c39101 | 6163 | |
97a5e98c | 6164 | driver_support = readl(&(h->cfgtable->driver_support)); |
0b9e7b74 AB |
6165 | /* Need to enable prefetch in the SCSI core for 6400 in x86 */ |
6166 | #ifdef CONFIG_X86 | |
97a5e98c | 6167 | driver_support |= ENABLE_SCSI_PREFETCH; |
f7c39101 | 6168 | #endif |
28e13446 SC |
6169 | driver_support |= ENABLE_UNIT_ATTN; |
6170 | writel(driver_support, &(h->cfgtable->driver_support)); | |
f7c39101 SC |
6171 | } |
6172 | ||
3d0eab67 SC |
6173 | /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result |
6174 | * in a prefetch beyond physical memory. | |
6175 | */ | |
6176 | static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h) | |
6177 | { | |
6178 | u32 dma_prefetch; | |
6179 | ||
6180 | if (h->board_id != 0x3225103C) | |
6181 | return; | |
6182 | dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG); | |
6183 | dma_prefetch |= 0x8000; | |
6184 | writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG); | |
6185 | } | |
6186 | ||
76438d08 SC |
6187 | static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h) |
6188 | { | |
6189 | int i; | |
6190 | u32 doorbell_value; | |
6191 | unsigned long flags; | |
6192 | /* wait until the clear_event_notify bit 6 is cleared by controller. */ | |
6193 | for (i = 0; i < MAX_CONFIG_WAIT; i++) { | |
6194 | spin_lock_irqsave(&h->lock, flags); | |
6195 | doorbell_value = readl(h->vaddr + SA5_DOORBELL); | |
6196 | spin_unlock_irqrestore(&h->lock, flags); | |
6197 | if (!(doorbell_value & DOORBELL_CLEAR_EVENTS)) | |
6198 | break; | |
6199 | /* delay and try again */ | |
6200 | msleep(20); | |
6201 | } | |
6202 | } | |
6203 | ||
6f039790 | 6204 | static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h) |
eb6b2ae9 SC |
6205 | { |
6206 | int i; | |
6eaf46fd SC |
6207 | u32 doorbell_value; |
6208 | unsigned long flags; | |
eb6b2ae9 SC |
6209 | |
6210 | /* under certain very rare conditions, this can take awhile. | |
6211 | * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right | |
6212 | * as we enter this code.) | |
6213 | */ | |
6214 | for (i = 0; i < MAX_CONFIG_WAIT; i++) { | |
6eaf46fd SC |
6215 | spin_lock_irqsave(&h->lock, flags); |
6216 | doorbell_value = readl(h->vaddr + SA5_DOORBELL); | |
6217 | spin_unlock_irqrestore(&h->lock, flags); | |
382be668 | 6218 | if (!(doorbell_value & CFGTBL_ChangeReq)) |
eb6b2ae9 SC |
6219 | break; |
6220 | /* delay and try again */ | |
60d3f5b0 | 6221 | usleep_range(10000, 20000); |
eb6b2ae9 | 6222 | } |
3f4336f3 SC |
6223 | } |
6224 | ||
6f039790 | 6225 | static int hpsa_enter_simple_mode(struct ctlr_info *h) |
3f4336f3 SC |
6226 | { |
6227 | u32 trans_support; | |
6228 | ||
6229 | trans_support = readl(&(h->cfgtable->TransportSupport)); | |
6230 | if (!(trans_support & SIMPLE_MODE)) | |
6231 | return -ENOTSUPP; | |
6232 | ||
6233 | h->max_commands = readl(&(h->cfgtable->CmdsOutMax)); | |
283b4a9b | 6234 | |
3f4336f3 SC |
6235 | /* Update the field, and then ring the doorbell */ |
6236 | writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest)); | |
b9af4937 | 6237 | writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); |
3f4336f3 SC |
6238 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
6239 | hpsa_wait_for_mode_change_ack(h); | |
eb6b2ae9 | 6240 | print_cfg_table(&h->pdev->dev, h->cfgtable); |
283b4a9b SC |
6241 | if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple)) |
6242 | goto error; | |
960a30e7 | 6243 | h->transMethod = CFGTBL_Trans_Simple; |
eb6b2ae9 | 6244 | return 0; |
283b4a9b | 6245 | error: |
050f7147 | 6246 | dev_err(&h->pdev->dev, "failed to enter simple mode\n"); |
283b4a9b | 6247 | return -ENODEV; |
eb6b2ae9 SC |
6248 | } |
6249 | ||
6f039790 | 6250 | static int hpsa_pci_init(struct ctlr_info *h) |
77c4495c | 6251 | { |
eb6b2ae9 | 6252 | int prod_index, err; |
edd16368 | 6253 | |
e5c880d1 SC |
6254 | prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id); |
6255 | if (prod_index < 0) | |
60f923b9 | 6256 | return prod_index; |
e5c880d1 SC |
6257 | h->product_name = products[prod_index].product_name; |
6258 | h->access = *(products[prod_index].access); | |
edd16368 | 6259 | |
e5a44df8 MG |
6260 | pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S | |
6261 | PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM); | |
6262 | ||
55c06c71 | 6263 | err = pci_enable_device(h->pdev); |
edd16368 | 6264 | if (err) { |
55c06c71 | 6265 | dev_warn(&h->pdev->dev, "unable to enable PCI device\n"); |
edd16368 SC |
6266 | return err; |
6267 | } | |
6268 | ||
f79cfec6 | 6269 | err = pci_request_regions(h->pdev, HPSA); |
edd16368 | 6270 | if (err) { |
55c06c71 SC |
6271 | dev_err(&h->pdev->dev, |
6272 | "cannot obtain PCI resources, aborting\n"); | |
edd16368 SC |
6273 | return err; |
6274 | } | |
4fa604e1 RE |
6275 | |
6276 | pci_set_master(h->pdev); | |
6277 | ||
6b3f4c52 | 6278 | hpsa_interrupt_mode(h); |
12d2cd47 | 6279 | err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr); |
3a7774ce | 6280 | if (err) |
edd16368 | 6281 | goto err_out_free_res; |
edd16368 | 6282 | h->vaddr = remap_pci_mem(h->paddr, 0x250); |
204892e9 SC |
6283 | if (!h->vaddr) { |
6284 | err = -ENOMEM; | |
6285 | goto err_out_free_res; | |
6286 | } | |
fe5389c8 | 6287 | err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY); |
2c4c8c8b | 6288 | if (err) |
edd16368 | 6289 | goto err_out_free_res; |
77c4495c SC |
6290 | err = hpsa_find_cfgtables(h); |
6291 | if (err) | |
edd16368 | 6292 | goto err_out_free_res; |
b93d7536 | 6293 | hpsa_find_board_params(h); |
edd16368 | 6294 | |
76c46e49 | 6295 | if (!hpsa_CISS_signature_present(h)) { |
edd16368 SC |
6296 | err = -ENODEV; |
6297 | goto err_out_free_res; | |
6298 | } | |
97a5e98c | 6299 | hpsa_set_driver_support_bits(h); |
3d0eab67 | 6300 | hpsa_p600_dma_prefetch_quirk(h); |
eb6b2ae9 SC |
6301 | err = hpsa_enter_simple_mode(h); |
6302 | if (err) | |
edd16368 | 6303 | goto err_out_free_res; |
edd16368 SC |
6304 | return 0; |
6305 | ||
6306 | err_out_free_res: | |
204892e9 SC |
6307 | if (h->transtable) |
6308 | iounmap(h->transtable); | |
6309 | if (h->cfgtable) | |
6310 | iounmap(h->cfgtable); | |
6311 | if (h->vaddr) | |
6312 | iounmap(h->vaddr); | |
f0bd0b68 | 6313 | pci_disable_device(h->pdev); |
55c06c71 | 6314 | pci_release_regions(h->pdev); |
edd16368 SC |
6315 | return err; |
6316 | } | |
6317 | ||
6f039790 | 6318 | static void hpsa_hba_inquiry(struct ctlr_info *h) |
339b2b14 SC |
6319 | { |
6320 | int rc; | |
6321 | ||
6322 | #define HBA_INQUIRY_BYTE_COUNT 64 | |
6323 | h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL); | |
6324 | if (!h->hba_inquiry_data) | |
6325 | return; | |
6326 | rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0, | |
6327 | h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT); | |
6328 | if (rc != 0) { | |
6329 | kfree(h->hba_inquiry_data); | |
6330 | h->hba_inquiry_data = NULL; | |
6331 | } | |
6332 | } | |
6333 | ||
6f039790 | 6334 | static int hpsa_init_reset_devices(struct pci_dev *pdev) |
4c2a8c40 | 6335 | { |
1df8552a | 6336 | int rc, i; |
3b747298 | 6337 | void __iomem *vaddr; |
4c2a8c40 SC |
6338 | |
6339 | if (!reset_devices) | |
6340 | return 0; | |
6341 | ||
132aa220 TH |
6342 | /* kdump kernel is loading, we don't know in which state is |
6343 | * the pci interface. The dev->enable_cnt is equal zero | |
6344 | * so we call enable+disable, wait a while and switch it on. | |
6345 | */ | |
6346 | rc = pci_enable_device(pdev); | |
6347 | if (rc) { | |
6348 | dev_warn(&pdev->dev, "Failed to enable PCI device\n"); | |
6349 | return -ENODEV; | |
6350 | } | |
6351 | pci_disable_device(pdev); | |
6352 | msleep(260); /* a randomly chosen number */ | |
6353 | rc = pci_enable_device(pdev); | |
6354 | if (rc) { | |
6355 | dev_warn(&pdev->dev, "failed to enable device.\n"); | |
6356 | return -ENODEV; | |
6357 | } | |
4fa604e1 | 6358 | |
859c75ab | 6359 | pci_set_master(pdev); |
4fa604e1 | 6360 | |
3b747298 TH |
6361 | vaddr = pci_ioremap_bar(pdev, 0); |
6362 | if (vaddr == NULL) { | |
6363 | rc = -ENOMEM; | |
6364 | goto out_disable; | |
6365 | } | |
6366 | writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET); | |
6367 | iounmap(vaddr); | |
6368 | ||
1df8552a SC |
6369 | /* Reset the controller with a PCI power-cycle or via doorbell */ |
6370 | rc = hpsa_kdump_hard_reset_controller(pdev); | |
4c2a8c40 | 6371 | |
1df8552a SC |
6372 | /* -ENOTSUPP here means we cannot reset the controller |
6373 | * but it's already (and still) up and running in | |
18867659 SC |
6374 | * "performant mode". Or, it might be 640x, which can't reset |
6375 | * due to concerns about shared bbwc between 6402/6404 pair. | |
1df8552a | 6376 | */ |
adf1b3a3 | 6377 | if (rc) |
132aa220 | 6378 | goto out_disable; |
4c2a8c40 SC |
6379 | |
6380 | /* Now try to get the controller to respond to a no-op */ | |
1ba66c9c | 6381 | dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n"); |
4c2a8c40 SC |
6382 | for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) { |
6383 | if (hpsa_noop(pdev) == 0) | |
6384 | break; | |
6385 | else | |
6386 | dev_warn(&pdev->dev, "no-op failed%s\n", | |
6387 | (i < 11 ? "; re-trying" : "")); | |
6388 | } | |
132aa220 TH |
6389 | |
6390 | out_disable: | |
6391 | ||
6392 | pci_disable_device(pdev); | |
6393 | return rc; | |
4c2a8c40 SC |
6394 | } |
6395 | ||
6f039790 | 6396 | static int hpsa_allocate_cmd_pool(struct ctlr_info *h) |
2e9d1b36 SC |
6397 | { |
6398 | h->cmd_pool_bits = kzalloc( | |
6399 | DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) * | |
6400 | sizeof(unsigned long), GFP_KERNEL); | |
6401 | h->cmd_pool = pci_alloc_consistent(h->pdev, | |
6402 | h->nr_cmds * sizeof(*h->cmd_pool), | |
6403 | &(h->cmd_pool_dhandle)); | |
6404 | h->errinfo_pool = pci_alloc_consistent(h->pdev, | |
6405 | h->nr_cmds * sizeof(*h->errinfo_pool), | |
6406 | &(h->errinfo_pool_dhandle)); | |
6407 | if ((h->cmd_pool_bits == NULL) | |
6408 | || (h->cmd_pool == NULL) | |
6409 | || (h->errinfo_pool == NULL)) { | |
6410 | dev_err(&h->pdev->dev, "out of memory in %s", __func__); | |
2c143342 | 6411 | goto clean_up; |
2e9d1b36 SC |
6412 | } |
6413 | return 0; | |
2c143342 RE |
6414 | clean_up: |
6415 | hpsa_free_cmd_pool(h); | |
6416 | return -ENOMEM; | |
2e9d1b36 SC |
6417 | } |
6418 | ||
6419 | static void hpsa_free_cmd_pool(struct ctlr_info *h) | |
6420 | { | |
6421 | kfree(h->cmd_pool_bits); | |
6422 | if (h->cmd_pool) | |
6423 | pci_free_consistent(h->pdev, | |
6424 | h->nr_cmds * sizeof(struct CommandList), | |
6425 | h->cmd_pool, h->cmd_pool_dhandle); | |
aca9012a SC |
6426 | if (h->ioaccel2_cmd_pool) |
6427 | pci_free_consistent(h->pdev, | |
6428 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), | |
6429 | h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle); | |
2e9d1b36 SC |
6430 | if (h->errinfo_pool) |
6431 | pci_free_consistent(h->pdev, | |
6432 | h->nr_cmds * sizeof(struct ErrorInfo), | |
6433 | h->errinfo_pool, | |
6434 | h->errinfo_pool_dhandle); | |
e1f7de0c MG |
6435 | if (h->ioaccel_cmd_pool) |
6436 | pci_free_consistent(h->pdev, | |
6437 | h->nr_cmds * sizeof(struct io_accel1_cmd), | |
6438 | h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle); | |
2e9d1b36 SC |
6439 | } |
6440 | ||
41b3cf08 SC |
6441 | static void hpsa_irq_affinity_hints(struct ctlr_info *h) |
6442 | { | |
ec429952 | 6443 | int i, cpu; |
41b3cf08 SC |
6444 | |
6445 | cpu = cpumask_first(cpu_online_mask); | |
6446 | for (i = 0; i < h->msix_vector; i++) { | |
ec429952 | 6447 | irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu)); |
41b3cf08 SC |
6448 | cpu = cpumask_next(cpu, cpu_online_mask); |
6449 | } | |
6450 | } | |
6451 | ||
ec501a18 RE |
6452 | /* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */ |
6453 | static void hpsa_free_irqs(struct ctlr_info *h) | |
6454 | { | |
6455 | int i; | |
6456 | ||
6457 | if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) { | |
6458 | /* Single reply queue, only one irq to free */ | |
6459 | i = h->intr_mode; | |
6460 | irq_set_affinity_hint(h->intr[i], NULL); | |
6461 | free_irq(h->intr[i], &h->q[i]); | |
6462 | return; | |
6463 | } | |
6464 | ||
6465 | for (i = 0; i < h->msix_vector; i++) { | |
6466 | irq_set_affinity_hint(h->intr[i], NULL); | |
6467 | free_irq(h->intr[i], &h->q[i]); | |
6468 | } | |
a4e17fc1 RE |
6469 | for (; i < MAX_REPLY_QUEUES; i++) |
6470 | h->q[i] = 0; | |
ec501a18 RE |
6471 | } |
6472 | ||
9ee61794 RE |
6473 | /* returns 0 on success; cleans up and returns -Enn on error */ |
6474 | static int hpsa_request_irqs(struct ctlr_info *h, | |
0ae01a32 SC |
6475 | irqreturn_t (*msixhandler)(int, void *), |
6476 | irqreturn_t (*intxhandler)(int, void *)) | |
6477 | { | |
254f796b | 6478 | int rc, i; |
0ae01a32 | 6479 | |
254f796b MG |
6480 | /* |
6481 | * initialize h->q[x] = x so that interrupt handlers know which | |
6482 | * queue to process. | |
6483 | */ | |
6484 | for (i = 0; i < MAX_REPLY_QUEUES; i++) | |
6485 | h->q[i] = (u8) i; | |
6486 | ||
eee0f03a | 6487 | if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) { |
254f796b | 6488 | /* If performant mode and MSI-X, use multiple reply queues */ |
a4e17fc1 | 6489 | for (i = 0; i < h->msix_vector; i++) { |
254f796b MG |
6490 | rc = request_irq(h->intr[i], msixhandler, |
6491 | 0, h->devname, | |
6492 | &h->q[i]); | |
a4e17fc1 RE |
6493 | if (rc) { |
6494 | int j; | |
6495 | ||
6496 | dev_err(&h->pdev->dev, | |
6497 | "failed to get irq %d for %s\n", | |
6498 | h->intr[i], h->devname); | |
6499 | for (j = 0; j < i; j++) { | |
6500 | free_irq(h->intr[j], &h->q[j]); | |
6501 | h->q[j] = 0; | |
6502 | } | |
6503 | for (; j < MAX_REPLY_QUEUES; j++) | |
6504 | h->q[j] = 0; | |
6505 | return rc; | |
6506 | } | |
6507 | } | |
41b3cf08 | 6508 | hpsa_irq_affinity_hints(h); |
254f796b MG |
6509 | } else { |
6510 | /* Use single reply pool */ | |
eee0f03a | 6511 | if (h->msix_vector > 0 || h->msi_vector) { |
254f796b MG |
6512 | rc = request_irq(h->intr[h->intr_mode], |
6513 | msixhandler, 0, h->devname, | |
6514 | &h->q[h->intr_mode]); | |
6515 | } else { | |
6516 | rc = request_irq(h->intr[h->intr_mode], | |
6517 | intxhandler, IRQF_SHARED, h->devname, | |
6518 | &h->q[h->intr_mode]); | |
6519 | } | |
6520 | } | |
0ae01a32 SC |
6521 | if (rc) { |
6522 | dev_err(&h->pdev->dev, "unable to get irq %d for %s\n", | |
6523 | h->intr[h->intr_mode], h->devname); | |
6524 | return -ENODEV; | |
6525 | } | |
6526 | return 0; | |
6527 | } | |
6528 | ||
6f039790 | 6529 | static int hpsa_kdump_soft_reset(struct ctlr_info *h) |
64670ac8 SC |
6530 | { |
6531 | if (hpsa_send_host_reset(h, RAID_CTLR_LUNID, | |
6532 | HPSA_RESET_TYPE_CONTROLLER)) { | |
6533 | dev_warn(&h->pdev->dev, "Resetting array controller failed.\n"); | |
6534 | return -EIO; | |
6535 | } | |
6536 | ||
6537 | dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n"); | |
6538 | if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) { | |
6539 | dev_warn(&h->pdev->dev, "Soft reset had no effect.\n"); | |
6540 | return -1; | |
6541 | } | |
6542 | ||
6543 | dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n"); | |
6544 | if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) { | |
6545 | dev_warn(&h->pdev->dev, "Board failed to become ready " | |
6546 | "after soft reset.\n"); | |
6547 | return -1; | |
6548 | } | |
6549 | ||
6550 | return 0; | |
6551 | } | |
6552 | ||
0097f0f4 | 6553 | static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h) |
64670ac8 | 6554 | { |
ec501a18 | 6555 | hpsa_free_irqs(h); |
64670ac8 | 6556 | #ifdef CONFIG_PCI_MSI |
0097f0f4 SC |
6557 | if (h->msix_vector) { |
6558 | if (h->pdev->msix_enabled) | |
6559 | pci_disable_msix(h->pdev); | |
6560 | } else if (h->msi_vector) { | |
6561 | if (h->pdev->msi_enabled) | |
6562 | pci_disable_msi(h->pdev); | |
6563 | } | |
64670ac8 | 6564 | #endif /* CONFIG_PCI_MSI */ |
0097f0f4 SC |
6565 | } |
6566 | ||
072b0518 SC |
6567 | static void hpsa_free_reply_queues(struct ctlr_info *h) |
6568 | { | |
6569 | int i; | |
6570 | ||
6571 | for (i = 0; i < h->nreply_queues; i++) { | |
6572 | if (!h->reply_queue[i].head) | |
6573 | continue; | |
6574 | pci_free_consistent(h->pdev, h->reply_queue_size, | |
6575 | h->reply_queue[i].head, h->reply_queue[i].busaddr); | |
6576 | h->reply_queue[i].head = NULL; | |
6577 | h->reply_queue[i].busaddr = 0; | |
6578 | } | |
6579 | } | |
6580 | ||
0097f0f4 SC |
6581 | static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h) |
6582 | { | |
6583 | hpsa_free_irqs_and_disable_msix(h); | |
64670ac8 SC |
6584 | hpsa_free_sg_chain_blocks(h); |
6585 | hpsa_free_cmd_pool(h); | |
e1f7de0c | 6586 | kfree(h->ioaccel1_blockFetchTable); |
64670ac8 | 6587 | kfree(h->blockFetchTable); |
072b0518 | 6588 | hpsa_free_reply_queues(h); |
64670ac8 SC |
6589 | if (h->vaddr) |
6590 | iounmap(h->vaddr); | |
6591 | if (h->transtable) | |
6592 | iounmap(h->transtable); | |
6593 | if (h->cfgtable) | |
6594 | iounmap(h->cfgtable); | |
132aa220 | 6595 | pci_disable_device(h->pdev); |
64670ac8 SC |
6596 | pci_release_regions(h->pdev); |
6597 | kfree(h); | |
6598 | } | |
6599 | ||
a0c12413 | 6600 | /* Called when controller lockup detected. */ |
f2405db8 | 6601 | static void fail_all_outstanding_cmds(struct ctlr_info *h) |
a0c12413 | 6602 | { |
281a7fd0 WS |
6603 | int i, refcount; |
6604 | struct CommandList *c; | |
a0c12413 | 6605 | |
080ef1cc | 6606 | flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */ |
f2405db8 | 6607 | for (i = 0; i < h->nr_cmds; i++) { |
f2405db8 | 6608 | c = h->cmd_pool + i; |
281a7fd0 WS |
6609 | refcount = atomic_inc_return(&c->refcount); |
6610 | if (refcount > 1) { | |
6611 | c->err_info->CommandStatus = CMD_HARDWARE_ERR; | |
6612 | finish_cmd(c); | |
6613 | } | |
6614 | cmd_free(h, c); | |
a0c12413 SC |
6615 | } |
6616 | } | |
6617 | ||
094963da SC |
6618 | static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value) |
6619 | { | |
6620 | int i, cpu; | |
6621 | ||
6622 | cpu = cpumask_first(cpu_online_mask); | |
6623 | for (i = 0; i < num_online_cpus(); i++) { | |
6624 | u32 *lockup_detected; | |
6625 | lockup_detected = per_cpu_ptr(h->lockup_detected, cpu); | |
6626 | *lockup_detected = value; | |
6627 | cpu = cpumask_next(cpu, cpu_online_mask); | |
6628 | } | |
6629 | wmb(); /* be sure the per-cpu variables are out to memory */ | |
6630 | } | |
6631 | ||
a0c12413 SC |
6632 | static void controller_lockup_detected(struct ctlr_info *h) |
6633 | { | |
6634 | unsigned long flags; | |
094963da | 6635 | u32 lockup_detected; |
a0c12413 | 6636 | |
a0c12413 SC |
6637 | h->access.set_intr_mask(h, HPSA_INTR_OFF); |
6638 | spin_lock_irqsave(&h->lock, flags); | |
094963da SC |
6639 | lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET); |
6640 | if (!lockup_detected) { | |
6641 | /* no heartbeat, but controller gave us a zero. */ | |
6642 | dev_warn(&h->pdev->dev, | |
6643 | "lockup detected but scratchpad register is zero\n"); | |
6644 | lockup_detected = 0xffffffff; | |
6645 | } | |
6646 | set_lockup_detected_for_all_cpus(h, lockup_detected); | |
a0c12413 SC |
6647 | spin_unlock_irqrestore(&h->lock, flags); |
6648 | dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n", | |
094963da | 6649 | lockup_detected); |
a0c12413 | 6650 | pci_disable_device(h->pdev); |
f2405db8 | 6651 | fail_all_outstanding_cmds(h); |
a0c12413 SC |
6652 | } |
6653 | ||
a0c12413 SC |
6654 | static void detect_controller_lockup(struct ctlr_info *h) |
6655 | { | |
6656 | u64 now; | |
6657 | u32 heartbeat; | |
6658 | unsigned long flags; | |
6659 | ||
a0c12413 SC |
6660 | now = get_jiffies_64(); |
6661 | /* If we've received an interrupt recently, we're ok. */ | |
6662 | if (time_after64(h->last_intr_timestamp + | |
e85c5974 | 6663 | (h->heartbeat_sample_interval), now)) |
a0c12413 SC |
6664 | return; |
6665 | ||
6666 | /* | |
6667 | * If we've already checked the heartbeat recently, we're ok. | |
6668 | * This could happen if someone sends us a signal. We | |
6669 | * otherwise don't care about signals in this thread. | |
6670 | */ | |
6671 | if (time_after64(h->last_heartbeat_timestamp + | |
e85c5974 | 6672 | (h->heartbeat_sample_interval), now)) |
a0c12413 SC |
6673 | return; |
6674 | ||
6675 | /* If heartbeat has not changed since we last looked, we're not ok. */ | |
6676 | spin_lock_irqsave(&h->lock, flags); | |
6677 | heartbeat = readl(&h->cfgtable->HeartBeat); | |
6678 | spin_unlock_irqrestore(&h->lock, flags); | |
6679 | if (h->last_heartbeat == heartbeat) { | |
6680 | controller_lockup_detected(h); | |
6681 | return; | |
6682 | } | |
6683 | ||
6684 | /* We're ok. */ | |
6685 | h->last_heartbeat = heartbeat; | |
6686 | h->last_heartbeat_timestamp = now; | |
6687 | } | |
6688 | ||
9846590e | 6689 | static void hpsa_ack_ctlr_events(struct ctlr_info *h) |
76438d08 SC |
6690 | { |
6691 | int i; | |
6692 | char *event_type; | |
6693 | ||
e4aa3e6a SC |
6694 | if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) |
6695 | return; | |
6696 | ||
76438d08 | 6697 | /* Ask the controller to clear the events we're handling. */ |
1f7cee8c SC |
6698 | if ((h->transMethod & (CFGTBL_Trans_io_accel1 |
6699 | | CFGTBL_Trans_io_accel2)) && | |
76438d08 SC |
6700 | (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE || |
6701 | h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) { | |
6702 | ||
6703 | if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE) | |
6704 | event_type = "state change"; | |
6705 | if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE) | |
6706 | event_type = "configuration change"; | |
6707 | /* Stop sending new RAID offload reqs via the IO accelerator */ | |
6708 | scsi_block_requests(h->scsi_host); | |
6709 | for (i = 0; i < h->ndevices; i++) | |
6710 | h->dev[i]->offload_enabled = 0; | |
23100dd9 | 6711 | hpsa_drain_accel_commands(h); |
76438d08 SC |
6712 | /* Set 'accelerator path config change' bit */ |
6713 | dev_warn(&h->pdev->dev, | |
6714 | "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n", | |
6715 | h->events, event_type); | |
6716 | writel(h->events, &(h->cfgtable->clear_event_notify)); | |
6717 | /* Set the "clear event notify field update" bit 6 */ | |
6718 | writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); | |
6719 | /* Wait until ctlr clears 'clear event notify field', bit 6 */ | |
6720 | hpsa_wait_for_clear_event_notify_ack(h); | |
6721 | scsi_unblock_requests(h->scsi_host); | |
6722 | } else { | |
6723 | /* Acknowledge controller notification events. */ | |
6724 | writel(h->events, &(h->cfgtable->clear_event_notify)); | |
6725 | writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL); | |
6726 | hpsa_wait_for_clear_event_notify_ack(h); | |
6727 | #if 0 | |
6728 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); | |
6729 | hpsa_wait_for_mode_change_ack(h); | |
6730 | #endif | |
6731 | } | |
9846590e | 6732 | return; |
76438d08 SC |
6733 | } |
6734 | ||
6735 | /* Check a register on the controller to see if there are configuration | |
6736 | * changes (added/changed/removed logical drives, etc.) which mean that | |
e863d68e ST |
6737 | * we should rescan the controller for devices. |
6738 | * Also check flag for driver-initiated rescan. | |
76438d08 | 6739 | */ |
9846590e | 6740 | static int hpsa_ctlr_needs_rescan(struct ctlr_info *h) |
76438d08 SC |
6741 | { |
6742 | if (!(h->fw_support & MISC_FW_EVENT_NOTIFY)) | |
9846590e | 6743 | return 0; |
76438d08 SC |
6744 | |
6745 | h->events = readl(&(h->cfgtable->event_notify)); | |
9846590e SC |
6746 | return h->events & RESCAN_REQUIRED_EVENT_BITS; |
6747 | } | |
76438d08 | 6748 | |
9846590e SC |
6749 | /* |
6750 | * Check if any of the offline devices have become ready | |
6751 | */ | |
6752 | static int hpsa_offline_devices_ready(struct ctlr_info *h) | |
6753 | { | |
6754 | unsigned long flags; | |
6755 | struct offline_device_entry *d; | |
6756 | struct list_head *this, *tmp; | |
6757 | ||
6758 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
6759 | list_for_each_safe(this, tmp, &h->offline_device_list) { | |
6760 | d = list_entry(this, struct offline_device_entry, | |
6761 | offline_list); | |
6762 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
d1fea47c SC |
6763 | if (!hpsa_volume_offline(h, d->scsi3addr)) { |
6764 | spin_lock_irqsave(&h->offline_device_lock, flags); | |
6765 | list_del(&d->offline_list); | |
6766 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
9846590e | 6767 | return 1; |
d1fea47c | 6768 | } |
9846590e SC |
6769 | spin_lock_irqsave(&h->offline_device_lock, flags); |
6770 | } | |
6771 | spin_unlock_irqrestore(&h->offline_device_lock, flags); | |
6772 | return 0; | |
76438d08 SC |
6773 | } |
6774 | ||
9846590e | 6775 | |
8a98db73 | 6776 | static void hpsa_monitor_ctlr_worker(struct work_struct *work) |
a0c12413 SC |
6777 | { |
6778 | unsigned long flags; | |
8a98db73 SC |
6779 | struct ctlr_info *h = container_of(to_delayed_work(work), |
6780 | struct ctlr_info, monitor_ctlr_work); | |
6781 | detect_controller_lockup(h); | |
094963da | 6782 | if (lockup_detected(h)) |
8a98db73 | 6783 | return; |
9846590e SC |
6784 | |
6785 | if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) { | |
6786 | scsi_host_get(h->scsi_host); | |
9846590e SC |
6787 | hpsa_ack_ctlr_events(h); |
6788 | hpsa_scan_start(h->scsi_host); | |
6789 | scsi_host_put(h->scsi_host); | |
6790 | } | |
6791 | ||
8a98db73 SC |
6792 | spin_lock_irqsave(&h->lock, flags); |
6793 | if (h->remove_in_progress) { | |
6794 | spin_unlock_irqrestore(&h->lock, flags); | |
a0c12413 SC |
6795 | return; |
6796 | } | |
8a98db73 SC |
6797 | schedule_delayed_work(&h->monitor_ctlr_work, |
6798 | h->heartbeat_sample_interval); | |
6799 | spin_unlock_irqrestore(&h->lock, flags); | |
a0c12413 SC |
6800 | } |
6801 | ||
6f039790 | 6802 | static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
edd16368 | 6803 | { |
4c2a8c40 | 6804 | int dac, rc; |
edd16368 | 6805 | struct ctlr_info *h; |
64670ac8 SC |
6806 | int try_soft_reset = 0; |
6807 | unsigned long flags; | |
edd16368 SC |
6808 | |
6809 | if (number_of_controllers == 0) | |
6810 | printk(KERN_INFO DRIVER_NAME "\n"); | |
edd16368 | 6811 | |
4c2a8c40 | 6812 | rc = hpsa_init_reset_devices(pdev); |
64670ac8 SC |
6813 | if (rc) { |
6814 | if (rc != -ENOTSUPP) | |
6815 | return rc; | |
6816 | /* If the reset fails in a particular way (it has no way to do | |
6817 | * a proper hard reset, so returns -ENOTSUPP) we can try to do | |
6818 | * a soft reset once we get the controller configured up to the | |
6819 | * point that it can accept a command. | |
6820 | */ | |
6821 | try_soft_reset = 1; | |
6822 | rc = 0; | |
6823 | } | |
6824 | ||
6825 | reinit_after_soft_reset: | |
edd16368 | 6826 | |
303932fd DB |
6827 | /* Command structures must be aligned on a 32-byte boundary because |
6828 | * the 5 lower bits of the address are used by the hardware. and by | |
6829 | * the driver. See comments in hpsa.h for more info. | |
6830 | */ | |
303932fd | 6831 | BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT); |
edd16368 SC |
6832 | h = kzalloc(sizeof(*h), GFP_KERNEL); |
6833 | if (!h) | |
ecd9aad4 | 6834 | return -ENOMEM; |
edd16368 | 6835 | |
55c06c71 | 6836 | h->pdev = pdev; |
a9a3a273 | 6837 | h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT; |
9846590e | 6838 | INIT_LIST_HEAD(&h->offline_device_list); |
6eaf46fd | 6839 | spin_lock_init(&h->lock); |
9846590e | 6840 | spin_lock_init(&h->offline_device_lock); |
6eaf46fd | 6841 | spin_lock_init(&h->scan_lock); |
34f0c627 | 6842 | atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS); |
094963da | 6843 | |
080ef1cc DB |
6844 | h->resubmit_wq = alloc_workqueue("hpsa", WQ_MEM_RECLAIM, 0); |
6845 | if (!h->resubmit_wq) { | |
6846 | dev_err(&h->pdev->dev, "Failed to allocate work queue\n"); | |
6847 | rc = -ENOMEM; | |
6848 | goto clean1; | |
6849 | } | |
094963da SC |
6850 | /* Allocate and clear per-cpu variable lockup_detected */ |
6851 | h->lockup_detected = alloc_percpu(u32); | |
2a5ac326 SC |
6852 | if (!h->lockup_detected) { |
6853 | rc = -ENOMEM; | |
094963da | 6854 | goto clean1; |
2a5ac326 | 6855 | } |
094963da SC |
6856 | set_lockup_detected_for_all_cpus(h, 0); |
6857 | ||
55c06c71 | 6858 | rc = hpsa_pci_init(h); |
ecd9aad4 | 6859 | if (rc != 0) |
edd16368 SC |
6860 | goto clean1; |
6861 | ||
f79cfec6 | 6862 | sprintf(h->devname, HPSA "%d", number_of_controllers); |
edd16368 SC |
6863 | h->ctlr = number_of_controllers; |
6864 | number_of_controllers++; | |
edd16368 SC |
6865 | |
6866 | /* configure PCI DMA stuff */ | |
ecd9aad4 SC |
6867 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64)); |
6868 | if (rc == 0) { | |
edd16368 | 6869 | dac = 1; |
ecd9aad4 SC |
6870 | } else { |
6871 | rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32)); | |
6872 | if (rc == 0) { | |
6873 | dac = 0; | |
6874 | } else { | |
6875 | dev_err(&pdev->dev, "no suitable DMA available\n"); | |
6876 | goto clean1; | |
6877 | } | |
edd16368 SC |
6878 | } |
6879 | ||
6880 | /* make sure the board interrupts are off */ | |
6881 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
10f66018 | 6882 | |
9ee61794 | 6883 | if (hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx)) |
edd16368 | 6884 | goto clean2; |
303932fd DB |
6885 | dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n", |
6886 | h->devname, pdev->device, | |
a9a3a273 | 6887 | h->intr[h->intr_mode], dac ? "" : " not"); |
8947fd10 RE |
6888 | rc = hpsa_allocate_cmd_pool(h); |
6889 | if (rc) | |
6890 | goto clean2_and_free_irqs; | |
33a2ffce SC |
6891 | if (hpsa_allocate_sg_chain_blocks(h)) |
6892 | goto clean4; | |
a08a8471 SC |
6893 | init_waitqueue_head(&h->scan_wait_queue); |
6894 | h->scan_finished = 1; /* no scan currently in progress */ | |
edd16368 SC |
6895 | |
6896 | pci_set_drvdata(pdev, h); | |
9a41338e | 6897 | h->ndevices = 0; |
316b221a | 6898 | h->hba_mode_enabled = 0; |
9a41338e SC |
6899 | h->scsi_host = NULL; |
6900 | spin_lock_init(&h->devlock); | |
64670ac8 SC |
6901 | hpsa_put_ctlr_into_performant_mode(h); |
6902 | ||
6903 | /* At this point, the controller is ready to take commands. | |
6904 | * Now, if reset_devices and the hard reset didn't work, try | |
6905 | * the soft reset and see if that works. | |
6906 | */ | |
6907 | if (try_soft_reset) { | |
6908 | ||
6909 | /* This is kind of gross. We may or may not get a completion | |
6910 | * from the soft reset command, and if we do, then the value | |
6911 | * from the fifo may or may not be valid. So, we wait 10 secs | |
6912 | * after the reset throwing away any completions we get during | |
6913 | * that time. Unregister the interrupt handler and register | |
6914 | * fake ones to scoop up any residual completions. | |
6915 | */ | |
6916 | spin_lock_irqsave(&h->lock, flags); | |
6917 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
6918 | spin_unlock_irqrestore(&h->lock, flags); | |
ec501a18 | 6919 | hpsa_free_irqs(h); |
9ee61794 | 6920 | rc = hpsa_request_irqs(h, hpsa_msix_discard_completions, |
64670ac8 SC |
6921 | hpsa_intx_discard_completions); |
6922 | if (rc) { | |
9ee61794 RE |
6923 | dev_warn(&h->pdev->dev, |
6924 | "Failed to request_irq after soft reset.\n"); | |
64670ac8 SC |
6925 | goto clean4; |
6926 | } | |
6927 | ||
6928 | rc = hpsa_kdump_soft_reset(h); | |
6929 | if (rc) | |
6930 | /* Neither hard nor soft reset worked, we're hosed. */ | |
6931 | goto clean4; | |
6932 | ||
6933 | dev_info(&h->pdev->dev, "Board READY.\n"); | |
6934 | dev_info(&h->pdev->dev, | |
6935 | "Waiting for stale completions to drain.\n"); | |
6936 | h->access.set_intr_mask(h, HPSA_INTR_ON); | |
6937 | msleep(10000); | |
6938 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
6939 | ||
6940 | rc = controller_reset_failed(h->cfgtable); | |
6941 | if (rc) | |
6942 | dev_info(&h->pdev->dev, | |
6943 | "Soft reset appears to have failed.\n"); | |
6944 | ||
6945 | /* since the controller's reset, we have to go back and re-init | |
6946 | * everything. Easiest to just forget what we've done and do it | |
6947 | * all over again. | |
6948 | */ | |
6949 | hpsa_undo_allocations_after_kdump_soft_reset(h); | |
6950 | try_soft_reset = 0; | |
6951 | if (rc) | |
6952 | /* don't go to clean4, we already unallocated */ | |
6953 | return -ENODEV; | |
6954 | ||
6955 | goto reinit_after_soft_reset; | |
6956 | } | |
edd16368 | 6957 | |
316b221a SC |
6958 | /* Enable Accelerated IO path at driver layer */ |
6959 | h->acciopath_status = 1; | |
da0697bd | 6960 | |
e863d68e | 6961 | |
edd16368 SC |
6962 | /* Turn the interrupts on so we can service requests */ |
6963 | h->access.set_intr_mask(h, HPSA_INTR_ON); | |
6964 | ||
339b2b14 | 6965 | hpsa_hba_inquiry(h); |
edd16368 | 6966 | hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */ |
8a98db73 SC |
6967 | |
6968 | /* Monitor the controller for firmware lockups */ | |
6969 | h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL; | |
6970 | INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker); | |
6971 | schedule_delayed_work(&h->monitor_ctlr_work, | |
6972 | h->heartbeat_sample_interval); | |
88bf6d62 | 6973 | return 0; |
edd16368 SC |
6974 | |
6975 | clean4: | |
33a2ffce | 6976 | hpsa_free_sg_chain_blocks(h); |
2e9d1b36 | 6977 | hpsa_free_cmd_pool(h); |
8947fd10 | 6978 | clean2_and_free_irqs: |
ec501a18 | 6979 | hpsa_free_irqs(h); |
edd16368 SC |
6980 | clean2: |
6981 | clean1: | |
080ef1cc DB |
6982 | if (h->resubmit_wq) |
6983 | destroy_workqueue(h->resubmit_wq); | |
094963da SC |
6984 | if (h->lockup_detected) |
6985 | free_percpu(h->lockup_detected); | |
edd16368 | 6986 | kfree(h); |
ecd9aad4 | 6987 | return rc; |
edd16368 SC |
6988 | } |
6989 | ||
6990 | static void hpsa_flush_cache(struct ctlr_info *h) | |
6991 | { | |
6992 | char *flush_buf; | |
6993 | struct CommandList *c; | |
702890e3 SC |
6994 | |
6995 | /* Don't bother trying to flush the cache if locked up */ | |
094963da | 6996 | if (unlikely(lockup_detected(h))) |
702890e3 | 6997 | return; |
edd16368 SC |
6998 | flush_buf = kzalloc(4, GFP_KERNEL); |
6999 | if (!flush_buf) | |
7000 | return; | |
7001 | ||
45fcb86e | 7002 | c = cmd_alloc(h); |
edd16368 | 7003 | if (!c) { |
45fcb86e | 7004 | dev_warn(&h->pdev->dev, "cmd_alloc returned NULL!\n"); |
edd16368 SC |
7005 | goto out_of_memory; |
7006 | } | |
a2dac136 SC |
7007 | if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0, |
7008 | RAID_CTLR_LUNID, TYPE_CMD)) { | |
7009 | goto out; | |
7010 | } | |
edd16368 SC |
7011 | hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE); |
7012 | if (c->err_info->CommandStatus != 0) | |
a2dac136 | 7013 | out: |
edd16368 SC |
7014 | dev_warn(&h->pdev->dev, |
7015 | "error flushing cache on controller\n"); | |
45fcb86e | 7016 | cmd_free(h, c); |
edd16368 SC |
7017 | out_of_memory: |
7018 | kfree(flush_buf); | |
7019 | } | |
7020 | ||
7021 | static void hpsa_shutdown(struct pci_dev *pdev) | |
7022 | { | |
7023 | struct ctlr_info *h; | |
7024 | ||
7025 | h = pci_get_drvdata(pdev); | |
7026 | /* Turn board interrupts off and send the flush cache command | |
7027 | * sendcmd will turn off interrupt, and send the flush... | |
7028 | * To write all data in the battery backed cache to disks | |
7029 | */ | |
7030 | hpsa_flush_cache(h); | |
7031 | h->access.set_intr_mask(h, HPSA_INTR_OFF); | |
0097f0f4 | 7032 | hpsa_free_irqs_and_disable_msix(h); |
edd16368 SC |
7033 | } |
7034 | ||
6f039790 | 7035 | static void hpsa_free_device_info(struct ctlr_info *h) |
55e14e76 SC |
7036 | { |
7037 | int i; | |
7038 | ||
7039 | for (i = 0; i < h->ndevices; i++) | |
7040 | kfree(h->dev[i]); | |
7041 | } | |
7042 | ||
6f039790 | 7043 | static void hpsa_remove_one(struct pci_dev *pdev) |
edd16368 SC |
7044 | { |
7045 | struct ctlr_info *h; | |
8a98db73 | 7046 | unsigned long flags; |
edd16368 SC |
7047 | |
7048 | if (pci_get_drvdata(pdev) == NULL) { | |
a0c12413 | 7049 | dev_err(&pdev->dev, "unable to remove device\n"); |
edd16368 SC |
7050 | return; |
7051 | } | |
7052 | h = pci_get_drvdata(pdev); | |
8a98db73 SC |
7053 | |
7054 | /* Get rid of any controller monitoring work items */ | |
7055 | spin_lock_irqsave(&h->lock, flags); | |
7056 | h->remove_in_progress = 1; | |
7057 | cancel_delayed_work(&h->monitor_ctlr_work); | |
7058 | spin_unlock_irqrestore(&h->lock, flags); | |
edd16368 SC |
7059 | hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */ |
7060 | hpsa_shutdown(pdev); | |
080ef1cc | 7061 | destroy_workqueue(h->resubmit_wq); |
edd16368 | 7062 | iounmap(h->vaddr); |
204892e9 SC |
7063 | iounmap(h->transtable); |
7064 | iounmap(h->cfgtable); | |
55e14e76 | 7065 | hpsa_free_device_info(h); |
33a2ffce | 7066 | hpsa_free_sg_chain_blocks(h); |
edd16368 SC |
7067 | pci_free_consistent(h->pdev, |
7068 | h->nr_cmds * sizeof(struct CommandList), | |
7069 | h->cmd_pool, h->cmd_pool_dhandle); | |
7070 | pci_free_consistent(h->pdev, | |
7071 | h->nr_cmds * sizeof(struct ErrorInfo), | |
7072 | h->errinfo_pool, h->errinfo_pool_dhandle); | |
072b0518 | 7073 | hpsa_free_reply_queues(h); |
edd16368 | 7074 | kfree(h->cmd_pool_bits); |
303932fd | 7075 | kfree(h->blockFetchTable); |
e1f7de0c | 7076 | kfree(h->ioaccel1_blockFetchTable); |
aca9012a | 7077 | kfree(h->ioaccel2_blockFetchTable); |
339b2b14 | 7078 | kfree(h->hba_inquiry_data); |
f0bd0b68 | 7079 | pci_disable_device(pdev); |
edd16368 | 7080 | pci_release_regions(pdev); |
094963da | 7081 | free_percpu(h->lockup_detected); |
edd16368 SC |
7082 | kfree(h); |
7083 | } | |
7084 | ||
7085 | static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev, | |
7086 | __attribute__((unused)) pm_message_t state) | |
7087 | { | |
7088 | return -ENOSYS; | |
7089 | } | |
7090 | ||
7091 | static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev) | |
7092 | { | |
7093 | return -ENOSYS; | |
7094 | } | |
7095 | ||
7096 | static struct pci_driver hpsa_pci_driver = { | |
f79cfec6 | 7097 | .name = HPSA, |
edd16368 | 7098 | .probe = hpsa_init_one, |
6f039790 | 7099 | .remove = hpsa_remove_one, |
edd16368 SC |
7100 | .id_table = hpsa_pci_device_id, /* id_table */ |
7101 | .shutdown = hpsa_shutdown, | |
7102 | .suspend = hpsa_suspend, | |
7103 | .resume = hpsa_resume, | |
7104 | }; | |
7105 | ||
303932fd DB |
7106 | /* Fill in bucket_map[], given nsgs (the max number of |
7107 | * scatter gather elements supported) and bucket[], | |
7108 | * which is an array of 8 integers. The bucket[] array | |
7109 | * contains 8 different DMA transfer sizes (in 16 | |
7110 | * byte increments) which the controller uses to fetch | |
7111 | * commands. This function fills in bucket_map[], which | |
7112 | * maps a given number of scatter gather elements to one of | |
7113 | * the 8 DMA transfer sizes. The point of it is to allow the | |
7114 | * controller to only do as much DMA as needed to fetch the | |
7115 | * command, with the DMA transfer size encoded in the lower | |
7116 | * bits of the command address. | |
7117 | */ | |
7118 | static void calc_bucket_map(int bucket[], int num_buckets, | |
2b08b3e9 | 7119 | int nsgs, int min_blocks, u32 *bucket_map) |
303932fd DB |
7120 | { |
7121 | int i, j, b, size; | |
7122 | ||
303932fd DB |
7123 | /* Note, bucket_map must have nsgs+1 entries. */ |
7124 | for (i = 0; i <= nsgs; i++) { | |
7125 | /* Compute size of a command with i SG entries */ | |
e1f7de0c | 7126 | size = i + min_blocks; |
303932fd DB |
7127 | b = num_buckets; /* Assume the biggest bucket */ |
7128 | /* Find the bucket that is just big enough */ | |
e1f7de0c | 7129 | for (j = 0; j < num_buckets; j++) { |
303932fd DB |
7130 | if (bucket[j] >= size) { |
7131 | b = j; | |
7132 | break; | |
7133 | } | |
7134 | } | |
7135 | /* for a command with i SG entries, use bucket b. */ | |
7136 | bucket_map[i] = b; | |
7137 | } | |
7138 | } | |
7139 | ||
e1f7de0c | 7140 | static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support) |
303932fd | 7141 | { |
6c311b57 SC |
7142 | int i; |
7143 | unsigned long register_value; | |
e1f7de0c MG |
7144 | unsigned long transMethod = CFGTBL_Trans_Performant | |
7145 | (trans_support & CFGTBL_Trans_use_short_tags) | | |
b9af4937 SC |
7146 | CFGTBL_Trans_enable_directed_msix | |
7147 | (trans_support & (CFGTBL_Trans_io_accel1 | | |
7148 | CFGTBL_Trans_io_accel2)); | |
e1f7de0c | 7149 | struct access_method access = SA5_performant_access; |
def342bd SC |
7150 | |
7151 | /* This is a bit complicated. There are 8 registers on | |
7152 | * the controller which we write to to tell it 8 different | |
7153 | * sizes of commands which there may be. It's a way of | |
7154 | * reducing the DMA done to fetch each command. Encoded into | |
7155 | * each command's tag are 3 bits which communicate to the controller | |
7156 | * which of the eight sizes that command fits within. The size of | |
7157 | * each command depends on how many scatter gather entries there are. | |
7158 | * Each SG entry requires 16 bytes. The eight registers are programmed | |
7159 | * with the number of 16-byte blocks a command of that size requires. | |
7160 | * The smallest command possible requires 5 such 16 byte blocks. | |
d66ae08b | 7161 | * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte |
def342bd SC |
7162 | * blocks. Note, this only extends to the SG entries contained |
7163 | * within the command block, and does not extend to chained blocks | |
7164 | * of SG elements. bft[] contains the eight values we write to | |
7165 | * the registers. They are not evenly distributed, but have more | |
7166 | * sizes for small commands, and fewer sizes for larger commands. | |
7167 | */ | |
d66ae08b | 7168 | int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4}; |
b9af4937 SC |
7169 | #define MIN_IOACCEL2_BFT_ENTRY 5 |
7170 | #define HPSA_IOACCEL2_HEADER_SZ 4 | |
7171 | int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12, | |
7172 | 13, 14, 15, 16, 17, 18, 19, | |
7173 | HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES}; | |
7174 | BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16); | |
7175 | BUILD_BUG_ON(ARRAY_SIZE(bft) != 8); | |
7176 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) > | |
7177 | 16 * MIN_IOACCEL2_BFT_ENTRY); | |
7178 | BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16); | |
d66ae08b | 7179 | BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4); |
303932fd DB |
7180 | /* 5 = 1 s/g entry or 4k |
7181 | * 6 = 2 s/g entry or 8k | |
7182 | * 8 = 4 s/g entry or 16k | |
7183 | * 10 = 6 s/g entry or 24k | |
7184 | */ | |
303932fd | 7185 | |
b3a52e79 SC |
7186 | /* If the controller supports either ioaccel method then |
7187 | * we can also use the RAID stack submit path that does not | |
7188 | * perform the superfluous readl() after each command submission. | |
7189 | */ | |
7190 | if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2)) | |
7191 | access = SA5_performant_access_no_read; | |
7192 | ||
303932fd | 7193 | /* Controller spec: zero out this buffer. */ |
072b0518 SC |
7194 | for (i = 0; i < h->nreply_queues; i++) |
7195 | memset(h->reply_queue[i].head, 0, h->reply_queue_size); | |
303932fd | 7196 | |
d66ae08b SC |
7197 | bft[7] = SG_ENTRIES_IN_CMD + 4; |
7198 | calc_bucket_map(bft, ARRAY_SIZE(bft), | |
e1f7de0c | 7199 | SG_ENTRIES_IN_CMD, 4, h->blockFetchTable); |
303932fd DB |
7200 | for (i = 0; i < 8; i++) |
7201 | writel(bft[i], &h->transtable->BlockFetch[i]); | |
7202 | ||
7203 | /* size of controller ring buffer */ | |
7204 | writel(h->max_commands, &h->transtable->RepQSize); | |
254f796b | 7205 | writel(h->nreply_queues, &h->transtable->RepQCount); |
303932fd DB |
7206 | writel(0, &h->transtable->RepQCtrAddrLow32); |
7207 | writel(0, &h->transtable->RepQCtrAddrHigh32); | |
254f796b MG |
7208 | |
7209 | for (i = 0; i < h->nreply_queues; i++) { | |
7210 | writel(0, &h->transtable->RepQAddr[i].upper); | |
072b0518 | 7211 | writel(h->reply_queue[i].busaddr, |
254f796b MG |
7212 | &h->transtable->RepQAddr[i].lower); |
7213 | } | |
7214 | ||
b9af4937 | 7215 | writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi); |
e1f7de0c MG |
7216 | writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest)); |
7217 | /* | |
7218 | * enable outbound interrupt coalescing in accelerator mode; | |
7219 | */ | |
7220 | if (trans_support & CFGTBL_Trans_io_accel1) { | |
7221 | access = SA5_ioaccel_mode1_access; | |
7222 | writel(10, &h->cfgtable->HostWrite.CoalIntDelay); | |
7223 | writel(4, &h->cfgtable->HostWrite.CoalIntCount); | |
c349775e ST |
7224 | } else { |
7225 | if (trans_support & CFGTBL_Trans_io_accel2) { | |
7226 | access = SA5_ioaccel_mode2_access; | |
7227 | writel(10, &h->cfgtable->HostWrite.CoalIntDelay); | |
7228 | writel(4, &h->cfgtable->HostWrite.CoalIntCount); | |
7229 | } | |
e1f7de0c | 7230 | } |
303932fd | 7231 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
3f4336f3 | 7232 | hpsa_wait_for_mode_change_ack(h); |
303932fd DB |
7233 | register_value = readl(&(h->cfgtable->TransportActive)); |
7234 | if (!(register_value & CFGTBL_Trans_Performant)) { | |
050f7147 SC |
7235 | dev_err(&h->pdev->dev, |
7236 | "performant mode problem - transport not active\n"); | |
303932fd DB |
7237 | return; |
7238 | } | |
960a30e7 | 7239 | /* Change the access methods to the performant access methods */ |
e1f7de0c MG |
7240 | h->access = access; |
7241 | h->transMethod = transMethod; | |
7242 | ||
b9af4937 SC |
7243 | if (!((trans_support & CFGTBL_Trans_io_accel1) || |
7244 | (trans_support & CFGTBL_Trans_io_accel2))) | |
e1f7de0c MG |
7245 | return; |
7246 | ||
b9af4937 SC |
7247 | if (trans_support & CFGTBL_Trans_io_accel1) { |
7248 | /* Set up I/O accelerator mode */ | |
7249 | for (i = 0; i < h->nreply_queues; i++) { | |
7250 | writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX); | |
7251 | h->reply_queue[i].current_entry = | |
7252 | readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX); | |
7253 | } | |
7254 | bft[7] = h->ioaccel_maxsg + 8; | |
7255 | calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8, | |
7256 | h->ioaccel1_blockFetchTable); | |
e1f7de0c | 7257 | |
b9af4937 | 7258 | /* initialize all reply queue entries to unused */ |
072b0518 SC |
7259 | for (i = 0; i < h->nreply_queues; i++) |
7260 | memset(h->reply_queue[i].head, | |
7261 | (u8) IOACCEL_MODE1_REPLY_UNUSED, | |
7262 | h->reply_queue_size); | |
e1f7de0c | 7263 | |
b9af4937 SC |
7264 | /* set all the constant fields in the accelerator command |
7265 | * frames once at init time to save CPU cycles later. | |
7266 | */ | |
7267 | for (i = 0; i < h->nr_cmds; i++) { | |
7268 | struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i]; | |
7269 | ||
7270 | cp->function = IOACCEL1_FUNCTION_SCSIIO; | |
7271 | cp->err_info = (u32) (h->errinfo_pool_dhandle + | |
7272 | (i * sizeof(struct ErrorInfo))); | |
7273 | cp->err_info_len = sizeof(struct ErrorInfo); | |
7274 | cp->sgl_offset = IOACCEL1_SGLOFFSET; | |
2b08b3e9 DB |
7275 | cp->host_context_flags = |
7276 | cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT); | |
b9af4937 SC |
7277 | cp->timeout_sec = 0; |
7278 | cp->ReplyQueue = 0; | |
50a0decf | 7279 | cp->tag = |
f2405db8 | 7280 | cpu_to_le64((i << DIRECT_LOOKUP_SHIFT)); |
50a0decf SC |
7281 | cp->host_addr = |
7282 | cpu_to_le64(h->ioaccel_cmd_pool_dhandle + | |
b9af4937 | 7283 | (i * sizeof(struct io_accel1_cmd))); |
b9af4937 SC |
7284 | } |
7285 | } else if (trans_support & CFGTBL_Trans_io_accel2) { | |
7286 | u64 cfg_offset, cfg_base_addr_index; | |
7287 | u32 bft2_offset, cfg_base_addr; | |
7288 | int rc; | |
7289 | ||
7290 | rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr, | |
7291 | &cfg_base_addr_index, &cfg_offset); | |
7292 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64); | |
7293 | bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ; | |
7294 | calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg, | |
7295 | 4, h->ioaccel2_blockFetchTable); | |
7296 | bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset); | |
7297 | BUILD_BUG_ON(offsetof(struct CfgTable, | |
7298 | io_accel_request_size_offset) != 0xb8); | |
7299 | h->ioaccel2_bft2_regs = | |
7300 | remap_pci_mem(pci_resource_start(h->pdev, | |
7301 | cfg_base_addr_index) + | |
7302 | cfg_offset + bft2_offset, | |
7303 | ARRAY_SIZE(bft2) * | |
7304 | sizeof(*h->ioaccel2_bft2_regs)); | |
7305 | for (i = 0; i < ARRAY_SIZE(bft2); i++) | |
7306 | writel(bft2[i], &h->ioaccel2_bft2_regs[i]); | |
e1f7de0c | 7307 | } |
b9af4937 SC |
7308 | writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL); |
7309 | hpsa_wait_for_mode_change_ack(h); | |
e1f7de0c MG |
7310 | } |
7311 | ||
7312 | static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h) | |
7313 | { | |
283b4a9b SC |
7314 | h->ioaccel_maxsg = |
7315 | readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); | |
7316 | if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES) | |
7317 | h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES; | |
7318 | ||
e1f7de0c MG |
7319 | /* Command structures must be aligned on a 128-byte boundary |
7320 | * because the 7 lower bits of the address are used by the | |
7321 | * hardware. | |
7322 | */ | |
e1f7de0c MG |
7323 | BUILD_BUG_ON(sizeof(struct io_accel1_cmd) % |
7324 | IOACCEL1_COMMANDLIST_ALIGNMENT); | |
7325 | h->ioaccel_cmd_pool = | |
7326 | pci_alloc_consistent(h->pdev, | |
7327 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), | |
7328 | &(h->ioaccel_cmd_pool_dhandle)); | |
7329 | ||
7330 | h->ioaccel1_blockFetchTable = | |
283b4a9b | 7331 | kmalloc(((h->ioaccel_maxsg + 1) * |
e1f7de0c MG |
7332 | sizeof(u32)), GFP_KERNEL); |
7333 | ||
7334 | if ((h->ioaccel_cmd_pool == NULL) || | |
7335 | (h->ioaccel1_blockFetchTable == NULL)) | |
7336 | goto clean_up; | |
7337 | ||
7338 | memset(h->ioaccel_cmd_pool, 0, | |
7339 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool)); | |
7340 | return 0; | |
7341 | ||
7342 | clean_up: | |
7343 | if (h->ioaccel_cmd_pool) | |
7344 | pci_free_consistent(h->pdev, | |
7345 | h->nr_cmds * sizeof(*h->ioaccel_cmd_pool), | |
7346 | h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle); | |
7347 | kfree(h->ioaccel1_blockFetchTable); | |
7348 | return 1; | |
6c311b57 SC |
7349 | } |
7350 | ||
aca9012a SC |
7351 | static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h) |
7352 | { | |
7353 | /* Allocate ioaccel2 mode command blocks and block fetch table */ | |
7354 | ||
7355 | h->ioaccel_maxsg = | |
7356 | readl(&(h->cfgtable->io_accel_max_embedded_sg_count)); | |
7357 | if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES) | |
7358 | h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES; | |
7359 | ||
aca9012a SC |
7360 | BUILD_BUG_ON(sizeof(struct io_accel2_cmd) % |
7361 | IOACCEL2_COMMANDLIST_ALIGNMENT); | |
7362 | h->ioaccel2_cmd_pool = | |
7363 | pci_alloc_consistent(h->pdev, | |
7364 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), | |
7365 | &(h->ioaccel2_cmd_pool_dhandle)); | |
7366 | ||
7367 | h->ioaccel2_blockFetchTable = | |
7368 | kmalloc(((h->ioaccel_maxsg + 1) * | |
7369 | sizeof(u32)), GFP_KERNEL); | |
7370 | ||
7371 | if ((h->ioaccel2_cmd_pool == NULL) || | |
7372 | (h->ioaccel2_blockFetchTable == NULL)) | |
7373 | goto clean_up; | |
7374 | ||
7375 | memset(h->ioaccel2_cmd_pool, 0, | |
7376 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool)); | |
7377 | return 0; | |
7378 | ||
7379 | clean_up: | |
7380 | if (h->ioaccel2_cmd_pool) | |
7381 | pci_free_consistent(h->pdev, | |
7382 | h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool), | |
7383 | h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle); | |
7384 | kfree(h->ioaccel2_blockFetchTable); | |
7385 | return 1; | |
7386 | } | |
7387 | ||
6f039790 | 7388 | static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h) |
6c311b57 SC |
7389 | { |
7390 | u32 trans_support; | |
e1f7de0c MG |
7391 | unsigned long transMethod = CFGTBL_Trans_Performant | |
7392 | CFGTBL_Trans_use_short_tags; | |
254f796b | 7393 | int i; |
6c311b57 | 7394 | |
02ec19c8 SC |
7395 | if (hpsa_simple_mode) |
7396 | return; | |
7397 | ||
67c99a72 | 7398 | trans_support = readl(&(h->cfgtable->TransportSupport)); |
7399 | if (!(trans_support & PERFORMANT_MODE)) | |
7400 | return; | |
7401 | ||
e1f7de0c MG |
7402 | /* Check for I/O accelerator mode support */ |
7403 | if (trans_support & CFGTBL_Trans_io_accel1) { | |
7404 | transMethod |= CFGTBL_Trans_io_accel1 | | |
7405 | CFGTBL_Trans_enable_directed_msix; | |
7406 | if (hpsa_alloc_ioaccel_cmd_and_bft(h)) | |
7407 | goto clean_up; | |
aca9012a SC |
7408 | } else { |
7409 | if (trans_support & CFGTBL_Trans_io_accel2) { | |
7410 | transMethod |= CFGTBL_Trans_io_accel2 | | |
7411 | CFGTBL_Trans_enable_directed_msix; | |
7412 | if (ioaccel2_alloc_cmds_and_bft(h)) | |
7413 | goto clean_up; | |
7414 | } | |
e1f7de0c MG |
7415 | } |
7416 | ||
eee0f03a | 7417 | h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1; |
cba3d38b | 7418 | hpsa_get_max_perf_mode_cmds(h); |
6c311b57 | 7419 | /* Performant mode ring buffer and supporting data structures */ |
072b0518 | 7420 | h->reply_queue_size = h->max_commands * sizeof(u64); |
6c311b57 | 7421 | |
254f796b | 7422 | for (i = 0; i < h->nreply_queues; i++) { |
072b0518 SC |
7423 | h->reply_queue[i].head = pci_alloc_consistent(h->pdev, |
7424 | h->reply_queue_size, | |
7425 | &(h->reply_queue[i].busaddr)); | |
7426 | if (!h->reply_queue[i].head) | |
7427 | goto clean_up; | |
254f796b MG |
7428 | h->reply_queue[i].size = h->max_commands; |
7429 | h->reply_queue[i].wraparound = 1; /* spec: init to 1 */ | |
7430 | h->reply_queue[i].current_entry = 0; | |
7431 | } | |
7432 | ||
6c311b57 | 7433 | /* Need a block fetch table for performant mode */ |
d66ae08b | 7434 | h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) * |
6c311b57 | 7435 | sizeof(u32)), GFP_KERNEL); |
072b0518 | 7436 | if (!h->blockFetchTable) |
6c311b57 SC |
7437 | goto clean_up; |
7438 | ||
e1f7de0c | 7439 | hpsa_enter_performant_mode(h, trans_support); |
303932fd DB |
7440 | return; |
7441 | ||
7442 | clean_up: | |
072b0518 | 7443 | hpsa_free_reply_queues(h); |
303932fd DB |
7444 | kfree(h->blockFetchTable); |
7445 | } | |
7446 | ||
23100dd9 | 7447 | static int is_accelerated_cmd(struct CommandList *c) |
76438d08 | 7448 | { |
23100dd9 SC |
7449 | return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2; |
7450 | } | |
7451 | ||
7452 | static void hpsa_drain_accel_commands(struct ctlr_info *h) | |
7453 | { | |
7454 | struct CommandList *c = NULL; | |
f2405db8 | 7455 | int i, accel_cmds_out; |
281a7fd0 | 7456 | int refcount; |
76438d08 | 7457 | |
f2405db8 | 7458 | do { /* wait for all outstanding ioaccel commands to drain out */ |
23100dd9 | 7459 | accel_cmds_out = 0; |
f2405db8 | 7460 | for (i = 0; i < h->nr_cmds; i++) { |
f2405db8 | 7461 | c = h->cmd_pool + i; |
281a7fd0 WS |
7462 | refcount = atomic_inc_return(&c->refcount); |
7463 | if (refcount > 1) /* Command is allocated */ | |
7464 | accel_cmds_out += is_accelerated_cmd(c); | |
7465 | cmd_free(h, c); | |
f2405db8 | 7466 | } |
23100dd9 | 7467 | if (accel_cmds_out <= 0) |
281a7fd0 | 7468 | break; |
76438d08 SC |
7469 | msleep(100); |
7470 | } while (1); | |
7471 | } | |
7472 | ||
edd16368 SC |
7473 | /* |
7474 | * This is it. Register the PCI driver information for the cards we control | |
7475 | * the OS will call our registered routines when it finds one of our cards. | |
7476 | */ | |
7477 | static int __init hpsa_init(void) | |
7478 | { | |
31468401 | 7479 | return pci_register_driver(&hpsa_pci_driver); |
edd16368 SC |
7480 | } |
7481 | ||
7482 | static void __exit hpsa_cleanup(void) | |
7483 | { | |
7484 | pci_unregister_driver(&hpsa_pci_driver); | |
edd16368 SC |
7485 | } |
7486 | ||
e1f7de0c MG |
7487 | static void __attribute__((unused)) verify_offsets(void) |
7488 | { | |
dd0e19f3 ST |
7489 | #define VERIFY_OFFSET(member, offset) \ |
7490 | BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset) | |
7491 | ||
7492 | VERIFY_OFFSET(structure_size, 0); | |
7493 | VERIFY_OFFSET(volume_blk_size, 4); | |
7494 | VERIFY_OFFSET(volume_blk_cnt, 8); | |
7495 | VERIFY_OFFSET(phys_blk_shift, 16); | |
7496 | VERIFY_OFFSET(parity_rotation_shift, 17); | |
7497 | VERIFY_OFFSET(strip_size, 18); | |
7498 | VERIFY_OFFSET(disk_starting_blk, 20); | |
7499 | VERIFY_OFFSET(disk_blk_cnt, 28); | |
7500 | VERIFY_OFFSET(data_disks_per_row, 36); | |
7501 | VERIFY_OFFSET(metadata_disks_per_row, 38); | |
7502 | VERIFY_OFFSET(row_cnt, 40); | |
7503 | VERIFY_OFFSET(layout_map_count, 42); | |
7504 | VERIFY_OFFSET(flags, 44); | |
7505 | VERIFY_OFFSET(dekindex, 46); | |
7506 | /* VERIFY_OFFSET(reserved, 48 */ | |
7507 | VERIFY_OFFSET(data, 64); | |
7508 | ||
7509 | #undef VERIFY_OFFSET | |
7510 | ||
b66cc250 MM |
7511 | #define VERIFY_OFFSET(member, offset) \ |
7512 | BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset) | |
7513 | ||
7514 | VERIFY_OFFSET(IU_type, 0); | |
7515 | VERIFY_OFFSET(direction, 1); | |
7516 | VERIFY_OFFSET(reply_queue, 2); | |
7517 | /* VERIFY_OFFSET(reserved1, 3); */ | |
7518 | VERIFY_OFFSET(scsi_nexus, 4); | |
7519 | VERIFY_OFFSET(Tag, 8); | |
7520 | VERIFY_OFFSET(cdb, 16); | |
7521 | VERIFY_OFFSET(cciss_lun, 32); | |
7522 | VERIFY_OFFSET(data_len, 40); | |
7523 | VERIFY_OFFSET(cmd_priority_task_attr, 44); | |
7524 | VERIFY_OFFSET(sg_count, 45); | |
7525 | /* VERIFY_OFFSET(reserved3 */ | |
7526 | VERIFY_OFFSET(err_ptr, 48); | |
7527 | VERIFY_OFFSET(err_len, 56); | |
7528 | /* VERIFY_OFFSET(reserved4 */ | |
7529 | VERIFY_OFFSET(sg, 64); | |
7530 | ||
7531 | #undef VERIFY_OFFSET | |
7532 | ||
e1f7de0c MG |
7533 | #define VERIFY_OFFSET(member, offset) \ |
7534 | BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset) | |
7535 | ||
7536 | VERIFY_OFFSET(dev_handle, 0x00); | |
7537 | VERIFY_OFFSET(reserved1, 0x02); | |
7538 | VERIFY_OFFSET(function, 0x03); | |
7539 | VERIFY_OFFSET(reserved2, 0x04); | |
7540 | VERIFY_OFFSET(err_info, 0x0C); | |
7541 | VERIFY_OFFSET(reserved3, 0x10); | |
7542 | VERIFY_OFFSET(err_info_len, 0x12); | |
7543 | VERIFY_OFFSET(reserved4, 0x13); | |
7544 | VERIFY_OFFSET(sgl_offset, 0x14); | |
7545 | VERIFY_OFFSET(reserved5, 0x15); | |
7546 | VERIFY_OFFSET(transfer_len, 0x1C); | |
7547 | VERIFY_OFFSET(reserved6, 0x20); | |
7548 | VERIFY_OFFSET(io_flags, 0x24); | |
7549 | VERIFY_OFFSET(reserved7, 0x26); | |
7550 | VERIFY_OFFSET(LUN, 0x34); | |
7551 | VERIFY_OFFSET(control, 0x3C); | |
7552 | VERIFY_OFFSET(CDB, 0x40); | |
7553 | VERIFY_OFFSET(reserved8, 0x50); | |
7554 | VERIFY_OFFSET(host_context_flags, 0x60); | |
7555 | VERIFY_OFFSET(timeout_sec, 0x62); | |
7556 | VERIFY_OFFSET(ReplyQueue, 0x64); | |
7557 | VERIFY_OFFSET(reserved9, 0x65); | |
50a0decf | 7558 | VERIFY_OFFSET(tag, 0x68); |
e1f7de0c MG |
7559 | VERIFY_OFFSET(host_addr, 0x70); |
7560 | VERIFY_OFFSET(CISS_LUN, 0x78); | |
7561 | VERIFY_OFFSET(SG, 0x78 + 8); | |
7562 | #undef VERIFY_OFFSET | |
7563 | } | |
7564 | ||
edd16368 SC |
7565 | module_init(hpsa_init); |
7566 | module_exit(hpsa_cleanup); |