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[SCSI] hpsa: complete the ioaccel raidmap code
[linux-block.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
3 * Copyright 2000, 2009 Hewlett-Packard Development Company, L.P.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; version 2 of the License.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
12 * NON INFRINGEMENT. See the GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
17 *
18 * Questions/Comments/Bugfixes to iss_storagedev@hp.com
19 *
20 */
21
22#include <linux/module.h>
23#include <linux/interrupt.h>
24#include <linux/types.h>
25#include <linux/pci.h>
e5a44df8 26#include <linux/pci-aspm.h>
edd16368
SC		 27#include <linux/kernel.h>
28#include <linux/slab.h>
29#include <linux/delay.h>
30#include <linux/fs.h>
31#include <linux/timer.h>
edd16368
SC		 32#include <linux/init.h>
33#include <linux/spinlock.h>
edd16368
SC		 34#include <linux/compat.h>
35#include <linux/blktrace_api.h>
36#include <linux/uaccess.h>
37#include <linux/io.h>
38#include <linux/dma-mapping.h>
39#include <linux/completion.h>
40#include <linux/moduleparam.h>
41#include <scsi/scsi.h>
42#include <scsi/scsi_cmnd.h>
43#include <scsi/scsi_device.h>
44#include <scsi/scsi_host.h>
667e23d4 45#include <scsi/scsi_tcq.h>
edd16368
SC		 46#include <linux/cciss_ioctl.h>
47#include <linux/string.h>
48#include <linux/bitmap.h>
60063497 49#include <linux/atomic.h>
edd16368 50#include <linux/kthread.h>
a0c12413 51#include <linux/jiffies.h>
283b4a9b 52#include <asm/div64.h>
edd16368
SC		 53#include "hpsa_cmd.h"
54#include "hpsa.h"
55
56/* HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.' */
e481cce8 57#define HPSA_DRIVER_VERSION "3.4.0-1"
edd16368 58#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 59#define HPSA "hpsa"
edd16368
SC		 60
61/* How long to wait (in milliseconds) for board to go into simple mode */
62#define MAX_CONFIG_WAIT 30000
63#define MAX_IOCTL_CONFIG_WAIT 1000
64
65/*define how many times we will try a command because of bus resets */
66#define MAX_CMD_RETRIES 3
67
68/* Embedded module documentation macros - see modules.h */
69MODULE_AUTHOR("Hewlett-Packard Company");
70MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
71 HPSA_DRIVER_VERSION);
72MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
73MODULE_VERSION(HPSA_DRIVER_VERSION);
74MODULE_LICENSE("GPL");
75
76static int hpsa_allow_any;
77module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
78MODULE_PARM_DESC(hpsa_allow_any,
79 "Allow hpsa driver to access unknown HP Smart Array hardware");
02ec19c8
SC		 80static int hpsa_simple_mode;
81module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
82MODULE_PARM_DESC(hpsa_simple_mode,
83 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 84
85/* define the PCI info for the cards we can control */
86static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 87 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
88 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
89 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
90 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
91 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 92 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
fe0c9610
MM		 102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1925},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
7c03b870 122 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 123 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 124 {0,}
125};
126
127MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
128
129/* board_id = Subsystem Device ID & Vendor ID
130 * product = Marketing Name for the board
131 * access = Address of the struct of function pointers
132 */
133static struct board_type products[] = {
edd16368
SC		 134 {0x3241103C, "Smart Array P212", &SA5_access},
135 {0x3243103C, "Smart Array P410", &SA5_access},
136 {0x3245103C, "Smart Array P410i", &SA5_access},
137 {0x3247103C, "Smart Array P411", &SA5_access},
138 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 139 {0x324A103C, "Smart Array P712m", &SA5_access},
140 {0x324B103C, "Smart Array P711m", &SA5_access},
fe0c9610
MM		 141 {0x3350103C, "Smart Array P222", &SA5_access},
142 {0x3351103C, "Smart Array P420", &SA5_access},
143 {0x3352103C, "Smart Array P421", &SA5_access},
144 {0x3353103C, "Smart Array P822", &SA5_access},
145 {0x3354103C, "Smart Array P420i", &SA5_access},
146 {0x3355103C, "Smart Array P220i", &SA5_access},
147 {0x3356103C, "Smart Array P721m", &SA5_access},
1fd6c8e3
MM		 148 {0x1921103C, "Smart Array P830i", &SA5_access},
149 {0x1922103C, "Smart Array P430", &SA5_access},
150 {0x1923103C, "Smart Array P431", &SA5_access},
151 {0x1924103C, "Smart Array P830", &SA5_access},
152 {0x1926103C, "Smart Array P731m", &SA5_access},
153 {0x1928103C, "Smart Array P230i", &SA5_access},
154 {0x1929103C, "Smart Array P530", &SA5_access},
97b9f53d
MM		 155 {0x21BD103C, "Smart Array", &SA5_access},
156 {0x21BE103C, "Smart Array", &SA5_access},
157 {0x21BF103C, "Smart Array", &SA5_access},
158 {0x21C0103C, "Smart Array", &SA5_access},
159 {0x21C1103C, "Smart Array", &SA5_access},
160 {0x21C2103C, "Smart Array", &SA5_access},
161 {0x21C3103C, "Smart Array", &SA5_access},
162 {0x21C4103C, "Smart Array", &SA5_access},
163 {0x21C5103C, "Smart Array", &SA5_access},
164 {0x21C7103C, "Smart Array", &SA5_access},
165 {0x21C8103C, "Smart Array", &SA5_access},
166 {0x21C9103C, "Smart Array", &SA5_access},
edd16368
SC		 167 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
168};
169
170static int number_of_controllers;
171
10f66018
SC		 172static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
173static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
edd16368
SC		 174static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg);
175static void start_io(struct ctlr_info *h);
176
177#ifdef CONFIG_COMPAT
178static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg);
179#endif
180
181static void cmd_free(struct ctlr_info *h, struct CommandList *c);
182static void cmd_special_free(struct ctlr_info *h, struct CommandList *c);
183static struct CommandList *cmd_alloc(struct ctlr_info *h);
184static struct CommandList *cmd_special_alloc(struct ctlr_info *h);
a2dac136 185static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
01a02ffc 186 void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
edd16368
SC		 187 int cmd_type);
188
f281233d 189static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 190static void hpsa_scan_start(struct Scsi_Host *);
191static int hpsa_scan_finished(struct Scsi_Host *sh,
192 unsigned long elapsed_time);
667e23d4
SC		 193static int hpsa_change_queue_depth(struct scsi_device *sdev,
194 int qdepth, int reason);
edd16368
SC		 195
196static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
75167d2c 197static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
edd16368
SC		 198static int hpsa_slave_alloc(struct scsi_device *sdev);
199static void hpsa_slave_destroy(struct scsi_device *sdev);
200
edd16368 201static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno);
edd16368
SC		 202static int check_for_unit_attention(struct ctlr_info *h,
203 struct CommandList *c);
204static void check_ioctl_unit_attention(struct ctlr_info *h,
205 struct CommandList *c);
303932fd
DB		 206/* performant mode helper functions */
207static void calc_bucket_map(int *bucket, int num_buckets,
e1f7de0c 208 int nsgs, int min_blocks, int *bucket_map);
6f039790 209static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 210static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 211static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
212 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
213 u64 *cfg_offset);
214static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
215 unsigned long *memory_bar);
216static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
217static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
218 int wait_for_ready);
75167d2c 219static inline void finish_cmd(struct CommandList *c);
283b4a9b 220static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 221#define BOARD_NOT_READY 0
222#define BOARD_READY 1
76438d08
SC		 223static void hpsa_drain_commands(struct ctlr_info *h);
224static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 225static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
226 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
227 u8 *scsi3addr);
edd16368 228
edd16368
SC		 229static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
230{
231 unsigned long *priv = shost_priv(sdev->host);
232 return (struct ctlr_info *) *priv;
233}
234
a23513e8
SC		 235static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
236{
237 unsigned long *priv = shost_priv(sh);
238 return (struct ctlr_info *) *priv;
239}
240
edd16368
SC		 241static int check_for_unit_attention(struct ctlr_info *h,
242 struct CommandList *c)
243{
244 if (c->err_info->SenseInfo[2] != UNIT_ATTENTION)
245 return 0;
246
247 switch (c->err_info->SenseInfo[12]) {
248 case STATE_CHANGED:
f79cfec6 249 dev_warn(&h->pdev->dev, HPSA "%d: a state change "
edd16368
SC		 250 "detected, command retried\n", h->ctlr);
251 break;
252 case LUN_FAILED:
f79cfec6 253 dev_warn(&h->pdev->dev, HPSA "%d: LUN failure "
edd16368
SC		 254 "detected, action required\n", h->ctlr);
255 break;
256 case REPORT_LUNS_CHANGED:
f79cfec6 257 dev_warn(&h->pdev->dev, HPSA "%d: report LUN data "
31468401 258 "changed, action required\n", h->ctlr);
edd16368 259 /*
4f4eb9f1
ST		 260 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
261 * target (array) devices.
edd16368
SC		 262 */
263 break;
264 case POWER_OR_RESET:
f79cfec6 265 dev_warn(&h->pdev->dev, HPSA "%d: a power on "
edd16368
SC		 266 "or device reset detected\n", h->ctlr);
267 break;
268 case UNIT_ATTENTION_CLEARED:
f79cfec6 269 dev_warn(&h->pdev->dev, HPSA "%d: unit attention "
edd16368
SC		 270 "cleared by another initiator\n", h->ctlr);
271 break;
272 default:
f79cfec6 273 dev_warn(&h->pdev->dev, HPSA "%d: unknown "
edd16368
SC		 274 "unit attention detected\n", h->ctlr);
275 break;
276 }
277 return 1;
278}
279
852af20a
MB		 280static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
281{
282 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
283 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
284 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
285 return 0;
286 dev_warn(&h->pdev->dev, HPSA "device busy");
287 return 1;
288}
289
edd16368
SC		 290static ssize_t host_store_rescan(struct device *dev,
291 struct device_attribute *attr,
292 const char *buf, size_t count)
293{
294 struct ctlr_info *h;
295 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 296 h = shost_to_hba(shost);
31468401 297 hpsa_scan_start(h->scsi_host);
edd16368
SC		 298 return count;
299}
300
d28ce020
SC		 301static ssize_t host_show_firmware_revision(struct device *dev,
302 struct device_attribute *attr, char *buf)
303{
304 struct ctlr_info *h;
305 struct Scsi_Host *shost = class_to_shost(dev);
306 unsigned char *fwrev;
307
308 h = shost_to_hba(shost);
309 if (!h->hba_inquiry_data)
310 return 0;
311 fwrev = &h->hba_inquiry_data[32];
312 return snprintf(buf, 20, "%c%c%c%c\n",
313 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
314}
315
94a13649
SC		 316static ssize_t host_show_commands_outstanding(struct device *dev,
317 struct device_attribute *attr, char *buf)
318{
319 struct Scsi_Host *shost = class_to_shost(dev);
320 struct ctlr_info *h = shost_to_hba(shost);
321
322 return snprintf(buf, 20, "%d\n", h->commands_outstanding);
323}
324
745a7a25
SC		 325static ssize_t host_show_transport_mode(struct device *dev,
326 struct device_attribute *attr, char *buf)
327{
328 struct ctlr_info *h;
329 struct Scsi_Host *shost = class_to_shost(dev);
330
331 h = shost_to_hba(shost);
332 return snprintf(buf, 20, "%s\n",
960a30e7 333 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 334 "performant" : "simple");
335}
336
46380786 337/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 338static u32 unresettable_controller[] = {
339 0x324a103C, /* Smart Array P712m */
340 0x324b103C, /* SmartArray P711m */
341 0x3223103C, /* Smart Array P800 */
342 0x3234103C, /* Smart Array P400 */
343 0x3235103C, /* Smart Array P400i */
344 0x3211103C, /* Smart Array E200i */
345 0x3212103C, /* Smart Array E200 */
346 0x3213103C, /* Smart Array E200i */
347 0x3214103C, /* Smart Array E200i */
348 0x3215103C, /* Smart Array E200i */
349 0x3237103C, /* Smart Array E500 */
350 0x323D103C, /* Smart Array P700m */
7af0abbc 351 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 352 0x409C0E11, /* Smart Array 6400 */
353 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 354 0x40700E11, /* Smart Array 5300 */
355 0x40820E11, /* Smart Array 532 */
356 0x40830E11, /* Smart Array 5312 */
357 0x409A0E11, /* Smart Array 641 */
358 0x409B0E11, /* Smart Array 642 */
359 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 360};
361
46380786
SC		 362/* List of controllers which cannot even be soft reset */
363static u32 soft_unresettable_controller[] = {
7af0abbc 364 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 365 0x40700E11, /* Smart Array 5300 */
366 0x40820E11, /* Smart Array 532 */
367 0x40830E11, /* Smart Array 5312 */
368 0x409A0E11, /* Smart Array 641 */
369 0x409B0E11, /* Smart Array 642 */
370 0x40910E11, /* Smart Array 6i */
46380786
SC		 371 /* Exclude 640x boards. These are two pci devices in one slot
372 * which share a battery backed cache module. One controls the
373 * cache, the other accesses the cache through the one that controls
374 * it. If we reset the one controlling the cache, the other will
375 * likely not be happy. Just forbid resetting this conjoined mess.
376 * The 640x isn't really supported by hpsa anyway.
377 */
378 0x409C0E11, /* Smart Array 6400 */
379 0x409D0E11, /* Smart Array 6400 EM */
380};
381
382static int ctlr_is_hard_resettable(u32 board_id)
941b1cda
SC		 383{
384 int i;
385
386 for (i = 0; i < ARRAY_SIZE(unresettable_controller); i++)
46380786
SC		 387 if (unresettable_controller[i] == board_id)
388 return 0;
389 return 1;
390}
391
392static int ctlr_is_soft_resettable(u32 board_id)
393{
394 int i;
395
396 for (i = 0; i < ARRAY_SIZE(soft_unresettable_controller); i++)
397 if (soft_unresettable_controller[i] == board_id)
941b1cda
SC		 398 return 0;
399 return 1;
400}
401
46380786
SC		 402static int ctlr_is_resettable(u32 board_id)
403{
404 return ctlr_is_hard_resettable(board_id) ||
405 ctlr_is_soft_resettable(board_id);
406}
407
941b1cda
SC		 408static ssize_t host_show_resettable(struct device *dev,
409 struct device_attribute *attr, char *buf)
410{
411 struct ctlr_info *h;
412 struct Scsi_Host *shost = class_to_shost(dev);
413
414 h = shost_to_hba(shost);
46380786 415 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 416}
417
edd16368
SC		 418static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
419{
420 return (scsi3addr[3] & 0xC0) == 0x40;
421}
422
423static const char *raid_label[] = { "0", "4", "1(1+0)", "5", "5+1", "ADG",
d82357ea 424 "1(ADM)", "UNKNOWN"
edd16368 425};
6b80b18f
ST		 426#define HPSA_RAID_0 0
427#define HPSA_RAID_4 1
428#define HPSA_RAID_1 2 /* also used for RAID 10 */
429#define HPSA_RAID_5 3 /* also used for RAID 50 */
430#define HPSA_RAID_51 4
431#define HPSA_RAID_6 5 /* also used for RAID 60 */
432#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
edd16368
SC		 433#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 1)
434
435static ssize_t raid_level_show(struct device *dev,
436 struct device_attribute *attr, char *buf)
437{
438 ssize_t l = 0;
82a72c0a 439 unsigned char rlevel;
edd16368
SC		 440 struct ctlr_info *h;
441 struct scsi_device *sdev;
442 struct hpsa_scsi_dev_t *hdev;
443 unsigned long flags;
444
445 sdev = to_scsi_device(dev);
446 h = sdev_to_hba(sdev);
447 spin_lock_irqsave(&h->lock, flags);
448 hdev = sdev->hostdata;
449 if (!hdev) {
450 spin_unlock_irqrestore(&h->lock, flags);
451 return -ENODEV;
452 }
453
454 /* Is this even a logical drive? */
455 if (!is_logical_dev_addr_mode(hdev->scsi3addr)) {
456 spin_unlock_irqrestore(&h->lock, flags);
457 l = snprintf(buf, PAGE_SIZE, "N/A\n");
458 return l;
459 }
460
461 rlevel = hdev->raid_level;
462 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 463 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 464 rlevel = RAID_UNKNOWN;
465 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
466 return l;
467}
468
469static ssize_t lunid_show(struct device *dev,
470 struct device_attribute *attr, char *buf)
471{
472 struct ctlr_info *h;
473 struct scsi_device *sdev;
474 struct hpsa_scsi_dev_t *hdev;
475 unsigned long flags;
476 unsigned char lunid[8];
477
478 sdev = to_scsi_device(dev);
479 h = sdev_to_hba(sdev);
480 spin_lock_irqsave(&h->lock, flags);
481 hdev = sdev->hostdata;
482 if (!hdev) {
483 spin_unlock_irqrestore(&h->lock, flags);
484 return -ENODEV;
485 }
486 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
487 spin_unlock_irqrestore(&h->lock, flags);
488 return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
489 lunid[0], lunid[1], lunid[2], lunid[3],
490 lunid[4], lunid[5], lunid[6], lunid[7]);
491}
492
493static ssize_t unique_id_show(struct device *dev,
494 struct device_attribute *attr, char *buf)
495{
496 struct ctlr_info *h;
497 struct scsi_device *sdev;
498 struct hpsa_scsi_dev_t *hdev;
499 unsigned long flags;
500 unsigned char sn[16];
501
502 sdev = to_scsi_device(dev);
503 h = sdev_to_hba(sdev);
504 spin_lock_irqsave(&h->lock, flags);
505 hdev = sdev->hostdata;
506 if (!hdev) {
507 spin_unlock_irqrestore(&h->lock, flags);
508 return -ENODEV;
509 }
510 memcpy(sn, hdev->device_id, sizeof(sn));
511 spin_unlock_irqrestore(&h->lock, flags);
512 return snprintf(buf, 16 * 2 + 2,
513 "%02X%02X%02X%02X%02X%02X%02X%02X"
514 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
515 sn[0], sn[1], sn[2], sn[3],
516 sn[4], sn[5], sn[6], sn[7],
517 sn[8], sn[9], sn[10], sn[11],
518 sn[12], sn[13], sn[14], sn[15]);
519}
520
c1988684
ST		 521static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
522 struct device_attribute *attr, char *buf)
523{
524 struct ctlr_info *h;
525 struct scsi_device *sdev;
526 struct hpsa_scsi_dev_t *hdev;
527 unsigned long flags;
528 int offload_enabled;
529
530 sdev = to_scsi_device(dev);
531 h = sdev_to_hba(sdev);
532 spin_lock_irqsave(&h->lock, flags);
533 hdev = sdev->hostdata;
534 if (!hdev) {
535 spin_unlock_irqrestore(&h->lock, flags);
536 return -ENODEV;
537 }
538 offload_enabled = hdev->offload_enabled;
539 spin_unlock_irqrestore(&h->lock, flags);
540 return snprintf(buf, 20, "%d\n", offload_enabled);
541}
542
3f5eac3a
SC		 543static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
544static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
545static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
546static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c1988684
ST		 547static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
548 host_show_hp_ssd_smart_path_enabled, NULL);
3f5eac3a
SC		 549static DEVICE_ATTR(firmware_revision, S_IRUGO,
550 host_show_firmware_revision, NULL);
551static DEVICE_ATTR(commands_outstanding, S_IRUGO,
552 host_show_commands_outstanding, NULL);
553static DEVICE_ATTR(transport_mode, S_IRUGO,
554 host_show_transport_mode, NULL);
941b1cda
SC		 555static DEVICE_ATTR(resettable, S_IRUGO,
556 host_show_resettable, NULL);
3f5eac3a
SC		 557
558static struct device_attribute *hpsa_sdev_attrs[] = {
559 &dev_attr_raid_level,
560 &dev_attr_lunid,
561 &dev_attr_unique_id,
c1988684 562 &dev_attr_hp_ssd_smart_path_enabled,
3f5eac3a
SC		 563 NULL,
564};
565
566static struct device_attribute *hpsa_shost_attrs[] = {
567 &dev_attr_rescan,
568 &dev_attr_firmware_revision,
569 &dev_attr_commands_outstanding,
570 &dev_attr_transport_mode,
941b1cda 571 &dev_attr_resettable,
3f5eac3a
SC		 572 NULL,
573};
574
575static struct scsi_host_template hpsa_driver_template = {
576 .module = THIS_MODULE,
f79cfec6
SC		 577 .name = HPSA,
578 .proc_name = HPSA,
3f5eac3a
SC		 579 .queuecommand = hpsa_scsi_queue_command,
580 .scan_start = hpsa_scan_start,
581 .scan_finished = hpsa_scan_finished,
582 .change_queue_depth = hpsa_change_queue_depth,
583 .this_id = -1,
584 .use_clustering = ENABLE_CLUSTERING,
75167d2c 585 .eh_abort_handler = hpsa_eh_abort_handler,
3f5eac3a
SC		 586 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
587 .ioctl = hpsa_ioctl,
588 .slave_alloc = hpsa_slave_alloc,
589 .slave_destroy = hpsa_slave_destroy,
590#ifdef CONFIG_COMPAT
591 .compat_ioctl = hpsa_compat_ioctl,
592#endif
593 .sdev_attrs = hpsa_sdev_attrs,
594 .shost_attrs = hpsa_shost_attrs,
c0d6a4d1 595 .max_sectors = 8192,
54b2b50c 596 .no_write_same = 1,
3f5eac3a
SC		 597};
598
599
600/* Enqueuing and dequeuing functions for cmdlists. */
601static inline void addQ(struct list_head *list, struct CommandList *c)
602{
603 list_add_tail(&c->list, list);
604}
605
254f796b 606static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 607{
608 u32 a;
254f796b 609 struct reply_pool *rq = &h->reply_queue[q];
e16a33ad 610 unsigned long flags;
3f5eac3a 611
e1f7de0c
MG		 612 if (h->transMethod & CFGTBL_Trans_io_accel1)
613 return h->access.command_completed(h, q);
614
3f5eac3a 615 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 616 return h->access.command_completed(h, q);
3f5eac3a 617
254f796b
MG		 618 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
619 a = rq->head[rq->current_entry];
620 rq->current_entry++;
e16a33ad 621 spin_lock_irqsave(&h->lock, flags);
3f5eac3a 622 h->commands_outstanding--;
e16a33ad 623 spin_unlock_irqrestore(&h->lock, flags);
3f5eac3a
SC		 624 } else {
625 a = FIFO_EMPTY;
626 }
627 /* Check for wraparound */
254f796b
MG		 628 if (rq->current_entry == h->max_commands) {
629 rq->current_entry = 0;
630 rq->wraparound ^= 1;
3f5eac3a
SC		 631 }
632 return a;
633}
634
c349775e
ST		 635/*
636 * There are some special bits in the bus address of the
637 * command that we have to set for the controller to know
638 * how to process the command:
639 *
640 * Normal performant mode:
641 * bit 0: 1 means performant mode, 0 means simple mode.
642 * bits 1-3 = block fetch table entry
643 * bits 4-6 = command type (== 0)
644 *
645 * ioaccel1 mode:
646 * bit 0 = "performant mode" bit.
647 * bits 1-3 = block fetch table entry
648 * bits 4-6 = command type (== 110)
649 * (command type is needed because ioaccel1 mode
650 * commands are submitted through the same register as normal
651 * mode commands, so this is how the controller knows whether
652 * the command is normal mode or ioaccel1 mode.)
653 *
654 * ioaccel2 mode:
655 * bit 0 = "performant mode" bit.
656 * bits 1-4 = block fetch table entry (note extra bit)
657 * bits 4-6 = not needed, because ioaccel2 mode has
658 * a separate special register for submitting commands.
659 */
660
3f5eac3a
SC		 661/* set_performant_mode: Modify the tag for cciss performant
662 * set bit 0 for pull model, bits 3-1 for block fetch
663 * register number
664 */
665static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
666{
254f796b 667 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 668 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
eee0f03a 669 if (likely(h->msix_vector > 0))
254f796b 670 c->Header.ReplyQueue =
804a5cb5 671 raw_smp_processor_id() % h->nreply_queues;
254f796b 672 }
3f5eac3a
SC		 673}
674
c349775e
ST		 675static void set_ioaccel1_performant_mode(struct ctlr_info *h,
676 struct CommandList *c)
677{
678 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
679
680 /* Tell the controller to post the reply to the queue for this
681 * processor. This seems to give the best I/O throughput.
682 */
683 cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
684 /* Set the bits in the address sent down to include:
685 * - performant mode bit (bit 0)
686 * - pull count (bits 1-3)
687 * - command type (bits 4-6)
688 */
689 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
690 IOACCEL1_BUSADDR_CMDTYPE;
691}
692
693static void set_ioaccel2_performant_mode(struct ctlr_info *h,
694 struct CommandList *c)
695{
696 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
697
698 /* Tell the controller to post the reply to the queue for this
699 * processor. This seems to give the best I/O throughput.
700 */
701 cp->reply_queue = smp_processor_id() % h->nreply_queues;
702 /* Set the bits in the address sent down to include:
703 * - performant mode bit not used in ioaccel mode 2
704 * - pull count (bits 0-3)
705 * - command type isn't needed for ioaccel2
706 */
707 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
708}
709
e85c5974
SC		 710static int is_firmware_flash_cmd(u8 *cdb)
711{
712 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
713}
714
715/*
716 * During firmware flash, the heartbeat register may not update as frequently
717 * as it should. So we dial down lockup detection during firmware flash. and
718 * dial it back up when firmware flash completes.
719 */
720#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
721#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
722static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
723 struct CommandList *c)
724{
725 if (!is_firmware_flash_cmd(c->Request.CDB))
726 return;
727 atomic_inc(&h->firmware_flash_in_progress);
728 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
729}
730
731static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
732 struct CommandList *c)
733{
734 if (is_firmware_flash_cmd(c->Request.CDB) &&
735 atomic_dec_and_test(&h->firmware_flash_in_progress))
736 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
737}
738
3f5eac3a
SC		 739static void enqueue_cmd_and_start_io(struct ctlr_info *h,
740 struct CommandList *c)
741{
742 unsigned long flags;
743
c349775e
ST		 744 switch (c->cmd_type) {
745 case CMD_IOACCEL1:
746 set_ioaccel1_performant_mode(h, c);
747 break;
748 case CMD_IOACCEL2:
749 set_ioaccel2_performant_mode(h, c);
750 break;
751 default:
752 set_performant_mode(h, c);
753 }
e85c5974 754 dial_down_lockup_detection_during_fw_flash(h, c);
3f5eac3a
SC		 755 spin_lock_irqsave(&h->lock, flags);
756 addQ(&h->reqQ, c);
757 h->Qdepth++;
3f5eac3a 758 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 759 start_io(h);
3f5eac3a
SC		 760}
761
762static inline void removeQ(struct CommandList *c)
763{
764 if (WARN_ON(list_empty(&c->list)))
765 return;
766 list_del_init(&c->list);
767}
768
769static inline int is_hba_lunid(unsigned char scsi3addr[])
770{
771 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
772}
773
774static inline int is_scsi_rev_5(struct ctlr_info *h)
775{
776 if (!h->hba_inquiry_data)
777 return 0;
778 if ((h->hba_inquiry_data[2] & 0x07) == 5)
779 return 1;
780 return 0;
781}
782
edd16368
SC		 783static int hpsa_find_target_lun(struct ctlr_info *h,
784 unsigned char scsi3addr[], int bus, int *target, int *lun)
785{
786 /* finds an unused bus, target, lun for a new physical device
787 * assumes h->devlock is held
788 */
789 int i, found = 0;
cfe5badc 790 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 791
263d9401 792 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 793
794 for (i = 0; i < h->ndevices; i++) {
795 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 796 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 797 }
798
263d9401
AM		 799 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
800 if (i < HPSA_MAX_DEVICES) {
801 /* *bus = 1; */
802 *target = i;
803 *lun = 0;
804 found = 1;
edd16368
SC		 805 }
806 return !found;
807}
808
809/* Add an entry into h->dev[] array. */
810static int hpsa_scsi_add_entry(struct ctlr_info *h, int hostno,
811 struct hpsa_scsi_dev_t *device,
812 struct hpsa_scsi_dev_t *added[], int *nadded)
813{
814 /* assumes h->devlock is held */
815 int n = h->ndevices;
816 int i;
817 unsigned char addr1[8], addr2[8];
818 struct hpsa_scsi_dev_t *sd;
819
cfe5badc 820 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 821 dev_err(&h->pdev->dev, "too many devices, some will be "
822 "inaccessible.\n");
823 return -1;
824 }
825
826 /* physical devices do not have lun or target assigned until now. */
827 if (device->lun != -1)
828 /* Logical device, lun is already assigned. */
829 goto lun_assigned;
830
831 /* If this device a non-zero lun of a multi-lun device
832 * byte 4 of the 8-byte LUN addr will contain the logical
833 * unit no, zero otherise.
834 */
835 if (device->scsi3addr[4] == 0) {
836 /* This is not a non-zero lun of a multi-lun device */
837 if (hpsa_find_target_lun(h, device->scsi3addr,
838 device->bus, &device->target, &device->lun) != 0)
839 return -1;
840 goto lun_assigned;
841 }
842
843 /* This is a non-zero lun of a multi-lun device.
844 * Search through our list and find the device which
845 * has the same 8 byte LUN address, excepting byte 4.
846 * Assign the same bus and target for this new LUN.
847 * Use the logical unit number from the firmware.
848 */
849 memcpy(addr1, device->scsi3addr, 8);
850 addr1[4] = 0;
851 for (i = 0; i < n; i++) {
852 sd = h->dev[i];
853 memcpy(addr2, sd->scsi3addr, 8);
854 addr2[4] = 0;
855 /* differ only in byte 4? */
856 if (memcmp(addr1, addr2, 8) == 0) {
857 device->bus = sd->bus;
858 device->target = sd->target;
859 device->lun = device->scsi3addr[4];
860 break;
861 }
862 }
863 if (device->lun == -1) {
864 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
865 " suspect firmware bug or unsupported hardware "
866 "configuration.\n");
867 return -1;
868 }
869
870lun_assigned:
871
872 h->dev[n] = device;
873 h->ndevices++;
874 added[*nadded] = device;
875 (*nadded)++;
876
877 /* initially, (before registering with scsi layer) we don't
878 * know our hostno and we don't want to print anything first
879 * time anyway (the scsi layer's inquiries will show that info)
880 */
881 /* if (hostno != -1) */
882 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d added.\n",
883 scsi_device_type(device->devtype), hostno,
884 device->bus, device->target, device->lun);
885 return 0;
886}
887
bd9244f7
ST		 888/* Update an entry in h->dev[] array. */
889static void hpsa_scsi_update_entry(struct ctlr_info *h, int hostno,
890 int entry, struct hpsa_scsi_dev_t *new_entry)
891{
892 /* assumes h->devlock is held */
893 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
894
895 /* Raid level changed. */
896 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125
SC		 897
898 /* Raid offload parameters changed. */
899 h->dev[entry]->offload_config = new_entry->offload_config;
900 h->dev[entry]->offload_enabled = new_entry->offload_enabled;
9fb0de2d
SC		 901 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
902 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
903 h->dev[entry]->raid_map = new_entry->raid_map;
250fb125 904
bd9244f7
ST		 905 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d updated.\n",
906 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
907 new_entry->target, new_entry->lun);
908}
909
2a8ccf31
SC		 910/* Replace an entry from h->dev[] array. */
911static void hpsa_scsi_replace_entry(struct ctlr_info *h, int hostno,
912 int entry, struct hpsa_scsi_dev_t *new_entry,
913 struct hpsa_scsi_dev_t *added[], int *nadded,
914 struct hpsa_scsi_dev_t *removed[], int *nremoved)
915{
916 /* assumes h->devlock is held */
cfe5badc 917 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 918 removed[*nremoved] = h->dev[entry];
919 (*nremoved)++;
01350d05
SC		 920
921 /*
922 * New physical devices won't have target/lun assigned yet
923 * so we need to preserve the values in the slot we are replacing.
924 */
925 if (new_entry->target == -1) {
926 new_entry->target = h->dev[entry]->target;
927 new_entry->lun = h->dev[entry]->lun;
928 }
929
2a8ccf31
SC		 930 h->dev[entry] = new_entry;
931 added[*nadded] = new_entry;
932 (*nadded)++;
933 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d changed.\n",
934 scsi_device_type(new_entry->devtype), hostno, new_entry->bus,
935 new_entry->target, new_entry->lun);
936}
937
edd16368
SC		 938/* Remove an entry from h->dev[] array. */
939static void hpsa_scsi_remove_entry(struct ctlr_info *h, int hostno, int entry,
940 struct hpsa_scsi_dev_t *removed[], int *nremoved)
941{
942 /* assumes h->devlock is held */
943 int i;
944 struct hpsa_scsi_dev_t *sd;
945
cfe5badc 946 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 947
948 sd = h->dev[entry];
949 removed[*nremoved] = h->dev[entry];
950 (*nremoved)++;
951
952 for (i = entry; i < h->ndevices-1; i++)
953 h->dev[i] = h->dev[i+1];
954 h->ndevices--;
955 dev_info(&h->pdev->dev, "%s device c%db%dt%dl%d removed.\n",
956 scsi_device_type(sd->devtype), hostno, sd->bus, sd->target,
957 sd->lun);
958}
959
960#define SCSI3ADDR_EQ(a, b) ( \
961 (a)[7] == (b)[7] && \
962 (a)[6] == (b)[6] && \
963 (a)[5] == (b)[5] && \
964 (a)[4] == (b)[4] && \
965 (a)[3] == (b)[3] && \
966 (a)[2] == (b)[2] && \
967 (a)[1] == (b)[1] && \
968 (a)[0] == (b)[0])
969
970static void fixup_botched_add(struct ctlr_info *h,
971 struct hpsa_scsi_dev_t *added)
972{
973 /* called when scsi_add_device fails in order to re-adjust
974 * h->dev[] to match the mid layer's view.
975 */
976 unsigned long flags;
977 int i, j;
978
979 spin_lock_irqsave(&h->lock, flags);
980 for (i = 0; i < h->ndevices; i++) {
981 if (h->dev[i] == added) {
982 for (j = i; j < h->ndevices-1; j++)
983 h->dev[j] = h->dev[j+1];
984 h->ndevices--;
985 break;
986 }
987 }
988 spin_unlock_irqrestore(&h->lock, flags);
989 kfree(added);
990}
991
992static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
993 struct hpsa_scsi_dev_t *dev2)
994{
edd16368
SC		 995 /* we compare everything except lun and target as these
996 * are not yet assigned. Compare parts likely
997 * to differ first
998 */
999 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1000 sizeof(dev1->scsi3addr)) != 0)
1001 return 0;
1002 if (memcmp(dev1->device_id, dev2->device_id,
1003 sizeof(dev1->device_id)) != 0)
1004 return 0;
1005 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1006 return 0;
1007 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1008 return 0;
edd16368
SC		 1009 if (dev1->devtype != dev2->devtype)
1010 return 0;
edd16368
SC		 1011 if (dev1->bus != dev2->bus)
1012 return 0;
1013 return 1;
1014}
1015
bd9244f7
ST		 1016static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1017 struct hpsa_scsi_dev_t *dev2)
1018{
1019 /* Device attributes that can change, but don't mean
1020 * that the device is a different device, nor that the OS
1021 * needs to be told anything about the change.
1022 */
1023 if (dev1->raid_level != dev2->raid_level)
1024 return 1;
250fb125
SC		 1025 if (dev1->offload_config != dev2->offload_config)
1026 return 1;
1027 if (dev1->offload_enabled != dev2->offload_enabled)
1028 return 1;
bd9244f7
ST		 1029 return 0;
1030}
1031
edd16368
SC		 1032/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1033 * and return needle location in *index. If scsi3addr matches, but not
1034 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1035 * location in *index.
1036 * In the case of a minor device attribute change, such as RAID level, just
1037 * return DEVICE_UPDATED, along with the updated device's location in index.
1038 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1039 */
1040static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1041 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1042 int *index)
1043{
1044 int i;
1045#define DEVICE_NOT_FOUND 0
1046#define DEVICE_CHANGED 1
1047#define DEVICE_SAME 2
bd9244f7 1048#define DEVICE_UPDATED 3
edd16368 1049 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1050 if (haystack[i] == NULL) /* previously removed. */
1051 continue;
edd16368
SC		 1052 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1053 *index = i;
bd9244f7
ST		 1054 if (device_is_the_same(needle, haystack[i])) {
1055 if (device_updated(needle, haystack[i]))
1056 return DEVICE_UPDATED;
edd16368 1057 return DEVICE_SAME;
bd9244f7 1058 } else {
edd16368 1059 return DEVICE_CHANGED;
bd9244f7 1060 }
edd16368
SC		 1061 }
1062 }
1063 *index = -1;
1064 return DEVICE_NOT_FOUND;
1065}
1066
4967bd3e 1067static void adjust_hpsa_scsi_table(struct ctlr_info *h, int hostno,
edd16368
SC		 1068 struct hpsa_scsi_dev_t *sd[], int nsds)
1069{
1070 /* sd contains scsi3 addresses and devtypes, and inquiry
1071 * data. This function takes what's in sd to be the current
1072 * reality and updates h->dev[] to reflect that reality.
1073 */
1074 int i, entry, device_change, changes = 0;
1075 struct hpsa_scsi_dev_t *csd;
1076 unsigned long flags;
1077 struct hpsa_scsi_dev_t **added, **removed;
1078 int nadded, nremoved;
1079 struct Scsi_Host *sh = NULL;
1080
cfe5badc
ST		 1081 added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
1082 removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 1083
1084 if (!added || !removed) {
1085 dev_warn(&h->pdev->dev, "out of memory in "
1086 "adjust_hpsa_scsi_table\n");
1087 goto free_and_out;
1088 }
1089
1090 spin_lock_irqsave(&h->devlock, flags);
1091
1092 /* find any devices in h->dev[] that are not in
1093 * sd[] and remove them from h->dev[], and for any
1094 * devices which have changed, remove the old device
1095 * info and add the new device info.
bd9244f7
ST		 1096 * If minor device attributes change, just update
1097 * the existing device structure.
edd16368
SC		 1098 */
1099 i = 0;
1100 nremoved = 0;
1101 nadded = 0;
1102 while (i < h->ndevices) {
1103 csd = h->dev[i];
1104 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1105 if (device_change == DEVICE_NOT_FOUND) {
1106 changes++;
1107 hpsa_scsi_remove_entry(h, hostno, i,
1108 removed, &nremoved);
1109 continue; /* remove ^^^, hence i not incremented */
1110 } else if (device_change == DEVICE_CHANGED) {
1111 changes++;
2a8ccf31
SC		 1112 hpsa_scsi_replace_entry(h, hostno, i, sd[entry],
1113 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1114 /* Set it to NULL to prevent it from being freed
1115 * at the bottom of hpsa_update_scsi_devices()
1116 */
1117 sd[entry] = NULL;
bd9244f7
ST		 1118 } else if (device_change == DEVICE_UPDATED) {
1119 hpsa_scsi_update_entry(h, hostno, i, sd[entry]);
edd16368
SC		 1120 }
1121 i++;
1122 }
1123
1124 /* Now, make sure every device listed in sd[] is also
1125 * listed in h->dev[], adding them if they aren't found
1126 */
1127
1128 for (i = 0; i < nsds; i++) {
1129 if (!sd[i]) /* if already added above. */
1130 continue;
1131 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1132 h->ndevices, &entry);
1133 if (device_change == DEVICE_NOT_FOUND) {
1134 changes++;
1135 if (hpsa_scsi_add_entry(h, hostno, sd[i],
1136 added, &nadded) != 0)
1137 break;
1138 sd[i] = NULL; /* prevent from being freed later. */
1139 } else if (device_change == DEVICE_CHANGED) {
1140 /* should never happen... */
1141 changes++;
1142 dev_warn(&h->pdev->dev,
1143 "device unexpectedly changed.\n");
1144 /* but if it does happen, we just ignore that device */
1145 }
1146 }
1147 spin_unlock_irqrestore(&h->devlock, flags);
1148
1149 /* Don't notify scsi mid layer of any changes the first time through
1150 * (or if there are no changes) scsi_scan_host will do it later the
1151 * first time through.
1152 */
1153 if (hostno == -1 || !changes)
1154 goto free_and_out;
1155
1156 sh = h->scsi_host;
1157 /* Notify scsi mid layer of any removed devices */
1158 for (i = 0; i < nremoved; i++) {
1159 struct scsi_device *sdev =
1160 scsi_device_lookup(sh, removed[i]->bus,
1161 removed[i]->target, removed[i]->lun);
1162 if (sdev != NULL) {
1163 scsi_remove_device(sdev);
1164 scsi_device_put(sdev);
1165 } else {
1166 /* We don't expect to get here.
1167 * future cmds to this device will get selection
1168 * timeout as if the device was gone.
1169 */
1170 dev_warn(&h->pdev->dev, "didn't find c%db%dt%dl%d "
1171 " for removal.", hostno, removed[i]->bus,
1172 removed[i]->target, removed[i]->lun);
1173 }
1174 kfree(removed[i]);
1175 removed[i] = NULL;
1176 }
1177
1178 /* Notify scsi mid layer of any added devices */
1179 for (i = 0; i < nadded; i++) {
1180 if (scsi_add_device(sh, added[i]->bus,
1181 added[i]->target, added[i]->lun) == 0)
1182 continue;
1183 dev_warn(&h->pdev->dev, "scsi_add_device c%db%dt%dl%d failed, "
1184 "device not added.\n", hostno, added[i]->bus,
1185 added[i]->target, added[i]->lun);
1186 /* now we have to remove it from h->dev,
1187 * since it didn't get added to scsi mid layer
1188 */
1189 fixup_botched_add(h, added[i]);
1190 }
1191
1192free_and_out:
1193 kfree(added);
1194 kfree(removed);
edd16368
SC		 1195}
1196
1197/*
9e03aa2f 1198 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 1199 * Assume's h->devlock is held.
1200 */
1201static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
1202 int bus, int target, int lun)
1203{
1204 int i;
1205 struct hpsa_scsi_dev_t *sd;
1206
1207 for (i = 0; i < h->ndevices; i++) {
1208 sd = h->dev[i];
1209 if (sd->bus == bus && sd->target == target && sd->lun == lun)
1210 return sd;
1211 }
1212 return NULL;
1213}
1214
1215/* link sdev->hostdata to our per-device structure. */
1216static int hpsa_slave_alloc(struct scsi_device *sdev)
1217{
1218 struct hpsa_scsi_dev_t *sd;
1219 unsigned long flags;
1220 struct ctlr_info *h;
1221
1222 h = sdev_to_hba(sdev);
1223 spin_lock_irqsave(&h->devlock, flags);
1224 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
1225 sdev_id(sdev), sdev->lun);
1226 if (sd != NULL)
1227 sdev->hostdata = sd;
1228 spin_unlock_irqrestore(&h->devlock, flags);
1229 return 0;
1230}
1231
1232static void hpsa_slave_destroy(struct scsi_device *sdev)
1233{
bcc44255 1234 /* nothing to do. */
edd16368
SC		 1235}
1236
33a2ffce
SC		 1237static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
1238{
1239 int i;
1240
1241 if (!h->cmd_sg_list)
1242 return;
1243 for (i = 0; i < h->nr_cmds; i++) {
1244 kfree(h->cmd_sg_list[i]);
1245 h->cmd_sg_list[i] = NULL;
1246 }
1247 kfree(h->cmd_sg_list);
1248 h->cmd_sg_list = NULL;
1249}
1250
1251static int hpsa_allocate_sg_chain_blocks(struct ctlr_info *h)
1252{
1253 int i;
1254
1255 if (h->chainsize <= 0)
1256 return 0;
1257
1258 h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
1259 GFP_KERNEL);
1260 if (!h->cmd_sg_list)
1261 return -ENOMEM;
1262 for (i = 0; i < h->nr_cmds; i++) {
1263 h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
1264 h->chainsize, GFP_KERNEL);
1265 if (!h->cmd_sg_list[i])
1266 goto clean;
1267 }
1268 return 0;
1269
1270clean:
1271 hpsa_free_sg_chain_blocks(h);
1272 return -ENOMEM;
1273}
1274
e2bea6df 1275static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 1276 struct CommandList *c)
1277{
1278 struct SGDescriptor *chain_sg, *chain_block;
1279 u64 temp64;
1280
1281 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1282 chain_block = h->cmd_sg_list[c->cmdindex];
1283 chain_sg->Ext = HPSA_SG_CHAIN;
1284 chain_sg->Len = sizeof(*chain_sg) *
1285 (c->Header.SGTotal - h->max_cmd_sg_entries);
1286 temp64 = pci_map_single(h->pdev, chain_block, chain_sg->Len,
1287 PCI_DMA_TODEVICE);
e2bea6df
SC		 1288 if (dma_mapping_error(&h->pdev->dev, temp64)) {
1289 /* prevent subsequent unmapping */
1290 chain_sg->Addr.lower = 0;
1291 chain_sg->Addr.upper = 0;
1292 return -1;
1293 }
33a2ffce
SC		 1294 chain_sg->Addr.lower = (u32) (temp64 & 0x0FFFFFFFFULL);
1295 chain_sg->Addr.upper = (u32) ((temp64 >> 32) & 0x0FFFFFFFFULL);
e2bea6df 1296 return 0;
33a2ffce
SC		 1297}
1298
1299static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
1300 struct CommandList *c)
1301{
1302 struct SGDescriptor *chain_sg;
1303 union u64bit temp64;
1304
1305 if (c->Header.SGTotal <= h->max_cmd_sg_entries)
1306 return;
1307
1308 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
1309 temp64.val32.lower = chain_sg->Addr.lower;
1310 temp64.val32.upper = chain_sg->Addr.upper;
1311 pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
1312}
1313
c349775e
ST		 1314static void handle_ioaccel_mode2_error(struct ctlr_info *h,
1315 struct CommandList *c,
1316 struct scsi_cmnd *cmd,
1317 struct io_accel2_cmd *c2)
1318{
1319 int data_len;
1320
1321 switch (c2->error_data.serv_response) {
1322 case IOACCEL2_SERV_RESPONSE_COMPLETE:
1323 switch (c2->error_data.status) {
1324 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
1325 break;
1326 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
1327 dev_warn(&h->pdev->dev,
1328 "%s: task complete with check condition.\n",
1329 "HP SSD Smart Path");
1330 if (c2->error_data.data_present !=
1331 IOACCEL2_SENSE_DATA_PRESENT)
1332 break;
1333 /* copy the sense data */
1334 data_len = c2->error_data.sense_data_len;
1335 if (data_len > SCSI_SENSE_BUFFERSIZE)
1336 data_len = SCSI_SENSE_BUFFERSIZE;
1337 if (data_len > sizeof(c2->error_data.sense_data_buff))
1338 data_len =
1339 sizeof(c2->error_data.sense_data_buff);
1340 memcpy(cmd->sense_buffer,
1341 c2->error_data.sense_data_buff, data_len);
1342 cmd->result |= SAM_STAT_CHECK_CONDITION;
1343 break;
1344 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
1345 dev_warn(&h->pdev->dev,
1346 "%s: task complete with BUSY status.\n",
1347 "HP SSD Smart Path");
1348 break;
1349 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
1350 dev_warn(&h->pdev->dev,
1351 "%s: task complete with reservation conflict.\n",
1352 "HP SSD Smart Path");
1353 break;
1354 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
1355 /* Make scsi midlayer do unlimited retries */
1356 cmd->result = DID_IMM_RETRY << 16;
1357 break;
1358 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
1359 dev_warn(&h->pdev->dev,
1360 "%s: task complete with aborted status.\n",
1361 "HP SSD Smart Path");
1362 break;
1363 default:
1364 dev_warn(&h->pdev->dev,
1365 "%s: task complete with unrecognized status: 0x%02x\n",
1366 "HP SSD Smart Path", c2->error_data.status);
1367 break;
1368 }
1369 break;
1370 case IOACCEL2_SERV_RESPONSE_FAILURE:
1371 /* don't expect to get here. */
1372 dev_warn(&h->pdev->dev,
1373 "unexpected delivery or target failure, status = 0x%02x\n",
1374 c2->error_data.status);
1375 break;
1376 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
1377 break;
1378 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
1379 break;
1380 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
1381 dev_warn(&h->pdev->dev, "task management function rejected.\n");
1382 break;
1383 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
1384 dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
1385 break;
1386 default:
1387 dev_warn(&h->pdev->dev,
1388 "%s: Unrecognized server response: 0x%02x\n",
1389 "HP SSD Smart Path", c2->error_data.serv_response);
1390 break;
1391 }
1392}
1393
1394static void process_ioaccel2_completion(struct ctlr_info *h,
1395 struct CommandList *c, struct scsi_cmnd *cmd,
1396 struct hpsa_scsi_dev_t *dev)
1397{
1398 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
1399
1400 /* check for good status */
1401 if (likely(c2->error_data.serv_response == 0 &&
1402 c2->error_data.status == 0)) {
1403 cmd_free(h, c);
1404 cmd->scsi_done(cmd);
1405 return;
1406 }
1407
1408 /* Any RAID offload error results in retry which will use
1409 * the normal I/O path so the controller can handle whatever's
1410 * wrong.
1411 */
1412 if (is_logical_dev_addr_mode(dev->scsi3addr) &&
1413 c2->error_data.serv_response ==
1414 IOACCEL2_SERV_RESPONSE_FAILURE) {
1415 if (c2->error_data.status !=
1416 IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
1417 dev_warn(&h->pdev->dev,
1418 "%s: Error 0x%02x, Retrying on standard path.\n",
1419 "HP SSD Smart Path", c2->error_data.status);
1420 dev->offload_enabled = 0;
1421 cmd->result = DID_SOFT_ERROR << 16;
1422 cmd_free(h, c);
1423 cmd->scsi_done(cmd);
1424 return;
1425 }
1426 handle_ioaccel_mode2_error(h, c, cmd, c2);
1427 cmd_free(h, c);
1428 cmd->scsi_done(cmd);
1429}
1430
1fb011fb 1431static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 1432{
1433 struct scsi_cmnd *cmd;
1434 struct ctlr_info *h;
1435 struct ErrorInfo *ei;
283b4a9b 1436 struct hpsa_scsi_dev_t *dev;
edd16368
SC		 1437
1438 unsigned char sense_key;
1439 unsigned char asc; /* additional sense code */
1440 unsigned char ascq; /* additional sense code qualifier */
db111e18 1441 unsigned long sense_data_size;
edd16368
SC		 1442
1443 ei = cp->err_info;
1444 cmd = (struct scsi_cmnd *) cp->scsi_cmd;
1445 h = cp->h;
283b4a9b 1446 dev = cmd->device->hostdata;
edd16368
SC		 1447
1448 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c
MG		 1449 if ((cp->cmd_type == CMD_SCSI) &&
1450 (cp->Header.SGTotal > h->max_cmd_sg_entries))
33a2ffce 1451 hpsa_unmap_sg_chain_block(h, cp);
edd16368
SC		 1452
1453 cmd->result = (DID_OK << 16); /* host byte */
1454 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e
ST		 1455
1456 if (cp->cmd_type == CMD_IOACCEL2)
1457 return process_ioaccel2_completion(h, cp, cmd, dev);
1458
5512672f 1459 cmd->result |= ei->ScsiStatus;
edd16368
SC		 1460
1461 /* copy the sense data whether we need to or not. */
db111e18
SC		 1462 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
1463 sense_data_size = SCSI_SENSE_BUFFERSIZE;
1464 else
1465 sense_data_size = sizeof(ei->SenseInfo);
1466 if (ei->SenseLen < sense_data_size)
1467 sense_data_size = ei->SenseLen;
1468
1469 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
edd16368
SC		 1470 scsi_set_resid(cmd, ei->ResidualCnt);
1471
1472 if (ei->CommandStatus == 0) {
edd16368 1473 cmd_free(h, cp);
2cc5bfaf 1474 cmd->scsi_done(cmd);
edd16368
SC		 1475 return;
1476 }
1477
e1f7de0c
MG		 1478 /* For I/O accelerator commands, copy over some fields to the normal
1479 * CISS header used below for error handling.
1480 */
1481 if (cp->cmd_type == CMD_IOACCEL1) {
1482 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
1483 cp->Header.SGList = cp->Header.SGTotal = scsi_sg_count(cmd);
1484 cp->Request.CDBLen = c->io_flags & IOACCEL1_IOFLAGS_CDBLEN_MASK;
1485 cp->Header.Tag.lower = c->Tag.lower;
1486 cp->Header.Tag.upper = c->Tag.upper;
1487 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
1488 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 1489
1490 /* Any RAID offload error results in retry which will use
1491 * the normal I/O path so the controller can handle whatever's
1492 * wrong.
1493 */
1494 if (is_logical_dev_addr_mode(dev->scsi3addr)) {
1495 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
1496 dev->offload_enabled = 0;
1497 cmd->result = DID_SOFT_ERROR << 16;
1498 cmd_free(h, cp);
1499 cmd->scsi_done(cmd);
1500 return;
1501 }
e1f7de0c
MG		 1502 }
1503
edd16368
SC		 1504 /* an error has occurred */
1505 switch (ei->CommandStatus) {
1506
1507 case CMD_TARGET_STATUS:
1508 if (ei->ScsiStatus) {
1509 /* Get sense key */
1510 sense_key = 0xf & ei->SenseInfo[2];
1511 /* Get additional sense code */
1512 asc = ei->SenseInfo[12];
1513 /* Get addition sense code qualifier */
1514 ascq = ei->SenseInfo[13];
1515 }
1516
1517 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
3ce438df 1518 if (check_for_unit_attention(h, cp))
edd16368 1519 break;
edd16368
SC		 1520 if (sense_key == ILLEGAL_REQUEST) {
1521 /*
1522 * SCSI REPORT_LUNS is commonly unsupported on
1523 * Smart Array. Suppress noisy complaint.
1524 */
1525 if (cp->Request.CDB[0] == REPORT_LUNS)
1526 break;
1527
1528 /* If ASC/ASCQ indicate Logical Unit
1529 * Not Supported condition,
1530 */
1531 if ((asc == 0x25) && (ascq == 0x0)) {
1532 dev_warn(&h->pdev->dev, "cp %p "
1533 "has check condition\n", cp);
1534 break;
1535 }
1536 }
1537
1538 if (sense_key == NOT_READY) {
1539 /* If Sense is Not Ready, Logical Unit
1540 * Not ready, Manual Intervention
1541 * required
1542 */
1543 if ((asc == 0x04) && (ascq == 0x03)) {
edd16368
SC		 1544 dev_warn(&h->pdev->dev, "cp %p "
1545 "has check condition: unit "
1546 "not ready, manual "
1547 "intervention required\n", cp);
1548 break;
1549 }
1550 }
1d3b3609
MG		 1551 if (sense_key == ABORTED_COMMAND) {
1552 /* Aborted command is retryable */
1553 dev_warn(&h->pdev->dev, "cp %p "
1554 "has check condition: aborted command: "
1555 "ASC: 0x%x, ASCQ: 0x%x\n",
1556 cp, asc, ascq);
2e311fba 1557 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609
MG		 1558 break;
1559 }
edd16368 1560 /* Must be some other type of check condition */
21b8e4ef 1561 dev_dbg(&h->pdev->dev, "cp %p has check condition: "
edd16368
SC		 1562 "unknown type: "
1563 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1564 "Returning result: 0x%x, "
1565 "cmd=[%02x %02x %02x %02x %02x "
807be732 1566 "%02x %02x %02x %02x %02x %02x "
edd16368
SC		 1567 "%02x %02x %02x %02x %02x]\n",
1568 cp, sense_key, asc, ascq,
1569 cmd->result,
1570 cmd->cmnd[0], cmd->cmnd[1],
1571 cmd->cmnd[2], cmd->cmnd[3],
1572 cmd->cmnd[4], cmd->cmnd[5],
1573 cmd->cmnd[6], cmd->cmnd[7],
807be732
MM		 1574 cmd->cmnd[8], cmd->cmnd[9],
1575 cmd->cmnd[10], cmd->cmnd[11],
1576 cmd->cmnd[12], cmd->cmnd[13],
1577 cmd->cmnd[14], cmd->cmnd[15]);
edd16368
SC		 1578 break;
1579 }
1580
1581
1582 /* Problem was not a check condition
1583 * Pass it up to the upper layers...
1584 */
1585 if (ei->ScsiStatus) {
1586 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
1587 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
1588 "Returning result: 0x%x\n",
1589 cp, ei->ScsiStatus,
1590 sense_key, asc, ascq,
1591 cmd->result);
1592 } else { /* scsi status is zero??? How??? */
1593 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
1594 "Returning no connection.\n", cp),
1595
1596 /* Ordinarily, this case should never happen,
1597 * but there is a bug in some released firmware
1598 * revisions that allows it to happen if, for
1599 * example, a 4100 backplane loses power and
1600 * the tape drive is in it. We assume that
1601 * it's a fatal error of some kind because we
1602 * can't show that it wasn't. We will make it
1603 * look like selection timeout since that is
1604 * the most common reason for this to occur,
1605 * and it's severe enough.
1606 */
1607
1608 cmd->result = DID_NO_CONNECT << 16;
1609 }
1610 break;
1611
1612 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1613 break;
1614 case CMD_DATA_OVERRUN:
1615 dev_warn(&h->pdev->dev, "cp %p has"
1616 " completed with data overrun "
1617 "reported\n", cp);
1618 break;
1619 case CMD_INVALID: {
1620 /* print_bytes(cp, sizeof(*cp), 1, 0);
1621 print_cmd(cp); */
1622 /* We get CMD_INVALID if you address a non-existent device
1623 * instead of a selection timeout (no response). You will
1624 * see this if you yank out a drive, then try to access it.
1625 * This is kind of a shame because it means that any other
1626 * CMD_INVALID (e.g. driver bug) will get interpreted as a
1627 * missing target. */
1628 cmd->result = DID_NO_CONNECT << 16;
1629 }
1630 break;
1631 case CMD_PROTOCOL_ERR:
256d0eaa 1632 cmd->result = DID_ERROR << 16;
edd16368 1633 dev_warn(&h->pdev->dev, "cp %p has "
256d0eaa 1634 "protocol error\n", cp);
edd16368
SC		 1635 break;
1636 case CMD_HARDWARE_ERR:
1637 cmd->result = DID_ERROR << 16;
1638 dev_warn(&h->pdev->dev, "cp %p had hardware error\n", cp);
1639 break;
1640 case CMD_CONNECTION_LOST:
1641 cmd->result = DID_ERROR << 16;
1642 dev_warn(&h->pdev->dev, "cp %p had connection lost\n", cp);
1643 break;
1644 case CMD_ABORTED:
1645 cmd->result = DID_ABORT << 16;
1646 dev_warn(&h->pdev->dev, "cp %p was aborted with status 0x%x\n",
1647 cp, ei->ScsiStatus);
1648 break;
1649 case CMD_ABORT_FAILED:
1650 cmd->result = DID_ERROR << 16;
1651 dev_warn(&h->pdev->dev, "cp %p reports abort failed\n", cp);
1652 break;
1653 case CMD_UNSOLICITED_ABORT:
f6e76055
SC		 1654 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
1655 dev_warn(&h->pdev->dev, "cp %p aborted due to an unsolicited "
edd16368
SC		 1656 "abort\n", cp);
1657 break;
1658 case CMD_TIMEOUT:
1659 cmd->result = DID_TIME_OUT << 16;
1660 dev_warn(&h->pdev->dev, "cp %p timedout\n", cp);
1661 break;
1d5e2ed0
SC		 1662 case CMD_UNABORTABLE:
1663 cmd->result = DID_ERROR << 16;
1664 dev_warn(&h->pdev->dev, "Command unabortable\n");
1665 break;
283b4a9b
SC		 1666 case CMD_IOACCEL_DISABLED:
1667 /* This only handles the direct pass-through case since RAID
1668 * offload is handled above. Just attempt a retry.
1669 */
1670 cmd->result = DID_SOFT_ERROR << 16;
1671 dev_warn(&h->pdev->dev,
1672 "cp %p had HP SSD Smart Path error\n", cp);
1673 break;
edd16368
SC		 1674 default:
1675 cmd->result = DID_ERROR << 16;
1676 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
1677 cp, ei->CommandStatus);
1678 }
edd16368 1679 cmd_free(h, cp);
2cc5bfaf 1680 cmd->scsi_done(cmd);
edd16368
SC		 1681}
1682
edd16368
SC		 1683static void hpsa_pci_unmap(struct pci_dev *pdev,
1684 struct CommandList *c, int sg_used, int data_direction)
1685{
1686 int i;
1687 union u64bit addr64;
1688
1689 for (i = 0; i < sg_used; i++) {
1690 addr64.val32.lower = c->SG[i].Addr.lower;
1691 addr64.val32.upper = c->SG[i].Addr.upper;
1692 pci_unmap_single(pdev, (dma_addr_t) addr64.val, c->SG[i].Len,
1693 data_direction);
1694 }
1695}
1696
a2dac136 1697static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 1698 struct CommandList *cp,
1699 unsigned char *buf,
1700 size_t buflen,
1701 int data_direction)
1702{
01a02ffc 1703 u64 addr64;
edd16368
SC		 1704
1705 if (buflen == 0 || data_direction == PCI_DMA_NONE) {
1706 cp->Header.SGList = 0;
1707 cp->Header.SGTotal = 0;
a2dac136 1708 return 0;
edd16368
SC		 1709 }
1710
01a02ffc 1711 addr64 = (u64) pci_map_single(pdev, buf, buflen, data_direction);
eceaae18 1712 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 1713 /* Prevent subsequent unmap of something never mapped */
eceaae18
SK		 1714 cp->Header.SGList = 0;
1715 cp->Header.SGTotal = 0;
a2dac136 1716 return -1;
eceaae18 1717 }
edd16368 1718 cp->SG[0].Addr.lower =
01a02ffc 1719 (u32) (addr64 & (u64) 0x00000000FFFFFFFF);
edd16368 1720 cp->SG[0].Addr.upper =
01a02ffc 1721 (u32) ((addr64 >> 32) & (u64) 0x00000000FFFFFFFF);
edd16368 1722 cp->SG[0].Len = buflen;
e1d9cbfa 1723 cp->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining */
01a02ffc
SC		 1724 cp->Header.SGList = (u8) 1; /* no. SGs contig in this cmd */
1725 cp->Header.SGTotal = (u16) 1; /* total sgs in this cmd list */
a2dac136 1726 return 0;
edd16368
SC		 1727}
1728
1729static inline void hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
1730 struct CommandList *c)
1731{
1732 DECLARE_COMPLETION_ONSTACK(wait);
1733
1734 c->waiting = &wait;
1735 enqueue_cmd_and_start_io(h, c);
1736 wait_for_completion(&wait);
1737}
1738
a0c12413
SC		 1739static void hpsa_scsi_do_simple_cmd_core_if_no_lockup(struct ctlr_info *h,
1740 struct CommandList *c)
1741{
1742 unsigned long flags;
1743
1744 /* If controller lockup detected, fake a hardware error. */
1745 spin_lock_irqsave(&h->lock, flags);
1746 if (unlikely(h->lockup_detected)) {
1747 spin_unlock_irqrestore(&h->lock, flags);
1748 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
1749 } else {
1750 spin_unlock_irqrestore(&h->lock, flags);
1751 hpsa_scsi_do_simple_cmd_core(h, c);
1752 }
1753}
1754
9c2fc160 1755#define MAX_DRIVER_CMD_RETRIES 25
edd16368
SC		 1756static void hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
1757 struct CommandList *c, int data_direction)
1758{
9c2fc160 1759 int backoff_time = 10, retry_count = 0;
edd16368
SC		 1760
1761 do {
7630abd0 1762 memset(c->err_info, 0, sizeof(*c->err_info));
edd16368
SC		 1763 hpsa_scsi_do_simple_cmd_core(h, c);
1764 retry_count++;
9c2fc160
SC		 1765 if (retry_count > 3) {
1766 msleep(backoff_time);
1767 if (backoff_time < 1000)
1768 backoff_time *= 2;
1769 }
852af20a 1770 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 1771 check_for_busy(h, c)) &&
1772 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368
SC		 1773 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
1774}
1775
1776static void hpsa_scsi_interpret_error(struct CommandList *cp)
1777{
1778 struct ErrorInfo *ei;
1779 struct device *d = &cp->h->pdev->dev;
1780
1781 ei = cp->err_info;
1782 switch (ei->CommandStatus) {
1783 case CMD_TARGET_STATUS:
1784 dev_warn(d, "cmd %p has completed with errors\n", cp);
1785 dev_warn(d, "cmd %p has SCSI Status = %x\n", cp,
1786 ei->ScsiStatus);
1787 if (ei->ScsiStatus == 0)
1788 dev_warn(d, "SCSI status is abnormally zero. "
1789 "(probably indicates selection timeout "
1790 "reported incorrectly due to a known "
1791 "firmware bug, circa July, 2001.)\n");
1792 break;
1793 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
1794 dev_info(d, "UNDERRUN\n");
1795 break;
1796 case CMD_DATA_OVERRUN:
1797 dev_warn(d, "cp %p has completed with data overrun\n", cp);
1798 break;
1799 case CMD_INVALID: {
1800 /* controller unfortunately reports SCSI passthru's
1801 * to non-existent targets as invalid commands.
1802 */
1803 dev_warn(d, "cp %p is reported invalid (probably means "
1804 "target device no longer present)\n", cp);
1805 /* print_bytes((unsigned char *) cp, sizeof(*cp), 1, 0);
1806 print_cmd(cp); */
1807 }
1808 break;
1809 case CMD_PROTOCOL_ERR:
1810 dev_warn(d, "cp %p has protocol error \n", cp);
1811 break;
1812 case CMD_HARDWARE_ERR:
1813 /* cmd->result = DID_ERROR << 16; */
1814 dev_warn(d, "cp %p had hardware error\n", cp);
1815 break;
1816 case CMD_CONNECTION_LOST:
1817 dev_warn(d, "cp %p had connection lost\n", cp);
1818 break;
1819 case CMD_ABORTED:
1820 dev_warn(d, "cp %p was aborted\n", cp);
1821 break;
1822 case CMD_ABORT_FAILED:
1823 dev_warn(d, "cp %p reports abort failed\n", cp);
1824 break;
1825 case CMD_UNSOLICITED_ABORT:
1826 dev_warn(d, "cp %p aborted due to an unsolicited abort\n", cp);
1827 break;
1828 case CMD_TIMEOUT:
1829 dev_warn(d, "cp %p timed out\n", cp);
1830 break;
1d5e2ed0
SC		 1831 case CMD_UNABORTABLE:
1832 dev_warn(d, "Command unabortable\n");
1833 break;
edd16368
SC		 1834 default:
1835 dev_warn(d, "cp %p returned unknown status %x\n", cp,
1836 ei->CommandStatus);
1837 }
1838}
1839
1840static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
1841 unsigned char page, unsigned char *buf,
1842 unsigned char bufsize)
1843{
1844 int rc = IO_OK;
1845 struct CommandList *c;
1846 struct ErrorInfo *ei;
1847
1848 c = cmd_special_alloc(h);
1849
1850 if (c == NULL) { /* trouble... */
1851 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
ecd9aad4 1852 return -ENOMEM;
edd16368
SC		 1853 }
1854
a2dac136
SC		 1855 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
1856 page, scsi3addr, TYPE_CMD)) {
1857 rc = -1;
1858 goto out;
1859 }
edd16368
SC		 1860 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
1861 ei = c->err_info;
1862 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
1863 hpsa_scsi_interpret_error(c);
1864 rc = -1;
1865 }
a2dac136 1866out:
edd16368
SC		 1867 cmd_special_free(h, c);
1868 return rc;
1869}
1870
bf711ac6
ST		 1871static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
1872 u8 reset_type)
edd16368
SC		 1873{
1874 int rc = IO_OK;
1875 struct CommandList *c;
1876 struct ErrorInfo *ei;
1877
1878 c = cmd_special_alloc(h);
1879
1880 if (c == NULL) { /* trouble... */
1881 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
e9ea04a6 1882 return -ENOMEM;
edd16368
SC		 1883 }
1884
a2dac136 1885 /* fill_cmd can't fail here, no data buffer to map. */
bf711ac6
ST		 1886 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
1887 scsi3addr, TYPE_MSG);
1888 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to LUN reset */
edd16368
SC		 1889 hpsa_scsi_do_simple_cmd_core(h, c);
1890 /* no unmap needed here because no data xfer. */
1891
1892 ei = c->err_info;
1893 if (ei->CommandStatus != 0) {
1894 hpsa_scsi_interpret_error(c);
1895 rc = -1;
1896 }
1897 cmd_special_free(h, c);
1898 return rc;
1899}
1900
1901static void hpsa_get_raid_level(struct ctlr_info *h,
1902 unsigned char *scsi3addr, unsigned char *raid_level)
1903{
1904 int rc;
1905 unsigned char *buf;
1906
1907 *raid_level = RAID_UNKNOWN;
1908 buf = kzalloc(64, GFP_KERNEL);
1909 if (!buf)
1910 return;
1911 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0xC1, buf, 64);
1912 if (rc == 0)
1913 *raid_level = buf[8];
1914 if (*raid_level > RAID_UNKNOWN)
1915 *raid_level = RAID_UNKNOWN;
1916 kfree(buf);
1917 return;
1918}
1919
283b4a9b
SC		 1920#define HPSA_MAP_DEBUG
1921#ifdef HPSA_MAP_DEBUG
1922static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
1923 struct raid_map_data *map_buff)
1924{
1925 struct raid_map_disk_data *dd = &map_buff->data[0];
1926 int map, row, col;
1927 u16 map_cnt, row_cnt, disks_per_row;
1928
1929 if (rc != 0)
1930 return;
1931
1932 dev_info(&h->pdev->dev, "structure_size = %u\n",
1933 le32_to_cpu(map_buff->structure_size));
1934 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
1935 le32_to_cpu(map_buff->volume_blk_size));
1936 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
1937 le64_to_cpu(map_buff->volume_blk_cnt));
1938 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
1939 map_buff->phys_blk_shift);
1940 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
1941 map_buff->parity_rotation_shift);
1942 dev_info(&h->pdev->dev, "strip_size = %u\n",
1943 le16_to_cpu(map_buff->strip_size));
1944 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
1945 le64_to_cpu(map_buff->disk_starting_blk));
1946 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
1947 le64_to_cpu(map_buff->disk_blk_cnt));
1948 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
1949 le16_to_cpu(map_buff->data_disks_per_row));
1950 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
1951 le16_to_cpu(map_buff->metadata_disks_per_row));
1952 dev_info(&h->pdev->dev, "row_cnt = %u\n",
1953 le16_to_cpu(map_buff->row_cnt));
1954 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
1955 le16_to_cpu(map_buff->layout_map_count));
1956
1957 map_cnt = le16_to_cpu(map_buff->layout_map_count);
1958 for (map = 0; map < map_cnt; map++) {
1959 dev_info(&h->pdev->dev, "Map%u:\n", map);
1960 row_cnt = le16_to_cpu(map_buff->row_cnt);
1961 for (row = 0; row < row_cnt; row++) {
1962 dev_info(&h->pdev->dev, " Row%u:\n", row);
1963 disks_per_row =
1964 le16_to_cpu(map_buff->data_disks_per_row);
1965 for (col = 0; col < disks_per_row; col++, dd++)
1966 dev_info(&h->pdev->dev,
1967 " D%02u: h=0x%04x xor=%u,%u\n",
1968 col, dd->ioaccel_handle,
1969 dd->xor_mult[0], dd->xor_mult[1]);
1970 disks_per_row =
1971 le16_to_cpu(map_buff->metadata_disks_per_row);
1972 for (col = 0; col < disks_per_row; col++, dd++)
1973 dev_info(&h->pdev->dev,
1974 " M%02u: h=0x%04x xor=%u,%u\n",
1975 col, dd->ioaccel_handle,
1976 dd->xor_mult[0], dd->xor_mult[1]);
1977 }
1978 }
1979}
1980#else
1981static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
1982 __attribute__((unused)) int rc,
1983 __attribute__((unused)) struct raid_map_data *map_buff)
1984{
1985}
1986#endif
1987
1988static int hpsa_get_raid_map(struct ctlr_info *h,
1989 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
1990{
1991 int rc = 0;
1992 struct CommandList *c;
1993 struct ErrorInfo *ei;
1994
1995 c = cmd_special_alloc(h);
1996 if (c == NULL) {
1997 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
1998 return -ENOMEM;
1999 }
2000 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
2001 sizeof(this_device->raid_map), 0,
2002 scsi3addr, TYPE_CMD)) {
2003 dev_warn(&h->pdev->dev, "Out of memory in hpsa_get_raid_map()\n");
2004 cmd_special_free(h, c);
2005 return -ENOMEM;
2006 }
2007 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2008 ei = c->err_info;
2009 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2010 hpsa_scsi_interpret_error(c);
2011 cmd_special_free(h, c);
2012 return -1;
2013 }
2014 cmd_special_free(h, c);
2015
2016 /* @todo in the future, dynamically allocate RAID map memory */
2017 if (le32_to_cpu(this_device->raid_map.structure_size) >
2018 sizeof(this_device->raid_map)) {
2019 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
2020 rc = -1;
2021 }
2022 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
2023 return rc;
2024}
2025
2026static void hpsa_get_ioaccel_status(struct ctlr_info *h,
2027 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
2028{
2029 int rc;
2030 unsigned char *buf;
2031 u8 ioaccel_status;
2032
2033 this_device->offload_config = 0;
2034 this_device->offload_enabled = 0;
2035
2036 buf = kzalloc(64, GFP_KERNEL);
2037 if (!buf)
2038 return;
2039 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
2040 HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
2041 if (rc != 0)
2042 goto out;
2043
2044#define IOACCEL_STATUS_BYTE 4
2045#define OFFLOAD_CONFIGURED_BIT 0x01
2046#define OFFLOAD_ENABLED_BIT 0x02
2047 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
2048 this_device->offload_config =
2049 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
2050 if (this_device->offload_config) {
2051 this_device->offload_enabled =
2052 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
2053 if (hpsa_get_raid_map(h, scsi3addr, this_device))
2054 this_device->offload_enabled = 0;
2055 }
2056out:
2057 kfree(buf);
2058 return;
2059}
2060
edd16368
SC		 2061/* Get the device id from inquiry page 0x83 */
2062static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
2063 unsigned char *device_id, int buflen)
2064{
2065 int rc;
2066 unsigned char *buf;
2067
2068 if (buflen > 16)
2069 buflen = 16;
2070 buf = kzalloc(64, GFP_KERNEL);
2071 if (!buf)
2072 return -1;
2073 rc = hpsa_scsi_do_inquiry(h, scsi3addr, 0x83, buf, 64);
2074 if (rc == 0)
2075 memcpy(device_id, &buf[8], buflen);
2076 kfree(buf);
2077 return rc != 0;
2078}
2079
2080static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
2081 struct ReportLUNdata *buf, int bufsize,
2082 int extended_response)
2083{
2084 int rc = IO_OK;
2085 struct CommandList *c;
2086 unsigned char scsi3addr[8];
2087 struct ErrorInfo *ei;
2088
2089 c = cmd_special_alloc(h);
2090 if (c == NULL) { /* trouble... */
2091 dev_err(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
2092 return -1;
2093 }
e89c0ae7
SC		 2094 /* address the controller */
2095 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 2096 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
2097 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
2098 rc = -1;
2099 goto out;
2100 }
edd16368
SC		 2101 if (extended_response)
2102 c->Request.CDB[1] = extended_response;
2103 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE);
2104 ei = c->err_info;
2105 if (ei->CommandStatus != 0 &&
2106 ei->CommandStatus != CMD_DATA_UNDERRUN) {
2107 hpsa_scsi_interpret_error(c);
2108 rc = -1;
283b4a9b
SC		 2109 } else {
2110 if (buf->extended_response_flag != extended_response) {
2111 dev_err(&h->pdev->dev,
2112 "report luns requested format %u, got %u\n",
2113 extended_response,
2114 buf->extended_response_flag);
2115 rc = -1;
2116 }
edd16368 2117 }
a2dac136 2118out:
edd16368
SC		 2119 cmd_special_free(h, c);
2120 return rc;
2121}
2122
2123static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
2124 struct ReportLUNdata *buf,
2125 int bufsize, int extended_response)
2126{
2127 return hpsa_scsi_do_report_luns(h, 0, buf, bufsize, extended_response);
2128}
2129
2130static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
2131 struct ReportLUNdata *buf, int bufsize)
2132{
2133 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
2134}
2135
2136static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
2137 int bus, int target, int lun)
2138{
2139 device->bus = bus;
2140 device->target = target;
2141 device->lun = lun;
2142}
2143
2144static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 2145 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
2146 unsigned char *is_OBDR_device)
edd16368 2147{
0b0e1d6c
SC		 2148
2149#define OBDR_SIG_OFFSET 43
2150#define OBDR_TAPE_SIG "$DR-10"
2151#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
2152#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
2153
ea6d3bc3 2154 unsigned char *inq_buff;
0b0e1d6c 2155 unsigned char *obdr_sig;
edd16368 2156
ea6d3bc3 2157 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
edd16368
SC		 2158 if (!inq_buff)
2159 goto bail_out;
2160
edd16368
SC		 2161 /* Do an inquiry to the device to see what it is. */
2162 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
2163 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
2164 /* Inquiry failed (msg printed already) */
2165 dev_err(&h->pdev->dev,
2166 "hpsa_update_device_info: inquiry failed\n");
2167 goto bail_out;
2168 }
2169
edd16368
SC		 2170 this_device->devtype = (inq_buff[0] & 0x1f);
2171 memcpy(this_device->scsi3addr, scsi3addr, 8);
2172 memcpy(this_device->vendor, &inq_buff[8],
2173 sizeof(this_device->vendor));
2174 memcpy(this_device->model, &inq_buff[16],
2175 sizeof(this_device->model));
edd16368
SC		 2176 memset(this_device->device_id, 0,
2177 sizeof(this_device->device_id));
2178 hpsa_get_device_id(h, scsi3addr, this_device->device_id,
2179 sizeof(this_device->device_id));
2180
2181 if (this_device->devtype == TYPE_DISK &&
283b4a9b 2182 is_logical_dev_addr_mode(scsi3addr)) {
edd16368 2183 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 2184 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
2185 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
2186 } else {
edd16368 2187 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 2188 this_device->offload_config = 0;
2189 this_device->offload_enabled = 0;
2190 }
edd16368 2191
0b0e1d6c
SC		 2192 if (is_OBDR_device) {
2193 /* See if this is a One-Button-Disaster-Recovery device
2194 * by looking for "$DR-10" at offset 43 in inquiry data.
2195 */
2196 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
2197 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
2198 strncmp(obdr_sig, OBDR_TAPE_SIG,
2199 OBDR_SIG_LEN) == 0);
2200 }
2201
edd16368
SC		 2202 kfree(inq_buff);
2203 return 0;
2204
2205bail_out:
2206 kfree(inq_buff);
2207 return 1;
2208}
2209
4f4eb9f1 2210static unsigned char *ext_target_model[] = {
edd16368
SC		 2211 "MSA2012",
2212 "MSA2024",
2213 "MSA2312",
2214 "MSA2324",
fda38518 2215 "P2000 G3 SAS",
e06c8e5c 2216 "MSA 2040 SAS",
edd16368
SC		 2217 NULL,
2218};
2219
4f4eb9f1 2220static int is_ext_target(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
edd16368
SC		 2221{
2222 int i;
2223
4f4eb9f1
ST		 2224 for (i = 0; ext_target_model[i]; i++)
2225 if (strncmp(device->model, ext_target_model[i],
2226 strlen(ext_target_model[i])) == 0)
edd16368
SC		 2227 return 1;
2228 return 0;
2229}
2230
2231/* Helper function to assign bus, target, lun mapping of devices.
4f4eb9f1 2232 * Puts non-external target logical volumes on bus 0, external target logical
edd16368
SC		 2233 * volumes on bus 1, physical devices on bus 2. and the hba on bus 3.
2234 * Logical drive target and lun are assigned at this time, but
2235 * physical device lun and target assignment are deferred (assigned
2236 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
2237 */
2238static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 2239 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 2240{
1f310bde
SC		 2241 u32 lunid = le32_to_cpu(*((__le32 *) lunaddrbytes));
2242
2243 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
2244 /* physical device, target and lun filled in later */
edd16368 2245 if (is_hba_lunid(lunaddrbytes))
1f310bde 2246 hpsa_set_bus_target_lun(device, 3, 0, lunid & 0x3fff);
edd16368 2247 else
1f310bde
SC		 2248 /* defer target, lun assignment for physical devices */
2249 hpsa_set_bus_target_lun(device, 2, -1, -1);
2250 return;
2251 }
2252 /* It's a logical device */
4f4eb9f1
ST		 2253 if (is_ext_target(h, device)) {
2254 /* external target way, put logicals on bus 1
1f310bde
SC		 2255 * and match target/lun numbers box
2256 * reports, other smart array, bus 0, target 0, match lunid
2257 */
2258 hpsa_set_bus_target_lun(device,
2259 1, (lunid >> 16) & 0x3fff, lunid & 0x00ff);
2260 return;
edd16368 2261 }
1f310bde 2262 hpsa_set_bus_target_lun(device, 0, 0, lunid & 0x3fff);
edd16368
SC		 2263}
2264
2265/*
2266 * If there is no lun 0 on a target, linux won't find any devices.
4f4eb9f1 2267 * For the external targets (arrays), we have to manually detect the enclosure
edd16368
SC		 2268 * which is at lun zero, as CCISS_REPORT_PHYSICAL_LUNS doesn't report
2269 * it for some reason. *tmpdevice is the target we're adding,
2270 * this_device is a pointer into the current element of currentsd[]
2271 * that we're building up in update_scsi_devices(), below.
2272 * lunzerobits is a bitmap that tracks which targets already have a
2273 * lun 0 assigned.
2274 * Returns 1 if an enclosure was added, 0 if not.
2275 */
4f4eb9f1 2276static int add_ext_target_dev(struct ctlr_info *h,
edd16368 2277 struct hpsa_scsi_dev_t *tmpdevice,
01a02ffc 2278 struct hpsa_scsi_dev_t *this_device, u8 *lunaddrbytes,
4f4eb9f1 2279 unsigned long lunzerobits[], int *n_ext_target_devs)
edd16368
SC		 2280{
2281 unsigned char scsi3addr[8];
2282
1f310bde 2283 if (test_bit(tmpdevice->target, lunzerobits))
edd16368
SC		 2284 return 0; /* There is already a lun 0 on this target. */
2285
2286 if (!is_logical_dev_addr_mode(lunaddrbytes))
2287 return 0; /* It's the logical targets that may lack lun 0. */
2288
4f4eb9f1
ST		 2289 if (!is_ext_target(h, tmpdevice))
2290 return 0; /* Only external target devices have this problem. */
edd16368 2291
1f310bde 2292 if (tmpdevice->lun == 0) /* if lun is 0, then we have a lun 0. */
edd16368
SC		 2293 return 0;
2294
c4f8a299 2295 memset(scsi3addr, 0, 8);
1f310bde 2296 scsi3addr[3] = tmpdevice->target;
edd16368
SC		 2297 if (is_hba_lunid(scsi3addr))
2298 return 0; /* Don't add the RAID controller here. */
2299
339b2b14
SC		 2300 if (is_scsi_rev_5(h))
2301 return 0; /* p1210m doesn't need to do this. */
2302
4f4eb9f1 2303 if (*n_ext_target_devs >= MAX_EXT_TARGETS) {
aca4a520
ST		 2304 dev_warn(&h->pdev->dev, "Maximum number of external "
2305 "target devices exceeded. Check your hardware "
edd16368
SC		 2306 "configuration.");
2307 return 0;
2308 }
2309
0b0e1d6c 2310 if (hpsa_update_device_info(h, scsi3addr, this_device, NULL))
edd16368 2311 return 0;
4f4eb9f1 2312 (*n_ext_target_devs)++;
1f310bde
SC		 2313 hpsa_set_bus_target_lun(this_device,
2314 tmpdevice->bus, tmpdevice->target, 0);
2315 set_bit(tmpdevice->target, lunzerobits);
edd16368
SC		 2316 return 1;
2317}
2318
54b6e9e9
ST		 2319/*
2320 * Get address of physical disk used for an ioaccel2 mode command:
2321 * 1. Extract ioaccel2 handle from the command.
2322 * 2. Find a matching ioaccel2 handle from list of physical disks.
2323 * 3. Return:
2324 * 1 and set scsi3addr to address of matching physical
2325 * 0 if no matching physical disk was found.
2326 */
2327static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
2328 struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
2329{
2330 struct ReportExtendedLUNdata *physicals = NULL;
2331 int responsesize = 24; /* size of physical extended response */
2332 int extended = 2; /* flag forces reporting 'other dev info'. */
2333 int reportsize = sizeof(*physicals) + HPSA_MAX_PHYS_LUN * responsesize;
2334 u32 nphysicals = 0; /* number of reported physical devs */
2335 int found = 0; /* found match (1) or not (0) */
2336 u32 find; /* handle we need to match */
2337 int i;
2338 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
2339 struct hpsa_scsi_dev_t *d; /* device of request being aborted */
2340 struct io_accel2_cmd *c2a; /* ioaccel2 command to abort */
2341 u32 it_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2342 u32 scsi_nexus; /* 4 byte device handle for the ioaccel2 cmd */
2343
2344 if (ioaccel2_cmd_to_abort->cmd_type != CMD_IOACCEL2)
2345 return 0; /* no match */
2346
2347 /* point to the ioaccel2 device handle */
2348 c2a = &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
2349 if (c2a == NULL)
2350 return 0; /* no match */
2351
2352 scmd = (struct scsi_cmnd *) ioaccel2_cmd_to_abort->scsi_cmd;
2353 if (scmd == NULL)
2354 return 0; /* no match */
2355
2356 d = scmd->device->hostdata;
2357 if (d == NULL)
2358 return 0; /* no match */
2359
2360 it_nexus = cpu_to_le32((u32) d->ioaccel_handle);
2361 scsi_nexus = cpu_to_le32((u32) c2a->scsi_nexus);
2362 find = c2a->scsi_nexus;
2363
2364 /* Get the list of physical devices */
2365 physicals = kzalloc(reportsize, GFP_KERNEL);
2366 if (hpsa_scsi_do_report_phys_luns(h, (struct ReportLUNdata *) physicals,
2367 reportsize, extended)) {
2368 dev_err(&h->pdev->dev,
2369 "Can't lookup %s device handle: report physical LUNs failed.\n",
2370 "HP SSD Smart Path");
2371 kfree(physicals);
2372 return 0;
2373 }
2374 nphysicals = be32_to_cpu(*((__be32 *)physicals->LUNListLength)) /
2375 responsesize;
2376
2377
2378 /* find ioaccel2 handle in list of physicals: */
2379 for (i = 0; i < nphysicals; i++) {
2380 /* handle is in bytes 28-31 of each lun */
2381 if (memcmp(&((struct ReportExtendedLUNdata *)
2382 physicals)->LUN[i][20], &find, 4) != 0) {
2383 continue; /* didn't match */
2384 }
2385 found = 1;
2386 memcpy(scsi3addr, &((struct ReportExtendedLUNdata *)
2387 physicals)->LUN[i][0], 8);
2388 break; /* found it */
2389 }
2390
2391 kfree(physicals);
2392 if (found)
2393 return 1;
2394 else
2395 return 0;
2396
2397}
edd16368
SC		 2398/*
2399 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
2400 * logdev. The number of luns in physdev and logdev are returned in
2401 * *nphysicals and *nlogicals, respectively.
2402 * Returns 0 on success, -1 otherwise.
2403 */
2404static int hpsa_gather_lun_info(struct ctlr_info *h,
2405 int reportlunsize,
283b4a9b 2406 struct ReportLUNdata *physdev, u32 *nphysicals, int *physical_mode,
01a02ffc 2407 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 2408{
283b4a9b
SC		 2409 int physical_entry_size = 8;
2410
2411 *physical_mode = 0;
2412
2413 /* For I/O accelerator mode we need to read physical device handles */
317d4adf
MM		 2414 if (h->transMethod & CFGTBL_Trans_io_accel1 ||
2415 h->transMethod & CFGTBL_Trans_io_accel2) {
283b4a9b
SC		 2416 *physical_mode = HPSA_REPORT_PHYS_EXTENDED;
2417 physical_entry_size = 24;
2418 }
a93aa1fe 2419 if (hpsa_scsi_do_report_phys_luns(h, physdev, reportlunsize,
283b4a9b 2420 *physical_mode)) {
edd16368
SC		 2421 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
2422 return -1;
2423 }
283b4a9b
SC		 2424 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) /
2425 physical_entry_size;
edd16368
SC		 2426 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
2427 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded."
2428 " %d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2429 *nphysicals - HPSA_MAX_PHYS_LUN);
2430 *nphysicals = HPSA_MAX_PHYS_LUN;
2431 }
2432 if (hpsa_scsi_do_report_log_luns(h, logdev, reportlunsize)) {
2433 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
2434 return -1;
2435 }
6df1e954 2436 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 2437 /* Reject Logicals in excess of our max capability. */
2438 if (*nlogicals > HPSA_MAX_LUN) {
2439 dev_warn(&h->pdev->dev,
2440 "maximum logical LUNs (%d) exceeded. "
2441 "%d LUNs ignored.\n", HPSA_MAX_LUN,
2442 *nlogicals - HPSA_MAX_LUN);
2443 *nlogicals = HPSA_MAX_LUN;
2444 }
2445 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
2446 dev_warn(&h->pdev->dev,
2447 "maximum logical + physical LUNs (%d) exceeded. "
2448 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
2449 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
2450 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
2451 }
2452 return 0;
2453}
2454
339b2b14 2455u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position, int i,
a93aa1fe
MG		 2456 int nphysicals, int nlogicals,
2457 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 2458 struct ReportLUNdata *logdev_list)
2459{
2460 /* Helper function, figure out where the LUN ID info is coming from
2461 * given index i, lists of physical and logical devices, where in
2462 * the list the raid controller is supposed to appear (first or last)
2463 */
2464
2465 int logicals_start = nphysicals + (raid_ctlr_position == 0);
2466 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
2467
2468 if (i == raid_ctlr_position)
2469 return RAID_CTLR_LUNID;
2470
2471 if (i < logicals_start)
2472 return &physdev_list->LUN[i - (raid_ctlr_position == 0)][0];
2473
2474 if (i < last_device)
2475 return &logdev_list->LUN[i - nphysicals -
2476 (raid_ctlr_position == 0)][0];
2477 BUG();
2478 return NULL;
2479}
2480
edd16368
SC		 2481static void hpsa_update_scsi_devices(struct ctlr_info *h, int hostno)
2482{
2483 /* the idea here is we could get notified
2484 * that some devices have changed, so we do a report
2485 * physical luns and report logical luns cmd, and adjust
2486 * our list of devices accordingly.
2487 *
2488 * The scsi3addr's of devices won't change so long as the
2489 * adapter is not reset. That means we can rescan and
2490 * tell which devices we already know about, vs. new
2491 * devices, vs. disappearing devices.
2492 */
a93aa1fe 2493 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 2494 struct ReportLUNdata *logdev_list = NULL;
01a02ffc
SC		 2495 u32 nphysicals = 0;
2496 u32 nlogicals = 0;
283b4a9b 2497 int physical_mode = 0;
01a02ffc 2498 u32 ndev_allocated = 0;
edd16368
SC		 2499 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
2500 int ncurrent = 0;
283b4a9b 2501 int reportlunsize = sizeof(*physdev_list) + HPSA_MAX_PHYS_LUN * 24;
4f4eb9f1 2502 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 2503 int raid_ctlr_position;
aca4a520 2504 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 2505
cfe5badc 2506 currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
edd16368
SC		 2507 physdev_list = kzalloc(reportlunsize, GFP_KERNEL);
2508 logdev_list = kzalloc(reportlunsize, GFP_KERNEL);
edd16368
SC		 2509 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
2510
0b0e1d6c 2511 if (!currentsd || !physdev_list || !logdev_list || !tmpdevice) {
edd16368
SC		 2512 dev_err(&h->pdev->dev, "out of memory\n");
2513 goto out;
2514 }
2515 memset(lunzerobits, 0, sizeof(lunzerobits));
2516
a93aa1fe
MG		 2517 if (hpsa_gather_lun_info(h, reportlunsize,
2518 (struct ReportLUNdata *) physdev_list, &nphysicals,
283b4a9b 2519 &physical_mode, logdev_list, &nlogicals))
edd16368
SC		 2520 goto out;
2521
aca4a520
ST		 2522 /* We might see up to the maximum number of logical and physical disks
2523 * plus external target devices, and a device for the local RAID
2524 * controller.
edd16368 2525 */
aca4a520 2526 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368
SC		 2527
2528 /* Allocate the per device structures */
2529 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 2530 if (i >= HPSA_MAX_DEVICES) {
2531 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
2532 " %d devices ignored.\n", HPSA_MAX_DEVICES,
2533 ndevs_to_allocate - HPSA_MAX_DEVICES);
2534 break;
2535 }
2536
edd16368
SC		 2537 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
2538 if (!currentsd[i]) {
2539 dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
2540 __FILE__, __LINE__);
2541 goto out;
2542 }
2543 ndev_allocated++;
2544 }
2545
339b2b14
SC		 2546 if (unlikely(is_scsi_rev_5(h)))
2547 raid_ctlr_position = 0;
2548 else
2549 raid_ctlr_position = nphysicals + nlogicals;
2550
edd16368 2551 /* adjust our table of devices */
4f4eb9f1 2552 n_ext_target_devs = 0;
edd16368 2553 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 2554 u8 *lunaddrbytes, is_OBDR = 0;
edd16368
SC		 2555
2556 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 2557 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
2558 i, nphysicals, nlogicals, physdev_list, logdev_list);
edd16368 2559 /* skip masked physical devices. */
339b2b14
SC		 2560 if (lunaddrbytes[3] & 0xC0 &&
2561 i < nphysicals + (raid_ctlr_position == 0))
edd16368
SC		 2562 continue;
2563
2564 /* Get device type, vendor, model, device id */
0b0e1d6c
SC		 2565 if (hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
2566 &is_OBDR))
edd16368 2567 continue; /* skip it if we can't talk to it. */
1f310bde 2568 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 2569 this_device = currentsd[ncurrent];
2570
2571 /*
4f4eb9f1 2572 * For external target devices, we have to insert a LUN 0 which
edd16368
SC		 2573 * doesn't show up in CCISS_REPORT_PHYSICAL data, but there
2574 * is nonetheless an enclosure device there. We have to
2575 * present that otherwise linux won't find anything if
2576 * there is no lun 0.
2577 */
4f4eb9f1 2578 if (add_ext_target_dev(h, tmpdevice, this_device,
1f310bde 2579 lunaddrbytes, lunzerobits,
4f4eb9f1 2580 &n_ext_target_devs)) {
edd16368
SC		 2581 ncurrent++;
2582 this_device = currentsd[ncurrent];
2583 }
2584
2585 *this_device = *tmpdevice;
edd16368
SC		 2586
2587 switch (this_device->devtype) {
0b0e1d6c 2588 case TYPE_ROM:
edd16368
SC		 2589 /* We don't *really* support actual CD-ROM devices,
2590 * just "One Button Disaster Recovery" tape drive
2591 * which temporarily pretends to be a CD-ROM drive.
2592 * So we check that the device is really an OBDR tape
2593 * device by checking for "$DR-10" in bytes 43-48 of
2594 * the inquiry data.
2595 */
0b0e1d6c
SC		 2596 if (is_OBDR)
2597 ncurrent++;
edd16368
SC		 2598 break;
2599 case TYPE_DISK:
283b4a9b
SC		 2600 if (i >= nphysicals) {
2601 ncurrent++;
edd16368 2602 break;
283b4a9b
SC		 2603 }
2604 if (physical_mode == HPSA_REPORT_PHYS_EXTENDED) {
2605 memcpy(&this_device->ioaccel_handle,
2606 &lunaddrbytes[20],
2607 sizeof(this_device->ioaccel_handle));
2608 ncurrent++;
2609 }
edd16368
SC		 2610 break;
2611 case TYPE_TAPE:
2612 case TYPE_MEDIUM_CHANGER:
2613 ncurrent++;
2614 break;
2615 case TYPE_RAID:
2616 /* Only present the Smartarray HBA as a RAID controller.
2617 * If it's a RAID controller other than the HBA itself
2618 * (an external RAID controller, MSA500 or similar)
2619 * don't present it.
2620 */
2621 if (!is_hba_lunid(lunaddrbytes))
2622 break;
2623 ncurrent++;
2624 break;
2625 default:
2626 break;
2627 }
cfe5badc 2628 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 2629 break;
2630 }
2631 adjust_hpsa_scsi_table(h, hostno, currentsd, ncurrent);
2632out:
2633 kfree(tmpdevice);
2634 for (i = 0; i < ndev_allocated; i++)
2635 kfree(currentsd[i]);
2636 kfree(currentsd);
edd16368
SC		 2637 kfree(physdev_list);
2638 kfree(logdev_list);
edd16368
SC		 2639}
2640
2641/* hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
2642 * dma mapping and fills in the scatter gather entries of the
2643 * hpsa command, cp.
2644 */
33a2ffce 2645static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 2646 struct CommandList *cp,
2647 struct scsi_cmnd *cmd)
2648{
2649 unsigned int len;
2650 struct scatterlist *sg;
01a02ffc 2651 u64 addr64;
33a2ffce
SC		 2652 int use_sg, i, sg_index, chained;
2653 struct SGDescriptor *curr_sg;
edd16368 2654
33a2ffce 2655 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 2656
2657 use_sg = scsi_dma_map(cmd);
2658 if (use_sg < 0)
2659 return use_sg;
2660
2661 if (!use_sg)
2662 goto sglist_finished;
2663
33a2ffce
SC		 2664 curr_sg = cp->SG;
2665 chained = 0;
2666 sg_index = 0;
edd16368 2667 scsi_for_each_sg(cmd, sg, use_sg, i) {
33a2ffce
SC		 2668 if (i == h->max_cmd_sg_entries - 1 &&
2669 use_sg > h->max_cmd_sg_entries) {
2670 chained = 1;
2671 curr_sg = h->cmd_sg_list[cp->cmdindex];
2672 sg_index = 0;
2673 }
01a02ffc 2674 addr64 = (u64) sg_dma_address(sg);
edd16368 2675 len = sg_dma_len(sg);
33a2ffce
SC		 2676 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2677 curr_sg->Addr.upper = (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2678 curr_sg->Len = len;
e1d9cbfa 2679 curr_sg->Ext = (i < scsi_sg_count(cmd) - 1) ? 0 : HPSA_SG_LAST;
33a2ffce
SC		 2680 curr_sg++;
2681 }
2682
2683 if (use_sg + chained > h->maxSG)
2684 h->maxSG = use_sg + chained;
2685
2686 if (chained) {
2687 cp->Header.SGList = h->max_cmd_sg_entries;
2688 cp->Header.SGTotal = (u16) (use_sg + 1);
e2bea6df
SC		 2689 if (hpsa_map_sg_chain_block(h, cp)) {
2690 scsi_dma_unmap(cmd);
2691 return -1;
2692 }
33a2ffce 2693 return 0;
edd16368
SC		 2694 }
2695
2696sglist_finished:
2697
01a02ffc
SC		 2698 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
2699 cp->Header.SGTotal = (u16) use_sg; /* total sgs in this cmd list */
edd16368
SC		 2700 return 0;
2701}
2702
283b4a9b
SC		 2703#define IO_ACCEL_INELIGIBLE (1)
2704static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
2705{
2706 int is_write = 0;
2707 u32 block;
2708 u32 block_cnt;
2709
2710 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
2711 switch (cdb[0]) {
2712 case WRITE_6:
2713 case WRITE_12:
2714 is_write = 1;
2715 case READ_6:
2716 case READ_12:
2717 if (*cdb_len == 6) {
2718 block = (((u32) cdb[2]) << 8) | cdb[3];
2719 block_cnt = cdb[4];
2720 } else {
2721 BUG_ON(*cdb_len != 12);
2722 block = (((u32) cdb[2]) << 24) |
2723 (((u32) cdb[3]) << 16) |
2724 (((u32) cdb[4]) << 8) |
2725 cdb[5];
2726 block_cnt =
2727 (((u32) cdb[6]) << 24) |
2728 (((u32) cdb[7]) << 16) |
2729 (((u32) cdb[8]) << 8) |
2730 cdb[9];
2731 }
2732 if (block_cnt > 0xffff)
2733 return IO_ACCEL_INELIGIBLE;
2734
2735 cdb[0] = is_write ? WRITE_10 : READ_10;
2736 cdb[1] = 0;
2737 cdb[2] = (u8) (block >> 24);
2738 cdb[3] = (u8) (block >> 16);
2739 cdb[4] = (u8) (block >> 8);
2740 cdb[5] = (u8) (block);
2741 cdb[6] = 0;
2742 cdb[7] = (u8) (block_cnt >> 8);
2743 cdb[8] = (u8) (block_cnt);
2744 cdb[9] = 0;
2745 *cdb_len = 10;
2746 break;
2747 }
2748 return 0;
2749}
2750
c349775e 2751static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b
SC		 2752 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2753 u8 *scsi3addr)
e1f7de0c
MG		 2754{
2755 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 2756 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
2757 unsigned int len;
2758 unsigned int total_len = 0;
2759 struct scatterlist *sg;
2760 u64 addr64;
2761 int use_sg, i;
2762 struct SGDescriptor *curr_sg;
2763 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
2764
283b4a9b
SC		 2765 /* TODO: implement chaining support */
2766 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
2767 return IO_ACCEL_INELIGIBLE;
2768
e1f7de0c
MG		 2769 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
2770
283b4a9b
SC		 2771 if (fixup_ioaccel_cdb(cdb, &cdb_len))
2772 return IO_ACCEL_INELIGIBLE;
2773
e1f7de0c
MG		 2774 c->cmd_type = CMD_IOACCEL1;
2775
2776 /* Adjust the DMA address to point to the accelerated command buffer */
2777 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
2778 (c->cmdindex * sizeof(*cp));
2779 BUG_ON(c->busaddr & 0x0000007F);
2780
2781 use_sg = scsi_dma_map(cmd);
2782 if (use_sg < 0)
2783 return use_sg;
2784
2785 if (use_sg) {
2786 curr_sg = cp->SG;
2787 scsi_for_each_sg(cmd, sg, use_sg, i) {
2788 addr64 = (u64) sg_dma_address(sg);
2789 len = sg_dma_len(sg);
2790 total_len += len;
2791 curr_sg->Addr.lower = (u32) (addr64 & 0x0FFFFFFFFULL);
2792 curr_sg->Addr.upper =
2793 (u32) ((addr64 >> 32) & 0x0FFFFFFFFULL);
2794 curr_sg->Len = len;
2795
2796 if (i == (scsi_sg_count(cmd) - 1))
2797 curr_sg->Ext = HPSA_SG_LAST;
2798 else
2799 curr_sg->Ext = 0; /* we are not chaining */
2800 curr_sg++;
2801 }
2802
2803 switch (cmd->sc_data_direction) {
2804 case DMA_TO_DEVICE:
2805 control |= IOACCEL1_CONTROL_DATA_OUT;
2806 break;
2807 case DMA_FROM_DEVICE:
2808 control |= IOACCEL1_CONTROL_DATA_IN;
2809 break;
2810 case DMA_NONE:
2811 control |= IOACCEL1_CONTROL_NODATAXFER;
2812 break;
2813 default:
2814 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2815 cmd->sc_data_direction);
2816 BUG();
2817 break;
2818 }
2819 } else {
2820 control |= IOACCEL1_CONTROL_NODATAXFER;
2821 }
2822
c349775e 2823 c->Header.SGList = use_sg;
e1f7de0c 2824 /* Fill out the command structure to submit */
283b4a9b 2825 cp->dev_handle = ioaccel_handle & 0xFFFF;
e1f7de0c
MG		 2826 cp->transfer_len = total_len;
2827 cp->io_flags = IOACCEL1_IOFLAGS_IO_REQ |
283b4a9b 2828 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK);
e1f7de0c 2829 cp->control = control;
283b4a9b
SC		 2830 memcpy(cp->CDB, cdb, cdb_len);
2831 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 2832 /* Tag was already set at init time. */
283b4a9b 2833 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 2834 return 0;
2835}
edd16368 2836
283b4a9b
SC		 2837/*
2838 * Queue a command directly to a device behind the controller using the
2839 * I/O accelerator path.
2840 */
2841static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
2842 struct CommandList *c)
2843{
2844 struct scsi_cmnd *cmd = c->scsi_cmd;
2845 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
2846
2847 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
2848 cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
2849}
2850
c349775e
ST		 2851static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
2852 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2853 u8 *scsi3addr)
2854{
2855 struct scsi_cmnd *cmd = c->scsi_cmd;
2856 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
2857 struct ioaccel2_sg_element *curr_sg;
2858 int use_sg, i;
2859 struct scatterlist *sg;
2860 u64 addr64;
2861 u32 len;
2862 u32 total_len = 0;
2863
2864 if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
2865 return IO_ACCEL_INELIGIBLE;
2866
2867 if (fixup_ioaccel_cdb(cdb, &cdb_len))
2868 return IO_ACCEL_INELIGIBLE;
2869 c->cmd_type = CMD_IOACCEL2;
2870 /* Adjust the DMA address to point to the accelerated command buffer */
2871 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
2872 (c->cmdindex * sizeof(*cp));
2873 BUG_ON(c->busaddr & 0x0000007F);
2874
2875 memset(cp, 0, sizeof(*cp));
2876 cp->IU_type = IOACCEL2_IU_TYPE;
2877
2878 use_sg = scsi_dma_map(cmd);
2879 if (use_sg < 0)
2880 return use_sg;
2881
2882 if (use_sg) {
2883 BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
2884 curr_sg = cp->sg;
2885 scsi_for_each_sg(cmd, sg, use_sg, i) {
2886 addr64 = (u64) sg_dma_address(sg);
2887 len = sg_dma_len(sg);
2888 total_len += len;
2889 curr_sg->address = cpu_to_le64(addr64);
2890 curr_sg->length = cpu_to_le32(len);
2891 curr_sg->reserved[0] = 0;
2892 curr_sg->reserved[1] = 0;
2893 curr_sg->reserved[2] = 0;
2894 curr_sg->chain_indicator = 0;
2895 curr_sg++;
2896 }
2897
2898 switch (cmd->sc_data_direction) {
2899 case DMA_TO_DEVICE:
2900 cp->direction = IOACCEL2_DIR_DATA_OUT;
2901 break;
2902 case DMA_FROM_DEVICE:
2903 cp->direction = IOACCEL2_DIR_DATA_IN;
2904 break;
2905 case DMA_NONE:
2906 cp->direction = IOACCEL2_DIR_NO_DATA;
2907 break;
2908 default:
2909 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
2910 cmd->sc_data_direction);
2911 BUG();
2912 break;
2913 }
2914 } else {
2915 cp->direction = IOACCEL2_DIR_NO_DATA;
2916 }
2917 cp->scsi_nexus = ioaccel_handle;
2918 cp->Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT) |
2919 DIRECT_LOOKUP_BIT;
2920 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
2921 memset(cp->cciss_lun, 0, sizeof(cp->cciss_lun));
2922 cp->cmd_priority_task_attr = 0;
2923
2924 /* fill in sg elements */
2925 cp->sg_count = (u8) use_sg;
2926
2927 cp->data_len = cpu_to_le32(total_len);
2928 cp->err_ptr = cpu_to_le64(c->busaddr +
2929 offsetof(struct io_accel2_cmd, error_data));
2930 cp->err_len = cpu_to_le32((u32) sizeof(cp->error_data));
2931
2932 enqueue_cmd_and_start_io(h, c);
2933 return 0;
2934}
2935
2936/*
2937 * Queue a command to the correct I/O accelerator path.
2938 */
2939static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
2940 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
2941 u8 *scsi3addr)
2942{
2943 if (h->transMethod & CFGTBL_Trans_io_accel1)
2944 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
2945 cdb, cdb_len, scsi3addr);
2946 else
2947 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
2948 cdb, cdb_len, scsi3addr);
2949}
2950
6b80b18f
ST		 2951static void raid_map_helper(struct raid_map_data *map,
2952 int offload_to_mirror, u32 *map_index, u32 *current_group)
2953{
2954 if (offload_to_mirror == 0) {
2955 /* use physical disk in the first mirrored group. */
2956 *map_index %= map->data_disks_per_row;
2957 return;
2958 }
2959 do {
2960 /* determine mirror group that *map_index indicates */
2961 *current_group = *map_index / map->data_disks_per_row;
2962 if (offload_to_mirror == *current_group)
2963 continue;
2964 if (*current_group < (map->layout_map_count - 1)) {
2965 /* select map index from next group */
2966 *map_index += map->data_disks_per_row;
2967 (*current_group)++;
2968 } else {
2969 /* select map index from first group */
2970 *map_index %= map->data_disks_per_row;
2971 *current_group = 0;
2972 }
2973 } while (offload_to_mirror != *current_group);
2974}
2975
283b4a9b
SC		 2976/*
2977 * Attempt to perform offload RAID mapping for a logical volume I/O.
2978 */
2979static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
2980 struct CommandList *c)
2981{
2982 struct scsi_cmnd *cmd = c->scsi_cmd;
2983 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
2984 struct raid_map_data *map = &dev->raid_map;
2985 struct raid_map_disk_data *dd = &map->data[0];
2986 int is_write = 0;
2987 u32 map_index;
2988 u64 first_block, last_block;
2989 u32 block_cnt;
2990 u32 blocks_per_row;
2991 u64 first_row, last_row;
2992 u32 first_row_offset, last_row_offset;
2993 u32 first_column, last_column;
6b80b18f
ST		 2994 u64 r0_first_row, r0_last_row;
2995 u32 r5or6_blocks_per_row;
2996 u64 r5or6_first_row, r5or6_last_row;
2997 u32 r5or6_first_row_offset, r5or6_last_row_offset;
2998 u32 r5or6_first_column, r5or6_last_column;
2999 u32 total_disks_per_row;
3000 u32 stripesize;
3001 u32 first_group, last_group, current_group;
283b4a9b
SC		 3002 u32 map_row;
3003 u32 disk_handle;
3004 u64 disk_block;
3005 u32 disk_block_cnt;
3006 u8 cdb[16];
3007 u8 cdb_len;
3008#if BITS_PER_LONG == 32
3009 u64 tmpdiv;
3010#endif
6b80b18f 3011 int offload_to_mirror;
283b4a9b
SC		 3012
3013 BUG_ON(!(dev->offload_config && dev->offload_enabled));
3014
3015 /* check for valid opcode, get LBA and block count */
3016 switch (cmd->cmnd[0]) {
3017 case WRITE_6:
3018 is_write = 1;
3019 case READ_6:
3020 first_block =
3021 (((u64) cmd->cmnd[2]) << 8) |
3022 cmd->cmnd[3];
3023 block_cnt = cmd->cmnd[4];
3024 break;
3025 case WRITE_10:
3026 is_write = 1;
3027 case READ_10:
3028 first_block =
3029 (((u64) cmd->cmnd[2]) << 24) |
3030 (((u64) cmd->cmnd[3]) << 16) |
3031 (((u64) cmd->cmnd[4]) << 8) |
3032 cmd->cmnd[5];
3033 block_cnt =
3034 (((u32) cmd->cmnd[7]) << 8) |
3035 cmd->cmnd[8];
3036 break;
3037 case WRITE_12:
3038 is_write = 1;
3039 case READ_12:
3040 first_block =
3041 (((u64) cmd->cmnd[2]) << 24) |
3042 (((u64) cmd->cmnd[3]) << 16) |
3043 (((u64) cmd->cmnd[4]) << 8) |
3044 cmd->cmnd[5];
3045 block_cnt =
3046 (((u32) cmd->cmnd[6]) << 24) |
3047 (((u32) cmd->cmnd[7]) << 16) |
3048 (((u32) cmd->cmnd[8]) << 8) |
3049 cmd->cmnd[9];
3050 break;
3051 case WRITE_16:
3052 is_write = 1;
3053 case READ_16:
3054 first_block =
3055 (((u64) cmd->cmnd[2]) << 56) |
3056 (((u64) cmd->cmnd[3]) << 48) |
3057 (((u64) cmd->cmnd[4]) << 40) |
3058 (((u64) cmd->cmnd[5]) << 32) |
3059 (((u64) cmd->cmnd[6]) << 24) |
3060 (((u64) cmd->cmnd[7]) << 16) |
3061 (((u64) cmd->cmnd[8]) << 8) |
3062 cmd->cmnd[9];
3063 block_cnt =
3064 (((u32) cmd->cmnd[10]) << 24) |
3065 (((u32) cmd->cmnd[11]) << 16) |
3066 (((u32) cmd->cmnd[12]) << 8) |
3067 cmd->cmnd[13];
3068 break;
3069 default:
3070 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
3071 }
3072 BUG_ON(block_cnt == 0);
3073 last_block = first_block + block_cnt - 1;
3074
3075 /* check for write to non-RAID-0 */
3076 if (is_write && dev->raid_level != 0)
3077 return IO_ACCEL_INELIGIBLE;
3078
3079 /* check for invalid block or wraparound */
3080 if (last_block >= map->volume_blk_cnt || last_block < first_block)
3081 return IO_ACCEL_INELIGIBLE;
3082
3083 /* calculate stripe information for the request */
3084 blocks_per_row = map->data_disks_per_row * map->strip_size;
3085#if BITS_PER_LONG == 32
3086 tmpdiv = first_block;
3087 (void) do_div(tmpdiv, blocks_per_row);
3088 first_row = tmpdiv;
3089 tmpdiv = last_block;
3090 (void) do_div(tmpdiv, blocks_per_row);
3091 last_row = tmpdiv;
3092 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3093 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3094 tmpdiv = first_row_offset;
3095 (void) do_div(tmpdiv, map->strip_size);
3096 first_column = tmpdiv;
3097 tmpdiv = last_row_offset;
3098 (void) do_div(tmpdiv, map->strip_size);
3099 last_column = tmpdiv;
3100#else
3101 first_row = first_block / blocks_per_row;
3102 last_row = last_block / blocks_per_row;
3103 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
3104 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
3105 first_column = first_row_offset / map->strip_size;
3106 last_column = last_row_offset / map->strip_size;
3107#endif
3108
3109 /* if this isn't a single row/column then give to the controller */
3110 if ((first_row != last_row) || (first_column != last_column))
3111 return IO_ACCEL_INELIGIBLE;
3112
3113 /* proceeding with driver mapping */
6b80b18f
ST		 3114 total_disks_per_row = map->data_disks_per_row +
3115 map->metadata_disks_per_row;
283b4a9b
SC		 3116 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3117 map->row_cnt;
6b80b18f
ST		 3118 map_index = (map_row * total_disks_per_row) + first_column;
3119
3120 switch (dev->raid_level) {
3121 case HPSA_RAID_0:
3122 break; /* nothing special to do */
3123 case HPSA_RAID_1:
3124 /* Handles load balance across RAID 1 members.
3125 * (2-drive R1 and R10 with even # of drives.)
3126 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 3127 */
6b80b18f 3128 BUG_ON(map->layout_map_count != 2);
283b4a9b
SC		 3129 if (dev->offload_to_mirror)
3130 map_index += map->data_disks_per_row;
3131 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 3132 break;
3133 case HPSA_RAID_ADM:
3134 /* Handles N-way mirrors (R1-ADM)
3135 * and R10 with # of drives divisible by 3.)
3136 */
3137 BUG_ON(map->layout_map_count != 3);
3138
3139 offload_to_mirror = dev->offload_to_mirror;
3140 raid_map_helper(map, offload_to_mirror,
3141 &map_index, &current_group);
3142 /* set mirror group to use next time */
3143 offload_to_mirror =
3144 (offload_to_mirror >= map->layout_map_count - 1)
3145 ? 0 : offload_to_mirror + 1;
3146 /* FIXME: remove after debug/dev */
3147 BUG_ON(offload_to_mirror >= map->layout_map_count);
3148 dev_warn(&h->pdev->dev,
3149 "DEBUG: Using physical disk map index %d from mirror group %d\n",
3150 map_index, offload_to_mirror);
3151 dev->offload_to_mirror = offload_to_mirror;
3152 /* Avoid direct use of dev->offload_to_mirror within this
3153 * function since multiple threads might simultaneously
3154 * increment it beyond the range of dev->layout_map_count -1.
3155 */
3156 break;
3157 case HPSA_RAID_5:
3158 case HPSA_RAID_6:
3159 if (map->layout_map_count <= 1)
3160 break;
3161
3162 /* Verify first and last block are in same RAID group */
3163 r5or6_blocks_per_row =
3164 map->strip_size * map->data_disks_per_row;
3165 BUG_ON(r5or6_blocks_per_row == 0);
3166 stripesize = r5or6_blocks_per_row * map->layout_map_count;
3167#if BITS_PER_LONG == 32
3168 tmpdiv = first_block;
3169 first_group = do_div(tmpdiv, stripesize);
3170 tmpdiv = first_group;
3171 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3172 first_group = tmpdiv;
3173 tmpdiv = last_block;
3174 last_group = do_div(tmpdiv, stripesize);
3175 tmpdiv = last_group;
3176 (void) do_div(tmpdiv, r5or6_blocks_per_row);
3177 last_group = tmpdiv;
3178#else
3179 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
3180 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
3181 if (first_group != last_group)
3182#endif
3183 return IO_ACCEL_INELIGIBLE;
3184
3185 /* Verify request is in a single row of RAID 5/6 */
3186#if BITS_PER_LONG == 32
3187 tmpdiv = first_block;
3188 (void) do_div(tmpdiv, stripesize);
3189 first_row = r5or6_first_row = r0_first_row = tmpdiv;
3190 tmpdiv = last_block;
3191 (void) do_div(tmpdiv, stripesize);
3192 r5or6_last_row = r0_last_row = tmpdiv;
3193#else
3194 first_row = r5or6_first_row = r0_first_row =
3195 first_block / stripesize;
3196 r5or6_last_row = r0_last_row = last_block / stripesize;
3197#endif
3198 if (r5or6_first_row != r5or6_last_row)
3199 return IO_ACCEL_INELIGIBLE;
3200
3201
3202 /* Verify request is in a single column */
3203#if BITS_PER_LONG == 32
3204 tmpdiv = first_block;
3205 first_row_offset = do_div(tmpdiv, stripesize);
3206 tmpdiv = first_row_offset;
3207 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
3208 r5or6_first_row_offset = first_row_offset;
3209 tmpdiv = last_block;
3210 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
3211 tmpdiv = r5or6_last_row_offset;
3212 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
3213 tmpdiv = r5or6_first_row_offset;
3214 (void) do_div(tmpdiv, map->strip_size);
3215 first_column = r5or6_first_column = tmpdiv;
3216 tmpdiv = r5or6_last_row_offset;
3217 (void) do_div(tmpdiv, map->strip_size);
3218 r5or6_last_column = tmpdiv;
3219#else
3220 first_row_offset = r5or6_first_row_offset =
3221 (u32)((first_block % stripesize) %
3222 r5or6_blocks_per_row);
3223
3224 r5or6_last_row_offset =
3225 (u32)((last_block % stripesize) %
3226 r5or6_blocks_per_row);
3227
3228 first_column = r5or6_first_column =
3229 r5or6_first_row_offset / map->strip_size;
3230 r5or6_last_column =
3231 r5or6_last_row_offset / map->strip_size;
3232#endif
3233 if (r5or6_first_column != r5or6_last_column)
3234 return IO_ACCEL_INELIGIBLE;
3235
3236 /* Request is eligible */
3237 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
3238 map->row_cnt;
3239
3240 map_index = (first_group *
3241 (map->row_cnt * total_disks_per_row)) +
3242 (map_row * total_disks_per_row) + first_column;
3243 break;
3244 default:
3245 return IO_ACCEL_INELIGIBLE;
283b4a9b 3246 }
6b80b18f 3247
283b4a9b
SC		 3248 disk_handle = dd[map_index].ioaccel_handle;
3249 disk_block = map->disk_starting_blk + (first_row * map->strip_size) +
3250 (first_row_offset - (first_column * map->strip_size));
3251 disk_block_cnt = block_cnt;
3252
3253 /* handle differing logical/physical block sizes */
3254 if (map->phys_blk_shift) {
3255 disk_block <<= map->phys_blk_shift;
3256 disk_block_cnt <<= map->phys_blk_shift;
3257 }
3258 BUG_ON(disk_block_cnt > 0xffff);
3259
3260 /* build the new CDB for the physical disk I/O */
3261 if (disk_block > 0xffffffff) {
3262 cdb[0] = is_write ? WRITE_16 : READ_16;
3263 cdb[1] = 0;
3264 cdb[2] = (u8) (disk_block >> 56);
3265 cdb[3] = (u8) (disk_block >> 48);
3266 cdb[4] = (u8) (disk_block >> 40);
3267 cdb[5] = (u8) (disk_block >> 32);
3268 cdb[6] = (u8) (disk_block >> 24);
3269 cdb[7] = (u8) (disk_block >> 16);
3270 cdb[8] = (u8) (disk_block >> 8);
3271 cdb[9] = (u8) (disk_block);
3272 cdb[10] = (u8) (disk_block_cnt >> 24);
3273 cdb[11] = (u8) (disk_block_cnt >> 16);
3274 cdb[12] = (u8) (disk_block_cnt >> 8);
3275 cdb[13] = (u8) (disk_block_cnt);
3276 cdb[14] = 0;
3277 cdb[15] = 0;
3278 cdb_len = 16;
3279 } else {
3280 cdb[0] = is_write ? WRITE_10 : READ_10;
3281 cdb[1] = 0;
3282 cdb[2] = (u8) (disk_block >> 24);
3283 cdb[3] = (u8) (disk_block >> 16);
3284 cdb[4] = (u8) (disk_block >> 8);
3285 cdb[5] = (u8) (disk_block);
3286 cdb[6] = 0;
3287 cdb[7] = (u8) (disk_block_cnt >> 8);
3288 cdb[8] = (u8) (disk_block_cnt);
3289 cdb[9] = 0;
3290 cdb_len = 10;
3291 }
3292 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
3293 dev->scsi3addr);
3294}
3295
f281233d 3296static int hpsa_scsi_queue_command_lck(struct scsi_cmnd *cmd,
edd16368
SC		 3297 void (*done)(struct scsi_cmnd *))
3298{
3299 struct ctlr_info *h;
3300 struct hpsa_scsi_dev_t *dev;
3301 unsigned char scsi3addr[8];
3302 struct CommandList *c;
3303 unsigned long flags;
283b4a9b 3304 int rc = 0;
edd16368
SC		 3305
3306 /* Get the ptr to our adapter structure out of cmd->host. */
3307 h = sdev_to_hba(cmd->device);
3308 dev = cmd->device->hostdata;
3309 if (!dev) {
3310 cmd->result = DID_NO_CONNECT << 16;
3311 done(cmd);
3312 return 0;
3313 }
3314 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
3315
edd16368 3316 spin_lock_irqsave(&h->lock, flags);
a0c12413
SC		 3317 if (unlikely(h->lockup_detected)) {
3318 spin_unlock_irqrestore(&h->lock, flags);
3319 cmd->result = DID_ERROR << 16;
3320 done(cmd);
3321 return 0;
3322 }
edd16368 3323 spin_unlock_irqrestore(&h->lock, flags);
e16a33ad 3324 c = cmd_alloc(h);
edd16368
SC		 3325 if (c == NULL) { /* trouble... */
3326 dev_err(&h->pdev->dev, "cmd_alloc returned NULL!\n");
3327 return SCSI_MLQUEUE_HOST_BUSY;
3328 }
3329
3330 /* Fill in the command list header */
3331
3332 cmd->scsi_done = done; /* save this for use by completion code */
3333
3334 /* save c in case we have to abort it */
3335 cmd->host_scribble = (unsigned char *) c;
3336
3337 c->cmd_type = CMD_SCSI;
3338 c->scsi_cmd = cmd;
e1f7de0c 3339
283b4a9b
SC		 3340 /* Call alternate submit routine for I/O accelerated commands.
3341 * Retries always go down the normal I/O path.
3342 */
3343 if (likely(cmd->retries == 0 &&
3344 cmd->request->cmd_type == REQ_TYPE_FS)) {
3345 if (dev->offload_enabled) {
3346 rc = hpsa_scsi_ioaccel_raid_map(h, c);
3347 if (rc == 0)
3348 return 0; /* Sent on ioaccel path */
3349 if (rc < 0) { /* scsi_dma_map failed. */
3350 cmd_free(h, c);
3351 return SCSI_MLQUEUE_HOST_BUSY;
3352 }
3353 } else if (dev->ioaccel_handle) {
3354 rc = hpsa_scsi_ioaccel_direct_map(h, c);
3355 if (rc == 0)
3356 return 0; /* Sent on direct map path */
3357 if (rc < 0) { /* scsi_dma_map failed. */
3358 cmd_free(h, c);
3359 return SCSI_MLQUEUE_HOST_BUSY;
3360 }
3361 }
3362 }
e1f7de0c 3363
edd16368
SC		 3364 c->Header.ReplyQueue = 0; /* unused in simple mode */
3365 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
303932fd
DB		 3366 c->Header.Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT);
3367 c->Header.Tag.lower |= DIRECT_LOOKUP_BIT;
edd16368
SC		 3368
3369 /* Fill in the request block... */
3370
3371 c->Request.Timeout = 0;
3372 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
3373 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
3374 c->Request.CDBLen = cmd->cmd_len;
3375 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
3376 c->Request.Type.Type = TYPE_CMD;
3377 c->Request.Type.Attribute = ATTR_SIMPLE;
3378 switch (cmd->sc_data_direction) {
3379 case DMA_TO_DEVICE:
3380 c->Request.Type.Direction = XFER_WRITE;
3381 break;
3382 case DMA_FROM_DEVICE:
3383 c->Request.Type.Direction = XFER_READ;
3384 break;
3385 case DMA_NONE:
3386 c->Request.Type.Direction = XFER_NONE;
3387 break;
3388 case DMA_BIDIRECTIONAL:
3389 /* This can happen if a buggy application does a scsi passthru
3390 * and sets both inlen and outlen to non-zero. ( see
3391 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
3392 */
3393
3394 c->Request.Type.Direction = XFER_RSVD;
3395 /* This is technically wrong, and hpsa controllers should
3396 * reject it with CMD_INVALID, which is the most correct
3397 * response, but non-fibre backends appear to let it
3398 * slide by, and give the same results as if this field
3399 * were set correctly. Either way is acceptable for
3400 * our purposes here.
3401 */
3402
3403 break;
3404
3405 default:
3406 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
3407 cmd->sc_data_direction);
3408 BUG();
3409 break;
3410 }
3411
33a2ffce 3412 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
edd16368
SC		 3413 cmd_free(h, c);
3414 return SCSI_MLQUEUE_HOST_BUSY;
3415 }
3416 enqueue_cmd_and_start_io(h, c);
3417 /* the cmd'll come back via intr handler in complete_scsi_command() */
3418 return 0;
3419}
3420
f281233d
JG		 3421static DEF_SCSI_QCMD(hpsa_scsi_queue_command)
3422
5f389360
SC		 3423static int do_not_scan_if_controller_locked_up(struct ctlr_info *h)
3424{
3425 unsigned long flags;
3426
3427 /*
3428 * Don't let rescans be initiated on a controller known
3429 * to be locked up. If the controller locks up *during*
3430 * a rescan, that thread is probably hosed, but at least
3431 * we can prevent new rescan threads from piling up on a
3432 * locked up controller.
3433 */
3434 spin_lock_irqsave(&h->lock, flags);
3435 if (unlikely(h->lockup_detected)) {
3436 spin_unlock_irqrestore(&h->lock, flags);
3437 spin_lock_irqsave(&h->scan_lock, flags);
3438 h->scan_finished = 1;
3439 wake_up_all(&h->scan_wait_queue);
3440 spin_unlock_irqrestore(&h->scan_lock, flags);
3441 return 1;
3442 }
3443 spin_unlock_irqrestore(&h->lock, flags);
3444 return 0;
3445}
3446
a08a8471
SC		 3447static void hpsa_scan_start(struct Scsi_Host *sh)
3448{
3449 struct ctlr_info *h = shost_to_hba(sh);
3450 unsigned long flags;
3451
5f389360
SC		 3452 if (do_not_scan_if_controller_locked_up(h))
3453 return;
3454
a08a8471
SC		 3455 /* wait until any scan already in progress is finished. */
3456 while (1) {
3457 spin_lock_irqsave(&h->scan_lock, flags);
3458 if (h->scan_finished)
3459 break;
3460 spin_unlock_irqrestore(&h->scan_lock, flags);
3461 wait_event(h->scan_wait_queue, h->scan_finished);
3462 /* Note: We don't need to worry about a race between this
3463 * thread and driver unload because the midlayer will
3464 * have incremented the reference count, so unload won't
3465 * happen if we're in here.
3466 */
3467 }
3468 h->scan_finished = 0; /* mark scan as in progress */
3469 spin_unlock_irqrestore(&h->scan_lock, flags);
3470
5f389360
SC		 3471 if (do_not_scan_if_controller_locked_up(h))
3472 return;
3473
a08a8471
SC		 3474 hpsa_update_scsi_devices(h, h->scsi_host->host_no);
3475
3476 spin_lock_irqsave(&h->scan_lock, flags);
3477 h->scan_finished = 1; /* mark scan as finished. */
3478 wake_up_all(&h->scan_wait_queue);
3479 spin_unlock_irqrestore(&h->scan_lock, flags);
3480}
3481
3482static int hpsa_scan_finished(struct Scsi_Host *sh,
3483 unsigned long elapsed_time)
3484{
3485 struct ctlr_info *h = shost_to_hba(sh);
3486 unsigned long flags;
3487 int finished;
3488
3489 spin_lock_irqsave(&h->scan_lock, flags);
3490 finished = h->scan_finished;
3491 spin_unlock_irqrestore(&h->scan_lock, flags);
3492 return finished;
3493}
3494
667e23d4
SC		 3495static int hpsa_change_queue_depth(struct scsi_device *sdev,
3496 int qdepth, int reason)
3497{
3498 struct ctlr_info *h = sdev_to_hba(sdev);
3499
3500 if (reason != SCSI_QDEPTH_DEFAULT)
3501 return -ENOTSUPP;
3502
3503 if (qdepth < 1)
3504 qdepth = 1;
3505 else
3506 if (qdepth > h->nr_cmds)
3507 qdepth = h->nr_cmds;
3508 scsi_adjust_queue_depth(sdev, scsi_get_tag_type(sdev), qdepth);
3509 return sdev->queue_depth;
3510}
3511
edd16368
SC		 3512static void hpsa_unregister_scsi(struct ctlr_info *h)
3513{
3514 /* we are being forcibly unloaded, and may not refuse. */
3515 scsi_remove_host(h->scsi_host);
3516 scsi_host_put(h->scsi_host);
3517 h->scsi_host = NULL;
3518}
3519
3520static int hpsa_register_scsi(struct ctlr_info *h)
3521{
b705690d
SC		 3522 struct Scsi_Host *sh;
3523 int error;
edd16368 3524
b705690d
SC		 3525 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
3526 if (sh == NULL)
3527 goto fail;
3528
3529 sh->io_port = 0;
3530 sh->n_io_port = 0;
3531 sh->this_id = -1;
3532 sh->max_channel = 3;
3533 sh->max_cmd_len = MAX_COMMAND_SIZE;
3534 sh->max_lun = HPSA_MAX_LUN;
3535 sh->max_id = HPSA_MAX_LUN;
3536 sh->can_queue = h->nr_cmds;
3537 sh->cmd_per_lun = h->nr_cmds;
3538 sh->sg_tablesize = h->maxsgentries;
3539 h->scsi_host = sh;
3540 sh->hostdata[0] = (unsigned long) h;
3541 sh->irq = h->intr[h->intr_mode];
3542 sh->unique_id = sh->irq;
3543 error = scsi_add_host(sh, &h->pdev->dev);
3544 if (error)
3545 goto fail_host_put;
3546 scsi_scan_host(sh);
3547 return 0;
3548
3549 fail_host_put:
3550 dev_err(&h->pdev->dev, "%s: scsi_add_host"
3551 " failed for controller %d\n", __func__, h->ctlr);
3552 scsi_host_put(sh);
3553 return error;
3554 fail:
3555 dev_err(&h->pdev->dev, "%s: scsi_host_alloc"
3556 " failed for controller %d\n", __func__, h->ctlr);
3557 return -ENOMEM;
edd16368
SC		 3558}
3559
3560static int wait_for_device_to_become_ready(struct ctlr_info *h,
3561 unsigned char lunaddr[])
3562{
3563 int rc = 0;
3564 int count = 0;
3565 int waittime = 1; /* seconds */
3566 struct CommandList *c;
3567
3568 c = cmd_special_alloc(h);
3569 if (!c) {
3570 dev_warn(&h->pdev->dev, "out of memory in "
3571 "wait_for_device_to_become_ready.\n");
3572 return IO_ERROR;
3573 }
3574
3575 /* Send test unit ready until device ready, or give up. */
3576 while (count < HPSA_TUR_RETRY_LIMIT) {
3577
3578 /* Wait for a bit. do this first, because if we send
3579 * the TUR right away, the reset will just abort it.
3580 */
3581 msleep(1000 * waittime);
3582 count++;
3583
3584 /* Increase wait time with each try, up to a point. */
3585 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
3586 waittime = waittime * 2;
3587
a2dac136
SC		 3588 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
3589 (void) fill_cmd(c, TEST_UNIT_READY, h,
3590 NULL, 0, 0, lunaddr, TYPE_CMD);
edd16368
SC		 3591 hpsa_scsi_do_simple_cmd_core(h, c);
3592 /* no unmap needed here because no data xfer. */
3593
3594 if (c->err_info->CommandStatus == CMD_SUCCESS)
3595 break;
3596
3597 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
3598 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
3599 (c->err_info->SenseInfo[2] == NO_SENSE ||
3600 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
3601 break;
3602
3603 dev_warn(&h->pdev->dev, "waiting %d secs "
3604 "for device to become ready.\n", waittime);
3605 rc = 1; /* device not ready. */
3606 }
3607
3608 if (rc)
3609 dev_warn(&h->pdev->dev, "giving up on device.\n");
3610 else
3611 dev_warn(&h->pdev->dev, "device is ready.\n");
3612
3613 cmd_special_free(h, c);
3614 return rc;
3615}
3616
3617/* Need at least one of these error handlers to keep ../scsi/hosts.c from
3618 * complaining. Doing a host- or bus-reset can't do anything good here.
3619 */
3620static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
3621{
3622 int rc;
3623 struct ctlr_info *h;
3624 struct hpsa_scsi_dev_t *dev;
3625
3626 /* find the controller to which the command to be aborted was sent */
3627 h = sdev_to_hba(scsicmd->device);
3628 if (h == NULL) /* paranoia */
3629 return FAILED;
edd16368
SC		 3630 dev = scsicmd->device->hostdata;
3631 if (!dev) {
3632 dev_err(&h->pdev->dev, "hpsa_eh_device_reset_handler: "
3633 "device lookup failed.\n");
3634 return FAILED;
3635 }
d416b0c7
SC		 3636 dev_warn(&h->pdev->dev, "resetting device %d:%d:%d:%d\n",
3637 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
edd16368 3638 /* send a reset to the SCSI LUN which the command was sent to */
bf711ac6 3639 rc = hpsa_send_reset(h, dev->scsi3addr, HPSA_RESET_TYPE_LUN);
edd16368
SC		 3640 if (rc == 0 && wait_for_device_to_become_ready(h, dev->scsi3addr) == 0)
3641 return SUCCESS;
3642
3643 dev_warn(&h->pdev->dev, "resetting device failed.\n");
3644 return FAILED;
3645}
3646
6cba3f19
SC		 3647static void swizzle_abort_tag(u8 *tag)
3648{
3649 u8 original_tag[8];
3650
3651 memcpy(original_tag, tag, 8);
3652 tag[0] = original_tag[3];
3653 tag[1] = original_tag[2];
3654 tag[2] = original_tag[1];
3655 tag[3] = original_tag[0];
3656 tag[4] = original_tag[7];
3657 tag[5] = original_tag[6];
3658 tag[6] = original_tag[5];
3659 tag[7] = original_tag[4];
3660}
3661
17eb87d2
ST		 3662static void hpsa_get_tag(struct ctlr_info *h,
3663 struct CommandList *c, u32 *taglower, u32 *tagupper)
3664{
3665 if (c->cmd_type == CMD_IOACCEL1) {
3666 struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
3667 &h->ioaccel_cmd_pool[c->cmdindex];
3668 *tagupper = cm1->Tag.upper;
3669 *taglower = cm1->Tag.lower;
54b6e9e9
ST		 3670 return;
3671 }
3672 if (c->cmd_type == CMD_IOACCEL2) {
3673 struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
3674 &h->ioaccel2_cmd_pool[c->cmdindex];
3675 *tagupper = cm2->Tag.upper;
3676 *taglower = cm2->Tag.lower;
3677 return;
17eb87d2 3678 }
54b6e9e9
ST		 3679 *tagupper = c->Header.Tag.upper;
3680 *taglower = c->Header.Tag.lower;
17eb87d2
ST		 3681}
3682
54b6e9e9 3683
75167d2c 3684static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
6cba3f19 3685 struct CommandList *abort, int swizzle)
75167d2c
SC		 3686{
3687 int rc = IO_OK;
3688 struct CommandList *c;
3689 struct ErrorInfo *ei;
17eb87d2 3690 u32 tagupper, taglower;
75167d2c
SC		 3691
3692 c = cmd_special_alloc(h);
3693 if (c == NULL) { /* trouble... */
3694 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
3695 return -ENOMEM;
3696 }
3697
a2dac136
SC		 3698 /* fill_cmd can't fail here, no buffer to map */
3699 (void) fill_cmd(c, HPSA_ABORT_MSG, h, abort,
3700 0, 0, scsi3addr, TYPE_MSG);
6cba3f19
SC		 3701 if (swizzle)
3702 swizzle_abort_tag(&c->Request.CDB[4]);
75167d2c 3703 hpsa_scsi_do_simple_cmd_core(h, c);
17eb87d2 3704 hpsa_get_tag(h, abort, &taglower, &tagupper);
75167d2c 3705 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd_core completed.\n",
17eb87d2 3706 __func__, tagupper, taglower);
75167d2c
SC		 3707 /* no unmap needed here because no data xfer. */
3708
3709 ei = c->err_info;
3710 switch (ei->CommandStatus) {
3711 case CMD_SUCCESS:
3712 break;
3713 case CMD_UNABORTABLE: /* Very common, don't make noise. */
3714 rc = -1;
3715 break;
3716 default:
3717 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
17eb87d2 3718 __func__, tagupper, taglower);
75167d2c
SC		 3719 hpsa_scsi_interpret_error(c);
3720 rc = -1;
3721 break;
3722 }
3723 cmd_special_free(h, c);
3724 dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
3725 abort->Header.Tag.upper, abort->Header.Tag.lower);
3726 return rc;
3727}
3728
3729/*
3730 * hpsa_find_cmd_in_queue
3731 *
3732 * Used to determine whether a command (find) is still present
3733 * in queue_head. Optionally excludes the last element of queue_head.
3734 *
3735 * This is used to avoid unnecessary aborts. Commands in h->reqQ have
3736 * not yet been submitted, and so can be aborted by the driver without
3737 * sending an abort to the hardware.
3738 *
3739 * Returns pointer to command if found in queue, NULL otherwise.
3740 */
3741static struct CommandList *hpsa_find_cmd_in_queue(struct ctlr_info *h,
3742 struct scsi_cmnd *find, struct list_head *queue_head)
3743{
3744 unsigned long flags;
3745 struct CommandList *c = NULL; /* ptr into cmpQ */
3746
3747 if (!find)
3748 return 0;
3749 spin_lock_irqsave(&h->lock, flags);
3750 list_for_each_entry(c, queue_head, list) {
3751 if (c->scsi_cmd == NULL) /* e.g.: passthru ioctl */
3752 continue;
3753 if (c->scsi_cmd == find) {
3754 spin_unlock_irqrestore(&h->lock, flags);
3755 return c;
3756 }
3757 }
3758 spin_unlock_irqrestore(&h->lock, flags);
3759 return NULL;
3760}
3761
6cba3f19
SC		 3762static struct CommandList *hpsa_find_cmd_in_queue_by_tag(struct ctlr_info *h,
3763 u8 *tag, struct list_head *queue_head)
3764{
3765 unsigned long flags;
3766 struct CommandList *c;
3767
3768 spin_lock_irqsave(&h->lock, flags);
3769 list_for_each_entry(c, queue_head, list) {
3770 if (memcmp(&c->Header.Tag, tag, 8) != 0)
3771 continue;
3772 spin_unlock_irqrestore(&h->lock, flags);
3773 return c;
3774 }
3775 spin_unlock_irqrestore(&h->lock, flags);
3776 return NULL;
3777}
3778
54b6e9e9
ST		 3779/* ioaccel2 path firmware cannot handle abort task requests.
3780 * Change abort requests to physical target reset, and send to the
3781 * address of the physical disk used for the ioaccel 2 command.
3782 * Return 0 on success (IO_OK)
3783 * -1 on failure
3784 */
3785
3786static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
3787 unsigned char *scsi3addr, struct CommandList *abort)
3788{
3789 int rc = IO_OK;
3790 struct scsi_cmnd *scmd; /* scsi command within request being aborted */
3791 struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
3792 unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
3793 unsigned char *psa = &phys_scsi3addr[0];
3794
3795 /* Get a pointer to the hpsa logical device. */
3796 scmd = (struct scsi_cmnd *) abort->scsi_cmd;
3797 dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
3798 if (dev == NULL) {
3799 dev_warn(&h->pdev->dev,
3800 "Cannot abort: no device pointer for command.\n");
3801 return -1; /* not abortable */
3802 }
3803
3804 if (!dev->offload_enabled) {
3805 dev_warn(&h->pdev->dev,
3806 "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
3807 return -1; /* not abortable */
3808 }
3809
3810 /* Incoming scsi3addr is logical addr. We need physical disk addr. */
3811 if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
3812 dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
3813 return -1; /* not abortable */
3814 }
3815
3816 /* send the reset */
3817 rc = hpsa_send_reset(h, psa, HPSA_RESET_TYPE_TARGET);
3818 if (rc != 0) {
3819 dev_warn(&h->pdev->dev,
3820 "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
3821 psa[0], psa[1], psa[2], psa[3],
3822 psa[4], psa[5], psa[6], psa[7]);
3823 return rc; /* failed to reset */
3824 }
3825
3826 /* wait for device to recover */
3827 if (wait_for_device_to_become_ready(h, psa) != 0) {
3828 dev_warn(&h->pdev->dev,
3829 "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
3830 psa[0], psa[1], psa[2], psa[3],
3831 psa[4], psa[5], psa[6], psa[7]);
3832 return -1; /* failed to recover */
3833 }
3834
3835 /* device recovered */
3836 dev_info(&h->pdev->dev,
3837 "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
3838 psa[0], psa[1], psa[2], psa[3],
3839 psa[4], psa[5], psa[6], psa[7]);
3840
3841 return rc; /* success */
3842}
3843
6cba3f19
SC		 3844/* Some Smart Arrays need the abort tag swizzled, and some don't. It's hard to
3845 * tell which kind we're dealing with, so we send the abort both ways. There
3846 * shouldn't be any collisions between swizzled and unswizzled tags due to the
3847 * way we construct our tags but we check anyway in case the assumptions which
3848 * make this true someday become false.
3849 */
3850static int hpsa_send_abort_both_ways(struct ctlr_info *h,
3851 unsigned char *scsi3addr, struct CommandList *abort)
3852{
3853 u8 swizzled_tag[8];
3854 struct CommandList *c;
3855 int rc = 0, rc2 = 0;
3856
54b6e9e9
ST		 3857 /* ioccelerator mode 2 commands should be aborted via the
3858 * accelerated path, since RAID path is unaware of these commands,
3859 * but underlying firmware can't handle abort TMF.
3860 * Change abort to physical device reset.
3861 */
3862 if (abort->cmd_type == CMD_IOACCEL2)
3863 return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr, abort);
3864
6cba3f19
SC		 3865 /* we do not expect to find the swizzled tag in our queue, but
3866 * check anyway just to be sure the assumptions which make this
3867 * the case haven't become wrong.
3868 */
3869 memcpy(swizzled_tag, &abort->Request.CDB[4], 8);
3870 swizzle_abort_tag(swizzled_tag);
3871 c = hpsa_find_cmd_in_queue_by_tag(h, swizzled_tag, &h->cmpQ);
3872 if (c != NULL) {
3873 dev_warn(&h->pdev->dev, "Unexpectedly found byte-swapped tag in completion queue.\n");
3874 return hpsa_send_abort(h, scsi3addr, abort, 0);
3875 }
3876 rc = hpsa_send_abort(h, scsi3addr, abort, 0);
3877
3878 /* if the command is still in our queue, we can't conclude that it was
3879 * aborted (it might have just completed normally) but in any case
3880 * we don't need to try to abort it another way.
3881 */
3882 c = hpsa_find_cmd_in_queue(h, abort->scsi_cmd, &h->cmpQ);
3883 if (c)
3884 rc2 = hpsa_send_abort(h, scsi3addr, abort, 1);
3885 return rc && rc2;
3886}
3887
75167d2c
SC		 3888/* Send an abort for the specified command.
3889 * If the device and controller support it,
3890 * send a task abort request.
3891 */
3892static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
3893{
3894
3895 int i, rc;
3896 struct ctlr_info *h;
3897 struct hpsa_scsi_dev_t *dev;
3898 struct CommandList *abort; /* pointer to command to be aborted */
3899 struct CommandList *found;
3900 struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
3901 char msg[256]; /* For debug messaging. */
3902 int ml = 0;
17eb87d2 3903 u32 tagupper, taglower;
75167d2c
SC		 3904
3905 /* Find the controller of the command to be aborted */
3906 h = sdev_to_hba(sc->device);
3907 if (WARN(h == NULL,
3908 "ABORT REQUEST FAILED, Controller lookup failed.\n"))
3909 return FAILED;
3910
3911 /* Check that controller supports some kind of task abort */
3912 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
3913 !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
3914 return FAILED;
3915
3916 memset(msg, 0, sizeof(msg));
3917 ml += sprintf(msg+ml, "ABORT REQUEST on C%d:B%d:T%d:L%d ",
3918 h->scsi_host->host_no, sc->device->channel,
3919 sc->device->id, sc->device->lun);
3920
3921 /* Find the device of the command to be aborted */
3922 dev = sc->device->hostdata;
3923 if (!dev) {
3924 dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
3925 msg);
3926 return FAILED;
3927 }
3928
3929 /* Get SCSI command to be aborted */
3930 abort = (struct CommandList *) sc->host_scribble;
3931 if (abort == NULL) {
3932 dev_err(&h->pdev->dev, "%s FAILED, Command to abort is NULL.\n",
3933 msg);
3934 return FAILED;
3935 }
17eb87d2
ST		 3936 hpsa_get_tag(h, abort, &taglower, &tagupper);
3937 ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
75167d2c
SC		 3938 as = (struct scsi_cmnd *) abort->scsi_cmd;
3939 if (as != NULL)
3940 ml += sprintf(msg+ml, "Command:0x%x SN:0x%lx ",
3941 as->cmnd[0], as->serial_number);
3942 dev_dbg(&h->pdev->dev, "%s\n", msg);
3943 dev_warn(&h->pdev->dev, "Abort request on C%d:B%d:T%d:L%d\n",
3944 h->scsi_host->host_no, dev->bus, dev->target, dev->lun);
3945
3946 /* Search reqQ to See if command is queued but not submitted,
3947 * if so, complete the command with aborted status and remove
3948 * it from the reqQ.
3949 */
3950 found = hpsa_find_cmd_in_queue(h, sc, &h->reqQ);
3951 if (found) {
3952 found->err_info->CommandStatus = CMD_ABORTED;
3953 finish_cmd(found);
3954 dev_info(&h->pdev->dev, "%s Request SUCCEEDED (driver queue).\n",
3955 msg);
3956 return SUCCESS;
3957 }
3958
3959 /* not in reqQ, if also not in cmpQ, must have already completed */
3960 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
3961 if (!found) {
d6ebd0f7 3962 dev_dbg(&h->pdev->dev, "%s Request SUCCEEDED (not known to driver).\n",
75167d2c
SC		 3963 msg);
3964 return SUCCESS;
3965 }
3966
3967 /*
3968 * Command is in flight, or possibly already completed
3969 * by the firmware (but not to the scsi mid layer) but we can't
3970 * distinguish which. Send the abort down.
3971 */
6cba3f19 3972 rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort);
75167d2c
SC		 3973 if (rc != 0) {
3974 dev_dbg(&h->pdev->dev, "%s Request FAILED.\n", msg);
3975 dev_warn(&h->pdev->dev, "FAILED abort on device C%d:B%d:T%d:L%d\n",
3976 h->scsi_host->host_no,
3977 dev->bus, dev->target, dev->lun);
3978 return FAILED;
3979 }
3980 dev_info(&h->pdev->dev, "%s REQUEST SUCCEEDED.\n", msg);
3981
3982 /* If the abort(s) above completed and actually aborted the
3983 * command, then the command to be aborted should already be
3984 * completed. If not, wait around a bit more to see if they
3985 * manage to complete normally.
3986 */
3987#define ABORT_COMPLETE_WAIT_SECS 30
3988 for (i = 0; i < ABORT_COMPLETE_WAIT_SECS * 10; i++) {
3989 found = hpsa_find_cmd_in_queue(h, sc, &h->cmpQ);
3990 if (!found)
3991 return SUCCESS;
3992 msleep(100);
3993 }
3994 dev_warn(&h->pdev->dev, "%s FAILED. Aborted command has not completed after %d seconds.\n",
3995 msg, ABORT_COMPLETE_WAIT_SECS);
3996 return FAILED;
3997}
3998
3999
edd16368
SC		 4000/*
4001 * For operations that cannot sleep, a command block is allocated at init,
4002 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
4003 * which ones are free or in use. Lock must be held when calling this.
4004 * cmd_free() is the complement.
4005 */
4006static struct CommandList *cmd_alloc(struct ctlr_info *h)
4007{
4008 struct CommandList *c;
4009 int i;
4010 union u64bit temp64;
4011 dma_addr_t cmd_dma_handle, err_dma_handle;
e16a33ad 4012 unsigned long flags;
edd16368 4013
e16a33ad 4014 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4015 do {
4016 i = find_first_zero_bit(h->cmd_pool_bits, h->nr_cmds);
e16a33ad
MG		 4017 if (i == h->nr_cmds) {
4018 spin_unlock_irqrestore(&h->lock, flags);
edd16368 4019 return NULL;
e16a33ad 4020 }
edd16368
SC		 4021 } while (test_and_set_bit
4022 (i & (BITS_PER_LONG - 1),
4023 h->cmd_pool_bits + (i / BITS_PER_LONG)) != 0);
e16a33ad
MG		 4024 spin_unlock_irqrestore(&h->lock, flags);
4025
edd16368
SC		 4026 c = h->cmd_pool + i;
4027 memset(c, 0, sizeof(*c));
4028 cmd_dma_handle = h->cmd_pool_dhandle
4029 + i * sizeof(*c);
4030 c->err_info = h->errinfo_pool + i;
4031 memset(c->err_info, 0, sizeof(*c->err_info));
4032 err_dma_handle = h->errinfo_pool_dhandle
4033 + i * sizeof(*c->err_info);
edd16368
SC		 4034
4035 c->cmdindex = i;
4036
9e0fc764 4037 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4038 c->busaddr = (u32) cmd_dma_handle;
4039 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4040 c->ErrDesc.Addr.lower = temp64.val32.lower;
4041 c->ErrDesc.Addr.upper = temp64.val32.upper;
4042 c->ErrDesc.Len = sizeof(*c->err_info);
4043
4044 c->h = h;
4045 return c;
4046}
4047
4048/* For operations that can wait for kmalloc to possibly sleep,
4049 * this routine can be called. Lock need not be held to call
4050 * cmd_special_alloc. cmd_special_free() is the complement.
4051 */
4052static struct CommandList *cmd_special_alloc(struct ctlr_info *h)
4053{
4054 struct CommandList *c;
4055 union u64bit temp64;
4056 dma_addr_t cmd_dma_handle, err_dma_handle;
4057
4058 c = pci_alloc_consistent(h->pdev, sizeof(*c), &cmd_dma_handle);
4059 if (c == NULL)
4060 return NULL;
4061 memset(c, 0, sizeof(*c));
4062
e1f7de0c 4063 c->cmd_type = CMD_SCSI;
edd16368
SC		 4064 c->cmdindex = -1;
4065
4066 c->err_info = pci_alloc_consistent(h->pdev, sizeof(*c->err_info),
4067 &err_dma_handle);
4068
4069 if (c->err_info == NULL) {
4070 pci_free_consistent(h->pdev,
4071 sizeof(*c), c, cmd_dma_handle);
4072 return NULL;
4073 }
4074 memset(c->err_info, 0, sizeof(*c->err_info));
4075
9e0fc764 4076 INIT_LIST_HEAD(&c->list);
01a02ffc
SC		 4077 c->busaddr = (u32) cmd_dma_handle;
4078 temp64.val = (u64) err_dma_handle;
edd16368
SC		 4079 c->ErrDesc.Addr.lower = temp64.val32.lower;
4080 c->ErrDesc.Addr.upper = temp64.val32.upper;
4081 c->ErrDesc.Len = sizeof(*c->err_info);
4082
4083 c->h = h;
4084 return c;
4085}
4086
4087static void cmd_free(struct ctlr_info *h, struct CommandList *c)
4088{
4089 int i;
e16a33ad 4090 unsigned long flags;
edd16368
SC		 4091
4092 i = c - h->cmd_pool;
e16a33ad 4093 spin_lock_irqsave(&h->lock, flags);
edd16368
SC		 4094 clear_bit(i & (BITS_PER_LONG - 1),
4095 h->cmd_pool_bits + (i / BITS_PER_LONG));
e16a33ad 4096 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4097}
4098
4099static void cmd_special_free(struct ctlr_info *h, struct CommandList *c)
4100{
4101 union u64bit temp64;
4102
4103 temp64.val32.lower = c->ErrDesc.Addr.lower;
4104 temp64.val32.upper = c->ErrDesc.Addr.upper;
4105 pci_free_consistent(h->pdev, sizeof(*c->err_info),
4106 c->err_info, (dma_addr_t) temp64.val);
4107 pci_free_consistent(h->pdev, sizeof(*c),
d896f3f3 4108 c, (dma_addr_t) (c->busaddr & DIRECT_LOOKUP_MASK));
edd16368
SC		 4109}
4110
4111#ifdef CONFIG_COMPAT
4112
edd16368
SC		 4113static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd, void *arg)
4114{
4115 IOCTL32_Command_struct __user *arg32 =
4116 (IOCTL32_Command_struct __user *) arg;
4117 IOCTL_Command_struct arg64;
4118 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
4119 int err;
4120 u32 cp;
4121
938abd84 4122 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4123 err = 0;
4124 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4125 sizeof(arg64.LUN_info));
4126 err |= copy_from_user(&arg64.Request, &arg32->Request,
4127 sizeof(arg64.Request));
4128 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4129 sizeof(arg64.error_info));
4130 err |= get_user(arg64.buf_size, &arg32->buf_size);
4131 err |= get_user(cp, &arg32->buf);
4132 arg64.buf = compat_ptr(cp);
4133 err |= copy_to_user(p, &arg64, sizeof(arg64));
4134
4135 if (err)
4136 return -EFAULT;
4137
e39eeaed 4138 err = hpsa_ioctl(dev, CCISS_PASSTHRU, (void *)p);
edd16368
SC		 4139 if (err)
4140 return err;
4141 err |= copy_in_user(&arg32->error_info, &p->error_info,
4142 sizeof(arg32->error_info));
4143 if (err)
4144 return -EFAULT;
4145 return err;
4146}
4147
4148static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
4149 int cmd, void *arg)
4150{
4151 BIG_IOCTL32_Command_struct __user *arg32 =
4152 (BIG_IOCTL32_Command_struct __user *) arg;
4153 BIG_IOCTL_Command_struct arg64;
4154 BIG_IOCTL_Command_struct __user *p =
4155 compat_alloc_user_space(sizeof(arg64));
4156 int err;
4157 u32 cp;
4158
938abd84 4159 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 4160 err = 0;
4161 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
4162 sizeof(arg64.LUN_info));
4163 err |= copy_from_user(&arg64.Request, &arg32->Request,
4164 sizeof(arg64.Request));
4165 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
4166 sizeof(arg64.error_info));
4167 err |= get_user(arg64.buf_size, &arg32->buf_size);
4168 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
4169 err |= get_user(cp, &arg32->buf);
4170 arg64.buf = compat_ptr(cp);
4171 err |= copy_to_user(p, &arg64, sizeof(arg64));
4172
4173 if (err)
4174 return -EFAULT;
4175
e39eeaed 4176 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, (void *)p);
edd16368
SC		 4177 if (err)
4178 return err;
4179 err |= copy_in_user(&arg32->error_info, &p->error_info,
4180 sizeof(arg32->error_info));
4181 if (err)
4182 return -EFAULT;
4183 return err;
4184}
71fe75a7
SC		 4185
4186static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void *arg)
4187{
4188 switch (cmd) {
4189 case CCISS_GETPCIINFO:
4190 case CCISS_GETINTINFO:
4191 case CCISS_SETINTINFO:
4192 case CCISS_GETNODENAME:
4193 case CCISS_SETNODENAME:
4194 case CCISS_GETHEARTBEAT:
4195 case CCISS_GETBUSTYPES:
4196 case CCISS_GETFIRMVER:
4197 case CCISS_GETDRIVVER:
4198 case CCISS_REVALIDVOLS:
4199 case CCISS_DEREGDISK:
4200 case CCISS_REGNEWDISK:
4201 case CCISS_REGNEWD:
4202 case CCISS_RESCANDISK:
4203 case CCISS_GETLUNINFO:
4204 return hpsa_ioctl(dev, cmd, arg);
4205
4206 case CCISS_PASSTHRU32:
4207 return hpsa_ioctl32_passthru(dev, cmd, arg);
4208 case CCISS_BIG_PASSTHRU32:
4209 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
4210
4211 default:
4212 return -ENOIOCTLCMD;
4213 }
4214}
edd16368
SC		 4215#endif
4216
4217static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
4218{
4219 struct hpsa_pci_info pciinfo;
4220
4221 if (!argp)
4222 return -EINVAL;
4223 pciinfo.domain = pci_domain_nr(h->pdev->bus);
4224 pciinfo.bus = h->pdev->bus->number;
4225 pciinfo.dev_fn = h->pdev->devfn;
4226 pciinfo.board_id = h->board_id;
4227 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
4228 return -EFAULT;
4229 return 0;
4230}
4231
4232static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
4233{
4234 DriverVer_type DriverVer;
4235 unsigned char vmaj, vmin, vsubmin;
4236 int rc;
4237
4238 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
4239 &vmaj, &vmin, &vsubmin);
4240 if (rc != 3) {
4241 dev_info(&h->pdev->dev, "driver version string '%s' "
4242 "unrecognized.", HPSA_DRIVER_VERSION);
4243 vmaj = 0;
4244 vmin = 0;
4245 vsubmin = 0;
4246 }
4247 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
4248 if (!argp)
4249 return -EINVAL;
4250 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
4251 return -EFAULT;
4252 return 0;
4253}
4254
4255static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4256{
4257 IOCTL_Command_struct iocommand;
4258 struct CommandList *c;
4259 char *buff = NULL;
4260 union u64bit temp64;
c1f63c8f 4261 int rc = 0;
edd16368
SC		 4262
4263 if (!argp)
4264 return -EINVAL;
4265 if (!capable(CAP_SYS_RAWIO))
4266 return -EPERM;
4267 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
4268 return -EFAULT;
4269 if ((iocommand.buf_size < 1) &&
4270 (iocommand.Request.Type.Direction != XFER_NONE)) {
4271 return -EINVAL;
4272 }
4273 if (iocommand.buf_size > 0) {
4274 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
4275 if (buff == NULL)
4276 return -EFAULT;
b03a7771
SC		 4277 if (iocommand.Request.Type.Direction == XFER_WRITE) {
4278 /* Copy the data into the buffer we created */
4279 if (copy_from_user(buff, iocommand.buf,
4280 iocommand.buf_size)) {
c1f63c8f
SC		 4281 rc = -EFAULT;
4282 goto out_kfree;
b03a7771
SC		 4283 }
4284 } else {
4285 memset(buff, 0, iocommand.buf_size);
edd16368 4286 }
b03a7771 4287 }
edd16368
SC		 4288 c = cmd_special_alloc(h);
4289 if (c == NULL) {
c1f63c8f
SC		 4290 rc = -ENOMEM;
4291 goto out_kfree;
edd16368
SC		 4292 }
4293 /* Fill in the command type */
4294 c->cmd_type = CMD_IOCTL_PEND;
4295 /* Fill in Command Header */
4296 c->Header.ReplyQueue = 0; /* unused in simple mode */
4297 if (iocommand.buf_size > 0) { /* buffer to fill */
4298 c->Header.SGList = 1;
4299 c->Header.SGTotal = 1;
4300 } else { /* no buffers to fill */
4301 c->Header.SGList = 0;
4302 c->Header.SGTotal = 0;
4303 }
4304 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
4305 /* use the kernel address the cmd block for tag */
4306 c->Header.Tag.lower = c->busaddr;
4307
4308 /* Fill in Request block */
4309 memcpy(&c->Request, &iocommand.Request,
4310 sizeof(c->Request));
4311
4312 /* Fill in the scatter gather information */
4313 if (iocommand.buf_size > 0) {
4314 temp64.val = pci_map_single(h->pdev, buff,
4315 iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4316 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4317 c->SG[0].Addr.lower = 0;
4318 c->SG[0].Addr.upper = 0;
4319 c->SG[0].Len = 0;
4320 rc = -ENOMEM;
4321 goto out;
4322 }
edd16368
SC		 4323 c->SG[0].Addr.lower = temp64.val32.lower;
4324 c->SG[0].Addr.upper = temp64.val32.upper;
4325 c->SG[0].Len = iocommand.buf_size;
e1d9cbfa 4326 c->SG[0].Ext = HPSA_SG_LAST; /* we are not chaining*/
edd16368 4327 }
a0c12413 4328 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
c2dd32e0
SC		 4329 if (iocommand.buf_size > 0)
4330 hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4331 check_ioctl_unit_attention(h, c);
4332
4333 /* Copy the error information out */
4334 memcpy(&iocommand.error_info, c->err_info,
4335 sizeof(iocommand.error_info));
4336 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 4337 rc = -EFAULT;
4338 goto out;
edd16368 4339 }
b03a7771
SC		 4340 if (iocommand.Request.Type.Direction == XFER_READ &&
4341 iocommand.buf_size > 0) {
edd16368
SC		 4342 /* Copy the data out of the buffer we created */
4343 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 4344 rc = -EFAULT;
4345 goto out;
edd16368
SC		 4346 }
4347 }
c1f63c8f 4348out:
edd16368 4349 cmd_special_free(h, c);
c1f63c8f
SC		 4350out_kfree:
4351 kfree(buff);
4352 return rc;
edd16368
SC		 4353}
4354
4355static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
4356{
4357 BIG_IOCTL_Command_struct *ioc;
4358 struct CommandList *c;
4359 unsigned char **buff = NULL;
4360 int *buff_size = NULL;
4361 union u64bit temp64;
4362 BYTE sg_used = 0;
4363 int status = 0;
4364 int i;
01a02ffc
SC		 4365 u32 left;
4366 u32 sz;
edd16368
SC		 4367 BYTE __user *data_ptr;
4368
4369 if (!argp)
4370 return -EINVAL;
4371 if (!capable(CAP_SYS_RAWIO))
4372 return -EPERM;
4373 ioc = (BIG_IOCTL_Command_struct *)
4374 kmalloc(sizeof(*ioc), GFP_KERNEL);
4375 if (!ioc) {
4376 status = -ENOMEM;
4377 goto cleanup1;
4378 }
4379 if (copy_from_user(ioc, argp, sizeof(*ioc))) {
4380 status = -EFAULT;
4381 goto cleanup1;
4382 }
4383 if ((ioc->buf_size < 1) &&
4384 (ioc->Request.Type.Direction != XFER_NONE)) {
4385 status = -EINVAL;
4386 goto cleanup1;
4387 }
4388 /* Check kmalloc limits using all SGs */
4389 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
4390 status = -EINVAL;
4391 goto cleanup1;
4392 }
d66ae08b 4393 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 4394 status = -EINVAL;
4395 goto cleanup1;
4396 }
d66ae08b 4397 buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
edd16368
SC		 4398 if (!buff) {
4399 status = -ENOMEM;
4400 goto cleanup1;
4401 }
d66ae08b 4402 buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
edd16368
SC		 4403 if (!buff_size) {
4404 status = -ENOMEM;
4405 goto cleanup1;
4406 }
4407 left = ioc->buf_size;
4408 data_ptr = ioc->buf;
4409 while (left) {
4410 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
4411 buff_size[sg_used] = sz;
4412 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
4413 if (buff[sg_used] == NULL) {
4414 status = -ENOMEM;
4415 goto cleanup1;
4416 }
4417 if (ioc->Request.Type.Direction == XFER_WRITE) {
4418 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
4419 status = -ENOMEM;
4420 goto cleanup1;
4421 }
4422 } else
4423 memset(buff[sg_used], 0, sz);
4424 left -= sz;
4425 data_ptr += sz;
4426 sg_used++;
4427 }
4428 c = cmd_special_alloc(h);
4429 if (c == NULL) {
4430 status = -ENOMEM;
4431 goto cleanup1;
4432 }
4433 c->cmd_type = CMD_IOCTL_PEND;
4434 c->Header.ReplyQueue = 0;
b03a7771 4435 c->Header.SGList = c->Header.SGTotal = sg_used;
edd16368
SC		 4436 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
4437 c->Header.Tag.lower = c->busaddr;
4438 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
4439 if (ioc->buf_size > 0) {
4440 int i;
4441 for (i = 0; i < sg_used; i++) {
4442 temp64.val = pci_map_single(h->pdev, buff[i],
4443 buff_size[i], PCI_DMA_BIDIRECTIONAL);
bcc48ffa
SC		 4444 if (dma_mapping_error(&h->pdev->dev, temp64.val)) {
4445 c->SG[i].Addr.lower = 0;
4446 c->SG[i].Addr.upper = 0;
4447 c->SG[i].Len = 0;
4448 hpsa_pci_unmap(h->pdev, c, i,
4449 PCI_DMA_BIDIRECTIONAL);
4450 status = -ENOMEM;
e2d4a1f6 4451 goto cleanup0;
bcc48ffa 4452 }
edd16368
SC		 4453 c->SG[i].Addr.lower = temp64.val32.lower;
4454 c->SG[i].Addr.upper = temp64.val32.upper;
4455 c->SG[i].Len = buff_size[i];
e1d9cbfa 4456 c->SG[i].Ext = i < sg_used - 1 ? 0 : HPSA_SG_LAST;
edd16368
SC		 4457 }
4458 }
a0c12413 4459 hpsa_scsi_do_simple_cmd_core_if_no_lockup(h, c);
b03a7771
SC		 4460 if (sg_used)
4461 hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
edd16368
SC		 4462 check_ioctl_unit_attention(h, c);
4463 /* Copy the error information out */
4464 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
4465 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 4466 status = -EFAULT;
e2d4a1f6 4467 goto cleanup0;
edd16368 4468 }
b03a7771 4469 if (ioc->Request.Type.Direction == XFER_READ && ioc->buf_size > 0) {
edd16368
SC		 4470 /* Copy the data out of the buffer we created */
4471 BYTE __user *ptr = ioc->buf;
4472 for (i = 0; i < sg_used; i++) {
4473 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 4474 status = -EFAULT;
e2d4a1f6 4475 goto cleanup0;
edd16368
SC		 4476 }
4477 ptr += buff_size[i];
4478 }
4479 }
edd16368 4480 status = 0;
e2d4a1f6
SC		 4481cleanup0:
4482 cmd_special_free(h, c);
edd16368
SC		 4483cleanup1:
4484 if (buff) {
4485 for (i = 0; i < sg_used; i++)
4486 kfree(buff[i]);
4487 kfree(buff);
4488 }
4489 kfree(buff_size);
4490 kfree(ioc);
4491 return status;
4492}
4493
4494static void check_ioctl_unit_attention(struct ctlr_info *h,
4495 struct CommandList *c)
4496{
4497 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
4498 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
4499 (void) check_for_unit_attention(h, c);
4500}
0390f0c0
SC		 4501
4502static int increment_passthru_count(struct ctlr_info *h)
4503{
4504 unsigned long flags;
4505
4506 spin_lock_irqsave(&h->passthru_count_lock, flags);
4507 if (h->passthru_count >= HPSA_MAX_CONCURRENT_PASSTHRUS) {
4508 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4509 return -1;
4510 }
4511 h->passthru_count++;
4512 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4513 return 0;
4514}
4515
4516static void decrement_passthru_count(struct ctlr_info *h)
4517{
4518 unsigned long flags;
4519
4520 spin_lock_irqsave(&h->passthru_count_lock, flags);
4521 if (h->passthru_count <= 0) {
4522 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4523 /* not expecting to get here. */
4524 dev_warn(&h->pdev->dev, "Bug detected, passthru_count seems to be incorrect.\n");
4525 return;
4526 }
4527 h->passthru_count--;
4528 spin_unlock_irqrestore(&h->passthru_count_lock, flags);
4529}
4530
edd16368
SC		 4531/*
4532 * ioctl
4533 */
4534static int hpsa_ioctl(struct scsi_device *dev, int cmd, void *arg)
4535{
4536 struct ctlr_info *h;
4537 void __user *argp = (void __user *)arg;
0390f0c0 4538 int rc;
edd16368
SC		 4539
4540 h = sdev_to_hba(dev);
4541
4542 switch (cmd) {
4543 case CCISS_DEREGDISK:
4544 case CCISS_REGNEWDISK:
4545 case CCISS_REGNEWD:
a08a8471 4546 hpsa_scan_start(h->scsi_host);
edd16368
SC		 4547 return 0;
4548 case CCISS_GETPCIINFO:
4549 return hpsa_getpciinfo_ioctl(h, argp);
4550 case CCISS_GETDRIVVER:
4551 return hpsa_getdrivver_ioctl(h, argp);
4552 case CCISS_PASSTHRU:
0390f0c0
SC		 4553 if (increment_passthru_count(h))
4554 return -EAGAIN;
4555 rc = hpsa_passthru_ioctl(h, argp);
4556 decrement_passthru_count(h);
4557 return rc;
edd16368 4558 case CCISS_BIG_PASSTHRU:
0390f0c0
SC		 4559 if (increment_passthru_count(h))
4560 return -EAGAIN;
4561 rc = hpsa_big_passthru_ioctl(h, argp);
4562 decrement_passthru_count(h);
4563 return rc;
edd16368
SC		 4564 default:
4565 return -ENOTTY;
4566 }
4567}
4568
6f039790
GKH		 4569static int hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
4570 u8 reset_type)
64670ac8
SC		 4571{
4572 struct CommandList *c;
4573
4574 c = cmd_alloc(h);
4575 if (!c)
4576 return -ENOMEM;
a2dac136
SC		 4577 /* fill_cmd can't fail here, no data buffer to map */
4578 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 4579 RAID_CTLR_LUNID, TYPE_MSG);
4580 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
4581 c->waiting = NULL;
4582 enqueue_cmd_and_start_io(h, c);
4583 /* Don't wait for completion, the reset won't complete. Don't free
4584 * the command either. This is the last command we will send before
4585 * re-initializing everything, so it doesn't matter and won't leak.
4586 */
4587 return 0;
4588}
4589
a2dac136 4590static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
01a02ffc 4591 void *buff, size_t size, u8 page_code, unsigned char *scsi3addr,
edd16368
SC		 4592 int cmd_type)
4593{
4594 int pci_dir = XFER_NONE;
75167d2c 4595 struct CommandList *a; /* for commands to be aborted */
edd16368
SC		 4596
4597 c->cmd_type = CMD_IOCTL_PEND;
4598 c->Header.ReplyQueue = 0;
4599 if (buff != NULL && size > 0) {
4600 c->Header.SGList = 1;
4601 c->Header.SGTotal = 1;
4602 } else {
4603 c->Header.SGList = 0;
4604 c->Header.SGTotal = 0;
4605 }
4606 c->Header.Tag.lower = c->busaddr;
4607 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
4608
4609 c->Request.Type.Type = cmd_type;
4610 if (cmd_type == TYPE_CMD) {
4611 switch (cmd) {
4612 case HPSA_INQUIRY:
4613 /* are we trying to read a vital product page */
4614 if (page_code != 0) {
4615 c->Request.CDB[1] = 0x01;
4616 c->Request.CDB[2] = page_code;
4617 }
4618 c->Request.CDBLen = 6;
4619 c->Request.Type.Attribute = ATTR_SIMPLE;
4620 c->Request.Type.Direction = XFER_READ;
4621 c->Request.Timeout = 0;
4622 c->Request.CDB[0] = HPSA_INQUIRY;
4623 c->Request.CDB[4] = size & 0xFF;
4624 break;
4625 case HPSA_REPORT_LOG:
4626 case HPSA_REPORT_PHYS:
4627 /* Talking to controller so It's a physical command
4628 mode = 00 target = 0. Nothing to write.
4629 */
4630 c->Request.CDBLen = 12;
4631 c->Request.Type.Attribute = ATTR_SIMPLE;
4632 c->Request.Type.Direction = XFER_READ;
4633 c->Request.Timeout = 0;
4634 c->Request.CDB[0] = cmd;
4635 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
4636 c->Request.CDB[7] = (size >> 16) & 0xFF;
4637 c->Request.CDB[8] = (size >> 8) & 0xFF;
4638 c->Request.CDB[9] = size & 0xFF;
4639 break;
edd16368
SC		 4640 case HPSA_CACHE_FLUSH:
4641 c->Request.CDBLen = 12;
4642 c->Request.Type.Attribute = ATTR_SIMPLE;
4643 c->Request.Type.Direction = XFER_WRITE;
4644 c->Request.Timeout = 0;
4645 c->Request.CDB[0] = BMIC_WRITE;
4646 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 4647 c->Request.CDB[7] = (size >> 8) & 0xFF;
4648 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 4649 break;
4650 case TEST_UNIT_READY:
4651 c->Request.CDBLen = 6;
4652 c->Request.Type.Attribute = ATTR_SIMPLE;
4653 c->Request.Type.Direction = XFER_NONE;
4654 c->Request.Timeout = 0;
4655 break;
283b4a9b
SC		 4656 case HPSA_GET_RAID_MAP:
4657 c->Request.CDBLen = 12;
4658 c->Request.Type.Attribute = ATTR_SIMPLE;
4659 c->Request.Type.Direction = XFER_READ;
4660 c->Request.Timeout = 0;
4661 c->Request.CDB[0] = HPSA_CISS_READ;
4662 c->Request.CDB[1] = cmd;
4663 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
4664 c->Request.CDB[7] = (size >> 16) & 0xFF;
4665 c->Request.CDB[8] = (size >> 8) & 0xFF;
4666 c->Request.CDB[9] = size & 0xFF;
4667 break;
edd16368
SC		 4668 default:
4669 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
4670 BUG();
a2dac136 4671 return -1;
edd16368
SC		 4672 }
4673 } else if (cmd_type == TYPE_MSG) {
4674 switch (cmd) {
4675
4676 case HPSA_DEVICE_RESET_MSG:
4677 c->Request.CDBLen = 16;
4678 c->Request.Type.Type = 1; /* It is a MSG not a CMD */
4679 c->Request.Type.Attribute = ATTR_SIMPLE;
4680 c->Request.Type.Direction = XFER_NONE;
4681 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 4682 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
4683 c->Request.CDB[0] = cmd;
21e89afd 4684 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 4685 /* If bytes 4-7 are zero, it means reset the */
4686 /* LunID device */
4687 c->Request.CDB[4] = 0x00;
4688 c->Request.CDB[5] = 0x00;
4689 c->Request.CDB[6] = 0x00;
4690 c->Request.CDB[7] = 0x00;
75167d2c
SC		 4691 break;
4692 case HPSA_ABORT_MSG:
4693 a = buff; /* point to command to be aborted */
4694 dev_dbg(&h->pdev->dev, "Abort Tag:0x%08x:%08x using request Tag:0x%08x:%08x\n",
4695 a->Header.Tag.upper, a->Header.Tag.lower,
4696 c->Header.Tag.upper, c->Header.Tag.lower);
4697 c->Request.CDBLen = 16;
4698 c->Request.Type.Type = TYPE_MSG;
4699 c->Request.Type.Attribute = ATTR_SIMPLE;
4700 c->Request.Type.Direction = XFER_WRITE;
4701 c->Request.Timeout = 0; /* Don't time out */
4702 c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
4703 c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
4704 c->Request.CDB[2] = 0x00; /* reserved */
4705 c->Request.CDB[3] = 0x00; /* reserved */
4706 /* Tag to abort goes in CDB[4]-CDB[11] */
4707 c->Request.CDB[4] = a->Header.Tag.lower & 0xFF;
4708 c->Request.CDB[5] = (a->Header.Tag.lower >> 8) & 0xFF;
4709 c->Request.CDB[6] = (a->Header.Tag.lower >> 16) & 0xFF;
4710 c->Request.CDB[7] = (a->Header.Tag.lower >> 24) & 0xFF;
4711 c->Request.CDB[8] = a->Header.Tag.upper & 0xFF;
4712 c->Request.CDB[9] = (a->Header.Tag.upper >> 8) & 0xFF;
4713 c->Request.CDB[10] = (a->Header.Tag.upper >> 16) & 0xFF;
4714 c->Request.CDB[11] = (a->Header.Tag.upper >> 24) & 0xFF;
4715 c->Request.CDB[12] = 0x00; /* reserved */
4716 c->Request.CDB[13] = 0x00; /* reserved */
4717 c->Request.CDB[14] = 0x00; /* reserved */
4718 c->Request.CDB[15] = 0x00; /* reserved */
edd16368 4719 break;
edd16368
SC		 4720 default:
4721 dev_warn(&h->pdev->dev, "unknown message type %d\n",
4722 cmd);
4723 BUG();
4724 }
4725 } else {
4726 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
4727 BUG();
4728 }
4729
4730 switch (c->Request.Type.Direction) {
4731 case XFER_READ:
4732 pci_dir = PCI_DMA_FROMDEVICE;
4733 break;
4734 case XFER_WRITE:
4735 pci_dir = PCI_DMA_TODEVICE;
4736 break;
4737 case XFER_NONE:
4738 pci_dir = PCI_DMA_NONE;
4739 break;
4740 default:
4741 pci_dir = PCI_DMA_BIDIRECTIONAL;
4742 }
a2dac136
SC		 4743 if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
4744 return -1;
4745 return 0;
edd16368
SC		 4746}
4747
4748/*
4749 * Map (physical) PCI mem into (virtual) kernel space
4750 */
4751static void __iomem *remap_pci_mem(ulong base, ulong size)
4752{
4753 ulong page_base = ((ulong) base) & PAGE_MASK;
4754 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 4755 void __iomem *page_remapped = ioremap_nocache(page_base,
4756 page_offs + size);
edd16368
SC		 4757
4758 return page_remapped ? (page_remapped + page_offs) : NULL;
4759}
4760
4761/* Takes cmds off the submission queue and sends them to the hardware,
4762 * then puts them on the queue of cmds waiting for completion.
4763 */
4764static void start_io(struct ctlr_info *h)
4765{
4766 struct CommandList *c;
e16a33ad 4767 unsigned long flags;
edd16368 4768
e16a33ad 4769 spin_lock_irqsave(&h->lock, flags);
9e0fc764
SC		 4770 while (!list_empty(&h->reqQ)) {
4771 c = list_entry(h->reqQ.next, struct CommandList, list);
edd16368
SC		 4772 /* can't do anything if fifo is full */
4773 if ((h->access.fifo_full(h))) {
396883e2 4774 h->fifo_recently_full = 1;
edd16368
SC		 4775 dev_warn(&h->pdev->dev, "fifo full\n");
4776 break;
4777 }
396883e2 4778 h->fifo_recently_full = 0;
edd16368
SC		 4779
4780 /* Get the first entry from the Request Q */
4781 removeQ(c);
4782 h->Qdepth--;
4783
edd16368
SC		 4784 /* Put job onto the completed Q */
4785 addQ(&h->cmpQ, c);
e16a33ad
MG		 4786
4787 /* Must increment commands_outstanding before unlocking
4788 * and submitting to avoid race checking for fifo full
4789 * condition.
4790 */
4791 h->commands_outstanding++;
4792 if (h->commands_outstanding > h->max_outstanding)
4793 h->max_outstanding = h->commands_outstanding;
4794
4795 /* Tell the controller execute command */
4796 spin_unlock_irqrestore(&h->lock, flags);
4797 h->access.submit_command(h, c);
4798 spin_lock_irqsave(&h->lock, flags);
edd16368 4799 }
e16a33ad 4800 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 4801}
4802
254f796b 4803static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 4804{
254f796b 4805 return h->access.command_completed(h, q);
edd16368
SC		 4806}
4807
900c5440 4808static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 4809{
4810 return h->access.intr_pending(h);
4811}
4812
4813static inline long interrupt_not_for_us(struct ctlr_info *h)
4814{
10f66018
SC		 4815 return (h->access.intr_pending(h) == 0) ||
4816 (h->interrupts_enabled == 0);
edd16368
SC		 4817}
4818
01a02ffc
SC		 4819static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
4820 u32 raw_tag)
edd16368
SC		 4821{
4822 if (unlikely(tag_index >= h->nr_cmds)) {
4823 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
4824 return 1;
4825 }
4826 return 0;
4827}
4828
5a3d16f5 4829static inline void finish_cmd(struct CommandList *c)
edd16368 4830{
e16a33ad 4831 unsigned long flags;
396883e2
SC		 4832 int io_may_be_stalled = 0;
4833 struct ctlr_info *h = c->h;
e16a33ad 4834
396883e2 4835 spin_lock_irqsave(&h->lock, flags);
edd16368 4836 removeQ(c);
396883e2
SC		 4837
4838 /*
4839 * Check for possibly stalled i/o.
4840 *
4841 * If a fifo_full condition is encountered, requests will back up
4842 * in h->reqQ. This queue is only emptied out by start_io which is
4843 * only called when a new i/o request comes in. If no i/o's are
4844 * forthcoming, the i/o's in h->reqQ can get stuck. So we call
4845 * start_io from here if we detect such a danger.
4846 *
4847 * Normally, we shouldn't hit this case, but pounding on the
4848 * CCISS_PASSTHRU ioctl can provoke it. Only call start_io if
4849 * commands_outstanding is low. We want to avoid calling
4850 * start_io from in here as much as possible, and esp. don't
4851 * want to get in a cycle where we call start_io every time
4852 * through here.
4853 */
4854 if (unlikely(h->fifo_recently_full) &&
4855 h->commands_outstanding < 5)
4856 io_may_be_stalled = 1;
4857
4858 spin_unlock_irqrestore(&h->lock, flags);
4859
e85c5974 4860 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 4861 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
4862 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 4863 complete_scsi_command(c);
edd16368
SC		 4864 else if (c->cmd_type == CMD_IOCTL_PEND)
4865 complete(c->waiting);
396883e2
SC		 4866 if (unlikely(io_may_be_stalled))
4867 start_io(h);
edd16368
SC		 4868}
4869
a104c99f
SC		 4870static inline u32 hpsa_tag_contains_index(u32 tag)
4871{
a104c99f
SC		 4872 return tag & DIRECT_LOOKUP_BIT;
4873}
4874
4875static inline u32 hpsa_tag_to_index(u32 tag)
4876{
a104c99f
SC		 4877 return tag >> DIRECT_LOOKUP_SHIFT;
4878}
4879
a9a3a273
SC		 4880
4881static inline u32 hpsa_tag_discard_error_bits(struct ctlr_info *h, u32 tag)
a104c99f 4882{
a9a3a273
SC		 4883#define HPSA_PERF_ERROR_BITS ((1 << DIRECT_LOOKUP_SHIFT) - 1)
4884#define HPSA_SIMPLE_ERROR_BITS 0x03
960a30e7 4885 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
a9a3a273
SC		 4886 return tag & ~HPSA_SIMPLE_ERROR_BITS;
4887 return tag & ~HPSA_PERF_ERROR_BITS;
a104c99f
SC		 4888}
4889
303932fd 4890/* process completion of an indexed ("direct lookup") command */
1d94f94d 4891static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 4892 u32 raw_tag)
4893{
4894 u32 tag_index;
4895 struct CommandList *c;
4896
4897 tag_index = hpsa_tag_to_index(raw_tag);
1d94f94d
SC		 4898 if (!bad_tag(h, tag_index, raw_tag)) {
4899 c = h->cmd_pool + tag_index;
4900 finish_cmd(c);
4901 }
303932fd
DB		 4902}
4903
4904/* process completion of a non-indexed command */
1d94f94d 4905static inline void process_nonindexed_cmd(struct ctlr_info *h,
303932fd
DB		 4906 u32 raw_tag)
4907{
4908 u32 tag;
4909 struct CommandList *c = NULL;
e16a33ad 4910 unsigned long flags;
303932fd 4911
a9a3a273 4912 tag = hpsa_tag_discard_error_bits(h, raw_tag);
e16a33ad 4913 spin_lock_irqsave(&h->lock, flags);
9e0fc764 4914 list_for_each_entry(c, &h->cmpQ, list) {
303932fd 4915 if ((c->busaddr & 0xFFFFFFE0) == (tag & 0xFFFFFFE0)) {
e16a33ad 4916 spin_unlock_irqrestore(&h->lock, flags);
5a3d16f5 4917 finish_cmd(c);
1d94f94d 4918 return;
303932fd
DB		 4919 }
4920 }
e16a33ad 4921 spin_unlock_irqrestore(&h->lock, flags);
303932fd 4922 bad_tag(h, h->nr_cmds + 1, raw_tag);
303932fd
DB		 4923}
4924
64670ac8
SC		 4925/* Some controllers, like p400, will give us one interrupt
4926 * after a soft reset, even if we turned interrupts off.
4927 * Only need to check for this in the hpsa_xxx_discard_completions
4928 * functions.
4929 */
4930static int ignore_bogus_interrupt(struct ctlr_info *h)
4931{
4932 if (likely(!reset_devices))
4933 return 0;
4934
4935 if (likely(h->interrupts_enabled))
4936 return 0;
4937
4938 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
4939 "(known firmware bug.) Ignoring.\n");
4940
4941 return 1;
4942}
4943
254f796b
MG		 4944/*
4945 * Convert &h->q[x] (passed to interrupt handlers) back to h.
4946 * Relies on (h-q[x] == x) being true for x such that
4947 * 0 <= x < MAX_REPLY_QUEUES.
4948 */
4949static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 4950{
254f796b
MG		 4951 return container_of((queue - *queue), struct ctlr_info, q[0]);
4952}
4953
4954static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
4955{
4956 struct ctlr_info *h = queue_to_hba(queue);
4957 u8 q = *(u8 *) queue;
64670ac8
SC		 4958 u32 raw_tag;
4959
4960 if (ignore_bogus_interrupt(h))
4961 return IRQ_NONE;
4962
4963 if (interrupt_not_for_us(h))
4964 return IRQ_NONE;
a0c12413 4965 h->last_intr_timestamp = get_jiffies_64();
64670ac8 4966 while (interrupt_pending(h)) {
254f796b 4967 raw_tag = get_next_completion(h, q);
64670ac8 4968 while (raw_tag != FIFO_EMPTY)
254f796b 4969 raw_tag = next_command(h, q);
64670ac8 4970 }
64670ac8
SC		 4971 return IRQ_HANDLED;
4972}
4973
254f796b 4974static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 4975{
254f796b 4976 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 4977 u32 raw_tag;
254f796b 4978 u8 q = *(u8 *) queue;
64670ac8
SC		 4979
4980 if (ignore_bogus_interrupt(h))
4981 return IRQ_NONE;
4982
a0c12413 4983 h->last_intr_timestamp = get_jiffies_64();
254f796b 4984 raw_tag = get_next_completion(h, q);
64670ac8 4985 while (raw_tag != FIFO_EMPTY)
254f796b 4986 raw_tag = next_command(h, q);
64670ac8
SC		 4987 return IRQ_HANDLED;
4988}
4989
254f796b 4990static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 4991{
254f796b 4992 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 4993 u32 raw_tag;
254f796b 4994 u8 q = *(u8 *) queue;
edd16368
SC		 4995
4996 if (interrupt_not_for_us(h))
4997 return IRQ_NONE;
a0c12413 4998 h->last_intr_timestamp = get_jiffies_64();
10f66018 4999 while (interrupt_pending(h)) {
254f796b 5000 raw_tag = get_next_completion(h, q);
10f66018 5001 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5002 if (likely(hpsa_tag_contains_index(raw_tag)))
5003 process_indexed_cmd(h, raw_tag);
10f66018 5004 else
1d94f94d 5005 process_nonindexed_cmd(h, raw_tag);
254f796b 5006 raw_tag = next_command(h, q);
10f66018
SC		 5007 }
5008 }
10f66018
SC		 5009 return IRQ_HANDLED;
5010}
5011
254f796b 5012static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 5013{
254f796b 5014 struct ctlr_info *h = queue_to_hba(queue);
10f66018 5015 u32 raw_tag;
254f796b 5016 u8 q = *(u8 *) queue;
10f66018 5017
a0c12413 5018 h->last_intr_timestamp = get_jiffies_64();
254f796b 5019 raw_tag = get_next_completion(h, q);
303932fd 5020 while (raw_tag != FIFO_EMPTY) {
1d94f94d
SC		 5021 if (likely(hpsa_tag_contains_index(raw_tag)))
5022 process_indexed_cmd(h, raw_tag);
303932fd 5023 else
1d94f94d 5024 process_nonindexed_cmd(h, raw_tag);
254f796b 5025 raw_tag = next_command(h, q);
edd16368 5026 }
edd16368
SC		 5027 return IRQ_HANDLED;
5028}
5029
a9a3a273
SC		 5030/* Send a message CDB to the firmware. Careful, this only works
5031 * in simple mode, not performant mode due to the tag lookup.
5032 * We only ever use this immediately after a controller reset.
5033 */
6f039790
GKH		 5034static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
5035 unsigned char type)
edd16368
SC		 5036{
5037 struct Command {
5038 struct CommandListHeader CommandHeader;
5039 struct RequestBlock Request;
5040 struct ErrDescriptor ErrorDescriptor;
5041 };
5042 struct Command *cmd;
5043 static const size_t cmd_sz = sizeof(*cmd) +
5044 sizeof(cmd->ErrorDescriptor);
5045 dma_addr_t paddr64;
5046 uint32_t paddr32, tag;
5047 void __iomem *vaddr;
5048 int i, err;
5049
5050 vaddr = pci_ioremap_bar(pdev, 0);
5051 if (vaddr == NULL)
5052 return -ENOMEM;
5053
5054 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
5055 * CCISS commands, so they must be allocated from the lower 4GiB of
5056 * memory.
5057 */
5058 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
5059 if (err) {
5060 iounmap(vaddr);
5061 return -ENOMEM;
5062 }
5063
5064 cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
5065 if (cmd == NULL) {
5066 iounmap(vaddr);
5067 return -ENOMEM;
5068 }
5069
5070 /* This must fit, because of the 32-bit consistent DMA mask. Also,
5071 * although there's no guarantee, we assume that the address is at
5072 * least 4-byte aligned (most likely, it's page-aligned).
5073 */
5074 paddr32 = paddr64;
5075
5076 cmd->CommandHeader.ReplyQueue = 0;
5077 cmd->CommandHeader.SGList = 0;
5078 cmd->CommandHeader.SGTotal = 0;
5079 cmd->CommandHeader.Tag.lower = paddr32;
5080 cmd->CommandHeader.Tag.upper = 0;
5081 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
5082
5083 cmd->Request.CDBLen = 16;
5084 cmd->Request.Type.Type = TYPE_MSG;
5085 cmd->Request.Type.Attribute = ATTR_HEADOFQUEUE;
5086 cmd->Request.Type.Direction = XFER_NONE;
5087 cmd->Request.Timeout = 0; /* Don't time out */
5088 cmd->Request.CDB[0] = opcode;
5089 cmd->Request.CDB[1] = type;
5090 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
5091 cmd->ErrorDescriptor.Addr.lower = paddr32 + sizeof(*cmd);
5092 cmd->ErrorDescriptor.Addr.upper = 0;
5093 cmd->ErrorDescriptor.Len = sizeof(struct ErrorInfo);
5094
5095 writel(paddr32, vaddr + SA5_REQUEST_PORT_OFFSET);
5096
5097 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
5098 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
a9a3a273 5099 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr32)
edd16368
SC		 5100 break;
5101 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
5102 }
5103
5104 iounmap(vaddr);
5105
5106 /* we leak the DMA buffer here ... no choice since the controller could
5107 * still complete the command.
5108 */
5109 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
5110 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
5111 opcode, type);
5112 return -ETIMEDOUT;
5113 }
5114
5115 pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
5116
5117 if (tag & HPSA_ERROR_BIT) {
5118 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
5119 opcode, type);
5120 return -EIO;
5121 }
5122
5123 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
5124 opcode, type);
5125 return 0;
5126}
5127
edd16368
SC		 5128#define hpsa_noop(p) hpsa_message(p, 3, 0)
5129
1df8552a 5130static int hpsa_controller_hard_reset(struct pci_dev *pdev,
cf0b08d0 5131 void * __iomem vaddr, u32 use_doorbell)
1df8552a
SC		 5132{
5133 u16 pmcsr;
5134 int pos;
5135
5136 if (use_doorbell) {
5137 /* For everything after the P600, the PCI power state method
5138 * of resetting the controller doesn't work, so we have this
5139 * other way using the doorbell register.
5140 */
5141 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 5142 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239
SC		 5143
5144 /* PMC hardware guys tell us we need a 5 second delay after
5145 * doorbell reset and before any attempt to talk to the board
5146 * at all to ensure that this actually works and doesn't fall
5147 * over in some weird corner cases.
5148 */
5149 msleep(5000);
1df8552a
SC		 5150 } else { /* Try to do it the PCI power state way */
5151
5152 /* Quoting from the Open CISS Specification: "The Power
5153 * Management Control/Status Register (CSR) controls the power
5154 * state of the device. The normal operating state is D0,
5155 * CSR=00h. The software off state is D3, CSR=03h. To reset
5156 * the controller, place the interface device in D3 then to D0,
5157 * this causes a secondary PCI reset which will reset the
5158 * controller." */
5159
5160 pos = pci_find_capability(pdev, PCI_CAP_ID_PM);
5161 if (pos == 0) {
5162 dev_err(&pdev->dev,
5163 "hpsa_reset_controller: "
5164 "PCI PM not supported\n");
5165 return -ENODEV;
5166 }
5167 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
5168 /* enter the D3hot power management state */
5169 pci_read_config_word(pdev, pos + PCI_PM_CTRL, &pmcsr);
5170 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5171 pmcsr |= PCI_D3hot;
5172 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
5173
5174 msleep(500);
5175
5176 /* enter the D0 power management state */
5177 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
5178 pmcsr |= PCI_D0;
5179 pci_write_config_word(pdev, pos + PCI_PM_CTRL, pmcsr);
c4853efe
MM		 5180
5181 /*
5182 * The P600 requires a small delay when changing states.
5183 * Otherwise we may think the board did not reset and we bail.
5184 * This for kdump only and is particular to the P600.
5185 */
5186 msleep(500);
1df8552a
SC		 5187 }
5188 return 0;
5189}
5190
6f039790 5191static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 5192{
5193 memset(driver_version, 0, len);
f79cfec6 5194 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 5195}
5196
6f039790 5197static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5198{
5199 char *driver_version;
5200 int i, size = sizeof(cfgtable->driver_version);
5201
5202 driver_version = kmalloc(size, GFP_KERNEL);
5203 if (!driver_version)
5204 return -ENOMEM;
5205
5206 init_driver_version(driver_version, size);
5207 for (i = 0; i < size; i++)
5208 writeb(driver_version[i], &cfgtable->driver_version[i]);
5209 kfree(driver_version);
5210 return 0;
5211}
5212
6f039790
GKH		 5213static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
5214 unsigned char *driver_ver)
580ada3c
SC		 5215{
5216 int i;
5217
5218 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
5219 driver_ver[i] = readb(&cfgtable->driver_version[i]);
5220}
5221
6f039790 5222static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 5223{
5224
5225 char *driver_ver, *old_driver_ver;
5226 int rc, size = sizeof(cfgtable->driver_version);
5227
5228 old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
5229 if (!old_driver_ver)
5230 return -ENOMEM;
5231 driver_ver = old_driver_ver + size;
5232
5233 /* After a reset, the 32 bytes of "driver version" in the cfgtable
5234 * should have been changed, otherwise we know the reset failed.
5235 */
5236 init_driver_version(old_driver_ver, size);
5237 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
5238 rc = !memcmp(driver_ver, old_driver_ver, size);
5239 kfree(old_driver_ver);
5240 return rc;
5241}
edd16368 5242/* This does a hard reset of the controller using PCI power management
1df8552a 5243 * states or the using the doorbell register.
edd16368 5244 */
6f039790 5245static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev)
edd16368 5246{
1df8552a
SC		 5247 u64 cfg_offset;
5248 u32 cfg_base_addr;
5249 u64 cfg_base_addr_index;
5250 void __iomem *vaddr;
5251 unsigned long paddr;
580ada3c 5252 u32 misc_fw_support;
270d05de 5253 int rc;
1df8552a 5254 struct CfgTable __iomem *cfgtable;
cf0b08d0 5255 u32 use_doorbell;
18867659 5256 u32 board_id;
270d05de 5257 u16 command_register;
edd16368 5258
1df8552a
SC		 5259 /* For controllers as old as the P600, this is very nearly
5260 * the same thing as
edd16368
SC		 5261 *
5262 * pci_save_state(pci_dev);
5263 * pci_set_power_state(pci_dev, PCI_D3hot);
5264 * pci_set_power_state(pci_dev, PCI_D0);
5265 * pci_restore_state(pci_dev);
5266 *
1df8552a
SC		 5267 * For controllers newer than the P600, the pci power state
5268 * method of resetting doesn't work so we have another way
5269 * using the doorbell register.
edd16368 5270 */
18867659 5271
25c1e56a 5272 rc = hpsa_lookup_board_id(pdev, &board_id);
46380786 5273 if (rc < 0 || !ctlr_is_resettable(board_id)) {
25c1e56a
SC		 5274 dev_warn(&pdev->dev, "Not resetting device.\n");
5275 return -ENODEV;
5276 }
46380786
SC		 5277
5278 /* if controller is soft- but not hard resettable... */
5279 if (!ctlr_is_hard_resettable(board_id))
5280 return -ENOTSUPP; /* try soft reset later. */
18867659 5281
270d05de
SC		 5282 /* Save the PCI command register */
5283 pci_read_config_word(pdev, 4, &command_register);
5284 /* Turn the board off. This is so that later pci_restore_state()
5285 * won't turn the board on before the rest of config space is ready.
5286 */
5287 pci_disable_device(pdev);
5288 pci_save_state(pdev);
edd16368 5289
1df8552a
SC		 5290 /* find the first memory BAR, so we can find the cfg table */
5291 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
5292 if (rc)
5293 return rc;
5294 vaddr = remap_pci_mem(paddr, 0x250);
5295 if (!vaddr)
5296 return -ENOMEM;
edd16368 5297
1df8552a
SC		 5298 /* find cfgtable in order to check if reset via doorbell is supported */
5299 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
5300 &cfg_base_addr_index, &cfg_offset);
5301 if (rc)
5302 goto unmap_vaddr;
5303 cfgtable = remap_pci_mem(pci_resource_start(pdev,
5304 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
5305 if (!cfgtable) {
5306 rc = -ENOMEM;
5307 goto unmap_vaddr;
5308 }
580ada3c
SC		 5309 rc = write_driver_ver_to_cfgtable(cfgtable);
5310 if (rc)
5311 goto unmap_vaddr;
edd16368 5312
cf0b08d0
SC		 5313 /* If reset via doorbell register is supported, use that.
5314 * There are two such methods. Favor the newest method.
5315 */
1df8552a 5316 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 5317 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
5318 if (use_doorbell) {
5319 use_doorbell = DOORBELL_CTLR_RESET2;
5320 } else {
5321 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
5322 if (use_doorbell) {
fba63097
MM		 5323 dev_warn(&pdev->dev, "Soft reset not supported. "
5324 "Firmware update is required.\n");
64670ac8 5325 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 5326 goto unmap_cfgtable;
5327 }
5328 }
edd16368 5329
1df8552a
SC		 5330 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
5331 if (rc)
5332 goto unmap_cfgtable;
edd16368 5333
270d05de
SC		 5334 pci_restore_state(pdev);
5335 rc = pci_enable_device(pdev);
5336 if (rc) {
5337 dev_warn(&pdev->dev, "failed to enable device.\n");
5338 goto unmap_cfgtable;
edd16368 5339 }
270d05de 5340 pci_write_config_word(pdev, 4, command_register);
edd16368 5341
1df8552a
SC		 5342 /* Some devices (notably the HP Smart Array 5i Controller)
5343 need a little pause here */
5344 msleep(HPSA_POST_RESET_PAUSE_MSECS);
5345
fe5389c8
SC		 5346 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
5347 if (rc) {
5348 dev_warn(&pdev->dev,
64670ac8
SC		 5349 "failed waiting for board to become ready "
5350 "after hard reset\n");
fe5389c8
SC		 5351 goto unmap_cfgtable;
5352 }
fe5389c8 5353
580ada3c
SC		 5354 rc = controller_reset_failed(vaddr);
5355 if (rc < 0)
5356 goto unmap_cfgtable;
5357 if (rc) {
64670ac8
SC		 5358 dev_warn(&pdev->dev, "Unable to successfully reset "
5359 "controller. Will try soft reset.\n");
5360 rc = -ENOTSUPP;
580ada3c 5361 } else {
64670ac8 5362 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 5363 }
5364
5365unmap_cfgtable:
5366 iounmap(cfgtable);
5367
5368unmap_vaddr:
5369 iounmap(vaddr);
5370 return rc;
edd16368
SC		 5371}
5372
5373/*
5374 * We cannot read the structure directly, for portability we must use
5375 * the io functions.
5376 * This is for debug only.
5377 */
edd16368
SC		 5378static void print_cfg_table(struct device *dev, struct CfgTable *tb)
5379{
58f8665c 5380#ifdef HPSA_DEBUG
edd16368
SC		 5381 int i;
5382 char temp_name[17];
5383
5384 dev_info(dev, "Controller Configuration information\n");
5385 dev_info(dev, "------------------------------------\n");
5386 for (i = 0; i < 4; i++)
5387 temp_name[i] = readb(&(tb->Signature[i]));
5388 temp_name[4] = '\0';
5389 dev_info(dev, " Signature = %s\n", temp_name);
5390 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
5391 dev_info(dev, " Transport methods supported = 0x%x\n",
5392 readl(&(tb->TransportSupport)));
5393 dev_info(dev, " Transport methods active = 0x%x\n",
5394 readl(&(tb->TransportActive)));
5395 dev_info(dev, " Requested transport Method = 0x%x\n",
5396 readl(&(tb->HostWrite.TransportRequest)));
5397 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
5398 readl(&(tb->HostWrite.CoalIntDelay)));
5399 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
5400 readl(&(tb->HostWrite.CoalIntCount)));
5401 dev_info(dev, " Max outstanding commands = 0x%d\n",
5402 readl(&(tb->CmdsOutMax)));
5403 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
5404 for (i = 0; i < 16; i++)
5405 temp_name[i] = readb(&(tb->ServerName[i]));
5406 temp_name[16] = '\0';
5407 dev_info(dev, " Server Name = %s\n", temp_name);
5408 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
5409 readl(&(tb->HeartBeat)));
edd16368 5410#endif /* HPSA_DEBUG */
58f8665c 5411}
edd16368
SC		 5412
5413static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
5414{
5415 int i, offset, mem_type, bar_type;
5416
5417 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
5418 return 0;
5419 offset = 0;
5420 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
5421 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
5422 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
5423 offset += 4;
5424 else {
5425 mem_type = pci_resource_flags(pdev, i) &
5426 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
5427 switch (mem_type) {
5428 case PCI_BASE_ADDRESS_MEM_TYPE_32:
5429 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
5430 offset += 4; /* 32 bit */
5431 break;
5432 case PCI_BASE_ADDRESS_MEM_TYPE_64:
5433 offset += 8;
5434 break;
5435 default: /* reserved in PCI 2.2 */
5436 dev_warn(&pdev->dev,
5437 "base address is invalid\n");
5438 return -1;
5439 break;
5440 }
5441 }
5442 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
5443 return i + 1;
5444 }
5445 return -1;
5446}
5447
5448/* If MSI/MSI-X is supported by the kernel we will try to enable it on
5449 * controllers that are capable. If not, we use IO-APIC mode.
5450 */
5451
6f039790 5452static void hpsa_interrupt_mode(struct ctlr_info *h)
edd16368
SC		 5453{
5454#ifdef CONFIG_PCI_MSI
254f796b
MG		 5455 int err, i;
5456 struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
5457
5458 for (i = 0; i < MAX_REPLY_QUEUES; i++) {
5459 hpsa_msix_entries[i].vector = 0;
5460 hpsa_msix_entries[i].entry = i;
5461 }
edd16368
SC		 5462
5463 /* Some boards advertise MSI but don't really support it */
6b3f4c52
SC		 5464 if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
5465 (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
edd16368 5466 goto default_int_mode;
55c06c71
SC		 5467 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
5468 dev_info(&h->pdev->dev, "MSIX\n");
eee0f03a 5469 h->msix_vector = MAX_REPLY_QUEUES;
254f796b 5470 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
eee0f03a 5471 h->msix_vector);
edd16368 5472 if (err > 0) {
55c06c71 5473 dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
edd16368 5474 "available\n", err);
eee0f03a
HR		 5475 h->msix_vector = err;
5476 err = pci_enable_msix(h->pdev, hpsa_msix_entries,
5477 h->msix_vector);
5478 }
5479 if (!err) {
5480 for (i = 0; i < h->msix_vector; i++)
5481 h->intr[i] = hpsa_msix_entries[i].vector;
5482 return;
edd16368 5483 } else {
55c06c71 5484 dev_warn(&h->pdev->dev, "MSI-X init failed %d\n",
edd16368 5485 err);
eee0f03a 5486 h->msix_vector = 0;
edd16368
SC		 5487 goto default_int_mode;
5488 }
5489 }
55c06c71
SC		 5490 if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
5491 dev_info(&h->pdev->dev, "MSI\n");
5492 if (!pci_enable_msi(h->pdev))
edd16368
SC		 5493 h->msi_vector = 1;
5494 else
55c06c71 5495 dev_warn(&h->pdev->dev, "MSI init failed\n");
edd16368
SC		 5496 }
5497default_int_mode:
5498#endif /* CONFIG_PCI_MSI */
5499 /* if we get here we're going to use the default interrupt mode */
a9a3a273 5500 h->intr[h->intr_mode] = h->pdev->irq;
edd16368
SC		 5501}
5502
6f039790 5503static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
e5c880d1
SC		 5504{
5505 int i;
5506 u32 subsystem_vendor_id, subsystem_device_id;
5507
5508 subsystem_vendor_id = pdev->subsystem_vendor;
5509 subsystem_device_id = pdev->subsystem_device;
5510 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
5511 subsystem_vendor_id;
5512
5513 for (i = 0; i < ARRAY_SIZE(products); i++)
5514 if (*board_id == products[i].board_id)
5515 return i;
5516
6798cc0a
SC		 5517 if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
5518 subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
5519 !hpsa_allow_any) {
e5c880d1
SC		 5520 dev_warn(&pdev->dev, "unrecognized board ID: "
5521 "0x%08x, ignoring.\n", *board_id);
5522 return -ENODEV;
5523 }
5524 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
5525}
5526
6f039790
GKH		 5527static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
5528 unsigned long *memory_bar)
3a7774ce
SC		 5529{
5530 int i;
5531
5532 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 5533 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 5534 /* addressing mode bits already removed */
12d2cd47
SC		 5535 *memory_bar = pci_resource_start(pdev, i);
5536 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 5537 *memory_bar);
5538 return 0;
5539 }
12d2cd47 5540 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 5541 return -ENODEV;
5542}
5543
6f039790
GKH		 5544static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
5545 int wait_for_ready)
2c4c8c8b 5546{
fe5389c8 5547 int i, iterations;
2c4c8c8b 5548 u32 scratchpad;
fe5389c8
SC		 5549 if (wait_for_ready)
5550 iterations = HPSA_BOARD_READY_ITERATIONS;
5551 else
5552 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 5553
fe5389c8
SC		 5554 for (i = 0; i < iterations; i++) {
5555 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
5556 if (wait_for_ready) {
5557 if (scratchpad == HPSA_FIRMWARE_READY)
5558 return 0;
5559 } else {
5560 if (scratchpad != HPSA_FIRMWARE_READY)
5561 return 0;
5562 }
2c4c8c8b
SC		 5563 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
5564 }
fe5389c8 5565 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 5566 return -ENODEV;
5567}
5568
6f039790
GKH		 5569static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
5570 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
5571 u64 *cfg_offset)
a51fd47f
SC		 5572{
5573 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
5574 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
5575 *cfg_base_addr &= (u32) 0x0000ffff;
5576 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
5577 if (*cfg_base_addr_index == -1) {
5578 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
5579 return -ENODEV;
5580 }
5581 return 0;
5582}
5583
6f039790 5584static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 5585{
01a02ffc
SC		 5586 u64 cfg_offset;
5587 u32 cfg_base_addr;
5588 u64 cfg_base_addr_index;
303932fd 5589 u32 trans_offset;
a51fd47f 5590 int rc;
77c4495c 5591
a51fd47f
SC		 5592 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
5593 &cfg_base_addr_index, &cfg_offset);
5594 if (rc)
5595 return rc;
77c4495c 5596 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 5597 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
77c4495c
SC		 5598 if (!h->cfgtable)
5599 return -ENOMEM;
580ada3c
SC		 5600 rc = write_driver_ver_to_cfgtable(h->cfgtable);
5601 if (rc)
5602 return rc;
77c4495c 5603 /* Find performant mode table. */
a51fd47f 5604 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 5605 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
5606 cfg_base_addr_index)+cfg_offset+trans_offset,
5607 sizeof(*h->transtable));
5608 if (!h->transtable)
5609 return -ENOMEM;
5610 return 0;
5611}
5612
6f039790 5613static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b
SC		 5614{
5615 h->max_commands = readl(&(h->cfgtable->MaxPerformantModeCommands));
72ceeaec
SC		 5616
5617 /* Limit commands in memory limited kdump scenario. */
5618 if (reset_devices && h->max_commands > 32)
5619 h->max_commands = 32;
5620
cba3d38b
SC		 5621 if (h->max_commands < 16) {
5622 dev_warn(&h->pdev->dev, "Controller reports "
5623 "max supported commands of %d, an obvious lie. "
5624 "Using 16. Ensure that firmware is up to date.\n",
5625 h->max_commands);
5626 h->max_commands = 16;
5627 }
5628}
5629
b93d7536
SC		 5630/* Interrogate the hardware for some limits:
5631 * max commands, max SG elements without chaining, and with chaining,
5632 * SG chain block size, etc.
5633 */
6f039790 5634static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 5635{
cba3d38b 5636 hpsa_get_max_perf_mode_cmds(h);
b93d7536
SC		 5637 h->nr_cmds = h->max_commands - 4; /* Allow room for some ioctls */
5638 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 5639 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
b93d7536
SC		 5640 /*
5641 * Limit in-command s/g elements to 32 save dma'able memory.
5642 * Howvever spec says if 0, use 31
5643 */
5644 h->max_cmd_sg_entries = 31;
5645 if (h->maxsgentries > 512) {
5646 h->max_cmd_sg_entries = 32;
5647 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries + 1;
5648 h->maxsgentries--; /* save one for chain pointer */
5649 } else {
5650 h->maxsgentries = 31; /* default to traditional values */
5651 h->chainsize = 0;
5652 }
75167d2c
SC		 5653
5654 /* Find out what task management functions are supported and cache */
5655 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 5656 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
5657 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
5658 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
5659 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
b93d7536
SC		 5660}
5661
76c46e49
SC		 5662static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
5663{
0fc9fd40 5664 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
76c46e49
SC		 5665 dev_warn(&h->pdev->dev, "not a valid CISS config table\n");
5666 return false;
5667 }
5668 return true;
5669}
5670
97a5e98c 5671static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 5672{
97a5e98c 5673 u32 driver_support;
f7c39101 5674
28e13446
SC		 5675#ifdef CONFIG_X86
5676 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
97a5e98c
SC		 5677 driver_support = readl(&(h->cfgtable->driver_support));
5678 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 5679#endif
28e13446
SC		 5680 driver_support |= ENABLE_UNIT_ATTN;
5681 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 5682}
5683
3d0eab67
SC		 5684/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
5685 * in a prefetch beyond physical memory.
5686 */
5687static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
5688{
5689 u32 dma_prefetch;
5690
5691 if (h->board_id != 0x3225103C)
5692 return;
5693 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
5694 dma_prefetch |= 0x8000;
5695 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
5696}
5697
76438d08
SC		 5698static void hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
5699{
5700 int i;
5701 u32 doorbell_value;
5702 unsigned long flags;
5703 /* wait until the clear_event_notify bit 6 is cleared by controller. */
5704 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
5705 spin_lock_irqsave(&h->lock, flags);
5706 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5707 spin_unlock_irqrestore(&h->lock, flags);
5708 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
5709 break;
5710 /* delay and try again */
5711 msleep(20);
5712 }
5713}
5714
6f039790 5715static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 5716{
5717 int i;
6eaf46fd
SC		 5718 u32 doorbell_value;
5719 unsigned long flags;
eb6b2ae9
SC		 5720
5721 /* under certain very rare conditions, this can take awhile.
5722 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
5723 * as we enter this code.)
5724 */
5725 for (i = 0; i < MAX_CONFIG_WAIT; i++) {
6eaf46fd
SC		 5726 spin_lock_irqsave(&h->lock, flags);
5727 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
5728 spin_unlock_irqrestore(&h->lock, flags);
382be668 5729 if (!(doorbell_value & CFGTBL_ChangeReq))
eb6b2ae9
SC		 5730 break;
5731 /* delay and try again */
60d3f5b0 5732 usleep_range(10000, 20000);
eb6b2ae9 5733 }
3f4336f3
SC		 5734}
5735
6f039790 5736static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 5737{
5738 u32 trans_support;
5739
5740 trans_support = readl(&(h->cfgtable->TransportSupport));
5741 if (!(trans_support & SIMPLE_MODE))
5742 return -ENOTSUPP;
5743
5744 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 5745
3f4336f3
SC		 5746 /* Update the field, and then ring the doorbell */
5747 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 5748 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3
SC		 5749 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
5750 hpsa_wait_for_mode_change_ack(h);
eb6b2ae9 5751 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 5752 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
5753 goto error;
960a30e7 5754 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 5755 return 0;
283b4a9b
SC		 5756error:
5757 dev_warn(&h->pdev->dev, "unable to get board into simple mode\n");
5758 return -ENODEV;
eb6b2ae9
SC		 5759}
5760
6f039790 5761static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 5762{
eb6b2ae9 5763 int prod_index, err;
edd16368 5764
e5c880d1
SC		 5765 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
5766 if (prod_index < 0)
5767 return -ENODEV;
5768 h->product_name = products[prod_index].product_name;
5769 h->access = *(products[prod_index].access);
edd16368 5770
e5a44df8
MG		 5771 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
5772 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
5773
55c06c71 5774 err = pci_enable_device(h->pdev);
edd16368 5775 if (err) {
55c06c71 5776 dev_warn(&h->pdev->dev, "unable to enable PCI device\n");
edd16368
SC		 5777 return err;
5778 }
5779
5cb460a6
SC		 5780 /* Enable bus mastering (pci_disable_device may disable this) */
5781 pci_set_master(h->pdev);
5782
f79cfec6 5783 err = pci_request_regions(h->pdev, HPSA);
edd16368 5784 if (err) {
55c06c71
SC		 5785 dev_err(&h->pdev->dev,
5786 "cannot obtain PCI resources, aborting\n");
edd16368
SC		 5787 return err;
5788 }
6b3f4c52 5789 hpsa_interrupt_mode(h);
12d2cd47 5790 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 5791 if (err)
edd16368 5792 goto err_out_free_res;
edd16368 5793 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9
SC		 5794 if (!h->vaddr) {
5795 err = -ENOMEM;
5796 goto err_out_free_res;
5797 }
fe5389c8 5798 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 5799 if (err)
edd16368 5800 goto err_out_free_res;
77c4495c
SC		 5801 err = hpsa_find_cfgtables(h);
5802 if (err)
edd16368 5803 goto err_out_free_res;
b93d7536 5804 hpsa_find_board_params(h);
edd16368 5805
76c46e49 5806 if (!hpsa_CISS_signature_present(h)) {
edd16368
SC		 5807 err = -ENODEV;
5808 goto err_out_free_res;
5809 }
97a5e98c 5810 hpsa_set_driver_support_bits(h);
3d0eab67 5811 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 5812 err = hpsa_enter_simple_mode(h);
5813 if (err)
edd16368 5814 goto err_out_free_res;
edd16368
SC		 5815 return 0;
5816
5817err_out_free_res:
204892e9
SC		 5818 if (h->transtable)
5819 iounmap(h->transtable);
5820 if (h->cfgtable)
5821 iounmap(h->cfgtable);
5822 if (h->vaddr)
5823 iounmap(h->vaddr);
f0bd0b68 5824 pci_disable_device(h->pdev);
55c06c71 5825 pci_release_regions(h->pdev);
edd16368
SC		 5826 return err;
5827}
5828
6f039790 5829static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 5830{
5831 int rc;
5832
5833#define HBA_INQUIRY_BYTE_COUNT 64
5834 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
5835 if (!h->hba_inquiry_data)
5836 return;
5837 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
5838 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
5839 if (rc != 0) {
5840 kfree(h->hba_inquiry_data);
5841 h->hba_inquiry_data = NULL;
5842 }
5843}
5844
6f039790 5845static int hpsa_init_reset_devices(struct pci_dev *pdev)
4c2a8c40 5846{
1df8552a 5847 int rc, i;
4c2a8c40
SC		 5848
5849 if (!reset_devices)
5850 return 0;
5851
1df8552a
SC		 5852 /* Reset the controller with a PCI power-cycle or via doorbell */
5853 rc = hpsa_kdump_hard_reset_controller(pdev);
4c2a8c40 5854
1df8552a
SC		 5855 /* -ENOTSUPP here means we cannot reset the controller
5856 * but it's already (and still) up and running in
18867659
SC		 5857 * "performant mode". Or, it might be 640x, which can't reset
5858 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a
SC		 5859 */
5860 if (rc == -ENOTSUPP)
64670ac8 5861 return rc; /* just try to do the kdump anyhow. */
1df8552a
SC		 5862 if (rc)
5863 return -ENODEV;
4c2a8c40
SC		 5864
5865 /* Now try to get the controller to respond to a no-op */
2b870cb3 5866 dev_warn(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 5867 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
5868 if (hpsa_noop(pdev) == 0)
5869 break;
5870 else
5871 dev_warn(&pdev->dev, "no-op failed%s\n",
5872 (i < 11 ? "; re-trying" : ""));
5873 }
5874 return 0;
5875}
5876
6f039790 5877static int hpsa_allocate_cmd_pool(struct ctlr_info *h)
2e9d1b36
SC		 5878{
5879 h->cmd_pool_bits = kzalloc(
5880 DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
5881 sizeof(unsigned long), GFP_KERNEL);
5882 h->cmd_pool = pci_alloc_consistent(h->pdev,
5883 h->nr_cmds * sizeof(*h->cmd_pool),
5884 &(h->cmd_pool_dhandle));
5885 h->errinfo_pool = pci_alloc_consistent(h->pdev,
5886 h->nr_cmds * sizeof(*h->errinfo_pool),
5887 &(h->errinfo_pool_dhandle));
5888 if ((h->cmd_pool_bits == NULL)
5889 || (h->cmd_pool == NULL)
5890 || (h->errinfo_pool == NULL)) {
5891 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
5892 return -ENOMEM;
5893 }
5894 return 0;
5895}
5896
5897static void hpsa_free_cmd_pool(struct ctlr_info *h)
5898{
5899 kfree(h->cmd_pool_bits);
5900 if (h->cmd_pool)
5901 pci_free_consistent(h->pdev,
5902 h->nr_cmds * sizeof(struct CommandList),
5903 h->cmd_pool, h->cmd_pool_dhandle);
aca9012a
SC		 5904 if (h->ioaccel2_cmd_pool)
5905 pci_free_consistent(h->pdev,
5906 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
5907 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
2e9d1b36
SC		 5908 if (h->errinfo_pool)
5909 pci_free_consistent(h->pdev,
5910 h->nr_cmds * sizeof(struct ErrorInfo),
5911 h->errinfo_pool,
5912 h->errinfo_pool_dhandle);
e1f7de0c
MG		 5913 if (h->ioaccel_cmd_pool)
5914 pci_free_consistent(h->pdev,
5915 h->nr_cmds * sizeof(struct io_accel1_cmd),
5916 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
2e9d1b36
SC		 5917}
5918
0ae01a32
SC		 5919static int hpsa_request_irq(struct ctlr_info *h,
5920 irqreturn_t (*msixhandler)(int, void *),
5921 irqreturn_t (*intxhandler)(int, void *))
5922{
254f796b 5923 int rc, i;
0ae01a32 5924
254f796b
MG		 5925 /*
5926 * initialize h->q[x] = x so that interrupt handlers know which
5927 * queue to process.
5928 */
5929 for (i = 0; i < MAX_REPLY_QUEUES; i++)
5930 h->q[i] = (u8) i;
5931
eee0f03a 5932 if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
254f796b 5933 /* If performant mode and MSI-X, use multiple reply queues */
eee0f03a 5934 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 5935 rc = request_irq(h->intr[i], msixhandler,
5936 0, h->devname,
5937 &h->q[i]);
5938 } else {
5939 /* Use single reply pool */
eee0f03a 5940 if (h->msix_vector > 0 || h->msi_vector) {
254f796b
MG		 5941 rc = request_irq(h->intr[h->intr_mode],
5942 msixhandler, 0, h->devname,
5943 &h->q[h->intr_mode]);
5944 } else {
5945 rc = request_irq(h->intr[h->intr_mode],
5946 intxhandler, IRQF_SHARED, h->devname,
5947 &h->q[h->intr_mode]);
5948 }
5949 }
0ae01a32
SC		 5950 if (rc) {
5951 dev_err(&h->pdev->dev, "unable to get irq %d for %s\n",
5952 h->intr[h->intr_mode], h->devname);
5953 return -ENODEV;
5954 }
5955 return 0;
5956}
5957
6f039790 5958static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8
SC		 5959{
5960 if (hpsa_send_host_reset(h, RAID_CTLR_LUNID,
5961 HPSA_RESET_TYPE_CONTROLLER)) {
5962 dev_warn(&h->pdev->dev, "Resetting array controller failed.\n");
5963 return -EIO;
5964 }
5965
5966 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
5967 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY)) {
5968 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
5969 return -1;
5970 }
5971
5972 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
5973 if (hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY)) {
5974 dev_warn(&h->pdev->dev, "Board failed to become ready "
5975 "after soft reset.\n");
5976 return -1;
5977 }
5978
5979 return 0;
5980}
5981
254f796b
MG		 5982static void free_irqs(struct ctlr_info *h)
5983{
5984 int i;
5985
5986 if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
5987 /* Single reply queue, only one irq to free */
5988 i = h->intr_mode;
5989 free_irq(h->intr[i], &h->q[i]);
5990 return;
5991 }
5992
eee0f03a 5993 for (i = 0; i < h->msix_vector; i++)
254f796b
MG		 5994 free_irq(h->intr[i], &h->q[i]);
5995}
5996
0097f0f4 5997static void hpsa_free_irqs_and_disable_msix(struct ctlr_info *h)
64670ac8 5998{
254f796b 5999 free_irqs(h);
64670ac8 6000#ifdef CONFIG_PCI_MSI
0097f0f4
SC		 6001 if (h->msix_vector) {
6002 if (h->pdev->msix_enabled)
6003 pci_disable_msix(h->pdev);
6004 } else if (h->msi_vector) {
6005 if (h->pdev->msi_enabled)
6006 pci_disable_msi(h->pdev);
6007 }
64670ac8 6008#endif /* CONFIG_PCI_MSI */
0097f0f4
SC		 6009}
6010
6011static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
6012{
6013 hpsa_free_irqs_and_disable_msix(h);
64670ac8
SC		 6014 hpsa_free_sg_chain_blocks(h);
6015 hpsa_free_cmd_pool(h);
e1f7de0c 6016 kfree(h->ioaccel1_blockFetchTable);
64670ac8
SC		 6017 kfree(h->blockFetchTable);
6018 pci_free_consistent(h->pdev, h->reply_pool_size,
6019 h->reply_pool, h->reply_pool_dhandle);
6020 if (h->vaddr)
6021 iounmap(h->vaddr);
6022 if (h->transtable)
6023 iounmap(h->transtable);
6024 if (h->cfgtable)
6025 iounmap(h->cfgtable);
6026 pci_release_regions(h->pdev);
6027 kfree(h);
6028}
6029
a0c12413
SC		 6030/* Called when controller lockup detected. */
6031static void fail_all_cmds_on_list(struct ctlr_info *h, struct list_head *list)
6032{
6033 struct CommandList *c = NULL;
6034
6035 assert_spin_locked(&h->lock);
6036 /* Mark all outstanding commands as failed and complete them. */
6037 while (!list_empty(list)) {
6038 c = list_entry(list->next, struct CommandList, list);
6039 c->err_info->CommandStatus = CMD_HARDWARE_ERR;
5a3d16f5 6040 finish_cmd(c);
a0c12413
SC		 6041 }
6042}
6043
6044static void controller_lockup_detected(struct ctlr_info *h)
6045{
6046 unsigned long flags;
6047
a0c12413
SC		 6048 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6049 spin_lock_irqsave(&h->lock, flags);
6050 h->lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
6051 spin_unlock_irqrestore(&h->lock, flags);
6052 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x\n",
6053 h->lockup_detected);
6054 pci_disable_device(h->pdev);
6055 spin_lock_irqsave(&h->lock, flags);
6056 fail_all_cmds_on_list(h, &h->cmpQ);
6057 fail_all_cmds_on_list(h, &h->reqQ);
6058 spin_unlock_irqrestore(&h->lock, flags);
6059}
6060
a0c12413
SC		 6061static void detect_controller_lockup(struct ctlr_info *h)
6062{
6063 u64 now;
6064 u32 heartbeat;
6065 unsigned long flags;
6066
a0c12413
SC		 6067 now = get_jiffies_64();
6068 /* If we've received an interrupt recently, we're ok. */
6069 if (time_after64(h->last_intr_timestamp +
e85c5974 6070 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6071 return;
6072
6073 /*
6074 * If we've already checked the heartbeat recently, we're ok.
6075 * This could happen if someone sends us a signal. We
6076 * otherwise don't care about signals in this thread.
6077 */
6078 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 6079 (h->heartbeat_sample_interval), now))
a0c12413
SC		 6080 return;
6081
6082 /* If heartbeat has not changed since we last looked, we're not ok. */
6083 spin_lock_irqsave(&h->lock, flags);
6084 heartbeat = readl(&h->cfgtable->HeartBeat);
6085 spin_unlock_irqrestore(&h->lock, flags);
6086 if (h->last_heartbeat == heartbeat) {
6087 controller_lockup_detected(h);
6088 return;
6089 }
6090
6091 /* We're ok. */
6092 h->last_heartbeat = heartbeat;
6093 h->last_heartbeat_timestamp = now;
6094}
6095
76438d08
SC		 6096static int hpsa_kickoff_rescan(struct ctlr_info *h)
6097{
6098 int i;
6099 char *event_type;
6100
6101 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 6102 if ((h->transMethod & (CFGTBL_Trans_io_accel1
6103 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 6104 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
6105 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
6106
6107 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
6108 event_type = "state change";
6109 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
6110 event_type = "configuration change";
6111 /* Stop sending new RAID offload reqs via the IO accelerator */
6112 scsi_block_requests(h->scsi_host);
6113 for (i = 0; i < h->ndevices; i++)
6114 h->dev[i]->offload_enabled = 0;
6115 hpsa_drain_commands(h);
6116 /* Set 'accelerator path config change' bit */
6117 dev_warn(&h->pdev->dev,
6118 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
6119 h->events, event_type);
6120 writel(h->events, &(h->cfgtable->clear_event_notify));
6121 /* Set the "clear event notify field update" bit 6 */
6122 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6123 /* Wait until ctlr clears 'clear event notify field', bit 6 */
6124 hpsa_wait_for_clear_event_notify_ack(h);
6125 scsi_unblock_requests(h->scsi_host);
6126 } else {
6127 /* Acknowledge controller notification events. */
6128 writel(h->events, &(h->cfgtable->clear_event_notify));
6129 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
6130 hpsa_wait_for_clear_event_notify_ack(h);
6131#if 0
6132 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6133 hpsa_wait_for_mode_change_ack(h);
6134#endif
6135 }
6136
6137 /* Something in the device list may have changed to trigger
6138 * the event, so do a rescan.
6139 */
6140 hpsa_scan_start(h->scsi_host);
6141 /* release reference taken on scsi host in check_controller_events */
6142 scsi_host_put(h->scsi_host);
6143 return 0;
6144}
6145
6146/* Check a register on the controller to see if there are configuration
6147 * changes (added/changed/removed logical drives, etc.) which mean that
6148 * we should rescan the controller for devices. If so, add the controller
6149 * to the list of controllers needing to be rescanned, and gets a
6150 * reference to the associated scsi_host.
6151 */
6152static void hpsa_ctlr_needs_rescan(struct ctlr_info *h)
6153{
6154 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
6155 return;
6156
6157 h->events = readl(&(h->cfgtable->event_notify));
6158 if (!h->events)
6159 return;
6160
6161 /*
6162 * Take a reference on scsi host for the duration of the scan
6163 * Release in hpsa_kickoff_rescan(). No lock needed for scan_list
6164 * as only a single thread accesses this list.
6165 */
6166 scsi_host_get(h->scsi_host);
6167 hpsa_kickoff_rescan(h);
6168}
6169
8a98db73 6170static void hpsa_monitor_ctlr_worker(struct work_struct *work)
a0c12413
SC		 6171{
6172 unsigned long flags;
8a98db73
SC		 6173 struct ctlr_info *h = container_of(to_delayed_work(work),
6174 struct ctlr_info, monitor_ctlr_work);
6175 detect_controller_lockup(h);
6176 if (h->lockup_detected)
6177 return;
76438d08 6178 hpsa_ctlr_needs_rescan(h);
8a98db73
SC		 6179 spin_lock_irqsave(&h->lock, flags);
6180 if (h->remove_in_progress) {
6181 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6182 return;
6183 }
8a98db73
SC		 6184 schedule_delayed_work(&h->monitor_ctlr_work,
6185 h->heartbeat_sample_interval);
6186 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 6187}
6188
6f039790 6189static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 6190{
4c2a8c40 6191 int dac, rc;
edd16368 6192 struct ctlr_info *h;
64670ac8
SC		 6193 int try_soft_reset = 0;
6194 unsigned long flags;
edd16368
SC		 6195
6196 if (number_of_controllers == 0)
6197 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 6198
4c2a8c40 6199 rc = hpsa_init_reset_devices(pdev);
64670ac8
SC		 6200 if (rc) {
6201 if (rc != -ENOTSUPP)
6202 return rc;
6203 /* If the reset fails in a particular way (it has no way to do
6204 * a proper hard reset, so returns -ENOTSUPP) we can try to do
6205 * a soft reset once we get the controller configured up to the
6206 * point that it can accept a command.
6207 */
6208 try_soft_reset = 1;
6209 rc = 0;
6210 }
6211
6212reinit_after_soft_reset:
edd16368 6213
303932fd
DB		 6214 /* Command structures must be aligned on a 32-byte boundary because
6215 * the 5 lower bits of the address are used by the hardware. and by
6216 * the driver. See comments in hpsa.h for more info.
6217 */
283b4a9b 6218#define COMMANDLIST_ALIGNMENT 128
303932fd 6219 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
edd16368
SC		 6220 h = kzalloc(sizeof(*h), GFP_KERNEL);
6221 if (!h)
ecd9aad4 6222 return -ENOMEM;
edd16368 6223
55c06c71 6224 h->pdev = pdev;
a9a3a273 6225 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9e0fc764
SC		 6226 INIT_LIST_HEAD(&h->cmpQ);
6227 INIT_LIST_HEAD(&h->reqQ);
6eaf46fd
SC		 6228 spin_lock_init(&h->lock);
6229 spin_lock_init(&h->scan_lock);
0390f0c0 6230 spin_lock_init(&h->passthru_count_lock);
55c06c71 6231 rc = hpsa_pci_init(h);
ecd9aad4 6232 if (rc != 0)
edd16368
SC		 6233 goto clean1;
6234
f79cfec6 6235 sprintf(h->devname, HPSA "%d", number_of_controllers);
edd16368
SC		 6236 h->ctlr = number_of_controllers;
6237 number_of_controllers++;
edd16368
SC		 6238
6239 /* configure PCI DMA stuff */
ecd9aad4
SC		 6240 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
6241 if (rc == 0) {
edd16368 6242 dac = 1;
ecd9aad4
SC		 6243 } else {
6244 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
6245 if (rc == 0) {
6246 dac = 0;
6247 } else {
6248 dev_err(&pdev->dev, "no suitable DMA available\n");
6249 goto clean1;
6250 }
edd16368
SC		 6251 }
6252
6253 /* make sure the board interrupts are off */
6254 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 6255
0ae01a32 6256 if (hpsa_request_irq(h, do_hpsa_intr_msi, do_hpsa_intr_intx))
edd16368 6257 goto clean2;
303932fd
DB		 6258 dev_info(&pdev->dev, "%s: <0x%x> at IRQ %d%s using DAC\n",
6259 h->devname, pdev->device,
a9a3a273 6260 h->intr[h->intr_mode], dac ? "" : " not");
2e9d1b36 6261 if (hpsa_allocate_cmd_pool(h))
edd16368 6262 goto clean4;
33a2ffce
SC		 6263 if (hpsa_allocate_sg_chain_blocks(h))
6264 goto clean4;
a08a8471
SC		 6265 init_waitqueue_head(&h->scan_wait_queue);
6266 h->scan_finished = 1; /* no scan currently in progress */
edd16368
SC		 6267
6268 pci_set_drvdata(pdev, h);
9a41338e
SC		 6269 h->ndevices = 0;
6270 h->scsi_host = NULL;
6271 spin_lock_init(&h->devlock);
64670ac8
SC		 6272 hpsa_put_ctlr_into_performant_mode(h);
6273
6274 /* At this point, the controller is ready to take commands.
6275 * Now, if reset_devices and the hard reset didn't work, try
6276 * the soft reset and see if that works.
6277 */
6278 if (try_soft_reset) {
6279
6280 /* This is kind of gross. We may or may not get a completion
6281 * from the soft reset command, and if we do, then the value
6282 * from the fifo may or may not be valid. So, we wait 10 secs
6283 * after the reset throwing away any completions we get during
6284 * that time. Unregister the interrupt handler and register
6285 * fake ones to scoop up any residual completions.
6286 */
6287 spin_lock_irqsave(&h->lock, flags);
6288 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6289 spin_unlock_irqrestore(&h->lock, flags);
254f796b 6290 free_irqs(h);
64670ac8
SC		 6291 rc = hpsa_request_irq(h, hpsa_msix_discard_completions,
6292 hpsa_intx_discard_completions);
6293 if (rc) {
6294 dev_warn(&h->pdev->dev, "Failed to request_irq after "
6295 "soft reset.\n");
6296 goto clean4;
6297 }
6298
6299 rc = hpsa_kdump_soft_reset(h);
6300 if (rc)
6301 /* Neither hard nor soft reset worked, we're hosed. */
6302 goto clean4;
6303
6304 dev_info(&h->pdev->dev, "Board READY.\n");
6305 dev_info(&h->pdev->dev,
6306 "Waiting for stale completions to drain.\n");
6307 h->access.set_intr_mask(h, HPSA_INTR_ON);
6308 msleep(10000);
6309 h->access.set_intr_mask(h, HPSA_INTR_OFF);
6310
6311 rc = controller_reset_failed(h->cfgtable);
6312 if (rc)
6313 dev_info(&h->pdev->dev,
6314 "Soft reset appears to have failed.\n");
6315
6316 /* since the controller's reset, we have to go back and re-init
6317 * everything. Easiest to just forget what we've done and do it
6318 * all over again.
6319 */
6320 hpsa_undo_allocations_after_kdump_soft_reset(h);
6321 try_soft_reset = 0;
6322 if (rc)
6323 /* don't go to clean4, we already unallocated */
6324 return -ENODEV;
6325
6326 goto reinit_after_soft_reset;
6327 }
edd16368
SC		 6328
6329 /* Turn the interrupts on so we can service requests */
6330 h->access.set_intr_mask(h, HPSA_INTR_ON);
6331
339b2b14 6332 hpsa_hba_inquiry(h);
edd16368 6333 hpsa_register_scsi(h); /* hook ourselves into SCSI subsystem */
8a98db73
SC		 6334
6335 /* Monitor the controller for firmware lockups */
6336 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
6337 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
6338 schedule_delayed_work(&h->monitor_ctlr_work,
6339 h->heartbeat_sample_interval);
88bf6d62 6340 return 0;
edd16368
SC		 6341
6342clean4:
33a2ffce 6343 hpsa_free_sg_chain_blocks(h);
2e9d1b36 6344 hpsa_free_cmd_pool(h);
254f796b 6345 free_irqs(h);
edd16368
SC		 6346clean2:
6347clean1:
edd16368 6348 kfree(h);
ecd9aad4 6349 return rc;
edd16368
SC		 6350}
6351
6352static void hpsa_flush_cache(struct ctlr_info *h)
6353{
6354 char *flush_buf;
6355 struct CommandList *c;
702890e3
SC		 6356 unsigned long flags;
6357
6358 /* Don't bother trying to flush the cache if locked up */
6359 spin_lock_irqsave(&h->lock, flags);
6360 if (unlikely(h->lockup_detected)) {
6361 spin_unlock_irqrestore(&h->lock, flags);
6362 return;
6363 }
6364 spin_unlock_irqrestore(&h->lock, flags);
edd16368
SC		 6365
6366 flush_buf = kzalloc(4, GFP_KERNEL);
6367 if (!flush_buf)
6368 return;
6369
6370 c = cmd_special_alloc(h);
6371 if (!c) {
6372 dev_warn(&h->pdev->dev, "cmd_special_alloc returned NULL!\n");
6373 goto out_of_memory;
6374 }
a2dac136
SC		 6375 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
6376 RAID_CTLR_LUNID, TYPE_CMD)) {
6377 goto out;
6378 }
edd16368
SC		 6379 hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_TODEVICE);
6380 if (c->err_info->CommandStatus != 0)
a2dac136 6381out:
edd16368
SC		 6382 dev_warn(&h->pdev->dev,
6383 "error flushing cache on controller\n");
6384 cmd_special_free(h, c);
6385out_of_memory:
6386 kfree(flush_buf);
6387}
6388
6389static void hpsa_shutdown(struct pci_dev *pdev)
6390{
6391 struct ctlr_info *h;
6392
6393 h = pci_get_drvdata(pdev);
6394 /* Turn board interrupts off and send the flush cache command
6395 * sendcmd will turn off interrupt, and send the flush...
6396 * To write all data in the battery backed cache to disks
6397 */
6398 hpsa_flush_cache(h);
6399 h->access.set_intr_mask(h, HPSA_INTR_OFF);
0097f0f4 6400 hpsa_free_irqs_and_disable_msix(h);
edd16368
SC		 6401}
6402
6f039790 6403static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 6404{
6405 int i;
6406
6407 for (i = 0; i < h->ndevices; i++)
6408 kfree(h->dev[i]);
6409}
6410
6f039790 6411static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 6412{
6413 struct ctlr_info *h;
8a98db73 6414 unsigned long flags;
edd16368
SC		 6415
6416 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 6417 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 6418 return;
6419 }
6420 h = pci_get_drvdata(pdev);
8a98db73
SC		 6421
6422 /* Get rid of any controller monitoring work items */
6423 spin_lock_irqsave(&h->lock, flags);
6424 h->remove_in_progress = 1;
6425 cancel_delayed_work(&h->monitor_ctlr_work);
6426 spin_unlock_irqrestore(&h->lock, flags);
6427
edd16368
SC		 6428 hpsa_unregister_scsi(h); /* unhook from SCSI subsystem */
6429 hpsa_shutdown(pdev);
6430 iounmap(h->vaddr);
204892e9
SC		 6431 iounmap(h->transtable);
6432 iounmap(h->cfgtable);
55e14e76 6433 hpsa_free_device_info(h);
33a2ffce 6434 hpsa_free_sg_chain_blocks(h);
edd16368
SC		 6435 pci_free_consistent(h->pdev,
6436 h->nr_cmds * sizeof(struct CommandList),
6437 h->cmd_pool, h->cmd_pool_dhandle);
6438 pci_free_consistent(h->pdev,
6439 h->nr_cmds * sizeof(struct ErrorInfo),
6440 h->errinfo_pool, h->errinfo_pool_dhandle);
303932fd
DB		 6441 pci_free_consistent(h->pdev, h->reply_pool_size,
6442 h->reply_pool, h->reply_pool_dhandle);
edd16368 6443 kfree(h->cmd_pool_bits);
303932fd 6444 kfree(h->blockFetchTable);
e1f7de0c 6445 kfree(h->ioaccel1_blockFetchTable);
aca9012a 6446 kfree(h->ioaccel2_blockFetchTable);
339b2b14 6447 kfree(h->hba_inquiry_data);
f0bd0b68 6448 pci_disable_device(pdev);
edd16368 6449 pci_release_regions(pdev);
edd16368
SC		 6450 kfree(h);
6451}
6452
6453static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
6454 __attribute__((unused)) pm_message_t state)
6455{
6456 return -ENOSYS;
6457}
6458
6459static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
6460{
6461 return -ENOSYS;
6462}
6463
6464static struct pci_driver hpsa_pci_driver = {
f79cfec6 6465 .name = HPSA,
edd16368 6466 .probe = hpsa_init_one,
6f039790 6467 .remove = hpsa_remove_one,
edd16368
SC		 6468 .id_table = hpsa_pci_device_id, /* id_table */
6469 .shutdown = hpsa_shutdown,
6470 .suspend = hpsa_suspend,
6471 .resume = hpsa_resume,
6472};
6473
303932fd
DB		 6474/* Fill in bucket_map[], given nsgs (the max number of
6475 * scatter gather elements supported) and bucket[],
6476 * which is an array of 8 integers. The bucket[] array
6477 * contains 8 different DMA transfer sizes (in 16
6478 * byte increments) which the controller uses to fetch
6479 * commands. This function fills in bucket_map[], which
6480 * maps a given number of scatter gather elements to one of
6481 * the 8 DMA transfer sizes. The point of it is to allow the
6482 * controller to only do as much DMA as needed to fetch the
6483 * command, with the DMA transfer size encoded in the lower
6484 * bits of the command address.
6485 */
6486static void calc_bucket_map(int bucket[], int num_buckets,
e1f7de0c 6487 int nsgs, int min_blocks, int *bucket_map)
303932fd
DB		 6488{
6489 int i, j, b, size;
6490
303932fd
DB		 6491 /* Note, bucket_map must have nsgs+1 entries. */
6492 for (i = 0; i <= nsgs; i++) {
6493 /* Compute size of a command with i SG entries */
e1f7de0c 6494 size = i + min_blocks;
303932fd
DB		 6495 b = num_buckets; /* Assume the biggest bucket */
6496 /* Find the bucket that is just big enough */
e1f7de0c 6497 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 6498 if (bucket[j] >= size) {
6499 b = j;
6500 break;
6501 }
6502 }
6503 /* for a command with i SG entries, use bucket b. */
6504 bucket_map[i] = b;
6505 }
6506}
6507
e1f7de0c 6508static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 6509{
6c311b57
SC		 6510 int i;
6511 unsigned long register_value;
e1f7de0c
MG		 6512 unsigned long transMethod = CFGTBL_Trans_Performant |
6513 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 6514 CFGTBL_Trans_enable_directed_msix |
6515 (trans_support & (CFGTBL_Trans_io_accel1 |
6516 CFGTBL_Trans_io_accel2));
e1f7de0c 6517 struct access_method access = SA5_performant_access;
def342bd
SC		 6518
6519 /* This is a bit complicated. There are 8 registers on
6520 * the controller which we write to to tell it 8 different
6521 * sizes of commands which there may be. It's a way of
6522 * reducing the DMA done to fetch each command. Encoded into
6523 * each command's tag are 3 bits which communicate to the controller
6524 * which of the eight sizes that command fits within. The size of
6525 * each command depends on how many scatter gather entries there are.
6526 * Each SG entry requires 16 bytes. The eight registers are programmed
6527 * with the number of 16-byte blocks a command of that size requires.
6528 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 6529 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 6530 * blocks. Note, this only extends to the SG entries contained
6531 * within the command block, and does not extend to chained blocks
6532 * of SG elements. bft[] contains the eight values we write to
6533 * the registers. They are not evenly distributed, but have more
6534 * sizes for small commands, and fewer sizes for larger commands.
6535 */
d66ae08b 6536 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 6537#define MIN_IOACCEL2_BFT_ENTRY 5
6538#define HPSA_IOACCEL2_HEADER_SZ 4
6539 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
6540 13, 14, 15, 16, 17, 18, 19,
6541 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
6542 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
6543 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
6544 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
6545 16 * MIN_IOACCEL2_BFT_ENTRY);
6546 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 6547 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 6548 /* 5 = 1 s/g entry or 4k
6549 * 6 = 2 s/g entry or 8k
6550 * 8 = 4 s/g entry or 16k
6551 * 10 = 6 s/g entry or 24k
6552 */
303932fd 6553
303932fd
DB		 6554 /* Controller spec: zero out this buffer. */
6555 memset(h->reply_pool, 0, h->reply_pool_size);
303932fd 6556
d66ae08b
SC		 6557 bft[7] = SG_ENTRIES_IN_CMD + 4;
6558 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 6559 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 6560 for (i = 0; i < 8; i++)
6561 writel(bft[i], &h->transtable->BlockFetch[i]);
6562
6563 /* size of controller ring buffer */
6564 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 6565 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 6566 writel(0, &h->transtable->RepQCtrAddrLow32);
6567 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 6568
6569 for (i = 0; i < h->nreply_queues; i++) {
6570 writel(0, &h->transtable->RepQAddr[i].upper);
6571 writel(h->reply_pool_dhandle +
6572 (h->max_commands * sizeof(u64) * i),
6573 &h->transtable->RepQAddr[i].lower);
6574 }
6575
b9af4937 6576 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 6577 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
6578 /*
6579 * enable outbound interrupt coalescing in accelerator mode;
6580 */
6581 if (trans_support & CFGTBL_Trans_io_accel1) {
6582 access = SA5_ioaccel_mode1_access;
6583 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
6584 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
c349775e
ST		 6585 } else {
6586 if (trans_support & CFGTBL_Trans_io_accel2) {
6587 access = SA5_ioaccel_mode2_access;
6588 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
6589 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
6590 }
e1f7de0c 6591 }
303932fd 6592 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
3f4336f3 6593 hpsa_wait_for_mode_change_ack(h);
303932fd
DB		 6594 register_value = readl(&(h->cfgtable->TransportActive));
6595 if (!(register_value & CFGTBL_Trans_Performant)) {
6596 dev_warn(&h->pdev->dev, "unable to get board into"
6597 " performant mode\n");
6598 return;
6599 }
960a30e7 6600 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 6601 h->access = access;
6602 h->transMethod = transMethod;
6603
b9af4937
SC		 6604 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
6605 (trans_support & CFGTBL_Trans_io_accel2)))
e1f7de0c
MG		 6606 return;
6607
b9af4937
SC		 6608 if (trans_support & CFGTBL_Trans_io_accel1) {
6609 /* Set up I/O accelerator mode */
6610 for (i = 0; i < h->nreply_queues; i++) {
6611 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
6612 h->reply_queue[i].current_entry =
6613 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
6614 }
6615 bft[7] = h->ioaccel_maxsg + 8;
6616 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
6617 h->ioaccel1_blockFetchTable);
e1f7de0c 6618
b9af4937
SC		 6619 /* initialize all reply queue entries to unused */
6620 memset(h->reply_pool, (u8) IOACCEL_MODE1_REPLY_UNUSED,
6621 h->reply_pool_size);
e1f7de0c 6622
b9af4937
SC		 6623 /* set all the constant fields in the accelerator command
6624 * frames once at init time to save CPU cycles later.
6625 */
6626 for (i = 0; i < h->nr_cmds; i++) {
6627 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
6628
6629 cp->function = IOACCEL1_FUNCTION_SCSIIO;
6630 cp->err_info = (u32) (h->errinfo_pool_dhandle +
6631 (i * sizeof(struct ErrorInfo)));
6632 cp->err_info_len = sizeof(struct ErrorInfo);
6633 cp->sgl_offset = IOACCEL1_SGLOFFSET;
6634 cp->host_context_flags = IOACCEL1_HCFLAGS_CISS_FORMAT;
6635 cp->timeout_sec = 0;
6636 cp->ReplyQueue = 0;
6637 cp->Tag.lower = (i << DIRECT_LOOKUP_SHIFT) |
6638 DIRECT_LOOKUP_BIT;
6639 cp->Tag.upper = 0;
6640 cp->host_addr.lower =
6641 (u32) (h->ioaccel_cmd_pool_dhandle +
6642 (i * sizeof(struct io_accel1_cmd)));
6643 cp->host_addr.upper = 0;
6644 }
6645 } else if (trans_support & CFGTBL_Trans_io_accel2) {
6646 u64 cfg_offset, cfg_base_addr_index;
6647 u32 bft2_offset, cfg_base_addr;
6648 int rc;
6649
6650 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
6651 &cfg_base_addr_index, &cfg_offset);
6652 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
6653 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
6654 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
6655 4, h->ioaccel2_blockFetchTable);
6656 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
6657 BUILD_BUG_ON(offsetof(struct CfgTable,
6658 io_accel_request_size_offset) != 0xb8);
6659 h->ioaccel2_bft2_regs =
6660 remap_pci_mem(pci_resource_start(h->pdev,
6661 cfg_base_addr_index) +
6662 cfg_offset + bft2_offset,
6663 ARRAY_SIZE(bft2) *
6664 sizeof(*h->ioaccel2_bft2_regs));
6665 for (i = 0; i < ARRAY_SIZE(bft2); i++)
6666 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 6667 }
b9af4937
SC		 6668 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
6669 hpsa_wait_for_mode_change_ack(h);
e1f7de0c
MG		 6670}
6671
6672static int hpsa_alloc_ioaccel_cmd_and_bft(struct ctlr_info *h)
6673{
283b4a9b
SC		 6674 h->ioaccel_maxsg =
6675 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
6676 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
6677 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
6678
e1f7de0c
MG		 6679 /* Command structures must be aligned on a 128-byte boundary
6680 * because the 7 lower bits of the address are used by the
6681 * hardware.
6682 */
6683#define IOACCEL1_COMMANDLIST_ALIGNMENT 128
6684 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
6685 IOACCEL1_COMMANDLIST_ALIGNMENT);
6686 h->ioaccel_cmd_pool =
6687 pci_alloc_consistent(h->pdev,
6688 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
6689 &(h->ioaccel_cmd_pool_dhandle));
6690
6691 h->ioaccel1_blockFetchTable =
283b4a9b 6692 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 6693 sizeof(u32)), GFP_KERNEL);
6694
6695 if ((h->ioaccel_cmd_pool == NULL) ||
6696 (h->ioaccel1_blockFetchTable == NULL))
6697 goto clean_up;
6698
6699 memset(h->ioaccel_cmd_pool, 0,
6700 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
6701 return 0;
6702
6703clean_up:
6704 if (h->ioaccel_cmd_pool)
6705 pci_free_consistent(h->pdev,
6706 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
6707 h->ioaccel_cmd_pool, h->ioaccel_cmd_pool_dhandle);
6708 kfree(h->ioaccel1_blockFetchTable);
6709 return 1;
6c311b57
SC		 6710}
6711
aca9012a
SC		 6712static int ioaccel2_alloc_cmds_and_bft(struct ctlr_info *h)
6713{
6714 /* Allocate ioaccel2 mode command blocks and block fetch table */
6715
6716 h->ioaccel_maxsg =
6717 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
6718 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
6719 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
6720
6721#define IOACCEL2_COMMANDLIST_ALIGNMENT 128
6722 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
6723 IOACCEL2_COMMANDLIST_ALIGNMENT);
6724 h->ioaccel2_cmd_pool =
6725 pci_alloc_consistent(h->pdev,
6726 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6727 &(h->ioaccel2_cmd_pool_dhandle));
6728
6729 h->ioaccel2_blockFetchTable =
6730 kmalloc(((h->ioaccel_maxsg + 1) *
6731 sizeof(u32)), GFP_KERNEL);
6732
6733 if ((h->ioaccel2_cmd_pool == NULL) ||
6734 (h->ioaccel2_blockFetchTable == NULL))
6735 goto clean_up;
6736
6737 memset(h->ioaccel2_cmd_pool, 0,
6738 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
6739 return 0;
6740
6741clean_up:
6742 if (h->ioaccel2_cmd_pool)
6743 pci_free_consistent(h->pdev,
6744 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
6745 h->ioaccel2_cmd_pool, h->ioaccel2_cmd_pool_dhandle);
6746 kfree(h->ioaccel2_blockFetchTable);
6747 return 1;
6748}
6749
6f039790 6750static void hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 6751{
6752 u32 trans_support;
e1f7de0c
MG		 6753 unsigned long transMethod = CFGTBL_Trans_Performant |
6754 CFGTBL_Trans_use_short_tags;
254f796b 6755 int i;
6c311b57 6756
02ec19c8
SC		 6757 if (hpsa_simple_mode)
6758 return;
6759
e1f7de0c
MG		 6760 /* Check for I/O accelerator mode support */
6761 if (trans_support & CFGTBL_Trans_io_accel1) {
6762 transMethod |= CFGTBL_Trans_io_accel1 |
6763 CFGTBL_Trans_enable_directed_msix;
6764 if (hpsa_alloc_ioaccel_cmd_and_bft(h))
6765 goto clean_up;
aca9012a
SC		 6766 } else {
6767 if (trans_support & CFGTBL_Trans_io_accel2) {
6768 transMethod |= CFGTBL_Trans_io_accel2 |
6769 CFGTBL_Trans_enable_directed_msix;
6770 if (ioaccel2_alloc_cmds_and_bft(h))
6771 goto clean_up;
6772 }
e1f7de0c
MG		 6773 }
6774
6775 /* TODO, check that this next line h->nreply_queues is correct */
6c311b57
SC		 6776 trans_support = readl(&(h->cfgtable->TransportSupport));
6777 if (!(trans_support & PERFORMANT_MODE))
6778 return;
6779
eee0f03a 6780 h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
cba3d38b 6781 hpsa_get_max_perf_mode_cmds(h);
6c311b57 6782 /* Performant mode ring buffer and supporting data structures */
254f796b 6783 h->reply_pool_size = h->max_commands * sizeof(u64) * h->nreply_queues;
6c311b57
SC		 6784 h->reply_pool = pci_alloc_consistent(h->pdev, h->reply_pool_size,
6785 &(h->reply_pool_dhandle));
6786
254f796b
MG		 6787 for (i = 0; i < h->nreply_queues; i++) {
6788 h->reply_queue[i].head = &h->reply_pool[h->max_commands * i];
6789 h->reply_queue[i].size = h->max_commands;
6790 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
6791 h->reply_queue[i].current_entry = 0;
6792 }
6793
6c311b57 6794 /* Need a block fetch table for performant mode */
d66ae08b 6795 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57
SC		 6796 sizeof(u32)), GFP_KERNEL);
6797
6798 if ((h->reply_pool == NULL)
6799 || (h->blockFetchTable == NULL))
6800 goto clean_up;
6801
e1f7de0c 6802 hpsa_enter_performant_mode(h, trans_support);
303932fd
DB		 6803 return;
6804
6805clean_up:
6806 if (h->reply_pool)
6807 pci_free_consistent(h->pdev, h->reply_pool_size,
6808 h->reply_pool, h->reply_pool_dhandle);
6809 kfree(h->blockFetchTable);
6810}
6811
76438d08
SC		 6812static void hpsa_drain_commands(struct ctlr_info *h)
6813{
6814 int cmds_out;
6815 unsigned long flags;
6816
6817 do { /* wait for all outstanding commands to drain out */
6818 spin_lock_irqsave(&h->lock, flags);
6819 cmds_out = h->commands_outstanding;
6820 spin_unlock_irqrestore(&h->lock, flags);
6821 if (cmds_out <= 0)
6822 break;
6823 msleep(100);
6824 } while (1);
6825}
6826
edd16368
SC		 6827/*
6828 * This is it. Register the PCI driver information for the cards we control
6829 * the OS will call our registered routines when it finds one of our cards.
6830 */
6831static int __init hpsa_init(void)
6832{
31468401 6833 return pci_register_driver(&hpsa_pci_driver);
edd16368
SC		 6834}
6835
6836static void __exit hpsa_cleanup(void)
6837{
6838 pci_unregister_driver(&hpsa_pci_driver);
edd16368
SC		 6839}
6840
e1f7de0c
MG		 6841static void __attribute__((unused)) verify_offsets(void)
6842{
b66cc250
MM		 6843#define VERIFY_OFFSET(member, offset) \
6844 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
6845
6846 VERIFY_OFFSET(IU_type, 0);
6847 VERIFY_OFFSET(direction, 1);
6848 VERIFY_OFFSET(reply_queue, 2);
6849 /* VERIFY_OFFSET(reserved1, 3); */
6850 VERIFY_OFFSET(scsi_nexus, 4);
6851 VERIFY_OFFSET(Tag, 8);
6852 VERIFY_OFFSET(cdb, 16);
6853 VERIFY_OFFSET(cciss_lun, 32);
6854 VERIFY_OFFSET(data_len, 40);
6855 VERIFY_OFFSET(cmd_priority_task_attr, 44);
6856 VERIFY_OFFSET(sg_count, 45);
6857 /* VERIFY_OFFSET(reserved3 */
6858 VERIFY_OFFSET(err_ptr, 48);
6859 VERIFY_OFFSET(err_len, 56);
6860 /* VERIFY_OFFSET(reserved4 */
6861 VERIFY_OFFSET(sg, 64);
6862
6863#undef VERIFY_OFFSET
6864
e1f7de0c
MG		 6865#define VERIFY_OFFSET(member, offset) \
6866 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
6867
6868 VERIFY_OFFSET(dev_handle, 0x00);
6869 VERIFY_OFFSET(reserved1, 0x02);
6870 VERIFY_OFFSET(function, 0x03);
6871 VERIFY_OFFSET(reserved2, 0x04);
6872 VERIFY_OFFSET(err_info, 0x0C);
6873 VERIFY_OFFSET(reserved3, 0x10);
6874 VERIFY_OFFSET(err_info_len, 0x12);
6875 VERIFY_OFFSET(reserved4, 0x13);
6876 VERIFY_OFFSET(sgl_offset, 0x14);
6877 VERIFY_OFFSET(reserved5, 0x15);
6878 VERIFY_OFFSET(transfer_len, 0x1C);
6879 VERIFY_OFFSET(reserved6, 0x20);
6880 VERIFY_OFFSET(io_flags, 0x24);
6881 VERIFY_OFFSET(reserved7, 0x26);
6882 VERIFY_OFFSET(LUN, 0x34);
6883 VERIFY_OFFSET(control, 0x3C);
6884 VERIFY_OFFSET(CDB, 0x40);
6885 VERIFY_OFFSET(reserved8, 0x50);
6886 VERIFY_OFFSET(host_context_flags, 0x60);
6887 VERIFY_OFFSET(timeout_sec, 0x62);
6888 VERIFY_OFFSET(ReplyQueue, 0x64);
6889 VERIFY_OFFSET(reserved9, 0x65);
6890 VERIFY_OFFSET(Tag, 0x68);
6891 VERIFY_OFFSET(host_addr, 0x70);
6892 VERIFY_OFFSET(CISS_LUN, 0x78);
6893 VERIFY_OFFSET(SG, 0x78 + 8);
6894#undef VERIFY_OFFSET
6895}
6896
edd16368
SC		 6897module_init(hpsa_init);
6898module_exit(hpsa_cleanup);
Linux 6.x block layer and io_uring tree(s)