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Merge branch 'pm-x86'
[linux-2.6-block.git] / drivers / scsi / hpsa.c
CommitLineData
edd16368
SC		 1/*
2 * Disk Array driver for HP Smart Array SAS controllers
94c7bc31 3 * Copyright 2016 Microsemi Corporation
1358f6dc
DB		 4 * Copyright 2014-2015 PMC-Sierra, Inc.
5 * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
edd16368
SC		 6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
14 * NON INFRINGEMENT. See the GNU General Public License for more details.
15 *
94c7bc31 16 * Questions/Comments/Bugfixes to esc.storagedev@microsemi.com
edd16368
SC		 17 *
18 */
19
20#include <linux/module.h>
21#include <linux/interrupt.h>
22#include <linux/types.h>
23#include <linux/pci.h>
e5a44df8 24#include <linux/pci-aspm.h>
edd16368
SC		 25#include <linux/kernel.h>
26#include <linux/slab.h>
27#include <linux/delay.h>
28#include <linux/fs.h>
29#include <linux/timer.h>
edd16368
SC		 30#include <linux/init.h>
31#include <linux/spinlock.h>
edd16368
SC		 32#include <linux/compat.h>
33#include <linux/blktrace_api.h>
34#include <linux/uaccess.h>
35#include <linux/io.h>
36#include <linux/dma-mapping.h>
37#include <linux/completion.h>
38#include <linux/moduleparam.h>
39#include <scsi/scsi.h>
40#include <scsi/scsi_cmnd.h>
41#include <scsi/scsi_device.h>
42#include <scsi/scsi_host.h>
667e23d4 43#include <scsi/scsi_tcq.h>
9437ac43 44#include <scsi/scsi_eh.h>
d04e62b9 45#include <scsi/scsi_transport_sas.h>
73153fe5 46#include <scsi/scsi_dbg.h>
edd16368
SC		 47#include <linux/cciss_ioctl.h>
48#include <linux/string.h>
49#include <linux/bitmap.h>
60063497 50#include <linux/atomic.h>
a0c12413 51#include <linux/jiffies.h>
42a91641 52#include <linux/percpu-defs.h>
094963da 53#include <linux/percpu.h>
2b08b3e9 54#include <asm/unaligned.h>
283b4a9b 55#include <asm/div64.h>
edd16368
SC		 56#include "hpsa_cmd.h"
57#include "hpsa.h"
58
ec2c3aa9
DB		 59/*
60 * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.'
61 * with an optional trailing '-' followed by a byte value (0-255).
62 */
c59c32cd 63#define HPSA_DRIVER_VERSION "3.4.20-160"
edd16368 64#define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
f79cfec6 65#define HPSA "hpsa"
edd16368 66
007e7aa9
RE		 67/* How long to wait for CISS doorbell communication */
68#define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
69#define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
70#define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
71#define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
edd16368
SC		 72#define MAX_IOCTL_CONFIG_WAIT 1000
73
74/*define how many times we will try a command because of bus resets */
75#define MAX_CMD_RETRIES 3
76
77/* Embedded module documentation macros - see modules.h */
78MODULE_AUTHOR("Hewlett-Packard Company");
79MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
80 HPSA_DRIVER_VERSION);
81MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
82MODULE_VERSION(HPSA_DRIVER_VERSION);
83MODULE_LICENSE("GPL");
253d2464 84MODULE_ALIAS("cciss");
edd16368 85
02ec19c8
SC		 86static int hpsa_simple_mode;
87module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
88MODULE_PARM_DESC(hpsa_simple_mode,
89 "Use 'simple mode' rather than 'performant mode'");
edd16368
SC		 90
91/* define the PCI info for the cards we can control */
92static const struct pci_device_id hpsa_pci_device_id[] = {
edd16368
SC		 93 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
94 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
95 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
96 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
97 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
163dbcd8
MM		 98 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
99 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
f8b01eb9 100 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
9143a961 101 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
102 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
103 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
104 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
105 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
106 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
107 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
7f1974a7 108 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103c, 0x1920},
fe0c9610
MM		 109 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
110 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
111 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
112 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
7f1974a7 113 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103c, 0x1925},
fe0c9610
MM		 114 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
115 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
97b9f53d
MM		 116 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
117 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
118 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
119 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
120 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
121 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
122 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
123 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
124 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
125 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
3b7a45e5 126 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
97b9f53d
MM		 127 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
128 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
129 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
3b7a45e5
JH		 130 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
131 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
132 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
133 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
134 {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
fdfa4b6d 135 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
cbb47dcb
DB		 136 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
137 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
138 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
139 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
140 {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
8e616a5e
SC		 141 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
142 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
143 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
144 {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
145 {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
7c03b870 146 {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
6798cc0a 147 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
135ae6ed
HR		 148 {PCI_VENDOR_ID_COMPAQ, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
149 PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
edd16368
SC		 150 {0,}
151};
152
153MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
154
155/* board_id = Subsystem Device ID & Vendor ID
156 * product = Marketing Name for the board
157 * access = Address of the struct of function pointers
158 */
159static struct board_type products[] = {
135ae6ed
HR		 160 {0x40700E11, "Smart Array 5300", &SA5A_access},
161 {0x40800E11, "Smart Array 5i", &SA5B_access},
162 {0x40820E11, "Smart Array 532", &SA5B_access},
163 {0x40830E11, "Smart Array 5312", &SA5B_access},
164 {0x409A0E11, "Smart Array 641", &SA5A_access},
165 {0x409B0E11, "Smart Array 642", &SA5A_access},
166 {0x409C0E11, "Smart Array 6400", &SA5A_access},
167 {0x409D0E11, "Smart Array 6400 EM", &SA5A_access},
168 {0x40910E11, "Smart Array 6i", &SA5A_access},
169 {0x3225103C, "Smart Array P600", &SA5A_access},
170 {0x3223103C, "Smart Array P800", &SA5A_access},
171 {0x3234103C, "Smart Array P400", &SA5A_access},
172 {0x3235103C, "Smart Array P400i", &SA5A_access},
173 {0x3211103C, "Smart Array E200i", &SA5A_access},
174 {0x3212103C, "Smart Array E200", &SA5A_access},
175 {0x3213103C, "Smart Array E200i", &SA5A_access},
176 {0x3214103C, "Smart Array E200i", &SA5A_access},
177 {0x3215103C, "Smart Array E200i", &SA5A_access},
178 {0x3237103C, "Smart Array E500", &SA5A_access},
179 {0x323D103C, "Smart Array P700m", &SA5A_access},
edd16368
SC		 180 {0x3241103C, "Smart Array P212", &SA5_access},
181 {0x3243103C, "Smart Array P410", &SA5_access},
182 {0x3245103C, "Smart Array P410i", &SA5_access},
183 {0x3247103C, "Smart Array P411", &SA5_access},
184 {0x3249103C, "Smart Array P812", &SA5_access},
163dbcd8
MM		 185 {0x324A103C, "Smart Array P712m", &SA5_access},
186 {0x324B103C, "Smart Array P711m", &SA5_access},
7d2cce58 187 {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
fe0c9610
MM		 188 {0x3350103C, "Smart Array P222", &SA5_access},
189 {0x3351103C, "Smart Array P420", &SA5_access},
190 {0x3352103C, "Smart Array P421", &SA5_access},
191 {0x3353103C, "Smart Array P822", &SA5_access},
192 {0x3354103C, "Smart Array P420i", &SA5_access},
193 {0x3355103C, "Smart Array P220i", &SA5_access},
194 {0x3356103C, "Smart Array P721m", &SA5_access},
7f1974a7 195 {0x1920103C, "Smart Array P430i", &SA5_access},
1fd6c8e3
MM		 196 {0x1921103C, "Smart Array P830i", &SA5_access},
197 {0x1922103C, "Smart Array P430", &SA5_access},
198 {0x1923103C, "Smart Array P431", &SA5_access},
199 {0x1924103C, "Smart Array P830", &SA5_access},
7f1974a7 200 {0x1925103C, "Smart Array P831", &SA5_access},
1fd6c8e3
MM		 201 {0x1926103C, "Smart Array P731m", &SA5_access},
202 {0x1928103C, "Smart Array P230i", &SA5_access},
203 {0x1929103C, "Smart Array P530", &SA5_access},
27fb8137
DB		 204 {0x21BD103C, "Smart Array P244br", &SA5_access},
205 {0x21BE103C, "Smart Array P741m", &SA5_access},
206 {0x21BF103C, "Smart HBA H240ar", &SA5_access},
207 {0x21C0103C, "Smart Array P440ar", &SA5_access},
c8ae0ab1 208 {0x21C1103C, "Smart Array P840ar", &SA5_access},
27fb8137
DB		 209 {0x21C2103C, "Smart Array P440", &SA5_access},
210 {0x21C3103C, "Smart Array P441", &SA5_access},
97b9f53d 211 {0x21C4103C, "Smart Array", &SA5_access},
27fb8137
DB		 212 {0x21C5103C, "Smart Array P841", &SA5_access},
213 {0x21C6103C, "Smart HBA H244br", &SA5_access},
214 {0x21C7103C, "Smart HBA H240", &SA5_access},
215 {0x21C8103C, "Smart HBA H241", &SA5_access},
97b9f53d 216 {0x21C9103C, "Smart Array", &SA5_access},
27fb8137
DB		 217 {0x21CA103C, "Smart Array P246br", &SA5_access},
218 {0x21CB103C, "Smart Array P840", &SA5_access},
3b7a45e5
JH		 219 {0x21CC103C, "Smart Array", &SA5_access},
220 {0x21CD103C, "Smart Array", &SA5_access},
27fb8137 221 {0x21CE103C, "Smart HBA", &SA5_access},
fdfa4b6d 222 {0x05809005, "SmartHBA-SA", &SA5_access},
cbb47dcb
DB		 223 {0x05819005, "SmartHBA-SA 8i", &SA5_access},
224 {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
225 {0x05839005, "SmartHBA-SA 8e", &SA5_access},
226 {0x05849005, "SmartHBA-SA 16i", &SA5_access},
227 {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
8e616a5e
SC		 228 {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
229 {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
230 {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
231 {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
232 {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
edd16368
SC		 233 {0xFFFF103C, "Unknown Smart Array", &SA5_access},
234};
235
d04e62b9
KB		 236static struct scsi_transport_template *hpsa_sas_transport_template;
237static int hpsa_add_sas_host(struct ctlr_info *h);
238static void hpsa_delete_sas_host(struct ctlr_info *h);
239static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
240 struct hpsa_scsi_dev_t *device);
241static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device);
242static struct hpsa_scsi_dev_t
243 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
244 struct sas_rphy *rphy);
245
a58e7e53
WS		 246#define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
247static const struct scsi_cmnd hpsa_cmd_busy;
248#define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
249static const struct scsi_cmnd hpsa_cmd_idle;
edd16368
SC		 250static int number_of_controllers;
251
10f66018
SC		 252static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
253static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
6f4e626f
NC		 254static int hpsa_ioctl(struct scsi_device *dev, unsigned int cmd,
255 void __user *arg);
edd16368
SC		 256
257#ifdef CONFIG_COMPAT
6f4e626f 258static int hpsa_compat_ioctl(struct scsi_device *dev, unsigned int cmd,
42a91641 259 void __user *arg);
edd16368
SC		 260#endif
261
262static void cmd_free(struct ctlr_info *h, struct CommandList *c);
edd16368 263static struct CommandList *cmd_alloc(struct ctlr_info *h);
73153fe5
WS		 264static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
265static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
266 struct scsi_cmnd *scmd);
a2dac136 267static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 268 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368 269 int cmd_type);
2c143342 270static void hpsa_free_cmd_pool(struct ctlr_info *h);
b7bb24eb 271#define VPD_PAGE (1 << 8)
b48d9804 272#define HPSA_SIMPLE_ERROR_BITS 0x03
edd16368 273
f281233d 274static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
a08a8471
SC		 275static void hpsa_scan_start(struct Scsi_Host *);
276static int hpsa_scan_finished(struct Scsi_Host *sh,
277 unsigned long elapsed_time);
7c0a0229 278static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
edd16368
SC		 279
280static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
281static int hpsa_slave_alloc(struct scsi_device *sdev);
41ce4c35 282static int hpsa_slave_configure(struct scsi_device *sdev);
edd16368
SC		 283static void hpsa_slave_destroy(struct scsi_device *sdev);
284
8aa60681 285static void hpsa_update_scsi_devices(struct ctlr_info *h);
edd16368
SC		 286static int check_for_unit_attention(struct ctlr_info *h,
287 struct CommandList *c);
288static void check_ioctl_unit_attention(struct ctlr_info *h,
289 struct CommandList *c);
303932fd
DB		 290/* performant mode helper functions */
291static void calc_bucket_map(int *bucket, int num_buckets,
2b08b3e9 292 int nsgs, int min_blocks, u32 *bucket_map);
105a3dbc
RE		 293static void hpsa_free_performant_mode(struct ctlr_info *h);
294static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
254f796b 295static inline u32 next_command(struct ctlr_info *h, u8 q);
6f039790
GKH		 296static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
297 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
298 u64 *cfg_offset);
299static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
300 unsigned long *memory_bar);
135ae6ed
HR		 301static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id,
302 bool *legacy_board);
bfd7546c
DB		 303static int wait_for_device_to_become_ready(struct ctlr_info *h,
304 unsigned char lunaddr[],
305 int reply_queue);
6f039790
GKH		 306static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
307 int wait_for_ready);
75167d2c 308static inline void finish_cmd(struct CommandList *c);
c706a795 309static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
fe5389c8
SC		 310#define BOARD_NOT_READY 0
311#define BOARD_READY 1
23100dd9 312static void hpsa_drain_accel_commands(struct ctlr_info *h);
76438d08 313static void hpsa_flush_cache(struct ctlr_info *h);
c349775e
ST		 314static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
315 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 316 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
080ef1cc 317static void hpsa_command_resubmit_worker(struct work_struct *work);
25163bd5
WS		 318static u32 lockup_detected(struct ctlr_info *h);
319static int detect_controller_lockup(struct ctlr_info *h);
c2adae44 320static void hpsa_disable_rld_caching(struct ctlr_info *h);
d04e62b9
KB		 321static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
322 struct ReportExtendedLUNdata *buf, int bufsize);
8383278d
ST		 323static bool hpsa_vpd_page_supported(struct ctlr_info *h,
324 unsigned char scsi3addr[], u8 page);
34592254 325static int hpsa_luns_changed(struct ctlr_info *h);
ba74fdc4
DB		 326static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
327 struct hpsa_scsi_dev_t *dev,
328 unsigned char *scsi3addr);
edd16368 329
edd16368
SC		 330static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
331{
332 unsigned long *priv = shost_priv(sdev->host);
333 return (struct ctlr_info *) *priv;
334}
335
a23513e8
SC		 336static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
337{
338 unsigned long *priv = shost_priv(sh);
339 return (struct ctlr_info *) *priv;
340}
341
a58e7e53
WS		 342static inline bool hpsa_is_cmd_idle(struct CommandList *c)
343{
344 return c->scsi_cmd == SCSI_CMD_IDLE;
345}
346
d604f533
WS		 347static inline bool hpsa_is_pending_event(struct CommandList *c)
348{
08ec46f6 349 return c->reset_pending;
d604f533
WS		 350}
351
9437ac43
SC		 352/* extract sense key, asc, and ascq from sense data. -1 means invalid. */
353static void decode_sense_data(const u8 *sense_data, int sense_data_len,
354 u8 *sense_key, u8 *asc, u8 *ascq)
355{
356 struct scsi_sense_hdr sshdr;
357 bool rc;
358
359 *sense_key = -1;
360 *asc = -1;
361 *ascq = -1;
362
363 if (sense_data_len < 1)
364 return;
365
366 rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
367 if (rc) {
368 *sense_key = sshdr.sense_key;
369 *asc = sshdr.asc;
370 *ascq = sshdr.ascq;
371 }
372}
373
edd16368
SC		 374static int check_for_unit_attention(struct ctlr_info *h,
375 struct CommandList *c)
376{
9437ac43
SC		 377 u8 sense_key, asc, ascq;
378 int sense_len;
379
380 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
381 sense_len = sizeof(c->err_info->SenseInfo);
382 else
383 sense_len = c->err_info->SenseLen;
384
385 decode_sense_data(c->err_info->SenseInfo, sense_len,
386 &sense_key, &asc, &ascq);
81c27557 387 if (sense_key != UNIT_ATTENTION || asc == 0xff)
edd16368
SC		 388 return 0;
389
9437ac43 390 switch (asc) {
edd16368 391 case STATE_CHANGED:
9437ac43 392 dev_warn(&h->pdev->dev,
2946e82b
RE		 393 "%s: a state change detected, command retried\n",
394 h->devname);
edd16368
SC		 395 break;
396 case LUN_FAILED:
7f73695a 397 dev_warn(&h->pdev->dev,
2946e82b 398 "%s: LUN failure detected\n", h->devname);
edd16368
SC		 399 break;
400 case REPORT_LUNS_CHANGED:
7f73695a 401 dev_warn(&h->pdev->dev,
2946e82b 402 "%s: report LUN data changed\n", h->devname);
edd16368 403 /*
4f4eb9f1
ST		 404 * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
405 * target (array) devices.
edd16368
SC		 406 */
407 break;
408 case POWER_OR_RESET:
2946e82b
RE		 409 dev_warn(&h->pdev->dev,
410 "%s: a power on or device reset detected\n",
411 h->devname);
edd16368
SC		 412 break;
413 case UNIT_ATTENTION_CLEARED:
2946e82b
RE		 414 dev_warn(&h->pdev->dev,
415 "%s: unit attention cleared by another initiator\n",
416 h->devname);
edd16368
SC		 417 break;
418 default:
2946e82b
RE		 419 dev_warn(&h->pdev->dev,
420 "%s: unknown unit attention detected\n",
421 h->devname);
edd16368
SC		 422 break;
423 }
424 return 1;
425}
426
852af20a
MB		 427static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
428{
429 if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
430 (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
431 c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
432 return 0;
433 dev_warn(&h->pdev->dev, HPSA "device busy");
434 return 1;
435}
436
e985c58f
SC		 437static u32 lockup_detected(struct ctlr_info *h);
438static ssize_t host_show_lockup_detected(struct device *dev,
439 struct device_attribute *attr, char *buf)
440{
441 int ld;
442 struct ctlr_info *h;
443 struct Scsi_Host *shost = class_to_shost(dev);
444
445 h = shost_to_hba(shost);
446 ld = lockup_detected(h);
447
448 return sprintf(buf, "ld=%d\n", ld);
449}
450
da0697bd
ST		 451static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
452 struct device_attribute *attr,
453 const char *buf, size_t count)
454{
455 int status, len;
456 struct ctlr_info *h;
457 struct Scsi_Host *shost = class_to_shost(dev);
458 char tmpbuf[10];
459
460 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
461 return -EACCES;
462 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
463 strncpy(tmpbuf, buf, len);
464 tmpbuf[len] = '\0';
465 if (sscanf(tmpbuf, "%d", &status) != 1)
466 return -EINVAL;
467 h = shost_to_hba(shost);
468 h->acciopath_status = !!status;
469 dev_warn(&h->pdev->dev,
470 "hpsa: HP SSD Smart Path %s via sysfs update.\n",
471 h->acciopath_status ? "enabled" : "disabled");
472 return count;
473}
474
2ba8bfc8
SC		 475static ssize_t host_store_raid_offload_debug(struct device *dev,
476 struct device_attribute *attr,
477 const char *buf, size_t count)
478{
479 int debug_level, len;
480 struct ctlr_info *h;
481 struct Scsi_Host *shost = class_to_shost(dev);
482 char tmpbuf[10];
483
484 if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
485 return -EACCES;
486 len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
487 strncpy(tmpbuf, buf, len);
488 tmpbuf[len] = '\0';
489 if (sscanf(tmpbuf, "%d", &debug_level) != 1)
490 return -EINVAL;
491 if (debug_level < 0)
492 debug_level = 0;
493 h = shost_to_hba(shost);
494 h->raid_offload_debug = debug_level;
495 dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
496 h->raid_offload_debug);
497 return count;
498}
499
edd16368
SC		 500static ssize_t host_store_rescan(struct device *dev,
501 struct device_attribute *attr,
502 const char *buf, size_t count)
503{
504 struct ctlr_info *h;
505 struct Scsi_Host *shost = class_to_shost(dev);
a23513e8 506 h = shost_to_hba(shost);
31468401 507 hpsa_scan_start(h->scsi_host);
edd16368
SC		 508 return count;
509}
510
d28ce020
SC		 511static ssize_t host_show_firmware_revision(struct device *dev,
512 struct device_attribute *attr, char *buf)
513{
514 struct ctlr_info *h;
515 struct Scsi_Host *shost = class_to_shost(dev);
516 unsigned char *fwrev;
517
518 h = shost_to_hba(shost);
519 if (!h->hba_inquiry_data)
520 return 0;
521 fwrev = &h->hba_inquiry_data[32];
522 return snprintf(buf, 20, "%c%c%c%c\n",
523 fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
524}
525
94a13649
SC		 526static ssize_t host_show_commands_outstanding(struct device *dev,
527 struct device_attribute *attr, char *buf)
528{
529 struct Scsi_Host *shost = class_to_shost(dev);
530 struct ctlr_info *h = shost_to_hba(shost);
531
0cbf768e
SC		 532 return snprintf(buf, 20, "%d\n",
533 atomic_read(&h->commands_outstanding));
94a13649
SC		 534}
535
745a7a25
SC		 536static ssize_t host_show_transport_mode(struct device *dev,
537 struct device_attribute *attr, char *buf)
538{
539 struct ctlr_info *h;
540 struct Scsi_Host *shost = class_to_shost(dev);
541
542 h = shost_to_hba(shost);
543 return snprintf(buf, 20, "%s\n",
960a30e7 544 h->transMethod & CFGTBL_Trans_Performant ?
745a7a25
SC		 545 "performant" : "simple");
546}
547
da0697bd
ST		 548static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
549 struct device_attribute *attr, char *buf)
550{
551 struct ctlr_info *h;
552 struct Scsi_Host *shost = class_to_shost(dev);
553
554 h = shost_to_hba(shost);
555 return snprintf(buf, 30, "HP SSD Smart Path %s\n",
556 (h->acciopath_status == 1) ? "enabled" : "disabled");
557}
558
46380786 559/* List of controllers which cannot be hard reset on kexec with reset_devices */
941b1cda
SC		 560static u32 unresettable_controller[] = {
561 0x324a103C, /* Smart Array P712m */
9b5c48c2 562 0x324b103C, /* Smart Array P711m */
941b1cda
SC		 563 0x3223103C, /* Smart Array P800 */
564 0x3234103C, /* Smart Array P400 */
565 0x3235103C, /* Smart Array P400i */
566 0x3211103C, /* Smart Array E200i */
567 0x3212103C, /* Smart Array E200 */
568 0x3213103C, /* Smart Array E200i */
569 0x3214103C, /* Smart Array E200i */
570 0x3215103C, /* Smart Array E200i */
571 0x3237103C, /* Smart Array E500 */
572 0x323D103C, /* Smart Array P700m */
7af0abbc 573 0x40800E11, /* Smart Array 5i */
941b1cda
SC		 574 0x409C0E11, /* Smart Array 6400 */
575 0x409D0E11, /* Smart Array 6400 EM */
5a4f934e
TH		 576 0x40700E11, /* Smart Array 5300 */
577 0x40820E11, /* Smart Array 532 */
578 0x40830E11, /* Smart Array 5312 */
579 0x409A0E11, /* Smart Array 641 */
580 0x409B0E11, /* Smart Array 642 */
581 0x40910E11, /* Smart Array 6i */
941b1cda
SC		 582};
583
46380786
SC		 584/* List of controllers which cannot even be soft reset */
585static u32 soft_unresettable_controller[] = {
7af0abbc 586 0x40800E11, /* Smart Array 5i */
5a4f934e
TH		 587 0x40700E11, /* Smart Array 5300 */
588 0x40820E11, /* Smart Array 532 */
589 0x40830E11, /* Smart Array 5312 */
590 0x409A0E11, /* Smart Array 641 */
591 0x409B0E11, /* Smart Array 642 */
592 0x40910E11, /* Smart Array 6i */
46380786
SC		 593 /* Exclude 640x boards. These are two pci devices in one slot
594 * which share a battery backed cache module. One controls the
595 * cache, the other accesses the cache through the one that controls
596 * it. If we reset the one controlling the cache, the other will
597 * likely not be happy. Just forbid resetting this conjoined mess.
598 * The 640x isn't really supported by hpsa anyway.
599 */
600 0x409C0E11, /* Smart Array 6400 */
601 0x409D0E11, /* Smart Array 6400 EM */
602};
603
9b5c48c2 604static int board_id_in_array(u32 a[], int nelems, u32 board_id)
941b1cda
SC		 605{
606 int i;
607
9b5c48c2
SC		 608 for (i = 0; i < nelems; i++)
609 if (a[i] == board_id)
610 return 1;
611 return 0;
46380786
SC		 612}
613
9b5c48c2 614static int ctlr_is_hard_resettable(u32 board_id)
46380786 615{
9b5c48c2
SC		 616 return !board_id_in_array(unresettable_controller,
617 ARRAY_SIZE(unresettable_controller), board_id);
618}
46380786 619
9b5c48c2
SC		 620static int ctlr_is_soft_resettable(u32 board_id)
621{
622 return !board_id_in_array(soft_unresettable_controller,
623 ARRAY_SIZE(soft_unresettable_controller), board_id);
941b1cda
SC		 624}
625
46380786
SC		 626static int ctlr_is_resettable(u32 board_id)
627{
628 return ctlr_is_hard_resettable(board_id) ||
629 ctlr_is_soft_resettable(board_id);
630}
631
941b1cda
SC		 632static ssize_t host_show_resettable(struct device *dev,
633 struct device_attribute *attr, char *buf)
634{
635 struct ctlr_info *h;
636 struct Scsi_Host *shost = class_to_shost(dev);
637
638 h = shost_to_hba(shost);
46380786 639 return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
941b1cda
SC		 640}
641
edd16368
SC		 642static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
643{
644 return (scsi3addr[3] & 0xC0) == 0x40;
645}
646
f2ef0ce7 647static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
7c59a0d4 648 "1(+0)ADM", "UNKNOWN", "PHYS DRV"
edd16368 649};
6b80b18f
ST		 650#define HPSA_RAID_0 0
651#define HPSA_RAID_4 1
652#define HPSA_RAID_1 2 /* also used for RAID 10 */
653#define HPSA_RAID_5 3 /* also used for RAID 50 */
654#define HPSA_RAID_51 4
655#define HPSA_RAID_6 5 /* also used for RAID 60 */
656#define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
7c59a0d4
DB		 657#define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2)
658#define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1)
edd16368 659
f3f01730
KB		 660static inline bool is_logical_device(struct hpsa_scsi_dev_t *device)
661{
662 return !device->physical_device;
663}
edd16368
SC		 664
665static ssize_t raid_level_show(struct device *dev,
666 struct device_attribute *attr, char *buf)
667{
668 ssize_t l = 0;
82a72c0a 669 unsigned char rlevel;
edd16368
SC		 670 struct ctlr_info *h;
671 struct scsi_device *sdev;
672 struct hpsa_scsi_dev_t *hdev;
673 unsigned long flags;
674
675 sdev = to_scsi_device(dev);
676 h = sdev_to_hba(sdev);
677 spin_lock_irqsave(&h->lock, flags);
678 hdev = sdev->hostdata;
679 if (!hdev) {
680 spin_unlock_irqrestore(&h->lock, flags);
681 return -ENODEV;
682 }
683
684 /* Is this even a logical drive? */
f3f01730 685 if (!is_logical_device(hdev)) {
edd16368
SC		 686 spin_unlock_irqrestore(&h->lock, flags);
687 l = snprintf(buf, PAGE_SIZE, "N/A\n");
688 return l;
689 }
690
691 rlevel = hdev->raid_level;
692 spin_unlock_irqrestore(&h->lock, flags);
82a72c0a 693 if (rlevel > RAID_UNKNOWN)
edd16368
SC		 694 rlevel = RAID_UNKNOWN;
695 l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
696 return l;
697}
698
699static ssize_t lunid_show(struct device *dev,
700 struct device_attribute *attr, char *buf)
701{
702 struct ctlr_info *h;
703 struct scsi_device *sdev;
704 struct hpsa_scsi_dev_t *hdev;
705 unsigned long flags;
706 unsigned char lunid[8];
707
708 sdev = to_scsi_device(dev);
709 h = sdev_to_hba(sdev);
710 spin_lock_irqsave(&h->lock, flags);
711 hdev = sdev->hostdata;
712 if (!hdev) {
713 spin_unlock_irqrestore(&h->lock, flags);
714 return -ENODEV;
715 }
716 memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
717 spin_unlock_irqrestore(&h->lock, flags);
609a70df 718 return snprintf(buf, 20, "0x%8phN\n", lunid);
edd16368
SC		 719}
720
721static ssize_t unique_id_show(struct device *dev,
722 struct device_attribute *attr, char *buf)
723{
724 struct ctlr_info *h;
725 struct scsi_device *sdev;
726 struct hpsa_scsi_dev_t *hdev;
727 unsigned long flags;
728 unsigned char sn[16];
729
730 sdev = to_scsi_device(dev);
731 h = sdev_to_hba(sdev);
732 spin_lock_irqsave(&h->lock, flags);
733 hdev = sdev->hostdata;
734 if (!hdev) {
735 spin_unlock_irqrestore(&h->lock, flags);
736 return -ENODEV;
737 }
738 memcpy(sn, hdev->device_id, sizeof(sn));
739 spin_unlock_irqrestore(&h->lock, flags);
740 return snprintf(buf, 16 * 2 + 2,
741 "%02X%02X%02X%02X%02X%02X%02X%02X"
742 "%02X%02X%02X%02X%02X%02X%02X%02X\n",
743 sn[0], sn[1], sn[2], sn[3],
744 sn[4], sn[5], sn[6], sn[7],
745 sn[8], sn[9], sn[10], sn[11],
746 sn[12], sn[13], sn[14], sn[15]);
747}
748
ded1be4a
JH		 749static ssize_t sas_address_show(struct device *dev,
750 struct device_attribute *attr, char *buf)
751{
752 struct ctlr_info *h;
753 struct scsi_device *sdev;
754 struct hpsa_scsi_dev_t *hdev;
755 unsigned long flags;
756 u64 sas_address;
757
758 sdev = to_scsi_device(dev);
759 h = sdev_to_hba(sdev);
760 spin_lock_irqsave(&h->lock, flags);
761 hdev = sdev->hostdata;
762 if (!hdev || is_logical_device(hdev) || !hdev->expose_device) {
763 spin_unlock_irqrestore(&h->lock, flags);
764 return -ENODEV;
765 }
766 sas_address = hdev->sas_address;
767 spin_unlock_irqrestore(&h->lock, flags);
768
769 return snprintf(buf, PAGE_SIZE, "0x%016llx\n", sas_address);
770}
771
c1988684
ST		 772static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
773 struct device_attribute *attr, char *buf)
774{
775 struct ctlr_info *h;
776 struct scsi_device *sdev;
777 struct hpsa_scsi_dev_t *hdev;
778 unsigned long flags;
779 int offload_enabled;
780
781 sdev = to_scsi_device(dev);
782 h = sdev_to_hba(sdev);
783 spin_lock_irqsave(&h->lock, flags);
784 hdev = sdev->hostdata;
785 if (!hdev) {
786 spin_unlock_irqrestore(&h->lock, flags);
787 return -ENODEV;
788 }
789 offload_enabled = hdev->offload_enabled;
790 spin_unlock_irqrestore(&h->lock, flags);
b2582a65
DB		 791
792 if (hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC)
793 return snprintf(buf, 20, "%d\n", offload_enabled);
794 else
795 return snprintf(buf, 40, "%s\n",
796 "Not applicable for a controller");
c1988684
ST		 797}
798
8270b862 799#define MAX_PATHS 8
8270b862
JH		 800static ssize_t path_info_show(struct device *dev,
801 struct device_attribute *attr, char *buf)
802{
803 struct ctlr_info *h;
804 struct scsi_device *sdev;
805 struct hpsa_scsi_dev_t *hdev;
806 unsigned long flags;
807 int i;
808 int output_len = 0;
809 u8 box;
810 u8 bay;
811 u8 path_map_index = 0;
812 char *active;
813 unsigned char phys_connector[2];
8270b862 814
8270b862
JH		 815 sdev = to_scsi_device(dev);
816 h = sdev_to_hba(sdev);
817 spin_lock_irqsave(&h->devlock, flags);
818 hdev = sdev->hostdata;
819 if (!hdev) {
820 spin_unlock_irqrestore(&h->devlock, flags);
821 return -ENODEV;
822 }
823
824 bay = hdev->bay;
825 for (i = 0; i < MAX_PATHS; i++) {
826 path_map_index = 1<<i;
827 if (i == hdev->active_path_index)
828 active = "Active";
829 else if (hdev->path_map & path_map_index)
830 active = "Inactive";
831 else
832 continue;
833
1faf072c
RV		 834 output_len += scnprintf(buf + output_len,
835 PAGE_SIZE - output_len,
836 "[%d:%d:%d:%d] %20.20s ",
8270b862
JH		 837 h->scsi_host->host_no,
838 hdev->bus, hdev->target, hdev->lun,
839 scsi_device_type(hdev->devtype));
840
cca8f13b 841 if (hdev->devtype == TYPE_RAID || is_logical_device(hdev)) {
2708f295 842 output_len += scnprintf(buf + output_len,
1faf072c
RV		 843 PAGE_SIZE - output_len,
844 "%s\n", active);
8270b862
JH		 845 continue;
846 }
847
848 box = hdev->box[i];
849 memcpy(&phys_connector, &hdev->phys_connector[i],
850 sizeof(phys_connector));
851 if (phys_connector[0] < '0')
852 phys_connector[0] = '0';
853 if (phys_connector[1] < '0')
854 phys_connector[1] = '0';
cca8f13b 855 output_len += scnprintf(buf + output_len,
1faf072c 856 PAGE_SIZE - output_len,
8270b862
JH		 857 "PORT: %.2s ",
858 phys_connector);
af15ed36
DB		 859 if ((hdev->devtype == TYPE_DISK || hdev->devtype == TYPE_ZBC) &&
860 hdev->expose_device) {
8270b862 861 if (box == 0 || box == 0xFF) {
2708f295 862 output_len += scnprintf(buf + output_len,
1faf072c 863 PAGE_SIZE - output_len,
8270b862
JH		 864 "BAY: %hhu %s\n",
865 bay, active);
866 } else {
2708f295 867 output_len += scnprintf(buf + output_len,
1faf072c 868 PAGE_SIZE - output_len,
8270b862
JH		 869 "BOX: %hhu BAY: %hhu %s\n",
870 box, bay, active);
871 }
872 } else if (box != 0 && box != 0xFF) {
2708f295 873 output_len += scnprintf(buf + output_len,
1faf072c 874 PAGE_SIZE - output_len, "BOX: %hhu %s\n",
8270b862
JH		 875 box, active);
876 } else
2708f295 877 output_len += scnprintf(buf + output_len,
1faf072c 878 PAGE_SIZE - output_len, "%s\n", active);
8270b862
JH		 879 }
880
881 spin_unlock_irqrestore(&h->devlock, flags);
1faf072c 882 return output_len;
8270b862
JH		 883}
884
16961204
HR		 885static ssize_t host_show_ctlr_num(struct device *dev,
886 struct device_attribute *attr, char *buf)
887{
888 struct ctlr_info *h;
889 struct Scsi_Host *shost = class_to_shost(dev);
890
891 h = shost_to_hba(shost);
892 return snprintf(buf, 20, "%d\n", h->ctlr);
893}
894
135ae6ed
HR		 895static ssize_t host_show_legacy_board(struct device *dev,
896 struct device_attribute *attr, char *buf)
897{
898 struct ctlr_info *h;
899 struct Scsi_Host *shost = class_to_shost(dev);
900
901 h = shost_to_hba(shost);
902 return snprintf(buf, 20, "%d\n", h->legacy_board ? 1 : 0);
903}
904
c828a892
JP		 905static DEVICE_ATTR_RO(raid_level);
906static DEVICE_ATTR_RO(lunid);
907static DEVICE_ATTR_RO(unique_id);
3f5eac3a 908static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
c828a892 909static DEVICE_ATTR_RO(sas_address);
c1988684
ST		 910static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
911 host_show_hp_ssd_smart_path_enabled, NULL);
c828a892 912static DEVICE_ATTR_RO(path_info);
da0697bd
ST		 913static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
914 host_show_hp_ssd_smart_path_status,
915 host_store_hp_ssd_smart_path_status);
2ba8bfc8
SC		 916static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
917 host_store_raid_offload_debug);
3f5eac3a
SC		 918static DEVICE_ATTR(firmware_revision, S_IRUGO,
919 host_show_firmware_revision, NULL);
920static DEVICE_ATTR(commands_outstanding, S_IRUGO,
921 host_show_commands_outstanding, NULL);
922static DEVICE_ATTR(transport_mode, S_IRUGO,
923 host_show_transport_mode, NULL);
941b1cda
SC		 924static DEVICE_ATTR(resettable, S_IRUGO,
925 host_show_resettable, NULL);
e985c58f
SC		 926static DEVICE_ATTR(lockup_detected, S_IRUGO,
927 host_show_lockup_detected, NULL);
16961204
HR		 928static DEVICE_ATTR(ctlr_num, S_IRUGO,
929 host_show_ctlr_num, NULL);
135ae6ed
HR		 930static DEVICE_ATTR(legacy_board, S_IRUGO,
931 host_show_legacy_board, NULL);
3f5eac3a
SC		 932
933static struct device_attribute *hpsa_sdev_attrs[] = {
934 &dev_attr_raid_level,
935 &dev_attr_lunid,
936 &dev_attr_unique_id,
c1988684 937 &dev_attr_hp_ssd_smart_path_enabled,
8270b862 938 &dev_attr_path_info,
ded1be4a 939 &dev_attr_sas_address,
3f5eac3a
SC		 940 NULL,
941};
942
943static struct device_attribute *hpsa_shost_attrs[] = {
944 &dev_attr_rescan,
945 &dev_attr_firmware_revision,
946 &dev_attr_commands_outstanding,
947 &dev_attr_transport_mode,
941b1cda 948 &dev_attr_resettable,
da0697bd 949 &dev_attr_hp_ssd_smart_path_status,
2ba8bfc8 950 &dev_attr_raid_offload_debug,
fb53c439 951 &dev_attr_lockup_detected,
16961204 952 &dev_attr_ctlr_num,
135ae6ed 953 &dev_attr_legacy_board,
3f5eac3a
SC		 954 NULL,
955};
956
08ec46f6
DB		 957#define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_DRIVER +\
958 HPSA_MAX_CONCURRENT_PASSTHRUS)
41ce4c35 959
3f5eac3a
SC		 960static struct scsi_host_template hpsa_driver_template = {
961 .module = THIS_MODULE,
f79cfec6
SC		 962 .name = HPSA,
963 .proc_name = HPSA,
3f5eac3a
SC		 964 .queuecommand = hpsa_scsi_queue_command,
965 .scan_start = hpsa_scan_start,
966 .scan_finished = hpsa_scan_finished,
7c0a0229 967 .change_queue_depth = hpsa_change_queue_depth,
3f5eac3a 968 .this_id = -1,
3f5eac3a
SC		 969 .eh_device_reset_handler = hpsa_eh_device_reset_handler,
970 .ioctl = hpsa_ioctl,
971 .slave_alloc = hpsa_slave_alloc,
41ce4c35 972 .slave_configure = hpsa_slave_configure,
3f5eac3a
SC		 973 .slave_destroy = hpsa_slave_destroy,
974#ifdef CONFIG_COMPAT
975 .compat_ioctl = hpsa_compat_ioctl,
976#endif
977 .sdev_attrs = hpsa_sdev_attrs,
978 .shost_attrs = hpsa_shost_attrs,
eb53a3ea 979 .max_sectors = 2048,
54b2b50c 980 .no_write_same = 1,
3f5eac3a
SC		 981};
982
254f796b 983static inline u32 next_command(struct ctlr_info *h, u8 q)
3f5eac3a
SC		 984{
985 u32 a;
072b0518 986 struct reply_queue_buffer *rq = &h->reply_queue[q];
3f5eac3a 987
e1f7de0c
MG		 988 if (h->transMethod & CFGTBL_Trans_io_accel1)
989 return h->access.command_completed(h, q);
990
3f5eac3a 991 if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
254f796b 992 return h->access.command_completed(h, q);
3f5eac3a 993
254f796b
MG		 994 if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
995 a = rq->head[rq->current_entry];
996 rq->current_entry++;
0cbf768e 997 atomic_dec(&h->commands_outstanding);
3f5eac3a
SC		 998 } else {
999 a = FIFO_EMPTY;
1000 }
1001 /* Check for wraparound */
254f796b
MG		 1002 if (rq->current_entry == h->max_commands) {
1003 rq->current_entry = 0;
1004 rq->wraparound ^= 1;
3f5eac3a
SC		 1005 }
1006 return a;
1007}
1008
c349775e
ST		 1009/*
1010 * There are some special bits in the bus address of the
1011 * command that we have to set for the controller to know
1012 * how to process the command:
1013 *
1014 * Normal performant mode:
1015 * bit 0: 1 means performant mode, 0 means simple mode.
1016 * bits 1-3 = block fetch table entry
1017 * bits 4-6 = command type (== 0)
1018 *
1019 * ioaccel1 mode:
1020 * bit 0 = "performant mode" bit.
1021 * bits 1-3 = block fetch table entry
1022 * bits 4-6 = command type (== 110)
1023 * (command type is needed because ioaccel1 mode
1024 * commands are submitted through the same register as normal
1025 * mode commands, so this is how the controller knows whether
1026 * the command is normal mode or ioaccel1 mode.)
1027 *
1028 * ioaccel2 mode:
1029 * bit 0 = "performant mode" bit.
1030 * bits 1-4 = block fetch table entry (note extra bit)
1031 * bits 4-6 = not needed, because ioaccel2 mode has
1032 * a separate special register for submitting commands.
1033 */
1034
25163bd5
WS		 1035/*
1036 * set_performant_mode: Modify the tag for cciss performant
3f5eac3a
SC		 1037 * set bit 0 for pull model, bits 3-1 for block fetch
1038 * register number
1039 */
25163bd5
WS		 1040#define DEFAULT_REPLY_QUEUE (-1)
1041static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
1042 int reply_queue)
3f5eac3a 1043{
254f796b 1044 if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
3f5eac3a 1045 c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
bc2bb154 1046 if (unlikely(!h->msix_vectors))
25163bd5 1047 return;
8b834bff 1048 c->Header.ReplyQueue = reply_queue;
254f796b 1049 }
3f5eac3a
SC		 1050}
1051
c349775e 1052static void set_ioaccel1_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1053 struct CommandList *c,
1054 int reply_queue)
c349775e
ST		 1055{
1056 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
1057
25163bd5
WS		 1058 /*
1059 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1060 * processor. This seems to give the best I/O throughput.
1061 */
8b834bff 1062 cp->ReplyQueue = reply_queue;
25163bd5
WS		 1063 /*
1064 * Set the bits in the address sent down to include:
c349775e
ST		 1065 * - performant mode bit (bit 0)
1066 * - pull count (bits 1-3)
1067 * - command type (bits 4-6)
1068 */
1069 c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
1070 IOACCEL1_BUSADDR_CMDTYPE;
1071}
1072
8be986cc
SC		 1073static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
1074 struct CommandList *c,
1075 int reply_queue)
1076{
1077 struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
1078 &h->ioaccel2_cmd_pool[c->cmdindex];
1079
1080 /* Tell the controller to post the reply to the queue for this
1081 * processor. This seems to give the best I/O throughput.
1082 */
8b834bff 1083 cp->reply_queue = reply_queue;
8be986cc
SC		 1084 /* Set the bits in the address sent down to include:
1085 * - performant mode bit not used in ioaccel mode 2
1086 * - pull count (bits 0-3)
1087 * - command type isn't needed for ioaccel2
1088 */
1089 c->busaddr |= h->ioaccel2_blockFetchTable[0];
1090}
1091
c349775e 1092static void set_ioaccel2_performant_mode(struct ctlr_info *h,
25163bd5
WS		 1093 struct CommandList *c,
1094 int reply_queue)
c349775e
ST		 1095{
1096 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
1097
25163bd5
WS		 1098 /*
1099 * Tell the controller to post the reply to the queue for this
c349775e
ST		 1100 * processor. This seems to give the best I/O throughput.
1101 */
8b834bff 1102 cp->reply_queue = reply_queue;
25163bd5
WS		 1103 /*
1104 * Set the bits in the address sent down to include:
c349775e
ST		 1105 * - performant mode bit not used in ioaccel mode 2
1106 * - pull count (bits 0-3)
1107 * - command type isn't needed for ioaccel2
1108 */
1109 c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
1110}
1111
e85c5974
SC		 1112static int is_firmware_flash_cmd(u8 *cdb)
1113{
1114 return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
1115}
1116
1117/*
1118 * During firmware flash, the heartbeat register may not update as frequently
1119 * as it should. So we dial down lockup detection during firmware flash. and
1120 * dial it back up when firmware flash completes.
1121 */
1122#define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
1123#define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
3d38f00c 1124#define HPSA_EVENT_MONITOR_INTERVAL (15 * HZ)
e85c5974
SC		 1125static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
1126 struct CommandList *c)
1127{
1128 if (!is_firmware_flash_cmd(c->Request.CDB))
1129 return;
1130 atomic_inc(&h->firmware_flash_in_progress);
1131 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
1132}
1133
1134static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
1135 struct CommandList *c)
1136{
1137 if (is_firmware_flash_cmd(c->Request.CDB) &&
1138 atomic_dec_and_test(&h->firmware_flash_in_progress))
1139 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
1140}
1141
25163bd5
WS		 1142static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
1143 struct CommandList *c, int reply_queue)
3f5eac3a 1144{
c05e8866
SC		 1145 dial_down_lockup_detection_during_fw_flash(h, c);
1146 atomic_inc(&h->commands_outstanding);
8b834bff
ML		 1147
1148 reply_queue = h->reply_map[raw_smp_processor_id()];
c349775e
ST		 1149 switch (c->cmd_type) {
1150 case CMD_IOACCEL1:
25163bd5 1151 set_ioaccel1_performant_mode(h, c, reply_queue);
c05e8866 1152 writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
c349775e
ST		 1153 break;
1154 case CMD_IOACCEL2:
25163bd5 1155 set_ioaccel2_performant_mode(h, c, reply_queue);
c05e8866 1156 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
c349775e 1157 break;
8be986cc
SC		 1158 case IOACCEL2_TMF:
1159 set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
1160 writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
1161 break;
c349775e 1162 default:
25163bd5 1163 set_performant_mode(h, c, reply_queue);
c05e8866 1164 h->access.submit_command(h, c);
c349775e 1165 }
3f5eac3a
SC		 1166}
1167
a58e7e53 1168static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
25163bd5 1169{
d604f533 1170 if (unlikely(hpsa_is_pending_event(c)))
a58e7e53
WS		 1171 return finish_cmd(c);
1172
25163bd5
WS		 1173 __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
1174}
1175
3f5eac3a
SC		 1176static inline int is_hba_lunid(unsigned char scsi3addr[])
1177{
1178 return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
1179}
1180
1181static inline int is_scsi_rev_5(struct ctlr_info *h)
1182{
1183 if (!h->hba_inquiry_data)
1184 return 0;
1185 if ((h->hba_inquiry_data[2] & 0x07) == 5)
1186 return 1;
1187 return 0;
1188}
1189
edd16368
SC		 1190static int hpsa_find_target_lun(struct ctlr_info *h,
1191 unsigned char scsi3addr[], int bus, int *target, int *lun)
1192{
1193 /* finds an unused bus, target, lun for a new physical device
1194 * assumes h->devlock is held
1195 */
1196 int i, found = 0;
cfe5badc 1197 DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
edd16368 1198
263d9401 1199 bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
edd16368
SC		 1200
1201 for (i = 0; i < h->ndevices; i++) {
1202 if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
263d9401 1203 __set_bit(h->dev[i]->target, lun_taken);
edd16368
SC		 1204 }
1205
263d9401
AM		 1206 i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
1207 if (i < HPSA_MAX_DEVICES) {
1208 /* *bus = 1; */
1209 *target = i;
1210 *lun = 0;
1211 found = 1;
edd16368
SC		 1212 }
1213 return !found;
1214}
1215
1d33d85d 1216static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
0d96ef5f
WS		 1217 struct hpsa_scsi_dev_t *dev, char *description)
1218{
7c59a0d4
DB		 1219#define LABEL_SIZE 25
1220 char label[LABEL_SIZE];
1221
9975ec9d
DB		 1222 if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
1223 return;
1224
7c59a0d4
DB		 1225 switch (dev->devtype) {
1226 case TYPE_RAID:
1227 snprintf(label, LABEL_SIZE, "controller");
1228 break;
1229 case TYPE_ENCLOSURE:
1230 snprintf(label, LABEL_SIZE, "enclosure");
1231 break;
1232 case TYPE_DISK:
af15ed36 1233 case TYPE_ZBC:
7c59a0d4
DB		 1234 if (dev->external)
1235 snprintf(label, LABEL_SIZE, "external");
1236 else if (!is_logical_dev_addr_mode(dev->scsi3addr))
1237 snprintf(label, LABEL_SIZE, "%s",
1238 raid_label[PHYSICAL_DRIVE]);
1239 else
1240 snprintf(label, LABEL_SIZE, "RAID-%s",
1241 dev->raid_level > RAID_UNKNOWN ? "?" :
1242 raid_label[dev->raid_level]);
1243 break;
1244 case TYPE_ROM:
1245 snprintf(label, LABEL_SIZE, "rom");
1246 break;
1247 case TYPE_TAPE:
1248 snprintf(label, LABEL_SIZE, "tape");
1249 break;
1250 case TYPE_MEDIUM_CHANGER:
1251 snprintf(label, LABEL_SIZE, "changer");
1252 break;
1253 default:
1254 snprintf(label, LABEL_SIZE, "UNKNOWN");
1255 break;
1256 }
1257
0d96ef5f 1258 dev_printk(level, &h->pdev->dev,
7c59a0d4 1259 "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n",
0d96ef5f
WS		 1260 h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
1261 description,
1262 scsi_device_type(dev->devtype),
1263 dev->vendor,
1264 dev->model,
7c59a0d4 1265 label,
0d96ef5f 1266 dev->offload_config ? '+' : '-',
b2582a65 1267 dev->offload_to_be_enabled ? '+' : '-',
2a168208 1268 dev->expose_device);
0d96ef5f
WS		 1269}
1270
edd16368 1271/* Add an entry into h->dev[] array. */
8aa60681 1272static int hpsa_scsi_add_entry(struct ctlr_info *h,
edd16368
SC		 1273 struct hpsa_scsi_dev_t *device,
1274 struct hpsa_scsi_dev_t *added[], int *nadded)
1275{
1276 /* assumes h->devlock is held */
1277 int n = h->ndevices;
1278 int i;
1279 unsigned char addr1[8], addr2[8];
1280 struct hpsa_scsi_dev_t *sd;
1281
cfe5badc 1282 if (n >= HPSA_MAX_DEVICES) {
edd16368
SC		 1283 dev_err(&h->pdev->dev, "too many devices, some will be "
1284 "inaccessible.\n");
1285 return -1;
1286 }
1287
1288 /* physical devices do not have lun or target assigned until now. */
1289 if (device->lun != -1)
1290 /* Logical device, lun is already assigned. */
1291 goto lun_assigned;
1292
1293 /* If this device a non-zero lun of a multi-lun device
1294 * byte 4 of the 8-byte LUN addr will contain the logical
2b08b3e9 1295 * unit no, zero otherwise.
edd16368
SC		 1296 */
1297 if (device->scsi3addr[4] == 0) {
1298 /* This is not a non-zero lun of a multi-lun device */
1299 if (hpsa_find_target_lun(h, device->scsi3addr,
1300 device->bus, &device->target, &device->lun) != 0)
1301 return -1;
1302 goto lun_assigned;
1303 }
1304
1305 /* This is a non-zero lun of a multi-lun device.
1306 * Search through our list and find the device which
9a4178b7 1307 * has the same 8 byte LUN address, excepting byte 4 and 5.
edd16368
SC		 1308 * Assign the same bus and target for this new LUN.
1309 * Use the logical unit number from the firmware.
1310 */
1311 memcpy(addr1, device->scsi3addr, 8);
1312 addr1[4] = 0;
9a4178b7 1313 addr1[5] = 0;
edd16368
SC		 1314 for (i = 0; i < n; i++) {
1315 sd = h->dev[i];
1316 memcpy(addr2, sd->scsi3addr, 8);
1317 addr2[4] = 0;
9a4178b7 1318 addr2[5] = 0;
1319 /* differ only in byte 4 and 5? */
edd16368
SC		 1320 if (memcmp(addr1, addr2, 8) == 0) {
1321 device->bus = sd->bus;
1322 device->target = sd->target;
1323 device->lun = device->scsi3addr[4];
1324 break;
1325 }
1326 }
1327 if (device->lun == -1) {
1328 dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
1329 " suspect firmware bug or unsupported hardware "
1330 "configuration.\n");
b64ae4ab 1331 return -1;
edd16368
SC		 1332 }
1333
1334lun_assigned:
1335
1336 h->dev[n] = device;
1337 h->ndevices++;
1338 added[*nadded] = device;
1339 (*nadded)++;
0d96ef5f 1340 hpsa_show_dev_msg(KERN_INFO, h, device,
2a168208 1341 device->expose_device ? "added" : "masked");
edd16368
SC		 1342 return 0;
1343}
1344
b2582a65
DB		 1345/*
1346 * Called during a scan operation.
1347 *
1348 * Update an entry in h->dev[] array.
1349 */
8aa60681 1350static void hpsa_scsi_update_entry(struct ctlr_info *h,
bd9244f7
ST		 1351 int entry, struct hpsa_scsi_dev_t *new_entry)
1352{
1353 /* assumes h->devlock is held */
1354 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
1355
1356 /* Raid level changed. */
1357 h->dev[entry]->raid_level = new_entry->raid_level;
250fb125 1358
b2582a65
DB		 1359 /*
1360 * ioacccel_handle may have changed for a dual domain disk
1361 */
1362 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1363
03383736 1364 /* Raid offload parameters changed. Careful about the ordering. */
b2582a65 1365 if (new_entry->offload_config && new_entry->offload_to_be_enabled) {
03383736
DB		 1366 /*
1367 * if drive is newly offload_enabled, we want to copy the
1368 * raid map data first. If previously offload_enabled and
1369 * offload_config were set, raid map data had better be
b2582a65 1370 * the same as it was before. If raid map data has changed
03383736
DB		 1371 * then it had better be the case that
1372 * h->dev[entry]->offload_enabled is currently 0.
1373 */
1374 h->dev[entry]->raid_map = new_entry->raid_map;
1375 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
03383736 1376 }
b2582a65 1377 if (new_entry->offload_to_be_enabled) {
a3144e0b
JH		 1378 h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
1379 wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
1380 }
1381 h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
250fb125 1382 h->dev[entry]->offload_config = new_entry->offload_config;
9fb0de2d 1383 h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
03383736 1384 h->dev[entry]->queue_depth = new_entry->queue_depth;
250fb125 1385
41ce4c35
SC		 1386 /*
1387 * We can turn off ioaccel offload now, but need to delay turning
b2582a65 1388 * ioaccel on until we can update h->dev[entry]->phys_disk[], but we
41ce4c35
SC		 1389 * can't do that until all the devices are updated.
1390 */
b2582a65
DB		 1391 h->dev[entry]->offload_to_be_enabled = new_entry->offload_to_be_enabled;
1392
1393 /*
1394 * turn ioaccel off immediately if told to do so.
1395 */
1396 if (!new_entry->offload_to_be_enabled)
41ce4c35
SC		 1397 h->dev[entry]->offload_enabled = 0;
1398
0d96ef5f 1399 hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
bd9244f7
ST		 1400}
1401
2a8ccf31 1402/* Replace an entry from h->dev[] array. */
8aa60681 1403static void hpsa_scsi_replace_entry(struct ctlr_info *h,
2a8ccf31
SC		 1404 int entry, struct hpsa_scsi_dev_t *new_entry,
1405 struct hpsa_scsi_dev_t *added[], int *nadded,
1406 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1407{
1408 /* assumes h->devlock is held */
cfe5badc 1409 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
2a8ccf31
SC		 1410 removed[*nremoved] = h->dev[entry];
1411 (*nremoved)++;
01350d05
SC		 1412
1413 /*
1414 * New physical devices won't have target/lun assigned yet
1415 * so we need to preserve the values in the slot we are replacing.
1416 */
1417 if (new_entry->target == -1) {
1418 new_entry->target = h->dev[entry]->target;
1419 new_entry->lun = h->dev[entry]->lun;
1420 }
1421
2a8ccf31
SC		 1422 h->dev[entry] = new_entry;
1423 added[*nadded] = new_entry;
1424 (*nadded)++;
b2582a65 1425
0d96ef5f 1426 hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
2a8ccf31
SC		 1427}
1428
edd16368 1429/* Remove an entry from h->dev[] array. */
8aa60681 1430static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
edd16368
SC		 1431 struct hpsa_scsi_dev_t *removed[], int *nremoved)
1432{
1433 /* assumes h->devlock is held */
1434 int i;
1435 struct hpsa_scsi_dev_t *sd;
1436
cfe5badc 1437 BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
edd16368
SC		 1438
1439 sd = h->dev[entry];
1440 removed[*nremoved] = h->dev[entry];
1441 (*nremoved)++;
1442
1443 for (i = entry; i < h->ndevices-1; i++)
1444 h->dev[i] = h->dev[i+1];
1445 h->ndevices--;
0d96ef5f 1446 hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
edd16368
SC		 1447}
1448
1449#define SCSI3ADDR_EQ(a, b) ( \
1450 (a)[7] == (b)[7] && \
1451 (a)[6] == (b)[6] && \
1452 (a)[5] == (b)[5] && \
1453 (a)[4] == (b)[4] && \
1454 (a)[3] == (b)[3] && \
1455 (a)[2] == (b)[2] && \
1456 (a)[1] == (b)[1] && \
1457 (a)[0] == (b)[0])
1458
1459static void fixup_botched_add(struct ctlr_info *h,
1460 struct hpsa_scsi_dev_t *added)
1461{
1462 /* called when scsi_add_device fails in order to re-adjust
1463 * h->dev[] to match the mid layer's view.
1464 */
1465 unsigned long flags;
1466 int i, j;
1467
1468 spin_lock_irqsave(&h->lock, flags);
1469 for (i = 0; i < h->ndevices; i++) {
1470 if (h->dev[i] == added) {
1471 for (j = i; j < h->ndevices-1; j++)
1472 h->dev[j] = h->dev[j+1];
1473 h->ndevices--;
1474 break;
1475 }
1476 }
1477 spin_unlock_irqrestore(&h->lock, flags);
1478 kfree(added);
1479}
1480
1481static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
1482 struct hpsa_scsi_dev_t *dev2)
1483{
edd16368
SC		 1484 /* we compare everything except lun and target as these
1485 * are not yet assigned. Compare parts likely
1486 * to differ first
1487 */
1488 if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
1489 sizeof(dev1->scsi3addr)) != 0)
1490 return 0;
1491 if (memcmp(dev1->device_id, dev2->device_id,
1492 sizeof(dev1->device_id)) != 0)
1493 return 0;
1494 if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
1495 return 0;
1496 if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
1497 return 0;
edd16368
SC		 1498 if (dev1->devtype != dev2->devtype)
1499 return 0;
edd16368
SC		 1500 if (dev1->bus != dev2->bus)
1501 return 0;
1502 return 1;
1503}
1504
bd9244f7
ST		 1505static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
1506 struct hpsa_scsi_dev_t *dev2)
1507{
1508 /* Device attributes that can change, but don't mean
1509 * that the device is a different device, nor that the OS
1510 * needs to be told anything about the change.
1511 */
1512 if (dev1->raid_level != dev2->raid_level)
1513 return 1;
250fb125
SC		 1514 if (dev1->offload_config != dev2->offload_config)
1515 return 1;
b2582a65 1516 if (dev1->offload_to_be_enabled != dev2->offload_to_be_enabled)
250fb125 1517 return 1;
93849508
DB		 1518 if (!is_logical_dev_addr_mode(dev1->scsi3addr))
1519 if (dev1->queue_depth != dev2->queue_depth)
1520 return 1;
b2582a65
DB		 1521 /*
1522 * This can happen for dual domain devices. An active
1523 * path change causes the ioaccel handle to change
1524 *
1525 * for example note the handle differences between p0 and p1
1526 * Device WWN ,WWN hash,Handle
1527 * D016 p0|0x3 [02]P2E:01:01,0x5000C5005FC4DACA,0x9B5616,0x01030003
1528 * p1 0x5000C5005FC4DAC9,0x6798C0,0x00040004
1529 */
1530 if (dev1->ioaccel_handle != dev2->ioaccel_handle)
1531 return 1;
bd9244f7
ST		 1532 return 0;
1533}
1534
edd16368
SC		 1535/* Find needle in haystack. If exact match found, return DEVICE_SAME,
1536 * and return needle location in *index. If scsi3addr matches, but not
1537 * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
bd9244f7
ST		 1538 * location in *index.
1539 * In the case of a minor device attribute change, such as RAID level, just
1540 * return DEVICE_UPDATED, along with the updated device's location in index.
1541 * If needle not found, return DEVICE_NOT_FOUND.
edd16368
SC		 1542 */
1543static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
1544 struct hpsa_scsi_dev_t *haystack[], int haystack_size,
1545 int *index)
1546{
1547 int i;
1548#define DEVICE_NOT_FOUND 0
1549#define DEVICE_CHANGED 1
1550#define DEVICE_SAME 2
bd9244f7 1551#define DEVICE_UPDATED 3
1d33d85d
DB		 1552 if (needle == NULL)
1553 return DEVICE_NOT_FOUND;
1554
edd16368 1555 for (i = 0; i < haystack_size; i++) {
23231048
SC		 1556 if (haystack[i] == NULL) /* previously removed. */
1557 continue;
edd16368
SC		 1558 if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
1559 *index = i;
bd9244f7
ST		 1560 if (device_is_the_same(needle, haystack[i])) {
1561 if (device_updated(needle, haystack[i]))
1562 return DEVICE_UPDATED;
edd16368 1563 return DEVICE_SAME;
bd9244f7 1564 } else {
9846590e
SC		 1565 /* Keep offline devices offline */
1566 if (needle->volume_offline)
1567 return DEVICE_NOT_FOUND;
edd16368 1568 return DEVICE_CHANGED;
bd9244f7 1569 }
edd16368
SC		 1570 }
1571 }
1572 *index = -1;
1573 return DEVICE_NOT_FOUND;
1574}
1575
9846590e
SC		 1576static void hpsa_monitor_offline_device(struct ctlr_info *h,
1577 unsigned char scsi3addr[])
1578{
1579 struct offline_device_entry *device;
1580 unsigned long flags;
1581
1582 /* Check to see if device is already on the list */
1583 spin_lock_irqsave(&h->offline_device_lock, flags);
1584 list_for_each_entry(device, &h->offline_device_list, offline_list) {
1585 if (memcmp(device->scsi3addr, scsi3addr,
1586 sizeof(device->scsi3addr)) == 0) {
1587 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1588 return;
1589 }
1590 }
1591 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1592
1593 /* Device is not on the list, add it. */
1594 device = kmalloc(sizeof(*device), GFP_KERNEL);
7e8a9486 1595 if (!device)
9846590e 1596 return;
7e8a9486 1597
9846590e
SC		 1598 memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
1599 spin_lock_irqsave(&h->offline_device_lock, flags);
1600 list_add_tail(&device->offline_list, &h->offline_device_list);
1601 spin_unlock_irqrestore(&h->offline_device_lock, flags);
1602}
1603
1604/* Print a message explaining various offline volume states */
1605static void hpsa_show_volume_status(struct ctlr_info *h,
1606 struct hpsa_scsi_dev_t *sd)
1607{
1608 if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
1609 dev_info(&h->pdev->dev,
1610 "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
1611 h->scsi_host->host_no,
1612 sd->bus, sd->target, sd->lun);
1613 switch (sd->volume_offline) {
1614 case HPSA_LV_OK:
1615 break;
1616 case HPSA_LV_UNDERGOING_ERASE:
1617 dev_info(&h->pdev->dev,
1618 "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
1619 h->scsi_host->host_no,
1620 sd->bus, sd->target, sd->lun);
1621 break;
5ca01204
SB		 1622 case HPSA_LV_NOT_AVAILABLE:
1623 dev_info(&h->pdev->dev,
1624 "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
1625 h->scsi_host->host_no,
1626 sd->bus, sd->target, sd->lun);
1627 break;
9846590e
SC		 1628 case HPSA_LV_UNDERGOING_RPI:
1629 dev_info(&h->pdev->dev,
5ca01204 1630 "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
9846590e
SC		 1631 h->scsi_host->host_no,
1632 sd->bus, sd->target, sd->lun);
1633 break;
1634 case HPSA_LV_PENDING_RPI:
1635 dev_info(&h->pdev->dev,
5ca01204
SB		 1636 "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
1637 h->scsi_host->host_no,
1638 sd->bus, sd->target, sd->lun);
9846590e
SC		 1639 break;
1640 case HPSA_LV_ENCRYPTED_NO_KEY:
1641 dev_info(&h->pdev->dev,
1642 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
1643 h->scsi_host->host_no,
1644 sd->bus, sd->target, sd->lun);
1645 break;
1646 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
1647 dev_info(&h->pdev->dev,
1648 "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
1649 h->scsi_host->host_no,
1650 sd->bus, sd->target, sd->lun);
1651 break;
1652 case HPSA_LV_UNDERGOING_ENCRYPTION:
1653 dev_info(&h->pdev->dev,
1654 "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
1655 h->scsi_host->host_no,
1656 sd->bus, sd->target, sd->lun);
1657 break;
1658 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
1659 dev_info(&h->pdev->dev,
1660 "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
1661 h->scsi_host->host_no,
1662 sd->bus, sd->target, sd->lun);
1663 break;
1664 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
1665 dev_info(&h->pdev->dev,
1666 "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
1667 h->scsi_host->host_no,
1668 sd->bus, sd->target, sd->lun);
1669 break;
1670 case HPSA_LV_PENDING_ENCRYPTION:
1671 dev_info(&h->pdev->dev,
1672 "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
1673 h->scsi_host->host_no,
1674 sd->bus, sd->target, sd->lun);
1675 break;
1676 case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
1677 dev_info(&h->pdev->dev,
1678 "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
1679 h->scsi_host->host_no,
1680 sd->bus, sd->target, sd->lun);
1681 break;
1682 }
1683}
1684
03383736
DB		 1685/*
1686 * Figure the list of physical drive pointers for a logical drive with
1687 * raid offload configured.
1688 */
1689static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
1690 struct hpsa_scsi_dev_t *dev[], int ndevices,
1691 struct hpsa_scsi_dev_t *logical_drive)
1692{
1693 struct raid_map_data *map = &logical_drive->raid_map;
1694 struct raid_map_disk_data *dd = &map->data[0];
1695 int i, j;
1696 int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
1697 le16_to_cpu(map->metadata_disks_per_row);
1698 int nraid_map_entries = le16_to_cpu(map->row_cnt) *
1699 le16_to_cpu(map->layout_map_count) *
1700 total_disks_per_row;
1701 int nphys_disk = le16_to_cpu(map->layout_map_count) *
1702 total_disks_per_row;
1703 int qdepth;
1704
1705 if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
1706 nraid_map_entries = RAID_MAP_MAX_ENTRIES;
1707
d604f533
WS		 1708 logical_drive->nphysical_disks = nraid_map_entries;
1709
03383736
DB		 1710 qdepth = 0;
1711 for (i = 0; i < nraid_map_entries; i++) {
1712 logical_drive->phys_disk[i] = NULL;
1713 if (!logical_drive->offload_config)
1714 continue;
1715 for (j = 0; j < ndevices; j++) {
1d33d85d
DB		 1716 if (dev[j] == NULL)
1717 continue;
ff615f06
PK		 1718 if (dev[j]->devtype != TYPE_DISK &&
1719 dev[j]->devtype != TYPE_ZBC)
af15ed36 1720 continue;
f3f01730 1721 if (is_logical_device(dev[j]))
03383736
DB		 1722 continue;
1723 if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
1724 continue;
1725
1726 logical_drive->phys_disk[i] = dev[j];
1727 if (i < nphys_disk)
1728 qdepth = min(h->nr_cmds, qdepth +
1729 logical_drive->phys_disk[i]->queue_depth);
1730 break;
1731 }
1732
1733 /*
1734 * This can happen if a physical drive is removed and
1735 * the logical drive is degraded. In that case, the RAID
1736 * map data will refer to a physical disk which isn't actually
1737 * present. And in that case offload_enabled should already
1738 * be 0, but we'll turn it off here just in case
1739 */
1740 if (!logical_drive->phys_disk[i]) {
b2582a65
DB		 1741 dev_warn(&h->pdev->dev,
1742 "%s: [%d:%d:%d:%d] A phys disk component of LV is missing, turning off offload_enabled for LV.\n",
1743 __func__,
1744 h->scsi_host->host_no, logical_drive->bus,
1745 logical_drive->target, logical_drive->lun);
03383736 1746 logical_drive->offload_enabled = 0;
41ce4c35
SC		 1747 logical_drive->offload_to_be_enabled = 0;
1748 logical_drive->queue_depth = 8;
03383736
DB		 1749 }
1750 }
1751 if (nraid_map_entries)
1752 /*
1753 * This is correct for reads, too high for full stripe writes,
1754 * way too high for partial stripe writes
1755 */
1756 logical_drive->queue_depth = qdepth;
2c5fc363
DB		 1757 else {
1758 if (logical_drive->external)
1759 logical_drive->queue_depth = EXTERNAL_QD;
1760 else
1761 logical_drive->queue_depth = h->nr_cmds;
1762 }
03383736
DB		 1763}
1764
1765static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
1766 struct hpsa_scsi_dev_t *dev[], int ndevices)
1767{
1768 int i;
1769
1770 for (i = 0; i < ndevices; i++) {
1d33d85d
DB		 1771 if (dev[i] == NULL)
1772 continue;
ff615f06
PK		 1773 if (dev[i]->devtype != TYPE_DISK &&
1774 dev[i]->devtype != TYPE_ZBC)
af15ed36 1775 continue;
f3f01730 1776 if (!is_logical_device(dev[i]))
03383736 1777 continue;
41ce4c35
SC		 1778
1779 /*
1780 * If offload is currently enabled, the RAID map and
1781 * phys_disk[] assignment *better* not be changing
b2582a65
DB		 1782 * because we would be changing ioaccel phsy_disk[] pointers
1783 * on a ioaccel volume processing I/O requests.
1784 *
1785 * If an ioaccel volume status changed, initially because it was
1786 * re-configured and thus underwent a transformation, or
1787 * a drive failed, we would have received a state change
1788 * request and ioaccel should have been turned off. When the
1789 * transformation completes, we get another state change
1790 * request to turn ioaccel back on. In this case, we need
1791 * to update the ioaccel information.
1792 *
1793 * Thus: If it is not currently enabled, but will be after
1794 * the scan completes, make sure the ioaccel pointers
1795 * are up to date.
41ce4c35 1796 */
41ce4c35 1797
b2582a65
DB		 1798 if (!dev[i]->offload_enabled && dev[i]->offload_to_be_enabled)
1799 hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
03383736
DB		 1800 }
1801}
1802
096ccff4
KB		 1803static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
1804{
1805 int rc = 0;
1806
1807 if (!h->scsi_host)
1808 return 1;
1809
d04e62b9
KB		 1810 if (is_logical_device(device)) /* RAID */
1811 rc = scsi_add_device(h->scsi_host, device->bus,
096ccff4 1812 device->target, device->lun);
d04e62b9
KB		 1813 else /* HBA */
1814 rc = hpsa_add_sas_device(h->sas_host, device);
1815
096ccff4
KB		 1816 return rc;
1817}
1818
ba74fdc4
DB		 1819static int hpsa_find_outstanding_commands_for_dev(struct ctlr_info *h,
1820 struct hpsa_scsi_dev_t *dev)
1821{
1822 int i;
1823 int count = 0;
1824
1825 for (i = 0; i < h->nr_cmds; i++) {
1826 struct CommandList *c = h->cmd_pool + i;
1827 int refcount = atomic_inc_return(&c->refcount);
1828
1829 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev,
1830 dev->scsi3addr)) {
1831 unsigned long flags;
1832
1833 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
1834 if (!hpsa_is_cmd_idle(c))
1835 ++count;
1836 spin_unlock_irqrestore(&h->lock, flags);
1837 }
1838
1839 cmd_free(h, c);
1840 }
1841
1842 return count;
1843}
1844
1845static void hpsa_wait_for_outstanding_commands_for_dev(struct ctlr_info *h,
1846 struct hpsa_scsi_dev_t *device)
1847{
1848 int cmds = 0;
1849 int waits = 0;
1850
1851 while (1) {
1852 cmds = hpsa_find_outstanding_commands_for_dev(h, device);
1853 if (cmds == 0)
1854 break;
1855 if (++waits > 20)
1856 break;
9211a07f
DB		 1857 msleep(1000);
1858 }
1859
1860 if (waits > 20)
ba74fdc4
DB		 1861 dev_warn(&h->pdev->dev,
1862 "%s: removing device with %d outstanding commands!\n",
1863 __func__, cmds);
ba74fdc4
DB		 1864}
1865
096ccff4
KB		 1866static void hpsa_remove_device(struct ctlr_info *h,
1867 struct hpsa_scsi_dev_t *device)
1868{
1869 struct scsi_device *sdev = NULL;
1870
1871 if (!h->scsi_host)
1872 return;
1873
0ff365f5
DB		 1874 /*
1875 * Allow for commands to drain
1876 */
1877 device->removed = 1;
1878 hpsa_wait_for_outstanding_commands_for_dev(h, device);
1879
d04e62b9
KB		 1880 if (is_logical_device(device)) { /* RAID */
1881 sdev = scsi_device_lookup(h->scsi_host, device->bus,
096ccff4 1882 device->target, device->lun);
d04e62b9
KB		 1883 if (sdev) {
1884 scsi_remove_device(sdev);
1885 scsi_device_put(sdev);
1886 } else {
1887 /*
1888 * We don't expect to get here. Future commands
1889 * to this device will get a selection timeout as
1890 * if the device were gone.
1891 */
1892 hpsa_show_dev_msg(KERN_WARNING, h, device,
096ccff4 1893 "didn't find device for removal.");
d04e62b9 1894 }
ba74fdc4
DB		 1895 } else { /* HBA */
1896
d04e62b9 1897 hpsa_remove_sas_device(device);
ba74fdc4 1898 }
096ccff4
KB		 1899}
1900
8aa60681 1901static void adjust_hpsa_scsi_table(struct ctlr_info *h,
edd16368
SC		 1902 struct hpsa_scsi_dev_t *sd[], int nsds)
1903{
1904 /* sd contains scsi3 addresses and devtypes, and inquiry
1905 * data. This function takes what's in sd to be the current
1906 * reality and updates h->dev[] to reflect that reality.
1907 */
1908 int i, entry, device_change, changes = 0;
1909 struct hpsa_scsi_dev_t *csd;
1910 unsigned long flags;
1911 struct hpsa_scsi_dev_t **added, **removed;
1912 int nadded, nremoved;
edd16368 1913
da03ded0
DB		 1914 /*
1915 * A reset can cause a device status to change
1916 * re-schedule the scan to see what happened.
1917 */
c59d04f3 1918 spin_lock_irqsave(&h->reset_lock, flags);
da03ded0
DB		 1919 if (h->reset_in_progress) {
1920 h->drv_req_rescan = 1;
c59d04f3 1921 spin_unlock_irqrestore(&h->reset_lock, flags);
da03ded0
DB		 1922 return;
1923 }
c59d04f3 1924 spin_unlock_irqrestore(&h->reset_lock, flags);
edd16368 1925
6396bb22
KC		 1926 added = kcalloc(HPSA_MAX_DEVICES, sizeof(*added), GFP_KERNEL);
1927 removed = kcalloc(HPSA_MAX_DEVICES, sizeof(*removed), GFP_KERNEL);
edd16368
SC		 1928
1929 if (!added || !removed) {
1930 dev_warn(&h->pdev->dev, "out of memory in "
1931 "adjust_hpsa_scsi_table\n");
1932 goto free_and_out;
1933 }
1934
1935 spin_lock_irqsave(&h->devlock, flags);
1936
1937 /* find any devices in h->dev[] that are not in
1938 * sd[] and remove them from h->dev[], and for any
1939 * devices which have changed, remove the old device
1940 * info and add the new device info.
bd9244f7
ST		 1941 * If minor device attributes change, just update
1942 * the existing device structure.
edd16368
SC		 1943 */
1944 i = 0;
1945 nremoved = 0;
1946 nadded = 0;
1947 while (i < h->ndevices) {
1948 csd = h->dev[i];
1949 device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
1950 if (device_change == DEVICE_NOT_FOUND) {
1951 changes++;
8aa60681 1952 hpsa_scsi_remove_entry(h, i, removed, &nremoved);
edd16368
SC		 1953 continue; /* remove ^^^, hence i not incremented */
1954 } else if (device_change == DEVICE_CHANGED) {
1955 changes++;
8aa60681 1956 hpsa_scsi_replace_entry(h, i, sd[entry],
2a8ccf31 1957 added, &nadded, removed, &nremoved);
c7f172dc
SC		 1958 /* Set it to NULL to prevent it from being freed
1959 * at the bottom of hpsa_update_scsi_devices()
1960 */
1961 sd[entry] = NULL;
bd9244f7 1962 } else if (device_change == DEVICE_UPDATED) {
8aa60681 1963 hpsa_scsi_update_entry(h, i, sd[entry]);
edd16368
SC		 1964 }
1965 i++;
1966 }
1967
1968 /* Now, make sure every device listed in sd[] is also
1969 * listed in h->dev[], adding them if they aren't found
1970 */
1971
1972 for (i = 0; i < nsds; i++) {
1973 if (!sd[i]) /* if already added above. */
1974 continue;
9846590e
SC		 1975
1976 /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
1977 * as the SCSI mid-layer does not handle such devices well.
1978 * It relentlessly loops sending TUR at 3Hz, then READ(10)
1979 * at 160Hz, and prevents the system from coming up.
1980 */
1981 if (sd[i]->volume_offline) {
1982 hpsa_show_volume_status(h, sd[i]);
0d96ef5f 1983 hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
9846590e
SC		 1984 continue;
1985 }
1986
edd16368
SC		 1987 device_change = hpsa_scsi_find_entry(sd[i], h->dev,
1988 h->ndevices, &entry);
1989 if (device_change == DEVICE_NOT_FOUND) {
1990 changes++;
8aa60681 1991 if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
edd16368
SC		 1992 break;
1993 sd[i] = NULL; /* prevent from being freed later. */
1994 } else if (device_change == DEVICE_CHANGED) {
1995 /* should never happen... */
1996 changes++;
1997 dev_warn(&h->pdev->dev,
1998 "device unexpectedly changed.\n");
1999 /* but if it does happen, we just ignore that device */
2000 }
2001 }
41ce4c35
SC		 2002 hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
2003
b2582a65
DB		 2004 /*
2005 * Now that h->dev[]->phys_disk[] is coherent, we can enable
41ce4c35 2006 * any logical drives that need it enabled.
b2582a65
DB		 2007 *
2008 * The raid map should be current by now.
2009 *
2010 * We are updating the device list used for I/O requests.
41ce4c35 2011 */
1d33d85d
DB		 2012 for (i = 0; i < h->ndevices; i++) {
2013 if (h->dev[i] == NULL)
2014 continue;
41ce4c35 2015 h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
1d33d85d 2016 }
41ce4c35 2017
edd16368
SC		 2018 spin_unlock_irqrestore(&h->devlock, flags);
2019
9846590e
SC		 2020 /* Monitor devices which are in one of several NOT READY states to be
2021 * brought online later. This must be done without holding h->devlock,
2022 * so don't touch h->dev[]
2023 */
2024 for (i = 0; i < nsds; i++) {
2025 if (!sd[i]) /* if already added above. */
2026 continue;
2027 if (sd[i]->volume_offline)
2028 hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
2029 }
2030
edd16368
SC		 2031 /* Don't notify scsi mid layer of any changes the first time through
2032 * (or if there are no changes) scsi_scan_host will do it later the
2033 * first time through.
2034 */
8aa60681 2035 if (!changes)
edd16368
SC		 2036 goto free_and_out;
2037
edd16368
SC		 2038 /* Notify scsi mid layer of any removed devices */
2039 for (i = 0; i < nremoved; i++) {
1d33d85d
DB		 2040 if (removed[i] == NULL)
2041 continue;
096ccff4
KB		 2042 if (removed[i]->expose_device)
2043 hpsa_remove_device(h, removed[i]);
edd16368
SC		 2044 kfree(removed[i]);
2045 removed[i] = NULL;
2046 }
2047
2048 /* Notify scsi mid layer of any added devices */
2049 for (i = 0; i < nadded; i++) {
096ccff4
KB		 2050 int rc = 0;
2051
1d33d85d
DB		 2052 if (added[i] == NULL)
2053 continue;
2a168208 2054 if (!(added[i]->expose_device))
41ce4c35 2055 continue;
096ccff4
KB		 2056 rc = hpsa_add_device(h, added[i]);
2057 if (!rc)
edd16368 2058 continue;
096ccff4
KB		 2059 dev_warn(&h->pdev->dev,
2060 "addition failed %d, device not added.", rc);
edd16368
SC		 2061 /* now we have to remove it from h->dev,
2062 * since it didn't get added to scsi mid layer
2063 */
2064 fixup_botched_add(h, added[i]);
853633e8 2065 h->drv_req_rescan = 1;
edd16368
SC		 2066 }
2067
2068free_and_out:
2069 kfree(added);
2070 kfree(removed);
edd16368
SC		 2071}
2072
2073/*
9e03aa2f 2074 * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
edd16368
SC		 2075 * Assume's h->devlock is held.
2076 */
2077static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
2078 int bus, int target, int lun)
2079{
2080 int i;
2081 struct hpsa_scsi_dev_t *sd;
2082
2083 for (i = 0; i < h->ndevices; i++) {
2084 sd = h->dev[i];
2085 if (sd->bus == bus && sd->target == target && sd->lun == lun)
2086 return sd;
2087 }
2088 return NULL;
2089}
2090
edd16368
SC		 2091static int hpsa_slave_alloc(struct scsi_device *sdev)
2092{
7630b3a5 2093 struct hpsa_scsi_dev_t *sd = NULL;
edd16368
SC		 2094 unsigned long flags;
2095 struct ctlr_info *h;
2096
2097 h = sdev_to_hba(sdev);
2098 spin_lock_irqsave(&h->devlock, flags);
d04e62b9
KB		 2099 if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) {
2100 struct scsi_target *starget;
2101 struct sas_rphy *rphy;
2102
2103 starget = scsi_target(sdev);
2104 rphy = target_to_rphy(starget);
2105 sd = hpsa_find_device_by_sas_rphy(h, rphy);
2106 if (sd) {
2107 sd->target = sdev_id(sdev);
2108 sd->lun = sdev->lun;
2109 }
7630b3a5
HR		 2110 }
2111 if (!sd)
d04e62b9
KB		 2112 sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
2113 sdev_id(sdev), sdev->lun);
2114
2115 if (sd && sd->expose_device) {
03383736 2116 atomic_set(&sd->ioaccel_cmds_out, 0);
d04e62b9 2117 sdev->hostdata = sd;
41ce4c35
SC		 2118 } else
2119 sdev->hostdata = NULL;
edd16368
SC		 2120 spin_unlock_irqrestore(&h->devlock, flags);
2121 return 0;
2122}
2123
41ce4c35
SC		 2124/* configure scsi device based on internal per-device structure */
2125static int hpsa_slave_configure(struct scsi_device *sdev)
2126{
2127 struct hpsa_scsi_dev_t *sd;
2128 int queue_depth;
2129
2130 sd = sdev->hostdata;
2a168208 2131 sdev->no_uld_attach = !sd || !sd->expose_device;
41ce4c35 2132
5086435e
DB		 2133 if (sd) {
2134 if (sd->external)
2135 queue_depth = EXTERNAL_QD;
2136 else
2137 queue_depth = sd->queue_depth != 0 ?
2138 sd->queue_depth : sdev->host->can_queue;
2139 } else
41ce4c35
SC		 2140 queue_depth = sdev->host->can_queue;
2141
2142 scsi_change_queue_depth(sdev, queue_depth);
2143
2144 return 0;
2145}
2146
edd16368
SC		 2147static void hpsa_slave_destroy(struct scsi_device *sdev)
2148{
bcc44255 2149 /* nothing to do. */
edd16368
SC		 2150}
2151
d9a729f3
WS		 2152static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
2153{
2154 int i;
2155
2156 if (!h->ioaccel2_cmd_sg_list)
2157 return;
2158 for (i = 0; i < h->nr_cmds; i++) {
2159 kfree(h->ioaccel2_cmd_sg_list[i]);
2160 h->ioaccel2_cmd_sg_list[i] = NULL;
2161 }
2162 kfree(h->ioaccel2_cmd_sg_list);
2163 h->ioaccel2_cmd_sg_list = NULL;
2164}
2165
2166static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
2167{
2168 int i;
2169
2170 if (h->chainsize <= 0)
2171 return 0;
2172
2173 h->ioaccel2_cmd_sg_list =
6396bb22 2174 kcalloc(h->nr_cmds, sizeof(*h->ioaccel2_cmd_sg_list),
d9a729f3
WS		 2175 GFP_KERNEL);
2176 if (!h->ioaccel2_cmd_sg_list)
2177 return -ENOMEM;
2178 for (i = 0; i < h->nr_cmds; i++) {
2179 h->ioaccel2_cmd_sg_list[i] =
6da2ec56
KC		 2180 kmalloc_array(h->maxsgentries,
2181 sizeof(*h->ioaccel2_cmd_sg_list[i]),
2182 GFP_KERNEL);
d9a729f3
WS		 2183 if (!h->ioaccel2_cmd_sg_list[i])
2184 goto clean;
2185 }
2186 return 0;
2187
2188clean:
2189 hpsa_free_ioaccel2_sg_chain_blocks(h);
2190 return -ENOMEM;
2191}
2192
33a2ffce
SC		 2193static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
2194{
2195 int i;
2196
2197 if (!h->cmd_sg_list)
2198 return;
2199 for (i = 0; i < h->nr_cmds; i++) {
2200 kfree(h->cmd_sg_list[i]);
2201 h->cmd_sg_list[i] = NULL;
2202 }
2203 kfree(h->cmd_sg_list);
2204 h->cmd_sg_list = NULL;
2205}
2206
105a3dbc 2207static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
33a2ffce
SC		 2208{
2209 int i;
2210
2211 if (h->chainsize <= 0)
2212 return 0;
2213
6396bb22
KC		 2214 h->cmd_sg_list = kcalloc(h->nr_cmds, sizeof(*h->cmd_sg_list),
2215 GFP_KERNEL);
7e8a9486 2216 if (!h->cmd_sg_list)
33a2ffce 2217 return -ENOMEM;
7e8a9486 2218
33a2ffce 2219 for (i = 0; i < h->nr_cmds; i++) {
6da2ec56
KC		 2220 h->cmd_sg_list[i] = kmalloc_array(h->chainsize,
2221 sizeof(*h->cmd_sg_list[i]),
2222 GFP_KERNEL);
7e8a9486 2223 if (!h->cmd_sg_list[i])
33a2ffce 2224 goto clean;
7e8a9486 2225
33a2ffce
SC		 2226 }
2227 return 0;
2228
2229clean:
2230 hpsa_free_sg_chain_blocks(h);
2231 return -ENOMEM;
2232}
2233
d9a729f3
WS		 2234static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
2235 struct io_accel2_cmd *cp, struct CommandList *c)
2236{
2237 struct ioaccel2_sg_element *chain_block;
2238 u64 temp64;
2239 u32 chain_size;
2240
2241 chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
a736e9b6 2242 chain_size = le32_to_cpu(cp->sg[0].length);
8bc8f47e
CH		 2243 temp64 = dma_map_single(&h->pdev->dev, chain_block, chain_size,
2244 DMA_TO_DEVICE);
d9a729f3
WS		 2245 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2246 /* prevent subsequent unmapping */
2247 cp->sg->address = 0;
2248 return -1;
2249 }
2250 cp->sg->address = cpu_to_le64(temp64);
2251 return 0;
2252}
2253
2254static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
2255 struct io_accel2_cmd *cp)
2256{
2257 struct ioaccel2_sg_element *chain_sg;
2258 u64 temp64;
2259 u32 chain_size;
2260
2261 chain_sg = cp->sg;
2262 temp64 = le64_to_cpu(chain_sg->address);
a736e9b6 2263 chain_size = le32_to_cpu(cp->sg[0].length);
8bc8f47e 2264 dma_unmap_single(&h->pdev->dev, temp64, chain_size, DMA_TO_DEVICE);
d9a729f3
WS		 2265}
2266
e2bea6df 2267static int hpsa_map_sg_chain_block(struct ctlr_info *h,
33a2ffce
SC		 2268 struct CommandList *c)
2269{
2270 struct SGDescriptor *chain_sg, *chain_block;
2271 u64 temp64;
50a0decf 2272 u32 chain_len;
33a2ffce
SC		 2273
2274 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
2275 chain_block = h->cmd_sg_list[c->cmdindex];
50a0decf
SC		 2276 chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
2277 chain_len = sizeof(*chain_sg) *
2b08b3e9 2278 (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
50a0decf 2279 chain_sg->Len = cpu_to_le32(chain_len);
8bc8f47e
CH		 2280 temp64 = dma_map_single(&h->pdev->dev, chain_block, chain_len,
2281 DMA_TO_DEVICE);
e2bea6df
SC		 2282 if (dma_mapping_error(&h->pdev->dev, temp64)) {
2283 /* prevent subsequent unmapping */
50a0decf 2284 chain_sg->Addr = cpu_to_le64(0);
e2bea6df
SC		 2285 return -1;
2286 }
50a0decf 2287 chain_sg->Addr = cpu_to_le64(temp64);
e2bea6df 2288 return 0;
33a2ffce
SC		 2289}
2290
2291static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
2292 struct CommandList *c)
2293{
2294 struct SGDescriptor *chain_sg;
33a2ffce 2295
50a0decf 2296 if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
33a2ffce
SC		 2297 return;
2298
2299 chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
8bc8f47e
CH		 2300 dma_unmap_single(&h->pdev->dev, le64_to_cpu(chain_sg->Addr),
2301 le32_to_cpu(chain_sg->Len), DMA_TO_DEVICE);
33a2ffce
SC		 2302}
2303
a09c1441
ST		 2304
2305/* Decode the various types of errors on ioaccel2 path.
2306 * Return 1 for any error that should generate a RAID path retry.
2307 * Return 0 for errors that don't require a RAID path retry.
2308 */
2309static int handle_ioaccel_mode2_error(struct ctlr_info *h,
c349775e
ST		 2310 struct CommandList *c,
2311 struct scsi_cmnd *cmd,
ba74fdc4
DB		 2312 struct io_accel2_cmd *c2,
2313 struct hpsa_scsi_dev_t *dev)
c349775e
ST		 2314{
2315 int data_len;
a09c1441 2316 int retry = 0;
c40820d5 2317 u32 ioaccel2_resid = 0;
c349775e
ST		 2318
2319 switch (c2->error_data.serv_response) {
2320 case IOACCEL2_SERV_RESPONSE_COMPLETE:
2321 switch (c2->error_data.status) {
2322 case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
2323 break;
2324 case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
ee6b1889 2325 cmd->result |= SAM_STAT_CHECK_CONDITION;
c349775e 2326 if (c2->error_data.data_present !=
ee6b1889
SC		 2327 IOACCEL2_SENSE_DATA_PRESENT) {
2328 memset(cmd->sense_buffer, 0,
2329 SCSI_SENSE_BUFFERSIZE);
c349775e 2330 break;
ee6b1889 2331 }
c349775e
ST		 2332 /* copy the sense data */
2333 data_len = c2->error_data.sense_data_len;
2334 if (data_len > SCSI_SENSE_BUFFERSIZE)
2335 data_len = SCSI_SENSE_BUFFERSIZE;
2336 if (data_len > sizeof(c2->error_data.sense_data_buff))
2337 data_len =
2338 sizeof(c2->error_data.sense_data_buff);
2339 memcpy(cmd->sense_buffer,
2340 c2->error_data.sense_data_buff, data_len);
a09c1441 2341 retry = 1;
c349775e
ST		 2342 break;
2343 case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
a09c1441 2344 retry = 1;
c349775e
ST		 2345 break;
2346 case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
a09c1441 2347 retry = 1;
c349775e
ST		 2348 break;
2349 case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
4a8da22b 2350 retry = 1;
c349775e
ST		 2351 break;
2352 case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
a09c1441 2353 retry = 1;
c349775e
ST		 2354 break;
2355 default:
a09c1441 2356 retry = 1;
c349775e
ST		 2357 break;
2358 }
2359 break;
2360 case IOACCEL2_SERV_RESPONSE_FAILURE:
c40820d5
JH		 2361 switch (c2->error_data.status) {
2362 case IOACCEL2_STATUS_SR_IO_ERROR:
2363 case IOACCEL2_STATUS_SR_IO_ABORTED:
2364 case IOACCEL2_STATUS_SR_OVERRUN:
2365 retry = 1;
2366 break;
2367 case IOACCEL2_STATUS_SR_UNDERRUN:
2368 cmd->result = (DID_OK << 16); /* host byte */
2369 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
2370 ioaccel2_resid = get_unaligned_le32(
2371 &c2->error_data.resid_cnt[0]);
2372 scsi_set_resid(cmd, ioaccel2_resid);
2373 break;
2374 case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
2375 case IOACCEL2_STATUS_SR_INVALID_DEVICE:
2376 case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
ba74fdc4
DB		 2377 /*
2378 * Did an HBA disk disappear? We will eventually
2379 * get a state change event from the controller but
2380 * in the meantime, we need to tell the OS that the
2381 * HBA disk is no longer there and stop I/O
2382 * from going down. This allows the potential re-insert
2383 * of the disk to get the same device node.
2384 */
2385 if (dev->physical_device && dev->expose_device) {
2386 cmd->result = DID_NO_CONNECT << 16;
2387 dev->removed = 1;
2388 h->drv_req_rescan = 1;
2389 dev_warn(&h->pdev->dev,
2390 "%s: device is gone!\n", __func__);
2391 } else
2392 /*
2393 * Retry by sending down the RAID path.
2394 * We will get an event from ctlr to
2395 * trigger rescan regardless.
2396 */
2397 retry = 1;
c40820d5
JH		 2398 break;
2399 default:
2400 retry = 1;
c40820d5 2401 }
c349775e
ST		 2402 break;
2403 case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
2404 break;
2405 case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
2406 break;
2407 case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
a09c1441 2408 retry = 1;
c349775e
ST		 2409 break;
2410 case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
c349775e
ST		 2411 break;
2412 default:
a09c1441 2413 retry = 1;
c349775e
ST		 2414 break;
2415 }
a09c1441
ST		 2416
2417 return retry; /* retry on raid path? */
c349775e
ST		 2418}
2419
a58e7e53
WS		 2420static void hpsa_cmd_resolve_events(struct ctlr_info *h,
2421 struct CommandList *c)
2422{
d604f533
WS		 2423 bool do_wake = false;
2424
a58e7e53 2425 /*
08ec46f6 2426 * Reset c->scsi_cmd here so that the reset handler will know
d604f533 2427 * this command has completed. Then, check to see if the handler is
a58e7e53
WS		 2428 * waiting for this command, and, if so, wake it.
2429 */
2430 c->scsi_cmd = SCSI_CMD_IDLE;
d604f533 2431 mb(); /* Declare command idle before checking for pending events. */
d604f533
WS		 2432 if (c->reset_pending) {
2433 unsigned long flags;
2434 struct hpsa_scsi_dev_t *dev;
2435
2436 /*
2437 * There appears to be a reset pending; lock the lock and
2438 * reconfirm. If so, then decrement the count of outstanding
2439 * commands and wake the reset command if this is the last one.
2440 */
2441 spin_lock_irqsave(&h->lock, flags);
2442 dev = c->reset_pending; /* Re-fetch under the lock. */
2443 if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
2444 do_wake = true;
2445 c->reset_pending = NULL;
2446 spin_unlock_irqrestore(&h->lock, flags);
2447 }
2448
2449 if (do_wake)
2450 wake_up_all(&h->event_sync_wait_queue);
a58e7e53
WS		 2451}
2452
73153fe5
WS		 2453static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
2454 struct CommandList *c)
2455{
2456 hpsa_cmd_resolve_events(h, c);
2457 cmd_tagged_free(h, c);
2458}
2459
8a0ff92c
WS		 2460static void hpsa_cmd_free_and_done(struct ctlr_info *h,
2461 struct CommandList *c, struct scsi_cmnd *cmd)
2462{
73153fe5 2463 hpsa_cmd_resolve_and_free(h, c);
d49c2077
DB		 2464 if (cmd && cmd->scsi_done)
2465 cmd->scsi_done(cmd);
8a0ff92c
WS		 2466}
2467
2468static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
2469{
2470 INIT_WORK(&c->work, hpsa_command_resubmit_worker);
2471 queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
2472}
2473
c349775e
ST		 2474static void process_ioaccel2_completion(struct ctlr_info *h,
2475 struct CommandList *c, struct scsi_cmnd *cmd,
2476 struct hpsa_scsi_dev_t *dev)
2477{
2478 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
2479
2480 /* check for good status */
2481 if (likely(c2->error_data.serv_response == 0 &&
8a0ff92c
WS		 2482 c2->error_data.status == 0))
2483 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e 2484
8a0ff92c
WS		 2485 /*
2486 * Any RAID offload error results in retry which will use
b2582a65 2487 * the normal I/O path so the controller can handle whatever is
c349775e
ST		 2488 * wrong.
2489 */
f3f01730 2490 if (is_logical_device(dev) &&
c349775e
ST		 2491 c2->error_data.serv_response ==
2492 IOACCEL2_SERV_RESPONSE_FAILURE) {
080ef1cc 2493 if (c2->error_data.status ==
064d1b1d 2494 IOACCEL2_STATUS_SR_IOACCEL_DISABLED) {
080ef1cc 2495 dev->offload_enabled = 0;
064d1b1d
DB		 2496 dev->offload_to_be_enabled = 0;
2497 }
8a0ff92c
WS		 2498
2499 return hpsa_retry_cmd(h, c);
a09c1441 2500 }
080ef1cc 2501
ba74fdc4 2502 if (handle_ioaccel_mode2_error(h, c, cmd, c2, dev))
8a0ff92c 2503 return hpsa_retry_cmd(h, c);
080ef1cc 2504
8a0ff92c 2505 return hpsa_cmd_free_and_done(h, c, cmd);
c349775e
ST		 2506}
2507
9437ac43
SC		 2508/* Returns 0 on success, < 0 otherwise. */
2509static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
2510 struct CommandList *cp)
2511{
2512 u8 tmf_status = cp->err_info->ScsiStatus;
2513
2514 switch (tmf_status) {
2515 case CISS_TMF_COMPLETE:
2516 /*
2517 * CISS_TMF_COMPLETE never happens, instead,
2518 * ei->CommandStatus == 0 for this case.
2519 */
2520 case CISS_TMF_SUCCESS:
2521 return 0;
2522 case CISS_TMF_INVALID_FRAME:
2523 case CISS_TMF_NOT_SUPPORTED:
2524 case CISS_TMF_FAILED:
2525 case CISS_TMF_WRONG_LUN:
2526 case CISS_TMF_OVERLAPPED_TAG:
2527 break;
2528 default:
2529 dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
2530 tmf_status);
2531 break;
2532 }
2533 return -tmf_status;
2534}
2535
1fb011fb 2536static void complete_scsi_command(struct CommandList *cp)
edd16368
SC		 2537{
2538 struct scsi_cmnd *cmd;
2539 struct ctlr_info *h;
2540 struct ErrorInfo *ei;
283b4a9b 2541 struct hpsa_scsi_dev_t *dev;
d9a729f3 2542 struct io_accel2_cmd *c2;
edd16368 2543
9437ac43
SC		 2544 u8 sense_key;
2545 u8 asc; /* additional sense code */
2546 u8 ascq; /* additional sense code qualifier */
db111e18 2547 unsigned long sense_data_size;
edd16368
SC		 2548
2549 ei = cp->err_info;
7fa3030c 2550 cmd = cp->scsi_cmd;
edd16368 2551 h = cp->h;
d49c2077
DB		 2552
2553 if (!cmd->device) {
2554 cmd->result = DID_NO_CONNECT << 16;
2555 return hpsa_cmd_free_and_done(h, cp, cmd);
2556 }
2557
283b4a9b 2558 dev = cmd->device->hostdata;
45e596cd
DB		 2559 if (!dev) {
2560 cmd->result = DID_NO_CONNECT << 16;
2561 return hpsa_cmd_free_and_done(h, cp, cmd);
2562 }
d9a729f3 2563 c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
edd16368
SC		 2564
2565 scsi_dma_unmap(cmd); /* undo the DMA mappings */
e1f7de0c 2566 if ((cp->cmd_type == CMD_SCSI) &&
2b08b3e9 2567 (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
33a2ffce 2568 hpsa_unmap_sg_chain_block(h, cp);
edd16368 2569
d9a729f3
WS		 2570 if ((cp->cmd_type == CMD_IOACCEL2) &&
2571 (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
2572 hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
2573
edd16368
SC		 2574 cmd->result = (DID_OK << 16); /* host byte */
2575 cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
c349775e 2576
d49c2077
DB		 2577 if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1) {
2578 if (dev->physical_device && dev->expose_device &&
2579 dev->removed) {
2580 cmd->result = DID_NO_CONNECT << 16;
2581 return hpsa_cmd_free_and_done(h, cp, cmd);
2582 }
2583 if (likely(cp->phys_disk != NULL))
2584 atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
2585 }
03383736 2586
25163bd5
WS		 2587 /*
2588 * We check for lockup status here as it may be set for
2589 * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
2590 * fail_all_oustanding_cmds()
2591 */
2592 if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
2593 /* DID_NO_CONNECT will prevent a retry */
2594 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 2595 return hpsa_cmd_free_and_done(h, cp, cmd);
25163bd5
WS		 2596 }
2597
08ec46f6 2598 if ((unlikely(hpsa_is_pending_event(cp))))
d604f533 2599 if (cp->reset_pending)
bfd7546c 2600 return hpsa_cmd_free_and_done(h, cp, cmd);
d604f533 2601
c349775e
ST		 2602 if (cp->cmd_type == CMD_IOACCEL2)
2603 return process_ioaccel2_completion(h, cp, cmd, dev);
2604
6aa4c361 2605 scsi_set_resid(cmd, ei->ResidualCnt);
8a0ff92c
WS		 2606 if (ei->CommandStatus == 0)
2607 return hpsa_cmd_free_and_done(h, cp, cmd);
6aa4c361 2608
e1f7de0c
MG		 2609 /* For I/O accelerator commands, copy over some fields to the normal
2610 * CISS header used below for error handling.
2611 */
2612 if (cp->cmd_type == CMD_IOACCEL1) {
2613 struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
2b08b3e9
DB		 2614 cp->Header.SGList = scsi_sg_count(cmd);
2615 cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
2616 cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
2617 IOACCEL1_IOFLAGS_CDBLEN_MASK;
50a0decf 2618 cp->Header.tag = c->tag;
e1f7de0c
MG		 2619 memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
2620 memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
283b4a9b
SC		 2621
2622 /* Any RAID offload error results in retry which will use
2623 * the normal I/O path so the controller can handle whatever's
2624 * wrong.
2625 */
f3f01730 2626 if (is_logical_device(dev)) {
283b4a9b
SC		 2627 if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
2628 dev->offload_enabled = 0;
d604f533 2629 return hpsa_retry_cmd(h, cp);
283b4a9b 2630 }
e1f7de0c
MG		 2631 }
2632
edd16368
SC		 2633 /* an error has occurred */
2634 switch (ei->CommandStatus) {
2635
2636 case CMD_TARGET_STATUS:
9437ac43
SC		 2637 cmd->result |= ei->ScsiStatus;
2638 /* copy the sense data */
2639 if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
2640 sense_data_size = SCSI_SENSE_BUFFERSIZE;
2641 else
2642 sense_data_size = sizeof(ei->SenseInfo);
2643 if (ei->SenseLen < sense_data_size)
2644 sense_data_size = ei->SenseLen;
2645 memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
2646 if (ei->ScsiStatus)
2647 decode_sense_data(ei->SenseInfo, sense_data_size,
2648 &sense_key, &asc, &ascq);
edd16368 2649 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
49ea45cb
DB		 2650 switch (sense_key) {
2651 case ABORTED_COMMAND:
2e311fba 2652 cmd->result |= DID_SOFT_ERROR << 16;
1d3b3609 2653 break;
49ea45cb
DB		 2654 case UNIT_ATTENTION:
2655 if (asc == 0x3F && ascq == 0x0E)
2656 h->drv_req_rescan = 1;
2657 break;
2658 case ILLEGAL_REQUEST:
2659 if (asc == 0x25 && ascq == 0x00) {
2660 dev->removed = 1;
2661 cmd->result = DID_NO_CONNECT << 16;
2662 }
2663 break;
1d3b3609 2664 }
edd16368
SC		 2665 break;
2666 }
edd16368
SC		 2667 /* Problem was not a check condition
2668 * Pass it up to the upper layers...
2669 */
2670 if (ei->ScsiStatus) {
2671 dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
2672 "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
2673 "Returning result: 0x%x\n",
2674 cp, ei->ScsiStatus,
2675 sense_key, asc, ascq,
2676 cmd->result);
2677 } else { /* scsi status is zero??? How??? */
2678 dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
2679 "Returning no connection.\n", cp),
2680
2681 /* Ordinarily, this case should never happen,
2682 * but there is a bug in some released firmware
2683 * revisions that allows it to happen if, for
2684 * example, a 4100 backplane loses power and
2685 * the tape drive is in it. We assume that
2686 * it's a fatal error of some kind because we
2687 * can't show that it wasn't. We will make it
2688 * look like selection timeout since that is
2689 * the most common reason for this to occur,
2690 * and it's severe enough.
2691 */
2692
2693 cmd->result = DID_NO_CONNECT << 16;
2694 }
2695 break;
2696
2697 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
2698 break;
2699 case CMD_DATA_OVERRUN:
f42e81e1
SC		 2700 dev_warn(&h->pdev->dev,
2701 "CDB %16phN data overrun\n", cp->Request.CDB);
edd16368
SC		 2702 break;
2703 case CMD_INVALID: {
2704 /* print_bytes(cp, sizeof(*cp), 1, 0);
2705 print_cmd(cp); */
2706 /* We get CMD_INVALID if you address a non-existent device
2707 * instead of a selection timeout (no response). You will
2708 * see this if you yank out a drive, then try to access it.
2709 * This is kind of a shame because it means that any other
2710 * CMD_INVALID (e.g. driver bug) will get interpreted as a
2711 * missing target. */
2712 cmd->result = DID_NO_CONNECT << 16;
2713 }
2714 break;
2715 case CMD_PROTOCOL_ERR:
256d0eaa 2716 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2717 dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
2718 cp->Request.CDB);
edd16368
SC		 2719 break;
2720 case CMD_HARDWARE_ERR:
2721 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2722 dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
2723 cp->Request.CDB);
edd16368
SC		 2724 break;
2725 case CMD_CONNECTION_LOST:
2726 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2727 dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
2728 cp->Request.CDB);
edd16368
SC		 2729 break;
2730 case CMD_ABORTED:
08ec46f6
DB		 2731 cmd->result = DID_ABORT << 16;
2732 break;
edd16368
SC		 2733 case CMD_ABORT_FAILED:
2734 cmd->result = DID_ERROR << 16;
f42e81e1
SC		 2735 dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
2736 cp->Request.CDB);
edd16368
SC		 2737 break;
2738 case CMD_UNSOLICITED_ABORT:
f6e76055 2739 cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
f42e81e1
SC		 2740 dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
2741 cp->Request.CDB);
edd16368
SC		 2742 break;
2743 case CMD_TIMEOUT:
2744 cmd->result = DID_TIME_OUT << 16;
f42e81e1
SC		 2745 dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
2746 cp->Request.CDB);
edd16368 2747 break;
1d5e2ed0
SC		 2748 case CMD_UNABORTABLE:
2749 cmd->result = DID_ERROR << 16;
2750 dev_warn(&h->pdev->dev, "Command unabortable\n");
2751 break;
9437ac43
SC		 2752 case CMD_TMF_STATUS:
2753 if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
2754 cmd->result = DID_ERROR << 16;
2755 break;
283b4a9b
SC		 2756 case CMD_IOACCEL_DISABLED:
2757 /* This only handles the direct pass-through case since RAID
2758 * offload is handled above. Just attempt a retry.
2759 */
2760 cmd->result = DID_SOFT_ERROR << 16;
2761 dev_warn(&h->pdev->dev,
2762 "cp %p had HP SSD Smart Path error\n", cp);
2763 break;
edd16368
SC		 2764 default:
2765 cmd->result = DID_ERROR << 16;
2766 dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
2767 cp, ei->CommandStatus);
2768 }
8a0ff92c
WS		 2769
2770 return hpsa_cmd_free_and_done(h, cp, cmd);
edd16368
SC		 2771}
2772
8bc8f47e
CH		 2773static void hpsa_pci_unmap(struct pci_dev *pdev, struct CommandList *c,
2774 int sg_used, enum dma_data_direction data_direction)
edd16368
SC		 2775{
2776 int i;
edd16368 2777
50a0decf 2778 for (i = 0; i < sg_used; i++)
8bc8f47e 2779 dma_unmap_single(&pdev->dev, le64_to_cpu(c->SG[i].Addr),
50a0decf
SC		 2780 le32_to_cpu(c->SG[i].Len),
2781 data_direction);
edd16368
SC		 2782}
2783
a2dac136 2784static int hpsa_map_one(struct pci_dev *pdev,
edd16368
SC		 2785 struct CommandList *cp,
2786 unsigned char *buf,
2787 size_t buflen,
8bc8f47e 2788 enum dma_data_direction data_direction)
edd16368 2789{
01a02ffc 2790 u64 addr64;
edd16368 2791
8bc8f47e 2792 if (buflen == 0 || data_direction == DMA_NONE) {
edd16368 2793 cp->Header.SGList = 0;
50a0decf 2794 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2795 return 0;
edd16368
SC		 2796 }
2797
8bc8f47e 2798 addr64 = dma_map_single(&pdev->dev, buf, buflen, data_direction);
eceaae18 2799 if (dma_mapping_error(&pdev->dev, addr64)) {
a2dac136 2800 /* Prevent subsequent unmap of something never mapped */
eceaae18 2801 cp->Header.SGList = 0;
50a0decf 2802 cp->Header.SGTotal = cpu_to_le16(0);
a2dac136 2803 return -1;
eceaae18 2804 }
50a0decf
SC		 2805 cp->SG[0].Addr = cpu_to_le64(addr64);
2806 cp->SG[0].Len = cpu_to_le32(buflen);
2807 cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
2808 cp->Header.SGList = 1; /* no. SGs contig in this cmd */
2809 cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
a2dac136 2810 return 0;
edd16368
SC		 2811}
2812
25163bd5
WS		 2813#define NO_TIMEOUT ((unsigned long) -1)
2814#define DEFAULT_TIMEOUT 30000 /* milliseconds */
2815static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
2816 struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
edd16368
SC		 2817{
2818 DECLARE_COMPLETION_ONSTACK(wait);
2819
2820 c->waiting = &wait;
25163bd5
WS		 2821 __enqueue_cmd_and_start_io(h, c, reply_queue);
2822 if (timeout_msecs == NO_TIMEOUT) {
2823 /* TODO: get rid of this no-timeout thing */
2824 wait_for_completion_io(&wait);
2825 return IO_OK;
2826 }
2827 if (!wait_for_completion_io_timeout(&wait,
2828 msecs_to_jiffies(timeout_msecs))) {
2829 dev_warn(&h->pdev->dev, "Command timed out.\n");
2830 return -ETIMEDOUT;
2831 }
2832 return IO_OK;
2833}
2834
2835static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
2836 int reply_queue, unsigned long timeout_msecs)
2837{
2838 if (unlikely(lockup_detected(h))) {
2839 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
2840 return IO_OK;
2841 }
2842 return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
edd16368
SC		 2843}
2844
094963da
SC		 2845static u32 lockup_detected(struct ctlr_info *h)
2846{
2847 int cpu;
2848 u32 rc, *lockup_detected;
2849
2850 cpu = get_cpu();
2851 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
2852 rc = *lockup_detected;
2853 put_cpu();
2854 return rc;
2855}
2856
9c2fc160 2857#define MAX_DRIVER_CMD_RETRIES 25
25163bd5 2858static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
8bc8f47e
CH		 2859 struct CommandList *c, enum dma_data_direction data_direction,
2860 unsigned long timeout_msecs)
edd16368 2861{
9c2fc160 2862 int backoff_time = 10, retry_count = 0;
25163bd5 2863 int rc;
edd16368
SC		 2864
2865 do {
7630abd0 2866 memset(c->err_info, 0, sizeof(*c->err_info));
25163bd5
WS		 2867 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
2868 timeout_msecs);
2869 if (rc)
2870 break;
edd16368 2871 retry_count++;
9c2fc160
SC		 2872 if (retry_count > 3) {
2873 msleep(backoff_time);
2874 if (backoff_time < 1000)
2875 backoff_time *= 2;
2876 }
852af20a 2877 } while ((check_for_unit_attention(h, c) ||
9c2fc160
SC		 2878 check_for_busy(h, c)) &&
2879 retry_count <= MAX_DRIVER_CMD_RETRIES);
edd16368 2880 hpsa_pci_unmap(h->pdev, c, 1, data_direction);
25163bd5
WS		 2881 if (retry_count > MAX_DRIVER_CMD_RETRIES)
2882 rc = -EIO;
2883 return rc;
edd16368
SC		 2884}
2885
d1e8beac
SC		 2886static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
2887 struct CommandList *c)
edd16368 2888{
d1e8beac
SC		 2889 const u8 *cdb = c->Request.CDB;
2890 const u8 *lun = c->Header.LUN.LunAddrBytes;
2891
609a70df
RV		 2892 dev_warn(&h->pdev->dev, "%s: LUN:%8phN CDB:%16phN\n",
2893 txt, lun, cdb);
d1e8beac
SC		 2894}
2895
2896static void hpsa_scsi_interpret_error(struct ctlr_info *h,
2897 struct CommandList *cp)
2898{
2899 const struct ErrorInfo *ei = cp->err_info;
edd16368 2900 struct device *d = &cp->h->pdev->dev;
9437ac43
SC		 2901 u8 sense_key, asc, ascq;
2902 int sense_len;
edd16368 2903
edd16368
SC		 2904 switch (ei->CommandStatus) {
2905 case CMD_TARGET_STATUS:
9437ac43
SC		 2906 if (ei->SenseLen > sizeof(ei->SenseInfo))
2907 sense_len = sizeof(ei->SenseInfo);
2908 else
2909 sense_len = ei->SenseLen;
2910 decode_sense_data(ei->SenseInfo, sense_len,
2911 &sense_key, &asc, &ascq);
d1e8beac
SC		 2912 hpsa_print_cmd(h, "SCSI status", cp);
2913 if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
9437ac43
SC		 2914 dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
2915 sense_key, asc, ascq);
d1e8beac 2916 else
9437ac43 2917 dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
edd16368
SC		 2918 if (ei->ScsiStatus == 0)
2919 dev_warn(d, "SCSI status is abnormally zero. "
2920 "(probably indicates selection timeout "
2921 "reported incorrectly due to a known "
2922 "firmware bug, circa July, 2001.)\n");
2923 break;
2924 case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
edd16368
SC		 2925 break;
2926 case CMD_DATA_OVERRUN:
d1e8beac 2927 hpsa_print_cmd(h, "overrun condition", cp);
edd16368
SC		 2928 break;
2929 case CMD_INVALID: {
2930 /* controller unfortunately reports SCSI passthru's
2931 * to non-existent targets as invalid commands.
2932 */
d1e8beac
SC		 2933 hpsa_print_cmd(h, "invalid command", cp);
2934 dev_warn(d, "probably means device no longer present\n");
edd16368
SC		 2935 }
2936 break;
2937 case CMD_PROTOCOL_ERR:
d1e8beac 2938 hpsa_print_cmd(h, "protocol error", cp);
edd16368
SC		 2939 break;
2940 case CMD_HARDWARE_ERR:
d1e8beac 2941 hpsa_print_cmd(h, "hardware error", cp);
edd16368
SC		 2942 break;
2943 case CMD_CONNECTION_LOST:
d1e8beac 2944 hpsa_print_cmd(h, "connection lost", cp);
edd16368
SC		 2945 break;
2946 case CMD_ABORTED:
d1e8beac 2947 hpsa_print_cmd(h, "aborted", cp);
edd16368
SC		 2948 break;
2949 case CMD_ABORT_FAILED:
d1e8beac 2950 hpsa_print_cmd(h, "abort failed", cp);
edd16368
SC		 2951 break;
2952 case CMD_UNSOLICITED_ABORT:
d1e8beac 2953 hpsa_print_cmd(h, "unsolicited abort", cp);
edd16368
SC		 2954 break;
2955 case CMD_TIMEOUT:
d1e8beac 2956 hpsa_print_cmd(h, "timed out", cp);
edd16368 2957 break;
1d5e2ed0 2958 case CMD_UNABORTABLE:
d1e8beac 2959 hpsa_print_cmd(h, "unabortable", cp);
1d5e2ed0 2960 break;
25163bd5
WS		 2961 case CMD_CTLR_LOCKUP:
2962 hpsa_print_cmd(h, "controller lockup detected", cp);
2963 break;
edd16368 2964 default:
d1e8beac
SC		 2965 hpsa_print_cmd(h, "unknown status", cp);
2966 dev_warn(d, "Unknown command status %x\n",
edd16368
SC		 2967 ei->CommandStatus);
2968 }
2969}
2970
0a7c3bb8
DB		 2971static int hpsa_do_receive_diagnostic(struct ctlr_info *h, u8 *scsi3addr,
2972 u8 page, u8 *buf, size_t bufsize)
2973{
2974 int rc = IO_OK;
2975 struct CommandList *c;
2976 struct ErrorInfo *ei;
2977
2978 c = cmd_alloc(h);
2979 if (fill_cmd(c, RECEIVE_DIAGNOSTIC, h, buf, bufsize,
2980 page, scsi3addr, TYPE_CMD)) {
2981 rc = -1;
2982 goto out;
2983 }
8bc8f47e
CH		 2984 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
2985 NO_TIMEOUT);
0a7c3bb8
DB		 2986 if (rc)
2987 goto out;
2988 ei = c->err_info;
2989 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
2990 hpsa_scsi_interpret_error(h, c);
2991 rc = -1;
2992 }
2993out:
2994 cmd_free(h, c);
2995 return rc;
2996}
2997
2998static u64 hpsa_get_enclosure_logical_identifier(struct ctlr_info *h,
2999 u8 *scsi3addr)
3000{
3001 u8 *buf;
3002 u64 sa = 0;
3003 int rc = 0;
3004
3005 buf = kzalloc(1024, GFP_KERNEL);
3006 if (!buf)
3007 return 0;
3008
3009 rc = hpsa_do_receive_diagnostic(h, scsi3addr, RECEIVE_DIAGNOSTIC,
3010 buf, 1024);
3011
3012 if (rc)
3013 goto out;
3014
3015 sa = get_unaligned_be64(buf+12);
3016
3017out:
3018 kfree(buf);
3019 return sa;
3020}
3021
edd16368 3022static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
b7bb24eb 3023 u16 page, unsigned char *buf,
edd16368
SC		 3024 unsigned char bufsize)
3025{
3026 int rc = IO_OK;
3027 struct CommandList *c;
3028 struct ErrorInfo *ei;
3029
45fcb86e 3030 c = cmd_alloc(h);
edd16368 3031
a2dac136
SC		 3032 if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
3033 page, scsi3addr, TYPE_CMD)) {
3034 rc = -1;
3035 goto out;
3036 }
8bc8f47e
CH		 3037 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
3038 NO_TIMEOUT);
25163bd5
WS		 3039 if (rc)
3040 goto out;
edd16368
SC		 3041 ei = c->err_info;
3042 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3043 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 3044 rc = -1;
3045 }
a2dac136 3046out:
45fcb86e 3047 cmd_free(h, c);
edd16368
SC		 3048 return rc;
3049}
3050
bf711ac6 3051static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
25163bd5 3052 u8 reset_type, int reply_queue)
edd16368
SC		 3053{
3054 int rc = IO_OK;
3055 struct CommandList *c;
3056 struct ErrorInfo *ei;
3057
45fcb86e 3058 c = cmd_alloc(h);
edd16368 3059
edd16368 3060
a2dac136 3061 /* fill_cmd can't fail here, no data buffer to map. */
0b9b7b6e 3062 (void) fill_cmd(c, reset_type, h, NULL, 0, 0,
bf711ac6 3063 scsi3addr, TYPE_MSG);
2ef28849 3064 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
25163bd5
WS		 3065 if (rc) {
3066 dev_warn(&h->pdev->dev, "Failed to send reset command\n");
3067 goto out;
3068 }
edd16368
SC		 3069 /* no unmap needed here because no data xfer. */
3070
3071 ei = c->err_info;
3072 if (ei->CommandStatus != 0) {
d1e8beac 3073 hpsa_scsi_interpret_error(h, c);
edd16368
SC		 3074 rc = -1;
3075 }
25163bd5 3076out:
45fcb86e 3077 cmd_free(h, c);
edd16368
SC		 3078 return rc;
3079}
3080
d604f533
WS		 3081static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
3082 struct hpsa_scsi_dev_t *dev,
3083 unsigned char *scsi3addr)
3084{
3085 int i;
3086 bool match = false;
3087 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
3088 struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
3089
3090 if (hpsa_is_cmd_idle(c))
3091 return false;
3092
3093 switch (c->cmd_type) {
3094 case CMD_SCSI:
3095 case CMD_IOCTL_PEND:
3096 match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
3097 sizeof(c->Header.LUN.LunAddrBytes));
3098 break;
3099
3100 case CMD_IOACCEL1:
3101 case CMD_IOACCEL2:
3102 if (c->phys_disk == dev) {
3103 /* HBA mode match */
3104 match = true;
3105 } else {
3106 /* Possible RAID mode -- check each phys dev. */
3107 /* FIXME: Do we need to take out a lock here? If
3108 * so, we could just call hpsa_get_pdisk_of_ioaccel2()
3109 * instead. */
3110 for (i = 0; i < dev->nphysical_disks && !match; i++) {
3111 /* FIXME: an alternate test might be
3112 *
3113 * match = dev->phys_disk[i]->ioaccel_handle
3114 * == c2->scsi_nexus; */
3115 match = dev->phys_disk[i] == c->phys_disk;
3116 }
3117 }
3118 break;
3119
3120 case IOACCEL2_TMF:
3121 for (i = 0; i < dev->nphysical_disks && !match; i++) {
3122 match = dev->phys_disk[i]->ioaccel_handle ==
3123 le32_to_cpu(ac->it_nexus);
3124 }
3125 break;
3126
3127 case 0: /* The command is in the middle of being initialized. */
3128 match = false;
3129 break;
3130
3131 default:
3132 dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
3133 c->cmd_type);
3134 BUG();
3135 }
3136
3137 return match;
3138}
3139
3140static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
3141 unsigned char *scsi3addr, u8 reset_type, int reply_queue)
3142{
3143 int i;
3144 int rc = 0;
3145
3146 /* We can really only handle one reset at a time */
3147 if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
3148 dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
3149 return -EINTR;
3150 }
3151
3152 BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
3153
3154 for (i = 0; i < h->nr_cmds; i++) {
3155 struct CommandList *c = h->cmd_pool + i;
3156 int refcount = atomic_inc_return(&c->refcount);
3157
3158 if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
3159 unsigned long flags;
3160
3161 /*
3162 * Mark the target command as having a reset pending,
3163 * then lock a lock so that the command cannot complete
3164 * while we're considering it. If the command is not
3165 * idle then count it; otherwise revoke the event.
3166 */
3167 c->reset_pending = dev;
3168 spin_lock_irqsave(&h->lock, flags); /* Implied MB */
3169 if (!hpsa_is_cmd_idle(c))
3170 atomic_inc(&dev->reset_cmds_out);
3171 else
3172 c->reset_pending = NULL;
3173 spin_unlock_irqrestore(&h->lock, flags);
3174 }
3175
3176 cmd_free(h, c);
3177 }
3178
3179 rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
3180 if (!rc)
3181 wait_event(h->event_sync_wait_queue,
3182 atomic_read(&dev->reset_cmds_out) == 0 ||
3183 lockup_detected(h));
3184
3185 if (unlikely(lockup_detected(h))) {
77678d3a
DB		 3186 dev_warn(&h->pdev->dev,
3187 "Controller lockup detected during reset wait\n");
3188 rc = -ENODEV;
3189 }
d604f533
WS		 3190
3191 if (unlikely(rc))
3192 atomic_set(&dev->reset_cmds_out, 0);
bfd7546c 3193 else
8516a2db 3194 rc = wait_for_device_to_become_ready(h, scsi3addr, 0);
d604f533
WS		 3195
3196 mutex_unlock(&h->reset_mutex);
3197 return rc;
3198}
3199
edd16368
SC		 3200static void hpsa_get_raid_level(struct ctlr_info *h,
3201 unsigned char *scsi3addr, unsigned char *raid_level)
3202{
3203 int rc;
3204 unsigned char *buf;
3205
3206 *raid_level = RAID_UNKNOWN;
3207 buf = kzalloc(64, GFP_KERNEL);
3208 if (!buf)
3209 return;
8383278d
ST		 3210
3211 if (!hpsa_vpd_page_supported(h, scsi3addr,
3212 HPSA_VPD_LV_DEVICE_GEOMETRY))
3213 goto exit;
3214
3215 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE |
3216 HPSA_VPD_LV_DEVICE_GEOMETRY, buf, 64);
3217
edd16368
SC		 3218 if (rc == 0)
3219 *raid_level = buf[8];
3220 if (*raid_level > RAID_UNKNOWN)
3221 *raid_level = RAID_UNKNOWN;
8383278d 3222exit:
edd16368
SC		 3223 kfree(buf);
3224 return;
3225}
3226
283b4a9b
SC		 3227#define HPSA_MAP_DEBUG
3228#ifdef HPSA_MAP_DEBUG
3229static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
3230 struct raid_map_data *map_buff)
3231{
3232 struct raid_map_disk_data *dd = &map_buff->data[0];
3233 int map, row, col;
3234 u16 map_cnt, row_cnt, disks_per_row;
3235
3236 if (rc != 0)
3237 return;
3238
2ba8bfc8
SC		 3239 /* Show details only if debugging has been activated. */
3240 if (h->raid_offload_debug < 2)
3241 return;
3242
283b4a9b
SC		 3243 dev_info(&h->pdev->dev, "structure_size = %u\n",
3244 le32_to_cpu(map_buff->structure_size));
3245 dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
3246 le32_to_cpu(map_buff->volume_blk_size));
3247 dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
3248 le64_to_cpu(map_buff->volume_blk_cnt));
3249 dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
3250 map_buff->phys_blk_shift);
3251 dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
3252 map_buff->parity_rotation_shift);
3253 dev_info(&h->pdev->dev, "strip_size = %u\n",
3254 le16_to_cpu(map_buff->strip_size));
3255 dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
3256 le64_to_cpu(map_buff->disk_starting_blk));
3257 dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
3258 le64_to_cpu(map_buff->disk_blk_cnt));
3259 dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
3260 le16_to_cpu(map_buff->data_disks_per_row));
3261 dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
3262 le16_to_cpu(map_buff->metadata_disks_per_row));
3263 dev_info(&h->pdev->dev, "row_cnt = %u\n",
3264 le16_to_cpu(map_buff->row_cnt));
3265 dev_info(&h->pdev->dev, "layout_map_count = %u\n",
3266 le16_to_cpu(map_buff->layout_map_count));
2b08b3e9 3267 dev_info(&h->pdev->dev, "flags = 0x%x\n",
dd0e19f3 3268 le16_to_cpu(map_buff->flags));
ba82d91b 3269 dev_info(&h->pdev->dev, "encryption = %s\n",
2b08b3e9
DB		 3270 le16_to_cpu(map_buff->flags) &
3271 RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
dd0e19f3
ST		 3272 dev_info(&h->pdev->dev, "dekindex = %u\n",
3273 le16_to_cpu(map_buff->dekindex));
283b4a9b
SC		 3274 map_cnt = le16_to_cpu(map_buff->layout_map_count);
3275 for (map = 0; map < map_cnt; map++) {
3276 dev_info(&h->pdev->dev, "Map%u:\n", map);
3277 row_cnt = le16_to_cpu(map_buff->row_cnt);
3278 for (row = 0; row < row_cnt; row++) {
3279 dev_info(&h->pdev->dev, " Row%u:\n", row);
3280 disks_per_row =
3281 le16_to_cpu(map_buff->data_disks_per_row);
3282 for (col = 0; col < disks_per_row; col++, dd++)
3283 dev_info(&h->pdev->dev,
3284 " D%02u: h=0x%04x xor=%u,%u\n",
3285 col, dd->ioaccel_handle,
3286 dd->xor_mult[0], dd->xor_mult[1]);
3287 disks_per_row =
3288 le16_to_cpu(map_buff->metadata_disks_per_row);
3289 for (col = 0; col < disks_per_row; col++, dd++)
3290 dev_info(&h->pdev->dev,
3291 " M%02u: h=0x%04x xor=%u,%u\n",
3292 col, dd->ioaccel_handle,
3293 dd->xor_mult[0], dd->xor_mult[1]);
3294 }
3295 }
3296}
3297#else
3298static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
3299 __attribute__((unused)) int rc,
3300 __attribute__((unused)) struct raid_map_data *map_buff)
3301{
3302}
3303#endif
3304
3305static int hpsa_get_raid_map(struct ctlr_info *h,
3306 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3307{
3308 int rc = 0;
3309 struct CommandList *c;
3310 struct ErrorInfo *ei;
3311
45fcb86e 3312 c = cmd_alloc(h);
bf43caf3 3313
283b4a9b
SC		 3314 if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
3315 sizeof(this_device->raid_map), 0,
3316 scsi3addr, TYPE_CMD)) {
2dd02d74
RE		 3317 dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
3318 cmd_free(h, c);
3319 return -1;
283b4a9b 3320 }
8bc8f47e
CH		 3321 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
3322 NO_TIMEOUT);
25163bd5
WS		 3323 if (rc)
3324 goto out;
283b4a9b
SC		 3325 ei = c->err_info;
3326 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3327 hpsa_scsi_interpret_error(h, c);
25163bd5
WS		 3328 rc = -1;
3329 goto out;
283b4a9b 3330 }
45fcb86e 3331 cmd_free(h, c);
283b4a9b
SC		 3332
3333 /* @todo in the future, dynamically allocate RAID map memory */
3334 if (le32_to_cpu(this_device->raid_map.structure_size) >
3335 sizeof(this_device->raid_map)) {
3336 dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
3337 rc = -1;
3338 }
3339 hpsa_debug_map_buff(h, rc, &this_device->raid_map);
3340 return rc;
25163bd5
WS		 3341out:
3342 cmd_free(h, c);
3343 return rc;
283b4a9b
SC		 3344}
3345
d04e62b9
KB		 3346static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h,
3347 unsigned char scsi3addr[], u16 bmic_device_index,
3348 struct bmic_sense_subsystem_info *buf, size_t bufsize)
3349{
3350 int rc = IO_OK;
3351 struct CommandList *c;
3352 struct ErrorInfo *ei;
3353
3354 c = cmd_alloc(h);
3355
3356 rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize,
3357 0, RAID_CTLR_LUNID, TYPE_CMD);
3358 if (rc)
3359 goto out;
3360
3361 c->Request.CDB[2] = bmic_device_index & 0xff;
3362 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3363
8bc8f47e
CH		 3364 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
3365 NO_TIMEOUT);
d04e62b9
KB		 3366 if (rc)
3367 goto out;
3368 ei = c->err_info;
3369 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3370 hpsa_scsi_interpret_error(h, c);
3371 rc = -1;
3372 }
3373out:
3374 cmd_free(h, c);
3375 return rc;
3376}
3377
66749d0d
ST		 3378static int hpsa_bmic_id_controller(struct ctlr_info *h,
3379 struct bmic_identify_controller *buf, size_t bufsize)
3380{
3381 int rc = IO_OK;
3382 struct CommandList *c;
3383 struct ErrorInfo *ei;
3384
3385 c = cmd_alloc(h);
3386
3387 rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize,
3388 0, RAID_CTLR_LUNID, TYPE_CMD);
3389 if (rc)
3390 goto out;
3391
8bc8f47e
CH		 3392 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
3393 NO_TIMEOUT);
66749d0d
ST		 3394 if (rc)
3395 goto out;
3396 ei = c->err_info;
3397 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3398 hpsa_scsi_interpret_error(h, c);
3399 rc = -1;
3400 }
3401out:
3402 cmd_free(h, c);
3403 return rc;
3404}
3405
03383736
DB		 3406static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
3407 unsigned char scsi3addr[], u16 bmic_device_index,
3408 struct bmic_identify_physical_device *buf, size_t bufsize)
3409{
3410 int rc = IO_OK;
3411 struct CommandList *c;
3412 struct ErrorInfo *ei;
3413
3414 c = cmd_alloc(h);
3415 rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
3416 0, RAID_CTLR_LUNID, TYPE_CMD);
3417 if (rc)
3418 goto out;
3419
3420 c->Request.CDB[2] = bmic_device_index & 0xff;
3421 c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
3422
8bc8f47e 3423 hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
3026ff9b 3424 NO_TIMEOUT);
03383736
DB		 3425 ei = c->err_info;
3426 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3427 hpsa_scsi_interpret_error(h, c);
3428 rc = -1;
3429 }
3430out:
3431 cmd_free(h, c);
d04e62b9 3432
03383736
DB		 3433 return rc;
3434}
3435
cca8f13b
DB		 3436/*
3437 * get enclosure information
3438 * struct ReportExtendedLUNdata *rlep - Used for BMIC drive number
3439 * struct hpsa_scsi_dev_t *encl_dev - device entry for enclosure
3440 * Uses id_physical_device to determine the box_index.
3441 */
3442static void hpsa_get_enclosure_info(struct ctlr_info *h,
3443 unsigned char *scsi3addr,
3444 struct ReportExtendedLUNdata *rlep, int rle_index,
3445 struct hpsa_scsi_dev_t *encl_dev)
3446{
3447 int rc = -1;
3448 struct CommandList *c = NULL;
3449 struct ErrorInfo *ei = NULL;
3450 struct bmic_sense_storage_box_params *bssbp = NULL;
3451 struct bmic_identify_physical_device *id_phys = NULL;
3452 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
3453 u16 bmic_device_index = 0;
3454
01d0e789 3455 encl_dev->eli =
0a7c3bb8
DB		 3456 hpsa_get_enclosure_logical_identifier(h, scsi3addr);
3457
01d0e789
DB		 3458 bmic_device_index = GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]);
3459
5ac517b8
DB		 3460 if (encl_dev->target == -1 || encl_dev->lun == -1) {
3461 rc = IO_OK;
3462 goto out;
3463 }
3464
17a9e54a
DB		 3465 if (bmic_device_index == 0xFF00 || MASKED_DEVICE(&rle->lunid[0])) {
3466 rc = IO_OK;
cca8f13b 3467 goto out;
17a9e54a 3468 }
cca8f13b
DB		 3469
3470 bssbp = kzalloc(sizeof(*bssbp), GFP_KERNEL);
3471 if (!bssbp)
3472 goto out;
3473
3474 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
3475 if (!id_phys)
3476 goto out;
3477
3478 rc = hpsa_bmic_id_physical_device(h, scsi3addr, bmic_device_index,
3479 id_phys, sizeof(*id_phys));
3480 if (rc) {
3481 dev_warn(&h->pdev->dev, "%s: id_phys failed %d bdi[0x%x]\n",
3482 __func__, encl_dev->external, bmic_device_index);
3483 goto out;
3484 }
3485
3486 c = cmd_alloc(h);
3487
3488 rc = fill_cmd(c, BMIC_SENSE_STORAGE_BOX_PARAMS, h, bssbp,
3489 sizeof(*bssbp), 0, RAID_CTLR_LUNID, TYPE_CMD);
3490
3491 if (rc)
3492 goto out;
3493
3494 if (id_phys->phys_connector[1] == 'E')
3495 c->Request.CDB[5] = id_phys->box_index;
3496 else
3497 c->Request.CDB[5] = 0;
3498
8bc8f47e 3499 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
3026ff9b 3500 NO_TIMEOUT);
cca8f13b
DB		 3501 if (rc)
3502 goto out;
3503
3504 ei = c->err_info;
3505 if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
3506 rc = -1;
3507 goto out;
3508 }
3509
3510 encl_dev->box[id_phys->active_path_number] = bssbp->phys_box_on_port;
3511 memcpy(&encl_dev->phys_connector[id_phys->active_path_number],
3512 bssbp->phys_connector, sizeof(bssbp->phys_connector));
3513
3514 rc = IO_OK;
3515out:
3516 kfree(bssbp);
3517 kfree(id_phys);
3518
3519 if (c)
3520 cmd_free(h, c);
3521
3522 if (rc != IO_OK)
3523 hpsa_show_dev_msg(KERN_INFO, h, encl_dev,
b4e9ce1c 3524 "Error, could not get enclosure information");
cca8f13b
DB		 3525}
3526
d04e62b9
KB		 3527static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h,
3528 unsigned char *scsi3addr)
3529{
3530 struct ReportExtendedLUNdata *physdev;
3531 u32 nphysicals;
3532 u64 sa = 0;
3533 int i;
3534
3535 physdev = kzalloc(sizeof(*physdev), GFP_KERNEL);
3536 if (!physdev)
3537 return 0;
3538
3539 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
3540 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
3541 kfree(physdev);
3542 return 0;
3543 }
3544 nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24;
3545
3546 for (i = 0; i < nphysicals; i++)
3547 if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) {
3548 sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]);
3549 break;
3550 }
3551
3552 kfree(physdev);
3553
3554 return sa;
3555}
3556
3557static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr,
3558 struct hpsa_scsi_dev_t *dev)
3559{
3560 int rc;
3561 u64 sa = 0;
3562
3563 if (is_hba_lunid(scsi3addr)) {
3564 struct bmic_sense_subsystem_info *ssi;
3565
3566 ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
7e8a9486 3567 if (!ssi)
d04e62b9 3568 return;
d04e62b9
KB		 3569
3570 rc = hpsa_bmic_sense_subsystem_information(h,
3571 scsi3addr, 0, ssi, sizeof(*ssi));
3572 if (rc == 0) {
3573 sa = get_unaligned_be64(ssi->primary_world_wide_id);
3574 h->sas_address = sa;
3575 }
3576
3577 kfree(ssi);
3578 } else
3579 sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr);
3580
3581 dev->sas_address = sa;
3582}
3583
4e188184
BAS		 3584static void hpsa_ext_ctrl_present(struct ctlr_info *h,
3585 struct ReportExtendedLUNdata *physdev)
3586{
3587 u32 nphysicals;
3588 int i;
3589
3590 if (h->discovery_polling)
3591 return;
3592
3593 nphysicals = (get_unaligned_be32(physdev->LUNListLength) / 24) + 1;
3594
3595 for (i = 0; i < nphysicals; i++) {
3596 if (physdev->LUN[i].device_type ==
3597 BMIC_DEVICE_TYPE_CONTROLLER
3598 && !is_hba_lunid(physdev->LUN[i].lunid)) {
3599 dev_info(&h->pdev->dev,
3600 "External controller present, activate discovery polling and disable rld caching\n");
3601 hpsa_disable_rld_caching(h);
3602 h->discovery_polling = 1;
3603 break;
3604 }
3605 }
3606}
3607
d04e62b9 3608/* Get a device id from inquiry page 0x83 */
8383278d 3609static bool hpsa_vpd_page_supported(struct ctlr_info *h,
1b70150a
SC		 3610 unsigned char scsi3addr[], u8 page)
3611{
3612 int rc;
3613 int i;
3614 int pages;
3615 unsigned char *buf, bufsize;
3616
3617 buf = kzalloc(256, GFP_KERNEL);
3618 if (!buf)
8383278d 3619 return false;
1b70150a
SC		 3620
3621 /* Get the size of the page list first */
3622 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3623 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3624 buf, HPSA_VPD_HEADER_SZ);
3625 if (rc != 0)
3626 goto exit_unsupported;
3627 pages = buf[3];
3628 if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
3629 bufsize = pages + HPSA_VPD_HEADER_SZ;
3630 else
3631 bufsize = 255;
3632
3633 /* Get the whole VPD page list */
3634 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
3635 VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
3636 buf, bufsize);
3637 if (rc != 0)
3638 goto exit_unsupported;
3639
3640 pages = buf[3];
3641 for (i = 1; i <= pages; i++)
3642 if (buf[3 + i] == page)
3643 goto exit_supported;
3644exit_unsupported:
3645 kfree(buf);
8383278d 3646 return false;
1b70150a
SC		 3647exit_supported:
3648 kfree(buf);
8383278d 3649 return true;
1b70150a
SC		 3650}
3651
b2582a65
DB		 3652/*
3653 * Called during a scan operation.
3654 * Sets ioaccel status on the new device list, not the existing device list
3655 *
3656 * The device list used during I/O will be updated later in
3657 * adjust_hpsa_scsi_table.
3658 */
283b4a9b
SC		 3659static void hpsa_get_ioaccel_status(struct ctlr_info *h,
3660 unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
3661{
3662 int rc;
3663 unsigned char *buf;
3664 u8 ioaccel_status;
3665
3666 this_device->offload_config = 0;
3667 this_device->offload_enabled = 0;
41ce4c35 3668 this_device->offload_to_be_enabled = 0;
283b4a9b
SC		 3669
3670 buf = kzalloc(64, GFP_KERNEL);
3671 if (!buf)
3672 return;
1b70150a
SC		 3673 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
3674 goto out;
283b4a9b 3675 rc = hpsa_scsi_do_inquiry(h, scsi3addr,
b7bb24eb 3676 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
283b4a9b
SC		 3677 if (rc != 0)
3678 goto out;
3679
3680#define IOACCEL_STATUS_BYTE 4
3681#define OFFLOAD_CONFIGURED_BIT 0x01
3682#define OFFLOAD_ENABLED_BIT 0x02
3683 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
3684 this_device->offload_config =
3685 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
3686 if (this_device->offload_config) {
b2582a65 3687 this_device->offload_to_be_enabled =
283b4a9b
SC		 3688 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
3689 if (hpsa_get_raid_map(h, scsi3addr, this_device))
b2582a65 3690 this_device->offload_to_be_enabled = 0;
283b4a9b 3691 }
b2582a65 3692
283b4a9b
SC		 3693out:
3694 kfree(buf);
3695 return;
3696}
3697
edd16368
SC		 3698/* Get the device id from inquiry page 0x83 */
3699static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
75d23d89 3700 unsigned char *device_id, int index, int buflen)
edd16368
SC		 3701{
3702 int rc;
3703 unsigned char *buf;
3704
8383278d
ST		 3705 /* Does controller have VPD for device id? */
3706 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_DEVICE_ID))
3707 return 1; /* not supported */
3708
edd16368
SC		 3709 buf = kzalloc(64, GFP_KERNEL);
3710 if (!buf)
a84d794d 3711 return -ENOMEM;
8383278d
ST		 3712
3713 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE |
3714 HPSA_VPD_LV_DEVICE_ID, buf, 64);
3715 if (rc == 0) {
3716 if (buflen > 16)
3717 buflen = 16;
3718 memcpy(device_id, &buf[8], buflen);
3719 }
75d23d89 3720
edd16368 3721 kfree(buf);
75d23d89 3722
8383278d 3723 return rc; /*0 - got id, otherwise, didn't */
edd16368
SC		 3724}
3725
3726static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
03383736 3727 void *buf, int bufsize,
edd16368
SC		 3728 int extended_response)
3729{
3730 int rc = IO_OK;
3731 struct CommandList *c;
3732 unsigned char scsi3addr[8];
3733 struct ErrorInfo *ei;
3734
45fcb86e 3735 c = cmd_alloc(h);
bf43caf3 3736
e89c0ae7
SC		 3737 /* address the controller */
3738 memset(scsi3addr, 0, sizeof(scsi3addr));
a2dac136
SC		 3739 if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
3740 buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
45f769b2 3741 rc = -EAGAIN;
a2dac136
SC		 3742 goto out;
3743 }
edd16368
SC		 3744 if (extended_response)
3745 c->Request.CDB[1] = extended_response;
8bc8f47e
CH		 3746 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
3747 NO_TIMEOUT);
25163bd5
WS		 3748 if (rc)
3749 goto out;
edd16368
SC		 3750 ei = c->err_info;
3751 if (ei->CommandStatus != 0 &&
3752 ei->CommandStatus != CMD_DATA_UNDERRUN) {
d1e8beac 3753 hpsa_scsi_interpret_error(h, c);
45f769b2 3754 rc = -EIO;
283b4a9b 3755 } else {
03383736
DB		 3756 struct ReportLUNdata *rld = buf;
3757
3758 if (rld->extended_response_flag != extended_response) {
45f769b2
HR		 3759 if (!h->legacy_board) {
3760 dev_err(&h->pdev->dev,
3761 "report luns requested format %u, got %u\n",
3762 extended_response,
3763 rld->extended_response_flag);
3764 rc = -EINVAL;
3765 } else
3766 rc = -EOPNOTSUPP;
283b4a9b 3767 }
edd16368 3768 }
a2dac136 3769out:
45fcb86e 3770 cmd_free(h, c);
edd16368
SC		 3771 return rc;
3772}
3773
3774static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
03383736 3775 struct ReportExtendedLUNdata *buf, int bufsize)
edd16368 3776{
2a80d545
HR		 3777 int rc;
3778 struct ReportLUNdata *lbuf;
3779
3780 rc = hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
3781 HPSA_REPORT_PHYS_EXTENDED);
45f769b2 3782 if (!rc || rc != -EOPNOTSUPP)
2a80d545
HR		 3783 return rc;
3784
3785 /* REPORT PHYS EXTENDED is not supported */
3786 lbuf = kzalloc(sizeof(*lbuf), GFP_KERNEL);
3787 if (!lbuf)
3788 return -ENOMEM;
3789
3790 rc = hpsa_scsi_do_report_luns(h, 0, lbuf, sizeof(*lbuf), 0);
3791 if (!rc) {
3792 int i;
3793 u32 nphys;
3794
3795 /* Copy ReportLUNdata header */
3796 memcpy(buf, lbuf, 8);
3797 nphys = be32_to_cpu(*((__be32 *)lbuf->LUNListLength)) / 8;
3798 for (i = 0; i < nphys; i++)
3799 memcpy(buf->LUN[i].lunid, lbuf->LUN[i], 8);
3800 }
3801 kfree(lbuf);
3802 return rc;
edd16368
SC		 3803}
3804
3805static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
3806 struct ReportLUNdata *buf, int bufsize)
3807{
3808 return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
3809}
3810
3811static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
3812 int bus, int target, int lun)
3813{
3814 device->bus = bus;
3815 device->target = target;
3816 device->lun = lun;
3817}
3818
9846590e
SC		 3819/* Use VPD inquiry to get details of volume status */
3820static int hpsa_get_volume_status(struct ctlr_info *h,
3821 unsigned char scsi3addr[])
3822{
3823 int rc;
3824 int status;
3825 int size;
3826 unsigned char *buf;
3827
3828 buf = kzalloc(64, GFP_KERNEL);
3829 if (!buf)
3830 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3831
3832 /* Does controller have VPD for logical volume status? */
24a4b078 3833 if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
9846590e 3834 goto exit_failed;
9846590e
SC		 3835
3836 /* Get the size of the VPD return buffer */
3837 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3838 buf, HPSA_VPD_HEADER_SZ);
24a4b078 3839 if (rc != 0)
9846590e 3840 goto exit_failed;
9846590e
SC		 3841 size = buf[3];
3842
3843 /* Now get the whole VPD buffer */
3844 rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
3845 buf, size + HPSA_VPD_HEADER_SZ);
24a4b078 3846 if (rc != 0)
9846590e 3847 goto exit_failed;
9846590e
SC		 3848 status = buf[4]; /* status byte */
3849
3850 kfree(buf);
3851 return status;
3852exit_failed:
3853 kfree(buf);
3854 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
3855}
3856
3857/* Determine offline status of a volume.
3858 * Return either:
3859 * 0 (not offline)
67955ba3 3860 * 0xff (offline for unknown reasons)
9846590e
SC		 3861 * # (integer code indicating one of several NOT READY states
3862 * describing why a volume is to be kept offline)
3863 */
85b29008 3864static unsigned char hpsa_volume_offline(struct ctlr_info *h,
9846590e
SC		 3865 unsigned char scsi3addr[])
3866{
3867 struct CommandList *c;
9437ac43
SC		 3868 unsigned char *sense;
3869 u8 sense_key, asc, ascq;
3870 int sense_len;
25163bd5 3871 int rc, ldstat = 0;
9846590e
SC		 3872 u16 cmd_status;
3873 u8 scsi_status;
3874#define ASC_LUN_NOT_READY 0x04
3875#define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
3876#define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
3877
3878 c = cmd_alloc(h);
bf43caf3 3879
9846590e 3880 (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
c448ecfa 3881 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
3026ff9b 3882 NO_TIMEOUT);
25163bd5
WS		 3883 if (rc) {
3884 cmd_free(h, c);
85b29008 3885 return HPSA_VPD_LV_STATUS_UNSUPPORTED;
25163bd5 3886 }
9846590e 3887 sense = c->err_info->SenseInfo;
9437ac43
SC		 3888 if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
3889 sense_len = sizeof(c->err_info->SenseInfo);
3890 else
3891 sense_len = c->err_info->SenseLen;
3892 decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
9846590e
SC		 3893 cmd_status = c->err_info->CommandStatus;
3894 scsi_status = c->err_info->ScsiStatus;
3895 cmd_free(h, c);
9846590e
SC		 3896
3897 /* Determine the reason for not ready state */
3898 ldstat = hpsa_get_volume_status(h, scsi3addr);
3899
3900 /* Keep volume offline in certain cases: */
3901 switch (ldstat) {
85b29008 3902 case HPSA_LV_FAILED:
9846590e 3903 case HPSA_LV_UNDERGOING_ERASE:
5ca01204 3904 case HPSA_LV_NOT_AVAILABLE:
9846590e
SC		 3905 case HPSA_LV_UNDERGOING_RPI:
3906 case HPSA_LV_PENDING_RPI:
3907 case HPSA_LV_ENCRYPTED_NO_KEY:
3908 case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
3909 case HPSA_LV_UNDERGOING_ENCRYPTION:
3910 case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
3911 case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
3912 return ldstat;
3913 case HPSA_VPD_LV_STATUS_UNSUPPORTED:
3914 /* If VPD status page isn't available,
3915 * use ASC/ASCQ to determine state
3916 */
3917 if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
3918 (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
3919 return ldstat;
3920 break;
3921 default:
3922 break;
3923 }
85b29008 3924 return HPSA_LV_OK;
9846590e
SC		 3925}
3926
edd16368 3927static int hpsa_update_device_info(struct ctlr_info *h,
0b0e1d6c
SC		 3928 unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
3929 unsigned char *is_OBDR_device)
edd16368 3930{
0b0e1d6c
SC		 3931
3932#define OBDR_SIG_OFFSET 43
3933#define OBDR_TAPE_SIG "$DR-10"
3934#define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
3935#define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
3936
ea6d3bc3 3937 unsigned char *inq_buff;
0b0e1d6c 3938 unsigned char *obdr_sig;
683fc444 3939 int rc = 0;
edd16368 3940
ea6d3bc3 3941 inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
683fc444
DB		 3942 if (!inq_buff) {
3943 rc = -ENOMEM;
edd16368 3944 goto bail_out;
683fc444 3945 }
edd16368 3946
edd16368
SC		 3947 /* Do an inquiry to the device to see what it is. */
3948 if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
3949 (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
edd16368 3950 dev_err(&h->pdev->dev,
85b29008
DB		 3951 "%s: inquiry failed, device will be skipped.\n",
3952 __func__);
3953 rc = HPSA_INQUIRY_FAILED;
edd16368
SC		 3954 goto bail_out;
3955 }
3956
4af61e4f
DB		 3957 scsi_sanitize_inquiry_string(&inq_buff[8], 8);
3958 scsi_sanitize_inquiry_string(&inq_buff[16], 16);
75d23d89 3959
edd16368
SC		 3960 this_device->devtype = (inq_buff[0] & 0x1f);
3961 memcpy(this_device->scsi3addr, scsi3addr, 8);
3962 memcpy(this_device->vendor, &inq_buff[8],
3963 sizeof(this_device->vendor));
3964 memcpy(this_device->model, &inq_buff[16],
3965 sizeof(this_device->model));
7630b3a5 3966 this_device->rev = inq_buff[2];
edd16368
SC		 3967 memset(this_device->device_id, 0,
3968 sizeof(this_device->device_id));
8383278d 3969 if (hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8,
a45bcc4e 3970 sizeof(this_device->device_id)) < 0) {
8383278d 3971 dev_err(&h->pdev->dev,
a45bcc4e 3972 "hpsa%d: %s: can't get device id for [%d:%d:%d:%d]\t%s\t%.16s\n",
8383278d
ST		 3973 h->ctlr, __func__,
3974 h->scsi_host->host_no,
a45bcc4e
DB		 3975 this_device->bus, this_device->target,
3976 this_device->lun,
8383278d
ST		 3977 scsi_device_type(this_device->devtype),
3978 this_device->model);
a45bcc4e
DB		 3979 rc = HPSA_LV_FAILED;
3980 goto bail_out;
3981 }
edd16368 3982
af15ed36
DB		 3983 if ((this_device->devtype == TYPE_DISK ||
3984 this_device->devtype == TYPE_ZBC) &&
283b4a9b 3985 is_logical_dev_addr_mode(scsi3addr)) {
85b29008 3986 unsigned char volume_offline;
67955ba3 3987
edd16368 3988 hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
283b4a9b
SC		 3989 if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
3990 hpsa_get_ioaccel_status(h, scsi3addr, this_device);
67955ba3 3991 volume_offline = hpsa_volume_offline(h, scsi3addr);
4d17944a
HR		 3992 if (volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED &&
3993 h->legacy_board) {
3994 /*
3995 * Legacy boards might not support volume status
3996 */
3997 dev_info(&h->pdev->dev,
3998 "C0:T%d:L%d Volume status not available, assuming online.\n",
3999 this_device->target, this_device->lun);
4000 volume_offline = 0;
4001 }
eb94588d 4002 this_device->volume_offline = volume_offline;
85b29008
DB		 4003 if (volume_offline == HPSA_LV_FAILED) {
4004 rc = HPSA_LV_FAILED;
4005 dev_err(&h->pdev->dev,
4006 "%s: LV failed, device will be skipped.\n",
4007 __func__);
4008 goto bail_out;
4009 }
283b4a9b 4010 } else {
edd16368 4011 this_device->raid_level = RAID_UNKNOWN;
283b4a9b
SC		 4012 this_device->offload_config = 0;
4013 this_device->offload_enabled = 0;
41ce4c35 4014 this_device->offload_to_be_enabled = 0;
a3144e0b 4015 this_device->hba_ioaccel_enabled = 0;
9846590e 4016 this_device->volume_offline = 0;
03383736 4017 this_device->queue_depth = h->nr_cmds;
283b4a9b 4018 }
edd16368 4019
5086435e
DB		 4020 if (this_device->external)
4021 this_device->queue_depth = EXTERNAL_QD;
4022
0b0e1d6c
SC		 4023 if (is_OBDR_device) {
4024 /* See if this is a One-Button-Disaster-Recovery device
4025 * by looking for "$DR-10" at offset 43 in inquiry data.
4026 */
4027 obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
4028 *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
4029 strncmp(obdr_sig, OBDR_TAPE_SIG,
4030 OBDR_SIG_LEN) == 0);
4031 }
edd16368
SC		 4032 kfree(inq_buff);
4033 return 0;
4034
4035bail_out:
4036 kfree(inq_buff);
683fc444 4037 return rc;
edd16368
SC		 4038}
4039
c795505a
KB		 4040/*
4041 * Helper function to assign bus, target, lun mapping of devices.
edd16368
SC		 4042 * Logical drive target and lun are assigned at this time, but
4043 * physical device lun and target assignment are deferred (assigned
4044 * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
c795505a 4045*/
edd16368 4046static void figure_bus_target_lun(struct ctlr_info *h,
1f310bde 4047 u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
edd16368 4048{
c795505a 4049 u32 lunid = get_unaligned_le32(lunaddrbytes);
1f310bde
SC		 4050
4051 if (!is_logical_dev_addr_mode(lunaddrbytes)) {
4052 /* physical device, target and lun filled in later */
7630b3a5
HR		 4053 if (is_hba_lunid(lunaddrbytes)) {
4054 int bus = HPSA_HBA_BUS;
4055
4056 if (!device->rev)
4057 bus = HPSA_LEGACY_HBA_BUS;
c795505a 4058 hpsa_set_bus_target_lun(device,
7630b3a5
HR		 4059 bus, 0, lunid & 0x3fff);
4060 } else
1f310bde 4061 /* defer target, lun assignment for physical devices */
c795505a
KB		 4062 hpsa_set_bus_target_lun(device,
4063 HPSA_PHYSICAL_DEVICE_BUS, -1, -1);
1f310bde
SC		 4064 return;
4065 }
4066 /* It's a logical device */
66749d0d 4067 if (device->external) {
1f310bde 4068 hpsa_set_bus_target_lun(device,
c795505a
KB		 4069 HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff,
4070 lunid & 0x00ff);
1f310bde 4071 return;
edd16368 4072 }
c795505a
KB		 4073 hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS,
4074 0, lunid & 0x3fff);
edd16368
SC		 4075}
4076
66749d0d
ST		 4077static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position,
4078 int i, int nphysicals, int nlocal_logicals)
4079{
4080 /* In report logicals, local logicals are listed first,
4081 * then any externals.
4082 */
4083 int logicals_start = nphysicals + (raid_ctlr_position == 0);
4084
4085 if (i == raid_ctlr_position)
4086 return 0;
4087
4088 if (i < logicals_start)
4089 return 0;
4090
4091 /* i is in logicals range, but still within local logicals */
4092 if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals)
4093 return 0;
4094
4095 return 1; /* it's an external lun */
4096}
4097
edd16368
SC		 4098/*
4099 * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
4100 * logdev. The number of luns in physdev and logdev are returned in
4101 * *nphysicals and *nlogicals, respectively.
4102 * Returns 0 on success, -1 otherwise.
4103 */
4104static int hpsa_gather_lun_info(struct ctlr_info *h,
03383736 4105 struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
01a02ffc 4106 struct ReportLUNdata *logdev, u32 *nlogicals)
edd16368 4107{
03383736 4108 if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
edd16368
SC		 4109 dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
4110 return -1;
4111 }
03383736 4112 *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
edd16368 4113 if (*nphysicals > HPSA_MAX_PHYS_LUN) {
03383736
DB		 4114 dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
4115 HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
edd16368
SC		 4116 *nphysicals = HPSA_MAX_PHYS_LUN;
4117 }
03383736 4118 if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
edd16368
SC		 4119 dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
4120 return -1;
4121 }
6df1e954 4122 *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
edd16368
SC		 4123 /* Reject Logicals in excess of our max capability. */
4124 if (*nlogicals > HPSA_MAX_LUN) {
4125 dev_warn(&h->pdev->dev,
4126 "maximum logical LUNs (%d) exceeded. "
4127 "%d LUNs ignored.\n", HPSA_MAX_LUN,
4128 *nlogicals - HPSA_MAX_LUN);
b64ae4ab 4129 *nlogicals = HPSA_MAX_LUN;
edd16368
SC		 4130 }
4131 if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
4132 dev_warn(&h->pdev->dev,
4133 "maximum logical + physical LUNs (%d) exceeded. "
4134 "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
4135 *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
4136 *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
4137 }
4138 return 0;
4139}
4140
42a91641
DB		 4141static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
4142 int i, int nphysicals, int nlogicals,
a93aa1fe 4143 struct ReportExtendedLUNdata *physdev_list,
339b2b14
SC		 4144 struct ReportLUNdata *logdev_list)
4145{
4146 /* Helper function, figure out where the LUN ID info is coming from
4147 * given index i, lists of physical and logical devices, where in
4148 * the list the raid controller is supposed to appear (first or last)
4149 */
4150
4151 int logicals_start = nphysicals + (raid_ctlr_position == 0);
4152 int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
4153
4154 if (i == raid_ctlr_position)
4155 return RAID_CTLR_LUNID;
4156
4157 if (i < logicals_start)
d5b5d964
SC		 4158 return &physdev_list->LUN[i -
4159 (raid_ctlr_position == 0)].lunid[0];
339b2b14
SC		 4160
4161 if (i < last_device)
4162 return &logdev_list->LUN[i - nphysicals -
4163 (raid_ctlr_position == 0)][0];
4164 BUG();
4165 return NULL;
4166}
4167
03383736
DB		 4168/* get physical drive ioaccel handle and queue depth */
4169static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
4170 struct hpsa_scsi_dev_t *dev,
f2039b03 4171 struct ReportExtendedLUNdata *rlep, int rle_index,
03383736
DB		 4172 struct bmic_identify_physical_device *id_phys)
4173{
4174 int rc;
4b6e5597
ST		 4175 struct ext_report_lun_entry *rle;
4176
4b6e5597 4177 rle = &rlep->LUN[rle_index];
03383736
DB		 4178
4179 dev->ioaccel_handle = rle->ioaccel_handle;
f2039b03 4180 if ((rle->device_flags & 0x08) && dev->ioaccel_handle)
a3144e0b 4181 dev->hba_ioaccel_enabled = 1;
03383736 4182 memset(id_phys, 0, sizeof(*id_phys));
f2039b03
DB		 4183 rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0],
4184 GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys,
03383736
DB		 4185 sizeof(*id_phys));
4186 if (!rc)
4187 /* Reserve space for FW operations */
4188#define DRIVE_CMDS_RESERVED_FOR_FW 2
4189#define DRIVE_QUEUE_DEPTH 7
4190 dev->queue_depth =
4191 le16_to_cpu(id_phys->current_queue_depth_limit) -
4192 DRIVE_CMDS_RESERVED_FOR_FW;
4193 else
4194 dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
03383736
DB		 4195}
4196
8270b862 4197static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
f2039b03 4198 struct ReportExtendedLUNdata *rlep, int rle_index,
8270b862
JH		 4199 struct bmic_identify_physical_device *id_phys)
4200{
f2039b03
DB		 4201 struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
4202
4203 if ((rle->device_flags & 0x08) && this_device->ioaccel_handle)
8270b862
JH		 4204 this_device->hba_ioaccel_enabled = 1;
4205
4206 memcpy(&this_device->active_path_index,
4207 &id_phys->active_path_number,
4208 sizeof(this_device->active_path_index));
4209 memcpy(&this_device->path_map,
4210 &id_phys->redundant_path_present_map,
4211 sizeof(this_device->path_map));
4212 memcpy(&this_device->box,
4213 &id_phys->alternate_paths_phys_box_on_port,
4214 sizeof(this_device->box));
4215 memcpy(&this_device->phys_connector,
4216 &id_phys->alternate_paths_phys_connector,
4217 sizeof(this_device->phys_connector));
4218 memcpy(&this_device->bay,
4219 &id_phys->phys_bay_in_box,
4220 sizeof(this_device->bay));
4221}
4222
66749d0d
ST		 4223/* get number of local logical disks. */
4224static int hpsa_set_local_logical_count(struct ctlr_info *h,
4225 struct bmic_identify_controller *id_ctlr,
4226 u32 *nlocals)
4227{
4228 int rc;
4229
4230 if (!id_ctlr) {
4231 dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n",
4232 __func__);
4233 return -ENOMEM;
4234 }
4235 memset(id_ctlr, 0, sizeof(*id_ctlr));
4236 rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr));
4237 if (!rc)
c99dfd20 4238 if (id_ctlr->configured_logical_drive_count < 255)
66749d0d
ST		 4239 *nlocals = id_ctlr->configured_logical_drive_count;
4240 else
4241 *nlocals = le16_to_cpu(
4242 id_ctlr->extended_logical_unit_count);
4243 else
4244 *nlocals = -1;
4245 return rc;
4246}
4247
64ce60ca
DB		 4248static bool hpsa_is_disk_spare(struct ctlr_info *h, u8 *lunaddrbytes)
4249{
4250 struct bmic_identify_physical_device *id_phys;
4251 bool is_spare = false;
4252 int rc;
4253
4254 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
4255 if (!id_phys)
4256 return false;
4257
4258 rc = hpsa_bmic_id_physical_device(h,
4259 lunaddrbytes,
4260 GET_BMIC_DRIVE_NUMBER(lunaddrbytes),
4261 id_phys, sizeof(*id_phys));
4262 if (rc == 0)
4263 is_spare = (id_phys->more_flags >> 6) & 0x01;
4264
4265 kfree(id_phys);
4266 return is_spare;
4267}
4268
4269#define RPL_DEV_FLAG_NON_DISK 0x1
4270#define RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED 0x2
4271#define RPL_DEV_FLAG_UNCONFIG_DISK 0x4
4272
4273#define BMIC_DEVICE_TYPE_ENCLOSURE 6
4274
4275static bool hpsa_skip_device(struct ctlr_info *h, u8 *lunaddrbytes,
4276 struct ext_report_lun_entry *rle)
4277{
4278 u8 device_flags;
4279 u8 device_type;
4280
4281 if (!MASKED_DEVICE(lunaddrbytes))
4282 return false;
4283
4284 device_flags = rle->device_flags;
4285 device_type = rle->device_type;
4286
4287 if (device_flags & RPL_DEV_FLAG_NON_DISK) {
4288 if (device_type == BMIC_DEVICE_TYPE_ENCLOSURE)
4289 return false;
4290 return true;
4291 }
4292
4293 if (!(device_flags & RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED))
4294 return false;
4295
4296 if (device_flags & RPL_DEV_FLAG_UNCONFIG_DISK)
4297 return false;
4298
4299 /*
4300 * Spares may be spun down, we do not want to
4301 * do an Inquiry to a RAID set spare drive as
4302 * that would have them spun up, that is a
4303 * performance hit because I/O to the RAID device
4304 * stops while the spin up occurs which can take
4305 * over 50 seconds.
4306 */
4307 if (hpsa_is_disk_spare(h, lunaddrbytes))
4308 return true;
4309
4310 return false;
4311}
66749d0d 4312
8aa60681 4313static void hpsa_update_scsi_devices(struct ctlr_info *h)
edd16368
SC		 4314{
4315 /* the idea here is we could get notified
4316 * that some devices have changed, so we do a report
4317 * physical luns and report logical luns cmd, and adjust
4318 * our list of devices accordingly.
4319 *
4320 * The scsi3addr's of devices won't change so long as the
4321 * adapter is not reset. That means we can rescan and
4322 * tell which devices we already know about, vs. new
4323 * devices, vs. disappearing devices.
4324 */
a93aa1fe 4325 struct ReportExtendedLUNdata *physdev_list = NULL;
edd16368 4326 struct ReportLUNdata *logdev_list = NULL;
03383736 4327 struct bmic_identify_physical_device *id_phys = NULL;
66749d0d 4328 struct bmic_identify_controller *id_ctlr = NULL;
01a02ffc
SC		 4329 u32 nphysicals = 0;
4330 u32 nlogicals = 0;
66749d0d 4331 u32 nlocal_logicals = 0;
01a02ffc 4332 u32 ndev_allocated = 0;
edd16368
SC		 4333 struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
4334 int ncurrent = 0;
4f4eb9f1 4335 int i, n_ext_target_devs, ndevs_to_allocate;
339b2b14 4336 int raid_ctlr_position;
04fa2f44 4337 bool physical_device;
aca4a520 4338 DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
edd16368 4339
6396bb22 4340 currentsd = kcalloc(HPSA_MAX_DEVICES, sizeof(*currentsd), GFP_KERNEL);
92084715
SC		 4341 physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
4342 logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
edd16368 4343 tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
03383736 4344 id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
66749d0d 4345 id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL);
edd16368 4346
03383736 4347 if (!currentsd || !physdev_list || !logdev_list ||
66749d0d 4348 !tmpdevice || !id_phys || !id_ctlr) {
edd16368
SC		 4349 dev_err(&h->pdev->dev, "out of memory\n");
4350 goto out;
4351 }
4352 memset(lunzerobits, 0, sizeof(lunzerobits));
4353
853633e8
DB		 4354 h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
4355
03383736 4356 if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
853633e8
DB		 4357 logdev_list, &nlogicals)) {
4358 h->drv_req_rescan = 1;
edd16368 4359 goto out;
853633e8 4360 }
edd16368 4361
66749d0d
ST		 4362 /* Set number of local logicals (non PTRAID) */
4363 if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) {
4364 dev_warn(&h->pdev->dev,
4365 "%s: Can't determine number of local logical devices.\n",
4366 __func__);
4367 }
edd16368 4368
aca4a520
ST		 4369 /* We might see up to the maximum number of logical and physical disks
4370 * plus external target devices, and a device for the local RAID
4371 * controller.
edd16368 4372 */
aca4a520 4373 ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
edd16368 4374
4e188184
BAS		 4375 hpsa_ext_ctrl_present(h, physdev_list);
4376
edd16368
SC		 4377 /* Allocate the per device structures */
4378 for (i = 0; i < ndevs_to_allocate; i++) {
b7ec021f
ST		 4379 if (i >= HPSA_MAX_DEVICES) {
4380 dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
4381 " %d devices ignored.\n", HPSA_MAX_DEVICES,
4382 ndevs_to_allocate - HPSA_MAX_DEVICES);
4383 break;
4384 }
4385
edd16368
SC		 4386 currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
4387 if (!currentsd[i]) {
853633e8 4388 h->drv_req_rescan = 1;
edd16368
SC		 4389 goto out;
4390 }
4391 ndev_allocated++;
4392 }
4393
8645291b 4394 if (is_scsi_rev_5(h))
339b2b14
SC		 4395 raid_ctlr_position = 0;
4396 else
4397 raid_ctlr_position = nphysicals + nlogicals;
4398
edd16368 4399 /* adjust our table of devices */
4f4eb9f1 4400 n_ext_target_devs = 0;
edd16368 4401 for (i = 0; i < nphysicals + nlogicals + 1; i++) {
0b0e1d6c 4402 u8 *lunaddrbytes, is_OBDR = 0;
683fc444 4403 int rc = 0;
f2039b03 4404 int phys_dev_index = i - (raid_ctlr_position == 0);
64ce60ca 4405 bool skip_device = false;
edd16368 4406
421bf80c
ST		 4407 memset(tmpdevice, 0, sizeof(*tmpdevice));
4408
04fa2f44 4409 physical_device = i < nphysicals + (raid_ctlr_position == 0);
edd16368
SC		 4410
4411 /* Figure out where the LUN ID info is coming from */
339b2b14
SC		 4412 lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
4413 i, nphysicals, nlogicals, physdev_list, logdev_list);
41ce4c35 4414
86cf7130
DB		 4415 /* Determine if this is a lun from an external target array */
4416 tmpdevice->external =
4417 figure_external_status(h, raid_ctlr_position, i,
4418 nphysicals, nlocal_logicals);
4419
64ce60ca
DB		 4420 /*
4421 * Skip over some devices such as a spare.
4422 */
4423 if (!tmpdevice->external && physical_device) {
4424 skip_device = hpsa_skip_device(h, lunaddrbytes,
4425 &physdev_list->LUN[phys_dev_index]);
4426 if (skip_device)
4427 continue;
4428 }
edd16368 4429
b2582a65 4430 /* Get device type, vendor, model, device id, raid_map */
683fc444
DB		 4431 rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
4432 &is_OBDR);
4433 if (rc == -ENOMEM) {
4434 dev_warn(&h->pdev->dev,
4435 "Out of memory, rescan deferred.\n");
853633e8 4436 h->drv_req_rescan = 1;
683fc444 4437 goto out;
853633e8 4438 }
683fc444 4439 if (rc) {
85b29008 4440 h->drv_req_rescan = 1;
683fc444
DB		 4441 continue;
4442 }
4443
1f310bde 4444 figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
edd16368
SC		 4445 this_device = currentsd[ncurrent];
4446
edd16368 4447 *this_device = *tmpdevice;
04fa2f44 4448 this_device->physical_device = physical_device;
edd16368 4449
04fa2f44
KB		 4450 /*
4451 * Expose all devices except for physical devices that
4452 * are masked.
4453 */
4454 if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device)
2a168208
KB		 4455 this_device->expose_device = 0;
4456 else
4457 this_device->expose_device = 1;
41ce4c35 4458
d04e62b9
KB		 4459
4460 /*
4461 * Get the SAS address for physical devices that are exposed.
4462 */
4463 if (this_device->physical_device && this_device->expose_device)
4464 hpsa_get_sas_address(h, lunaddrbytes, this_device);
41ce4c35 4465
edd16368 4466 switch (this_device->devtype) {
0b0e1d6c 4467 case TYPE_ROM:
edd16368
SC		 4468 /* We don't *really* support actual CD-ROM devices,
4469 * just "One Button Disaster Recovery" tape drive
4470 * which temporarily pretends to be a CD-ROM drive.
4471 * So we check that the device is really an OBDR tape
4472 * device by checking for "$DR-10" in bytes 43-48 of
4473 * the inquiry data.
4474 */
0b0e1d6c
SC		 4475 if (is_OBDR)
4476 ncurrent++;
edd16368
SC		 4477 break;
4478 case TYPE_DISK:
af15ed36 4479 case TYPE_ZBC:
04fa2f44 4480 if (this_device->physical_device) {
b9092b79
KB		 4481 /* The disk is in HBA mode. */
4482 /* Never use RAID mapper in HBA mode. */
ecf418d1 4483 this_device->offload_enabled = 0;
b9092b79 4484 hpsa_get_ioaccel_drive_info(h, this_device,
f2039b03
DB		 4485 physdev_list, phys_dev_index, id_phys);
4486 hpsa_get_path_info(this_device,
4487 physdev_list, phys_dev_index, id_phys);
b9092b79 4488 }
ecf418d1 4489 ncurrent++;
edd16368
SC		 4490 break;
4491 case TYPE_TAPE:
4492 case TYPE_MEDIUM_CHANGER:
cca8f13b
DB		 4493 ncurrent++;
4494 break;
41ce4c35 4495 case TYPE_ENCLOSURE:
17a9e54a
DB		 4496 if (!this_device->external)
4497 hpsa_get_enclosure_info(h, lunaddrbytes,
cca8f13b
DB		 4498 physdev_list, phys_dev_index,
4499 this_device);
b9092b79 4500 ncurrent++;
41ce4c35 4501 break;
edd16368
SC		 4502 case TYPE_RAID:
4503 /* Only present the Smartarray HBA as a RAID controller.
4504 * If it's a RAID controller other than the HBA itself
4505 * (an external RAID controller, MSA500 or similar)
4506 * don't present it.
4507 */
4508 if (!is_hba_lunid(lunaddrbytes))
4509 break;
4510 ncurrent++;
4511 break;
4512 default:
4513 break;
4514 }
cfe5badc 4515 if (ncurrent >= HPSA_MAX_DEVICES)
edd16368
SC		 4516 break;
4517 }
d04e62b9
KB		 4518
4519 if (h->sas_host == NULL) {
4520 int rc = 0;
4521
4522 rc = hpsa_add_sas_host(h);
4523 if (rc) {
4524 dev_warn(&h->pdev->dev,
4525 "Could not add sas host %d\n", rc);
4526 goto out;
4527 }
4528 }
4529
8aa60681 4530 adjust_hpsa_scsi_table(h, currentsd, ncurrent);
edd16368
SC		 4531out:
4532 kfree(tmpdevice);
4533 for (i = 0; i < ndev_allocated; i++)
4534 kfree(currentsd[i]);
4535 kfree(currentsd);
edd16368
SC		 4536 kfree(physdev_list);
4537 kfree(logdev_list);
66749d0d 4538 kfree(id_ctlr);
03383736 4539 kfree(id_phys);
edd16368
SC		 4540}
4541
ec5cbf04
WS		 4542static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
4543 struct scatterlist *sg)
4544{
4545 u64 addr64 = (u64) sg_dma_address(sg);
4546 unsigned int len = sg_dma_len(sg);
4547
4548 desc->Addr = cpu_to_le64(addr64);
4549 desc->Len = cpu_to_le32(len);
4550 desc->Ext = 0;
4551}
4552
c7ee65b3
WS		 4553/*
4554 * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
edd16368
SC		 4555 * dma mapping and fills in the scatter gather entries of the
4556 * hpsa command, cp.
4557 */
33a2ffce 4558static int hpsa_scatter_gather(struct ctlr_info *h,
edd16368
SC		 4559 struct CommandList *cp,
4560 struct scsi_cmnd *cmd)
4561{
edd16368 4562 struct scatterlist *sg;
b3a7ba7c 4563 int use_sg, i, sg_limit, chained, last_sg;
33a2ffce 4564 struct SGDescriptor *curr_sg;
edd16368 4565
33a2ffce 4566 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
edd16368
SC		 4567
4568 use_sg = scsi_dma_map(cmd);
4569 if (use_sg < 0)
4570 return use_sg;
4571
4572 if (!use_sg)
4573 goto sglist_finished;
4574
b3a7ba7c
WS		 4575 /*
4576 * If the number of entries is greater than the max for a single list,
4577 * then we have a chained list; we will set up all but one entry in the
4578 * first list (the last entry is saved for link information);
4579 * otherwise, we don't have a chained list and we'll set up at each of
4580 * the entries in the one list.
4581 */
33a2ffce 4582 curr_sg = cp->SG;
b3a7ba7c
WS		 4583 chained = use_sg > h->max_cmd_sg_entries;
4584 sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
4585 last_sg = scsi_sg_count(cmd) - 1;
4586 scsi_for_each_sg(cmd, sg, sg_limit, i) {
ec5cbf04 4587 hpsa_set_sg_descriptor(curr_sg, sg);
33a2ffce
SC		 4588 curr_sg++;
4589 }
ec5cbf04 4590
b3a7ba7c
WS		 4591 if (chained) {
4592 /*
4593 * Continue with the chained list. Set curr_sg to the chained
4594 * list. Modify the limit to the total count less the entries
4595 * we've already set up. Resume the scan at the list entry
4596 * where the previous loop left off.
4597 */
4598 curr_sg = h->cmd_sg_list[cp->cmdindex];
4599 sg_limit = use_sg - sg_limit;
4600 for_each_sg(sg, sg, sg_limit, i) {
4601 hpsa_set_sg_descriptor(curr_sg, sg);
4602 curr_sg++;
4603 }
4604 }
4605
ec5cbf04 4606 /* Back the pointer up to the last entry and mark it as "last". */
b3a7ba7c 4607 (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
33a2ffce
SC		 4608
4609 if (use_sg + chained > h->maxSG)
4610 h->maxSG = use_sg + chained;
4611
4612 if (chained) {
4613 cp->Header.SGList = h->max_cmd_sg_entries;
50a0decf 4614 cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
e2bea6df
SC		 4615 if (hpsa_map_sg_chain_block(h, cp)) {
4616 scsi_dma_unmap(cmd);
4617 return -1;
4618 }
33a2ffce 4619 return 0;
edd16368
SC		 4620 }
4621
4622sglist_finished:
4623
01a02ffc 4624 cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
c7ee65b3 4625 cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
edd16368
SC		 4626 return 0;
4627}
4628
b63c64ac
DB		 4629static inline void warn_zero_length_transfer(struct ctlr_info *h,
4630 u8 *cdb, int cdb_len,
4631 const char *func)
4632{
f4d0ad1f
AS		 4633 dev_warn(&h->pdev->dev,
4634 "%s: Blocking zero-length request: CDB:%*phN\n",
4635 func, cdb_len, cdb);
b63c64ac
DB		 4636}
4637
4638#define IO_ACCEL_INELIGIBLE 1
4639/* zero-length transfers trigger hardware errors. */
4640static bool is_zero_length_transfer(u8 *cdb)
4641{
4642 u32 block_cnt;
4643
4644 /* Block zero-length transfer sizes on certain commands. */
4645 switch (cdb[0]) {
4646 case READ_10:
4647 case WRITE_10:
4648 case VERIFY: /* 0x2F */
4649 case WRITE_VERIFY: /* 0x2E */
4650 block_cnt = get_unaligned_be16(&cdb[7]);
4651 break;
4652 case READ_12:
4653 case WRITE_12:
4654 case VERIFY_12: /* 0xAF */
4655 case WRITE_VERIFY_12: /* 0xAE */
4656 block_cnt = get_unaligned_be32(&cdb[6]);
4657 break;
4658 case READ_16:
4659 case WRITE_16:
4660 case VERIFY_16: /* 0x8F */
4661 block_cnt = get_unaligned_be32(&cdb[10]);
4662 break;
4663 default:
4664 return false;
4665 }
4666
4667 return block_cnt == 0;
4668}
4669
283b4a9b
SC		 4670static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
4671{
4672 int is_write = 0;
4673 u32 block;
4674 u32 block_cnt;
4675
4676 /* Perform some CDB fixups if needed using 10 byte reads/writes only */
4677 switch (cdb[0]) {
4678 case WRITE_6:
4679 case WRITE_12:
4680 is_write = 1;
5dfdb089 4681 /* fall through */
283b4a9b
SC		 4682 case READ_6:
4683 case READ_12:
4684 if (*cdb_len == 6) {
abbada71
MR		 4685 block = (((cdb[1] & 0x1F) << 16) |
4686 (cdb[2] << 8) |
4687 cdb[3]);
283b4a9b 4688 block_cnt = cdb[4];
c8a6c9a6
DB		 4689 if (block_cnt == 0)
4690 block_cnt = 256;
283b4a9b
SC		 4691 } else {
4692 BUG_ON(*cdb_len != 12);
c8a6c9a6
DB		 4693 block = get_unaligned_be32(&cdb[2]);
4694 block_cnt = get_unaligned_be32(&cdb[6]);
283b4a9b
SC		 4695 }
4696 if (block_cnt > 0xffff)
4697 return IO_ACCEL_INELIGIBLE;
4698
4699 cdb[0] = is_write ? WRITE_10 : READ_10;
4700 cdb[1] = 0;
4701 cdb[2] = (u8) (block >> 24);
4702 cdb[3] = (u8) (block >> 16);
4703 cdb[4] = (u8) (block >> 8);
4704 cdb[5] = (u8) (block);
4705 cdb[6] = 0;
4706 cdb[7] = (u8) (block_cnt >> 8);
4707 cdb[8] = (u8) (block_cnt);
4708 cdb[9] = 0;
4709 *cdb_len = 10;
4710 break;
4711 }
4712 return 0;
4713}
4714
c349775e 4715static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
283b4a9b 4716 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4717 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
e1f7de0c
MG		 4718{
4719 struct scsi_cmnd *cmd = c->scsi_cmd;
e1f7de0c
MG		 4720 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
4721 unsigned int len;
4722 unsigned int total_len = 0;
4723 struct scatterlist *sg;
4724 u64 addr64;
4725 int use_sg, i;
4726 struct SGDescriptor *curr_sg;
4727 u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
4728
283b4a9b 4729 /* TODO: implement chaining support */
03383736
DB		 4730 if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
4731 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4732 return IO_ACCEL_INELIGIBLE;
03383736 4733 }
283b4a9b 4734
e1f7de0c
MG		 4735 BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
4736
b63c64ac
DB		 4737 if (is_zero_length_transfer(cdb)) {
4738 warn_zero_length_transfer(h, cdb, cdb_len, __func__);
4739 atomic_dec(&phys_disk->ioaccel_cmds_out);
4740 return IO_ACCEL_INELIGIBLE;
4741 }
4742
03383736
DB		 4743 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4744 atomic_dec(&phys_disk->ioaccel_cmds_out);
283b4a9b 4745 return IO_ACCEL_INELIGIBLE;
03383736 4746 }
283b4a9b 4747
e1f7de0c
MG		 4748 c->cmd_type = CMD_IOACCEL1;
4749
4750 /* Adjust the DMA address to point to the accelerated command buffer */
4751 c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
4752 (c->cmdindex * sizeof(*cp));
4753 BUG_ON(c->busaddr & 0x0000007F);
4754
4755 use_sg = scsi_dma_map(cmd);
03383736
DB		 4756 if (use_sg < 0) {
4757 atomic_dec(&phys_disk->ioaccel_cmds_out);
e1f7de0c 4758 return use_sg;
03383736 4759 }
e1f7de0c
MG		 4760
4761 if (use_sg) {
4762 curr_sg = cp->SG;
4763 scsi_for_each_sg(cmd, sg, use_sg, i) {
4764 addr64 = (u64) sg_dma_address(sg);
4765 len = sg_dma_len(sg);
4766 total_len += len;
50a0decf
SC		 4767 curr_sg->Addr = cpu_to_le64(addr64);
4768 curr_sg->Len = cpu_to_le32(len);
4769 curr_sg->Ext = cpu_to_le32(0);
e1f7de0c
MG		 4770 curr_sg++;
4771 }
50a0decf 4772 (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
e1f7de0c
MG		 4773
4774 switch (cmd->sc_data_direction) {
4775 case DMA_TO_DEVICE:
4776 control |= IOACCEL1_CONTROL_DATA_OUT;
4777 break;
4778 case DMA_FROM_DEVICE:
4779 control |= IOACCEL1_CONTROL_DATA_IN;
4780 break;
4781 case DMA_NONE:
4782 control |= IOACCEL1_CONTROL_NODATAXFER;
4783 break;
4784 default:
4785 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4786 cmd->sc_data_direction);
4787 BUG();
4788 break;
4789 }
4790 } else {
4791 control |= IOACCEL1_CONTROL_NODATAXFER;
4792 }
4793
c349775e 4794 c->Header.SGList = use_sg;
e1f7de0c 4795 /* Fill out the command structure to submit */
2b08b3e9
DB		 4796 cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
4797 cp->transfer_len = cpu_to_le32(total_len);
4798 cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
4799 (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
4800 cp->control = cpu_to_le32(control);
283b4a9b
SC		 4801 memcpy(cp->CDB, cdb, cdb_len);
4802 memcpy(cp->CISS_LUN, scsi3addr, 8);
c349775e 4803 /* Tag was already set at init time. */
283b4a9b 4804 enqueue_cmd_and_start_io(h, c);
e1f7de0c
MG		 4805 return 0;
4806}
edd16368 4807
283b4a9b
SC		 4808/*
4809 * Queue a command directly to a device behind the controller using the
4810 * I/O accelerator path.
4811 */
4812static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
4813 struct CommandList *c)
4814{
4815 struct scsi_cmnd *cmd = c->scsi_cmd;
4816 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4817
45e596cd
DB		 4818 if (!dev)
4819 return -1;
4820
03383736
DB		 4821 c->phys_disk = dev;
4822
283b4a9b 4823 return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
03383736 4824 cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
283b4a9b
SC		 4825}
4826
dd0e19f3
ST		 4827/*
4828 * Set encryption parameters for the ioaccel2 request
4829 */
4830static void set_encrypt_ioaccel2(struct ctlr_info *h,
4831 struct CommandList *c, struct io_accel2_cmd *cp)
4832{
4833 struct scsi_cmnd *cmd = c->scsi_cmd;
4834 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
4835 struct raid_map_data *map = &dev->raid_map;
4836 u64 first_block;
4837
dd0e19f3 4838 /* Are we doing encryption on this device */
2b08b3e9 4839 if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
dd0e19f3
ST		 4840 return;
4841 /* Set the data encryption key index. */
4842 cp->dekindex = map->dekindex;
4843
4844 /* Set the encryption enable flag, encoded into direction field. */
4845 cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
4846
4847 /* Set encryption tweak values based on logical block address
4848 * If block size is 512, tweak value is LBA.
4849 * For other block sizes, tweak is (LBA * block size)/ 512)
4850 */
4851 switch (cmd->cmnd[0]) {
4852 /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
dd0e19f3 4853 case READ_6:
abbada71
MR		 4854 case WRITE_6:
4855 first_block = (((cmd->cmnd[1] & 0x1F) << 16) |
4856 (cmd->cmnd[2] << 8) |
4857 cmd->cmnd[3]);
dd0e19f3
ST		 4858 break;
4859 case WRITE_10:
4860 case READ_10:
dd0e19f3
ST		 4861 /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
4862 case WRITE_12:
4863 case READ_12:
2b08b3e9 4864 first_block = get_unaligned_be32(&cmd->cmnd[2]);
dd0e19f3
ST		 4865 break;
4866 case WRITE_16:
4867 case READ_16:
2b08b3e9 4868 first_block = get_unaligned_be64(&cmd->cmnd[2]);
dd0e19f3
ST		 4869 break;
4870 default:
4871 dev_err(&h->pdev->dev,
2b08b3e9
DB		 4872 "ERROR: %s: size (0x%x) not supported for encryption\n",
4873 __func__, cmd->cmnd[0]);
dd0e19f3
ST		 4874 BUG();
4875 break;
4876 }
2b08b3e9
DB		 4877
4878 if (le32_to_cpu(map->volume_blk_size) != 512)
4879 first_block = first_block *
4880 le32_to_cpu(map->volume_blk_size)/512;
4881
4882 cp->tweak_lower = cpu_to_le32(first_block);
4883 cp->tweak_upper = cpu_to_le32(first_block >> 32);
dd0e19f3
ST		 4884}
4885
c349775e
ST		 4886static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
4887 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 4888 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e
ST		 4889{
4890 struct scsi_cmnd *cmd = c->scsi_cmd;
4891 struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
4892 struct ioaccel2_sg_element *curr_sg;
4893 int use_sg, i;
4894 struct scatterlist *sg;
4895 u64 addr64;
4896 u32 len;
4897 u32 total_len = 0;
4898
45e596cd
DB		 4899 if (!cmd->device)
4900 return -1;
4901
4902 if (!cmd->device->hostdata)
4903 return -1;
4904
d9a729f3 4905 BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
c349775e 4906
b63c64ac
DB		 4907 if (is_zero_length_transfer(cdb)) {
4908 warn_zero_length_transfer(h, cdb, cdb_len, __func__);
4909 atomic_dec(&phys_disk->ioaccel_cmds_out);
4910 return IO_ACCEL_INELIGIBLE;
4911 }
4912
03383736
DB		 4913 if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
4914 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4915 return IO_ACCEL_INELIGIBLE;
03383736
DB		 4916 }
4917
c349775e
ST		 4918 c->cmd_type = CMD_IOACCEL2;
4919 /* Adjust the DMA address to point to the accelerated command buffer */
4920 c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
4921 (c->cmdindex * sizeof(*cp));
4922 BUG_ON(c->busaddr & 0x0000007F);
4923
4924 memset(cp, 0, sizeof(*cp));
4925 cp->IU_type = IOACCEL2_IU_TYPE;
4926
4927 use_sg = scsi_dma_map(cmd);
03383736
DB		 4928 if (use_sg < 0) {
4929 atomic_dec(&phys_disk->ioaccel_cmds_out);
c349775e 4930 return use_sg;
03383736 4931 }
c349775e
ST		 4932
4933 if (use_sg) {
c349775e 4934 curr_sg = cp->sg;
d9a729f3
WS		 4935 if (use_sg > h->ioaccel_maxsg) {
4936 addr64 = le64_to_cpu(
4937 h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
4938 curr_sg->address = cpu_to_le64(addr64);
4939 curr_sg->length = 0;
4940 curr_sg->reserved[0] = 0;
4941 curr_sg->reserved[1] = 0;
4942 curr_sg->reserved[2] = 0;
4943 curr_sg->chain_indicator = 0x80;
4944
4945 curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
4946 }
c349775e
ST		 4947 scsi_for_each_sg(cmd, sg, use_sg, i) {
4948 addr64 = (u64) sg_dma_address(sg);
4949 len = sg_dma_len(sg);
4950 total_len += len;
4951 curr_sg->address = cpu_to_le64(addr64);
4952 curr_sg->length = cpu_to_le32(len);
4953 curr_sg->reserved[0] = 0;
4954 curr_sg->reserved[1] = 0;
4955 curr_sg->reserved[2] = 0;
4956 curr_sg->chain_indicator = 0;
4957 curr_sg++;
4958 }
4959
4960 switch (cmd->sc_data_direction) {
4961 case DMA_TO_DEVICE:
dd0e19f3
ST		 4962 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4963 cp->direction |= IOACCEL2_DIR_DATA_OUT;
c349775e
ST		 4964 break;
4965 case DMA_FROM_DEVICE:
dd0e19f3
ST		 4966 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4967 cp->direction |= IOACCEL2_DIR_DATA_IN;
c349775e
ST		 4968 break;
4969 case DMA_NONE:
dd0e19f3
ST		 4970 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4971 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e
ST		 4972 break;
4973 default:
4974 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
4975 cmd->sc_data_direction);
4976 BUG();
4977 break;
4978 }
4979 } else {
dd0e19f3
ST		 4980 cp->direction &= ~IOACCEL2_DIRECTION_MASK;
4981 cp->direction |= IOACCEL2_DIR_NO_DATA;
c349775e 4982 }
dd0e19f3
ST		 4983
4984 /* Set encryption parameters, if necessary */
4985 set_encrypt_ioaccel2(h, c, cp);
4986
2b08b3e9 4987 cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
f2405db8 4988 cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
c349775e 4989 memcpy(cp->cdb, cdb, sizeof(cp->cdb));
c349775e 4990
c349775e
ST		 4991 cp->data_len = cpu_to_le32(total_len);
4992 cp->err_ptr = cpu_to_le64(c->busaddr +
4993 offsetof(struct io_accel2_cmd, error_data));
50a0decf 4994 cp->err_len = cpu_to_le32(sizeof(cp->error_data));
c349775e 4995
d9a729f3
WS		 4996 /* fill in sg elements */
4997 if (use_sg > h->ioaccel_maxsg) {
4998 cp->sg_count = 1;
a736e9b6 4999 cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0]));
d9a729f3
WS		 5000 if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
5001 atomic_dec(&phys_disk->ioaccel_cmds_out);
5002 scsi_dma_unmap(cmd);
5003 return -1;
5004 }
5005 } else
5006 cp->sg_count = (u8) use_sg;
5007
c349775e
ST		 5008 enqueue_cmd_and_start_io(h, c);
5009 return 0;
5010}
5011
5012/*
5013 * Queue a command to the correct I/O accelerator path.
5014 */
5015static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
5016 struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
03383736 5017 u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
c349775e 5018{
45e596cd
DB		 5019 if (!c->scsi_cmd->device)
5020 return -1;
5021
5022 if (!c->scsi_cmd->device->hostdata)
5023 return -1;
5024
03383736
DB		 5025 /* Try to honor the device's queue depth */
5026 if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
5027 phys_disk->queue_depth) {
5028 atomic_dec(&phys_disk->ioaccel_cmds_out);
5029 return IO_ACCEL_INELIGIBLE;
5030 }
c349775e
ST		 5031 if (h->transMethod & CFGTBL_Trans_io_accel1)
5032 return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
03383736
DB		 5033 cdb, cdb_len, scsi3addr,
5034 phys_disk);
c349775e
ST		 5035 else
5036 return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
03383736
DB		 5037 cdb, cdb_len, scsi3addr,
5038 phys_disk);
c349775e
ST		 5039}
5040
6b80b18f
ST		 5041static void raid_map_helper(struct raid_map_data *map,
5042 int offload_to_mirror, u32 *map_index, u32 *current_group)
5043{
5044 if (offload_to_mirror == 0) {
5045 /* use physical disk in the first mirrored group. */
2b08b3e9 5046 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 5047 return;
5048 }
5049 do {
5050 /* determine mirror group that *map_index indicates */
2b08b3e9
DB		 5051 *current_group = *map_index /
5052 le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 5053 if (offload_to_mirror == *current_group)
5054 continue;
2b08b3e9 5055 if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
6b80b18f 5056 /* select map index from next group */
2b08b3e9 5057 *map_index += le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 5058 (*current_group)++;
5059 } else {
5060 /* select map index from first group */
2b08b3e9 5061 *map_index %= le16_to_cpu(map->data_disks_per_row);
6b80b18f
ST		 5062 *current_group = 0;
5063 }
5064 } while (offload_to_mirror != *current_group);
5065}
5066
283b4a9b
SC		 5067/*
5068 * Attempt to perform offload RAID mapping for a logical volume I/O.
5069 */
5070static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
5071 struct CommandList *c)
5072{
5073 struct scsi_cmnd *cmd = c->scsi_cmd;
5074 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
5075 struct raid_map_data *map = &dev->raid_map;
5076 struct raid_map_disk_data *dd = &map->data[0];
5077 int is_write = 0;
5078 u32 map_index;
5079 u64 first_block, last_block;
5080 u32 block_cnt;
5081 u32 blocks_per_row;
5082 u64 first_row, last_row;
5083 u32 first_row_offset, last_row_offset;
5084 u32 first_column, last_column;
6b80b18f
ST		 5085 u64 r0_first_row, r0_last_row;
5086 u32 r5or6_blocks_per_row;
5087 u64 r5or6_first_row, r5or6_last_row;
5088 u32 r5or6_first_row_offset, r5or6_last_row_offset;
5089 u32 r5or6_first_column, r5or6_last_column;
5090 u32 total_disks_per_row;
5091 u32 stripesize;
5092 u32 first_group, last_group, current_group;
283b4a9b
SC		 5093 u32 map_row;
5094 u32 disk_handle;
5095 u64 disk_block;
5096 u32 disk_block_cnt;
5097 u8 cdb[16];
5098 u8 cdb_len;
2b08b3e9 5099 u16 strip_size;
283b4a9b
SC		 5100#if BITS_PER_LONG == 32
5101 u64 tmpdiv;
5102#endif
6b80b18f 5103 int offload_to_mirror;
283b4a9b 5104
45e596cd
DB		 5105 if (!dev)
5106 return -1;
5107
283b4a9b
SC		 5108 /* check for valid opcode, get LBA and block count */
5109 switch (cmd->cmnd[0]) {
5110 case WRITE_6:
5111 is_write = 1;
5dfdb089 5112 /* fall through */
283b4a9b 5113 case READ_6:
abbada71
MR		 5114 first_block = (((cmd->cmnd[1] & 0x1F) << 16) |
5115 (cmd->cmnd[2] << 8) |
5116 cmd->cmnd[3]);
283b4a9b 5117 block_cnt = cmd->cmnd[4];
3fa89a04
SC		 5118 if (block_cnt == 0)
5119 block_cnt = 256;
283b4a9b
SC		 5120 break;
5121 case WRITE_10:
5122 is_write = 1;
5dfdb089 5123 /* fall through */
283b4a9b
SC		 5124 case READ_10:
5125 first_block =
5126 (((u64) cmd->cmnd[2]) << 24) |
5127 (((u64) cmd->cmnd[3]) << 16) |
5128 (((u64) cmd->cmnd[4]) << 8) |
5129 cmd->cmnd[5];
5130 block_cnt =
5131 (((u32) cmd->cmnd[7]) << 8) |
5132 cmd->cmnd[8];
5133 break;
5134 case WRITE_12:
5135 is_write = 1;
5dfdb089 5136 /* fall through */
283b4a9b
SC		 5137 case READ_12:
5138 first_block =
5139 (((u64) cmd->cmnd[2]) << 24) |
5140 (((u64) cmd->cmnd[3]) << 16) |
5141 (((u64) cmd->cmnd[4]) << 8) |
5142 cmd->cmnd[5];
5143 block_cnt =
5144 (((u32) cmd->cmnd[6]) << 24) |
5145 (((u32) cmd->cmnd[7]) << 16) |
5146 (((u32) cmd->cmnd[8]) << 8) |
5147 cmd->cmnd[9];
5148 break;
5149 case WRITE_16:
5150 is_write = 1;
5dfdb089 5151 /* fall through */
283b4a9b
SC		 5152 case READ_16:
5153 first_block =
5154 (((u64) cmd->cmnd[2]) << 56) |
5155 (((u64) cmd->cmnd[3]) << 48) |
5156 (((u64) cmd->cmnd[4]) << 40) |
5157 (((u64) cmd->cmnd[5]) << 32) |
5158 (((u64) cmd->cmnd[6]) << 24) |
5159 (((u64) cmd->cmnd[7]) << 16) |
5160 (((u64) cmd->cmnd[8]) << 8) |
5161 cmd->cmnd[9];
5162 block_cnt =
5163 (((u32) cmd->cmnd[10]) << 24) |
5164 (((u32) cmd->cmnd[11]) << 16) |
5165 (((u32) cmd->cmnd[12]) << 8) |
5166 cmd->cmnd[13];
5167 break;
5168 default:
5169 return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
5170 }
283b4a9b
SC		 5171 last_block = first_block + block_cnt - 1;
5172
5173 /* check for write to non-RAID-0 */
5174 if (is_write && dev->raid_level != 0)
5175 return IO_ACCEL_INELIGIBLE;
5176
5177 /* check for invalid block or wraparound */
2b08b3e9
DB		 5178 if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
5179 last_block < first_block)
283b4a9b
SC		 5180 return IO_ACCEL_INELIGIBLE;
5181
5182 /* calculate stripe information for the request */
2b08b3e9
DB		 5183 blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
5184 le16_to_cpu(map->strip_size);
5185 strip_size = le16_to_cpu(map->strip_size);
283b4a9b
SC		 5186#if BITS_PER_LONG == 32
5187 tmpdiv = first_block;
5188 (void) do_div(tmpdiv, blocks_per_row);
5189 first_row = tmpdiv;
5190 tmpdiv = last_block;
5191 (void) do_div(tmpdiv, blocks_per_row);
5192 last_row = tmpdiv;
5193 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
5194 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
5195 tmpdiv = first_row_offset;
2b08b3e9 5196 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 5197 first_column = tmpdiv;
5198 tmpdiv = last_row_offset;
2b08b3e9 5199 (void) do_div(tmpdiv, strip_size);
283b4a9b
SC		 5200 last_column = tmpdiv;
5201#else
5202 first_row = first_block / blocks_per_row;
5203 last_row = last_block / blocks_per_row;
5204 first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
5205 last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
2b08b3e9
DB		 5206 first_column = first_row_offset / strip_size;
5207 last_column = last_row_offset / strip_size;
283b4a9b
SC		 5208#endif
5209
5210 /* if this isn't a single row/column then give to the controller */
5211 if ((first_row != last_row) || (first_column != last_column))
5212 return IO_ACCEL_INELIGIBLE;
5213
5214 /* proceeding with driver mapping */
2b08b3e9
DB		 5215 total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
5216 le16_to_cpu(map->metadata_disks_per_row);
283b4a9b 5217 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 5218 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 5219 map_index = (map_row * total_disks_per_row) + first_column;
5220
5221 switch (dev->raid_level) {
5222 case HPSA_RAID_0:
5223 break; /* nothing special to do */
5224 case HPSA_RAID_1:
5225 /* Handles load balance across RAID 1 members.
5226 * (2-drive R1 and R10 with even # of drives.)
5227 * Appropriate for SSDs, not optimal for HDDs
283b4a9b 5228 */
2b08b3e9 5229 BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
283b4a9b 5230 if (dev->offload_to_mirror)
2b08b3e9 5231 map_index += le16_to_cpu(map->data_disks_per_row);
283b4a9b 5232 dev->offload_to_mirror = !dev->offload_to_mirror;
6b80b18f
ST		 5233 break;
5234 case HPSA_RAID_ADM:
5235 /* Handles N-way mirrors (R1-ADM)
5236 * and R10 with # of drives divisible by 3.)
5237 */
2b08b3e9 5238 BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
6b80b18f
ST		 5239
5240 offload_to_mirror = dev->offload_to_mirror;
5241 raid_map_helper(map, offload_to_mirror,
5242 &map_index, &current_group);
5243 /* set mirror group to use next time */
5244 offload_to_mirror =
2b08b3e9
DB		 5245 (offload_to_mirror >=
5246 le16_to_cpu(map->layout_map_count) - 1)
6b80b18f 5247 ? 0 : offload_to_mirror + 1;
6b80b18f
ST		 5248 dev->offload_to_mirror = offload_to_mirror;
5249 /* Avoid direct use of dev->offload_to_mirror within this
5250 * function since multiple threads might simultaneously
5251 * increment it beyond the range of dev->layout_map_count -1.
5252 */
5253 break;
5254 case HPSA_RAID_5:
5255 case HPSA_RAID_6:
2b08b3e9 5256 if (le16_to_cpu(map->layout_map_count) <= 1)
6b80b18f
ST		 5257 break;
5258
5259 /* Verify first and last block are in same RAID group */
5260 r5or6_blocks_per_row =
2b08b3e9
DB		 5261 le16_to_cpu(map->strip_size) *
5262 le16_to_cpu(map->data_disks_per_row);
6b80b18f 5263 BUG_ON(r5or6_blocks_per_row == 0);
2b08b3e9
DB		 5264 stripesize = r5or6_blocks_per_row *
5265 le16_to_cpu(map->layout_map_count);
6b80b18f
ST		 5266#if BITS_PER_LONG == 32
5267 tmpdiv = first_block;
5268 first_group = do_div(tmpdiv, stripesize);
5269 tmpdiv = first_group;
5270 (void) do_div(tmpdiv, r5or6_blocks_per_row);
5271 first_group = tmpdiv;
5272 tmpdiv = last_block;
5273 last_group = do_div(tmpdiv, stripesize);
5274 tmpdiv = last_group;
5275 (void) do_div(tmpdiv, r5or6_blocks_per_row);
5276 last_group = tmpdiv;
5277#else
5278 first_group = (first_block % stripesize) / r5or6_blocks_per_row;
5279 last_group = (last_block % stripesize) / r5or6_blocks_per_row;
6b80b18f 5280#endif
000ff7c2 5281 if (first_group != last_group)
6b80b18f
ST		 5282 return IO_ACCEL_INELIGIBLE;
5283
5284 /* Verify request is in a single row of RAID 5/6 */
5285#if BITS_PER_LONG == 32
5286 tmpdiv = first_block;
5287 (void) do_div(tmpdiv, stripesize);
5288 first_row = r5or6_first_row = r0_first_row = tmpdiv;
5289 tmpdiv = last_block;
5290 (void) do_div(tmpdiv, stripesize);
5291 r5or6_last_row = r0_last_row = tmpdiv;
5292#else
5293 first_row = r5or6_first_row = r0_first_row =
5294 first_block / stripesize;
5295 r5or6_last_row = r0_last_row = last_block / stripesize;
5296#endif
5297 if (r5or6_first_row != r5or6_last_row)
5298 return IO_ACCEL_INELIGIBLE;
5299
5300
5301 /* Verify request is in a single column */
5302#if BITS_PER_LONG == 32
5303 tmpdiv = first_block;
5304 first_row_offset = do_div(tmpdiv, stripesize);
5305 tmpdiv = first_row_offset;
5306 first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
5307 r5or6_first_row_offset = first_row_offset;
5308 tmpdiv = last_block;
5309 r5or6_last_row_offset = do_div(tmpdiv, stripesize);
5310 tmpdiv = r5or6_last_row_offset;
5311 r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
5312 tmpdiv = r5or6_first_row_offset;
5313 (void) do_div(tmpdiv, map->strip_size);
5314 first_column = r5or6_first_column = tmpdiv;
5315 tmpdiv = r5or6_last_row_offset;
5316 (void) do_div(tmpdiv, map->strip_size);
5317 r5or6_last_column = tmpdiv;
5318#else
5319 first_row_offset = r5or6_first_row_offset =
5320 (u32)((first_block % stripesize) %
5321 r5or6_blocks_per_row);
5322
5323 r5or6_last_row_offset =
5324 (u32)((last_block % stripesize) %
5325 r5or6_blocks_per_row);
5326
5327 first_column = r5or6_first_column =
2b08b3e9 5328 r5or6_first_row_offset / le16_to_cpu(map->strip_size);
6b80b18f 5329 r5or6_last_column =
2b08b3e9 5330 r5or6_last_row_offset / le16_to_cpu(map->strip_size);
6b80b18f
ST		 5331#endif
5332 if (r5or6_first_column != r5or6_last_column)
5333 return IO_ACCEL_INELIGIBLE;
5334
5335 /* Request is eligible */
5336 map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
2b08b3e9 5337 le16_to_cpu(map->row_cnt);
6b80b18f
ST		 5338
5339 map_index = (first_group *
2b08b3e9 5340 (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
6b80b18f
ST		 5341 (map_row * total_disks_per_row) + first_column;
5342 break;
5343 default:
5344 return IO_ACCEL_INELIGIBLE;
283b4a9b 5345 }
6b80b18f 5346
07543e0c
SC		 5347 if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
5348 return IO_ACCEL_INELIGIBLE;
5349
03383736 5350 c->phys_disk = dev->phys_disk[map_index];
c3390df4
DB		 5351 if (!c->phys_disk)
5352 return IO_ACCEL_INELIGIBLE;
03383736 5353
283b4a9b 5354 disk_handle = dd[map_index].ioaccel_handle;
2b08b3e9
DB		 5355 disk_block = le64_to_cpu(map->disk_starting_blk) +
5356 first_row * le16_to_cpu(map->strip_size) +
5357 (first_row_offset - first_column *
5358 le16_to_cpu(map->strip_size));
283b4a9b
SC		 5359 disk_block_cnt = block_cnt;
5360
5361 /* handle differing logical/physical block sizes */
5362 if (map->phys_blk_shift) {
5363 disk_block <<= map->phys_blk_shift;
5364 disk_block_cnt <<= map->phys_blk_shift;
5365 }
5366 BUG_ON(disk_block_cnt > 0xffff);
5367
5368 /* build the new CDB for the physical disk I/O */
5369 if (disk_block > 0xffffffff) {
5370 cdb[0] = is_write ? WRITE_16 : READ_16;
5371 cdb[1] = 0;
5372 cdb[2] = (u8) (disk_block >> 56);
5373 cdb[3] = (u8) (disk_block >> 48);
5374 cdb[4] = (u8) (disk_block >> 40);
5375 cdb[5] = (u8) (disk_block >> 32);
5376 cdb[6] = (u8) (disk_block >> 24);
5377 cdb[7] = (u8) (disk_block >> 16);
5378 cdb[8] = (u8) (disk_block >> 8);
5379 cdb[9] = (u8) (disk_block);
5380 cdb[10] = (u8) (disk_block_cnt >> 24);
5381 cdb[11] = (u8) (disk_block_cnt >> 16);
5382 cdb[12] = (u8) (disk_block_cnt >> 8);
5383 cdb[13] = (u8) (disk_block_cnt);
5384 cdb[14] = 0;
5385 cdb[15] = 0;
5386 cdb_len = 16;
5387 } else {
5388 cdb[0] = is_write ? WRITE_10 : READ_10;
5389 cdb[1] = 0;
5390 cdb[2] = (u8) (disk_block >> 24);
5391 cdb[3] = (u8) (disk_block >> 16);
5392 cdb[4] = (u8) (disk_block >> 8);
5393 cdb[5] = (u8) (disk_block);
5394 cdb[6] = 0;
5395 cdb[7] = (u8) (disk_block_cnt >> 8);
5396 cdb[8] = (u8) (disk_block_cnt);
5397 cdb[9] = 0;
5398 cdb_len = 10;
5399 }
5400 return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
03383736
DB		 5401 dev->scsi3addr,
5402 dev->phys_disk[map_index]);
283b4a9b
SC		 5403}
5404
25163bd5
WS		 5405/*
5406 * Submit commands down the "normal" RAID stack path
5407 * All callers to hpsa_ciss_submit must check lockup_detected
5408 * beforehand, before (opt.) and after calling cmd_alloc
5409 */
574f05d3
SC		 5410static int hpsa_ciss_submit(struct ctlr_info *h,
5411 struct CommandList *c, struct scsi_cmnd *cmd,
5412 unsigned char scsi3addr[])
edd16368 5413{
edd16368 5414 cmd->host_scribble = (unsigned char *) c;
edd16368
SC		 5415 c->cmd_type = CMD_SCSI;
5416 c->scsi_cmd = cmd;
5417 c->Header.ReplyQueue = 0; /* unused in simple mode */
5418 memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
f2405db8 5419 c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
edd16368
SC		 5420
5421 /* Fill in the request block... */
5422
5423 c->Request.Timeout = 0;
edd16368
SC		 5424 BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
5425 c->Request.CDBLen = cmd->cmd_len;
5426 memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
edd16368
SC		 5427 switch (cmd->sc_data_direction) {
5428 case DMA_TO_DEVICE:
a505b86f
SC		 5429 c->Request.type_attr_dir =
5430 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 5431 break;
5432 case DMA_FROM_DEVICE:
a505b86f
SC		 5433 c->Request.type_attr_dir =
5434 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 5435 break;
5436 case DMA_NONE:
a505b86f
SC		 5437 c->Request.type_attr_dir =
5438 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 5439 break;
5440 case DMA_BIDIRECTIONAL:
5441 /* This can happen if a buggy application does a scsi passthru
5442 * and sets both inlen and outlen to non-zero. ( see
5443 * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
5444 */
5445
a505b86f
SC		 5446 c->Request.type_attr_dir =
5447 TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
edd16368
SC		 5448 /* This is technically wrong, and hpsa controllers should
5449 * reject it with CMD_INVALID, which is the most correct
5450 * response, but non-fibre backends appear to let it
5451 * slide by, and give the same results as if this field
5452 * were set correctly. Either way is acceptable for
5453 * our purposes here.
5454 */
5455
5456 break;
5457
5458 default:
5459 dev_err(&h->pdev->dev, "unknown data direction: %d\n",
5460 cmd->sc_data_direction);
5461 BUG();
5462 break;
5463 }
5464
33a2ffce 5465 if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
73153fe5 5466 hpsa_cmd_resolve_and_free(h, c);
edd16368
SC		 5467 return SCSI_MLQUEUE_HOST_BUSY;
5468 }
5469 enqueue_cmd_and_start_io(h, c);
5470 /* the cmd'll come back via intr handler in complete_scsi_command() */
5471 return 0;
5472}
5473
360c73bd
SC		 5474static void hpsa_cmd_init(struct ctlr_info *h, int index,
5475 struct CommandList *c)
5476{
5477 dma_addr_t cmd_dma_handle, err_dma_handle;
5478
5479 /* Zero out all of commandlist except the last field, refcount */
5480 memset(c, 0, offsetof(struct CommandList, refcount));
5481 c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
5482 cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
5483 c->err_info = h->errinfo_pool + index;
5484 memset(c->err_info, 0, sizeof(*c->err_info));
5485 err_dma_handle = h->errinfo_pool_dhandle
5486 + index * sizeof(*c->err_info);
5487 c->cmdindex = index;
5488 c->busaddr = (u32) cmd_dma_handle;
5489 c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
5490 c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
5491 c->h = h;
a58e7e53 5492 c->scsi_cmd = SCSI_CMD_IDLE;
360c73bd
SC		 5493}
5494
5495static void hpsa_preinitialize_commands(struct ctlr_info *h)
5496{
5497 int i;
5498
5499 for (i = 0; i < h->nr_cmds; i++) {
5500 struct CommandList *c = h->cmd_pool + i;
5501
5502 hpsa_cmd_init(h, i, c);
5503 atomic_set(&c->refcount, 0);
5504 }
5505}
5506
5507static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
5508 struct CommandList *c)
5509{
5510 dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
5511
73153fe5
WS		 5512 BUG_ON(c->cmdindex != index);
5513
360c73bd
SC		 5514 memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
5515 memset(c->err_info, 0, sizeof(*c->err_info));
5516 c->busaddr = (u32) cmd_dma_handle;
5517}
5518
592a0ad5
WS		 5519static int hpsa_ioaccel_submit(struct ctlr_info *h,
5520 struct CommandList *c, struct scsi_cmnd *cmd,
5521 unsigned char *scsi3addr)
5522{
5523 struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
5524 int rc = IO_ACCEL_INELIGIBLE;
5525
45e596cd
DB		 5526 if (!dev)
5527 return SCSI_MLQUEUE_HOST_BUSY;
5528
592a0ad5
WS		 5529 cmd->host_scribble = (unsigned char *) c;
5530
5531 if (dev->offload_enabled) {
5532 hpsa_cmd_init(h, c->cmdindex, c);
5533 c->cmd_type = CMD_SCSI;
5534 c->scsi_cmd = cmd;
5535 rc = hpsa_scsi_ioaccel_raid_map(h, c);
5536 if (rc < 0) /* scsi_dma_map failed. */
5537 rc = SCSI_MLQUEUE_HOST_BUSY;
a3144e0b 5538 } else if (dev->hba_ioaccel_enabled) {
592a0ad5
WS		 5539 hpsa_cmd_init(h, c->cmdindex, c);
5540 c->cmd_type = CMD_SCSI;
5541 c->scsi_cmd = cmd;
5542 rc = hpsa_scsi_ioaccel_direct_map(h, c);
5543 if (rc < 0) /* scsi_dma_map failed. */
5544 rc = SCSI_MLQUEUE_HOST_BUSY;
5545 }
5546 return rc;
5547}
5548
080ef1cc
DB		 5549static void hpsa_command_resubmit_worker(struct work_struct *work)
5550{
5551 struct scsi_cmnd *cmd;
5552 struct hpsa_scsi_dev_t *dev;
8a0ff92c 5553 struct CommandList *c = container_of(work, struct CommandList, work);
080ef1cc
DB		 5554
5555 cmd = c->scsi_cmd;
5556 dev = cmd->device->hostdata;
5557 if (!dev) {
5558 cmd->result = DID_NO_CONNECT << 16;
8a0ff92c 5559 return hpsa_cmd_free_and_done(c->h, c, cmd);
080ef1cc 5560 }
d604f533 5561 if (c->reset_pending)
d2315ce6 5562 return hpsa_cmd_free_and_done(c->h, c, cmd);
592a0ad5
WS		 5563 if (c->cmd_type == CMD_IOACCEL2) {
5564 struct ctlr_info *h = c->h;
5565 struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
5566 int rc;
5567
5568 if (c2->error_data.serv_response ==
5569 IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
5570 rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
5571 if (rc == 0)
5572 return;
5573 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
5574 /*
5575 * If we get here, it means dma mapping failed.
5576 * Try again via scsi mid layer, which will
5577 * then get SCSI_MLQUEUE_HOST_BUSY.
5578 */
5579 cmd->result = DID_IMM_RETRY << 16;
8a0ff92c 5580 return hpsa_cmd_free_and_done(h, c, cmd);
592a0ad5
WS		 5581 }
5582 /* else, fall thru and resubmit down CISS path */
5583 }
5584 }
360c73bd 5585 hpsa_cmd_partial_init(c->h, c->cmdindex, c);
080ef1cc
DB		 5586 if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
5587 /*
5588 * If we get here, it means dma mapping failed. Try
5589 * again via scsi mid layer, which will then get
5590 * SCSI_MLQUEUE_HOST_BUSY.
592a0ad5
WS		 5591 *
5592 * hpsa_ciss_submit will have already freed c
5593 * if it encountered a dma mapping failure.
080ef1cc
DB		 5594 */
5595 cmd->result = DID_IMM_RETRY << 16;
5596 cmd->scsi_done(cmd);
5597 }
5598}
5599
574f05d3
SC		 5600/* Running in struct Scsi_Host->host_lock less mode */
5601static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
5602{
5603 struct ctlr_info *h;
5604 struct hpsa_scsi_dev_t *dev;
5605 unsigned char scsi3addr[8];
5606 struct CommandList *c;
5607 int rc = 0;
5608
5609 /* Get the ptr to our adapter structure out of cmd->host. */
5610 h = sdev_to_hba(cmd->device);
73153fe5
WS		 5611
5612 BUG_ON(cmd->request->tag < 0);
5613
574f05d3
SC		 5614 dev = cmd->device->hostdata;
5615 if (!dev) {
1ccde700 5616 cmd->result = DID_NO_CONNECT << 16;
ba74fdc4
DB		 5617 cmd->scsi_done(cmd);
5618 return 0;
5619 }
5620
5621 if (dev->removed) {
574f05d3
SC		 5622 cmd->result = DID_NO_CONNECT << 16;
5623 cmd->scsi_done(cmd);
5624 return 0;
5625 }
574f05d3 5626
73153fe5 5627 memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
bf43caf3 5628
407863cb 5629 if (unlikely(lockup_detected(h))) {
25163bd5 5630 cmd->result = DID_NO_CONNECT << 16;
407863cb
SC		 5631 cmd->scsi_done(cmd);
5632 return 0;
5633 }
73153fe5 5634 c = cmd_tagged_alloc(h, cmd);
574f05d3 5635
407863cb
SC		 5636 /*
5637 * Call alternate submit routine for I/O accelerated commands.
574f05d3
SC		 5638 * Retries always go down the normal I/O path.
5639 */
5640 if (likely(cmd->retries == 0 &&
57292b58
CH		 5641 !blk_rq_is_passthrough(cmd->request) &&
5642 h->acciopath_status)) {
592a0ad5
WS		 5643 rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
5644 if (rc == 0)
5645 return 0;
5646 if (rc == SCSI_MLQUEUE_HOST_BUSY) {
73153fe5 5647 hpsa_cmd_resolve_and_free(h, c);
592a0ad5 5648 return SCSI_MLQUEUE_HOST_BUSY;
574f05d3
SC		 5649 }
5650 }
5651 return hpsa_ciss_submit(h, c, cmd, scsi3addr);
5652}
5653
8ebc9248 5654static void hpsa_scan_complete(struct ctlr_info *h)
5f389360
SC		 5655{
5656 unsigned long flags;
5657
8ebc9248
WS		 5658 spin_lock_irqsave(&h->scan_lock, flags);
5659 h->scan_finished = 1;
87b9e6aa 5660 wake_up(&h->scan_wait_queue);
8ebc9248 5661 spin_unlock_irqrestore(&h->scan_lock, flags);
5f389360
SC		 5662}
5663
a08a8471
SC		 5664static void hpsa_scan_start(struct Scsi_Host *sh)
5665{
5666 struct ctlr_info *h = shost_to_hba(sh);
5667 unsigned long flags;
5668
8ebc9248
WS		 5669 /*
5670 * Don't let rescans be initiated on a controller known to be locked
5671 * up. If the controller locks up *during* a rescan, that thread is
5672 * probably hosed, but at least we can prevent new rescan threads from
5673 * piling up on a locked up controller.
5674 */
5675 if (unlikely(lockup_detected(h)))
5676 return hpsa_scan_complete(h);
5f389360 5677
87b9e6aa
DB		 5678 /*
5679 * If a scan is already waiting to run, no need to add another
5680 */
5681 spin_lock_irqsave(&h->scan_lock, flags);
5682 if (h->scan_waiting) {
5683 spin_unlock_irqrestore(&h->scan_lock, flags);
5684 return;
5685 }
5686
5687 spin_unlock_irqrestore(&h->scan_lock, flags);
5688
a08a8471
SC		 5689 /* wait until any scan already in progress is finished. */
5690 while (1) {
5691 spin_lock_irqsave(&h->scan_lock, flags);
5692 if (h->scan_finished)
5693 break;
87b9e6aa 5694 h->scan_waiting = 1;
a08a8471
SC		 5695 spin_unlock_irqrestore(&h->scan_lock, flags);
5696 wait_event(h->scan_wait_queue, h->scan_finished);
5697 /* Note: We don't need to worry about a race between this
5698 * thread and driver unload because the midlayer will
5699 * have incremented the reference count, so unload won't
5700 * happen if we're in here.
5701 */
5702 }
5703 h->scan_finished = 0; /* mark scan as in progress */
87b9e6aa 5704 h->scan_waiting = 0;
a08a8471
SC		 5705 spin_unlock_irqrestore(&h->scan_lock, flags);
5706
8ebc9248
WS		 5707 if (unlikely(lockup_detected(h)))
5708 return hpsa_scan_complete(h);
5f389360 5709
bfd7546c
DB		 5710 /*
5711 * Do the scan after a reset completion
5712 */
c59d04f3 5713 spin_lock_irqsave(&h->reset_lock, flags);
bfd7546c
DB		 5714 if (h->reset_in_progress) {
5715 h->drv_req_rescan = 1;
c59d04f3 5716 spin_unlock_irqrestore(&h->reset_lock, flags);
3b476aa2 5717 hpsa_scan_complete(h);
bfd7546c
DB		 5718 return;
5719 }
c59d04f3 5720 spin_unlock_irqrestore(&h->reset_lock, flags);
bfd7546c 5721
8aa60681 5722 hpsa_update_scsi_devices(h);
a08a8471 5723
8ebc9248 5724 hpsa_scan_complete(h);
a08a8471
SC		 5725}
5726
7c0a0229
DB		 5727static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
5728{
03383736
DB		 5729 struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
5730
5731 if (!logical_drive)
5732 return -ENODEV;
7c0a0229
DB		 5733
5734 if (qdepth < 1)
5735 qdepth = 1;
03383736
DB		 5736 else if (qdepth > logical_drive->queue_depth)
5737 qdepth = logical_drive->queue_depth;
5738
5739 return scsi_change_queue_depth(sdev, qdepth);
7c0a0229
DB		 5740}
5741
a08a8471
SC		 5742static int hpsa_scan_finished(struct Scsi_Host *sh,
5743 unsigned long elapsed_time)
5744{
5745 struct ctlr_info *h = shost_to_hba(sh);
5746 unsigned long flags;
5747 int finished;
5748
5749 spin_lock_irqsave(&h->scan_lock, flags);
5750 finished = h->scan_finished;
5751 spin_unlock_irqrestore(&h->scan_lock, flags);
5752 return finished;
5753}
5754
2946e82b 5755static int hpsa_scsi_host_alloc(struct ctlr_info *h)
edd16368 5756{
b705690d 5757 struct Scsi_Host *sh;
edd16368 5758
b705690d 5759 sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
2946e82b
RE		 5760 if (sh == NULL) {
5761 dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
5762 return -ENOMEM;
5763 }
b705690d
SC		 5764
5765 sh->io_port = 0;
5766 sh->n_io_port = 0;
5767 sh->this_id = -1;
5768 sh->max_channel = 3;
5769 sh->max_cmd_len = MAX_COMMAND_SIZE;
5770 sh->max_lun = HPSA_MAX_LUN;
5771 sh->max_id = HPSA_MAX_LUN;
41ce4c35 5772 sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
03383736 5773 sh->cmd_per_lun = sh->can_queue;
b705690d 5774 sh->sg_tablesize = h->maxsgentries;
d04e62b9 5775 sh->transportt = hpsa_sas_transport_template;
b705690d 5776 sh->hostdata[0] = (unsigned long) h;
bc2bb154 5777 sh->irq = pci_irq_vector(h->pdev, 0);
b705690d 5778 sh->unique_id = sh->irq;
64d513ac 5779
2946e82b 5780 h->scsi_host = sh;
b705690d 5781 return 0;
2946e82b 5782}
b705690d 5783
2946e82b
RE		 5784static int hpsa_scsi_add_host(struct ctlr_info *h)
5785{
5786 int rv;
5787
5788 rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
5789 if (rv) {
5790 dev_err(&h->pdev->dev, "scsi_add_host failed\n");
5791 return rv;
5792 }
5793 scsi_scan_host(h->scsi_host);
5794 return 0;
edd16368
SC		 5795}
5796
73153fe5
WS		 5797/*
5798 * The block layer has already gone to the trouble of picking out a unique,
5799 * small-integer tag for this request. We use an offset from that value as
5800 * an index to select our command block. (The offset allows us to reserve the
5801 * low-numbered entries for our own uses.)
5802 */
5803static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
5804{
5805 int idx = scmd->request->tag;
5806
5807 if (idx < 0)
5808 return idx;
5809
5810 /* Offset to leave space for internal cmds. */
5811 return idx += HPSA_NRESERVED_CMDS;
5812}
5813
b69324ff
WS		 5814/*
5815 * Send a TEST_UNIT_READY command to the specified LUN using the specified
5816 * reply queue; returns zero if the unit is ready, and non-zero otherwise.
5817 */
5818static int hpsa_send_test_unit_ready(struct ctlr_info *h,
5819 struct CommandList *c, unsigned char lunaddr[],
5820 int reply_queue)
5821{
5822 int rc;
5823
5824 /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
5825 (void) fill_cmd(c, TEST_UNIT_READY, h,
5826 NULL, 0, 0, lunaddr, TYPE_CMD);
1edb6934 5827 rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
b69324ff
WS		 5828 if (rc)
5829 return rc;
5830 /* no unmap needed here because no data xfer. */
5831
5832 /* Check if the unit is already ready. */
5833 if (c->err_info->CommandStatus == CMD_SUCCESS)
5834 return 0;
5835
5836 /*
5837 * The first command sent after reset will receive "unit attention" to
5838 * indicate that the LUN has been reset...this is actually what we're
5839 * looking for (but, success is good too).
5840 */
5841 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
5842 c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
5843 (c->err_info->SenseInfo[2] == NO_SENSE ||
5844 c->err_info->SenseInfo[2] == UNIT_ATTENTION))
5845 return 0;
5846
5847 return 1;
5848}
5849
5850/*
5851 * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
5852 * returns zero when the unit is ready, and non-zero when giving up.
5853 */
5854static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
5855 struct CommandList *c,
5856 unsigned char lunaddr[], int reply_queue)
edd16368 5857{
8919358e 5858 int rc;
edd16368
SC		 5859 int count = 0;
5860 int waittime = 1; /* seconds */
edd16368
SC		 5861
5862 /* Send test unit ready until device ready, or give up. */
b69324ff 5863 for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
edd16368 5864
b69324ff
WS		 5865 /*
5866 * Wait for a bit. do this first, because if we send
edd16368
SC		 5867 * the TUR right away, the reset will just abort it.
5868 */
5869 msleep(1000 * waittime);
b69324ff
WS		 5870
5871 rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
5872 if (!rc)
5873 break;
edd16368
SC		 5874
5875 /* Increase wait time with each try, up to a point. */
5876 if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
b69324ff 5877 waittime *= 2;
edd16368 5878
b69324ff
WS		 5879 dev_warn(&h->pdev->dev,
5880 "waiting %d secs for device to become ready.\n",
5881 waittime);
5882 }
edd16368 5883
b69324ff
WS		 5884 return rc;
5885}
edd16368 5886
b69324ff
WS		 5887static int wait_for_device_to_become_ready(struct ctlr_info *h,
5888 unsigned char lunaddr[],
5889 int reply_queue)
5890{
5891 int first_queue;
5892 int last_queue;
5893 int rq;
5894 int rc = 0;
5895 struct CommandList *c;
5896
5897 c = cmd_alloc(h);
5898
5899 /*
5900 * If no specific reply queue was requested, then send the TUR
5901 * repeatedly, requesting a reply on each reply queue; otherwise execute
5902 * the loop exactly once using only the specified queue.
5903 */
5904 if (reply_queue == DEFAULT_REPLY_QUEUE) {
5905 first_queue = 0;
5906 last_queue = h->nreply_queues - 1;
5907 } else {
5908 first_queue = reply_queue;
5909 last_queue = reply_queue;
5910 }
5911
5912 for (rq = first_queue; rq <= last_queue; rq++) {
5913 rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
5914 if (rc)
edd16368 5915 break;
edd16368
SC		 5916 }
5917
5918 if (rc)
5919 dev_warn(&h->pdev->dev, "giving up on device.\n");
5920 else
5921 dev_warn(&h->pdev->dev, "device is ready.\n");
5922
45fcb86e 5923 cmd_free(h, c);
edd16368
SC		 5924 return rc;
5925}
5926
5927/* Need at least one of these error handlers to keep ../scsi/hosts.c from
5928 * complaining. Doing a host- or bus-reset can't do anything good here.
5929 */
5930static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
5931{
c59d04f3 5932 int rc = SUCCESS;
edd16368
SC		 5933 struct ctlr_info *h;
5934 struct hpsa_scsi_dev_t *dev;
0b9b7b6e 5935 u8 reset_type;
2dc127bb 5936 char msg[48];
c59d04f3 5937 unsigned long flags;
edd16368
SC		 5938
5939 /* find the controller to which the command to be aborted was sent */
5940 h = sdev_to_hba(scsicmd->device);
5941 if (h == NULL) /* paranoia */
5942 return FAILED;
e345893b 5943
c59d04f3
DB		 5944 spin_lock_irqsave(&h->reset_lock, flags);
5945 h->reset_in_progress = 1;
5946 spin_unlock_irqrestore(&h->reset_lock, flags);
5947
5948 if (lockup_detected(h)) {
5949 rc = FAILED;
5950 goto return_reset_status;
5951 }
e345893b 5952
edd16368
SC		 5953 dev = scsicmd->device->hostdata;
5954 if (!dev) {
d604f533 5955 dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
c59d04f3
DB		 5956 rc = FAILED;
5957 goto return_reset_status;
edd16368 5958 }
25163bd5 5959
c59d04f3
DB		 5960 if (dev->devtype == TYPE_ENCLOSURE) {
5961 rc = SUCCESS;
5962 goto return_reset_status;
5963 }
ef8a5203 5964
25163bd5
WS		 5965 /* if controller locked up, we can guarantee command won't complete */
5966 if (lockup_detected(h)) {
2dc127bb
DC		 5967 snprintf(msg, sizeof(msg),
5968 "cmd %d RESET FAILED, lockup detected",
5969 hpsa_get_cmd_index(scsicmd));
73153fe5 5970 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
c59d04f3
DB		 5971 rc = FAILED;
5972 goto return_reset_status;
25163bd5
WS		 5973 }
5974
5975 /* this reset request might be the result of a lockup; check */
5976 if (detect_controller_lockup(h)) {
2dc127bb
DC		 5977 snprintf(msg, sizeof(msg),
5978 "cmd %d RESET FAILED, new lockup detected",
5979 hpsa_get_cmd_index(scsicmd));
73153fe5 5980 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
c59d04f3
DB		 5981 rc = FAILED;
5982 goto return_reset_status;
25163bd5
WS		 5983 }
5984
d604f533 5985 /* Do not attempt on controller */
c59d04f3
DB		 5986 if (is_hba_lunid(dev->scsi3addr)) {
5987 rc = SUCCESS;
5988 goto return_reset_status;
5989 }
d604f533 5990
0b9b7b6e
ST		 5991 if (is_logical_dev_addr_mode(dev->scsi3addr))
5992 reset_type = HPSA_DEVICE_RESET_MSG;
5993 else
5994 reset_type = HPSA_PHYS_TARGET_RESET;
5995
5996 sprintf(msg, "resetting %s",
5997 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ");
5998 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
25163bd5 5999
edd16368 6000 /* send a reset to the SCSI LUN which the command was sent to */
0b9b7b6e 6001 rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type,
d604f533 6002 DEFAULT_REPLY_QUEUE);
c59d04f3
DB		 6003 if (rc == 0)
6004 rc = SUCCESS;
6005 else
6006 rc = FAILED;
6007
0b9b7b6e
ST		 6008 sprintf(msg, "reset %s %s",
6009 reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ",
c59d04f3 6010 rc == SUCCESS ? "completed successfully" : "failed");
d604f533 6011 hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
c59d04f3
DB		 6012
6013return_reset_status:
6014 spin_lock_irqsave(&h->reset_lock, flags);
da03ded0 6015 h->reset_in_progress = 0;
c59d04f3
DB		 6016 spin_unlock_irqrestore(&h->reset_lock, flags);
6017 return rc;
edd16368
SC		 6018}
6019
73153fe5
WS		 6020/*
6021 * For operations with an associated SCSI command, a command block is allocated
6022 * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
6023 * block request tag as an index into a table of entries. cmd_tagged_free() is
6024 * the complement, although cmd_free() may be called instead.
6025 */
6026static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
6027 struct scsi_cmnd *scmd)
6028{
6029 int idx = hpsa_get_cmd_index(scmd);
6030 struct CommandList *c = h->cmd_pool + idx;
6031
6032 if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
6033 dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
6034 idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
6035 /* The index value comes from the block layer, so if it's out of
6036 * bounds, it's probably not our bug.
6037 */
6038 BUG();
6039 }
6040
6041 atomic_inc(&c->refcount);
6042 if (unlikely(!hpsa_is_cmd_idle(c))) {
6043 /*
6044 * We expect that the SCSI layer will hand us a unique tag
6045 * value. Thus, there should never be a collision here between
6046 * two requests...because if the selected command isn't idle
6047 * then someone is going to be very disappointed.
6048 */
6049 dev_err(&h->pdev->dev,
6050 "tag collision (tag=%d) in cmd_tagged_alloc().\n",
6051 idx);
6052 if (c->scsi_cmd != NULL)
6053 scsi_print_command(c->scsi_cmd);
6054 scsi_print_command(scmd);
6055 }
6056
6057 hpsa_cmd_partial_init(h, idx, c);
6058 return c;
6059}
6060
6061static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
6062{
6063 /*
6064 * Release our reference to the block. We don't need to do anything
08ec46f6 6065 * else to free it, because it is accessed by index.
73153fe5
WS		 6066 */
6067 (void)atomic_dec(&c->refcount);
6068}
6069
edd16368
SC		 6070/*
6071 * For operations that cannot sleep, a command block is allocated at init,
6072 * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
6073 * which ones are free or in use. Lock must be held when calling this.
6074 * cmd_free() is the complement.
bf43caf3
RE		 6075 * This function never gives up and returns NULL. If it hangs,
6076 * another thread must call cmd_free() to free some tags.
edd16368 6077 */
281a7fd0 6078
edd16368
SC		 6079static struct CommandList *cmd_alloc(struct ctlr_info *h)
6080{
6081 struct CommandList *c;
360c73bd 6082 int refcount, i;
73153fe5 6083 int offset = 0;
4c413128 6084
33811026
RE		 6085 /*
6086 * There is some *extremely* small but non-zero chance that that
4c413128
SC		 6087 * multiple threads could get in here, and one thread could
6088 * be scanning through the list of bits looking for a free
6089 * one, but the free ones are always behind him, and other
6090 * threads sneak in behind him and eat them before he can
6091 * get to them, so that while there is always a free one, a
6092 * very unlucky thread might be starved anyway, never able to
6093 * beat the other threads. In reality, this happens so
6094 * infrequently as to be indistinguishable from never.
73153fe5
WS		 6095 *
6096 * Note that we start allocating commands before the SCSI host structure
6097 * is initialized. Since the search starts at bit zero, this
6098 * all works, since we have at least one command structure available;
6099 * however, it means that the structures with the low indexes have to be
6100 * reserved for driver-initiated requests, while requests from the block
6101 * layer will use the higher indexes.
4c413128 6102 */
edd16368 6103
281a7fd0 6104 for (;;) {
73153fe5
WS		 6105 i = find_next_zero_bit(h->cmd_pool_bits,
6106 HPSA_NRESERVED_CMDS,
6107 offset);
6108 if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
281a7fd0
WS		 6109 offset = 0;
6110 continue;
6111 }
6112 c = h->cmd_pool + i;
6113 refcount = atomic_inc_return(&c->refcount);
6114 if (unlikely(refcount > 1)) {
6115 cmd_free(h, c); /* already in use */
73153fe5 6116 offset = (i + 1) % HPSA_NRESERVED_CMDS;
281a7fd0
WS		 6117 continue;
6118 }
6119 set_bit(i & (BITS_PER_LONG - 1),
6120 h->cmd_pool_bits + (i / BITS_PER_LONG));
6121 break; /* it's ours now. */
6122 }
360c73bd 6123 hpsa_cmd_partial_init(h, i, c);
edd16368
SC		 6124 return c;
6125}
6126
73153fe5
WS		 6127/*
6128 * This is the complementary operation to cmd_alloc(). Note, however, in some
6129 * corner cases it may also be used to free blocks allocated by
6130 * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
6131 * the clear-bit is harmless.
6132 */
edd16368
SC		 6133static void cmd_free(struct ctlr_info *h, struct CommandList *c)
6134{
281a7fd0
WS		 6135 if (atomic_dec_and_test(&c->refcount)) {
6136 int i;
edd16368 6137
281a7fd0
WS		 6138 i = c - h->cmd_pool;
6139 clear_bit(i & (BITS_PER_LONG - 1),
6140 h->cmd_pool_bits + (i / BITS_PER_LONG));
6141 }
edd16368
SC		 6142}
6143
edd16368
SC		 6144#ifdef CONFIG_COMPAT
6145
6f4e626f 6146static int hpsa_ioctl32_passthru(struct scsi_device *dev, unsigned int cmd,
42a91641 6147 void __user *arg)
edd16368
SC		 6148{
6149 IOCTL32_Command_struct __user *arg32 =
6150 (IOCTL32_Command_struct __user *) arg;
6151 IOCTL_Command_struct arg64;
6152 IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
6153 int err;
6154 u32 cp;
6155
938abd84 6156 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 6157 err = 0;
6158 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
6159 sizeof(arg64.LUN_info));
6160 err |= copy_from_user(&arg64.Request, &arg32->Request,
6161 sizeof(arg64.Request));
6162 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
6163 sizeof(arg64.error_info));
6164 err |= get_user(arg64.buf_size, &arg32->buf_size);
6165 err |= get_user(cp, &arg32->buf);
6166 arg64.buf = compat_ptr(cp);
6167 err |= copy_to_user(p, &arg64, sizeof(arg64));
6168
6169 if (err)
6170 return -EFAULT;
6171
42a91641 6172 err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
edd16368
SC		 6173 if (err)
6174 return err;
6175 err |= copy_in_user(&arg32->error_info, &p->error_info,
6176 sizeof(arg32->error_info));
6177 if (err)
6178 return -EFAULT;
6179 return err;
6180}
6181
6182static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
6f4e626f 6183 unsigned int cmd, void __user *arg)
edd16368
SC		 6184{
6185 BIG_IOCTL32_Command_struct __user *arg32 =
6186 (BIG_IOCTL32_Command_struct __user *) arg;
6187 BIG_IOCTL_Command_struct arg64;
6188 BIG_IOCTL_Command_struct __user *p =
6189 compat_alloc_user_space(sizeof(arg64));
6190 int err;
6191 u32 cp;
6192
938abd84 6193 memset(&arg64, 0, sizeof(arg64));
edd16368
SC		 6194 err = 0;
6195 err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
6196 sizeof(arg64.LUN_info));
6197 err |= copy_from_user(&arg64.Request, &arg32->Request,
6198 sizeof(arg64.Request));
6199 err |= copy_from_user(&arg64.error_info, &arg32->error_info,
6200 sizeof(arg64.error_info));
6201 err |= get_user(arg64.buf_size, &arg32->buf_size);
6202 err |= get_user(arg64.malloc_size, &arg32->malloc_size);
6203 err |= get_user(cp, &arg32->buf);
6204 arg64.buf = compat_ptr(cp);
6205 err |= copy_to_user(p, &arg64, sizeof(arg64));
6206
6207 if (err)
6208 return -EFAULT;
6209
42a91641 6210 err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
edd16368
SC		 6211 if (err)
6212 return err;
6213 err |= copy_in_user(&arg32->error_info, &p->error_info,
6214 sizeof(arg32->error_info));
6215 if (err)
6216 return -EFAULT;
6217 return err;
6218}
71fe75a7 6219
6f4e626f
NC		 6220static int hpsa_compat_ioctl(struct scsi_device *dev, unsigned int cmd,
6221 void __user *arg)
71fe75a7
SC		 6222{
6223 switch (cmd) {
6224 case CCISS_GETPCIINFO:
6225 case CCISS_GETINTINFO:
6226 case CCISS_SETINTINFO:
6227 case CCISS_GETNODENAME:
6228 case CCISS_SETNODENAME:
6229 case CCISS_GETHEARTBEAT:
6230 case CCISS_GETBUSTYPES:
6231 case CCISS_GETFIRMVER:
6232 case CCISS_GETDRIVVER:
6233 case CCISS_REVALIDVOLS:
6234 case CCISS_DEREGDISK:
6235 case CCISS_REGNEWDISK:
6236 case CCISS_REGNEWD:
6237 case CCISS_RESCANDISK:
6238 case CCISS_GETLUNINFO:
6239 return hpsa_ioctl(dev, cmd, arg);
6240
6241 case CCISS_PASSTHRU32:
6242 return hpsa_ioctl32_passthru(dev, cmd, arg);
6243 case CCISS_BIG_PASSTHRU32:
6244 return hpsa_ioctl32_big_passthru(dev, cmd, arg);
6245
6246 default:
6247 return -ENOIOCTLCMD;
6248 }
6249}
edd16368
SC		 6250#endif
6251
6252static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
6253{
6254 struct hpsa_pci_info pciinfo;
6255
6256 if (!argp)
6257 return -EINVAL;
6258 pciinfo.domain = pci_domain_nr(h->pdev->bus);
6259 pciinfo.bus = h->pdev->bus->number;
6260 pciinfo.dev_fn = h->pdev->devfn;
6261 pciinfo.board_id = h->board_id;
6262 if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
6263 return -EFAULT;
6264 return 0;
6265}
6266
6267static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
6268{
6269 DriverVer_type DriverVer;
6270 unsigned char vmaj, vmin, vsubmin;
6271 int rc;
6272
6273 rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
6274 &vmaj, &vmin, &vsubmin);
6275 if (rc != 3) {
6276 dev_info(&h->pdev->dev, "driver version string '%s' "
6277 "unrecognized.", HPSA_DRIVER_VERSION);
6278 vmaj = 0;
6279 vmin = 0;
6280 vsubmin = 0;
6281 }
6282 DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
6283 if (!argp)
6284 return -EINVAL;
6285 if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
6286 return -EFAULT;
6287 return 0;
6288}
6289
6290static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6291{
6292 IOCTL_Command_struct iocommand;
6293 struct CommandList *c;
6294 char *buff = NULL;
50a0decf 6295 u64 temp64;
c1f63c8f 6296 int rc = 0;
edd16368
SC		 6297
6298 if (!argp)
6299 return -EINVAL;
6300 if (!capable(CAP_SYS_RAWIO))
6301 return -EPERM;
6302 if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
6303 return -EFAULT;
6304 if ((iocommand.buf_size < 1) &&
6305 (iocommand.Request.Type.Direction != XFER_NONE)) {
6306 return -EINVAL;
6307 }
6308 if (iocommand.buf_size > 0) {
6309 buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
6310 if (buff == NULL)
2dd02d74 6311 return -ENOMEM;
9233fb10 6312 if (iocommand.Request.Type.Direction & XFER_WRITE) {
b03a7771
SC		 6313 /* Copy the data into the buffer we created */
6314 if (copy_from_user(buff, iocommand.buf,
6315 iocommand.buf_size)) {
c1f63c8f
SC		 6316 rc = -EFAULT;
6317 goto out_kfree;
b03a7771
SC		 6318 }
6319 } else {
6320 memset(buff, 0, iocommand.buf_size);
edd16368 6321 }
b03a7771 6322 }
45fcb86e 6323 c = cmd_alloc(h);
bf43caf3 6324
edd16368
SC		 6325 /* Fill in the command type */
6326 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6327 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6328 /* Fill in Command Header */
6329 c->Header.ReplyQueue = 0; /* unused in simple mode */
6330 if (iocommand.buf_size > 0) { /* buffer to fill */
6331 c->Header.SGList = 1;
50a0decf 6332 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6333 } else { /* no buffers to fill */
6334 c->Header.SGList = 0;
50a0decf 6335 c->Header.SGTotal = cpu_to_le16(0);
edd16368
SC		 6336 }
6337 memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6338
6339 /* Fill in Request block */
6340 memcpy(&c->Request, &iocommand.Request,
6341 sizeof(c->Request));
6342
6343 /* Fill in the scatter gather information */
6344 if (iocommand.buf_size > 0) {
8bc8f47e
CH		 6345 temp64 = dma_map_single(&h->pdev->dev, buff,
6346 iocommand.buf_size, DMA_BIDIRECTIONAL);
50a0decf
SC		 6347 if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
6348 c->SG[0].Addr = cpu_to_le64(0);
6349 c->SG[0].Len = cpu_to_le32(0);
bcc48ffa
SC		 6350 rc = -ENOMEM;
6351 goto out;
6352 }
50a0decf
SC		 6353 c->SG[0].Addr = cpu_to_le64(temp64);
6354 c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
6355 c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
edd16368 6356 }
c448ecfa 6357 rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
3fb134cb 6358 NO_TIMEOUT);
c2dd32e0 6359 if (iocommand.buf_size > 0)
8bc8f47e 6360 hpsa_pci_unmap(h->pdev, c, 1, DMA_BIDIRECTIONAL);
edd16368 6361 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6362 if (rc) {
6363 rc = -EIO;
6364 goto out;
6365 }
edd16368
SC		 6366
6367 /* Copy the error information out */
6368 memcpy(&iocommand.error_info, c->err_info,
6369 sizeof(iocommand.error_info));
6370 if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
c1f63c8f
SC		 6371 rc = -EFAULT;
6372 goto out;
edd16368 6373 }
9233fb10 6374 if ((iocommand.Request.Type.Direction & XFER_READ) &&
b03a7771 6375 iocommand.buf_size > 0) {
edd16368
SC		 6376 /* Copy the data out of the buffer we created */
6377 if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
c1f63c8f
SC		 6378 rc = -EFAULT;
6379 goto out;
edd16368
SC		 6380 }
6381 }
c1f63c8f 6382out:
45fcb86e 6383 cmd_free(h, c);
c1f63c8f
SC		 6384out_kfree:
6385 kfree(buff);
6386 return rc;
edd16368
SC		 6387}
6388
6389static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
6390{
6391 BIG_IOCTL_Command_struct *ioc;
6392 struct CommandList *c;
6393 unsigned char **buff = NULL;
6394 int *buff_size = NULL;
50a0decf 6395 u64 temp64;
edd16368
SC		 6396 BYTE sg_used = 0;
6397 int status = 0;
01a02ffc
SC		 6398 u32 left;
6399 u32 sz;
edd16368
SC		 6400 BYTE __user *data_ptr;
6401
6402 if (!argp)
6403 return -EINVAL;
6404 if (!capable(CAP_SYS_RAWIO))
6405 return -EPERM;
048a864e 6406 ioc = vmemdup_user(argp, sizeof(*ioc));
6407 if (IS_ERR(ioc)) {
6408 status = PTR_ERR(ioc);
edd16368
SC		 6409 goto cleanup1;
6410 }
6411 if ((ioc->buf_size < 1) &&
6412 (ioc->Request.Type.Direction != XFER_NONE)) {
6413 status = -EINVAL;
6414 goto cleanup1;
6415 }
6416 /* Check kmalloc limits using all SGs */
6417 if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
6418 status = -EINVAL;
6419 goto cleanup1;
6420 }
d66ae08b 6421 if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
edd16368
SC		 6422 status = -EINVAL;
6423 goto cleanup1;
6424 }
6396bb22 6425 buff = kcalloc(SG_ENTRIES_IN_CMD, sizeof(char *), GFP_KERNEL);
edd16368
SC		 6426 if (!buff) {
6427 status = -ENOMEM;
6428 goto cleanup1;
6429 }
6da2ec56 6430 buff_size = kmalloc_array(SG_ENTRIES_IN_CMD, sizeof(int), GFP_KERNEL);
edd16368
SC		 6431 if (!buff_size) {
6432 status = -ENOMEM;
6433 goto cleanup1;
6434 }
6435 left = ioc->buf_size;
6436 data_ptr = ioc->buf;
6437 while (left) {
6438 sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
6439 buff_size[sg_used] = sz;
6440 buff[sg_used] = kmalloc(sz, GFP_KERNEL);
6441 if (buff[sg_used] == NULL) {
6442 status = -ENOMEM;
6443 goto cleanup1;
6444 }
9233fb10 6445 if (ioc->Request.Type.Direction & XFER_WRITE) {
edd16368 6446 if (copy_from_user(buff[sg_used], data_ptr, sz)) {
0758f4f7 6447 status = -EFAULT;
edd16368
SC		 6448 goto cleanup1;
6449 }
6450 } else
6451 memset(buff[sg_used], 0, sz);
6452 left -= sz;
6453 data_ptr += sz;
6454 sg_used++;
6455 }
45fcb86e 6456 c = cmd_alloc(h);
bf43caf3 6457
edd16368 6458 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6459 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368 6460 c->Header.ReplyQueue = 0;
50a0decf
SC		 6461 c->Header.SGList = (u8) sg_used;
6462 c->Header.SGTotal = cpu_to_le16(sg_used);
edd16368 6463 memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
edd16368
SC		 6464 memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
6465 if (ioc->buf_size > 0) {
6466 int i;
6467 for (i = 0; i < sg_used; i++) {
8bc8f47e
CH		 6468 temp64 = dma_map_single(&h->pdev->dev, buff[i],
6469 buff_size[i], DMA_BIDIRECTIONAL);
50a0decf
SC		 6470 if (dma_mapping_error(&h->pdev->dev,
6471 (dma_addr_t) temp64)) {
6472 c->SG[i].Addr = cpu_to_le64(0);
6473 c->SG[i].Len = cpu_to_le32(0);
bcc48ffa 6474 hpsa_pci_unmap(h->pdev, c, i,
8bc8f47e 6475 DMA_BIDIRECTIONAL);
bcc48ffa 6476 status = -ENOMEM;
e2d4a1f6 6477 goto cleanup0;
bcc48ffa 6478 }
50a0decf
SC		 6479 c->SG[i].Addr = cpu_to_le64(temp64);
6480 c->SG[i].Len = cpu_to_le32(buff_size[i]);
6481 c->SG[i].Ext = cpu_to_le32(0);
edd16368 6482 }
50a0decf 6483 c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
edd16368 6484 }
c448ecfa 6485 status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
3fb134cb 6486 NO_TIMEOUT);
b03a7771 6487 if (sg_used)
8bc8f47e 6488 hpsa_pci_unmap(h->pdev, c, sg_used, DMA_BIDIRECTIONAL);
edd16368 6489 check_ioctl_unit_attention(h, c);
25163bd5
WS		 6490 if (status) {
6491 status = -EIO;
6492 goto cleanup0;
6493 }
6494
edd16368
SC		 6495 /* Copy the error information out */
6496 memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
6497 if (copy_to_user(argp, ioc, sizeof(*ioc))) {
edd16368 6498 status = -EFAULT;
e2d4a1f6 6499 goto cleanup0;
edd16368 6500 }
9233fb10 6501 if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
2b08b3e9
DB		 6502 int i;
6503
edd16368
SC		 6504 /* Copy the data out of the buffer we created */
6505 BYTE __user *ptr = ioc->buf;
6506 for (i = 0; i < sg_used; i++) {
6507 if (copy_to_user(ptr, buff[i], buff_size[i])) {
edd16368 6508 status = -EFAULT;
e2d4a1f6 6509 goto cleanup0;
edd16368
SC		 6510 }
6511 ptr += buff_size[i];
6512 }
6513 }
edd16368 6514 status = 0;
e2d4a1f6 6515cleanup0:
45fcb86e 6516 cmd_free(h, c);
edd16368
SC		 6517cleanup1:
6518 if (buff) {
2b08b3e9
DB		 6519 int i;
6520
edd16368
SC		 6521 for (i = 0; i < sg_used; i++)
6522 kfree(buff[i]);
6523 kfree(buff);
6524 }
6525 kfree(buff_size);
048a864e 6526 kvfree(ioc);
edd16368
SC		 6527 return status;
6528}
6529
6530static void check_ioctl_unit_attention(struct ctlr_info *h,
6531 struct CommandList *c)
6532{
6533 if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
6534 c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
6535 (void) check_for_unit_attention(h, c);
6536}
0390f0c0 6537
edd16368
SC		 6538/*
6539 * ioctl
6540 */
6f4e626f
NC		 6541static int hpsa_ioctl(struct scsi_device *dev, unsigned int cmd,
6542 void __user *arg)
edd16368
SC		 6543{
6544 struct ctlr_info *h;
6545 void __user *argp = (void __user *)arg;
0390f0c0 6546 int rc;
edd16368
SC		 6547
6548 h = sdev_to_hba(dev);
6549
6550 switch (cmd) {
6551 case CCISS_DEREGDISK:
6552 case CCISS_REGNEWDISK:
6553 case CCISS_REGNEWD:
a08a8471 6554 hpsa_scan_start(h->scsi_host);
edd16368
SC		 6555 return 0;
6556 case CCISS_GETPCIINFO:
6557 return hpsa_getpciinfo_ioctl(h, argp);
6558 case CCISS_GETDRIVVER:
6559 return hpsa_getdrivver_ioctl(h, argp);
6560 case CCISS_PASSTHRU:
34f0c627 6561 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6562 return -EAGAIN;
6563 rc = hpsa_passthru_ioctl(h, argp);
34f0c627 6564 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6565 return rc;
edd16368 6566 case CCISS_BIG_PASSTHRU:
34f0c627 6567 if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
0390f0c0
SC		 6568 return -EAGAIN;
6569 rc = hpsa_big_passthru_ioctl(h, argp);
34f0c627 6570 atomic_inc(&h->passthru_cmds_avail);
0390f0c0 6571 return rc;
edd16368
SC		 6572 default:
6573 return -ENOTTY;
6574 }
6575}
6576
bf43caf3 6577static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
6f039790 6578 u8 reset_type)
64670ac8
SC		 6579{
6580 struct CommandList *c;
6581
6582 c = cmd_alloc(h);
bf43caf3 6583
a2dac136
SC		 6584 /* fill_cmd can't fail here, no data buffer to map */
6585 (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
64670ac8
SC		 6586 RAID_CTLR_LUNID, TYPE_MSG);
6587 c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
6588 c->waiting = NULL;
6589 enqueue_cmd_and_start_io(h, c);
6590 /* Don't wait for completion, the reset won't complete. Don't free
6591 * the command either. This is the last command we will send before
6592 * re-initializing everything, so it doesn't matter and won't leak.
6593 */
bf43caf3 6594 return;
64670ac8
SC		 6595}
6596
a2dac136 6597static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
b7bb24eb 6598 void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
edd16368
SC		 6599 int cmd_type)
6600{
8bc8f47e 6601 enum dma_data_direction dir = DMA_NONE;
edd16368
SC		 6602
6603 c->cmd_type = CMD_IOCTL_PEND;
a58e7e53 6604 c->scsi_cmd = SCSI_CMD_BUSY;
edd16368
SC		 6605 c->Header.ReplyQueue = 0;
6606 if (buff != NULL && size > 0) {
6607 c->Header.SGList = 1;
50a0decf 6608 c->Header.SGTotal = cpu_to_le16(1);
edd16368
SC		 6609 } else {
6610 c->Header.SGList = 0;
50a0decf 6611 c->Header.SGTotal = cpu_to_le16(0);
edd16368 6612 }
edd16368
SC		 6613 memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
6614
edd16368
SC		 6615 if (cmd_type == TYPE_CMD) {
6616 switch (cmd) {
6617 case HPSA_INQUIRY:
6618 /* are we trying to read a vital product page */
b7bb24eb 6619 if (page_code & VPD_PAGE) {
edd16368 6620 c->Request.CDB[1] = 0x01;
b7bb24eb 6621 c->Request.CDB[2] = (page_code & 0xff);
edd16368
SC		 6622 }
6623 c->Request.CDBLen = 6;
a505b86f
SC		 6624 c->Request.type_attr_dir =
6625 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6626 c->Request.Timeout = 0;
6627 c->Request.CDB[0] = HPSA_INQUIRY;
6628 c->Request.CDB[4] = size & 0xFF;
6629 break;
0a7c3bb8
DB		 6630 case RECEIVE_DIAGNOSTIC:
6631 c->Request.CDBLen = 6;
6632 c->Request.type_attr_dir =
6633 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6634 c->Request.Timeout = 0;
6635 c->Request.CDB[0] = cmd;
6636 c->Request.CDB[1] = 1;
6637 c->Request.CDB[2] = 1;
6638 c->Request.CDB[3] = (size >> 8) & 0xFF;
6639 c->Request.CDB[4] = size & 0xFF;
6640 break;
edd16368
SC		 6641 case HPSA_REPORT_LOG:
6642 case HPSA_REPORT_PHYS:
6643 /* Talking to controller so It's a physical command
6644 mode = 00 target = 0. Nothing to write.
6645 */
6646 c->Request.CDBLen = 12;
a505b86f
SC		 6647 c->Request.type_attr_dir =
6648 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
edd16368
SC		 6649 c->Request.Timeout = 0;
6650 c->Request.CDB[0] = cmd;
6651 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6652 c->Request.CDB[7] = (size >> 16) & 0xFF;
6653 c->Request.CDB[8] = (size >> 8) & 0xFF;
6654 c->Request.CDB[9] = size & 0xFF;
6655 break;
c2adae44
ST		 6656 case BMIC_SENSE_DIAG_OPTIONS:
6657 c->Request.CDBLen = 16;
6658 c->Request.type_attr_dir =
6659 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6660 c->Request.Timeout = 0;
6661 /* Spec says this should be BMIC_WRITE */
6662 c->Request.CDB[0] = BMIC_READ;
6663 c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS;
6664 break;
6665 case BMIC_SET_DIAG_OPTIONS:
6666 c->Request.CDBLen = 16;
6667 c->Request.type_attr_dir =
6668 TYPE_ATTR_DIR(cmd_type,
6669 ATTR_SIMPLE, XFER_WRITE);
6670 c->Request.Timeout = 0;
6671 c->Request.CDB[0] = BMIC_WRITE;
6672 c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS;
6673 break;
edd16368
SC		 6674 case HPSA_CACHE_FLUSH:
6675 c->Request.CDBLen = 12;
a505b86f
SC		 6676 c->Request.type_attr_dir =
6677 TYPE_ATTR_DIR(cmd_type,
6678 ATTR_SIMPLE, XFER_WRITE);
edd16368
SC		 6679 c->Request.Timeout = 0;
6680 c->Request.CDB[0] = BMIC_WRITE;
6681 c->Request.CDB[6] = BMIC_CACHE_FLUSH;
bb158eab
SC		 6682 c->Request.CDB[7] = (size >> 8) & 0xFF;
6683 c->Request.CDB[8] = size & 0xFF;
edd16368
SC		 6684 break;
6685 case TEST_UNIT_READY:
6686 c->Request.CDBLen = 6;
a505b86f
SC		 6687 c->Request.type_attr_dir =
6688 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368
SC		 6689 c->Request.Timeout = 0;
6690 break;
283b4a9b
SC		 6691 case HPSA_GET_RAID_MAP:
6692 c->Request.CDBLen = 12;
a505b86f
SC		 6693 c->Request.type_attr_dir =
6694 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
283b4a9b
SC		 6695 c->Request.Timeout = 0;
6696 c->Request.CDB[0] = HPSA_CISS_READ;
6697 c->Request.CDB[1] = cmd;
6698 c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
6699 c->Request.CDB[7] = (size >> 16) & 0xFF;
6700 c->Request.CDB[8] = (size >> 8) & 0xFF;
6701 c->Request.CDB[9] = size & 0xFF;
6702 break;
316b221a
SC		 6703 case BMIC_SENSE_CONTROLLER_PARAMETERS:
6704 c->Request.CDBLen = 10;
a505b86f
SC		 6705 c->Request.type_attr_dir =
6706 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
316b221a
SC		 6707 c->Request.Timeout = 0;
6708 c->Request.CDB[0] = BMIC_READ;
6709 c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
6710 c->Request.CDB[7] = (size >> 16) & 0xFF;
6711 c->Request.CDB[8] = (size >> 8) & 0xFF;
6712 break;
03383736
DB		 6713 case BMIC_IDENTIFY_PHYSICAL_DEVICE:
6714 c->Request.CDBLen = 10;
6715 c->Request.type_attr_dir =
6716 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6717 c->Request.Timeout = 0;
6718 c->Request.CDB[0] = BMIC_READ;
6719 c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
6720 c->Request.CDB[7] = (size >> 16) & 0xFF;
6721 c->Request.CDB[8] = (size >> 8) & 0XFF;
6722 break;
d04e62b9
KB		 6723 case BMIC_SENSE_SUBSYSTEM_INFORMATION:
6724 c->Request.CDBLen = 10;
6725 c->Request.type_attr_dir =
6726 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6727 c->Request.Timeout = 0;
6728 c->Request.CDB[0] = BMIC_READ;
6729 c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION;
6730 c->Request.CDB[7] = (size >> 16) & 0xFF;
6731 c->Request.CDB[8] = (size >> 8) & 0XFF;
6732 break;
cca8f13b
DB		 6733 case BMIC_SENSE_STORAGE_BOX_PARAMS:
6734 c->Request.CDBLen = 10;
6735 c->Request.type_attr_dir =
6736 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6737 c->Request.Timeout = 0;
6738 c->Request.CDB[0] = BMIC_READ;
6739 c->Request.CDB[6] = BMIC_SENSE_STORAGE_BOX_PARAMS;
6740 c->Request.CDB[7] = (size >> 16) & 0xFF;
6741 c->Request.CDB[8] = (size >> 8) & 0XFF;
6742 break;
66749d0d
ST		 6743 case BMIC_IDENTIFY_CONTROLLER:
6744 c->Request.CDBLen = 10;
6745 c->Request.type_attr_dir =
6746 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
6747 c->Request.Timeout = 0;
6748 c->Request.CDB[0] = BMIC_READ;
6749 c->Request.CDB[1] = 0;
6750 c->Request.CDB[2] = 0;
6751 c->Request.CDB[3] = 0;
6752 c->Request.CDB[4] = 0;
6753 c->Request.CDB[5] = 0;
6754 c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER;
6755 c->Request.CDB[7] = (size >> 16) & 0xFF;
6756 c->Request.CDB[8] = (size >> 8) & 0XFF;
6757 c->Request.CDB[9] = 0;
6758 break;
edd16368
SC		 6759 default:
6760 dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
6761 BUG();
edd16368
SC		 6762 }
6763 } else if (cmd_type == TYPE_MSG) {
6764 switch (cmd) {
6765
0b9b7b6e
ST		 6766 case HPSA_PHYS_TARGET_RESET:
6767 c->Request.CDBLen = 16;
6768 c->Request.type_attr_dir =
6769 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
6770 c->Request.Timeout = 0; /* Don't time out */
6771 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6772 c->Request.CDB[0] = HPSA_RESET;
6773 c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE;
6774 /* Physical target reset needs no control bytes 4-7*/
6775 c->Request.CDB[4] = 0x00;
6776 c->Request.CDB[5] = 0x00;
6777 c->Request.CDB[6] = 0x00;
6778 c->Request.CDB[7] = 0x00;
6779 break;
edd16368
SC		 6780 case HPSA_DEVICE_RESET_MSG:
6781 c->Request.CDBLen = 16;
a505b86f
SC		 6782 c->Request.type_attr_dir =
6783 TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
edd16368 6784 c->Request.Timeout = 0; /* Don't time out */
64670ac8
SC		 6785 memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
6786 c->Request.CDB[0] = cmd;
21e89afd 6787 c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
edd16368
SC		 6788 /* If bytes 4-7 are zero, it means reset the */
6789 /* LunID device */
6790 c->Request.CDB[4] = 0x00;
6791 c->Request.CDB[5] = 0x00;
6792 c->Request.CDB[6] = 0x00;
6793 c->Request.CDB[7] = 0x00;
75167d2c 6794 break;
edd16368
SC		 6795 default:
6796 dev_warn(&h->pdev->dev, "unknown message type %d\n",
6797 cmd);
6798 BUG();
6799 }
6800 } else {
6801 dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
6802 BUG();
6803 }
6804
a505b86f 6805 switch (GET_DIR(c->Request.type_attr_dir)) {
edd16368 6806 case XFER_READ:
8bc8f47e 6807 dir = DMA_FROM_DEVICE;
edd16368
SC		 6808 break;
6809 case XFER_WRITE:
8bc8f47e 6810 dir = DMA_TO_DEVICE;
edd16368
SC		 6811 break;
6812 case XFER_NONE:
8bc8f47e 6813 dir = DMA_NONE;
edd16368
SC		 6814 break;
6815 default:
8bc8f47e 6816 dir = DMA_BIDIRECTIONAL;
edd16368 6817 }
8bc8f47e 6818 if (hpsa_map_one(h->pdev, c, buff, size, dir))
a2dac136
SC		 6819 return -1;
6820 return 0;
edd16368
SC		 6821}
6822
6823/*
6824 * Map (physical) PCI mem into (virtual) kernel space
6825 */
6826static void __iomem *remap_pci_mem(ulong base, ulong size)
6827{
6828 ulong page_base = ((ulong) base) & PAGE_MASK;
6829 ulong page_offs = ((ulong) base) - page_base;
088ba34c
SC		 6830 void __iomem *page_remapped = ioremap_nocache(page_base,
6831 page_offs + size);
edd16368
SC		 6832
6833 return page_remapped ? (page_remapped + page_offs) : NULL;
6834}
6835
254f796b 6836static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
edd16368 6837{
254f796b 6838 return h->access.command_completed(h, q);
edd16368
SC		 6839}
6840
900c5440 6841static inline bool interrupt_pending(struct ctlr_info *h)
edd16368
SC		 6842{
6843 return h->access.intr_pending(h);
6844}
6845
6846static inline long interrupt_not_for_us(struct ctlr_info *h)
6847{
10f66018
SC		 6848 return (h->access.intr_pending(h) == 0) ||
6849 (h->interrupts_enabled == 0);
edd16368
SC		 6850}
6851
01a02ffc
SC		 6852static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
6853 u32 raw_tag)
edd16368
SC		 6854{
6855 if (unlikely(tag_index >= h->nr_cmds)) {
6856 dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
6857 return 1;
6858 }
6859 return 0;
6860}
6861
5a3d16f5 6862static inline void finish_cmd(struct CommandList *c)
edd16368 6863{
e85c5974 6864 dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
c349775e
ST		 6865 if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
6866 || c->cmd_type == CMD_IOACCEL2))
1fb011fb 6867 complete_scsi_command(c);
8be986cc 6868 else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
edd16368 6869 complete(c->waiting);
a104c99f
SC		 6870}
6871
303932fd 6872/* process completion of an indexed ("direct lookup") command */
1d94f94d 6873static inline void process_indexed_cmd(struct ctlr_info *h,
303932fd
DB		 6874 u32 raw_tag)
6875{
6876 u32 tag_index;
6877 struct CommandList *c;
6878
f2405db8 6879 tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
1d94f94d
SC		 6880 if (!bad_tag(h, tag_index, raw_tag)) {
6881 c = h->cmd_pool + tag_index;
6882 finish_cmd(c);
6883 }
303932fd
DB		 6884}
6885
64670ac8
SC		 6886/* Some controllers, like p400, will give us one interrupt
6887 * after a soft reset, even if we turned interrupts off.
6888 * Only need to check for this in the hpsa_xxx_discard_completions
6889 * functions.
6890 */
6891static int ignore_bogus_interrupt(struct ctlr_info *h)
6892{
6893 if (likely(!reset_devices))
6894 return 0;
6895
6896 if (likely(h->interrupts_enabled))
6897 return 0;
6898
6899 dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
6900 "(known firmware bug.) Ignoring.\n");
6901
6902 return 1;
6903}
6904
254f796b
MG		 6905/*
6906 * Convert &h->q[x] (passed to interrupt handlers) back to h.
6907 * Relies on (h-q[x] == x) being true for x such that
6908 * 0 <= x < MAX_REPLY_QUEUES.
6909 */
6910static struct ctlr_info *queue_to_hba(u8 *queue)
64670ac8 6911{
254f796b
MG		 6912 return container_of((queue - *queue), struct ctlr_info, q[0]);
6913}
6914
6915static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
6916{
6917 struct ctlr_info *h = queue_to_hba(queue);
6918 u8 q = *(u8 *) queue;
64670ac8
SC		 6919 u32 raw_tag;
6920
6921 if (ignore_bogus_interrupt(h))
6922 return IRQ_NONE;
6923
6924 if (interrupt_not_for_us(h))
6925 return IRQ_NONE;
a0c12413 6926 h->last_intr_timestamp = get_jiffies_64();
64670ac8 6927 while (interrupt_pending(h)) {
254f796b 6928 raw_tag = get_next_completion(h, q);
64670ac8 6929 while (raw_tag != FIFO_EMPTY)
254f796b 6930 raw_tag = next_command(h, q);
64670ac8 6931 }
64670ac8
SC		 6932 return IRQ_HANDLED;
6933}
6934
254f796b 6935static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
64670ac8 6936{
254f796b 6937 struct ctlr_info *h = queue_to_hba(queue);
64670ac8 6938 u32 raw_tag;
254f796b 6939 u8 q = *(u8 *) queue;
64670ac8
SC		 6940
6941 if (ignore_bogus_interrupt(h))
6942 return IRQ_NONE;
6943
a0c12413 6944 h->last_intr_timestamp = get_jiffies_64();
254f796b 6945 raw_tag = get_next_completion(h, q);
64670ac8 6946 while (raw_tag != FIFO_EMPTY)
254f796b 6947 raw_tag = next_command(h, q);
64670ac8
SC		 6948 return IRQ_HANDLED;
6949}
6950
254f796b 6951static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
edd16368 6952{
254f796b 6953 struct ctlr_info *h = queue_to_hba((u8 *) queue);
303932fd 6954 u32 raw_tag;
254f796b 6955 u8 q = *(u8 *) queue;
edd16368
SC		 6956
6957 if (interrupt_not_for_us(h))
6958 return IRQ_NONE;
a0c12413 6959 h->last_intr_timestamp = get_jiffies_64();
10f66018 6960 while (interrupt_pending(h)) {
254f796b 6961 raw_tag = get_next_completion(h, q);
10f66018 6962 while (raw_tag != FIFO_EMPTY) {
f2405db8 6963 process_indexed_cmd(h, raw_tag);
254f796b 6964 raw_tag = next_command(h, q);
10f66018
SC		 6965 }
6966 }
10f66018
SC		 6967 return IRQ_HANDLED;
6968}
6969
254f796b 6970static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
10f66018 6971{
254f796b 6972 struct ctlr_info *h = queue_to_hba(queue);
10f66018 6973 u32 raw_tag;
254f796b 6974 u8 q = *(u8 *) queue;
10f66018 6975
a0c12413 6976 h->last_intr_timestamp = get_jiffies_64();
254f796b 6977 raw_tag = get_next_completion(h, q);
303932fd 6978 while (raw_tag != FIFO_EMPTY) {
f2405db8 6979 process_indexed_cmd(h, raw_tag);
254f796b 6980 raw_tag = next_command(h, q);
edd16368 6981 }
edd16368
SC		 6982 return IRQ_HANDLED;
6983}
6984
a9a3a273
SC		 6985/* Send a message CDB to the firmware. Careful, this only works
6986 * in simple mode, not performant mode due to the tag lookup.
6987 * We only ever use this immediately after a controller reset.
6988 */
6f039790
GKH		 6989static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
6990 unsigned char type)
edd16368
SC		 6991{
6992 struct Command {
6993 struct CommandListHeader CommandHeader;
6994 struct RequestBlock Request;
6995 struct ErrDescriptor ErrorDescriptor;
6996 };
6997 struct Command *cmd;
6998 static const size_t cmd_sz = sizeof(*cmd) +
6999 sizeof(cmd->ErrorDescriptor);
7000 dma_addr_t paddr64;
2b08b3e9
DB		 7001 __le32 paddr32;
7002 u32 tag;
edd16368
SC		 7003 void __iomem *vaddr;
7004 int i, err;
7005
7006 vaddr = pci_ioremap_bar(pdev, 0);
7007 if (vaddr == NULL)
7008 return -ENOMEM;
7009
7010 /* The Inbound Post Queue only accepts 32-bit physical addresses for the
7011 * CCISS commands, so they must be allocated from the lower 4GiB of
7012 * memory.
7013 */
8bc8f47e 7014 err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
edd16368
SC		 7015 if (err) {
7016 iounmap(vaddr);
1eaec8f3 7017 return err;
edd16368
SC		 7018 }
7019
8bc8f47e 7020 cmd = dma_alloc_coherent(&pdev->dev, cmd_sz, &paddr64, GFP_KERNEL);
edd16368
SC		 7021 if (cmd == NULL) {
7022 iounmap(vaddr);
7023 return -ENOMEM;
7024 }
7025
7026 /* This must fit, because of the 32-bit consistent DMA mask. Also,
7027 * although there's no guarantee, we assume that the address is at
7028 * least 4-byte aligned (most likely, it's page-aligned).
7029 */
2b08b3e9 7030 paddr32 = cpu_to_le32(paddr64);
edd16368
SC		 7031
7032 cmd->CommandHeader.ReplyQueue = 0;
7033 cmd->CommandHeader.SGList = 0;
50a0decf 7034 cmd->CommandHeader.SGTotal = cpu_to_le16(0);
2b08b3e9 7035 cmd->CommandHeader.tag = cpu_to_le64(paddr64);
edd16368
SC		 7036 memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
7037
7038 cmd->Request.CDBLen = 16;
a505b86f
SC		 7039 cmd->Request.type_attr_dir =
7040 TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
edd16368
SC		 7041 cmd->Request.Timeout = 0; /* Don't time out */
7042 cmd->Request.CDB[0] = opcode;
7043 cmd->Request.CDB[1] = type;
7044 memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
50a0decf 7045 cmd->ErrorDescriptor.Addr =
2b08b3e9 7046 cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
50a0decf 7047 cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
edd16368 7048
2b08b3e9 7049 writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
edd16368
SC		 7050
7051 for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
7052 tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
2b08b3e9 7053 if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
edd16368
SC		 7054 break;
7055 msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
7056 }
7057
7058 iounmap(vaddr);
7059
7060 /* we leak the DMA buffer here ... no choice since the controller could
7061 * still complete the command.
7062 */
7063 if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
7064 dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
7065 opcode, type);
7066 return -ETIMEDOUT;
7067 }
7068
8bc8f47e 7069 dma_free_coherent(&pdev->dev, cmd_sz, cmd, paddr64);
edd16368
SC		 7070
7071 if (tag & HPSA_ERROR_BIT) {
7072 dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
7073 opcode, type);
7074 return -EIO;
7075 }
7076
7077 dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
7078 opcode, type);
7079 return 0;
7080}
7081
edd16368
SC		 7082#define hpsa_noop(p) hpsa_message(p, 3, 0)
7083
1df8552a 7084static int hpsa_controller_hard_reset(struct pci_dev *pdev,
42a91641 7085 void __iomem *vaddr, u32 use_doorbell)
1df8552a 7086{
1df8552a
SC		 7087
7088 if (use_doorbell) {
7089 /* For everything after the P600, the PCI power state method
7090 * of resetting the controller doesn't work, so we have this
7091 * other way using the doorbell register.
7092 */
7093 dev_info(&pdev->dev, "using doorbell to reset controller\n");
cf0b08d0 7094 writel(use_doorbell, vaddr + SA5_DOORBELL);
85009239 7095
00701a96 7096 /* PMC hardware guys tell us we need a 10 second delay after
85009239
SC		 7097 * doorbell reset and before any attempt to talk to the board
7098 * at all to ensure that this actually works and doesn't fall
7099 * over in some weird corner cases.
7100 */
00701a96 7101 msleep(10000);
1df8552a
SC		 7102 } else { /* Try to do it the PCI power state way */
7103
7104 /* Quoting from the Open CISS Specification: "The Power
7105 * Management Control/Status Register (CSR) controls the power
7106 * state of the device. The normal operating state is D0,
7107 * CSR=00h. The software off state is D3, CSR=03h. To reset
7108 * the controller, place the interface device in D3 then to D0,
7109 * this causes a secondary PCI reset which will reset the
7110 * controller." */
2662cab8
DB		 7111
7112 int rc = 0;
7113
1df8552a 7114 dev_info(&pdev->dev, "using PCI PM to reset controller\n");
2662cab8 7115
1df8552a 7116 /* enter the D3hot power management state */
2662cab8
DB		 7117 rc = pci_set_power_state(pdev, PCI_D3hot);
7118 if (rc)
7119 return rc;
1df8552a
SC		 7120
7121 msleep(500);
7122
7123 /* enter the D0 power management state */
2662cab8
DB		 7124 rc = pci_set_power_state(pdev, PCI_D0);
7125 if (rc)
7126 return rc;
c4853efe
MM		 7127
7128 /*
7129 * The P600 requires a small delay when changing states.
7130 * Otherwise we may think the board did not reset and we bail.
7131 * This for kdump only and is particular to the P600.
7132 */
7133 msleep(500);
1df8552a
SC		 7134 }
7135 return 0;
7136}
7137
6f039790 7138static void init_driver_version(char *driver_version, int len)
580ada3c
SC		 7139{
7140 memset(driver_version, 0, len);
f79cfec6 7141 strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
580ada3c
SC		 7142}
7143
6f039790 7144static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 7145{
7146 char *driver_version;
7147 int i, size = sizeof(cfgtable->driver_version);
7148
7149 driver_version = kmalloc(size, GFP_KERNEL);
7150 if (!driver_version)
7151 return -ENOMEM;
7152
7153 init_driver_version(driver_version, size);
7154 for (i = 0; i < size; i++)
7155 writeb(driver_version[i], &cfgtable->driver_version[i]);
7156 kfree(driver_version);
7157 return 0;
7158}
7159
6f039790
GKH		 7160static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
7161 unsigned char *driver_ver)
580ada3c
SC		 7162{
7163 int i;
7164
7165 for (i = 0; i < sizeof(cfgtable->driver_version); i++)
7166 driver_ver[i] = readb(&cfgtable->driver_version[i]);
7167}
7168
6f039790 7169static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
580ada3c
SC		 7170{
7171
7172 char *driver_ver, *old_driver_ver;
7173 int rc, size = sizeof(cfgtable->driver_version);
7174
6da2ec56 7175 old_driver_ver = kmalloc_array(2, size, GFP_KERNEL);
580ada3c
SC		 7176 if (!old_driver_ver)
7177 return -ENOMEM;
7178 driver_ver = old_driver_ver + size;
7179
7180 /* After a reset, the 32 bytes of "driver version" in the cfgtable
7181 * should have been changed, otherwise we know the reset failed.
7182 */
7183 init_driver_version(old_driver_ver, size);
7184 read_driver_ver_from_cfgtable(cfgtable, driver_ver);
7185 rc = !memcmp(driver_ver, old_driver_ver, size);
7186 kfree(old_driver_ver);
7187 return rc;
7188}
edd16368 7189/* This does a hard reset of the controller using PCI power management
1df8552a 7190 * states or the using the doorbell register.
edd16368 7191 */
6b6c1cd7 7192static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
edd16368 7193{
1df8552a
SC		 7194 u64 cfg_offset;
7195 u32 cfg_base_addr;
7196 u64 cfg_base_addr_index;
7197 void __iomem *vaddr;
7198 unsigned long paddr;
580ada3c 7199 u32 misc_fw_support;
270d05de 7200 int rc;
1df8552a 7201 struct CfgTable __iomem *cfgtable;
cf0b08d0 7202 u32 use_doorbell;
270d05de 7203 u16 command_register;
edd16368 7204
1df8552a
SC		 7205 /* For controllers as old as the P600, this is very nearly
7206 * the same thing as
edd16368
SC		 7207 *
7208 * pci_save_state(pci_dev);
7209 * pci_set_power_state(pci_dev, PCI_D3hot);
7210 * pci_set_power_state(pci_dev, PCI_D0);
7211 * pci_restore_state(pci_dev);
7212 *
1df8552a
SC		 7213 * For controllers newer than the P600, the pci power state
7214 * method of resetting doesn't work so we have another way
7215 * using the doorbell register.
edd16368 7216 */
18867659 7217
60f923b9
RE		 7218 if (!ctlr_is_resettable(board_id)) {
7219 dev_warn(&pdev->dev, "Controller not resettable\n");
25c1e56a
SC		 7220 return -ENODEV;
7221 }
46380786
SC		 7222
7223 /* if controller is soft- but not hard resettable... */
7224 if (!ctlr_is_hard_resettable(board_id))
7225 return -ENOTSUPP; /* try soft reset later. */
18867659 7226
270d05de
SC		 7227 /* Save the PCI command register */
7228 pci_read_config_word(pdev, 4, &command_register);
270d05de 7229 pci_save_state(pdev);
edd16368 7230
1df8552a
SC		 7231 /* find the first memory BAR, so we can find the cfg table */
7232 rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
7233 if (rc)
7234 return rc;
7235 vaddr = remap_pci_mem(paddr, 0x250);
7236 if (!vaddr)
7237 return -ENOMEM;
edd16368 7238
1df8552a
SC		 7239 /* find cfgtable in order to check if reset via doorbell is supported */
7240 rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
7241 &cfg_base_addr_index, &cfg_offset);
7242 if (rc)
7243 goto unmap_vaddr;
7244 cfgtable = remap_pci_mem(pci_resource_start(pdev,
7245 cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
7246 if (!cfgtable) {
7247 rc = -ENOMEM;
7248 goto unmap_vaddr;
7249 }
580ada3c
SC		 7250 rc = write_driver_ver_to_cfgtable(cfgtable);
7251 if (rc)
03741d95 7252 goto unmap_cfgtable;
edd16368 7253
cf0b08d0
SC		 7254 /* If reset via doorbell register is supported, use that.
7255 * There are two such methods. Favor the newest method.
7256 */
1df8552a 7257 misc_fw_support = readl(&cfgtable->misc_fw_support);
cf0b08d0
SC		 7258 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
7259 if (use_doorbell) {
7260 use_doorbell = DOORBELL_CTLR_RESET2;
7261 } else {
7262 use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
7263 if (use_doorbell) {
050f7147
SC		 7264 dev_warn(&pdev->dev,
7265 "Soft reset not supported. Firmware update is required.\n");
64670ac8 7266 rc = -ENOTSUPP; /* try soft reset */
cf0b08d0
SC		 7267 goto unmap_cfgtable;
7268 }
7269 }
edd16368 7270
1df8552a
SC		 7271 rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
7272 if (rc)
7273 goto unmap_cfgtable;
edd16368 7274
270d05de 7275 pci_restore_state(pdev);
270d05de 7276 pci_write_config_word(pdev, 4, command_register);
edd16368 7277
1df8552a
SC		 7278 /* Some devices (notably the HP Smart Array 5i Controller)
7279 need a little pause here */
7280 msleep(HPSA_POST_RESET_PAUSE_MSECS);
7281
fe5389c8
SC		 7282 rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
7283 if (rc) {
7284 dev_warn(&pdev->dev,
050f7147 7285 "Failed waiting for board to become ready after hard reset\n");
fe5389c8
SC		 7286 goto unmap_cfgtable;
7287 }
fe5389c8 7288
580ada3c
SC		 7289 rc = controller_reset_failed(vaddr);
7290 if (rc < 0)
7291 goto unmap_cfgtable;
7292 if (rc) {
64670ac8
SC		 7293 dev_warn(&pdev->dev, "Unable to successfully reset "
7294 "controller. Will try soft reset.\n");
7295 rc = -ENOTSUPP;
580ada3c 7296 } else {
64670ac8 7297 dev_info(&pdev->dev, "board ready after hard reset.\n");
1df8552a
SC		 7298 }
7299
7300unmap_cfgtable:
7301 iounmap(cfgtable);
7302
7303unmap_vaddr:
7304 iounmap(vaddr);
7305 return rc;
edd16368
SC		 7306}
7307
7308/*
7309 * We cannot read the structure directly, for portability we must use
7310 * the io functions.
7311 * This is for debug only.
7312 */
42a91641 7313static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
edd16368 7314{
58f8665c 7315#ifdef HPSA_DEBUG
edd16368
SC		 7316 int i;
7317 char temp_name[17];
7318
7319 dev_info(dev, "Controller Configuration information\n");
7320 dev_info(dev, "------------------------------------\n");
7321 for (i = 0; i < 4; i++)
7322 temp_name[i] = readb(&(tb->Signature[i]));
7323 temp_name[4] = '\0';
7324 dev_info(dev, " Signature = %s\n", temp_name);
7325 dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
7326 dev_info(dev, " Transport methods supported = 0x%x\n",
7327 readl(&(tb->TransportSupport)));
7328 dev_info(dev, " Transport methods active = 0x%x\n",
7329 readl(&(tb->TransportActive)));
7330 dev_info(dev, " Requested transport Method = 0x%x\n",
7331 readl(&(tb->HostWrite.TransportRequest)));
7332 dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
7333 readl(&(tb->HostWrite.CoalIntDelay)));
7334 dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
7335 readl(&(tb->HostWrite.CoalIntCount)));
69d6e33d 7336 dev_info(dev, " Max outstanding commands = %d\n",
edd16368
SC		 7337 readl(&(tb->CmdsOutMax)));
7338 dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
7339 for (i = 0; i < 16; i++)
7340 temp_name[i] = readb(&(tb->ServerName[i]));
7341 temp_name[16] = '\0';
7342 dev_info(dev, " Server Name = %s\n", temp_name);
7343 dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
7344 readl(&(tb->HeartBeat)));
edd16368 7345#endif /* HPSA_DEBUG */
58f8665c 7346}
edd16368
SC		 7347
7348static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
7349{
7350 int i, offset, mem_type, bar_type;
7351
7352 if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
7353 return 0;
7354 offset = 0;
7355 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
7356 bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
7357 if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
7358 offset += 4;
7359 else {
7360 mem_type = pci_resource_flags(pdev, i) &
7361 PCI_BASE_ADDRESS_MEM_TYPE_MASK;
7362 switch (mem_type) {
7363 case PCI_BASE_ADDRESS_MEM_TYPE_32:
7364 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
7365 offset += 4; /* 32 bit */
7366 break;
7367 case PCI_BASE_ADDRESS_MEM_TYPE_64:
7368 offset += 8;
7369 break;
7370 default: /* reserved in PCI 2.2 */
7371 dev_warn(&pdev->dev,
7372 "base address is invalid\n");
7373 return -1;
7374 break;
7375 }
7376 }
7377 if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
7378 return i + 1;
7379 }
7380 return -1;
7381}
7382
cc64c817
RE		 7383static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
7384{
bc2bb154
CH		 7385 pci_free_irq_vectors(h->pdev);
7386 h->msix_vectors = 0;
cc64c817
RE		 7387}
7388
8b834bff
ML		 7389static void hpsa_setup_reply_map(struct ctlr_info *h)
7390{
7391 const struct cpumask *mask;
7392 unsigned int queue, cpu;
7393
7394 for (queue = 0; queue < h->msix_vectors; queue++) {
7395 mask = pci_irq_get_affinity(h->pdev, queue);
7396 if (!mask)
7397 goto fallback;
7398
7399 for_each_cpu(cpu, mask)
7400 h->reply_map[cpu] = queue;
7401 }
7402 return;
7403
7404fallback:
7405 for_each_possible_cpu(cpu)
7406 h->reply_map[cpu] = 0;
7407}
7408
edd16368 7409/* If MSI/MSI-X is supported by the kernel we will try to enable it on
050f7147 7410 * controllers that are capable. If not, we use legacy INTx mode.
edd16368 7411 */
bc2bb154 7412static int hpsa_interrupt_mode(struct ctlr_info *h)
edd16368 7413{
bc2bb154
CH		 7414 unsigned int flags = PCI_IRQ_LEGACY;
7415 int ret;
edd16368
SC		 7416
7417 /* Some boards advertise MSI but don't really support it */
bc2bb154
CH		 7418 switch (h->board_id) {
7419 case 0x40700E11:
7420 case 0x40800E11:
7421 case 0x40820E11:
7422 case 0x40830E11:
7423 break;
7424 default:
7425 ret = pci_alloc_irq_vectors(h->pdev, 1, MAX_REPLY_QUEUES,
7426 PCI_IRQ_MSIX | PCI_IRQ_AFFINITY);
7427 if (ret > 0) {
7428 h->msix_vectors = ret;
7429 return 0;
edd16368 7430 }
bc2bb154
CH		 7431
7432 flags |= PCI_IRQ_MSI;
7433 break;
edd16368 7434 }
bc2bb154
CH		 7435
7436 ret = pci_alloc_irq_vectors(h->pdev, 1, 1, flags);
7437 if (ret < 0)
7438 return ret;
7439 return 0;
edd16368
SC		 7440}
7441
135ae6ed
HR		 7442static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id,
7443 bool *legacy_board)
e5c880d1
SC		 7444{
7445 int i;
7446 u32 subsystem_vendor_id, subsystem_device_id;
7447
7448 subsystem_vendor_id = pdev->subsystem_vendor;
7449 subsystem_device_id = pdev->subsystem_device;
7450 *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
7451 subsystem_vendor_id;
7452
135ae6ed
HR		 7453 if (legacy_board)
7454 *legacy_board = false;
e5c880d1 7455 for (i = 0; i < ARRAY_SIZE(products); i++)
135ae6ed
HR		 7456 if (*board_id == products[i].board_id) {
7457 if (products[i].access != &SA5A_access &&
7458 products[i].access != &SA5B_access)
7459 return i;
c8cd71f1
HR		 7460 dev_warn(&pdev->dev,
7461 "legacy board ID: 0x%08x\n",
7462 *board_id);
7463 if (legacy_board)
7464 *legacy_board = true;
7465 return i;
135ae6ed 7466 }
e5c880d1 7467
c8cd71f1 7468 dev_warn(&pdev->dev, "unrecognized board ID: 0x%08x\n", *board_id);
135ae6ed
HR		 7469 if (legacy_board)
7470 *legacy_board = true;
e5c880d1
SC		 7471 return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
7472}
7473
6f039790
GKH		 7474static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
7475 unsigned long *memory_bar)
3a7774ce
SC		 7476{
7477 int i;
7478
7479 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
12d2cd47 7480 if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3a7774ce 7481 /* addressing mode bits already removed */
12d2cd47
SC		 7482 *memory_bar = pci_resource_start(pdev, i);
7483 dev_dbg(&pdev->dev, "memory BAR = %lx\n",
3a7774ce
SC		 7484 *memory_bar);
7485 return 0;
7486 }
12d2cd47 7487 dev_warn(&pdev->dev, "no memory BAR found\n");
3a7774ce
SC		 7488 return -ENODEV;
7489}
7490
6f039790
GKH		 7491static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
7492 int wait_for_ready)
2c4c8c8b 7493{
fe5389c8 7494 int i, iterations;
2c4c8c8b 7495 u32 scratchpad;
fe5389c8
SC		 7496 if (wait_for_ready)
7497 iterations = HPSA_BOARD_READY_ITERATIONS;
7498 else
7499 iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
2c4c8c8b 7500
fe5389c8
SC		 7501 for (i = 0; i < iterations; i++) {
7502 scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
7503 if (wait_for_ready) {
7504 if (scratchpad == HPSA_FIRMWARE_READY)
7505 return 0;
7506 } else {
7507 if (scratchpad != HPSA_FIRMWARE_READY)
7508 return 0;
7509 }
2c4c8c8b
SC		 7510 msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
7511 }
fe5389c8 7512 dev_warn(&pdev->dev, "board not ready, timed out.\n");
2c4c8c8b
SC		 7513 return -ENODEV;
7514}
7515
6f039790
GKH		 7516static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
7517 u32 *cfg_base_addr, u64 *cfg_base_addr_index,
7518 u64 *cfg_offset)
a51fd47f
SC		 7519{
7520 *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
7521 *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
7522 *cfg_base_addr &= (u32) 0x0000ffff;
7523 *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
7524 if (*cfg_base_addr_index == -1) {
7525 dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
7526 return -ENODEV;
7527 }
7528 return 0;
7529}
7530
195f2c65
RE		 7531static void hpsa_free_cfgtables(struct ctlr_info *h)
7532{
105a3dbc 7533 if (h->transtable) {
195f2c65 7534 iounmap(h->transtable);
105a3dbc
RE		 7535 h->transtable = NULL;
7536 }
7537 if (h->cfgtable) {
195f2c65 7538 iounmap(h->cfgtable);
105a3dbc
RE		 7539 h->cfgtable = NULL;
7540 }
195f2c65
RE		 7541}
7542
7543/* Find and map CISS config table and transfer table
7544+ * several items must be unmapped (freed) later
7545+ * */
6f039790 7546static int hpsa_find_cfgtables(struct ctlr_info *h)
edd16368 7547{
01a02ffc
SC		 7548 u64 cfg_offset;
7549 u32 cfg_base_addr;
7550 u64 cfg_base_addr_index;
303932fd 7551 u32 trans_offset;
a51fd47f 7552 int rc;
77c4495c 7553
a51fd47f
SC		 7554 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
7555 &cfg_base_addr_index, &cfg_offset);
7556 if (rc)
7557 return rc;
77c4495c 7558 h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
a51fd47f 7559 cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
cd3c81c4
RE		 7560 if (!h->cfgtable) {
7561 dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
77c4495c 7562 return -ENOMEM;
cd3c81c4 7563 }
580ada3c
SC		 7564 rc = write_driver_ver_to_cfgtable(h->cfgtable);
7565 if (rc)
7566 return rc;
77c4495c 7567 /* Find performant mode table. */
a51fd47f 7568 trans_offset = readl(&h->cfgtable->TransMethodOffset);
77c4495c
SC		 7569 h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
7570 cfg_base_addr_index)+cfg_offset+trans_offset,
7571 sizeof(*h->transtable));
195f2c65
RE		 7572 if (!h->transtable) {
7573 dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
7574 hpsa_free_cfgtables(h);
77c4495c 7575 return -ENOMEM;
195f2c65 7576 }
77c4495c
SC		 7577 return 0;
7578}
7579
6f039790 7580static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
cba3d38b 7581{
41ce4c35
SC		 7582#define MIN_MAX_COMMANDS 16
7583 BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
7584
7585 h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
72ceeaec
SC		 7586
7587 /* Limit commands in memory limited kdump scenario. */
7588 if (reset_devices && h->max_commands > 32)
7589 h->max_commands = 32;
7590
41ce4c35
SC		 7591 if (h->max_commands < MIN_MAX_COMMANDS) {
7592 dev_warn(&h->pdev->dev,
7593 "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
7594 h->max_commands,
7595 MIN_MAX_COMMANDS);
7596 h->max_commands = MIN_MAX_COMMANDS;
cba3d38b
SC		 7597 }
7598}
7599
c7ee65b3
WS		 7600/* If the controller reports that the total max sg entries is greater than 512,
7601 * then we know that chained SG blocks work. (Original smart arrays did not
7602 * support chained SG blocks and would return zero for max sg entries.)
7603 */
7604static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
7605{
7606 return h->maxsgentries > 512;
7607}
7608
b93d7536
SC		 7609/* Interrogate the hardware for some limits:
7610 * max commands, max SG elements without chaining, and with chaining,
7611 * SG chain block size, etc.
7612 */
6f039790 7613static void hpsa_find_board_params(struct ctlr_info *h)
b93d7536 7614{
cba3d38b 7615 hpsa_get_max_perf_mode_cmds(h);
45fcb86e 7616 h->nr_cmds = h->max_commands;
b93d7536 7617 h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
283b4a9b 7618 h->fw_support = readl(&(h->cfgtable->misc_fw_support));
c7ee65b3
WS		 7619 if (hpsa_supports_chained_sg_blocks(h)) {
7620 /* Limit in-command s/g elements to 32 save dma'able memory. */
b93d7536 7621 h->max_cmd_sg_entries = 32;
1a63ea6f 7622 h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
b93d7536
SC		 7623 h->maxsgentries--; /* save one for chain pointer */
7624 } else {
c7ee65b3
WS		 7625 /*
7626 * Original smart arrays supported at most 31 s/g entries
7627 * embedded inline in the command (trying to use more
7628 * would lock up the controller)
7629 */
7630 h->max_cmd_sg_entries = 31;
1a63ea6f 7631 h->maxsgentries = 31; /* default to traditional values */
c7ee65b3 7632 h->chainsize = 0;
b93d7536 7633 }
75167d2c
SC		 7634
7635 /* Find out what task management functions are supported and cache */
7636 h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
0e7a7fce
ST		 7637 if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
7638 dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
7639 if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
7640 dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
8be986cc
SC		 7641 if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
7642 dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
b93d7536
SC		 7643}
7644
76c46e49
SC		 7645static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
7646{
0fc9fd40 7647 if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
050f7147 7648 dev_err(&h->pdev->dev, "not a valid CISS config table\n");
76c46e49
SC		 7649 return false;
7650 }
7651 return true;
7652}
7653
97a5e98c 7654static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
f7c39101 7655{
97a5e98c 7656 u32 driver_support;
f7c39101 7657
97a5e98c 7658 driver_support = readl(&(h->cfgtable->driver_support));
0b9e7b74
AB		 7659 /* Need to enable prefetch in the SCSI core for 6400 in x86 */
7660#ifdef CONFIG_X86
97a5e98c 7661 driver_support |= ENABLE_SCSI_PREFETCH;
f7c39101 7662#endif
28e13446
SC		 7663 driver_support |= ENABLE_UNIT_ATTN;
7664 writel(driver_support, &(h->cfgtable->driver_support));
f7c39101
SC		 7665}
7666
3d0eab67
SC		 7667/* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
7668 * in a prefetch beyond physical memory.
7669 */
7670static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
7671{
7672 u32 dma_prefetch;
7673
7674 if (h->board_id != 0x3225103C)
7675 return;
7676 dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
7677 dma_prefetch |= 0x8000;
7678 writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
7679}
7680
c706a795 7681static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
76438d08
SC		 7682{
7683 int i;
7684 u32 doorbell_value;
7685 unsigned long flags;
7686 /* wait until the clear_event_notify bit 6 is cleared by controller. */
007e7aa9 7687 for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
76438d08
SC		 7688 spin_lock_irqsave(&h->lock, flags);
7689 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7690 spin_unlock_irqrestore(&h->lock, flags);
7691 if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
c706a795 7692 goto done;
76438d08 7693 /* delay and try again */
007e7aa9 7694 msleep(CLEAR_EVENT_WAIT_INTERVAL);
76438d08 7695 }
c706a795
RE		 7696 return -ENODEV;
7697done:
7698 return 0;
76438d08
SC		 7699}
7700
c706a795 7701static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
eb6b2ae9
SC		 7702{
7703 int i;
6eaf46fd
SC		 7704 u32 doorbell_value;
7705 unsigned long flags;
eb6b2ae9
SC		 7706
7707 /* under certain very rare conditions, this can take awhile.
7708 * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
7709 * as we enter this code.)
7710 */
007e7aa9 7711 for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
25163bd5
WS		 7712 if (h->remove_in_progress)
7713 goto done;
6eaf46fd
SC		 7714 spin_lock_irqsave(&h->lock, flags);
7715 doorbell_value = readl(h->vaddr + SA5_DOORBELL);
7716 spin_unlock_irqrestore(&h->lock, flags);
382be668 7717 if (!(doorbell_value & CFGTBL_ChangeReq))
c706a795 7718 goto done;
eb6b2ae9 7719 /* delay and try again */
007e7aa9 7720 msleep(MODE_CHANGE_WAIT_INTERVAL);
eb6b2ae9 7721 }
c706a795
RE		 7722 return -ENODEV;
7723done:
7724 return 0;
3f4336f3
SC		 7725}
7726
c706a795 7727/* return -ENODEV or other reason on error, 0 on success */
6f039790 7728static int hpsa_enter_simple_mode(struct ctlr_info *h)
3f4336f3
SC		 7729{
7730 u32 trans_support;
7731
7732 trans_support = readl(&(h->cfgtable->TransportSupport));
7733 if (!(trans_support & SIMPLE_MODE))
7734 return -ENOTSUPP;
7735
7736 h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
283b4a9b 7737
3f4336f3
SC		 7738 /* Update the field, and then ring the doorbell */
7739 writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
b9af4937 7740 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
3f4336f3 7741 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 7742 if (hpsa_wait_for_mode_change_ack(h))
7743 goto error;
eb6b2ae9 7744 print_cfg_table(&h->pdev->dev, h->cfgtable);
283b4a9b
SC		 7745 if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
7746 goto error;
960a30e7 7747 h->transMethod = CFGTBL_Trans_Simple;
eb6b2ae9 7748 return 0;
283b4a9b 7749error:
050f7147 7750 dev_err(&h->pdev->dev, "failed to enter simple mode\n");
283b4a9b 7751 return -ENODEV;
eb6b2ae9
SC		 7752}
7753
195f2c65
RE		 7754/* free items allocated or mapped by hpsa_pci_init */
7755static void hpsa_free_pci_init(struct ctlr_info *h)
7756{
7757 hpsa_free_cfgtables(h); /* pci_init 4 */
7758 iounmap(h->vaddr); /* pci_init 3 */
105a3dbc 7759 h->vaddr = NULL;
195f2c65 7760 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
943a7021
RE		 7761 /*
7762 * call pci_disable_device before pci_release_regions per
7763 * Documentation/PCI/pci.txt
7764 */
195f2c65 7765 pci_disable_device(h->pdev); /* pci_init 1 */
943a7021 7766 pci_release_regions(h->pdev); /* pci_init 2 */
195f2c65
RE		 7767}
7768
7769/* several items must be freed later */
6f039790 7770static int hpsa_pci_init(struct ctlr_info *h)
77c4495c 7771{
eb6b2ae9 7772 int prod_index, err;
135ae6ed 7773 bool legacy_board;
edd16368 7774
135ae6ed 7775 prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id, &legacy_board);
e5c880d1 7776 if (prod_index < 0)
60f923b9 7777 return prod_index;
e5c880d1
SC		 7778 h->product_name = products[prod_index].product_name;
7779 h->access = *(products[prod_index].access);
135ae6ed 7780 h->legacy_board = legacy_board;
e5a44df8
MG		 7781 pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
7782 PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
7783
55c06c71 7784 err = pci_enable_device(h->pdev);
edd16368 7785 if (err) {
195f2c65 7786 dev_err(&h->pdev->dev, "failed to enable PCI device\n");
943a7021 7787 pci_disable_device(h->pdev);
edd16368
SC		 7788 return err;
7789 }
7790
f79cfec6 7791 err = pci_request_regions(h->pdev, HPSA);
edd16368 7792 if (err) {
55c06c71 7793 dev_err(&h->pdev->dev,
195f2c65 7794 "failed to obtain PCI resources\n");
943a7021
RE		 7795 pci_disable_device(h->pdev);
7796 return err;
edd16368 7797 }
4fa604e1
RE		 7798
7799 pci_set_master(h->pdev);
7800
bc2bb154
CH		 7801 err = hpsa_interrupt_mode(h);
7802 if (err)
7803 goto clean1;
8b834bff
ML		 7804
7805 /* setup mapping between CPU and reply queue */
7806 hpsa_setup_reply_map(h);
7807
12d2cd47 7808 err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
3a7774ce 7809 if (err)
195f2c65 7810 goto clean2; /* intmode+region, pci */
edd16368 7811 h->vaddr = remap_pci_mem(h->paddr, 0x250);
204892e9 7812 if (!h->vaddr) {
195f2c65 7813 dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
204892e9 7814 err = -ENOMEM;
195f2c65 7815 goto clean2; /* intmode+region, pci */
204892e9 7816 }
fe5389c8 7817 err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
2c4c8c8b 7818 if (err)
195f2c65 7819 goto clean3; /* vaddr, intmode+region, pci */
77c4495c
SC		 7820 err = hpsa_find_cfgtables(h);
7821 if (err)
195f2c65 7822 goto clean3; /* vaddr, intmode+region, pci */
b93d7536 7823 hpsa_find_board_params(h);
edd16368 7824
76c46e49 7825 if (!hpsa_CISS_signature_present(h)) {
edd16368 7826 err = -ENODEV;
195f2c65 7827 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368 7828 }
97a5e98c 7829 hpsa_set_driver_support_bits(h);
3d0eab67 7830 hpsa_p600_dma_prefetch_quirk(h);
eb6b2ae9
SC		 7831 err = hpsa_enter_simple_mode(h);
7832 if (err)
195f2c65 7833 goto clean4; /* cfgtables, vaddr, intmode+region, pci */
edd16368
SC		 7834 return 0;
7835
195f2c65
RE		 7836clean4: /* cfgtables, vaddr, intmode+region, pci */
7837 hpsa_free_cfgtables(h);
7838clean3: /* vaddr, intmode+region, pci */
7839 iounmap(h->vaddr);
105a3dbc 7840 h->vaddr = NULL;
195f2c65
RE		 7841clean2: /* intmode+region, pci */
7842 hpsa_disable_interrupt_mode(h);
bc2bb154 7843clean1:
943a7021
RE		 7844 /*
7845 * call pci_disable_device before pci_release_regions per
7846 * Documentation/PCI/pci.txt
7847 */
195f2c65 7848 pci_disable_device(h->pdev);
943a7021 7849 pci_release_regions(h->pdev);
edd16368
SC		 7850 return err;
7851}
7852
6f039790 7853static void hpsa_hba_inquiry(struct ctlr_info *h)
339b2b14
SC		 7854{
7855 int rc;
7856
7857#define HBA_INQUIRY_BYTE_COUNT 64
7858 h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
7859 if (!h->hba_inquiry_data)
7860 return;
7861 rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
7862 h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
7863 if (rc != 0) {
7864 kfree(h->hba_inquiry_data);
7865 h->hba_inquiry_data = NULL;
7866 }
7867}
7868
6b6c1cd7 7869static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
4c2a8c40 7870{
1df8552a 7871 int rc, i;
3b747298 7872 void __iomem *vaddr;
4c2a8c40
SC		 7873
7874 if (!reset_devices)
7875 return 0;
7876
132aa220
TH		 7877 /* kdump kernel is loading, we don't know in which state is
7878 * the pci interface. The dev->enable_cnt is equal zero
7879 * so we call enable+disable, wait a while and switch it on.
7880 */
7881 rc = pci_enable_device(pdev);
7882 if (rc) {
7883 dev_warn(&pdev->dev, "Failed to enable PCI device\n");
7884 return -ENODEV;
7885 }
7886 pci_disable_device(pdev);
7887 msleep(260); /* a randomly chosen number */
7888 rc = pci_enable_device(pdev);
7889 if (rc) {
7890 dev_warn(&pdev->dev, "failed to enable device.\n");
7891 return -ENODEV;
7892 }
4fa604e1 7893
859c75ab 7894 pci_set_master(pdev);
4fa604e1 7895
3b747298
TH		 7896 vaddr = pci_ioremap_bar(pdev, 0);
7897 if (vaddr == NULL) {
7898 rc = -ENOMEM;
7899 goto out_disable;
7900 }
7901 writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
7902 iounmap(vaddr);
7903
1df8552a 7904 /* Reset the controller with a PCI power-cycle or via doorbell */
6b6c1cd7 7905 rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
4c2a8c40 7906
1df8552a
SC		 7907 /* -ENOTSUPP here means we cannot reset the controller
7908 * but it's already (and still) up and running in
18867659
SC		 7909 * "performant mode". Or, it might be 640x, which can't reset
7910 * due to concerns about shared bbwc between 6402/6404 pair.
1df8552a 7911 */
adf1b3a3 7912 if (rc)
132aa220 7913 goto out_disable;
4c2a8c40
SC		 7914
7915 /* Now try to get the controller to respond to a no-op */
1ba66c9c 7916 dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
4c2a8c40
SC		 7917 for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
7918 if (hpsa_noop(pdev) == 0)
7919 break;
7920 else
7921 dev_warn(&pdev->dev, "no-op failed%s\n",
7922 (i < 11 ? "; re-trying" : ""));
7923 }
132aa220
TH		 7924
7925out_disable:
7926
7927 pci_disable_device(pdev);
7928 return rc;
4c2a8c40
SC		 7929}
7930
1fb7c98a
RE		 7931static void hpsa_free_cmd_pool(struct ctlr_info *h)
7932{
7933 kfree(h->cmd_pool_bits);
105a3dbc
RE		 7934 h->cmd_pool_bits = NULL;
7935 if (h->cmd_pool) {
8bc8f47e 7936 dma_free_coherent(&h->pdev->dev,
1fb7c98a
RE		 7937 h->nr_cmds * sizeof(struct CommandList),
7938 h->cmd_pool,
7939 h->cmd_pool_dhandle);
105a3dbc
RE		 7940 h->cmd_pool = NULL;
7941 h->cmd_pool_dhandle = 0;
7942 }
7943 if (h->errinfo_pool) {
8bc8f47e 7944 dma_free_coherent(&h->pdev->dev,
1fb7c98a
RE		 7945 h->nr_cmds * sizeof(struct ErrorInfo),
7946 h->errinfo_pool,
7947 h->errinfo_pool_dhandle);
105a3dbc
RE		 7948 h->errinfo_pool = NULL;
7949 h->errinfo_pool_dhandle = 0;
7950 }
1fb7c98a
RE		 7951}
7952
d37ffbe4 7953static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
2e9d1b36 7954{
6396bb22
KC		 7955 h->cmd_pool_bits = kcalloc(DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG),
7956 sizeof(unsigned long),
7957 GFP_KERNEL);
8bc8f47e 7958 h->cmd_pool = dma_alloc_coherent(&h->pdev->dev,
2e9d1b36 7959 h->nr_cmds * sizeof(*h->cmd_pool),
8bc8f47e
CH		 7960 &h->cmd_pool_dhandle, GFP_KERNEL);
7961 h->errinfo_pool = dma_alloc_coherent(&h->pdev->dev,
2e9d1b36 7962 h->nr_cmds * sizeof(*h->errinfo_pool),
8bc8f47e 7963 &h->errinfo_pool_dhandle, GFP_KERNEL);
2e9d1b36
SC		 7964 if ((h->cmd_pool_bits == NULL)
7965 || (h->cmd_pool == NULL)
7966 || (h->errinfo_pool == NULL)) {
7967 dev_err(&h->pdev->dev, "out of memory in %s", __func__);
2c143342 7968 goto clean_up;
2e9d1b36 7969 }
360c73bd 7970 hpsa_preinitialize_commands(h);
2e9d1b36 7971 return 0;
2c143342
RE		 7972clean_up:
7973 hpsa_free_cmd_pool(h);
7974 return -ENOMEM;
2e9d1b36
SC		 7975}
7976
ec501a18
RE		 7977/* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
7978static void hpsa_free_irqs(struct ctlr_info *h)
7979{
7980 int i;
7981
bc2bb154 7982 if (!h->msix_vectors || h->intr_mode != PERF_MODE_INT) {
ec501a18 7983 /* Single reply queue, only one irq to free */
7dc62d93 7984 free_irq(pci_irq_vector(h->pdev, 0), &h->q[h->intr_mode]);
bc2bb154 7985 h->q[h->intr_mode] = 0;
ec501a18
RE		 7986 return;
7987 }
7988
bc2bb154
CH		 7989 for (i = 0; i < h->msix_vectors; i++) {
7990 free_irq(pci_irq_vector(h->pdev, i), &h->q[i]);
105a3dbc 7991 h->q[i] = 0;
ec501a18 7992 }
a4e17fc1
RE		 7993 for (; i < MAX_REPLY_QUEUES; i++)
7994 h->q[i] = 0;
ec501a18
RE		 7995}
7996
9ee61794
RE		 7997/* returns 0 on success; cleans up and returns -Enn on error */
7998static int hpsa_request_irqs(struct ctlr_info *h,
0ae01a32
SC		 7999 irqreturn_t (*msixhandler)(int, void *),
8000 irqreturn_t (*intxhandler)(int, void *))
8001{
254f796b 8002 int rc, i;
0ae01a32 8003
254f796b
MG		 8004 /*
8005 * initialize h->q[x] = x so that interrupt handlers know which
8006 * queue to process.
8007 */
8008 for (i = 0; i < MAX_REPLY_QUEUES; i++)
8009 h->q[i] = (u8) i;
8010
bc2bb154 8011 if (h->intr_mode == PERF_MODE_INT && h->msix_vectors > 0) {
254f796b 8012 /* If performant mode and MSI-X, use multiple reply queues */
bc2bb154 8013 for (i = 0; i < h->msix_vectors; i++) {
8b47004a 8014 sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
bc2bb154 8015 rc = request_irq(pci_irq_vector(h->pdev, i), msixhandler,
8b47004a 8016 0, h->intrname[i],
254f796b 8017 &h->q[i]);
a4e17fc1
RE		 8018 if (rc) {
8019 int j;
8020
8021 dev_err(&h->pdev->dev,
8022 "failed to get irq %d for %s\n",
bc2bb154 8023 pci_irq_vector(h->pdev, i), h->devname);
a4e17fc1 8024 for (j = 0; j < i; j++) {
bc2bb154 8025 free_irq(pci_irq_vector(h->pdev, j), &h->q[j]);
a4e17fc1
RE		 8026 h->q[j] = 0;
8027 }
8028 for (; j < MAX_REPLY_QUEUES; j++)
8029 h->q[j] = 0;
8030 return rc;
8031 }
8032 }
254f796b
MG		 8033 } else {
8034 /* Use single reply pool */
bc2bb154
CH		 8035 if (h->msix_vectors > 0 || h->pdev->msi_enabled) {
8036 sprintf(h->intrname[0], "%s-msi%s", h->devname,
8037 h->msix_vectors ? "x" : "");
8038 rc = request_irq(pci_irq_vector(h->pdev, 0),
8b47004a 8039 msixhandler, 0,
bc2bb154 8040 h->intrname[0],
254f796b
MG		 8041 &h->q[h->intr_mode]);
8042 } else {
8b47004a
RE		 8043 sprintf(h->intrname[h->intr_mode],
8044 "%s-intx", h->devname);
bc2bb154 8045 rc = request_irq(pci_irq_vector(h->pdev, 0),
8b47004a 8046 intxhandler, IRQF_SHARED,
bc2bb154 8047 h->intrname[0],
254f796b
MG		 8048 &h->q[h->intr_mode]);
8049 }
8050 }
0ae01a32 8051 if (rc) {
195f2c65 8052 dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
bc2bb154 8053 pci_irq_vector(h->pdev, 0), h->devname);
195f2c65 8054 hpsa_free_irqs(h);
0ae01a32
SC		 8055 return -ENODEV;
8056 }
8057 return 0;
8058}
8059
6f039790 8060static int hpsa_kdump_soft_reset(struct ctlr_info *h)
64670ac8 8061{
39c53f55 8062 int rc;
bf43caf3 8063 hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
64670ac8
SC		 8064
8065 dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
39c53f55
RE		 8066 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
8067 if (rc) {
64670ac8 8068 dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
39c53f55 8069 return rc;
64670ac8
SC		 8070 }
8071
8072 dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
39c53f55
RE		 8073 rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
8074 if (rc) {
64670ac8
SC		 8075 dev_warn(&h->pdev->dev, "Board failed to become ready "
8076 "after soft reset.\n");
39c53f55 8077 return rc;
64670ac8
SC		 8078 }
8079
8080 return 0;
8081}
8082
072b0518
SC		 8083static void hpsa_free_reply_queues(struct ctlr_info *h)
8084{
8085 int i;
8086
8087 for (i = 0; i < h->nreply_queues; i++) {
8088 if (!h->reply_queue[i].head)
8089 continue;
8bc8f47e 8090 dma_free_coherent(&h->pdev->dev,
1fb7c98a
RE		 8091 h->reply_queue_size,
8092 h->reply_queue[i].head,
8093 h->reply_queue[i].busaddr);
072b0518
SC		 8094 h->reply_queue[i].head = NULL;
8095 h->reply_queue[i].busaddr = 0;
8096 }
105a3dbc 8097 h->reply_queue_size = 0;
072b0518
SC		 8098}
8099
0097f0f4
SC		 8100static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
8101{
105a3dbc
RE		 8102 hpsa_free_performant_mode(h); /* init_one 7 */
8103 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8104 hpsa_free_cmd_pool(h); /* init_one 5 */
8105 hpsa_free_irqs(h); /* init_one 4 */
2946e82b
RE		 8106 scsi_host_put(h->scsi_host); /* init_one 3 */
8107 h->scsi_host = NULL; /* init_one 3 */
8108 hpsa_free_pci_init(h); /* init_one 2_5 */
9ecd953a
RE		 8109 free_percpu(h->lockup_detected); /* init_one 2 */
8110 h->lockup_detected = NULL; /* init_one 2 */
8111 if (h->resubmit_wq) {
8112 destroy_workqueue(h->resubmit_wq); /* init_one 1 */
8113 h->resubmit_wq = NULL;
8114 }
8115 if (h->rescan_ctlr_wq) {
8116 destroy_workqueue(h->rescan_ctlr_wq);
8117 h->rescan_ctlr_wq = NULL;
8118 }
105a3dbc 8119 kfree(h); /* init_one 1 */
64670ac8
SC		 8120}
8121
a0c12413 8122/* Called when controller lockup detected. */
f2405db8 8123static void fail_all_outstanding_cmds(struct ctlr_info *h)
a0c12413 8124{
281a7fd0
WS		 8125 int i, refcount;
8126 struct CommandList *c;
25163bd5 8127 int failcount = 0;
a0c12413 8128
080ef1cc 8129 flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
f2405db8 8130 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 8131 c = h->cmd_pool + i;
281a7fd0
WS		 8132 refcount = atomic_inc_return(&c->refcount);
8133 if (refcount > 1) {
25163bd5 8134 c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
281a7fd0 8135 finish_cmd(c);
433b5f4d 8136 atomic_dec(&h->commands_outstanding);
25163bd5 8137 failcount++;
281a7fd0
WS		 8138 }
8139 cmd_free(h, c);
a0c12413 8140 }
25163bd5
WS		 8141 dev_warn(&h->pdev->dev,
8142 "failed %d commands in fail_all\n", failcount);
a0c12413
SC		 8143}
8144
094963da
SC		 8145static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
8146{
c8ed0010 8147 int cpu;
094963da 8148
c8ed0010 8149 for_each_online_cpu(cpu) {
094963da
SC		 8150 u32 *lockup_detected;
8151 lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
8152 *lockup_detected = value;
094963da
SC		 8153 }
8154 wmb(); /* be sure the per-cpu variables are out to memory */
8155}
8156
a0c12413
SC		 8157static void controller_lockup_detected(struct ctlr_info *h)
8158{
8159 unsigned long flags;
094963da 8160 u32 lockup_detected;
a0c12413 8161
a0c12413
SC		 8162 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8163 spin_lock_irqsave(&h->lock, flags);
094963da
SC		 8164 lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
8165 if (!lockup_detected) {
8166 /* no heartbeat, but controller gave us a zero. */
8167 dev_warn(&h->pdev->dev,
25163bd5
WS		 8168 "lockup detected after %d but scratchpad register is zero\n",
8169 h->heartbeat_sample_interval / HZ);
094963da
SC		 8170 lockup_detected = 0xffffffff;
8171 }
8172 set_lockup_detected_for_all_cpus(h, lockup_detected);
a0c12413 8173 spin_unlock_irqrestore(&h->lock, flags);
25163bd5
WS		 8174 dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
8175 lockup_detected, h->heartbeat_sample_interval / HZ);
b9b08cad
DB		 8176 if (lockup_detected == 0xffff0000) {
8177 dev_warn(&h->pdev->dev, "Telling controller to do a CHKPT\n");
8178 writel(DOORBELL_GENERATE_CHKPT, h->vaddr + SA5_DOORBELL);
8179 }
a0c12413 8180 pci_disable_device(h->pdev);
f2405db8 8181 fail_all_outstanding_cmds(h);
a0c12413
SC		 8182}
8183
25163bd5 8184static int detect_controller_lockup(struct ctlr_info *h)
a0c12413
SC		 8185{
8186 u64 now;
8187 u32 heartbeat;
8188 unsigned long flags;
8189
a0c12413
SC		 8190 now = get_jiffies_64();
8191 /* If we've received an interrupt recently, we're ok. */
8192 if (time_after64(h->last_intr_timestamp +
e85c5974 8193 (h->heartbeat_sample_interval), now))
25163bd5 8194 return false;
a0c12413
SC		 8195
8196 /*
8197 * If we've already checked the heartbeat recently, we're ok.
8198 * This could happen if someone sends us a signal. We
8199 * otherwise don't care about signals in this thread.
8200 */
8201 if (time_after64(h->last_heartbeat_timestamp +
e85c5974 8202 (h->heartbeat_sample_interval), now))
25163bd5 8203 return false;
a0c12413
SC		 8204
8205 /* If heartbeat has not changed since we last looked, we're not ok. */
8206 spin_lock_irqsave(&h->lock, flags);
8207 heartbeat = readl(&h->cfgtable->HeartBeat);
8208 spin_unlock_irqrestore(&h->lock, flags);
8209 if (h->last_heartbeat == heartbeat) {
8210 controller_lockup_detected(h);
25163bd5 8211 return true;
a0c12413
SC		 8212 }
8213
8214 /* We're ok. */
8215 h->last_heartbeat = heartbeat;
8216 h->last_heartbeat_timestamp = now;
25163bd5 8217 return false;
a0c12413
SC		 8218}
8219
b2582a65
DB		 8220/*
8221 * Set ioaccel status for all ioaccel volumes.
8222 *
8223 * Called from monitor controller worker (hpsa_event_monitor_worker)
8224 *
8225 * A Volume (or Volumes that comprise an Array set may be undergoing a
8226 * transformation, so we will be turning off ioaccel for all volumes that
8227 * make up the Array.
8228 */
8229static void hpsa_set_ioaccel_status(struct ctlr_info *h)
76438d08 8230{
b2582a65 8231 int rc;
76438d08 8232 int i;
b2582a65
DB		 8233 u8 ioaccel_status;
8234 unsigned char *buf;
8235 struct hpsa_scsi_dev_t *device;
8236
8237 if (!h)
8238 return;
8239
8240 buf = kmalloc(64, GFP_KERNEL);
8241 if (!buf)
8242 return;
8243
8244 /*
8245 * Run through current device list used during I/O requests.
8246 */
8247 for (i = 0; i < h->ndevices; i++) {
8248 device = h->dev[i];
8249
8250 if (!device)
8251 continue;
b2582a65
DB		 8252 if (!hpsa_vpd_page_supported(h, device->scsi3addr,
8253 HPSA_VPD_LV_IOACCEL_STATUS))
8254 continue;
8255
8256 memset(buf, 0, 64);
8257
8258 rc = hpsa_scsi_do_inquiry(h, device->scsi3addr,
8259 VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS,
8260 buf, 64);
8261 if (rc != 0)
8262 continue;
8263
8264 ioaccel_status = buf[IOACCEL_STATUS_BYTE];
8265 device->offload_config =
8266 !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
8267 if (device->offload_config)
8268 device->offload_to_be_enabled =
8269 !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
8270
8271 /*
8272 * Immediately turn off ioaccel for any volume the
8273 * controller tells us to. Some of the reasons could be:
8274 * transformation - change to the LVs of an Array.
8275 * degraded volume - component failure
8276 *
8277 * If ioaccel is to be re-enabled, re-enable later during the
8278 * scan operation so the driver can get a fresh raidmap
8279 * before turning ioaccel back on.
8280 *
8281 */
8282 if (!device->offload_to_be_enabled)
8283 device->offload_enabled = 0;
8284 }
8285
8286 kfree(buf);
8287}
8288
8289static void hpsa_ack_ctlr_events(struct ctlr_info *h)
8290{
76438d08
SC		 8291 char *event_type;
8292
e4aa3e6a
SC		 8293 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
8294 return;
8295
76438d08 8296 /* Ask the controller to clear the events we're handling. */
1f7cee8c
SC		 8297 if ((h->transMethod & (CFGTBL_Trans_io_accel1
8298 | CFGTBL_Trans_io_accel2)) &&
76438d08
SC		 8299 (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
8300 h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
8301
8302 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
8303 event_type = "state change";
8304 if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
8305 event_type = "configuration change";
8306 /* Stop sending new RAID offload reqs via the IO accelerator */
8307 scsi_block_requests(h->scsi_host);
b2582a65 8308 hpsa_set_ioaccel_status(h);
23100dd9 8309 hpsa_drain_accel_commands(h);
76438d08
SC		 8310 /* Set 'accelerator path config change' bit */
8311 dev_warn(&h->pdev->dev,
8312 "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
8313 h->events, event_type);
8314 writel(h->events, &(h->cfgtable->clear_event_notify));
8315 /* Set the "clear event notify field update" bit 6 */
8316 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
8317 /* Wait until ctlr clears 'clear event notify field', bit 6 */
8318 hpsa_wait_for_clear_event_notify_ack(h);
8319 scsi_unblock_requests(h->scsi_host);
8320 } else {
8321 /* Acknowledge controller notification events. */
8322 writel(h->events, &(h->cfgtable->clear_event_notify));
8323 writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
8324 hpsa_wait_for_clear_event_notify_ack(h);
76438d08 8325 }
9846590e 8326 return;
76438d08
SC		 8327}
8328
8329/* Check a register on the controller to see if there are configuration
8330 * changes (added/changed/removed logical drives, etc.) which mean that
e863d68e
ST		 8331 * we should rescan the controller for devices.
8332 * Also check flag for driver-initiated rescan.
76438d08 8333 */
9846590e 8334static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
76438d08 8335{
853633e8
DB		 8336 if (h->drv_req_rescan) {
8337 h->drv_req_rescan = 0;
8338 return 1;
8339 }
8340
76438d08 8341 if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
9846590e 8342 return 0;
76438d08
SC		 8343
8344 h->events = readl(&(h->cfgtable->event_notify));
9846590e
SC		 8345 return h->events & RESCAN_REQUIRED_EVENT_BITS;
8346}
76438d08 8347
9846590e
SC		 8348/*
8349 * Check if any of the offline devices have become ready
8350 */
8351static int hpsa_offline_devices_ready(struct ctlr_info *h)
8352{
8353 unsigned long flags;
8354 struct offline_device_entry *d;
8355 struct list_head *this, *tmp;
8356
8357 spin_lock_irqsave(&h->offline_device_lock, flags);
8358 list_for_each_safe(this, tmp, &h->offline_device_list) {
8359 d = list_entry(this, struct offline_device_entry,
8360 offline_list);
8361 spin_unlock_irqrestore(&h->offline_device_lock, flags);
d1fea47c
SC		 8362 if (!hpsa_volume_offline(h, d->scsi3addr)) {
8363 spin_lock_irqsave(&h->offline_device_lock, flags);
8364 list_del(&d->offline_list);
8365 spin_unlock_irqrestore(&h->offline_device_lock, flags);
9846590e 8366 return 1;
d1fea47c 8367 }
9846590e
SC		 8368 spin_lock_irqsave(&h->offline_device_lock, flags);
8369 }
8370 spin_unlock_irqrestore(&h->offline_device_lock, flags);
8371 return 0;
76438d08
SC		 8372}
8373
34592254
ST		 8374static int hpsa_luns_changed(struct ctlr_info *h)
8375{
8376 int rc = 1; /* assume there are changes */
8377 struct ReportLUNdata *logdev = NULL;
8378
8379 /* if we can't find out if lun data has changed,
8380 * assume that it has.
8381 */
8382
8383 if (!h->lastlogicals)
7e8a9486 8384 return rc;
34592254
ST		 8385
8386 logdev = kzalloc(sizeof(*logdev), GFP_KERNEL);
7e8a9486
AK		 8387 if (!logdev)
8388 return rc;
8389
34592254
ST		 8390 if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) {
8391 dev_warn(&h->pdev->dev,
8392 "report luns failed, can't track lun changes.\n");
8393 goto out;
8394 }
8395 if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) {
8396 dev_info(&h->pdev->dev,
8397 "Lun changes detected.\n");
8398 memcpy(h->lastlogicals, logdev, sizeof(*logdev));
8399 goto out;
8400 } else
8401 rc = 0; /* no changes detected. */
8402out:
8403 kfree(logdev);
8404 return rc;
8405}
8406
3d38f00c 8407static void hpsa_perform_rescan(struct ctlr_info *h)
a0c12413 8408{
3d38f00c 8409 struct Scsi_Host *sh = NULL;
a0c12413 8410 unsigned long flags;
9846590e 8411
bfd7546c
DB		 8412 /*
8413 * Do the scan after the reset
8414 */
c59d04f3 8415 spin_lock_irqsave(&h->reset_lock, flags);
bfd7546c
DB		 8416 if (h->reset_in_progress) {
8417 h->drv_req_rescan = 1;
c59d04f3 8418 spin_unlock_irqrestore(&h->reset_lock, flags);
bfd7546c
DB		 8419 return;
8420 }
c59d04f3 8421 spin_unlock_irqrestore(&h->reset_lock, flags);
bfd7546c 8422
3d38f00c
ST		 8423 sh = scsi_host_get(h->scsi_host);
8424 if (sh != NULL) {
8425 hpsa_scan_start(sh);
8426 scsi_host_put(sh);
8427 h->drv_req_rescan = 0;
8428 }
8429}
8430
8431/*
8432 * watch for controller events
8433 */
8434static void hpsa_event_monitor_worker(struct work_struct *work)
8435{
8436 struct ctlr_info *h = container_of(to_delayed_work(work),
8437 struct ctlr_info, event_monitor_work);
8438 unsigned long flags;
8439
8440 spin_lock_irqsave(&h->lock, flags);
8441 if (h->remove_in_progress) {
8442 spin_unlock_irqrestore(&h->lock, flags);
8443 return;
8444 }
8445 spin_unlock_irqrestore(&h->lock, flags);
8446
8447 if (hpsa_ctlr_needs_rescan(h)) {
9846590e 8448 hpsa_ack_ctlr_events(h);
3d38f00c
ST		 8449 hpsa_perform_rescan(h);
8450 }
8451
8452 spin_lock_irqsave(&h->lock, flags);
8453 if (!h->remove_in_progress)
8454 schedule_delayed_work(&h->event_monitor_work,
8455 HPSA_EVENT_MONITOR_INTERVAL);
8456 spin_unlock_irqrestore(&h->lock, flags);
8457}
8458
8459static void hpsa_rescan_ctlr_worker(struct work_struct *work)
8460{
8461 unsigned long flags;
8462 struct ctlr_info *h = container_of(to_delayed_work(work),
8463 struct ctlr_info, rescan_ctlr_work);
8464
8465 spin_lock_irqsave(&h->lock, flags);
8466 if (h->remove_in_progress) {
8467 spin_unlock_irqrestore(&h->lock, flags);
8468 return;
8469 }
8470 spin_unlock_irqrestore(&h->lock, flags);
8471
8472 if (h->drv_req_rescan || hpsa_offline_devices_ready(h)) {
8473 hpsa_perform_rescan(h);
34592254
ST		 8474 } else if (h->discovery_polling) {
8475 if (hpsa_luns_changed(h)) {
34592254
ST		 8476 dev_info(&h->pdev->dev,
8477 "driver discovery polling rescan.\n");
3d38f00c 8478 hpsa_perform_rescan(h);
34592254 8479 }
9846590e 8480 }
8a98db73 8481 spin_lock_irqsave(&h->lock, flags);
6636e7f4
DB		 8482 if (!h->remove_in_progress)
8483 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8484 h->heartbeat_sample_interval);
8485 spin_unlock_irqrestore(&h->lock, flags);
8486}
8487
8488static void hpsa_monitor_ctlr_worker(struct work_struct *work)
8489{
8490 unsigned long flags;
8491 struct ctlr_info *h = container_of(to_delayed_work(work),
8492 struct ctlr_info, monitor_ctlr_work);
8493
8494 detect_controller_lockup(h);
8495 if (lockup_detected(h))
a0c12413 8496 return;
6636e7f4
DB		 8497
8498 spin_lock_irqsave(&h->lock, flags);
8499 if (!h->remove_in_progress)
8500 schedule_delayed_work(&h->monitor_ctlr_work,
8a98db73
SC		 8501 h->heartbeat_sample_interval);
8502 spin_unlock_irqrestore(&h->lock, flags);
a0c12413
SC		 8503}
8504
6636e7f4
DB		 8505static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
8506 char *name)
8507{
8508 struct workqueue_struct *wq = NULL;
6636e7f4 8509
397ea9cb 8510 wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
6636e7f4
DB		 8511 if (!wq)
8512 dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
8513
8514 return wq;
8515}
8516
8b834bff
ML		 8517static void hpda_free_ctlr_info(struct ctlr_info *h)
8518{
8519 kfree(h->reply_map);
8520 kfree(h);
8521}
8522
8523static struct ctlr_info *hpda_alloc_ctlr_info(void)
8524{
8525 struct ctlr_info *h;
8526
8527 h = kzalloc(sizeof(*h), GFP_KERNEL);
8528 if (!h)
8529 return NULL;
8530
6396bb22 8531 h->reply_map = kcalloc(nr_cpu_ids, sizeof(*h->reply_map), GFP_KERNEL);
8b834bff
ML		 8532 if (!h->reply_map) {
8533 kfree(h);
8534 return NULL;
8535 }
8536 return h;
8537}
8538
6f039790 8539static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
edd16368 8540{
4c2a8c40 8541 int dac, rc;
edd16368 8542 struct ctlr_info *h;
64670ac8
SC		 8543 int try_soft_reset = 0;
8544 unsigned long flags;
6b6c1cd7 8545 u32 board_id;
edd16368
SC		 8546
8547 if (number_of_controllers == 0)
8548 printk(KERN_INFO DRIVER_NAME "\n");
edd16368 8549
135ae6ed 8550 rc = hpsa_lookup_board_id(pdev, &board_id, NULL);
6b6c1cd7
TH		 8551 if (rc < 0) {
8552 dev_warn(&pdev->dev, "Board ID not found\n");
8553 return rc;
8554 }
8555
8556 rc = hpsa_init_reset_devices(pdev, board_id);
64670ac8
SC		 8557 if (rc) {
8558 if (rc != -ENOTSUPP)
8559 return rc;
8560 /* If the reset fails in a particular way (it has no way to do
8561 * a proper hard reset, so returns -ENOTSUPP) we can try to do
8562 * a soft reset once we get the controller configured up to the
8563 * point that it can accept a command.
8564 */
8565 try_soft_reset = 1;
8566 rc = 0;
8567 }
8568
8569reinit_after_soft_reset:
edd16368 8570
303932fd
DB		 8571 /* Command structures must be aligned on a 32-byte boundary because
8572 * the 5 lower bits of the address are used by the hardware. and by
8573 * the driver. See comments in hpsa.h for more info.
8574 */
303932fd 8575 BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
8b834bff 8576 h = hpda_alloc_ctlr_info();
105a3dbc
RE		 8577 if (!h) {
8578 dev_err(&pdev->dev, "Failed to allocate controller head\n");
ecd9aad4 8579 return -ENOMEM;
105a3dbc 8580 }
edd16368 8581
55c06c71 8582 h->pdev = pdev;
105a3dbc 8583
a9a3a273 8584 h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
9846590e 8585 INIT_LIST_HEAD(&h->offline_device_list);
6eaf46fd 8586 spin_lock_init(&h->lock);
9846590e 8587 spin_lock_init(&h->offline_device_lock);
6eaf46fd 8588 spin_lock_init(&h->scan_lock);
c59d04f3 8589 spin_lock_init(&h->reset_lock);
34f0c627 8590 atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
094963da
SC		 8591
8592 /* Allocate and clear per-cpu variable lockup_detected */
8593 h->lockup_detected = alloc_percpu(u32);
2a5ac326 8594 if (!h->lockup_detected) {
105a3dbc 8595 dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
2a5ac326 8596 rc = -ENOMEM;
2efa5929 8597 goto clean1; /* aer/h */
2a5ac326 8598 }
094963da
SC		 8599 set_lockup_detected_for_all_cpus(h, 0);
8600
55c06c71 8601 rc = hpsa_pci_init(h);
105a3dbc 8602 if (rc)
2946e82b
RE		 8603 goto clean2; /* lu, aer/h */
8604
8605 /* relies on h-> settings made by hpsa_pci_init, including
8606 * interrupt_mode h->intr */
8607 rc = hpsa_scsi_host_alloc(h);
8608 if (rc)
8609 goto clean2_5; /* pci, lu, aer/h */
edd16368 8610
2946e82b 8611 sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
edd16368
SC		 8612 h->ctlr = number_of_controllers;
8613 number_of_controllers++;
edd16368
SC		 8614
8615 /* configure PCI DMA stuff */
8bc8f47e 8616 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
ecd9aad4 8617 if (rc == 0) {
edd16368 8618 dac = 1;
ecd9aad4 8619 } else {
8bc8f47e 8620 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
ecd9aad4
SC		 8621 if (rc == 0) {
8622 dac = 0;
8623 } else {
8624 dev_err(&pdev->dev, "no suitable DMA available\n");
2946e82b 8625 goto clean3; /* shost, pci, lu, aer/h */
ecd9aad4 8626 }
edd16368
SC		 8627 }
8628
8629 /* make sure the board interrupts are off */
8630 h->access.set_intr_mask(h, HPSA_INTR_OFF);
10f66018 8631
105a3dbc
RE		 8632 rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
8633 if (rc)
2946e82b 8634 goto clean3; /* shost, pci, lu, aer/h */
d37ffbe4 8635 rc = hpsa_alloc_cmd_pool(h);
8947fd10 8636 if (rc)
2946e82b 8637 goto clean4; /* irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8638 rc = hpsa_alloc_sg_chain_blocks(h);
8639 if (rc)
2946e82b 8640 goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
a08a8471 8641 init_waitqueue_head(&h->scan_wait_queue);
d604f533
WS		 8642 init_waitqueue_head(&h->event_sync_wait_queue);
8643 mutex_init(&h->reset_mutex);
a08a8471 8644 h->scan_finished = 1; /* no scan currently in progress */
87b9e6aa 8645 h->scan_waiting = 0;
edd16368
SC		 8646
8647 pci_set_drvdata(pdev, h);
9a41338e 8648 h->ndevices = 0;
2946e82b 8649
9a41338e 8650 spin_lock_init(&h->devlock);
105a3dbc
RE		 8651 rc = hpsa_put_ctlr_into_performant_mode(h);
8652 if (rc)
2946e82b
RE		 8653 goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
8654
2efa5929
RE		 8655 /* create the resubmit workqueue */
8656 h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
8657 if (!h->rescan_ctlr_wq) {
8658 rc = -ENOMEM;
8659 goto clean7;
8660 }
8661
8662 h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
8663 if (!h->resubmit_wq) {
8664 rc = -ENOMEM;
8665 goto clean7; /* aer/h */
8666 }
64670ac8 8667
105a3dbc
RE		 8668 /*
8669 * At this point, the controller is ready to take commands.
64670ac8
SC		 8670 * Now, if reset_devices and the hard reset didn't work, try
8671 * the soft reset and see if that works.
8672 */
8673 if (try_soft_reset) {
8674
8675 /* This is kind of gross. We may or may not get a completion
8676 * from the soft reset command, and if we do, then the value
8677 * from the fifo may or may not be valid. So, we wait 10 secs
8678 * after the reset throwing away any completions we get during
8679 * that time. Unregister the interrupt handler and register
8680 * fake ones to scoop up any residual completions.
8681 */
8682 spin_lock_irqsave(&h->lock, flags);
8683 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8684 spin_unlock_irqrestore(&h->lock, flags);
ec501a18 8685 hpsa_free_irqs(h);
9ee61794 8686 rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
64670ac8
SC		 8687 hpsa_intx_discard_completions);
8688 if (rc) {
9ee61794
RE		 8689 dev_warn(&h->pdev->dev,
8690 "Failed to request_irq after soft reset.\n");
d498757c 8691 /*
b2ef480c
RE		 8692 * cannot goto clean7 or free_irqs will be called
8693 * again. Instead, do its work
8694 */
8695 hpsa_free_performant_mode(h); /* clean7 */
8696 hpsa_free_sg_chain_blocks(h); /* clean6 */
8697 hpsa_free_cmd_pool(h); /* clean5 */
8698 /*
8699 * skip hpsa_free_irqs(h) clean4 since that
8700 * was just called before request_irqs failed
d498757c
RE		 8701 */
8702 goto clean3;
64670ac8
SC		 8703 }
8704
8705 rc = hpsa_kdump_soft_reset(h);
8706 if (rc)
8707 /* Neither hard nor soft reset worked, we're hosed. */
7ef7323f 8708 goto clean7;
64670ac8
SC		 8709
8710 dev_info(&h->pdev->dev, "Board READY.\n");
8711 dev_info(&h->pdev->dev,
8712 "Waiting for stale completions to drain.\n");
8713 h->access.set_intr_mask(h, HPSA_INTR_ON);
8714 msleep(10000);
8715 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8716
8717 rc = controller_reset_failed(h->cfgtable);
8718 if (rc)
8719 dev_info(&h->pdev->dev,
8720 "Soft reset appears to have failed.\n");
8721
8722 /* since the controller's reset, we have to go back and re-init
8723 * everything. Easiest to just forget what we've done and do it
8724 * all over again.
8725 */
8726 hpsa_undo_allocations_after_kdump_soft_reset(h);
8727 try_soft_reset = 0;
8728 if (rc)
b2ef480c 8729 /* don't goto clean, we already unallocated */
64670ac8
SC		 8730 return -ENODEV;
8731
8732 goto reinit_after_soft_reset;
8733 }
edd16368 8734
105a3dbc
RE		 8735 /* Enable Accelerated IO path at driver layer */
8736 h->acciopath_status = 1;
34592254
ST		 8737 /* Disable discovery polling.*/
8738 h->discovery_polling = 0;
da0697bd 8739
e863d68e 8740
edd16368
SC		 8741 /* Turn the interrupts on so we can service requests */
8742 h->access.set_intr_mask(h, HPSA_INTR_ON);
8743
339b2b14 8744 hpsa_hba_inquiry(h);
8a98db73 8745
34592254
ST		 8746 h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL);
8747 if (!h->lastlogicals)
8748 dev_info(&h->pdev->dev,
8749 "Can't track change to report lun data\n");
8750
cf477237
DB		 8751 /* hook into SCSI subsystem */
8752 rc = hpsa_scsi_add_host(h);
8753 if (rc)
8754 goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
8755
8a98db73
SC		 8756 /* Monitor the controller for firmware lockups */
8757 h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
8758 INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
8759 schedule_delayed_work(&h->monitor_ctlr_work,
8760 h->heartbeat_sample_interval);
6636e7f4
DB		 8761 INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
8762 queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
8763 h->heartbeat_sample_interval);
3d38f00c
ST		 8764 INIT_DELAYED_WORK(&h->event_monitor_work, hpsa_event_monitor_worker);
8765 schedule_delayed_work(&h->event_monitor_work,
8766 HPSA_EVENT_MONITOR_INTERVAL);
88bf6d62 8767 return 0;
edd16368 8768
2946e82b 8769clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
105a3dbc
RE		 8770 hpsa_free_performant_mode(h);
8771 h->access.set_intr_mask(h, HPSA_INTR_OFF);
8772clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
33a2ffce 8773 hpsa_free_sg_chain_blocks(h);
2946e82b 8774clean5: /* cmd, irq, shost, pci, lu, aer/h */
2e9d1b36 8775 hpsa_free_cmd_pool(h);
2946e82b 8776clean4: /* irq, shost, pci, lu, aer/h */
ec501a18 8777 hpsa_free_irqs(h);
2946e82b
RE		 8778clean3: /* shost, pci, lu, aer/h */
8779 scsi_host_put(h->scsi_host);
8780 h->scsi_host = NULL;
8781clean2_5: /* pci, lu, aer/h */
195f2c65 8782 hpsa_free_pci_init(h);
2946e82b 8783clean2: /* lu, aer/h */
105a3dbc
RE		 8784 if (h->lockup_detected) {
8785 free_percpu(h->lockup_detected);
8786 h->lockup_detected = NULL;
8787 }
8788clean1: /* wq/aer/h */
8789 if (h->resubmit_wq) {
080ef1cc 8790 destroy_workqueue(h->resubmit_wq);
105a3dbc
RE		 8791 h->resubmit_wq = NULL;
8792 }
8793 if (h->rescan_ctlr_wq) {
6636e7f4 8794 destroy_workqueue(h->rescan_ctlr_wq);
105a3dbc
RE		 8795 h->rescan_ctlr_wq = NULL;
8796 }
edd16368 8797 kfree(h);
ecd9aad4 8798 return rc;
edd16368
SC		 8799}
8800
8801static void hpsa_flush_cache(struct ctlr_info *h)
8802{
8803 char *flush_buf;
8804 struct CommandList *c;
25163bd5 8805 int rc;
702890e3 8806
094963da 8807 if (unlikely(lockup_detected(h)))
702890e3 8808 return;
edd16368
SC		 8809 flush_buf = kzalloc(4, GFP_KERNEL);
8810 if (!flush_buf)
8811 return;
8812
45fcb86e 8813 c = cmd_alloc(h);
bf43caf3 8814
a2dac136
SC		 8815 if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
8816 RAID_CTLR_LUNID, TYPE_CMD)) {
8817 goto out;
8818 }
8bc8f47e
CH		 8819 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_TO_DEVICE,
8820 DEFAULT_TIMEOUT);
25163bd5
WS		 8821 if (rc)
8822 goto out;
edd16368 8823 if (c->err_info->CommandStatus != 0)
a2dac136 8824out:
edd16368
SC		 8825 dev_warn(&h->pdev->dev,
8826 "error flushing cache on controller\n");
45fcb86e 8827 cmd_free(h, c);
edd16368
SC		 8828 kfree(flush_buf);
8829}
8830
c2adae44
ST		 8831/* Make controller gather fresh report lun data each time we
8832 * send down a report luns request
8833 */
8834static void hpsa_disable_rld_caching(struct ctlr_info *h)
8835{
8836 u32 *options;
8837 struct CommandList *c;
8838 int rc;
8839
8840 /* Don't bother trying to set diag options if locked up */
8841 if (unlikely(h->lockup_detected))
8842 return;
8843
8844 options = kzalloc(sizeof(*options), GFP_KERNEL);
7e8a9486 8845 if (!options)
c2adae44 8846 return;
c2adae44
ST		 8847
8848 c = cmd_alloc(h);
8849
8850 /* first, get the current diag options settings */
8851 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
8852 RAID_CTLR_LUNID, TYPE_CMD))
8853 goto errout;
8854
8bc8f47e
CH		 8855 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
8856 NO_TIMEOUT);
c2adae44
ST		 8857 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8858 goto errout;
8859
8860 /* Now, set the bit for disabling the RLD caching */
8861 *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING;
8862
8863 if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0,
8864 RAID_CTLR_LUNID, TYPE_CMD))
8865 goto errout;
8866
8bc8f47e
CH		 8867 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_TO_DEVICE,
8868 NO_TIMEOUT);
c2adae44
ST		 8869 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8870 goto errout;
8871
8872 /* Now verify that it got set: */
8873 if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
8874 RAID_CTLR_LUNID, TYPE_CMD))
8875 goto errout;
8876
8bc8f47e
CH		 8877 rc = hpsa_scsi_do_simple_cmd_with_retry(h, c, DMA_FROM_DEVICE,
8878 NO_TIMEOUT);
c2adae44
ST		 8879 if ((rc != 0) || (c->err_info->CommandStatus != 0))
8880 goto errout;
8881
d8a080c3 8882 if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING)
c2adae44
ST		 8883 goto out;
8884
8885errout:
8886 dev_err(&h->pdev->dev,
8887 "Error: failed to disable report lun data caching.\n");
8888out:
8889 cmd_free(h, c);
8890 kfree(options);
8891}
8892
0d98ba8d 8893static void __hpsa_shutdown(struct pci_dev *pdev)
edd16368
SC		 8894{
8895 struct ctlr_info *h;
8896
8897 h = pci_get_drvdata(pdev);
8898 /* Turn board interrupts off and send the flush cache command
8899 * sendcmd will turn off interrupt, and send the flush...
8900 * To write all data in the battery backed cache to disks
8901 */
8902 hpsa_flush_cache(h);
8903 h->access.set_intr_mask(h, HPSA_INTR_OFF);
105a3dbc 8904 hpsa_free_irqs(h); /* init_one 4 */
cc64c817 8905 hpsa_disable_interrupt_mode(h); /* pci_init 2 */
edd16368
SC		 8906}
8907
0d98ba8d
SK		 8908static void hpsa_shutdown(struct pci_dev *pdev)
8909{
8910 __hpsa_shutdown(pdev);
8911 pci_disable_device(pdev);
8912}
8913
6f039790 8914static void hpsa_free_device_info(struct ctlr_info *h)
55e14e76
SC		 8915{
8916 int i;
8917
105a3dbc 8918 for (i = 0; i < h->ndevices; i++) {
55e14e76 8919 kfree(h->dev[i]);
105a3dbc
RE		 8920 h->dev[i] = NULL;
8921 }
55e14e76
SC		 8922}
8923
6f039790 8924static void hpsa_remove_one(struct pci_dev *pdev)
edd16368
SC		 8925{
8926 struct ctlr_info *h;
8a98db73 8927 unsigned long flags;
edd16368
SC		 8928
8929 if (pci_get_drvdata(pdev) == NULL) {
a0c12413 8930 dev_err(&pdev->dev, "unable to remove device\n");
edd16368
SC		 8931 return;
8932 }
8933 h = pci_get_drvdata(pdev);
8a98db73
SC		 8934
8935 /* Get rid of any controller monitoring work items */
8936 spin_lock_irqsave(&h->lock, flags);
8937 h->remove_in_progress = 1;
8a98db73 8938 spin_unlock_irqrestore(&h->lock, flags);
6636e7f4
DB		 8939 cancel_delayed_work_sync(&h->monitor_ctlr_work);
8940 cancel_delayed_work_sync(&h->rescan_ctlr_work);
3d38f00c 8941 cancel_delayed_work_sync(&h->event_monitor_work);
6636e7f4
DB		 8942 destroy_workqueue(h->rescan_ctlr_wq);
8943 destroy_workqueue(h->resubmit_wq);
cc64c817 8944
dfb2e6f4
MW		 8945 hpsa_delete_sas_host(h);
8946
2d041306
DB		 8947 /*
8948 * Call before disabling interrupts.
8949 * scsi_remove_host can trigger I/O operations especially
8950 * when multipath is enabled. There can be SYNCHRONIZE CACHE
8951 * operations which cannot complete and will hang the system.
8952 */
8953 if (h->scsi_host)
8954 scsi_remove_host(h->scsi_host); /* init_one 8 */
105a3dbc 8955 /* includes hpsa_free_irqs - init_one 4 */
195f2c65 8956 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
0d98ba8d 8957 __hpsa_shutdown(pdev);
cc64c817 8958
105a3dbc
RE		 8959 hpsa_free_device_info(h); /* scan */
8960
2946e82b
RE		 8961 kfree(h->hba_inquiry_data); /* init_one 10 */
8962 h->hba_inquiry_data = NULL; /* init_one 10 */
2946e82b 8963 hpsa_free_ioaccel2_sg_chain_blocks(h);
105a3dbc
RE		 8964 hpsa_free_performant_mode(h); /* init_one 7 */
8965 hpsa_free_sg_chain_blocks(h); /* init_one 6 */
8966 hpsa_free_cmd_pool(h); /* init_one 5 */
34592254 8967 kfree(h->lastlogicals);
105a3dbc
RE		 8968
8969 /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
195f2c65 8970
2946e82b
RE		 8971 scsi_host_put(h->scsi_host); /* init_one 3 */
8972 h->scsi_host = NULL; /* init_one 3 */
8973
195f2c65 8974 /* includes hpsa_disable_interrupt_mode - pci_init 2 */
2946e82b 8975 hpsa_free_pci_init(h); /* init_one 2.5 */
195f2c65 8976
105a3dbc
RE		 8977 free_percpu(h->lockup_detected); /* init_one 2 */
8978 h->lockup_detected = NULL; /* init_one 2 */
8979 /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
d04e62b9 8980
8b834bff 8981 hpda_free_ctlr_info(h); /* init_one 1 */
edd16368
SC		 8982}
8983
8984static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
8985 __attribute__((unused)) pm_message_t state)
8986{
8987 return -ENOSYS;
8988}
8989
8990static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
8991{
8992 return -ENOSYS;
8993}
8994
8995static struct pci_driver hpsa_pci_driver = {
f79cfec6 8996 .name = HPSA,
edd16368 8997 .probe = hpsa_init_one,
6f039790 8998 .remove = hpsa_remove_one,
edd16368
SC		 8999 .id_table = hpsa_pci_device_id, /* id_table */
9000 .shutdown = hpsa_shutdown,
9001 .suspend = hpsa_suspend,
9002 .resume = hpsa_resume,
9003};
9004
303932fd
DB		 9005/* Fill in bucket_map[], given nsgs (the max number of
9006 * scatter gather elements supported) and bucket[],
9007 * which is an array of 8 integers. The bucket[] array
9008 * contains 8 different DMA transfer sizes (in 16
9009 * byte increments) which the controller uses to fetch
9010 * commands. This function fills in bucket_map[], which
9011 * maps a given number of scatter gather elements to one of
9012 * the 8 DMA transfer sizes. The point of it is to allow the
9013 * controller to only do as much DMA as needed to fetch the
9014 * command, with the DMA transfer size encoded in the lower
9015 * bits of the command address.
9016 */
9017static void calc_bucket_map(int bucket[], int num_buckets,
2b08b3e9 9018 int nsgs, int min_blocks, u32 *bucket_map)
303932fd
DB		 9019{
9020 int i, j, b, size;
9021
303932fd
DB		 9022 /* Note, bucket_map must have nsgs+1 entries. */
9023 for (i = 0; i <= nsgs; i++) {
9024 /* Compute size of a command with i SG entries */
e1f7de0c 9025 size = i + min_blocks;
303932fd
DB		 9026 b = num_buckets; /* Assume the biggest bucket */
9027 /* Find the bucket that is just big enough */
e1f7de0c 9028 for (j = 0; j < num_buckets; j++) {
303932fd
DB		 9029 if (bucket[j] >= size) {
9030 b = j;
9031 break;
9032 }
9033 }
9034 /* for a command with i SG entries, use bucket b. */
9035 bucket_map[i] = b;
9036 }
9037}
9038
105a3dbc
RE		 9039/*
9040 * return -ENODEV on err, 0 on success (or no action)
9041 * allocates numerous items that must be freed later
9042 */
c706a795 9043static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
303932fd 9044{
6c311b57
SC		 9045 int i;
9046 unsigned long register_value;
e1f7de0c
MG		 9047 unsigned long transMethod = CFGTBL_Trans_Performant |
9048 (trans_support & CFGTBL_Trans_use_short_tags) |
b9af4937
SC		 9049 CFGTBL_Trans_enable_directed_msix |
9050 (trans_support & (CFGTBL_Trans_io_accel1 |
9051 CFGTBL_Trans_io_accel2));
e1f7de0c 9052 struct access_method access = SA5_performant_access;
def342bd
SC		 9053
9054 /* This is a bit complicated. There are 8 registers on
9055 * the controller which we write to to tell it 8 different
9056 * sizes of commands which there may be. It's a way of
9057 * reducing the DMA done to fetch each command. Encoded into
9058 * each command's tag are 3 bits which communicate to the controller
9059 * which of the eight sizes that command fits within. The size of
9060 * each command depends on how many scatter gather entries there are.
9061 * Each SG entry requires 16 bytes. The eight registers are programmed
9062 * with the number of 16-byte blocks a command of that size requires.
9063 * The smallest command possible requires 5 such 16 byte blocks.
d66ae08b 9064 * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
def342bd
SC		 9065 * blocks. Note, this only extends to the SG entries contained
9066 * within the command block, and does not extend to chained blocks
9067 * of SG elements. bft[] contains the eight values we write to
9068 * the registers. They are not evenly distributed, but have more
9069 * sizes for small commands, and fewer sizes for larger commands.
9070 */
d66ae08b 9071 int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
b9af4937
SC		 9072#define MIN_IOACCEL2_BFT_ENTRY 5
9073#define HPSA_IOACCEL2_HEADER_SZ 4
9074 int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
9075 13, 14, 15, 16, 17, 18, 19,
9076 HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
9077 BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
9078 BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
9079 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
9080 16 * MIN_IOACCEL2_BFT_ENTRY);
9081 BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
d66ae08b 9082 BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
303932fd
DB		 9083 /* 5 = 1 s/g entry or 4k
9084 * 6 = 2 s/g entry or 8k
9085 * 8 = 4 s/g entry or 16k
9086 * 10 = 6 s/g entry or 24k
9087 */
303932fd 9088
b3a52e79
SC		 9089 /* If the controller supports either ioaccel method then
9090 * we can also use the RAID stack submit path that does not
9091 * perform the superfluous readl() after each command submission.
9092 */
9093 if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
9094 access = SA5_performant_access_no_read;
9095
303932fd 9096 /* Controller spec: zero out this buffer. */
072b0518
SC		 9097 for (i = 0; i < h->nreply_queues; i++)
9098 memset(h->reply_queue[i].head, 0, h->reply_queue_size);
303932fd 9099
d66ae08b
SC		 9100 bft[7] = SG_ENTRIES_IN_CMD + 4;
9101 calc_bucket_map(bft, ARRAY_SIZE(bft),
e1f7de0c 9102 SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
303932fd
DB		 9103 for (i = 0; i < 8; i++)
9104 writel(bft[i], &h->transtable->BlockFetch[i]);
9105
9106 /* size of controller ring buffer */
9107 writel(h->max_commands, &h->transtable->RepQSize);
254f796b 9108 writel(h->nreply_queues, &h->transtable->RepQCount);
303932fd
DB		 9109 writel(0, &h->transtable->RepQCtrAddrLow32);
9110 writel(0, &h->transtable->RepQCtrAddrHigh32);
254f796b
MG		 9111
9112 for (i = 0; i < h->nreply_queues; i++) {
9113 writel(0, &h->transtable->RepQAddr[i].upper);
072b0518 9114 writel(h->reply_queue[i].busaddr,
254f796b
MG		 9115 &h->transtable->RepQAddr[i].lower);
9116 }
9117
b9af4937 9118 writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
e1f7de0c
MG		 9119 writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
9120 /*
9121 * enable outbound interrupt coalescing in accelerator mode;
9122 */
9123 if (trans_support & CFGTBL_Trans_io_accel1) {
9124 access = SA5_ioaccel_mode1_access;
9125 writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
9126 writel(4, &h->cfgtable->HostWrite.CoalIntCount);
96b6ce4e
DB		 9127 } else
9128 if (trans_support & CFGTBL_Trans_io_accel2)
c349775e 9129 access = SA5_ioaccel_mode2_access;
303932fd 9130 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 9131 if (hpsa_wait_for_mode_change_ack(h)) {
9132 dev_err(&h->pdev->dev,
9133 "performant mode problem - doorbell timeout\n");
9134 return -ENODEV;
9135 }
303932fd
DB		 9136 register_value = readl(&(h->cfgtable->TransportActive));
9137 if (!(register_value & CFGTBL_Trans_Performant)) {
050f7147
SC		 9138 dev_err(&h->pdev->dev,
9139 "performant mode problem - transport not active\n");
c706a795 9140 return -ENODEV;
303932fd 9141 }
960a30e7 9142 /* Change the access methods to the performant access methods */
e1f7de0c
MG		 9143 h->access = access;
9144 h->transMethod = transMethod;
9145
b9af4937
SC		 9146 if (!((trans_support & CFGTBL_Trans_io_accel1) ||
9147 (trans_support & CFGTBL_Trans_io_accel2)))
c706a795 9148 return 0;
e1f7de0c 9149
b9af4937
SC		 9150 if (trans_support & CFGTBL_Trans_io_accel1) {
9151 /* Set up I/O accelerator mode */
9152 for (i = 0; i < h->nreply_queues; i++) {
9153 writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
9154 h->reply_queue[i].current_entry =
9155 readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
9156 }
9157 bft[7] = h->ioaccel_maxsg + 8;
9158 calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
9159 h->ioaccel1_blockFetchTable);
e1f7de0c 9160
b9af4937 9161 /* initialize all reply queue entries to unused */
072b0518
SC		 9162 for (i = 0; i < h->nreply_queues; i++)
9163 memset(h->reply_queue[i].head,
9164 (u8) IOACCEL_MODE1_REPLY_UNUSED,
9165 h->reply_queue_size);
e1f7de0c 9166
b9af4937
SC		 9167 /* set all the constant fields in the accelerator command
9168 * frames once at init time to save CPU cycles later.
9169 */
9170 for (i = 0; i < h->nr_cmds; i++) {
9171 struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
9172
9173 cp->function = IOACCEL1_FUNCTION_SCSIIO;
9174 cp->err_info = (u32) (h->errinfo_pool_dhandle +
9175 (i * sizeof(struct ErrorInfo)));
9176 cp->err_info_len = sizeof(struct ErrorInfo);
9177 cp->sgl_offset = IOACCEL1_SGLOFFSET;
2b08b3e9
DB		 9178 cp->host_context_flags =
9179 cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
b9af4937
SC		 9180 cp->timeout_sec = 0;
9181 cp->ReplyQueue = 0;
50a0decf 9182 cp->tag =
f2405db8 9183 cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
50a0decf
SC		 9184 cp->host_addr =
9185 cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
b9af4937 9186 (i * sizeof(struct io_accel1_cmd)));
b9af4937
SC		 9187 }
9188 } else if (trans_support & CFGTBL_Trans_io_accel2) {
9189 u64 cfg_offset, cfg_base_addr_index;
9190 u32 bft2_offset, cfg_base_addr;
9191 int rc;
9192
9193 rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
9194 &cfg_base_addr_index, &cfg_offset);
9195 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
9196 bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
9197 calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
9198 4, h->ioaccel2_blockFetchTable);
9199 bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
9200 BUILD_BUG_ON(offsetof(struct CfgTable,
9201 io_accel_request_size_offset) != 0xb8);
9202 h->ioaccel2_bft2_regs =
9203 remap_pci_mem(pci_resource_start(h->pdev,
9204 cfg_base_addr_index) +
9205 cfg_offset + bft2_offset,
9206 ARRAY_SIZE(bft2) *
9207 sizeof(*h->ioaccel2_bft2_regs));
9208 for (i = 0; i < ARRAY_SIZE(bft2); i++)
9209 writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
e1f7de0c 9210 }
b9af4937 9211 writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
c706a795
RE		 9212 if (hpsa_wait_for_mode_change_ack(h)) {
9213 dev_err(&h->pdev->dev,
9214 "performant mode problem - enabling ioaccel mode\n");
9215 return -ENODEV;
9216 }
9217 return 0;
e1f7de0c
MG		 9218}
9219
1fb7c98a
RE		 9220/* Free ioaccel1 mode command blocks and block fetch table */
9221static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
9222{
105a3dbc 9223 if (h->ioaccel_cmd_pool) {
1fb7c98a
RE		 9224 pci_free_consistent(h->pdev,
9225 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
9226 h->ioaccel_cmd_pool,
9227 h->ioaccel_cmd_pool_dhandle);
105a3dbc
RE		 9228 h->ioaccel_cmd_pool = NULL;
9229 h->ioaccel_cmd_pool_dhandle = 0;
9230 }
1fb7c98a 9231 kfree(h->ioaccel1_blockFetchTable);
105a3dbc 9232 h->ioaccel1_blockFetchTable = NULL;
1fb7c98a
RE		 9233}
9234
d37ffbe4
RE		 9235/* Allocate ioaccel1 mode command blocks and block fetch table */
9236static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
e1f7de0c 9237{
283b4a9b
SC		 9238 h->ioaccel_maxsg =
9239 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
9240 if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
9241 h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
9242
e1f7de0c
MG		 9243 /* Command structures must be aligned on a 128-byte boundary
9244 * because the 7 lower bits of the address are used by the
9245 * hardware.
9246 */
e1f7de0c
MG		 9247 BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
9248 IOACCEL1_COMMANDLIST_ALIGNMENT);
9249 h->ioaccel_cmd_pool =
8bc8f47e 9250 dma_alloc_coherent(&h->pdev->dev,
e1f7de0c 9251 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
8bc8f47e 9252 &h->ioaccel_cmd_pool_dhandle, GFP_KERNEL);
e1f7de0c
MG		 9253
9254 h->ioaccel1_blockFetchTable =
283b4a9b 9255 kmalloc(((h->ioaccel_maxsg + 1) *
e1f7de0c
MG		 9256 sizeof(u32)), GFP_KERNEL);
9257
9258 if ((h->ioaccel_cmd_pool == NULL) ||
9259 (h->ioaccel1_blockFetchTable == NULL))
9260 goto clean_up;
9261
9262 memset(h->ioaccel_cmd_pool, 0,
9263 h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
9264 return 0;
9265
9266clean_up:
1fb7c98a 9267 hpsa_free_ioaccel1_cmd_and_bft(h);
2dd02d74 9268 return -ENOMEM;
6c311b57
SC		 9269}
9270
1fb7c98a
RE		 9271/* Free ioaccel2 mode command blocks and block fetch table */
9272static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
9273{
d9a729f3
WS		 9274 hpsa_free_ioaccel2_sg_chain_blocks(h);
9275
105a3dbc 9276 if (h->ioaccel2_cmd_pool) {
1fb7c98a
RE		 9277 pci_free_consistent(h->pdev,
9278 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
9279 h->ioaccel2_cmd_pool,
9280 h->ioaccel2_cmd_pool_dhandle);
105a3dbc
RE		 9281 h->ioaccel2_cmd_pool = NULL;
9282 h->ioaccel2_cmd_pool_dhandle = 0;
9283 }
1fb7c98a 9284 kfree(h->ioaccel2_blockFetchTable);
105a3dbc 9285 h->ioaccel2_blockFetchTable = NULL;
1fb7c98a
RE		 9286}
9287
d37ffbe4
RE		 9288/* Allocate ioaccel2 mode command blocks and block fetch table */
9289static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
aca9012a 9290{
d9a729f3
WS		 9291 int rc;
9292
aca9012a
SC		 9293 /* Allocate ioaccel2 mode command blocks and block fetch table */
9294
9295 h->ioaccel_maxsg =
9296 readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
9297 if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
9298 h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
9299
aca9012a
SC		 9300 BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
9301 IOACCEL2_COMMANDLIST_ALIGNMENT);
9302 h->ioaccel2_cmd_pool =
8bc8f47e 9303 dma_alloc_coherent(&h->pdev->dev,
aca9012a 9304 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
8bc8f47e 9305 &h->ioaccel2_cmd_pool_dhandle, GFP_KERNEL);
aca9012a
SC		 9306
9307 h->ioaccel2_blockFetchTable =
9308 kmalloc(((h->ioaccel_maxsg + 1) *
9309 sizeof(u32)), GFP_KERNEL);
9310
9311 if ((h->ioaccel2_cmd_pool == NULL) ||
d9a729f3
WS		 9312 (h->ioaccel2_blockFetchTable == NULL)) {
9313 rc = -ENOMEM;
9314 goto clean_up;
9315 }
9316
9317 rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
9318 if (rc)
aca9012a
SC		 9319 goto clean_up;
9320
9321 memset(h->ioaccel2_cmd_pool, 0,
9322 h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
9323 return 0;
9324
9325clean_up:
1fb7c98a 9326 hpsa_free_ioaccel2_cmd_and_bft(h);
d9a729f3 9327 return rc;
aca9012a
SC		 9328}
9329
105a3dbc
RE		 9330/* Free items allocated by hpsa_put_ctlr_into_performant_mode */
9331static void hpsa_free_performant_mode(struct ctlr_info *h)
9332{
9333 kfree(h->blockFetchTable);
9334 h->blockFetchTable = NULL;
9335 hpsa_free_reply_queues(h);
9336 hpsa_free_ioaccel1_cmd_and_bft(h);
9337 hpsa_free_ioaccel2_cmd_and_bft(h);
9338}
9339
9340/* return -ENODEV on error, 0 on success (or no action)
9341 * allocates numerous items that must be freed later
9342 */
9343static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
6c311b57
SC		 9344{
9345 u32 trans_support;
e1f7de0c
MG		 9346 unsigned long transMethod = CFGTBL_Trans_Performant |
9347 CFGTBL_Trans_use_short_tags;
105a3dbc 9348 int i, rc;
6c311b57 9349
02ec19c8 9350 if (hpsa_simple_mode)
105a3dbc 9351 return 0;
02ec19c8 9352
67c99a72 9353 trans_support = readl(&(h->cfgtable->TransportSupport));
9354 if (!(trans_support & PERFORMANT_MODE))
105a3dbc 9355 return 0;
67c99a72 9356
e1f7de0c
MG		 9357 /* Check for I/O accelerator mode support */
9358 if (trans_support & CFGTBL_Trans_io_accel1) {
9359 transMethod |= CFGTBL_Trans_io_accel1 |
9360 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 9361 rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
9362 if (rc)
9363 return rc;
9364 } else if (trans_support & CFGTBL_Trans_io_accel2) {
9365 transMethod |= CFGTBL_Trans_io_accel2 |
aca9012a 9366 CFGTBL_Trans_enable_directed_msix;
105a3dbc
RE		 9367 rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
9368 if (rc)
9369 return rc;
e1f7de0c
MG		 9370 }
9371
bc2bb154 9372 h->nreply_queues = h->msix_vectors > 0 ? h->msix_vectors : 1;
cba3d38b 9373 hpsa_get_max_perf_mode_cmds(h);
6c311b57 9374 /* Performant mode ring buffer and supporting data structures */
072b0518 9375 h->reply_queue_size = h->max_commands * sizeof(u64);
6c311b57 9376
254f796b 9377 for (i = 0; i < h->nreply_queues; i++) {
8bc8f47e 9378 h->reply_queue[i].head = dma_alloc_coherent(&h->pdev->dev,
072b0518 9379 h->reply_queue_size,
8bc8f47e
CH		 9380 &h->reply_queue[i].busaddr,
9381 GFP_KERNEL);
105a3dbc
RE		 9382 if (!h->reply_queue[i].head) {
9383 rc = -ENOMEM;
9384 goto clean1; /* rq, ioaccel */
9385 }
254f796b
MG		 9386 h->reply_queue[i].size = h->max_commands;
9387 h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
9388 h->reply_queue[i].current_entry = 0;
9389 }
9390
6c311b57 9391 /* Need a block fetch table for performant mode */
d66ae08b 9392 h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
6c311b57 9393 sizeof(u32)), GFP_KERNEL);
105a3dbc
RE		 9394 if (!h->blockFetchTable) {
9395 rc = -ENOMEM;
9396 goto clean1; /* rq, ioaccel */
9397 }
6c311b57 9398
105a3dbc
RE		 9399 rc = hpsa_enter_performant_mode(h, trans_support);
9400 if (rc)
9401 goto clean2; /* bft, rq, ioaccel */
9402 return 0;
303932fd 9403
105a3dbc 9404clean2: /* bft, rq, ioaccel */
303932fd 9405 kfree(h->blockFetchTable);
105a3dbc
RE		 9406 h->blockFetchTable = NULL;
9407clean1: /* rq, ioaccel */
9408 hpsa_free_reply_queues(h);
9409 hpsa_free_ioaccel1_cmd_and_bft(h);
9410 hpsa_free_ioaccel2_cmd_and_bft(h);
9411 return rc;
303932fd
DB		 9412}
9413
23100dd9 9414static int is_accelerated_cmd(struct CommandList *c)
76438d08 9415{
23100dd9
SC		 9416 return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
9417}
9418
9419static void hpsa_drain_accel_commands(struct ctlr_info *h)
9420{
9421 struct CommandList *c = NULL;
f2405db8 9422 int i, accel_cmds_out;
281a7fd0 9423 int refcount;
76438d08 9424
f2405db8 9425 do { /* wait for all outstanding ioaccel commands to drain out */
23100dd9 9426 accel_cmds_out = 0;
f2405db8 9427 for (i = 0; i < h->nr_cmds; i++) {
f2405db8 9428 c = h->cmd_pool + i;
281a7fd0
WS		 9429 refcount = atomic_inc_return(&c->refcount);
9430 if (refcount > 1) /* Command is allocated */
9431 accel_cmds_out += is_accelerated_cmd(c);
9432 cmd_free(h, c);
f2405db8 9433 }
23100dd9 9434 if (accel_cmds_out <= 0)
281a7fd0 9435 break;
76438d08
SC		 9436 msleep(100);
9437 } while (1);
9438}
9439
d04e62b9
KB		 9440static struct hpsa_sas_phy *hpsa_alloc_sas_phy(
9441 struct hpsa_sas_port *hpsa_sas_port)
9442{
9443 struct hpsa_sas_phy *hpsa_sas_phy;
9444 struct sas_phy *phy;
9445
9446 hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL);
9447 if (!hpsa_sas_phy)
9448 return NULL;
9449
9450 phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev,
9451 hpsa_sas_port->next_phy_index);
9452 if (!phy) {
9453 kfree(hpsa_sas_phy);
9454 return NULL;
9455 }
9456
9457 hpsa_sas_port->next_phy_index++;
9458 hpsa_sas_phy->phy = phy;
9459 hpsa_sas_phy->parent_port = hpsa_sas_port;
9460
9461 return hpsa_sas_phy;
9462}
9463
9464static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy)
9465{
9466 struct sas_phy *phy = hpsa_sas_phy->phy;
9467
9468 sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy);
d04e62b9
KB		 9469 if (hpsa_sas_phy->added_to_port)
9470 list_del(&hpsa_sas_phy->phy_list_entry);
55ca38b4 9471 sas_phy_delete(phy);
d04e62b9
KB		 9472 kfree(hpsa_sas_phy);
9473}
9474
9475static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy)
9476{
9477 int rc;
9478 struct hpsa_sas_port *hpsa_sas_port;
9479 struct sas_phy *phy;
9480 struct sas_identify *identify;
9481
9482 hpsa_sas_port = hpsa_sas_phy->parent_port;
9483 phy = hpsa_sas_phy->phy;
9484
9485 identify = &phy->identify;
9486 memset(identify, 0, sizeof(*identify));
9487 identify->sas_address = hpsa_sas_port->sas_address;
9488 identify->device_type = SAS_END_DEVICE;
9489 identify->initiator_port_protocols = SAS_PROTOCOL_STP;
9490 identify->target_port_protocols = SAS_PROTOCOL_STP;
9491 phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
9492 phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
9493 phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN;
9494 phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN;
9495 phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN;
9496
9497 rc = sas_phy_add(hpsa_sas_phy->phy);
9498 if (rc)
9499 return rc;
9500
9501 sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy);
9502 list_add_tail(&hpsa_sas_phy->phy_list_entry,
9503 &hpsa_sas_port->phy_list_head);
9504 hpsa_sas_phy->added_to_port = true;
9505
9506 return 0;
9507}
9508
9509static int
9510 hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port,
9511 struct sas_rphy *rphy)
9512{
9513 struct sas_identify *identify;
9514
9515 identify = &rphy->identify;
9516 identify->sas_address = hpsa_sas_port->sas_address;
9517 identify->initiator_port_protocols = SAS_PROTOCOL_STP;
9518 identify->target_port_protocols = SAS_PROTOCOL_STP;
9519
9520 return sas_rphy_add(rphy);
9521}
9522
9523static struct hpsa_sas_port
9524 *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node,
9525 u64 sas_address)
9526{
9527 int rc;
9528 struct hpsa_sas_port *hpsa_sas_port;
9529 struct sas_port *port;
9530
9531 hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL);
9532 if (!hpsa_sas_port)
9533 return NULL;
9534
9535 INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head);
9536 hpsa_sas_port->parent_node = hpsa_sas_node;
9537
9538 port = sas_port_alloc_num(hpsa_sas_node->parent_dev);
9539 if (!port)
9540 goto free_hpsa_port;
9541
9542 rc = sas_port_add(port);
9543 if (rc)
9544 goto free_sas_port;
9545
9546 hpsa_sas_port->port = port;
9547 hpsa_sas_port->sas_address = sas_address;
9548 list_add_tail(&hpsa_sas_port->port_list_entry,
9549 &hpsa_sas_node->port_list_head);
9550
9551 return hpsa_sas_port;
9552
9553free_sas_port:
9554 sas_port_free(port);
9555free_hpsa_port:
9556 kfree(hpsa_sas_port);
9557
9558 return NULL;
9559}
9560
9561static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port)
9562{
9563 struct hpsa_sas_phy *hpsa_sas_phy;
9564 struct hpsa_sas_phy *next;
9565
9566 list_for_each_entry_safe(hpsa_sas_phy, next,
9567 &hpsa_sas_port->phy_list_head, phy_list_entry)
9568 hpsa_free_sas_phy(hpsa_sas_phy);
9569
9570 sas_port_delete(hpsa_sas_port->port);
9571 list_del(&hpsa_sas_port->port_list_entry);
9572 kfree(hpsa_sas_port);
9573}
9574
9575static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev)
9576{
9577 struct hpsa_sas_node *hpsa_sas_node;
9578
9579 hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL);
9580 if (hpsa_sas_node) {
9581 hpsa_sas_node->parent_dev = parent_dev;
9582 INIT_LIST_HEAD(&hpsa_sas_node->port_list_head);
9583 }
9584
9585 return hpsa_sas_node;
9586}
9587
9588static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node)
9589{
9590 struct hpsa_sas_port *hpsa_sas_port;
9591 struct hpsa_sas_port *next;
9592
9593 if (!hpsa_sas_node)
9594 return;
9595
9596 list_for_each_entry_safe(hpsa_sas_port, next,
9597 &hpsa_sas_node->port_list_head, port_list_entry)
9598 hpsa_free_sas_port(hpsa_sas_port);
9599
9600 kfree(hpsa_sas_node);
9601}
9602
9603static struct hpsa_scsi_dev_t
9604 *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
9605 struct sas_rphy *rphy)
9606{
9607 int i;
9608 struct hpsa_scsi_dev_t *device;
9609
9610 for (i = 0; i < h->ndevices; i++) {
9611 device = h->dev[i];
9612 if (!device->sas_port)
9613 continue;
9614 if (device->sas_port->rphy == rphy)
9615 return device;
9616 }
9617
9618 return NULL;
9619}
9620
9621static int hpsa_add_sas_host(struct ctlr_info *h)
9622{
9623 int rc;
9624 struct device *parent_dev;
9625 struct hpsa_sas_node *hpsa_sas_node;
9626 struct hpsa_sas_port *hpsa_sas_port;
9627 struct hpsa_sas_phy *hpsa_sas_phy;
9628
0a7c3bb8 9629 parent_dev = &h->scsi_host->shost_dev;
d04e62b9
KB		 9630
9631 hpsa_sas_node = hpsa_alloc_sas_node(parent_dev);
9632 if (!hpsa_sas_node)
9633 return -ENOMEM;
9634
9635 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address);
9636 if (!hpsa_sas_port) {
9637 rc = -ENODEV;
9638 goto free_sas_node;
9639 }
9640
9641 hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port);
9642 if (!hpsa_sas_phy) {
9643 rc = -ENODEV;
9644 goto free_sas_port;
9645 }
9646
9647 rc = hpsa_sas_port_add_phy(hpsa_sas_phy);
9648 if (rc)
9649 goto free_sas_phy;
9650
9651 h->sas_host = hpsa_sas_node;
9652
9653 return 0;
9654
9655free_sas_phy:
9656 hpsa_free_sas_phy(hpsa_sas_phy);
9657free_sas_port:
9658 hpsa_free_sas_port(hpsa_sas_port);
9659free_sas_node:
9660 hpsa_free_sas_node(hpsa_sas_node);
9661
9662 return rc;
9663}
9664
9665static void hpsa_delete_sas_host(struct ctlr_info *h)
9666{
9667 hpsa_free_sas_node(h->sas_host);
9668}
9669
9670static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
9671 struct hpsa_scsi_dev_t *device)
9672{
9673 int rc;
9674 struct hpsa_sas_port *hpsa_sas_port;
9675 struct sas_rphy *rphy;
9676
9677 hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address);
9678 if (!hpsa_sas_port)
9679 return -ENOMEM;
9680
9681 rphy = sas_end_device_alloc(hpsa_sas_port->port);
9682 if (!rphy) {
9683 rc = -ENODEV;
9684 goto free_sas_port;
9685 }
9686
9687 hpsa_sas_port->rphy = rphy;
9688 device->sas_port = hpsa_sas_port;
9689
9690 rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy);
9691 if (rc)
9692 goto free_sas_port;
9693
9694 return 0;
9695
9696free_sas_port:
9697 hpsa_free_sas_port(hpsa_sas_port);
9698 device->sas_port = NULL;
9699
9700 return rc;
9701}
9702
9703static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device)
9704{
9705 if (device->sas_port) {
9706 hpsa_free_sas_port(device->sas_port);
9707 device->sas_port = NULL;
9708 }
9709}
9710
9711static int
9712hpsa_sas_get_linkerrors(struct sas_phy *phy)
9713{
9714 return 0;
9715}
9716
9717static int
9718hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier)
9719{
01d0e789
DB		 9720 struct Scsi_Host *shost = phy_to_shost(rphy);
9721 struct ctlr_info *h;
9722 struct hpsa_scsi_dev_t *sd;
9723
9724 if (!shost)
9725 return -ENXIO;
9726
9727 h = shost_to_hba(shost);
9728
9729 if (!h)
9730 return -ENXIO;
9731
9732 sd = hpsa_find_device_by_sas_rphy(h, rphy);
9733 if (!sd)
9734 return -ENXIO;
9735
9736 *identifier = sd->eli;
9737
d04e62b9
KB		 9738 return 0;
9739}
9740
9741static int
9742hpsa_sas_get_bay_identifier(struct sas_rphy *rphy)
9743{
9744 return -ENXIO;
9745}
9746
9747static int
9748hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset)
9749{
9750 return 0;
9751}
9752
9753static int
9754hpsa_sas_phy_enable(struct sas_phy *phy, int enable)
9755{
9756 return 0;
9757}
9758
9759static int
9760hpsa_sas_phy_setup(struct sas_phy *phy)
9761{
9762 return 0;
9763}
9764
9765static void
9766hpsa_sas_phy_release(struct sas_phy *phy)
9767{
9768}
9769
9770static int
9771hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates)
9772{
9773 return -EINVAL;
9774}
9775
d04e62b9
KB		 9776static struct sas_function_template hpsa_sas_transport_functions = {
9777 .get_linkerrors = hpsa_sas_get_linkerrors,
9778 .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier,
9779 .get_bay_identifier = hpsa_sas_get_bay_identifier,
9780 .phy_reset = hpsa_sas_phy_reset,
9781 .phy_enable = hpsa_sas_phy_enable,
9782 .phy_setup = hpsa_sas_phy_setup,
9783 .phy_release = hpsa_sas_phy_release,
9784 .set_phy_speed = hpsa_sas_phy_speed,
d04e62b9
KB		 9785};
9786
edd16368
SC		 9787/*
9788 * This is it. Register the PCI driver information for the cards we control
9789 * the OS will call our registered routines when it finds one of our cards.
9790 */
9791static int __init hpsa_init(void)
9792{
d04e62b9
KB		 9793 int rc;
9794
9795 hpsa_sas_transport_template =
9796 sas_attach_transport(&hpsa_sas_transport_functions);
9797 if (!hpsa_sas_transport_template)
9798 return -ENODEV;
9799
9800 rc = pci_register_driver(&hpsa_pci_driver);
9801
9802 if (rc)
9803 sas_release_transport(hpsa_sas_transport_template);
9804
9805 return rc;
edd16368
SC		 9806}
9807
9808static void __exit hpsa_cleanup(void)
9809{
9810 pci_unregister_driver(&hpsa_pci_driver);
d04e62b9 9811 sas_release_transport(hpsa_sas_transport_template);
edd16368
SC		 9812}
9813
e1f7de0c
MG		 9814static void __attribute__((unused)) verify_offsets(void)
9815{
dd0e19f3
ST		 9816#define VERIFY_OFFSET(member, offset) \
9817 BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
9818
9819 VERIFY_OFFSET(structure_size, 0);
9820 VERIFY_OFFSET(volume_blk_size, 4);
9821 VERIFY_OFFSET(volume_blk_cnt, 8);
9822 VERIFY_OFFSET(phys_blk_shift, 16);
9823 VERIFY_OFFSET(parity_rotation_shift, 17);
9824 VERIFY_OFFSET(strip_size, 18);
9825 VERIFY_OFFSET(disk_starting_blk, 20);
9826 VERIFY_OFFSET(disk_blk_cnt, 28);
9827 VERIFY_OFFSET(data_disks_per_row, 36);
9828 VERIFY_OFFSET(metadata_disks_per_row, 38);
9829 VERIFY_OFFSET(row_cnt, 40);
9830 VERIFY_OFFSET(layout_map_count, 42);
9831 VERIFY_OFFSET(flags, 44);
9832 VERIFY_OFFSET(dekindex, 46);
9833 /* VERIFY_OFFSET(reserved, 48 */
9834 VERIFY_OFFSET(data, 64);
9835
9836#undef VERIFY_OFFSET
9837
b66cc250
MM		 9838#define VERIFY_OFFSET(member, offset) \
9839 BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
9840
9841 VERIFY_OFFSET(IU_type, 0);
9842 VERIFY_OFFSET(direction, 1);
9843 VERIFY_OFFSET(reply_queue, 2);
9844 /* VERIFY_OFFSET(reserved1, 3); */
9845 VERIFY_OFFSET(scsi_nexus, 4);
9846 VERIFY_OFFSET(Tag, 8);
9847 VERIFY_OFFSET(cdb, 16);
9848 VERIFY_OFFSET(cciss_lun, 32);
9849 VERIFY_OFFSET(data_len, 40);
9850 VERIFY_OFFSET(cmd_priority_task_attr, 44);
9851 VERIFY_OFFSET(sg_count, 45);
9852 /* VERIFY_OFFSET(reserved3 */
9853 VERIFY_OFFSET(err_ptr, 48);
9854 VERIFY_OFFSET(err_len, 56);
9855 /* VERIFY_OFFSET(reserved4 */
9856 VERIFY_OFFSET(sg, 64);
9857
9858#undef VERIFY_OFFSET
9859
e1f7de0c
MG		 9860#define VERIFY_OFFSET(member, offset) \
9861 BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
9862
9863 VERIFY_OFFSET(dev_handle, 0x00);
9864 VERIFY_OFFSET(reserved1, 0x02);
9865 VERIFY_OFFSET(function, 0x03);
9866 VERIFY_OFFSET(reserved2, 0x04);
9867 VERIFY_OFFSET(err_info, 0x0C);
9868 VERIFY_OFFSET(reserved3, 0x10);
9869 VERIFY_OFFSET(err_info_len, 0x12);
9870 VERIFY_OFFSET(reserved4, 0x13);
9871 VERIFY_OFFSET(sgl_offset, 0x14);
9872 VERIFY_OFFSET(reserved5, 0x15);
9873 VERIFY_OFFSET(transfer_len, 0x1C);
9874 VERIFY_OFFSET(reserved6, 0x20);
9875 VERIFY_OFFSET(io_flags, 0x24);
9876 VERIFY_OFFSET(reserved7, 0x26);
9877 VERIFY_OFFSET(LUN, 0x34);
9878 VERIFY_OFFSET(control, 0x3C);
9879 VERIFY_OFFSET(CDB, 0x40);
9880 VERIFY_OFFSET(reserved8, 0x50);
9881 VERIFY_OFFSET(host_context_flags, 0x60);
9882 VERIFY_OFFSET(timeout_sec, 0x62);
9883 VERIFY_OFFSET(ReplyQueue, 0x64);
9884 VERIFY_OFFSET(reserved9, 0x65);
50a0decf 9885 VERIFY_OFFSET(tag, 0x68);
e1f7de0c
MG		 9886 VERIFY_OFFSET(host_addr, 0x70);
9887 VERIFY_OFFSET(CISS_LUN, 0x78);
9888 VERIFY_OFFSET(SG, 0x78 + 8);
9889#undef VERIFY_OFFSET
9890}
9891
edd16368
SC		 9892module_init(hpsa_init);
9893module_exit(hpsa_cleanup);
Linux 6.x block layer and io_uring tree(s)