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hisi_sas: add v2 int init and phy up handler
[linux-2.6-block.git] / drivers / scsi / hisi_sas / hisi_sas_v2_hw.c
CommitLineData
3417ba8a
JG		 1/*
2 * Copyright (c) 2016 Linaro Ltd.
3 * Copyright (c) 2016 Hisilicon Limited.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License as published by
7 * the Free Software Foundation; either version 2 of the License, or
8 * (at your option) any later version.
9 *
10 */
11
12#include "hisi_sas.h"
13#define DRV_NAME "hisi_sas_v2_hw"
14
45c901b8
JG		 15/* global registers need init*/
16#define DLVRY_QUEUE_ENABLE 0x0
17#define IOST_BASE_ADDR_LO 0x8
18#define IOST_BASE_ADDR_HI 0xc
19#define ITCT_BASE_ADDR_LO 0x10
20#define ITCT_BASE_ADDR_HI 0x14
21#define IO_BROKEN_MSG_ADDR_LO 0x18
22#define IO_BROKEN_MSG_ADDR_HI 0x1c
23#define PHY_CONTEXT 0x20
24#define PHY_STATE 0x24
25#define PHY_PORT_NUM_MA 0x28
26#define PORT_STATE 0x2c
27#define PORT_STATE_PHY8_PORT_NUM_OFF 16
28#define PORT_STATE_PHY8_PORT_NUM_MSK (0xf << PORT_STATE_PHY8_PORT_NUM_OFF)
29#define PORT_STATE_PHY8_CONN_RATE_OFF 20
30#define PORT_STATE_PHY8_CONN_RATE_MSK (0xf << PORT_STATE_PHY8_CONN_RATE_OFF)
31#define PHY_CONN_RATE 0x30
32#define HGC_TRANS_TASK_CNT_LIMIT 0x38
33#define AXI_AHB_CLK_CFG 0x3c
34#define ITCT_CLR 0x44
35#define ITCT_CLR_EN_OFF 16
36#define ITCT_CLR_EN_MSK (0x1 << ITCT_CLR_EN_OFF)
37#define ITCT_DEV_OFF 0
38#define ITCT_DEV_MSK (0x7ff << ITCT_DEV_OFF)
39#define AXI_USER1 0x48
40#define AXI_USER2 0x4c
41#define IO_SATA_BROKEN_MSG_ADDR_LO 0x58
42#define IO_SATA_BROKEN_MSG_ADDR_HI 0x5c
43#define SATA_INITI_D2H_STORE_ADDR_LO 0x60
44#define SATA_INITI_D2H_STORE_ADDR_HI 0x64
45#define HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL 0x84
46#define HGC_SAS_TXFAIL_RETRY_CTRL 0x88
47#define HGC_GET_ITV_TIME 0x90
48#define DEVICE_MSG_WORK_MODE 0x94
49#define OPENA_WT_CONTI_TIME 0x9c
50#define I_T_NEXUS_LOSS_TIME 0xa0
51#define MAX_CON_TIME_LIMIT_TIME 0xa4
52#define BUS_INACTIVE_LIMIT_TIME 0xa8
53#define REJECT_TO_OPEN_LIMIT_TIME 0xac
54#define CFG_AGING_TIME 0xbc
55#define HGC_DFX_CFG2 0xc0
56#define HGC_IOMB_PROC1_STATUS 0x104
57#define CFG_1US_TIMER_TRSH 0xcc
58#define HGC_INVLD_DQE_INFO 0x148
59#define HGC_INVLD_DQE_INFO_FB_CH0_OFF 9
60#define HGC_INVLD_DQE_INFO_FB_CH0_MSK (0x1 << HGC_INVLD_DQE_INFO_FB_CH0_OFF)
61#define HGC_INVLD_DQE_INFO_FB_CH3_OFF 18
62#define INT_COAL_EN 0x19c
63#define OQ_INT_COAL_TIME 0x1a0
64#define OQ_INT_COAL_CNT 0x1a4
65#define ENT_INT_COAL_TIME 0x1a8
66#define ENT_INT_COAL_CNT 0x1ac
67#define OQ_INT_SRC 0x1b0
68#define OQ_INT_SRC_MSK 0x1b4
69#define ENT_INT_SRC1 0x1b8
70#define ENT_INT_SRC1_D2H_FIS_CH0_OFF 0
71#define ENT_INT_SRC1_D2H_FIS_CH0_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH0_OFF)
72#define ENT_INT_SRC1_D2H_FIS_CH1_OFF 8
73#define ENT_INT_SRC1_D2H_FIS_CH1_MSK (0x1 << ENT_INT_SRC1_D2H_FIS_CH1_OFF)
74#define ENT_INT_SRC2 0x1bc
75#define ENT_INT_SRC3 0x1c0
76#define ENT_INT_SRC3_ITC_INT_OFF 15
77#define ENT_INT_SRC3_ITC_INT_MSK (0x1 << ENT_INT_SRC3_ITC_INT_OFF)
78#define ENT_INT_SRC_MSK1 0x1c4
79#define ENT_INT_SRC_MSK2 0x1c8
80#define ENT_INT_SRC_MSK3 0x1cc
81#define ENT_INT_SRC_MSK3_ENT95_MSK_OFF 31
82#define ENT_INT_SRC_MSK3_ENT95_MSK_MSK (0x1 << ENT_INT_SRC_MSK3_ENT95_MSK_OFF)
83#define SAS_ECC_INTR_MSK 0x1ec
84#define HGC_ERR_STAT_EN 0x238
85#define DLVRY_Q_0_BASE_ADDR_LO 0x260
86#define DLVRY_Q_0_BASE_ADDR_HI 0x264
87#define DLVRY_Q_0_DEPTH 0x268
88#define DLVRY_Q_0_WR_PTR 0x26c
89#define DLVRY_Q_0_RD_PTR 0x270
90#define HYPER_STREAM_ID_EN_CFG 0xc80
91#define OQ0_INT_SRC_MSK 0xc90
92#define COMPL_Q_0_BASE_ADDR_LO 0x4e0
93#define COMPL_Q_0_BASE_ADDR_HI 0x4e4
94#define COMPL_Q_0_DEPTH 0x4e8
95#define COMPL_Q_0_WR_PTR 0x4ec
96#define COMPL_Q_0_RD_PTR 0x4f0
97
98/* phy registers need init */
99#define PORT_BASE (0x2000)
100
101#define PHY_CFG (PORT_BASE + 0x0)
102#define HARD_PHY_LINKRATE (PORT_BASE + 0x4)
103#define PHY_CFG_ENA_OFF 0
104#define PHY_CFG_ENA_MSK (0x1 << PHY_CFG_ENA_OFF)
105#define PHY_CFG_DC_OPT_OFF 2
106#define PHY_CFG_DC_OPT_MSK (0x1 << PHY_CFG_DC_OPT_OFF)
107#define PROG_PHY_LINK_RATE (PORT_BASE + 0x8)
108#define PROG_PHY_LINK_RATE_MAX_OFF 0
109#define PROG_PHY_LINK_RATE_MAX_MSK (0xff << PROG_PHY_LINK_RATE_MAX_OFF)
110#define PHY_CTRL (PORT_BASE + 0x14)
111#define PHY_CTRL_RESET_OFF 0
112#define PHY_CTRL_RESET_MSK (0x1 << PHY_CTRL_RESET_OFF)
113#define SAS_PHY_CTRL (PORT_BASE + 0x20)
114#define SL_CFG (PORT_BASE + 0x84)
115#define PHY_PCN (PORT_BASE + 0x44)
116#define SL_TOUT_CFG (PORT_BASE + 0x8c)
117#define SL_CONTROL (PORT_BASE + 0x94)
118#define SL_CONTROL_NOTIFY_EN_OFF 0
119#define SL_CONTROL_NOTIFY_EN_MSK (0x1 << SL_CONTROL_NOTIFY_EN_OFF)
120#define TX_ID_DWORD0 (PORT_BASE + 0x9c)
121#define TX_ID_DWORD1 (PORT_BASE + 0xa0)
122#define TX_ID_DWORD2 (PORT_BASE + 0xa4)
123#define TX_ID_DWORD3 (PORT_BASE + 0xa8)
124#define TX_ID_DWORD4 (PORT_BASE + 0xaC)
125#define TX_ID_DWORD5 (PORT_BASE + 0xb0)
126#define TX_ID_DWORD6 (PORT_BASE + 0xb4)
127#define RX_IDAF_DWORD0 (PORT_BASE + 0xc4)
128#define RX_IDAF_DWORD1 (PORT_BASE + 0xc8)
129#define RX_IDAF_DWORD2 (PORT_BASE + 0xcc)
130#define RX_IDAF_DWORD3 (PORT_BASE + 0xd0)
131#define RX_IDAF_DWORD4 (PORT_BASE + 0xd4)
132#define RX_IDAF_DWORD5 (PORT_BASE + 0xd8)
133#define RX_IDAF_DWORD6 (PORT_BASE + 0xdc)
134#define RXOP_CHECK_CFG_H (PORT_BASE + 0xfc)
135#define DONE_RECEIVED_TIME (PORT_BASE + 0x11c)
136#define CHL_INT0 (PORT_BASE + 0x1b4)
137#define CHL_INT0_HOTPLUG_TOUT_OFF 0
138#define CHL_INT0_HOTPLUG_TOUT_MSK (0x1 << CHL_INT0_HOTPLUG_TOUT_OFF)
139#define CHL_INT0_SL_RX_BCST_ACK_OFF 1
140#define CHL_INT0_SL_RX_BCST_ACK_MSK (0x1 << CHL_INT0_SL_RX_BCST_ACK_OFF)
141#define CHL_INT0_SL_PHY_ENABLE_OFF 2
142#define CHL_INT0_SL_PHY_ENABLE_MSK (0x1 << CHL_INT0_SL_PHY_ENABLE_OFF)
143#define CHL_INT0_NOT_RDY_OFF 4
144#define CHL_INT0_NOT_RDY_MSK (0x1 << CHL_INT0_NOT_RDY_OFF)
145#define CHL_INT0_PHY_RDY_OFF 5
146#define CHL_INT0_PHY_RDY_MSK (0x1 << CHL_INT0_PHY_RDY_OFF)
147#define CHL_INT1 (PORT_BASE + 0x1b8)
148#define CHL_INT1_DMAC_TX_ECC_ERR_OFF 15
149#define CHL_INT1_DMAC_TX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_TX_ECC_ERR_OFF)
150#define CHL_INT1_DMAC_RX_ECC_ERR_OFF 17
151#define CHL_INT1_DMAC_RX_ECC_ERR_MSK (0x1 << CHL_INT1_DMAC_RX_ECC_ERR_OFF)
152#define CHL_INT2 (PORT_BASE + 0x1bc)
153#define CHL_INT0_MSK (PORT_BASE + 0x1c0)
154#define CHL_INT1_MSK (PORT_BASE + 0x1c4)
155#define CHL_INT2_MSK (PORT_BASE + 0x1c8)
156#define CHL_INT_COAL_EN (PORT_BASE + 0x1d0)
157#define PHY_CTRL_RDY_MSK (PORT_BASE + 0x2b0)
158#define PHYCTRL_NOT_RDY_MSK (PORT_BASE + 0x2b4)
159#define PHYCTRL_DWS_RESET_MSK (PORT_BASE + 0x2b8)
160#define PHYCTRL_PHY_ENA_MSK (PORT_BASE + 0x2bc)
161#define SL_RX_BCAST_CHK_MSK (PORT_BASE + 0x2c0)
162#define PHYCTRL_OOB_RESTART_MSK (PORT_BASE + 0x2c4)
163#define DMA_TX_STATUS (PORT_BASE + 0x2d0)
164#define DMA_TX_STATUS_BUSY_OFF 0
165#define DMA_TX_STATUS_BUSY_MSK (0x1 << DMA_TX_STATUS_BUSY_OFF)
166#define DMA_RX_STATUS (PORT_BASE + 0x2e8)
167#define DMA_RX_STATUS_BUSY_OFF 0
168#define DMA_RX_STATUS_BUSY_MSK (0x1 << DMA_RX_STATUS_BUSY_OFF)
169
170#define AXI_CFG (0x5100)
171#define AM_CFG_MAX_TRANS (0x5010)
172#define AM_CFG_SINGLE_PORT_MAX_TRANS (0x5014)
173
174/* HW dma structures */
175/* Delivery queue header */
176/* dw0 */
177#define CMD_HDR_RESP_REPORT_OFF 5
178#define CMD_HDR_RESP_REPORT_MSK (0x1 << CMD_HDR_RESP_REPORT_OFF)
179#define CMD_HDR_TLR_CTRL_OFF 6
180#define CMD_HDR_TLR_CTRL_MSK (0x3 << CMD_HDR_TLR_CTRL_OFF)
181#define CMD_HDR_PORT_OFF 18
182#define CMD_HDR_PORT_MSK (0xf << CMD_HDR_PORT_OFF)
183#define CMD_HDR_PRIORITY_OFF 27
184#define CMD_HDR_PRIORITY_MSK (0x1 << CMD_HDR_PRIORITY_OFF)
185#define CMD_HDR_CMD_OFF 29
186#define CMD_HDR_CMD_MSK (0x7 << CMD_HDR_CMD_OFF)
187/* dw1 */
188#define CMD_HDR_DIR_OFF 5
189#define CMD_HDR_DIR_MSK (0x3 << CMD_HDR_DIR_OFF)
190#define CMD_HDR_RESET_OFF 7
191#define CMD_HDR_RESET_MSK (0x1 << CMD_HDR_RESET_OFF)
192#define CMD_HDR_VDTL_OFF 10
193#define CMD_HDR_VDTL_MSK (0x1 << CMD_HDR_VDTL_OFF)
194#define CMD_HDR_FRAME_TYPE_OFF 11
195#define CMD_HDR_FRAME_TYPE_MSK (0x1f << CMD_HDR_FRAME_TYPE_OFF)
196#define CMD_HDR_DEV_ID_OFF 16
197#define CMD_HDR_DEV_ID_MSK (0xffff << CMD_HDR_DEV_ID_OFF)
198/* dw2 */
199#define CMD_HDR_CFL_OFF 0
200#define CMD_HDR_CFL_MSK (0x1ff << CMD_HDR_CFL_OFF)
201#define CMD_HDR_NCQ_TAG_OFF 10
202#define CMD_HDR_NCQ_TAG_MSK (0x1f << CMD_HDR_NCQ_TAG_OFF)
203#define CMD_HDR_MRFL_OFF 15
204#define CMD_HDR_MRFL_MSK (0x1ff << CMD_HDR_MRFL_OFF)
205#define CMD_HDR_SG_MOD_OFF 24
206#define CMD_HDR_SG_MOD_MSK (0x3 << CMD_HDR_SG_MOD_OFF)
207#define CMD_HDR_FIRST_BURST_OFF 26
208#define CMD_HDR_FIRST_BURST_MSK (0x1 << CMD_HDR_SG_MOD_OFF)
209/* dw3 */
210#define CMD_HDR_IPTT_OFF 0
211#define CMD_HDR_IPTT_MSK (0xffff << CMD_HDR_IPTT_OFF)
212/* dw6 */
213#define CMD_HDR_DIF_SGL_LEN_OFF 0
214#define CMD_HDR_DIF_SGL_LEN_MSK (0xffff << CMD_HDR_DIF_SGL_LEN_OFF)
215#define CMD_HDR_DATA_SGL_LEN_OFF 16
216#define CMD_HDR_DATA_SGL_LEN_MSK (0xffff << CMD_HDR_DATA_SGL_LEN_OFF)
217
218/* Completion header */
219/* dw0 */
220#define CMPLT_HDR_RSPNS_XFRD_OFF 10
221#define CMPLT_HDR_RSPNS_XFRD_MSK (0x1 << CMPLT_HDR_RSPNS_XFRD_OFF)
222#define CMPLT_HDR_ERX_OFF 12
223#define CMPLT_HDR_ERX_MSK (0x1 << CMPLT_HDR_ERX_OFF)
224/* dw1 */
225#define CMPLT_HDR_IPTT_OFF 0
226#define CMPLT_HDR_IPTT_MSK (0xffff << CMPLT_HDR_IPTT_OFF)
227#define CMPLT_HDR_DEV_ID_OFF 16
228#define CMPLT_HDR_DEV_ID_MSK (0xffff << CMPLT_HDR_DEV_ID_OFF)
229
230/* ITCT header */
231/* qw0 */
232#define ITCT_HDR_DEV_TYPE_OFF 0
233#define ITCT_HDR_DEV_TYPE_MSK (0x3 << ITCT_HDR_DEV_TYPE_OFF)
234#define ITCT_HDR_VALID_OFF 2
235#define ITCT_HDR_VALID_MSK (0x1 << ITCT_HDR_VALID_OFF)
236#define ITCT_HDR_MCR_OFF 5
237#define ITCT_HDR_MCR_MSK (0xf << ITCT_HDR_MCR_OFF)
238#define ITCT_HDR_VLN_OFF 9
239#define ITCT_HDR_VLN_MSK (0xf << ITCT_HDR_VLN_OFF)
240#define ITCT_HDR_PORT_ID_OFF 28
241#define ITCT_HDR_PORT_ID_MSK (0xf << ITCT_HDR_PORT_ID_OFF)
242/* qw2 */
243#define ITCT_HDR_INLT_OFF 0
244#define ITCT_HDR_INLT_MSK (0xffffULL << ITCT_HDR_INLT_OFF)
245#define ITCT_HDR_BITLT_OFF 16
246#define ITCT_HDR_BITLT_MSK (0xffffULL << ITCT_HDR_BITLT_OFF)
247#define ITCT_HDR_MCTLT_OFF 32
248#define ITCT_HDR_MCTLT_MSK (0xffffULL << ITCT_HDR_MCTLT_OFF)
249#define ITCT_HDR_RTOLT_OFF 48
250#define ITCT_HDR_RTOLT_MSK (0xffffULL << ITCT_HDR_RTOLT_OFF)
251
94eac9e1
JG		 252struct hisi_sas_complete_v2_hdr {
253 __le32 dw0;
254 __le32 dw1;
255 __le32 act;
256 __le32 dw3;
257};
258
7911e66f
JG		 259enum {
260 HISI_SAS_PHY_PHY_UPDOWN,
261 HISI_SAS_PHY_INT_NR
262};
263
94eac9e1
JG		 264#define HISI_SAS_COMMAND_ENTRIES_V2_HW 4096
265
266static u32 hisi_sas_read32(struct hisi_hba *hisi_hba, u32 off)
267{
268 void __iomem *regs = hisi_hba->regs + off;
269
270 return readl(regs);
271}
272
273static void hisi_sas_write32(struct hisi_hba *hisi_hba, u32 off, u32 val)
274{
275 void __iomem *regs = hisi_hba->regs + off;
276
277 writel(val, regs);
278}
279
280static void hisi_sas_phy_write32(struct hisi_hba *hisi_hba, int phy_no,
281 u32 off, u32 val)
282{
283 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
284
285 writel(val, regs);
286}
287
288static u32 hisi_sas_phy_read32(struct hisi_hba *hisi_hba,
289 int phy_no, u32 off)
290{
291 void __iomem *regs = hisi_hba->regs + (0x400 * phy_no) + off;
292
293 return readl(regs);
294}
295
29a20428
JG		 296static void config_phy_opt_mode_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
297{
298 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
299
300 cfg &= ~PHY_CFG_DC_OPT_MSK;
301 cfg |= 1 << PHY_CFG_DC_OPT_OFF;
302 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
303}
304
806bb768
JG		 305static void config_id_frame_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
306{
307 struct sas_identify_frame identify_frame;
308 u32 *identify_buffer;
309
310 memset(&identify_frame, 0, sizeof(identify_frame));
311 identify_frame.dev_type = SAS_END_DEVICE;
312 identify_frame.frame_type = 0;
313 identify_frame._un1 = 1;
314 identify_frame.initiator_bits = SAS_PROTOCOL_ALL;
315 identify_frame.target_bits = SAS_PROTOCOL_NONE;
316 memcpy(&identify_frame._un4_11[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
317 memcpy(&identify_frame.sas_addr[0], hisi_hba->sas_addr, SAS_ADDR_SIZE);
318 identify_frame.phy_id = phy_no;
319 identify_buffer = (u32 *)(&identify_frame);
320
321 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD0,
322 __swab32(identify_buffer[0]));
323 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD1,
324 identify_buffer[2]);
325 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD2,
326 identify_buffer[1]);
327 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD3,
328 identify_buffer[4]);
329 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD4,
330 identify_buffer[3]);
331 hisi_sas_phy_write32(hisi_hba, phy_no, TX_ID_DWORD5,
332 __swab32(identify_buffer[5]));
333}
334
335static void init_id_frame_v2_hw(struct hisi_hba *hisi_hba)
336{
337 int i;
338
339 for (i = 0; i < hisi_hba->n_phy; i++)
340 config_id_frame_v2_hw(hisi_hba, i);
341}
342
94eac9e1
JG		 343static int reset_hw_v2_hw(struct hisi_hba *hisi_hba)
344{
345 int i, reset_val;
346 u32 val;
347 unsigned long end_time;
348 struct device *dev = &hisi_hba->pdev->dev;
349
350 /* The mask needs to be set depending on the number of phys */
351 if (hisi_hba->n_phy == 9)
352 reset_val = 0x1fffff;
353 else
354 reset_val = 0x7ffff;
355
356 /* Disable all of the DQ */
357 for (i = 0; i < HISI_SAS_MAX_QUEUES; i++)
358 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE, 0);
359
360 /* Disable all of the PHYs */
361 for (i = 0; i < hisi_hba->n_phy; i++) {
362 u32 phy_cfg = hisi_sas_phy_read32(hisi_hba, i, PHY_CFG);
363
364 phy_cfg &= ~PHY_CTRL_RESET_MSK;
365 hisi_sas_phy_write32(hisi_hba, i, PHY_CFG, phy_cfg);
366 }
367 udelay(50);
368
369 /* Ensure DMA tx & rx idle */
370 for (i = 0; i < hisi_hba->n_phy; i++) {
371 u32 dma_tx_status, dma_rx_status;
372
373 end_time = jiffies + msecs_to_jiffies(1000);
374
375 while (1) {
376 dma_tx_status = hisi_sas_phy_read32(hisi_hba, i,
377 DMA_TX_STATUS);
378 dma_rx_status = hisi_sas_phy_read32(hisi_hba, i,
379 DMA_RX_STATUS);
380
381 if (!(dma_tx_status & DMA_TX_STATUS_BUSY_MSK) &&
382 !(dma_rx_status & DMA_RX_STATUS_BUSY_MSK))
383 break;
384
385 msleep(20);
386 if (time_after(jiffies, end_time))
387 return -EIO;
388 }
389 }
390
391 /* Ensure axi bus idle */
392 end_time = jiffies + msecs_to_jiffies(1000);
393 while (1) {
394 u32 axi_status =
395 hisi_sas_read32(hisi_hba, AXI_CFG);
396
397 if (axi_status == 0)
398 break;
399
400 msleep(20);
401 if (time_after(jiffies, end_time))
402 return -EIO;
403 }
404
405 /* reset and disable clock*/
406 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg,
407 reset_val);
408 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg + 4,
409 reset_val);
410 msleep(1);
411 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg, &val);
412 if (reset_val != (val & reset_val)) {
413 dev_err(dev, "SAS reset fail.\n");
414 return -EIO;
415 }
416
417 /* De-reset and enable clock*/
418 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_reset_reg + 4,
419 reset_val);
420 regmap_write(hisi_hba->ctrl, hisi_hba->ctrl_clock_ena_reg,
421 reset_val);
422 msleep(1);
423 regmap_read(hisi_hba->ctrl, hisi_hba->ctrl_reset_sts_reg,
424 &val);
425 if (val & reset_val) {
426 dev_err(dev, "SAS de-reset fail.\n");
427 return -EIO;
428 }
429
430 return 0;
431}
432
433static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
434{
435 struct device *dev = &hisi_hba->pdev->dev;
436 struct device_node *np = dev->of_node;
437 int i;
438
439 /* Global registers init */
440
441 /* Deal with am-max-transmissions quirk */
442 if (of_get_property(np, "hip06-sas-v2-quirk-amt", NULL)) {
443 hisi_sas_write32(hisi_hba, AM_CFG_MAX_TRANS, 0x2020);
444 hisi_sas_write32(hisi_hba, AM_CFG_SINGLE_PORT_MAX_TRANS,
445 0x2020);
446 } /* Else, use defaults -> do nothing */
447
448 hisi_sas_write32(hisi_hba, DLVRY_QUEUE_ENABLE,
449 (u32)((1ULL << hisi_hba->queue_count) - 1));
450 hisi_sas_write32(hisi_hba, AXI_USER1, 0xc0000000);
451 hisi_sas_write32(hisi_hba, AXI_USER2, 0x10000);
452 hisi_sas_write32(hisi_hba, HGC_SAS_TXFAIL_RETRY_CTRL, 0x108);
453 hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
454 hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
455 hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
456 hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x4E20);
457 hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
458 hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
459 hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);
460 hisi_sas_write32(hisi_hba, HGC_GET_ITV_TIME, 0x1);
461 hisi_sas_write32(hisi_hba, INT_COAL_EN, 0x1);
462 hisi_sas_write32(hisi_hba, OQ_INT_COAL_TIME, 0x1);
463 hisi_sas_write32(hisi_hba, OQ_INT_COAL_CNT, 0x1);
464 hisi_sas_write32(hisi_hba, ENT_INT_COAL_TIME, 0x1);
465 hisi_sas_write32(hisi_hba, ENT_INT_COAL_CNT, 0x1);
466 hisi_sas_write32(hisi_hba, OQ_INT_SRC, 0x0);
467 hisi_sas_write32(hisi_hba, ENT_INT_SRC1, 0xffffffff);
468 hisi_sas_write32(hisi_hba, ENT_INT_SRC2, 0xffffffff);
469 hisi_sas_write32(hisi_hba, ENT_INT_SRC3, 0xffffffff);
470 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK1, 0x7efefefe);
471 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK2, 0x7efefefe);
472 hisi_sas_write32(hisi_hba, ENT_INT_SRC_MSK3, 0x7ffffffe);
473 hisi_sas_write32(hisi_hba, SAS_ECC_INTR_MSK, 0xfffff3c0);
474 for (i = 0; i < hisi_hba->queue_count; i++)
475 hisi_sas_write32(hisi_hba, OQ0_INT_SRC_MSK+0x4*i, 0);
476
477 hisi_sas_write32(hisi_hba, AXI_AHB_CLK_CFG, 1);
478 hisi_sas_write32(hisi_hba, HYPER_STREAM_ID_EN_CFG, 1);
479
480 for (i = 0; i < hisi_hba->n_phy; i++) {
481 hisi_sas_phy_write32(hisi_hba, i, PROG_PHY_LINK_RATE, 0x855);
482 hisi_sas_phy_write32(hisi_hba, i, SAS_PHY_CTRL, 0x30b9908);
483 hisi_sas_phy_write32(hisi_hba, i, SL_TOUT_CFG, 0x7d7d7d7d);
484 hisi_sas_phy_write32(hisi_hba, i, DONE_RECEIVED_TIME, 0x10);
485 hisi_sas_phy_write32(hisi_hba, i, CHL_INT0, 0xffffffff);
486 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1, 0xffffffff);
487 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2, 0xffffffff);
488 hisi_sas_phy_write32(hisi_hba, i, RXOP_CHECK_CFG_H, 0x1000);
489 hisi_sas_phy_write32(hisi_hba, i, CHL_INT1_MSK, 0xffffffff);
490 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x8ffffbff);
491 hisi_sas_phy_write32(hisi_hba, i, SL_CFG, 0x23f801fc);
492 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL_RDY_MSK, 0x0);
493 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_NOT_RDY_MSK, 0x0);
494 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_DWS_RESET_MSK, 0x0);
495 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_PHY_ENA_MSK, 0x0);
496 hisi_sas_phy_write32(hisi_hba, i, SL_RX_BCAST_CHK_MSK, 0x0);
497 hisi_sas_phy_write32(hisi_hba, i, CHL_INT_COAL_EN, 0x0);
498 hisi_sas_phy_write32(hisi_hba, i, PHYCTRL_OOB_RESTART_MSK, 0x0);
499 hisi_sas_phy_write32(hisi_hba, i, PHY_CTRL, 0x199B694);
500 }
501
502 for (i = 0; i < hisi_hba->queue_count; i++) {
503 /* Delivery queue */
504 hisi_sas_write32(hisi_hba,
505 DLVRY_Q_0_BASE_ADDR_HI + (i * 0x14),
506 upper_32_bits(hisi_hba->cmd_hdr_dma[i]));
507
508 hisi_sas_write32(hisi_hba, DLVRY_Q_0_BASE_ADDR_LO + (i * 0x14),
509 lower_32_bits(hisi_hba->cmd_hdr_dma[i]));
510
511 hisi_sas_write32(hisi_hba, DLVRY_Q_0_DEPTH + (i * 0x14),
512 HISI_SAS_QUEUE_SLOTS);
513
514 /* Completion queue */
515 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_HI + (i * 0x14),
516 upper_32_bits(hisi_hba->complete_hdr_dma[i]));
517
518 hisi_sas_write32(hisi_hba, COMPL_Q_0_BASE_ADDR_LO + (i * 0x14),
519 lower_32_bits(hisi_hba->complete_hdr_dma[i]));
520
521 hisi_sas_write32(hisi_hba, COMPL_Q_0_DEPTH + (i * 0x14),
522 HISI_SAS_QUEUE_SLOTS);
523 }
524
525 /* itct */
526 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_LO,
527 lower_32_bits(hisi_hba->itct_dma));
528
529 hisi_sas_write32(hisi_hba, ITCT_BASE_ADDR_HI,
530 upper_32_bits(hisi_hba->itct_dma));
531
532 /* iost */
533 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_LO,
534 lower_32_bits(hisi_hba->iost_dma));
535
536 hisi_sas_write32(hisi_hba, IOST_BASE_ADDR_HI,
537 upper_32_bits(hisi_hba->iost_dma));
538
539 /* breakpoint */
540 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_LO,
541 lower_32_bits(hisi_hba->breakpoint_dma));
542
543 hisi_sas_write32(hisi_hba, IO_BROKEN_MSG_ADDR_HI,
544 upper_32_bits(hisi_hba->breakpoint_dma));
545
546 /* SATA broken msg */
547 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_LO,
548 lower_32_bits(hisi_hba->sata_breakpoint_dma));
549
550 hisi_sas_write32(hisi_hba, IO_SATA_BROKEN_MSG_ADDR_HI,
551 upper_32_bits(hisi_hba->sata_breakpoint_dma));
552
553 /* SATA initial fis */
554 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_LO,
555 lower_32_bits(hisi_hba->initial_fis_dma));
556
557 hisi_sas_write32(hisi_hba, SATA_INITI_D2H_STORE_ADDR_HI,
558 upper_32_bits(hisi_hba->initial_fis_dma));
559}
560
561static int hw_init_v2_hw(struct hisi_hba *hisi_hba)
562{
563 struct device *dev = &hisi_hba->pdev->dev;
564 int rc;
565
566 rc = reset_hw_v2_hw(hisi_hba);
567 if (rc) {
568 dev_err(dev, "hisi_sas_reset_hw failed, rc=%d", rc);
569 return rc;
570 }
571
572 msleep(100);
573 init_reg_v2_hw(hisi_hba);
574
806bb768
JG		 575 init_id_frame_v2_hw(hisi_hba);
576
94eac9e1
JG		 577 return 0;
578}
579
29a20428
JG		 580static void enable_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
581{
582 u32 cfg = hisi_sas_phy_read32(hisi_hba, phy_no, PHY_CFG);
583
584 cfg |= PHY_CFG_ENA_MSK;
585 hisi_sas_phy_write32(hisi_hba, phy_no, PHY_CFG, cfg);
586}
587
588static void start_phy_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
589{
590 config_id_frame_v2_hw(hisi_hba, phy_no);
591 config_phy_opt_mode_v2_hw(hisi_hba, phy_no);
592 enable_phy_v2_hw(hisi_hba, phy_no);
593}
594
595static void start_phys_v2_hw(unsigned long data)
596{
597 struct hisi_hba *hisi_hba = (struct hisi_hba *)data;
598 int i;
599
600 for (i = 0; i < hisi_hba->n_phy; i++)
601 start_phy_v2_hw(hisi_hba, i);
602}
603
604static void phys_init_v2_hw(struct hisi_hba *hisi_hba)
605{
606 int i;
607 struct timer_list *timer = &hisi_hba->timer;
608
609 for (i = 0; i < hisi_hba->n_phy; i++) {
610 hisi_sas_phy_write32(hisi_hba, i, CHL_INT2_MSK, 0x6a);
611 hisi_sas_phy_read32(hisi_hba, i, CHL_INT2_MSK);
612 }
613
614 setup_timer(timer, start_phys_v2_hw, (unsigned long)hisi_hba);
615 mod_timer(timer, jiffies + HZ);
616}
617
7911e66f
JG		 618static void sl_notify_v2_hw(struct hisi_hba *hisi_hba, int phy_no)
619{
620 u32 sl_control;
621
622 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
623 sl_control |= SL_CONTROL_NOTIFY_EN_MSK;
624 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
625 msleep(1);
626 sl_control = hisi_sas_phy_read32(hisi_hba, phy_no, SL_CONTROL);
627 sl_control &= ~SL_CONTROL_NOTIFY_EN_MSK;
628 hisi_sas_phy_write32(hisi_hba, phy_no, SL_CONTROL, sl_control);
629}
630
631static int phy_up_v2_hw(int phy_no, struct hisi_hba *hisi_hba)
632{
633 int i, res = 0;
634 u32 context, port_id, link_rate, hard_phy_linkrate;
635 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
636 struct asd_sas_phy *sas_phy = &phy->sas_phy;
637 struct device *dev = &hisi_hba->pdev->dev;
638 u32 *frame_rcvd = (u32 *)sas_phy->frame_rcvd;
639 struct sas_identify_frame *id = (struct sas_identify_frame *)frame_rcvd;
640
641 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 1);
642
643 /* Check for SATA dev */
644 context = hisi_sas_read32(hisi_hba, PHY_CONTEXT);
645 if (context & (1 << phy_no))
646 goto end;
647
648 if (phy_no == 8) {
649 u32 port_state = hisi_sas_read32(hisi_hba, PORT_STATE);
650
651 port_id = (port_state & PORT_STATE_PHY8_PORT_NUM_MSK) >>
652 PORT_STATE_PHY8_PORT_NUM_OFF;
653 link_rate = (port_state & PORT_STATE_PHY8_CONN_RATE_MSK) >>
654 PORT_STATE_PHY8_CONN_RATE_OFF;
655 } else {
656 port_id = hisi_sas_read32(hisi_hba, PHY_PORT_NUM_MA);
657 port_id = (port_id >> (4 * phy_no)) & 0xf;
658 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
659 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
660 }
661
662 if (port_id == 0xf) {
663 dev_err(dev, "phyup: phy%d invalid portid\n", phy_no);
664 res = IRQ_NONE;
665 goto end;
666 }
667
668 for (i = 0; i < 6; i++) {
669 u32 idaf = hisi_sas_phy_read32(hisi_hba, phy_no,
670 RX_IDAF_DWORD0 + (i * 4));
671 frame_rcvd[i] = __swab32(idaf);
672 }
673
674 /* Get the linkrates */
675 link_rate = hisi_sas_read32(hisi_hba, PHY_CONN_RATE);
676 link_rate = (link_rate >> (phy_no * 4)) & 0xf;
677 sas_phy->linkrate = link_rate;
678 hard_phy_linkrate = hisi_sas_phy_read32(hisi_hba, phy_no,
679 HARD_PHY_LINKRATE);
680 phy->maximum_linkrate = hard_phy_linkrate & 0xf;
681 phy->minimum_linkrate = (hard_phy_linkrate >> 4) & 0xf;
682
683 sas_phy->oob_mode = SAS_OOB_MODE;
684 memcpy(sas_phy->attached_sas_addr, &id->sas_addr, SAS_ADDR_SIZE);
685 dev_info(dev, "phyup: phy%d link_rate=%d\n", phy_no, link_rate);
686 phy->port_id = port_id;
687 phy->phy_type &= ~(PORT_TYPE_SAS | PORT_TYPE_SATA);
688 phy->phy_type |= PORT_TYPE_SAS;
689 phy->phy_attached = 1;
690 phy->identify.device_type = id->dev_type;
691 phy->frame_rcvd_size = sizeof(struct sas_identify_frame);
692 if (phy->identify.device_type == SAS_END_DEVICE)
693 phy->identify.target_port_protocols =
694 SAS_PROTOCOL_SSP;
695 else if (phy->identify.device_type != SAS_PHY_UNUSED)
696 phy->identify.target_port_protocols =
697 SAS_PROTOCOL_SMP;
698 queue_work(hisi_hba->wq, &phy->phyup_ws);
699
700end:
701 hisi_sas_phy_write32(hisi_hba, phy_no, CHL_INT0,
702 CHL_INT0_SL_PHY_ENABLE_MSK);
703 hisi_sas_phy_write32(hisi_hba, phy_no, PHYCTRL_PHY_ENA_MSK, 0);
704
705 return res;
706}
707
708static irqreturn_t int_phy_updown_v2_hw(int irq_no, void *p)
709{
710 struct hisi_hba *hisi_hba = p;
711 u32 irq_msk;
712 int phy_no = 0;
713 irqreturn_t res = IRQ_HANDLED;
714
715 irq_msk = (hisi_sas_read32(hisi_hba, HGC_INVLD_DQE_INFO)
716 >> HGC_INVLD_DQE_INFO_FB_CH0_OFF) & 0x1ff;
717 while (irq_msk) {
718 if (irq_msk & 1) {
719 u32 irq_value = hisi_sas_phy_read32(hisi_hba, phy_no,
720 CHL_INT0);
721
722 if (irq_value & CHL_INT0_SL_PHY_ENABLE_MSK)
723 /* phy up */
724 if (phy_up_v2_hw(phy_no, hisi_hba)) {
725 res = IRQ_NONE;
726 goto end;
727 }
728
729 }
730 irq_msk >>= 1;
731 phy_no++;
732 }
733
734end:
735 return res;
736}
737
738static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
739 int_phy_updown_v2_hw,
740};
741
742/**
743 * There is a limitation in the hip06 chipset that we need
744 * to map in all mbigen interrupts, even if they are not used.
745 */
746static int interrupt_init_v2_hw(struct hisi_hba *hisi_hba)
747{
748 struct platform_device *pdev = hisi_hba->pdev;
749 struct device *dev = &pdev->dev;
750 int i, irq, rc, irq_map[128];
751
752
753 for (i = 0; i < 128; i++)
754 irq_map[i] = platform_get_irq(pdev, i);
755
756 for (i = 0; i < HISI_SAS_PHY_INT_NR; i++) {
757 int idx = i;
758
759 irq = irq_map[idx + 1]; /* Phy up/down is irq1 */
760 if (!irq) {
761 dev_err(dev, "irq init: fail map phy interrupt %d\n",
762 idx);
763 return -ENOENT;
764 }
765
766 rc = devm_request_irq(dev, irq, phy_interrupts[i], 0,
767 DRV_NAME " phy", hisi_hba);
768 if (rc) {
769 dev_err(dev, "irq init: could not request "
770 "phy interrupt %d, rc=%d\n",
771 irq, rc);
772 return -ENOENT;
773 }
774 }
775
776 return 0;
777}
778
94eac9e1
JG		 779static int hisi_sas_v2_init(struct hisi_hba *hisi_hba)
780{
781 int rc;
782
783 rc = hw_init_v2_hw(hisi_hba);
784 if (rc)
785 return rc;
786
7911e66f
JG		 787 rc = interrupt_init_v2_hw(hisi_hba);
788 if (rc)
789 return rc;
790
29a20428
JG		 791 phys_init_v2_hw(hisi_hba);
792
94eac9e1
JG		 793 return 0;
794}
795
3417ba8a 796static const struct hisi_sas_hw hisi_sas_v2_hw = {
94eac9e1 797 .hw_init = hisi_sas_v2_init,
7911e66f 798 .sl_notify = sl_notify_v2_hw,
94eac9e1
JG		 799 .max_command_entries = HISI_SAS_COMMAND_ENTRIES_V2_HW,
800 .complete_hdr_size = sizeof(struct hisi_sas_complete_v2_hdr),
3417ba8a
JG		 801};
802
803static int hisi_sas_v2_probe(struct platform_device *pdev)
804{
805 return hisi_sas_probe(pdev, &hisi_sas_v2_hw);
806}
807
808static int hisi_sas_v2_remove(struct platform_device *pdev)
809{
810 return hisi_sas_remove(pdev);
811}
812
813static const struct of_device_id sas_v2_of_match[] = {
814 { .compatible = "hisilicon,hip06-sas-v2",},
815 {},
816};
817MODULE_DEVICE_TABLE(of, sas_v2_of_match);
818
819static struct platform_driver hisi_sas_v2_driver = {
820 .probe = hisi_sas_v2_probe,
821 .remove = hisi_sas_v2_remove,
822 .driver = {
823 .name = DRV_NAME,
824 .of_match_table = sas_v2_of_match,
825 },
826};
827
828module_platform_driver(hisi_sas_v2_driver);
829
830MODULE_LICENSE("GPL");
831MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
832MODULE_DESCRIPTION("HISILICON SAS controller v2 hw driver");
833MODULE_ALIAS("platform:" DRV_NAME);
Linux 6.x block layer and io_uring tree(s)