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Merge tag 'probes-fixes-v6.16-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6-block.git] / drivers / scsi / hisi_sas / hisi_sas_main.c
CommitLineData
2874c5fd 1// SPDX-License-Identifier: GPL-2.0-or-later
e8899fad
JG		 2/*
3 * Copyright (c) 2015 Linaro Ltd.
4 * Copyright (c) 2015 Hisilicon Limited.
e8899fad
JG		 5 */
6
7#include "hisi_sas.h"
8#define DRV_NAME "hisi_sas"
9
4ca7fe99
YL		 10#define LINK_RATE_BIT_MASK 2
11#define FIS_BUF_SIZE 20
12#define WAIT_CMD_COMPLETE_DELAY 100
13#define WAIT_CMD_COMPLETE_TMROUT 5000
14#define DELAY_FOR_LINK_READY 2000
15#define BLK_CNT_OPTIMIZE_MARK 64
16#define HZ_TO_MHZ 1000000
17#define DELAY_FOR_SOFTRESET_MAX 1000
18#define DELAY_FOR_SOFTRESET_MIN 900
19
42e7a693
JG		 20#define DEV_IS_GONE(dev) \
21 ((!dev) || (dev->dev_type == SAS_PHY_UNUSED))
22
7c594f04 23static int hisi_sas_softreset_ata_disk(struct domain_device *device);
057c3d1f
XT		 24static int hisi_sas_control_phy(struct asd_sas_phy *sas_phy, enum phy_func func,
25 void *funcdata);
d5a60dfd
XC		 26static void hisi_sas_release_task(struct hisi_hba *hisi_hba,
27 struct domain_device *device);
28static void hisi_sas_dev_gone(struct domain_device *device);
cac9b2a2 29
095478a6
JG		 30struct hisi_sas_internal_abort_data {
31 bool rst_ha_timeout; /* reset the HA for timeout */
32};
33
750d4fbe 34static u8 hisi_sas_get_ata_protocol_from_tf(struct ata_queued_cmd *qc)
6c7bb8a1 35{
750d4fbe
XY		 36 if (!qc)
37 return HISI_SAS_SATA_PROTOCOL_PIO;
38
39 switch (qc->tf.protocol) {
40 case ATA_PROT_NODATA:
41 return HISI_SAS_SATA_PROTOCOL_NONDATA;
42 case ATA_PROT_PIO:
43 return HISI_SAS_SATA_PROTOCOL_PIO;
44 case ATA_PROT_DMA:
45 return HISI_SAS_SATA_PROTOCOL_DMA;
46 case ATA_PROT_NCQ_NODATA:
47 case ATA_PROT_NCQ:
48 return HISI_SAS_SATA_PROTOCOL_FPDMA;
49 default:
50 return HISI_SAS_SATA_PROTOCOL_PIO;
51 }
52}
53
54u8 hisi_sas_get_ata_protocol(struct sas_task *task)
55{
56 struct host_to_dev_fis *fis = &task->ata_task.fis;
57 struct ata_queued_cmd *qc = task->uldd_task;
58 int direction = task->data_dir;
59
468f4b8d 60 switch (fis->command) {
6c7bb8a1
XC		 61 case ATA_CMD_FPDMA_WRITE:
62 case ATA_CMD_FPDMA_READ:
63 case ATA_CMD_FPDMA_RECV:
64 case ATA_CMD_FPDMA_SEND:
65 case ATA_CMD_NCQ_NON_DATA:
edafeef4 66 return HISI_SAS_SATA_PROTOCOL_FPDMA;
6c7bb8a1
XC		 67
68 case ATA_CMD_DOWNLOAD_MICRO:
69 case ATA_CMD_ID_ATA:
70 case ATA_CMD_PMP_READ:
71 case ATA_CMD_READ_LOG_EXT:
72 case ATA_CMD_PIO_READ:
73 case ATA_CMD_PIO_READ_EXT:
74 case ATA_CMD_PMP_WRITE:
75 case ATA_CMD_WRITE_LOG_EXT:
76 case ATA_CMD_PIO_WRITE:
77 case ATA_CMD_PIO_WRITE_EXT:
edafeef4 78 return HISI_SAS_SATA_PROTOCOL_PIO;
6c7bb8a1
XC		 79
80 case ATA_CMD_DSM:
81 case ATA_CMD_DOWNLOAD_MICRO_DMA:
82 case ATA_CMD_PMP_READ_DMA:
83 case ATA_CMD_PMP_WRITE_DMA:
84 case ATA_CMD_READ:
85 case ATA_CMD_READ_EXT:
86 case ATA_CMD_READ_LOG_DMA_EXT:
87 case ATA_CMD_READ_STREAM_DMA_EXT:
88 case ATA_CMD_TRUSTED_RCV_DMA:
89 case ATA_CMD_TRUSTED_SND_DMA:
90 case ATA_CMD_WRITE:
91 case ATA_CMD_WRITE_EXT:
92 case ATA_CMD_WRITE_FUA_EXT:
93 case ATA_CMD_WRITE_QUEUED:
94 case ATA_CMD_WRITE_LOG_DMA_EXT:
95 case ATA_CMD_WRITE_STREAM_DMA_EXT:
c3fe8a2b 96 case ATA_CMD_ZAC_MGMT_IN:
edafeef4 97 return HISI_SAS_SATA_PROTOCOL_DMA;
6c7bb8a1
XC		 98
99 case ATA_CMD_CHK_POWER:
100 case ATA_CMD_DEV_RESET:
101 case ATA_CMD_EDD:
102 case ATA_CMD_FLUSH:
103 case ATA_CMD_FLUSH_EXT:
104 case ATA_CMD_VERIFY:
105 case ATA_CMD_VERIFY_EXT:
106 case ATA_CMD_SET_FEATURES:
107 case ATA_CMD_STANDBY:
108 case ATA_CMD_STANDBYNOW1:
c3fe8a2b 109 case ATA_CMD_ZAC_MGMT_OUT:
edafeef4 110 return HISI_SAS_SATA_PROTOCOL_NONDATA;
468f4b8d 111
3ff0f0b6
XT		 112 case ATA_CMD_SET_MAX:
113 switch (fis->features) {
114 case ATA_SET_MAX_PASSWD:
115 case ATA_SET_MAX_LOCK:
116 return HISI_SAS_SATA_PROTOCOL_PIO;
468f4b8d 117
3ff0f0b6
XT		 118 case ATA_SET_MAX_PASSWD_DMA:
119 case ATA_SET_MAX_UNLOCK_DMA:
120 return HISI_SAS_SATA_PROTOCOL_DMA;
121
122 default:
123 return HISI_SAS_SATA_PROTOCOL_NONDATA;
468f4b8d 124 }
3ff0f0b6
XT		 125
126 default:
6c7bb8a1
XC		 127 if (direction == DMA_NONE)
128 return HISI_SAS_SATA_PROTOCOL_NONDATA;
750d4fbe 129 return hisi_sas_get_ata_protocol_from_tf(qc);
6c7bb8a1
XC		 130 }
131}
132EXPORT_SYMBOL_GPL(hisi_sas_get_ata_protocol);
133
75904077
XC		 134void hisi_sas_sata_done(struct sas_task *task,
135 struct hisi_sas_slot *slot)
136{
137 struct task_status_struct *ts = &task->task_status;
138 struct ata_task_resp *resp = (struct ata_task_resp *)ts->buf;
f557e32c
XT		 139 struct hisi_sas_status_buffer *status_buf =
140 hisi_sas_status_buf_addr_mem(slot);
141 u8 *iu = &status_buf->iu[0];
92c8fe15 142 struct dev_to_host_fis *d2h = (struct dev_to_host_fis *)iu;
75904077
XC		 143
144 resp->frame_len = sizeof(struct dev_to_host_fis);
145 memcpy(&resp->ending_fis[0], d2h, sizeof(struct dev_to_host_fis));
146
147 ts->buf_valid_size = sizeof(*resp);
148}
149EXPORT_SYMBOL_GPL(hisi_sas_sata_done);
150
c2c1d9de
XC		 151/*
152 * This function assumes linkrate mask fits in 8 bits, which it
153 * does for all HW versions supported.
154 */
155u8 hisi_sas_get_prog_phy_linkrate_mask(enum sas_linkrate max)
156{
4a8bec88 157 u8 rate = 0;
c2c1d9de
XC		 158 int i;
159
160 max -= SAS_LINK_RATE_1_5_GBPS;
161 for (i = 0; i <= max; i++)
4ca7fe99 162 rate |= 1 << (i * LINK_RATE_BIT_MASK);
c2c1d9de
XC		 163 return rate;
164}
165EXPORT_SYMBOL_GPL(hisi_sas_get_prog_phy_linkrate_mask);
166
42e7a693
JG		 167static struct hisi_hba *dev_to_hisi_hba(struct domain_device *device)
168{
169 return device->port->ha->lldd_ha;
170}
171
2e244f0f
JG		 172struct hisi_sas_port *to_hisi_sas_port(struct asd_sas_port *sas_port)
173{
174 return container_of(sas_port, struct hisi_sas_port, sas_port);
175}
176EXPORT_SYMBOL_GPL(to_hisi_sas_port);
177
a25d0d3d
XC		 178void hisi_sas_stop_phys(struct hisi_hba *hisi_hba)
179{
180 int phy_no;
181
182 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++)
c63b88cc 183 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
a25d0d3d
XC		 184}
185EXPORT_SYMBOL_GPL(hisi_sas_stop_phys);
186
257efd1f
JG		 187static void hisi_sas_slot_index_clear(struct hisi_hba *hisi_hba, int slot_idx)
188{
189 void *bitmap = hisi_hba->slot_index_tags;
190
4d6942e2 191 __clear_bit(slot_idx, bitmap);
257efd1f
JG		 192}
193
42e7a693
JG		 194static void hisi_sas_slot_index_free(struct hisi_hba *hisi_hba, int slot_idx)
195{
93352abc 196 if (hisi_hba->hw->slot_index_alloc ||
ea44242b 197 slot_idx < HISI_SAS_RESERVED_IPTT) {
e9dc5e11 198 spin_lock(&hisi_hba->lock);
784b46b7 199 hisi_sas_slot_index_clear(hisi_hba, slot_idx);
e9dc5e11 200 spin_unlock(&hisi_hba->lock);
784b46b7 201 }
42e7a693
JG		 202}
203
204static void hisi_sas_slot_index_set(struct hisi_hba *hisi_hba, int slot_idx)
205{
206 void *bitmap = hisi_hba->slot_index_tags;
207
4d6942e2 208 __set_bit(slot_idx, bitmap);
42e7a693
JG		 209}
210
784b46b7 211static int hisi_sas_slot_index_alloc(struct hisi_hba *hisi_hba,
295fd233 212 struct request *rq)
42e7a693 213{
784b46b7 214 int index;
42e7a693
JG		 215 void *bitmap = hisi_hba->slot_index_tags;
216
295fd233 217 if (rq)
f7d190a9 218 return rq->tag + HISI_SAS_RESERVED_IPTT;
784b46b7 219
e9dc5e11 220 spin_lock(&hisi_hba->lock);
f7d190a9 221 index = find_next_zero_bit(bitmap, HISI_SAS_RESERVED_IPTT,
784b46b7 222 hisi_hba->last_slot_index + 1);
f7d190a9 223 if (index >= HISI_SAS_RESERVED_IPTT) {
784b46b7 224 index = find_next_zero_bit(bitmap,
f7d190a9
JG		 225 HISI_SAS_RESERVED_IPTT,
226 0);
227 if (index >= HISI_SAS_RESERVED_IPTT) {
e9dc5e11 228 spin_unlock(&hisi_hba->lock);
fa3be0f2 229 return -SAS_QUEUE_FULL;
784b46b7 230 }
fa3be0f2 231 }
42e7a693 232 hisi_sas_slot_index_set(hisi_hba, index);
fa3be0f2 233 hisi_hba->last_slot_index = index;
e9dc5e11 234 spin_unlock(&hisi_hba->lock);
fa3be0f2 235
784b46b7 236 return index;
42e7a693
JG		 237}
238
27a3f229 239void hisi_sas_slot_task_free(struct hisi_hba *hisi_hba, struct sas_task *task,
71fb36b5 240 struct hisi_sas_slot *slot, bool need_lock)
27a3f229 241{
4fefe5bb
XC		 242 int device_id = slot->device_id;
243 struct hisi_sas_device *sas_dev = &hisi_hba->devices[device_id];
27a3f229 244
d3c4dd4e 245 if (task) {
11b75249 246 struct device *dev = hisi_hba->dev;
27a3f229 247
6ba0fbc3
XT		 248 if (!task->lldd_task)
249 return;
250
251 task->lldd_task = NULL;
252
b3cce125 253 if (!sas_protocol_ata(task->task_proto)) {
f0902095 254 if (slot->n_elem) {
bc22f9c0
XC		 255 if (task->task_proto & SAS_PROTOCOL_SSP)
256 dma_unmap_sg(dev, task->scatter,
257 task->num_scatter,
258 task->data_dir);
f0902095
XC		 259 else
260 dma_unmap_sg(dev, &task->smp_task.smp_req,
261 1, DMA_TO_DEVICE);
262 }
847e8355
XC		 263 if (slot->n_elem_dif) {
264 struct sas_ssp_task *ssp_task = &task->ssp_task;
265 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
266
b3cce125
XC		 267 dma_unmap_sg(dev, scsi_prot_sglist(scsi_cmnd),
268 scsi_prot_sg_count(scsi_cmnd),
269 task->data_dir);
847e8355 270 }
b3cce125 271 }
d3c4dd4e 272 }
27a3f229 273
71fb36b5
XY		 274 if (need_lock) {
275 spin_lock(&sas_dev->lock);
276 list_del_init(&slot->entry);
277 spin_unlock(&sas_dev->lock);
278 } else {
279 list_del_init(&slot->entry);
280 }
2ba5afb6
XC		 281
282 memset(slot, 0, offsetof(struct hisi_sas_slot, buf));
283
27a3f229 284 hisi_sas_slot_index_free(hisi_hba, slot->idx);
27a3f229
JG		 285}
286EXPORT_SYMBOL_GPL(hisi_sas_slot_task_free);
287
a2b3820b 288static void hisi_sas_task_prep_smp(struct hisi_hba *hisi_hba,
66ee999b
JG		 289 struct hisi_sas_slot *slot)
290{
a2b3820b 291 hisi_hba->hw->prep_smp(hisi_hba, slot);
66ee999b
JG		 292}
293
a2b3820b 294static void hisi_sas_task_prep_ssp(struct hisi_hba *hisi_hba,
78bd2b4f 295 struct hisi_sas_slot *slot)
42e7a693 296{
78bd2b4f 297 hisi_hba->hw->prep_ssp(hisi_hba, slot);
42e7a693
JG		 298}
299
a2b3820b 300static void hisi_sas_task_prep_ata(struct hisi_hba *hisi_hba,
6f2ff1a1
JG		 301 struct hisi_sas_slot *slot)
302{
a2b3820b 303 hisi_hba->hw->prep_stp(hisi_hba, slot);
6f2ff1a1
JG		 304}
305
a2b3820b 306static void hisi_sas_task_prep_abort(struct hisi_hba *hisi_hba,
095478a6 307 struct hisi_sas_slot *slot)
441c2740 308{
095478a6 309 hisi_hba->hw->prep_abort(hisi_hba, slot);
441c2740
JG		 310}
311
6e1b731b 312static void hisi_sas_dma_unmap(struct hisi_hba *hisi_hba,
bc22f9c0 313 struct sas_task *task, int n_elem)
6e1b731b
XC		 314{
315 struct device *dev = hisi_hba->dev;
316
bc22f9c0 317 if (!sas_protocol_ata(task->task_proto) && n_elem) {
6e1b731b 318 if (task->num_scatter) {
bc22f9c0
XC		 319 dma_unmap_sg(dev, task->scatter, task->num_scatter,
320 task->data_dir);
6e1b731b 321 } else if (task->task_proto & SAS_PROTOCOL_SMP) {
bc22f9c0
XC		 322 dma_unmap_sg(dev, &task->smp_task.smp_req,
323 1, DMA_TO_DEVICE);
6e1b731b
XC		 324 }
325 }
326}
327
328static int hisi_sas_dma_map(struct hisi_hba *hisi_hba,
bc22f9c0 329 struct sas_task *task, int *n_elem)
6e1b731b
XC		 330{
331 struct device *dev = hisi_hba->dev;
332 int rc;
333
334 if (sas_protocol_ata(task->task_proto)) {
335 *n_elem = task->num_scatter;
336 } else {
5f6c32d7 337 unsigned int req_len;
6e1b731b
XC		 338
339 if (task->num_scatter) {
340 *n_elem = dma_map_sg(dev, task->scatter,
341 task->num_scatter, task->data_dir);
342 if (!*n_elem) {
343 rc = -ENOMEM;
344 goto prep_out;
345 }
346 } else if (task->task_proto & SAS_PROTOCOL_SMP) {
bc22f9c0
XC		 347 *n_elem = dma_map_sg(dev, &task->smp_task.smp_req,
348 1, DMA_TO_DEVICE);
349 if (!*n_elem) {
6e1b731b
XC		 350 rc = -ENOMEM;
351 goto prep_out;
352 }
353 req_len = sg_dma_len(&task->smp_task.smp_req);
354 if (req_len & 0x3) {
355 rc = -EINVAL;
356 goto err_out_dma_unmap;
357 }
6e1b731b
XC		 358 }
359 }
360
361 if (*n_elem > HISI_SAS_SGE_PAGE_CNT) {
b601577d 362 dev_err(dev, "task prep: n_elem(%d) > HISI_SAS_SGE_PAGE_CNT\n",
6e1b731b
XC		 363 *n_elem);
364 rc = -EINVAL;
365 goto err_out_dma_unmap;
366 }
367 return 0;
368
369err_out_dma_unmap:
370 /* It would be better to call dma_unmap_sg() here, but it's messy */
bc22f9c0 371 hisi_sas_dma_unmap(hisi_hba, task, *n_elem);
6e1b731b
XC		 372prep_out:
373 return rc;
374}
375
b3cce125
XC		 376static void hisi_sas_dif_dma_unmap(struct hisi_hba *hisi_hba,
377 struct sas_task *task, int n_elem_dif)
378{
379 struct device *dev = hisi_hba->dev;
380
381 if (n_elem_dif) {
382 struct sas_ssp_task *ssp_task = &task->ssp_task;
383 struct scsi_cmnd *scsi_cmnd = ssp_task->cmd;
384
385 dma_unmap_sg(dev, scsi_prot_sglist(scsi_cmnd),
386 scsi_prot_sg_count(scsi_cmnd),
387 task->data_dir);
388 }
389}
390
391static int hisi_sas_dif_dma_map(struct hisi_hba *hisi_hba,
392 int *n_elem_dif, struct sas_task *task)
393{
394 struct device *dev = hisi_hba->dev;
395 struct sas_ssp_task *ssp_task;
396 struct scsi_cmnd *scsi_cmnd;
397 int rc;
398
399 if (task->num_scatter) {
400 ssp_task = &task->ssp_task;
401 scsi_cmnd = ssp_task->cmd;
402
403 if (scsi_prot_sg_count(scsi_cmnd)) {
404 *n_elem_dif = dma_map_sg(dev,
405 scsi_prot_sglist(scsi_cmnd),
406 scsi_prot_sg_count(scsi_cmnd),
407 task->data_dir);
408
409 if (!*n_elem_dif)
410 return -ENOMEM;
411
412 if (*n_elem_dif > HISI_SAS_SGE_DIF_PAGE_CNT) {
413 dev_err(dev, "task prep: n_elem_dif(%d) too large\n",
414 *n_elem_dif);
415 rc = -EINVAL;
416 goto err_out_dif_dma_unmap;
417 }
418 }
419 }
420
421 return 0;
422
423err_out_dif_dma_unmap:
424 dma_unmap_sg(dev, scsi_prot_sglist(scsi_cmnd),
425 scsi_prot_sg_count(scsi_cmnd), task->data_dir);
426 return rc;
427}
428
dc313f6b
JG		 429static
430void hisi_sas_task_deliver(struct hisi_hba *hisi_hba,
431 struct hisi_sas_slot *slot,
432 struct hisi_sas_dq *dq,
095478a6 433 struct hisi_sas_device *sas_dev)
42e7a693 434{
dc313f6b
JG		 435 struct hisi_sas_cmd_hdr *cmd_hdr_base;
436 int dlvry_queue_slot, dlvry_queue;
437 struct sas_task *task = slot->task;
fa222db0 438 int wr_q_index;
42e7a693 439
e9dc5e11 440 spin_lock(&dq->lock);
897cc769
JG		 441 wr_q_index = dq->wr_point;
442 dq->wr_point = (dq->wr_point + 1) % HISI_SAS_QUEUE_SLOTS;
fa222db0 443 list_add_tail(&slot->delivery, &dq->list);
e9dc5e11
XC		 444 spin_unlock(&dq->lock);
445 spin_lock(&sas_dev->lock);
4fefe5bb 446 list_add_tail(&slot->entry, &sas_dev->list);
e9dc5e11 447 spin_unlock(&sas_dev->lock);
42e7a693 448
b1a49412 449 dlvry_queue = dq->id;
fa222db0 450 dlvry_queue_slot = wr_q_index;
42e7a693 451
4fefe5bb 452 slot->device_id = sas_dev->device_id;
42e7a693
JG		 453 slot->dlvry_queue = dlvry_queue;
454 slot->dlvry_queue_slot = dlvry_queue_slot;
455 cmd_hdr_base = hisi_hba->cmd_hdr[dlvry_queue];
456 slot->cmd_hdr = &cmd_hdr_base[dlvry_queue_slot];
dc313f6b 457
42e7a693
JG		 458 task->lldd_task = slot;
459
42e7a693 460 memset(slot->cmd_hdr, 0, sizeof(struct hisi_sas_cmd_hdr));
f557e32c 461 memset(hisi_sas_cmd_hdr_addr_mem(slot), 0, HISI_SAS_COMMAND_TABLE_SZ);
d380f555
XC		 462 memset(hisi_sas_status_buf_addr_mem(slot), 0,
463 sizeof(struct hisi_sas_err_record));
42e7a693
JG		 464
465 switch (task->task_proto) {
66ee999b 466 case SAS_PROTOCOL_SMP:
a2b3820b 467 hisi_sas_task_prep_smp(hisi_hba, slot);
66ee999b 468 break;
42e7a693 469 case SAS_PROTOCOL_SSP:
78bd2b4f 470 hisi_sas_task_prep_ssp(hisi_hba, slot);
42e7a693
JG		 471 break;
472 case SAS_PROTOCOL_SATA:
473 case SAS_PROTOCOL_STP:
095478a6 474 case SAS_PROTOCOL_STP_ALL:
a2b3820b 475 hisi_sas_task_prep_ata(hisi_hba, slot);
6f2ff1a1 476 break;
095478a6
JG		 477 case SAS_PROTOCOL_INTERNAL_ABORT:
478 hisi_sas_task_prep_abort(hisi_hba, slot);
479 break;
42e7a693 480 default:
095478a6 481 return;
42e7a693
JG		 482 }
483
6c6ac8b7
JG		 484 /* Make slot memories observable before marking as ready */
485 smp_wmb();
1c09b663 486 WRITE_ONCE(slot->ready, 1);
42e7a693 487
0e462085
JG		 488 spin_lock(&dq->lock);
489 hisi_hba->hw->start_delivery(dq);
490 spin_unlock(&dq->lock);
42e7a693
JG		 491}
492
96e54376 493static int hisi_sas_queue_command(struct sas_task *task, gfp_t gfp_flags)
42e7a693 494{
bc22f9c0 495 int n_elem = 0, n_elem_dif = 0;
745b6847
XC		 496 struct domain_device *device = task->dev;
497 struct asd_sas_port *sas_port = device->port;
dc313f6b 498 struct hisi_sas_device *sas_dev = device->lldd_dev;
095478a6 499 bool internal_abort = sas_is_internal_abort(task);
2f6bca20 500 struct hisi_sas_dq *dq = NULL;
dc313f6b
JG		 501 struct hisi_sas_port *port;
502 struct hisi_hba *hisi_hba;
503 struct hisi_sas_slot *slot;
295fd233 504 struct request *rq = NULL;
dc313f6b
JG		 505 struct device *dev;
506 int rc;
42e7a693 507
745b6847
XC		 508 if (!sas_port) {
509 struct task_status_struct *ts = &task->task_status;
510
511 ts->resp = SAS_TASK_UNDELIVERED;
512 ts->stat = SAS_PHY_DOWN;
513 /*
514 * libsas will use dev->port, should
515 * not call task_done for sata
516 */
095478a6 517 if (device->dev_type != SAS_SATA_DEV && !internal_abort)
745b6847
XC		 518 task->task_done(task);
519 return -ECOMM;
520 }
521
522 hisi_hba = dev_to_hisi_hba(device);
523 dev = hisi_hba->dev;
524
095478a6
JG		 525 switch (task->task_proto) {
526 case SAS_PROTOCOL_SSP:
527 case SAS_PROTOCOL_SMP:
528 case SAS_PROTOCOL_SATA:
529 case SAS_PROTOCOL_STP:
530 case SAS_PROTOCOL_STP_ALL:
531 if (unlikely(test_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags))) {
532 if (!gfpflags_allow_blocking(gfp_flags))
533 return -EINVAL;
214e702d 534
095478a6
JG		 535 down(&hisi_hba->sem);
536 up(&hisi_hba->sem);
537 }
06ec0fb9 538
095478a6
JG		 539 if (DEV_IS_GONE(sas_dev)) {
540 if (sas_dev)
541 dev_info(dev, "task prep: device %d not ready\n",
542 sas_dev->device_id);
543 else
544 dev_info(dev, "task prep: device %016llx not ready\n",
545 SAS_ADDR(device->sas_addr));
dc313f6b 546
095478a6
JG		 547 return -ECOMM;
548 }
dc313f6b 549
095478a6
JG		 550 port = to_hisi_sas_port(sas_port);
551 if (!port->port_attached) {
552 dev_info(dev, "task prep: %s port%d not attach device\n",
553 dev_is_sata(device) ? "SATA/STP" : "SAS",
554 device->port->id);
dc313f6b 555
095478a6 556 return -ECOMM;
dc313f6b 557 }
dc313f6b 558
295fd233
JG		 559 rq = sas_task_find_rq(task);
560 if (rq) {
095478a6
JG		 561 unsigned int dq_index;
562 u32 blk_tag;
dc313f6b 563
295fd233 564 blk_tag = blk_mq_unique_tag(rq);
095478a6
JG		 565 dq_index = blk_mq_unique_tag_to_hwq(blk_tag);
566 dq = &hisi_hba->dq[dq_index];
567 } else {
0e47effa
XC		 568 int queue;
569
570 if (hisi_hba->iopoll_q_cnt) {
571 /*
572 * Use interrupt queue (queue 0) to deliver and complete
573 * internal IOs of libsas or libata when there is at least
574 * one iopoll queue
575 */
576 queue = 0;
577 } else {
578 struct Scsi_Host *shost = hisi_hba->shost;
579 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT];
dc313f6b 580
0e47effa
XC		 581 queue = qmap->mq_map[raw_smp_processor_id()];
582 }
095478a6
JG		 583 dq = &hisi_hba->dq[queue];
584 }
585 break;
586 case SAS_PROTOCOL_INTERNAL_ABORT:
587 if (!hisi_hba->hw->prep_abort)
588 return TMF_RESP_FUNC_FAILED;
589
590 if (test_bit(HISI_SAS_HW_FAULT_BIT, &hisi_hba->flags))
591 return -EIO;
592
593 hisi_hba = dev_to_hisi_hba(device);
594
595 if (unlikely(test_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags)))
596 return -EINVAL;
597
598 port = to_hisi_sas_port(sas_port);
599 dq = &hisi_hba->dq[task->abort_task.qid];
600 break;
601 default:
602 dev_err(hisi_hba->dev, "task prep: unknown/unsupported proto (0x%x)\n",
603 task->task_proto);
604 return -EINVAL;
dc313f6b
JG		 605 }
606
bc22f9c0 607 rc = hisi_sas_dma_map(hisi_hba, task, &n_elem);
dc313f6b
JG		 608 if (rc < 0)
609 goto prep_out;
610
611 if (!sas_protocol_ata(task->task_proto)) {
612 rc = hisi_sas_dif_dma_map(hisi_hba, &n_elem_dif, task);
613 if (rc < 0)
614 goto err_out_dma_unmap;
615 }
616
095478a6 617 if (!internal_abort && hisi_hba->hw->slot_index_alloc)
dc313f6b
JG		 618 rc = hisi_hba->hw->slot_index_alloc(hisi_hba, device);
619 else
295fd233 620 rc = hisi_sas_slot_index_alloc(hisi_hba, rq);
dc313f6b
JG		 621
622 if (rc < 0)
623 goto err_out_dif_dma_unmap;
624
625 slot = &hisi_hba->slot_info[rc];
626 slot->n_elem = n_elem;
627 slot->n_elem_dif = n_elem_dif;
628 slot->task = task;
629 slot->port = port;
630
96e54376 631 slot->tmf = task->tmf;
095478a6 632 slot->is_internal = !!task->tmf || internal_abort;
dc313f6b 633
42e7a693 634 /* protect task_prep and start_delivery sequence */
095478a6 635 hisi_sas_task_deliver(hisi_hba, slot, dq, sas_dev);
42e7a693 636
dc313f6b
JG		 637 return 0;
638
639err_out_dif_dma_unmap:
640 if (!sas_protocol_ata(task->task_proto))
641 hisi_sas_dif_dma_unmap(hisi_hba, task, n_elem_dif);
642err_out_dma_unmap:
bc22f9c0 643 hisi_sas_dma_unmap(hisi_hba, task, n_elem);
dc313f6b
JG		 644prep_out:
645 dev_err(dev, "task exec: failed[%d]!\n", rc);
42e7a693
JG		 646 return rc;
647}
257efd1f 648
26c7efc3
AD		 649static void hisi_sas_bytes_dmaed(struct hisi_hba *hisi_hba, int phy_no,
650 gfp_t gfp_flags)
66139921
JG		 651{
652 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
653 struct asd_sas_phy *sas_phy = &phy->sas_phy;
66139921
JG		 654
655 if (!phy->phy_attached)
656 return;
657
872a90b5 658 sas_notify_phy_event(sas_phy, PHYE_OOB_DONE, gfp_flags);
66139921
JG		 659
660 if (sas_phy->phy) {
661 struct sas_phy *sphy = sas_phy->phy;
662
663 sphy->negotiated_linkrate = sas_phy->linkrate;
66139921 664 sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
2ae75787
XC		 665 sphy->maximum_linkrate_hw =
666 hisi_hba->hw->phy_get_max_linkrate();
667 if (sphy->minimum_linkrate == SAS_LINK_RATE_UNKNOWN)
668 sphy->minimum_linkrate = phy->minimum_linkrate;
669
670 if (sphy->maximum_linkrate == SAS_LINK_RATE_UNKNOWN)
671 sphy->maximum_linkrate = phy->maximum_linkrate;
66139921
JG		 672 }
673
674 if (phy->phy_type & PORT_TYPE_SAS) {
675 struct sas_identify_frame *id;
676
677 id = (struct sas_identify_frame *)phy->frame_rcvd;
678 id->dev_type = phy->identify.device_type;
679 id->initiator_bits = SAS_PROTOCOL_ALL;
680 id->target_bits = phy->identify.target_port_protocols;
681 } else if (phy->phy_type & PORT_TYPE_SATA) {
01d4e3a2 682 /* Nothing */
66139921
JG		 683 }
684
685 sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
872a90b5 686 sas_notify_port_event(sas_phy, PORTE_BYTES_DMAED, gfp_flags);
66139921
JG		 687}
688
abda97c2
JG		 689static struct hisi_sas_device *hisi_sas_alloc_dev(struct domain_device *device)
690{
691 struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
692 struct hisi_sas_device *sas_dev = NULL;
1b865185
XC		 693 int last = hisi_hba->last_dev_id;
694 int first = (hisi_hba->last_dev_id + 1) % HISI_SAS_MAX_DEVICES;
abda97c2
JG		 695 int i;
696
e9dc5e11 697 spin_lock(&hisi_hba->lock);
1b865185 698 for (i = first; i != last; i %= HISI_SAS_MAX_DEVICES) {
abda97c2 699 if (hisi_hba->devices[i].dev_type == SAS_PHY_UNUSED) {
b1a49412
XC		 700 int queue = i % hisi_hba->queue_count;
701 struct hisi_sas_dq *dq = &hisi_hba->dq[queue];
702
abda97c2
JG		 703 hisi_hba->devices[i].device_id = i;
704 sas_dev = &hisi_hba->devices[i];
57dbb2b2 705 sas_dev->dev_status = HISI_SAS_DEV_INIT;
abda97c2
JG		 706 sas_dev->dev_type = device->dev_type;
707 sas_dev->hisi_hba = hisi_hba;
708 sas_dev->sas_device = device;
b1a49412 709 sas_dev->dq = dq;
4fefe5bb 710 spin_lock_init(&sas_dev->lock);
405314df 711 INIT_LIST_HEAD(&hisi_hba->devices[i].list);
abda97c2
JG		 712 break;
713 }
1b865185 714 i++;
abda97c2 715 }
1b865185 716 hisi_hba->last_dev_id = i;
e9dc5e11 717 spin_unlock(&hisi_hba->lock);
abda97c2
JG		 718
719 return sas_dev;
720}
721
b711ef5e
XC		 722static void hisi_sas_sync_poll_cq(struct hisi_sas_cq *cq)
723{
724 /* make sure CQ entries being processed are processed to completion */
725 spin_lock(&cq->poll_lock);
726 spin_unlock(&cq->poll_lock);
727}
728
729static bool hisi_sas_queue_is_poll(struct hisi_sas_cq *cq)
730{
731 struct hisi_hba *hisi_hba = cq->hisi_hba;
732
733 if (cq->id < hisi_hba->queue_count - hisi_hba->iopoll_q_cnt)
734 return false;
735 return true;
736}
737
738static void hisi_sas_sync_cq(struct hisi_sas_cq *cq)
739{
740 if (hisi_sas_queue_is_poll(cq))
741 hisi_sas_sync_poll_cq(cq);
742 else
743 synchronize_irq(cq->irq_no);
744}
745
746void hisi_sas_sync_poll_cqs(struct hisi_hba *hisi_hba)
747{
748 int i;
749
750 for (i = 0; i < hisi_hba->queue_count; i++) {
751 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
752
753 if (hisi_sas_queue_is_poll(cq))
754 hisi_sas_sync_poll_cq(cq);
755 }
756}
757EXPORT_SYMBOL_GPL(hisi_sas_sync_poll_cqs);
758
759void hisi_sas_sync_cqs(struct hisi_hba *hisi_hba)
760{
761 int i;
762
763 for (i = 0; i < hisi_hba->queue_count; i++) {
764 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
765
766 hisi_sas_sync_cq(cq);
767 }
768}
769EXPORT_SYMBOL_GPL(hisi_sas_sync_cqs);
770
693e66a0
JG		 771static void hisi_sas_tmf_aborted(struct sas_task *task)
772{
773 struct hisi_sas_slot *slot = task->lldd_task;
774 struct domain_device *device = task->dev;
775 struct hisi_sas_device *sas_dev = device->lldd_dev;
776 struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
777
778 if (slot) {
779 struct hisi_sas_cq *cq =
780 &hisi_hba->cq[slot->dlvry_queue];
781 /*
b711ef5e 782 * sync irq or poll queue to avoid free'ing task
693e66a0
JG		 783 * before using task in IO completion
784 */
b711ef5e 785 hisi_sas_sync_cq(cq);
693e66a0
JG		 786 slot->task = NULL;
787 }
788}
789
b45e05aa 790#define HISI_SAS_DISK_RECOVER_CNT 3
d5a60dfd
XC		 791static int hisi_sas_init_device(struct domain_device *device)
792{
793 int rc = TMF_RESP_FUNC_COMPLETE;
794 struct scsi_lun lun;
b45e05aa 795 int retry = HISI_SAS_DISK_RECOVER_CNT;
d5a60dfd
XC		 796 struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
797
798 switch (device->dev_type) {
799 case SAS_END_DEVICE:
800 int_to_scsilun(0, &lun);
801
b45e05aa 802 while (retry-- > 0) {
037b4805 803 rc = sas_abort_task_set(device, lun.scsi_lun);
b45e05aa
XC		 804 if (rc == TMF_RESP_FUNC_COMPLETE) {
805 hisi_sas_release_task(hisi_hba, device);
806 break;
807 }
808 }
d5a60dfd
XC		 809 break;
810 case SAS_SATA_DEV:
811 case SAS_SATA_PM:
812 case SAS_SATA_PM_PORT:
813 case SAS_SATA_PENDING:
57dbb2b2 814 /*
e9dedc13
JG		 815 * If an expander is swapped when a SATA disk is attached then
816 * we should issue a hard reset to clear previous affiliation
817 * of STP target port, see SPL (chapter 6.19.4).
818 *
819 * However we don't need to issue a hard reset here for these
820 * reasons:
821 * a. When probing the device, libsas/libata already issues a
a76f1b63 822 * hard reset in sas_probe_sata() -> ata_port_probe().
e9dedc13
JG		 823 * Note that in hisi_sas_debug_I_T_nexus_reset() we take care
824 * to issue a hard reset by checking the dev status (== INIT).
825 * b. When resetting the controller, this is simply unnecessary.
57dbb2b2 826 */
d5a60dfd
XC		 827 while (retry-- > 0) {
828 rc = hisi_sas_softreset_ata_disk(device);
829 if (!rc)
830 break;
831 }
832 break;
833 default:
834 break;
835 }
836
837 return rc;
838}
839
ed638918 840int hisi_sas_sdev_init(struct scsi_device *sdev)
36c6b761 841{
e9dedc13
JG		 842 struct domain_device *ddev = sdev_to_domain_dev(sdev);
843 struct hisi_sas_device *sas_dev = ddev->lldd_dev;
36c6b761
XC		 844 int rc;
845
ed638918 846 rc = sas_sdev_init(sdev);
36c6b761
XC		 847 if (rc)
848 return rc;
36c6b761 849
e9dedc13
JG		 850 rc = hisi_sas_init_device(ddev);
851 if (rc)
852 return rc;
853 sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
854 return 0;
36c6b761 855}
ed638918 856EXPORT_SYMBOL_GPL(hisi_sas_sdev_init);
36c6b761 857
abda97c2
JG		 858static int hisi_sas_dev_found(struct domain_device *device)
859{
860 struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
861 struct domain_device *parent_dev = device->parent;
862 struct hisi_sas_device *sas_dev;
11b75249 863 struct device *dev = hisi_hba->dev;
d5a60dfd 864 int rc;
abda97c2 865
685b6d6e
JG		 866 if (hisi_hba->hw->alloc_dev)
867 sas_dev = hisi_hba->hw->alloc_dev(device);
868 else
869 sas_dev = hisi_sas_alloc_dev(device);
abda97c2
JG		 870 if (!sas_dev) {
871 dev_err(dev, "fail alloc dev: max support %d devices\n",
872 HISI_SAS_MAX_DEVICES);
873 return -EINVAL;
874 }
875
876 device->lldd_dev = sas_dev;
877 hisi_hba->hw->setup_itct(hisi_hba, sas_dev);
878
924a3541 879 if (parent_dev && dev_is_expander(parent_dev->dev_type)) {
abda97c2 880 int phy_no;
abda97c2 881
f0ed7bd5
JY		 882 phy_no = sas_find_attached_phy_id(&parent_dev->ex_dev, device);
883 if (phy_no < 0) {
abda97c2
JG		 884 dev_info(dev, "dev found: no attached "
885 "dev:%016llx at ex:%016llx\n",
886 SAS_ADDR(device->sas_addr),
887 SAS_ADDR(parent_dev->sas_addr));
f0ed7bd5 888 rc = phy_no;
d5a60dfd 889 goto err_out;
abda97c2
JG		 890 }
891 }
892
f1c88211
XC		 893 dev_info(dev, "dev[%d:%x] found\n",
894 sas_dev->device_id, sas_dev->dev_type);
895
abda97c2 896 return 0;
d5a60dfd
XC		 897
898err_out:
899 hisi_sas_dev_gone(device);
900 return rc;
abda97c2
JG		 901}
902
47c2e30a 903int hisi_sas_sdev_configure(struct scsi_device *sdev, struct queue_limits *lim)
31eec8a6
JG		 904{
905 struct domain_device *dev = sdev_to_domain_dev(sdev);
47c2e30a 906 int ret = sas_sdev_configure(sdev, lim);
31eec8a6
JG		 907
908 if (ret)
909 return ret;
910 if (!dev_is_sata(dev))
4ca7fe99 911 sas_change_queue_depth(sdev, HISI_SAS_BLK_QUEUE_DEPTH);
31eec8a6
JG		 912
913 return 0;
914}
47c2e30a 915EXPORT_SYMBOL_GPL(hisi_sas_sdev_configure);
31eec8a6 916
235bfc7f 917void hisi_sas_scan_start(struct Scsi_Host *shost)
701f75ec
JG		 918{
919 struct hisi_hba *hisi_hba = shost_priv(shost);
701f75ec 920
396b8044 921 hisi_hba->hw->phys_init(hisi_hba);
701f75ec 922}
235bfc7f 923EXPORT_SYMBOL_GPL(hisi_sas_scan_start);
701f75ec 924
235bfc7f 925int hisi_sas_scan_finished(struct Scsi_Host *shost, unsigned long time)
701f75ec
JG		 926{
927 struct hisi_hba *hisi_hba = shost_priv(shost);
928 struct sas_ha_struct *sha = &hisi_hba->sha;
929
396b8044
JG		 930 /* Wait for PHY up interrupt to occur */
931 if (time < HZ)
701f75ec
JG		 932 return 0;
933
934 sas_drain_work(sha);
935 return 1;
936}
235bfc7f 937EXPORT_SYMBOL_GPL(hisi_sas_scan_finished);
701f75ec 938
ae9b69e8
XC		 939static void hisi_sas_phyup_work_common(struct work_struct *work,
940 enum hisi_sas_phy_event event)
66139921
JG		 941{
942 struct hisi_sas_phy *phy =
ae9b69e8 943 container_of(work, typeof(*phy), works[event]);
66139921
JG		 944 struct hisi_hba *hisi_hba = phy->hisi_hba;
945 struct asd_sas_phy *sas_phy = &phy->sas_phy;
daff37f0
XY		 946 struct asd_sas_port *sas_port = sas_phy->port;
947 struct hisi_sas_port *port = phy->port;
948 struct device *dev = hisi_hba->dev;
949 struct domain_device *port_dev;
66139921
JG		 950 int phy_no = sas_phy->id;
951
daff37f0
XY		 952 if (!test_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags) &&
953 sas_port && port && (port->id != phy->port_id)) {
954 dev_info(dev, "phy%d's hw port id changed from %d to %llu\n",
955 phy_no, port->id, phy->port_id);
956 port_dev = sas_port->port_dev;
957 if (port_dev && !dev_is_expander(port_dev->dev_type)) {
958 /*
959 * Set the device state to gone to block
960 * sending IO to the device.
961 */
962 set_bit(SAS_DEV_GONE, &port_dev->state);
963 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
964 return;
965 }
966 }
967
366da0da 968 phy->wait_phyup_cnt = 0;
569eddcf
XC		 969 if (phy->identify.target_port_protocols == SAS_PROTOCOL_SSP)
970 hisi_hba->hw->sl_notify_ssp(hisi_hba, phy_no);
26c7efc3 971 hisi_sas_bytes_dmaed(hisi_hba, phy_no, GFP_KERNEL);
66139921 972}
976867e6 973
ae9b69e8
XC		 974static void hisi_sas_phyup_work(struct work_struct *work)
975{
976 hisi_sas_phyup_work_common(work, HISI_PHYE_PHY_UP);
977}
978
057c3d1f
XT		 979static void hisi_sas_linkreset_work(struct work_struct *work)
980{
981 struct hisi_sas_phy *phy =
982 container_of(work, typeof(*phy), works[HISI_PHYE_LINK_RESET]);
983 struct asd_sas_phy *sas_phy = &phy->sas_phy;
984
985 hisi_sas_control_phy(sas_phy, PHY_FUNC_LINK_RESET, NULL);
986}
987
ae9b69e8
XC		 988static void hisi_sas_phyup_pm_work(struct work_struct *work)
989{
990 struct hisi_sas_phy *phy =
991 container_of(work, typeof(*phy), works[HISI_PHYE_PHY_UP_PM]);
992 struct hisi_hba *hisi_hba = phy->hisi_hba;
993 struct device *dev = hisi_hba->dev;
994
995 hisi_sas_phyup_work_common(work, HISI_PHYE_PHY_UP_PM);
996 pm_runtime_put_sync(dev);
997}
998
e537b62b
XT		 999static const work_func_t hisi_sas_phye_fns[HISI_PHYES_NUM] = {
1000 [HISI_PHYE_PHY_UP] = hisi_sas_phyup_work,
057c3d1f 1001 [HISI_PHYE_LINK_RESET] = hisi_sas_linkreset_work,
ae9b69e8 1002 [HISI_PHYE_PHY_UP_PM] = hisi_sas_phyup_pm_work,
e537b62b
XT		 1003};
1004
1005bool hisi_sas_notify_phy_event(struct hisi_sas_phy *phy,
1006 enum hisi_sas_phy_event event)
1007{
1008 struct hisi_hba *hisi_hba = phy->hisi_hba;
1009
1010 if (WARN_ON(event >= HISI_PHYES_NUM))
1011 return false;
1012
1013 return queue_work(hisi_hba->wq, &phy->works[event]);
1014}
1015EXPORT_SYMBOL_GPL(hisi_sas_notify_phy_event);
1016
b6c9b15e
XT		 1017static void hisi_sas_wait_phyup_timedout(struct timer_list *t)
1018{
41cb0855 1019 struct hisi_sas_phy *phy = timer_container_of(phy, t, timer);
b6c9b15e
XT		 1020 struct hisi_hba *hisi_hba = phy->hisi_hba;
1021 struct device *dev = hisi_hba->dev;
1022 int phy_no = phy->sas_phy.id;
1023
1024 dev_warn(dev, "phy%d wait phyup timeout, issuing link reset\n", phy_no);
1025 hisi_sas_notify_phy_event(phy, HISI_PHYE_LINK_RESET);
1026}
1027
366da0da
LJ		 1028#define HISI_SAS_WAIT_PHYUP_RETRIES 10
1029
b6c9b15e
XT		 1030void hisi_sas_phy_oob_ready(struct hisi_hba *hisi_hba, int phy_no)
1031{
1032 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1033 struct device *dev = hisi_hba->dev;
37310bad 1034 unsigned long flags;
b6c9b15e 1035
e16b9ed6 1036 dev_dbg(dev, "phy%d OOB ready\n", phy_no);
37310bad
QL		 1037 spin_lock_irqsave(&phy->lock, flags);
1038 if (phy->phy_attached) {
1039 spin_unlock_irqrestore(&phy->lock, flags);
e16b9ed6 1040 return;
37310bad 1041 }
e16b9ed6 1042
b6c9b15e 1043 if (!timer_pending(&phy->timer)) {
366da0da
LJ		 1044 if (phy->wait_phyup_cnt < HISI_SAS_WAIT_PHYUP_RETRIES) {
1045 phy->wait_phyup_cnt++;
1046 phy->timer.expires = jiffies +
2f12a499 1047 HISI_SAS_WAIT_PHYUP_TIMEOUT;
366da0da 1048 add_timer(&phy->timer);
37310bad
QL		 1049 spin_unlock_irqrestore(&phy->lock, flags);
1050 return;
366da0da 1051 }
37310bad
QL		 1052
1053 dev_warn(dev, "phy%d failed to come up %d times, giving up\n",
1054 phy_no, phy->wait_phyup_cnt);
1055 phy->wait_phyup_cnt = 0;
b6c9b15e 1056 }
37310bad 1057 spin_unlock_irqrestore(&phy->lock, flags);
b6c9b15e 1058}
37310bad 1059
b6c9b15e
XT		 1060EXPORT_SYMBOL_GPL(hisi_sas_phy_oob_ready);
1061
976867e6
JG		 1062static void hisi_sas_phy_init(struct hisi_hba *hisi_hba, int phy_no)
1063{
1064 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1065 struct asd_sas_phy *sas_phy = &phy->sas_phy;
e537b62b 1066 int i;
976867e6
JG		 1067
1068 phy->hisi_hba = hisi_hba;
1069 phy->port = NULL;
eba8c20c
XT		 1070 phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
1071 phy->maximum_linkrate = hisi_hba->hw->phy_get_max_linkrate();
976867e6 1072 sas_phy->enabled = (phy_no < hisi_hba->n_phy) ? 1 : 0;
976867e6
JG		 1073 sas_phy->iproto = SAS_PROTOCOL_ALL;
1074 sas_phy->tproto = 0;
976867e6
JG		 1075 sas_phy->role = PHY_ROLE_INITIATOR;
1076 sas_phy->oob_mode = OOB_NOT_CONNECTED;
1077 sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
1078 sas_phy->id = phy_no;
1079 sas_phy->sas_addr = &hisi_hba->sas_addr[0];
1080 sas_phy->frame_rcvd = &phy->frame_rcvd[0];
1081 sas_phy->ha = (struct sas_ha_struct *)hisi_hba->shost->hostdata;
1082 sas_phy->lldd_phy = phy;
66139921 1083
e537b62b
XT		 1084 for (i = 0; i < HISI_PHYES_NUM; i++)
1085 INIT_WORK(&phy->works[i], hisi_sas_phye_fns[i]);
ce70c2e6
JG		 1086
1087 spin_lock_init(&phy->lock);
b6c9b15e
XT		 1088
1089 timer_setup(&phy->timer, hisi_sas_wait_phyup_timedout, 0);
976867e6
JG		 1090}
1091
c63b88cc
JG		 1092/* Wrapper to ensure we track hisi_sas_phy.enable properly */
1093void hisi_sas_phy_enable(struct hisi_hba *hisi_hba, int phy_no, int enable)
1094{
1095 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1096 struct asd_sas_phy *aphy = &phy->sas_phy;
1097 struct sas_phy *sphy = aphy->phy;
1098 unsigned long flags;
1099
1100 spin_lock_irqsave(&phy->lock, flags);
1101
1102 if (enable) {
1103 /* We may have been enabled already; if so, don't touch */
1104 if (!phy->enable)
1105 sphy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN;
1106 hisi_hba->hw->phy_start(hisi_hba, phy_no);
1107 } else {
1108 sphy->negotiated_linkrate = SAS_PHY_DISABLED;
1109 hisi_hba->hw->phy_disable(hisi_hba, phy_no);
1110 }
1111 phy->enable = enable;
1112 spin_unlock_irqrestore(&phy->lock, flags);
1113}
1114EXPORT_SYMBOL_GPL(hisi_sas_phy_enable);
1115
184a4635
JG		 1116static void hisi_sas_port_notify_formed(struct asd_sas_phy *sas_phy)
1117{
184a4635
JG		 1118 struct hisi_sas_phy *phy = sas_phy->lldd_phy;
1119 struct asd_sas_port *sas_port = sas_phy->port;
8c39673d 1120 struct hisi_sas_port *port;
184a4635
JG		 1121
1122 if (!sas_port)
1123 return;
1124
8c39673d 1125 port = to_hisi_sas_port(sas_port);
184a4635
JG		 1126 port->port_attached = 1;
1127 port->id = phy->port_id;
1128 phy->port = port;
1129 sas_port->lldd_port = port;
184a4635
JG		 1130}
1131
d3c4dd4e 1132static void hisi_sas_do_release_task(struct hisi_hba *hisi_hba, struct sas_task *task,
71fb36b5 1133 struct hisi_sas_slot *slot, bool need_lock)
184a4635 1134{
d3c4dd4e
JG		 1135 if (task) {
1136 unsigned long flags;
1137 struct task_status_struct *ts;
184a4635 1138
d3c4dd4e 1139 ts = &task->task_status;
184a4635 1140
d3c4dd4e
JG		 1141 ts->resp = SAS_TASK_COMPLETE;
1142 ts->stat = SAS_ABORTED_TASK;
1143 spin_lock_irqsave(&task->task_state_lock, flags);
26fc0ea7 1144 task->task_state_flags &= ~SAS_TASK_STATE_PENDING;
47905957
XC		 1145 if (!slot->is_internal && task->task_proto != SAS_PROTOCOL_SMP)
1146 task->task_state_flags |= SAS_TASK_STATE_DONE;
d3c4dd4e
JG		 1147 spin_unlock_irqrestore(&task->task_state_lock, flags);
1148 }
184a4635 1149
71fb36b5 1150 hisi_sas_slot_task_free(hisi_hba, task, slot, need_lock);
184a4635
JG		 1151}
1152
1153static void hisi_sas_release_task(struct hisi_hba *hisi_hba,
1154 struct domain_device *device)
1155{
405314df
JG		 1156 struct hisi_sas_slot *slot, *slot2;
1157 struct hisi_sas_device *sas_dev = device->lldd_dev;
184a4635 1158
71fb36b5 1159 spin_lock(&sas_dev->lock);
405314df 1160 list_for_each_entry_safe(slot, slot2, &sas_dev->list, entry)
71fb36b5
XY		 1161 hisi_sas_do_release_task(hisi_hba, slot->task, slot, false);
1162
1163 spin_unlock(&sas_dev->lock);
184a4635
JG		 1164}
1165
4d0951ee 1166void hisi_sas_release_tasks(struct hisi_hba *hisi_hba)
06ec0fb9 1167{
405314df
JG		 1168 struct hisi_sas_device *sas_dev;
1169 struct domain_device *device;
06ec0fb9
XC		 1170 int i;
1171
405314df
JG		 1172 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
1173 sas_dev = &hisi_hba->devices[i];
1174 device = sas_dev->sas_device;
06ec0fb9 1175
405314df
JG		 1176 if ((sas_dev->dev_type == SAS_PHY_UNUSED) ||
1177 !device)
06ec0fb9 1178 continue;
405314df
JG		 1179
1180 hisi_sas_release_task(hisi_hba, device);
06ec0fb9
XC		 1181 }
1182}
4d0951ee 1183EXPORT_SYMBOL_GPL(hisi_sas_release_tasks);
06ec0fb9 1184
d30ff263
XC		 1185static void hisi_sas_dereg_device(struct hisi_hba *hisi_hba,
1186 struct domain_device *device)
1187{
1188 if (hisi_hba->hw->dereg_device)
1189 hisi_hba->hw->dereg_device(hisi_hba, device);
1190}
1191
095478a6
JG		 1192static int
1193hisi_sas_internal_task_abort_dev(struct hisi_sas_device *sas_dev,
1194 bool rst_ha_timeout)
1195{
1196 struct hisi_sas_internal_abort_data data = { rst_ha_timeout };
1197 struct domain_device *device = sas_dev->sas_device;
1198 struct hisi_hba *hisi_hba = sas_dev->hisi_hba;
1199 int i, rc;
1200
1201 for (i = 0; i < hisi_hba->cq_nvecs; i++) {
1202 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
1203 const struct cpumask *mask = cq->irq_mask;
1204
1205 if (mask && !cpumask_intersects(cpu_online_mask, mask))
1206 continue;
1207 rc = sas_execute_internal_abort_dev(device, i, &data);
1208 if (rc)
1209 return rc;
1210 }
1211
1212 return 0;
1213}
1214
abda97c2
JG		 1215static void hisi_sas_dev_gone(struct domain_device *device)
1216{
1217 struct hisi_sas_device *sas_dev = device->lldd_dev;
1218 struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
11b75249 1219 struct device *dev = hisi_hba->dev;
8fa9a7bd 1220 int ret = 0;
abda97c2 1221
f1c88211 1222 dev_info(dev, "dev[%d:%x] is gone\n",
abda97c2
JG		 1223 sas_dev->device_id, sas_dev->dev_type);
1224
e74006ed 1225 down(&hisi_hba->sem);
b5a9fa20 1226 if (!test_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags)) {
095478a6 1227 hisi_sas_internal_task_abort_dev(sas_dev, true);
40f2702b 1228
f8e45ec2
XC		 1229 hisi_sas_dereg_device(hisi_hba, device);
1230
8fa9a7bd 1231 ret = hisi_hba->hw->clear_itct(hisi_hba, sas_dev);
f8e45ec2 1232 device->lldd_dev = NULL;
f8e45ec2 1233 }
d30ff263 1234
0258141a
XT		 1235 if (hisi_hba->hw->free_device)
1236 hisi_hba->hw->free_device(sas_dev);
8fa9a7bd
XC		 1237
1238 /* Don't mark it as SAS_PHY_UNUSED if failed to clear ITCT */
1239 if (!ret)
1240 sas_dev->dev_type = SAS_PHY_UNUSED;
e74006ed
XC		 1241 sas_dev->sas_device = NULL;
1242 up(&hisi_hba->sem);
abda97c2 1243}
42e7a693 1244
eb44e4d7 1245static int hisi_sas_phy_set_linkrate(struct hisi_hba *hisi_hba, int phy_no,
757db2da
JG		 1246 struct sas_phy_linkrates *r)
1247{
1248 struct sas_phy_linkrates _r;
1249
1250 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1251 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1252 enum sas_linkrate min, max;
1253
eb44e4d7
LJ		 1254 if (r->minimum_linkrate > SAS_LINK_RATE_1_5_GBPS)
1255 return -EINVAL;
1256
757db2da
JG		 1257 if (r->maximum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1258 max = sas_phy->phy->maximum_linkrate;
1259 min = r->minimum_linkrate;
1260 } else if (r->minimum_linkrate == SAS_LINK_RATE_UNKNOWN) {
1261 max = r->maximum_linkrate;
1262 min = sas_phy->phy->minimum_linkrate;
1263 } else
eb44e4d7 1264 return -EINVAL;
757db2da
JG		 1265
1266 _r.maximum_linkrate = max;
1267 _r.minimum_linkrate = min;
1268
5a54691f
LJ		 1269 sas_phy->phy->maximum_linkrate = max;
1270 sas_phy->phy->minimum_linkrate = min;
1271
c63b88cc 1272 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
4ca7fe99 1273 msleep(HISI_SAS_DELAY_FOR_PHY_DISABLE);
757db2da 1274 hisi_hba->hw->phy_set_linkrate(hisi_hba, phy_no, &_r);
c63b88cc 1275 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
eb44e4d7
LJ		 1276
1277 return 0;
757db2da
JG		 1278}
1279
e4189d53
JG		 1280static int hisi_sas_control_phy(struct asd_sas_phy *sas_phy, enum phy_func func,
1281 void *funcdata)
1282{
046ab7d0
XC		 1283 struct hisi_sas_phy *phy = container_of(sas_phy,
1284 struct hisi_sas_phy, sas_phy);
e4189d53
JG		 1285 struct sas_ha_struct *sas_ha = sas_phy->ha;
1286 struct hisi_hba *hisi_hba = sas_ha->lldd_ha;
046ab7d0
XC		 1287 struct device *dev = hisi_hba->dev;
1288 DECLARE_COMPLETION_ONSTACK(completion);
e4189d53 1289 int phy_no = sas_phy->id;
046ab7d0
XC		 1290 u8 sts = phy->phy_attached;
1291 int ret = 0;
1292
20c63493 1293 down(&hisi_hba->sem);
046ab7d0 1294 phy->reset_completion = &completion;
e4189d53
JG		 1295
1296 switch (func) {
1297 case PHY_FUNC_HARD_RESET:
1298 hisi_hba->hw->phy_hard_reset(hisi_hba, phy_no);
1299 break;
1300
1301 case PHY_FUNC_LINK_RESET:
c63b88cc 1302 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
4ca7fe99 1303 msleep(HISI_SAS_DELAY_FOR_PHY_DISABLE);
c63b88cc 1304 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
e4189d53
JG		 1305 break;
1306
1307 case PHY_FUNC_DISABLE:
c63b88cc 1308 hisi_sas_phy_enable(hisi_hba, phy_no, 0);
046ab7d0 1309 goto out;
e4189d53
JG		 1310
1311 case PHY_FUNC_SET_LINK_RATE:
046ab7d0
XC		 1312 ret = hisi_sas_phy_set_linkrate(hisi_hba, phy_no, funcdata);
1313 break;
1314
c52108c6
XT		 1315 case PHY_FUNC_GET_EVENTS:
1316 if (hisi_hba->hw->get_events) {
1317 hisi_hba->hw->get_events(hisi_hba, phy_no);
046ab7d0 1318 goto out;
c52108c6 1319 }
df561f66 1320 fallthrough;
e4189d53
JG		 1321 case PHY_FUNC_RELEASE_SPINUP_HOLD:
1322 default:
046ab7d0
XC		 1323 ret = -EOPNOTSUPP;
1324 goto out;
e4189d53 1325 }
046ab7d0 1326
512623de
XC		 1327 if (sts && !wait_for_completion_timeout(&completion,
1328 HISI_SAS_WAIT_PHYUP_TIMEOUT)) {
046ab7d0
XC		 1329 dev_warn(dev, "phy%d wait phyup timed out for func %d\n",
1330 phy_no, func);
1331 if (phy->in_reset)
1332 ret = -ETIMEDOUT;
1333 }
1334
1335out:
1336 phy->reset_completion = NULL;
1337
20c63493 1338 up(&hisi_hba->sem);
046ab7d0 1339 return ret;
e4189d53 1340}
184a4635 1341
7c594f04
XC		 1342static void hisi_sas_fill_ata_reset_cmd(struct ata_device *dev,
1343 bool reset, int pmp, u8 *fis)
1344{
1345 struct ata_taskfile tf;
1346
1347 ata_tf_init(dev, &tf);
1348 if (reset)
1349 tf.ctl |= ATA_SRST;
1350 else
1351 tf.ctl &= ~ATA_SRST;
1352 tf.command = ATA_CMD_DEV_RESET;
1353 ata_tf_to_fis(&tf, pmp, 0, fis);
1354}
1355
1356static int hisi_sas_softreset_ata_disk(struct domain_device *device)
1357{
4ca7fe99 1358 u8 fis[FIS_BUF_SIZE] = {0};
7c594f04
XC		 1359 struct ata_port *ap = device->sata_dev.ap;
1360 struct ata_link *link;
1361 int rc = TMF_RESP_FUNC_FAILED;
1362 struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
11b75249 1363 struct device *dev = hisi_hba->dev;
7c594f04
XC		 1364
1365 ata_for_each_link(link, ap, EDGE) {
1366 int pmp = sata_srst_pmp(link);
1367
1368 hisi_sas_fill_ata_reset_cmd(link->device, 1, pmp, fis);
3f2e252e 1369 rc = sas_execute_ata_cmd(device, fis, -1);
7c594f04
XC		 1370 if (rc != TMF_RESP_FUNC_COMPLETE)
1371 break;
1372 }
1373
1374 if (rc == TMF_RESP_FUNC_COMPLETE) {
4ca7fe99 1375 usleep_range(DELAY_FOR_SOFTRESET_MIN, DELAY_FOR_SOFTRESET_MAX);
7c594f04
XC		 1376 ata_for_each_link(link, ap, EDGE) {
1377 int pmp = sata_srst_pmp(link);
1378
1379 hisi_sas_fill_ata_reset_cmd(link->device, 0, pmp, fis);
3f2e252e 1380 rc = sas_execute_ata_cmd(device, fis, -1);
7c594f04 1381 if (rc != TMF_RESP_FUNC_COMPLETE)
f4df167a
LJ		 1382 dev_err(dev, "ata disk %016llx de-reset failed\n",
1383 SAS_ADDR(device->sas_addr));
7c594f04
XC		 1384 }
1385 } else {
f4df167a
LJ		 1386 dev_err(dev, "ata disk %016llx reset failed\n",
1387 SAS_ADDR(device->sas_addr));
7c594f04
XC		 1388 }
1389
e85d93b2 1390 if (rc == TMF_RESP_FUNC_COMPLETE)
7c594f04 1391 hisi_sas_release_task(hisi_hba, device);
7c594f04
XC		 1392
1393 return rc;
1394}
1395
a669bdbf 1396static void hisi_sas_refresh_port_id(struct hisi_hba *hisi_hba)
917d3bda 1397{
a669bdbf 1398 u32 state = hisi_hba->hw->get_phys_state(hisi_hba);
917d3bda
XT		 1399 int i;
1400
1401 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
a669bdbf
XT		 1402 struct hisi_sas_device *sas_dev = &hisi_hba->devices[i];
1403 struct domain_device *device = sas_dev->sas_device;
1404 struct asd_sas_port *sas_port;
1405 struct hisi_sas_port *port;
1406 struct hisi_sas_phy *phy = NULL;
1407 struct asd_sas_phy *sas_phy;
1408
917d3bda 1409 if ((sas_dev->dev_type == SAS_PHY_UNUSED)
a669bdbf 1410 || !device || !device->port)
917d3bda
XT		 1411 continue;
1412
a669bdbf
XT		 1413 sas_port = device->port;
1414 port = to_hisi_sas_port(sas_port);
1415
29e2bac8 1416 spin_lock(&sas_port->phy_list_lock);
a669bdbf
XT		 1417 list_for_each_entry(sas_phy, &sas_port->phy_list, port_phy_el)
1418 if (state & BIT(sas_phy->id)) {
1419 phy = sas_phy->lldd_phy;
1420 break;
1421 }
29e2bac8 1422 spin_unlock(&sas_port->phy_list_lock);
a669bdbf
XT		 1423
1424 if (phy) {
1425 port->id = phy->port_id;
917d3bda 1426
a669bdbf
XT		 1427 /* Update linkrate of directly attached device. */
1428 if (!device->parent)
1429 device->linkrate = phy->sas_phy.linkrate;
917d3bda 1430
a669bdbf 1431 hisi_hba->hw->setup_itct(hisi_hba, sas_dev);
f58c8970 1432 } else if (!port->port_attached)
a669bdbf 1433 port->id = 0xff;
917d3bda
XT		 1434 }
1435}
1436
4bc05809 1437static void hisi_sas_rescan_topology(struct hisi_hba *hisi_hba, u32 state)
917d3bda 1438{
64359afb 1439 u32 new_state = hisi_hba->hw->get_phys_state(hisi_hba);
917d3bda
XT		 1440 struct asd_sas_port *_sas_port = NULL;
1441 int phy_no;
1442
1443 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1444 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
1445 struct asd_sas_phy *sas_phy = &phy->sas_phy;
1446 struct asd_sas_port *sas_port = sas_phy->port;
964231aa 1447 bool do_port_check = _sas_port != sas_port;
917d3bda
XT		 1448
1449 if (!sas_phy->phy->enabled)
1450 continue;
1451
1452 /* Report PHY state change to libsas */
64359afb 1453 if (new_state & BIT(phy_no)) {
a669bdbf 1454 if (do_port_check && sas_port && sas_port->port_dev) {
917d3bda
XT		 1455 struct domain_device *dev = sas_port->port_dev;
1456
1457 _sas_port = sas_port;
917d3bda 1458
924a3541 1459 if (dev_is_expander(dev->dev_type))
872a90b5 1460 sas_notify_port_event(sas_phy,
26c7efc3
AD		 1461 PORTE_BROADCAST_RCVD,
1462 GFP_KERNEL);
917d3bda 1463 }
447f78c0 1464 } else {
26c7efc3 1465 hisi_sas_phy_down(hisi_hba, phy_no, 0, GFP_KERNEL);
64359afb
YL		 1466
1467 /*
1468 * The new_state is not ready but old_state is ready,
1469 * the two possible causes:
1470 * 1. The connected device is removed
1471 * 2. Device exists but phyup timed out
1472 */
1473 if (state & BIT(phy_no))
1474 hisi_sas_notify_phy_event(phy,
1475 HISI_PHYE_LINK_RESET);
447f78c0 1476 }
917d3bda 1477 }
917d3bda
XT		 1478}
1479
6175abde
XT		 1480static void hisi_sas_reset_init_all_devices(struct hisi_hba *hisi_hba)
1481{
1482 struct hisi_sas_device *sas_dev;
1483 struct domain_device *device;
1484 int i;
1485
1486 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
1487 sas_dev = &hisi_hba->devices[i];
1488 device = sas_dev->sas_device;
1489
1490 if ((sas_dev->dev_type == SAS_PHY_UNUSED) || !device)
1491 continue;
1492
1493 hisi_sas_init_device(device);
1494 }
1495}
1496
31709548
XT		 1497static void hisi_sas_send_ata_reset_each_phy(struct hisi_hba *hisi_hba,
1498 struct asd_sas_port *sas_port,
1499 struct domain_device *device)
1500{
31709548
XT		 1501 struct ata_port *ap = device->sata_dev.ap;
1502 struct device *dev = hisi_hba->dev;
31709548 1503 int rc = TMF_RESP_FUNC_FAILED;
31709548 1504 struct ata_link *link;
4ca7fe99 1505 u8 fis[FIS_BUF_SIZE] = {0};
29e2bac8 1506 int i;
31709548 1507
29e2bac8 1508 for (i = 0; i < hisi_hba->n_phy; i++) {
29e2bac8
XC		 1509 if (!(sas_port->phy_mask & BIT(i)))
1510 continue;
31709548
XT		 1511
1512 ata_for_each_link(link, ap, EDGE) {
1513 int pmp = sata_srst_pmp(link);
1514
31709548 1515 hisi_sas_fill_ata_reset_cmd(link->device, 1, pmp, fis);
3f2e252e 1516 rc = sas_execute_ata_cmd(device, fis, i);
31709548
XT		 1517 if (rc != TMF_RESP_FUNC_COMPLETE) {
1518 dev_err(dev, "phy%d ata reset failed rc=%d\n",
29e2bac8 1519 i, rc);
31709548
XT		 1520 break;
1521 }
1522 }
1523 }
1524}
1525
1526static void hisi_sas_terminate_stp_reject(struct hisi_hba *hisi_hba)
1527{
1528 struct device *dev = hisi_hba->dev;
1529 int port_no, rc, i;
1530
1531 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
1532 struct hisi_sas_device *sas_dev = &hisi_hba->devices[i];
1533 struct domain_device *device = sas_dev->sas_device;
1534
1535 if ((sas_dev->dev_type == SAS_PHY_UNUSED) || !device)
1536 continue;
1537
095478a6 1538 rc = hisi_sas_internal_task_abort_dev(sas_dev, false);
31709548
XT		 1539 if (rc < 0)
1540 dev_err(dev, "STP reject: abort dev failed %d\n", rc);
1541 }
1542
1543 for (port_no = 0; port_no < hisi_hba->n_phy; port_no++) {
1544 struct hisi_sas_port *port = &hisi_hba->port[port_no];
1545 struct asd_sas_port *sas_port = &port->sas_port;
1546 struct domain_device *port_dev = sas_port->port_dev;
1547 struct domain_device *device;
1548
924a3541 1549 if (!port_dev || !dev_is_expander(port_dev->dev_type))
31709548
XT		 1550 continue;
1551
1552 /* Try to find a SATA device */
1553 list_for_each_entry(device, &sas_port->dev_list,
1554 dev_list_node) {
1555 if (dev_is_sata(device)) {
1556 hisi_sas_send_ata_reset_each_phy(hisi_hba,
1557 sas_port,
1558 device);
1559 break;
1560 }
1561 }
1562 }
1563}
1564
4522204a 1565void hisi_sas_controller_reset_prepare(struct hisi_hba *hisi_hba)
06ec0fb9 1566{
917d3bda 1567 struct Scsi_Host *shost = hisi_hba->shost;
06ec0fb9 1568
4522204a 1569 hisi_hba->phy_state = hisi_hba->hw->get_phys_state(hisi_hba);
06ec0fb9 1570
917d3bda 1571 scsi_block_requests(shost);
4ca7fe99
YL		 1572 hisi_hba->hw->wait_cmds_complete_timeout(hisi_hba,
1573 WAIT_CMD_COMPLETE_DELAY,
1574 WAIT_CMD_COMPLETE_TMROUT);
a865ae14 1575
f9242f16
XC		 1576 /*
1577 * hisi_hba->timer is only used for v1/v2 hw, and check hw->sht
1578 * which is also only used for v1/v2 hw to skip it for v3 hw
1579 */
1580 if (hisi_hba->hw->sht)
8fa7292f 1581 timer_delete_sync(&hisi_hba->timer);
6f7c32d6 1582
917d3bda 1583 set_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
4522204a
XT		 1584}
1585EXPORT_SYMBOL_GPL(hisi_sas_controller_reset_prepare);
1586
89954f02
YL		 1587static void hisi_sas_async_init_wait_phyup(void *data, async_cookie_t cookie)
1588{
1589 struct hisi_sas_phy *phy = data;
1590 struct hisi_hba *hisi_hba = phy->hisi_hba;
1591 struct device *dev = hisi_hba->dev;
1592 DECLARE_COMPLETION_ONSTACK(completion);
1593 int phy_no = phy->sas_phy.id;
1594
1595 phy->reset_completion = &completion;
1596 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
1597 if (!wait_for_completion_timeout(&completion,
1598 HISI_SAS_WAIT_PHYUP_TIMEOUT))
1599 dev_warn(dev, "phy%d wait phyup timed out\n", phy_no);
1600
1601 phy->reset_completion = NULL;
1602}
1603
4522204a
XT		 1604void hisi_sas_controller_reset_done(struct hisi_hba *hisi_hba)
1605{
1606 struct Scsi_Host *shost = hisi_hba->shost;
89954f02
YL		 1607 ASYNC_DOMAIN_EXCLUSIVE(async);
1608 int phy_no;
917d3bda 1609
917d3bda 1610 /* Init and wait for PHYs to come up and all libsas event finished. */
89954f02
YL		 1611 for (phy_no = 0; phy_no < hisi_hba->n_phy; phy_no++) {
1612 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
08a07dc7 1613 struct asd_sas_phy *sas_phy = &phy->sas_phy;
89954f02 1614
08a07dc7 1615 if (!sas_phy->phy->enabled)
89954f02
YL		 1616 continue;
1617
08a07dc7
YL		 1618 if (!(hisi_hba->phy_state & BIT(phy_no))) {
1619 hisi_sas_phy_enable(hisi_hba, phy_no, 1);
1620 continue;
1621 }
1622
89954f02
YL		 1623 async_schedule_domain(hisi_sas_async_init_wait_phyup,
1624 phy, &async);
1625 }
1626
1627 async_synchronize_full_domain(&async);
a669bdbf 1628 hisi_sas_refresh_port_id(hisi_hba);
214e702d 1629 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
31709548
XT		 1630
1631 if (hisi_hba->reject_stp_links_msk)
1632 hisi_sas_terminate_stp_reject(hisi_hba);
6175abde 1633 hisi_sas_reset_init_all_devices(hisi_hba);
fb51e7a8 1634 scsi_unblock_requests(shost);
b5a9fa20 1635 clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
16775db6 1636 up(&hisi_hba->sem);
917d3bda 1637
69f4ec1e 1638 hisi_sas_rescan_topology(hisi_hba, hisi_hba->phy_state);
4522204a
XT		 1639}
1640EXPORT_SYMBOL_GPL(hisi_sas_controller_reset_done);
1641
2c74cb1f 1642static int hisi_sas_controller_prereset(struct hisi_hba *hisi_hba)
4522204a 1643{
4522204a 1644 if (!hisi_hba->hw->soft_reset)
d34ee535 1645 return -ENOENT;
4522204a 1646
16775db6
QL		 1647 down(&hisi_hba->sem);
1648 if (test_and_set_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags)) {
1649 up(&hisi_hba->sem);
d34ee535 1650 return -EPERM;
16775db6 1651 }
4522204a 1652
3f030550 1653 if (hisi_sas_debugfs_enable)
2c74cb1f
JX		 1654 hisi_hba->hw->debugfs_snapshot_regs(hisi_hba);
1655
1656 return 0;
1657}
1658
1659static int hisi_sas_controller_reset(struct hisi_hba *hisi_hba)
1660{
1661 struct device *dev = hisi_hba->dev;
1662 struct Scsi_Host *shost = hisi_hba->shost;
1663 int rc;
1664
4522204a
XT		 1665 dev_info(dev, "controller resetting...\n");
1666 hisi_sas_controller_reset_prepare(hisi_hba);
1667
1668 rc = hisi_hba->hw->soft_reset(hisi_hba);
1669 if (rc) {
1670 dev_warn(dev, "controller reset failed (%d)\n", rc);
1671 clear_bit(HISI_SAS_REJECT_CMD_BIT, &hisi_hba->flags);
1672 up(&hisi_hba->sem);
1673 scsi_unblock_requests(shost);
b5a9fa20 1674 clear_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags);
4522204a
XT		 1675 return rc;
1676 }
bc555115 1677 clear_bit(HISI_SAS_HW_FAULT_BIT, &hisi_hba->flags);
4522204a
XT		 1678
1679 hisi_sas_controller_reset_done(hisi_hba);
fb51e7a8 1680 dev_info(dev, "controller reset complete\n");
06ec0fb9 1681
214e702d 1682 return 0;
06ec0fb9
XC		 1683}
1684
0efff300
JG		 1685static int hisi_sas_abort_task(struct sas_task *task)
1686{
095478a6 1687 struct hisi_sas_internal_abort_data internal_abort_data = { false };
0efff300
JG		 1688 struct domain_device *device = task->dev;
1689 struct hisi_sas_device *sas_dev = device->lldd_dev;
4b329abc 1690 struct hisi_sas_slot *slot = task->lldd_task;
c6ef8954
XC		 1691 struct hisi_hba *hisi_hba;
1692 struct device *dev;
0efff300
JG		 1693 int rc = TMF_RESP_FUNC_FAILED;
1694 unsigned long flags;
1695
c6ef8954 1696 if (!sas_dev)
0efff300 1697 return TMF_RESP_FUNC_FAILED;
c6ef8954
XC		 1698
1699 hisi_hba = dev_to_hisi_hba(task->dev);
1700 dev = hisi_hba->dev;
0efff300 1701
b81b6cce 1702 spin_lock_irqsave(&task->task_state_lock, flags);
0efff300 1703 if (task->task_state_flags & SAS_TASK_STATE_DONE) {
584f53fe
XC		 1704 struct hisi_sas_cq *cq;
1705
1706 if (slot) {
1707 /*
b711ef5e 1708 * sync irq or poll queue to avoid free'ing task
584f53fe
XC		 1709 * before using task in IO completion
1710 */
1711 cq = &hisi_hba->cq[slot->dlvry_queue];
b711ef5e 1712 hisi_sas_sync_cq(cq);
584f53fe 1713 }
b81b6cce 1714 spin_unlock_irqrestore(&task->task_state_lock, flags);
0efff300
JG		 1715 rc = TMF_RESP_FUNC_COMPLETE;
1716 goto out;
1717 }
b81b6cce
XC		 1718 task->task_state_flags |= SAS_TASK_STATE_ABORTED;
1719 spin_unlock_irqrestore(&task->task_state_lock, flags);
0efff300 1720
8dd10296
YL		 1721 if (!slot)
1722 goto out;
1723
1724 if (task->task_proto & SAS_PROTOCOL_SSP) {
735bcc77 1725 u16 tag = slot->idx;
c35279f2 1726 int rc2;
0efff300 1727
4fea759e 1728 rc = sas_abort_task(task, tag);
095478a6
JG		 1729 rc2 = sas_execute_internal_abort_single(device, tag,
1730 slot->dlvry_queue, &internal_abort_data);
813709f2
XT		 1731 if (rc2 < 0) {
1732 dev_err(dev, "abort task: internal abort (%d)\n", rc2);
1733 return TMF_RESP_FUNC_FAILED;
1734 }
1735
c35279f2
JG		 1736 /*
1737 * If the TMF finds that the IO is not in the device and also
1738 * the internal abort does not succeed, then it is safe to
1739 * free the slot.
1740 * Note: if the internal abort succeeds then the slot
1741 * will have already been completed
1742 */
1743 if (rc == TMF_RESP_FUNC_COMPLETE && rc2 != TMF_RESP_FUNC_SUCC) {
e85d93b2 1744 if (task->lldd_task)
71fb36b5 1745 hisi_sas_do_release_task(hisi_hba, task, slot, true);
0efff300 1746 }
0efff300
JG		 1747 } else if (task->task_proto & SAS_PROTOCOL_SATA ||
1748 task->task_proto & SAS_PROTOCOL_STP) {
1749 if (task->dev->dev_type == SAS_SATA_DEV) {
930d97da
XY		 1750 struct ata_queued_cmd *qc = task->uldd_task;
1751
095478a6 1752 rc = hisi_sas_internal_task_abort_dev(sas_dev, false);
813709f2
XT		 1753 if (rc < 0) {
1754 dev_err(dev, "abort task: internal abort failed\n");
1755 goto out;
1756 }
d30ff263 1757 hisi_sas_dereg_device(hisi_hba, device);
930d97da
XY		 1758
1759 /*
1760 * If an ATA internal command times out in ATA EH, it
1761 * need to execute soft reset, so check the scsicmd
1762 */
1763 if ((sas_dev->dev_status == HISI_SAS_DEV_NCQ_ERR) &&
1764 qc && qc->scsicmd) {
71fb36b5 1765 hisi_sas_do_release_task(hisi_hba, task, slot, true);
930d97da
XY		 1766 rc = TMF_RESP_FUNC_COMPLETE;
1767 } else {
1768 rc = hisi_sas_softreset_ata_disk(device);
1769 }
0efff300 1770 }
8dd10296 1771 } else if (task->task_proto & SAS_PROTOCOL_SMP) {
dc8a49ca 1772 /* SMP */
dc8a49ca 1773 u32 tag = slot->idx;
584f53fe 1774 struct hisi_sas_cq *cq = &hisi_hba->cq[slot->dlvry_queue];
0efff300 1775
095478a6
JG		 1776 rc = sas_execute_internal_abort_single(device,
1777 tag, slot->dlvry_queue,
1778 &internal_abort_data);
813709f2 1779 if (((rc < 0) || (rc == TMF_RESP_FUNC_FAILED)) &&
584f53fe
XC		 1780 task->lldd_task) {
1781 /*
b711ef5e 1782 * sync irq or poll queue to avoid free'ing task
584f53fe
XC		 1783 * before using task in IO completion
1784 */
b711ef5e 1785 hisi_sas_sync_cq(cq);
584f53fe
XC		 1786 slot->task = NULL;
1787 }
0efff300
JG		 1788 }
1789
1790out:
1791 if (rc != TMF_RESP_FUNC_COMPLETE)
1792 dev_notice(dev, "abort task: rc=%d\n", rc);
1793 return rc;
1794}
1795
1796static int hisi_sas_abort_task_set(struct domain_device *device, u8 *lun)
1797{
095478a6 1798 struct hisi_sas_device *sas_dev = device->lldd_dev;
2a038131
XT		 1799 struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
1800 struct device *dev = hisi_hba->dev;
01d4e3a2 1801 int rc;
2a038131 1802
095478a6 1803 rc = hisi_sas_internal_task_abort_dev(sas_dev, false);
2a038131
XT		 1804 if (rc < 0) {
1805 dev_err(dev, "abort task set: internal abort rc=%d\n", rc);
1806 return TMF_RESP_FUNC_FAILED;
1807 }
1808 hisi_sas_dereg_device(hisi_hba, device);
0efff300 1809
69b80a0e 1810 rc = sas_abort_task_set(device, lun);
e85d93b2 1811 if (rc == TMF_RESP_FUNC_COMPLETE)
2a038131 1812 hisi_sas_release_task(hisi_hba, device);
2a038131 1813
0efff300
JG		 1814 return rc;
1815}
1816
0efff300
JG		 1817static int hisi_sas_debug_I_T_nexus_reset(struct domain_device *device)
1818{
3e1fb1b8 1819 struct sas_phy *local_phy = sas_get_local_phy(device);
57dbb2b2 1820 struct hisi_sas_device *sas_dev = device->lldd_dev;
3e1fb1b8
XC		 1821 struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
1822 struct sas_ha_struct *sas_ha = &hisi_hba->sha;
57dbb2b2 1823 int rc, reset_type;
3e1fb1b8 1824
c2bae4f7
LJ		 1825 if (!local_phy->enabled) {
1826 sas_put_local_phy(local_phy);
1827 return -ENODEV;
1828 }
1829
3e1fb1b8 1830 if (scsi_is_sas_phy_local(local_phy)) {
445ee2de
LJ		 1831 struct asd_sas_phy *sas_phy =
1832 sas_ha->sas_phy[local_phy->number];
1833 struct hisi_sas_phy *phy =
1834 container_of(sas_phy, struct hisi_sas_phy, sas_phy);
046ab7d0
XC		 1835 unsigned long flags;
1836
1837 spin_lock_irqsave(&phy->lock, flags);
3e1fb1b8 1838 phy->in_reset = 1;
046ab7d0 1839 spin_unlock_irqrestore(&phy->lock, flags);
3e1fb1b8
XC		 1840 }
1841
57dbb2b2 1842 reset_type = (sas_dev->dev_status == HISI_SAS_DEV_INIT ||
af01b2b9 1843 !dev_is_sata(device)) ? true : false;
57dbb2b2 1844
3e1fb1b8
XC		 1845 rc = sas_phy_reset(local_phy, reset_type);
1846 sas_put_local_phy(local_phy);
1847
1848 if (scsi_is_sas_phy_local(local_phy)) {
445ee2de
LJ		 1849 struct asd_sas_phy *sas_phy =
1850 sas_ha->sas_phy[local_phy->number];
1851 struct hisi_sas_phy *phy =
1852 container_of(sas_phy, struct hisi_sas_phy, sas_phy);
3e1fb1b8
XC		 1853 unsigned long flags;
1854
1855 spin_lock_irqsave(&phy->lock, flags);
3e1fb1b8
XC		 1856 phy->in_reset = 0;
1857 spin_unlock_irqrestore(&phy->lock, flags);
1858
1859 /* report PHY down if timed out */
046ab7d0 1860 if (rc == -ETIMEDOUT)
26c7efc3 1861 hisi_sas_phy_down(hisi_hba, sas_phy->id, 0, GFP_KERNEL);
71453bd9
JG		 1862 return rc;
1863 }
1864
3c2673a0 1865 /* Remote phy */
71453bd9
JG		 1866 if (rc)
1867 return rc;
1868
71453bd9 1869 if (dev_is_sata(device)) {
3c2673a0
JZ		 1870 struct ata_link *link = &device->sata_dev.ap->link;
1871
0098c55e 1872 rc = ata_wait_after_reset(link, jiffies + HISI_SAS_WAIT_PHYUP_TIMEOUT,
3c2673a0 1873 smp_ata_check_ready_type);
71453bd9 1874 } else {
4ca7fe99 1875 msleep(DELAY_FOR_LINK_READY);
57dbb2b2 1876 }
3e1fb1b8 1877
0efff300
JG		 1878 return rc;
1879}
1880
1881static int hisi_sas_I_T_nexus_reset(struct domain_device *device)
1882{
095478a6 1883 struct hisi_sas_device *sas_dev = device->lldd_dev;
0efff300 1884 struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
813709f2 1885 struct device *dev = hisi_hba->dev;
4a8bec88 1886 int rc;
0efff300 1887
930d97da
XY		 1888 if (sas_dev->dev_status == HISI_SAS_DEV_NCQ_ERR)
1889 sas_dev->dev_status = HISI_SAS_DEV_NORMAL;
1890
095478a6 1891 rc = hisi_sas_internal_task_abort_dev(sas_dev, false);
813709f2
XT		 1892 if (rc < 0) {
1893 dev_err(dev, "I_T nexus reset: internal abort (%d)\n", rc);
1894 return TMF_RESP_FUNC_FAILED;
1895 }
d30ff263
XC		 1896 hisi_sas_dereg_device(hisi_hba, device);
1897
e4d953ca 1898 if (dev_is_sata(device)) {
0e83fc61 1899 rc = hisi_sas_softreset_ata_disk(device);
e4d953ca
YL		 1900 if (rc == TMF_RESP_FUNC_FAILED)
1901 dev_err(dev, "ata disk %016llx reset (%d)\n",
1902 SAS_ADDR(device->sas_addr), rc);
0e83fc61
LJ		 1903 }
1904
e4d953ca 1905 rc = hisi_sas_debug_I_T_nexus_reset(device);
e85d93b2 1906 if ((rc == TMF_RESP_FUNC_COMPLETE) || (rc == -ENODEV))
6131243a 1907 hisi_sas_release_task(hisi_hba, device);
e85d93b2 1908
6131243a 1909 return rc;
0efff300
JG		 1910}
1911
1912static int hisi_sas_lu_reset(struct domain_device *device, u8 *lun)
1913{
0efff300
JG		 1914 struct hisi_sas_device *sas_dev = device->lldd_dev;
1915 struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
11b75249 1916 struct device *dev = hisi_hba->dev;
0efff300
JG		 1917 int rc = TMF_RESP_FUNC_FAILED;
1918
a5ac1f5d 1919 /* Clear internal IO and then lu reset */
095478a6 1920 rc = hisi_sas_internal_task_abort_dev(sas_dev, false);
a5ac1f5d
LJ		 1921 if (rc < 0) {
1922 dev_err(dev, "lu_reset: internal abort failed\n");
1923 goto out;
1924 }
1925 hisi_sas_dereg_device(hisi_hba, device);
1926
055945df 1927 if (dev_is_sata(device)) {
92c8fe15 1928 struct sas_phy *phy = sas_get_local_phy(device);
055945df 1929
af01b2b9 1930 rc = sas_phy_reset(phy, true);
e85d93b2 1931 if (rc == 0)
055945df 1932 hisi_sas_release_task(hisi_hba, device);
055945df
JG		 1933 sas_put_local_phy(phy);
1934 } else {
29d77690 1935 rc = sas_lu_reset(device, lun);
e85d93b2 1936 if (rc == TMF_RESP_FUNC_COMPLETE)
055945df 1937 hisi_sas_release_task(hisi_hba, device);
055945df
JG		 1938 }
1939out:
14d3f397 1940 if (rc != TMF_RESP_FUNC_COMPLETE)
ad604832 1941 dev_err(dev, "lu_reset: for device[%d]:rc= %d\n",
14d3f397 1942 sas_dev->device_id, rc);
0efff300
JG		 1943 return rc;
1944}
1945
0f757339
LJ		 1946static void hisi_sas_async_I_T_nexus_reset(void *data, async_cookie_t cookie)
1947{
1948 struct domain_device *device = data;
1949 struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
1950 int rc;
1951
1952 rc = hisi_sas_debug_I_T_nexus_reset(device);
1953 if (rc != TMF_RESP_FUNC_COMPLETE)
1954 dev_info(hisi_hba->dev, "I_T_nexus reset fail for dev:%016llx rc=%d\n",
1955 SAS_ADDR(device->sas_addr), rc);
1956}
1957
8b05ad6a
JG		 1958static int hisi_sas_clear_nexus_ha(struct sas_ha_struct *sas_ha)
1959{
1960 struct hisi_hba *hisi_hba = sas_ha->lldd_ha;
e402acdb 1961 HISI_SAS_DECLARE_RST_WORK_ON_STACK(r);
0f757339 1962 ASYNC_DOMAIN_EXCLUSIVE(async);
94a3555d 1963 int i;
8b05ad6a 1964
e402acdb
XT		 1965 queue_work(hisi_hba->wq, &r.work);
1966 wait_for_completion(r.completion);
94a3555d
JZ		 1967 if (!r.done)
1968 return TMF_RESP_FUNC_FAILED;
f2ae8d04
XT		 1969
1970 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
1971 struct hisi_sas_device *sas_dev = &hisi_hba->devices[i];
1972 struct domain_device *device = sas_dev->sas_device;
1973
1974 if ((sas_dev->dev_type == SAS_PHY_UNUSED) || !device ||
924a3541 1975 dev_is_expander(device->dev_type))
f2ae8d04
XT		 1976 continue;
1977
0f757339
LJ		 1978 async_schedule_domain(hisi_sas_async_I_T_nexus_reset,
1979 device, &async);
f2ae8d04
XT		 1980 }
1981
0f757339 1982 async_synchronize_full_domain(&async);
f2ae8d04 1983 hisi_sas_release_tasks(hisi_hba);
e402acdb 1984
94a3555d 1985 return TMF_RESP_FUNC_COMPLETE;
8b05ad6a
JG		 1986}
1987
0efff300
JG		 1988static int hisi_sas_query_task(struct sas_task *task)
1989{
0efff300
JG		 1990 int rc = TMF_RESP_FUNC_FAILED;
1991
1992 if (task->lldd_task && task->task_proto & SAS_PROTOCOL_SSP) {
0efff300
JG		 1993 struct hisi_sas_slot *slot = task->lldd_task;
1994 u32 tag = slot->idx;
1995
72f8810e 1996 rc = sas_query_task(task, tag);
0efff300
JG		 1997 switch (rc) {
1998 /* The task is still in Lun, release it then */
1999 case TMF_RESP_FUNC_SUCC:
2000 /* The task is not in Lun or failed, reset the phy */
2001 case TMF_RESP_FUNC_FAILED:
2002 case TMF_RESP_FUNC_COMPLETE:
2003 break;
997ee43c
XC		 2004 default:
2005 rc = TMF_RESP_FUNC_FAILED;
2006 break;
0efff300
JG		 2007 }
2008 }
2009 return rc;
2010}
2011
095478a6
JG		 2012static bool hisi_sas_internal_abort_timeout(struct sas_task *task,
2013 void *data)
441c2740
JG		 2014{
2015 struct domain_device *device = task->dev;
095478a6
JG		 2016 struct hisi_hba *hisi_hba = dev_to_hisi_hba(device);
2017 struct hisi_sas_internal_abort_data *timeout = data;
441c2740 2018
3f030550 2019 if (hisi_sas_debugfs_enable) {
3c4f53b2
YL		 2020 /*
2021 * If timeout occurs in device gone scenario, to avoid
2022 * circular dependency like:
2023 * hisi_sas_dev_gone() -> down() -> ... ->
2024 * hisi_sas_internal_abort_timeout() -> down().
2025 */
2026 if (!timeout->rst_ha_timeout)
2027 down(&hisi_hba->sem);
2ff07b5c 2028 hisi_hba->hw->debugfs_snapshot_regs(hisi_hba);
3c4f53b2
YL		 2029 if (!timeout->rst_ha_timeout)
2030 up(&hisi_hba->sem);
2ff07b5c 2031 }
c35279f2 2032
095478a6
JG		 2033 if (task->task_state_flags & SAS_TASK_STATE_DONE) {
2034 pr_err("Internal abort: timeout %016llx\n",
2035 SAS_ADDR(device->sas_addr));
2036 } else {
2037 struct hisi_sas_slot *slot = task->lldd_task;
441c2740 2038
095478a6 2039 set_bit(HISI_SAS_HW_FAULT_BIT, &hisi_hba->flags);
441c2740 2040
095478a6
JG		 2041 if (slot) {
2042 struct hisi_sas_cq *cq =
2043 &hisi_hba->cq[slot->dlvry_queue];
2044 /*
b711ef5e 2045 * sync irq or poll queue to avoid free'ing task
095478a6
JG		 2046 * before using task in IO completion
2047 */
b711ef5e 2048 hisi_sas_sync_cq(cq);
095478a6
JG		 2049 slot->task = NULL;
2050 }
795f25a3 2051
095478a6
JG		 2052 if (timeout->rst_ha_timeout) {
2053 pr_err("Internal abort: timeout and not done %016llx. Queuing reset.\n",
2054 SAS_ADDR(device->sas_addr));
2055 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2056 } else {
2057 pr_err("Internal abort: timeout and not done %016llx.\n",
2058 SAS_ADDR(device->sas_addr));
795f25a3 2059 }
095478a6
JG		 2060
2061 return true;
795f25a3
JG		 2062 }
2063
095478a6 2064 return false;
795f25a3
JG		 2065}
2066
184a4635
JG		 2067static void hisi_sas_port_formed(struct asd_sas_phy *sas_phy)
2068{
2069 hisi_sas_port_notify_formed(sas_phy);
2070}
2071
6379c560
XT		 2072static int hisi_sas_write_gpio(struct sas_ha_struct *sha, u8 reg_type,
2073 u8 reg_index, u8 reg_count, u8 *write_data)
2074{
2075 struct hisi_hba *hisi_hba = sha->lldd_ha;
2076
2077 if (!hisi_hba->hw->write_gpio)
2078 return -EOPNOTSUPP;
2079
2080 return hisi_hba->hw->write_gpio(hisi_hba, reg_type,
2081 reg_index, reg_count, write_data);
2082}
2083
184a4635
JG		 2084static void hisi_sas_phy_disconnected(struct hisi_sas_phy *phy)
2085{
efdcad62
JG		 2086 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2087 struct sas_phy *sphy = sas_phy->phy;
c63b88cc 2088 unsigned long flags;
efdcad62 2089
184a4635
JG		 2090 phy->phy_attached = 0;
2091 phy->phy_type = 0;
2092 phy->port = NULL;
efdcad62 2093
c63b88cc
JG		 2094 spin_lock_irqsave(&phy->lock, flags);
2095 if (phy->enable)
efdcad62
JG		 2096 sphy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN;
2097 else
2098 sphy->negotiated_linkrate = SAS_PHY_DISABLED;
c63b88cc 2099 spin_unlock_irqrestore(&phy->lock, flags);
184a4635
JG		 2100}
2101
26c7efc3
AD		 2102void hisi_sas_phy_down(struct hisi_hba *hisi_hba, int phy_no, int rdy,
2103 gfp_t gfp_flags)
184a4635
JG		 2104{
2105 struct hisi_sas_phy *phy = &hisi_hba->phy[phy_no];
2106 struct asd_sas_phy *sas_phy = &phy->sas_phy;
3e1fb1b8 2107 struct device *dev = hisi_hba->dev;
184a4635
JG		 2108
2109 if (rdy) {
2110 /* Phy down but ready */
26c7efc3 2111 hisi_sas_bytes_dmaed(hisi_hba, phy_no, gfp_flags);
184a4635
JG		 2112 hisi_sas_port_notify_formed(sas_phy);
2113 } else {
92c8fe15 2114 struct hisi_sas_port *port = phy->port;
184a4635 2115
b5a9fa20 2116 if (test_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags) ||
ed99e1d9 2117 phy->in_reset) {
3e1fb1b8
XC		 2118 dev_info(dev, "ignore flutter phy%d down\n", phy_no);
2119 return;
2120 }
184a4635 2121 /* Phy down and not ready */
872a90b5 2122 sas_notify_phy_event(sas_phy, PHYE_LOSS_OF_SIGNAL, gfp_flags);
184a4635
JG		 2123 sas_phy_disconnected(sas_phy);
2124
2125 if (port) {
2126 if (phy->phy_type & PORT_TYPE_SAS) {
2127 int port_id = port->id;
2128
2129 if (!hisi_hba->hw->get_wideport_bitmap(hisi_hba,
2130 port_id))
2131 port->port_attached = 0;
2132 } else if (phy->phy_type & PORT_TYPE_SATA)
2133 port->port_attached = 0;
2134 }
2135 hisi_sas_phy_disconnected(phy);
2136 }
2137}
2138EXPORT_SYMBOL_GPL(hisi_sas_phy_down);
2139
e9b6bada
JG		 2140void hisi_sas_phy_bcast(struct hisi_sas_phy *phy)
2141{
2142 struct asd_sas_phy *sas_phy = &phy->sas_phy;
2143 struct hisi_hba *hisi_hba = phy->hisi_hba;
2144
2145 if (test_bit(HISI_SAS_RESETTING_BIT, &hisi_hba->flags))
2146 return;
2147
2148 sas_notify_port_event(sas_phy, PORTE_BROADCAST_RCVD, GFP_ATOMIC);
2149}
2150EXPORT_SYMBOL_GPL(hisi_sas_phy_bcast);
2151
a97fa586
XC		 2152int hisi_sas_host_reset(struct Scsi_Host *shost, int reset_type)
2153{
2154 struct hisi_hba *hisi_hba = shost_priv(shost);
2155
2156 if (reset_type != SCSI_ADAPTER_RESET)
2157 return -EOPNOTSUPP;
2158
2159 queue_work(hisi_hba->wq, &hisi_hba->rst_work);
2160
2161 return 0;
2162}
2163EXPORT_SYMBOL_GPL(hisi_sas_host_reset);
2164
e21fe3a5
JG		 2165struct scsi_transport_template *hisi_sas_stt;
2166EXPORT_SYMBOL_GPL(hisi_sas_stt);
e8899fad
JG		 2167
2168static struct sas_domain_function_template hisi_sas_transport_ops = {
abda97c2
JG		 2169 .lldd_dev_found = hisi_sas_dev_found,
2170 .lldd_dev_gone = hisi_sas_dev_gone,
42e7a693 2171 .lldd_execute_task = hisi_sas_queue_command,
e4189d53 2172 .lldd_control_phy = hisi_sas_control_phy,
0efff300
JG		 2173 .lldd_abort_task = hisi_sas_abort_task,
2174 .lldd_abort_task_set = hisi_sas_abort_task_set,
0efff300
JG		 2175 .lldd_I_T_nexus_reset = hisi_sas_I_T_nexus_reset,
2176 .lldd_lu_reset = hisi_sas_lu_reset,
2177 .lldd_query_task = hisi_sas_query_task,
640208a1 2178 .lldd_clear_nexus_ha = hisi_sas_clear_nexus_ha,
184a4635 2179 .lldd_port_formed = hisi_sas_port_formed,
640208a1 2180 .lldd_write_gpio = hisi_sas_write_gpio,
693e66a0 2181 .lldd_tmf_aborted = hisi_sas_tmf_aborted,
095478a6 2182 .lldd_abort_timeout = hisi_sas_internal_abort_timeout,
e8899fad
JG		 2183};
2184
06ec0fb9
XC		 2185void hisi_sas_init_mem(struct hisi_hba *hisi_hba)
2186{
93352abc 2187 int i, s, j, max_command_entries = HISI_SAS_MAX_COMMANDS;
26889e5e 2188 struct hisi_sas_breakpoint *sata_breakpoint = hisi_hba->sata_breakpoint;
06ec0fb9
XC		 2189
2190 for (i = 0; i < hisi_hba->queue_count; i++) {
2191 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
2192 struct hisi_sas_dq *dq = &hisi_hba->dq[i];
26889e5e
JG		 2193 struct hisi_sas_cmd_hdr *cmd_hdr = hisi_hba->cmd_hdr[i];
2194
2195 s = sizeof(struct hisi_sas_cmd_hdr);
2196 for (j = 0; j < HISI_SAS_QUEUE_SLOTS; j++)
2197 memset(&cmd_hdr[j], 0, s);
06ec0fb9 2198
06ec0fb9
XC		 2199 dq->wr_point = 0;
2200
2201 s = hisi_hba->hw->complete_hdr_size * HISI_SAS_QUEUE_SLOTS;
2202 memset(hisi_hba->complete_hdr[i], 0, s);
2203 cq->rd_point = 0;
2204 }
2205
2206 s = sizeof(struct hisi_sas_initial_fis) * hisi_hba->n_phy;
2207 memset(hisi_hba->initial_fis, 0, s);
2208
2209 s = max_command_entries * sizeof(struct hisi_sas_iost);
2210 memset(hisi_hba->iost, 0, s);
2211
2212 s = max_command_entries * sizeof(struct hisi_sas_breakpoint);
2213 memset(hisi_hba->breakpoint, 0, s);
2214
26889e5e
JG		 2215 s = sizeof(struct hisi_sas_sata_breakpoint);
2216 for (j = 0; j < HISI_SAS_MAX_ITCT_ENTRIES; j++)
2217 memset(&sata_breakpoint[j], 0, s);
06ec0fb9
XC		 2218}
2219EXPORT_SYMBOL_GPL(hisi_sas_init_mem);
2220
ae68b566 2221int hisi_sas_alloc(struct hisi_hba *hisi_hba)
6be6de18 2222{
11b75249 2223 struct device *dev = hisi_hba->dev;
93352abc 2224 int i, j, s, max_command_entries = HISI_SAS_MAX_COMMANDS;
2ba5afb6
XC		 2225 int max_command_entries_ru, sz_slot_buf_ru;
2226 int blk_cnt, slots_per_blk;
6be6de18 2227
d2fc401e 2228 sema_init(&hisi_hba->sem, 1);
fa42d80d 2229 spin_lock_init(&hisi_hba->lock);
976867e6
JG		 2230 for (i = 0; i < hisi_hba->n_phy; i++) {
2231 hisi_sas_phy_init(hisi_hba, i);
2232 hisi_hba->port[i].port_attached = 0;
2233 hisi_hba->port[i].id = -1;
976867e6
JG		 2234 }
2235
af740dbe
JG		 2236 for (i = 0; i < HISI_SAS_MAX_DEVICES; i++) {
2237 hisi_hba->devices[i].dev_type = SAS_PHY_UNUSED;
2238 hisi_hba->devices[i].device_id = i;
57dbb2b2 2239 hisi_hba->devices[i].dev_status = HISI_SAS_DEV_INIT;
af740dbe
JG		 2240 }
2241
6be6de18 2242 for (i = 0; i < hisi_hba->queue_count; i++) {
9101a079 2243 struct hisi_sas_cq *cq = &hisi_hba->cq[i];
4fde02ad 2244 struct hisi_sas_dq *dq = &hisi_hba->dq[i];
9101a079
JG		 2245
2246 /* Completion queue structure */
2247 cq->id = i;
2248 cq->hisi_hba = hisi_hba;
0e47effa 2249 spin_lock_init(&cq->poll_lock);
9101a079 2250
4fde02ad 2251 /* Delivery queue structure */
39bade0c 2252 spin_lock_init(&dq->lock);
fa222db0 2253 INIT_LIST_HEAD(&dq->list);
4fde02ad
JG		 2254 dq->id = i;
2255 dq->hisi_hba = hisi_hba;
2256
6be6de18
JG		 2257 /* Delivery queue */
2258 s = sizeof(struct hisi_sas_cmd_hdr) * HISI_SAS_QUEUE_SLOTS;
4e63ac82
XC		 2259 hisi_hba->cmd_hdr[i] = dmam_alloc_coherent(dev, s,
2260 &hisi_hba->cmd_hdr_dma[i],
2261 GFP_KERNEL);
6be6de18
JG		 2262 if (!hisi_hba->cmd_hdr[i])
2263 goto err_out;
6be6de18
JG		 2264
2265 /* Completion queue */
2266 s = hisi_hba->hw->complete_hdr_size * HISI_SAS_QUEUE_SLOTS;
4e63ac82
XC		 2267 hisi_hba->complete_hdr[i] = dmam_alloc_coherent(dev, s,
2268 &hisi_hba->complete_hdr_dma[i],
2269 GFP_KERNEL);
6be6de18
JG		 2270 if (!hisi_hba->complete_hdr[i])
2271 goto err_out;
6be6de18
JG		 2272 }
2273
6be6de18 2274 s = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_itct);
4e63ac82 2275 hisi_hba->itct = dmam_alloc_coherent(dev, s, &hisi_hba->itct_dma,
a07b4876 2276 GFP_KERNEL);
6be6de18
JG		 2277 if (!hisi_hba->itct)
2278 goto err_out;
2279
a8d547bd 2280 hisi_hba->slot_info = devm_kcalloc(dev, max_command_entries,
6be6de18
JG		 2281 sizeof(struct hisi_sas_slot),
2282 GFP_KERNEL);
2283 if (!hisi_hba->slot_info)
2284 goto err_out;
2285
2ba5afb6 2286 /* roundup to avoid overly large block size */
4ca7fe99
YL		 2287 max_command_entries_ru = roundup(max_command_entries,
2288 BLK_CNT_OPTIMIZE_MARK);
b3cce125
XC		 2289 if (hisi_hba->prot_mask & HISI_SAS_DIX_PROT_MASK)
2290 sz_slot_buf_ru = sizeof(struct hisi_sas_slot_dif_buf_table);
2291 else
2292 sz_slot_buf_ru = sizeof(struct hisi_sas_slot_buf_table);
4ca7fe99
YL		 2293
2294 sz_slot_buf_ru = roundup(sz_slot_buf_ru, BLK_CNT_OPTIMIZE_MARK);
599aefc8 2295 s = max(lcm(max_command_entries_ru, sz_slot_buf_ru), PAGE_SIZE);
2ba5afb6
XC		 2296 blk_cnt = (max_command_entries_ru * sz_slot_buf_ru) / s;
2297 slots_per_blk = s / sz_slot_buf_ru;
b3cce125 2298
2ba5afb6 2299 for (i = 0; i < blk_cnt; i++) {
2ba5afb6 2300 int slot_index = i * slots_per_blk;
b3cce125
XC		 2301 dma_addr_t buf_dma;
2302 void *buf;
2ba5afb6 2303
b3cce125 2304 buf = dmam_alloc_coherent(dev, s, &buf_dma,
a07b4876 2305 GFP_KERNEL);
2ba5afb6
XC		 2306 if (!buf)
2307 goto err_out;
2ba5afb6
XC		 2308
2309 for (j = 0; j < slots_per_blk; j++, slot_index++) {
2310 struct hisi_sas_slot *slot;
2311
2312 slot = &hisi_hba->slot_info[slot_index];
2313 slot->buf = buf;
2314 slot->buf_dma = buf_dma;
2315 slot->idx = slot_index;
2316
b3cce125
XC		 2317 buf += sz_slot_buf_ru;
2318 buf_dma += sz_slot_buf_ru;
2ba5afb6
XC		 2319 }
2320 }
2321
a8d547bd 2322 s = max_command_entries * sizeof(struct hisi_sas_iost);
4e63ac82
XC		 2323 hisi_hba->iost = dmam_alloc_coherent(dev, s, &hisi_hba->iost_dma,
2324 GFP_KERNEL);
6be6de18
JG		 2325 if (!hisi_hba->iost)
2326 goto err_out;
2327
a8d547bd 2328 s = max_command_entries * sizeof(struct hisi_sas_breakpoint);
4e63ac82
XC		 2329 hisi_hba->breakpoint = dmam_alloc_coherent(dev, s,
2330 &hisi_hba->breakpoint_dma,
2331 GFP_KERNEL);
6be6de18
JG		 2332 if (!hisi_hba->breakpoint)
2333 goto err_out;
2334
54585ec6
CJ		 2335 s = hisi_hba->slot_index_count = max_command_entries;
2336 hisi_hba->slot_index_tags = devm_bitmap_zalloc(dev, s, GFP_KERNEL);
257efd1f
JG		 2337 if (!hisi_hba->slot_index_tags)
2338 goto err_out;
2339
6be6de18 2340 s = sizeof(struct hisi_sas_initial_fis) * HISI_SAS_MAX_PHYS;
4e63ac82
XC		 2341 hisi_hba->initial_fis = dmam_alloc_coherent(dev, s,
2342 &hisi_hba->initial_fis_dma,
2343 GFP_KERNEL);
6be6de18
JG		 2344 if (!hisi_hba->initial_fis)
2345 goto err_out;
6be6de18 2346
3297ded1 2347 s = HISI_SAS_MAX_ITCT_ENTRIES * sizeof(struct hisi_sas_sata_breakpoint);
4e63ac82
XC		 2348 hisi_hba->sata_breakpoint = dmam_alloc_coherent(dev, s,
2349 &hisi_hba->sata_breakpoint_dma,
2350 GFP_KERNEL);
6be6de18
JG		 2351 if (!hisi_hba->sata_breakpoint)
2352 goto err_out;
6be6de18 2353
f7d190a9 2354 hisi_hba->last_slot_index = 0;
257efd1f 2355
b97c0741
BVA		 2356 hisi_hba->wq =
2357 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, dev_name(dev));
7e9080e1
JG		 2358 if (!hisi_hba->wq) {
2359 dev_err(dev, "sas_alloc: failed to create workqueue\n");
2360 goto err_out;
2361 }
2362
6be6de18
JG		 2363 return 0;
2364err_out:
2365 return -ENOMEM;
2366}
e21fe3a5 2367EXPORT_SYMBOL_GPL(hisi_sas_alloc);
6be6de18 2368
e21fe3a5 2369void hisi_sas_free(struct hisi_hba *hisi_hba)
89d53322 2370{
6c86e046
XC		 2371 int i;
2372
2373 for (i = 0; i < hisi_hba->n_phy; i++) {
2374 struct hisi_sas_phy *phy = &hisi_hba->phy[i];
2375
8fa7292f 2376 timer_delete_sync(&phy->timer);
6c86e046
XC		 2377 }
2378
7e9080e1
JG		 2379 if (hisi_hba->wq)
2380 destroy_workqueue(hisi_hba->wq);
89d53322 2381}
e21fe3a5 2382EXPORT_SYMBOL_GPL(hisi_sas_free);
6be6de18 2383
b4241f0f 2384void hisi_sas_rst_work_handler(struct work_struct *work)
06ec0fb9
XC		 2385{
2386 struct hisi_hba *hisi_hba =
2387 container_of(work, struct hisi_hba, rst_work);
2388
2c74cb1f
JX		 2389 if (hisi_sas_controller_prereset(hisi_hba))
2390 return;
2391
06ec0fb9
XC		 2392 hisi_sas_controller_reset(hisi_hba);
2393}
b4241f0f 2394EXPORT_SYMBOL_GPL(hisi_sas_rst_work_handler);
06ec0fb9 2395
e402acdb
XT		 2396void hisi_sas_sync_rst_work_handler(struct work_struct *work)
2397{
2398 struct hisi_sas_rst *rst =
2399 container_of(work, struct hisi_sas_rst, work);
2400
2c74cb1f
JX		 2401 if (hisi_sas_controller_prereset(rst->hisi_hba))
2402 goto rst_complete;
2403
e402acdb
XT		 2404 if (!hisi_sas_controller_reset(rst->hisi_hba))
2405 rst->done = true;
2c74cb1f 2406rst_complete:
e402acdb
XT		 2407 complete(rst->completion);
2408}
2409EXPORT_SYMBOL_GPL(hisi_sas_sync_rst_work_handler);
2410
0fa24c19 2411int hisi_sas_get_fw_info(struct hisi_hba *hisi_hba)
7eb7869f 2412{
0fa24c19
JG		 2413 struct device *dev = hisi_hba->dev;
2414 struct platform_device *pdev = hisi_hba->platform_dev;
2415 struct device_node *np = pdev ? pdev->dev.of_node : NULL;
3bc45af8 2416 struct clk *refclk;
7eb7869f 2417
4d558c77 2418 if (device_property_read_u8_array(dev, "sas-addr", hisi_hba->sas_addr,
0fa24c19
JG		 2419 SAS_ADDR_SIZE)) {
2420 dev_err(dev, "could not get property sas-addr\n");
2421 return -ENOENT;
2422 }
e26b2f40 2423
4d558c77 2424 if (np) {
0fa24c19
JG		 2425 /*
2426 * These properties are only required for platform device-based
2427 * controller with DT firmware.
2428 */
4d558c77
JG		 2429 hisi_hba->ctrl = syscon_regmap_lookup_by_phandle(np,
2430 "hisilicon,sas-syscon");
0fa24c19
JG		 2431 if (IS_ERR(hisi_hba->ctrl)) {
2432 dev_err(dev, "could not get syscon\n");
2433 return -ENOENT;
2434 }
e26b2f40 2435
4d558c77 2436 if (device_property_read_u32(dev, "ctrl-reset-reg",
0fa24c19 2437 &hisi_hba->ctrl_reset_reg)) {
01d4e3a2 2438 dev_err(dev, "could not get property ctrl-reset-reg\n");
0fa24c19
JG		 2439 return -ENOENT;
2440 }
e26b2f40 2441
4d558c77 2442 if (device_property_read_u32(dev, "ctrl-reset-sts-reg",
0fa24c19 2443 &hisi_hba->ctrl_reset_sts_reg)) {
01d4e3a2 2444 dev_err(dev, "could not get property ctrl-reset-sts-reg\n");
0fa24c19
JG		 2445 return -ENOENT;
2446 }
e26b2f40 2447
4d558c77 2448 if (device_property_read_u32(dev, "ctrl-clock-ena-reg",
0fa24c19 2449 &hisi_hba->ctrl_clock_ena_reg)) {
01d4e3a2 2450 dev_err(dev, "could not get property ctrl-clock-ena-reg\n");
0fa24c19
JG		 2451 return -ENOENT;
2452 }
4d558c77
JG		 2453 }
2454
0fa24c19 2455 refclk = devm_clk_get(dev, NULL);
3bc45af8 2456 if (IS_ERR(refclk))
87e287c1 2457 dev_dbg(dev, "no ref clk property\n");
3bc45af8 2458 else
4ca7fe99
YL		 2459 hisi_hba->refclk_frequency_mhz = clk_get_rate(refclk) /
2460 HZ_TO_MHZ;
3bc45af8 2461
0fa24c19
JG		 2462 if (device_property_read_u32(dev, "phy-count", &hisi_hba->n_phy)) {
2463 dev_err(dev, "could not get property phy-count\n");
2464 return -ENOENT;
2465 }
e26b2f40 2466
4d558c77 2467 if (device_property_read_u32(dev, "queue-count",
0fa24c19
JG		 2468 &hisi_hba->queue_count)) {
2469 dev_err(dev, "could not get property queue-count\n");
2470 return -ENOENT;
2471 }
2472
2473 return 0;
2474}
2475EXPORT_SYMBOL_GPL(hisi_sas_get_fw_info);
2476
2477static struct Scsi_Host *hisi_sas_shost_alloc(struct platform_device *pdev,
2478 const struct hisi_sas_hw *hw)
2479{
2480 struct resource *res;
2481 struct Scsi_Host *shost;
2482 struct hisi_hba *hisi_hba;
2483 struct device *dev = &pdev->dev;
d9a00459 2484 int error;
0fa24c19 2485
235bfc7f 2486 shost = scsi_host_alloc(hw->sht, sizeof(*hisi_hba));
0fa24c19
JG		 2487 if (!shost) {
2488 dev_err(dev, "scsi host alloc failed\n");
2489 return NULL;
2490 }
2491 hisi_hba = shost_priv(shost);
2492
2493 INIT_WORK(&hisi_hba->rst_work, hisi_sas_rst_work_handler);
2494 hisi_hba->hw = hw;
2495 hisi_hba->dev = dev;
2496 hisi_hba->platform_dev = pdev;
2497 hisi_hba->shost = shost;
2498 SHOST_TO_SAS_HA(shost) = &hisi_hba->sha;
2499
77570eed 2500 timer_setup(&hisi_hba->timer, NULL, 0);
0fa24c19
JG		 2501
2502 if (hisi_sas_get_fw_info(hisi_hba) < 0)
e26b2f40
JG		 2503 goto err_out;
2504
2c335fa7
YL		 2505 if (hisi_hba->hw->fw_info_check) {
2506 if (hisi_hba->hw->fw_info_check(hisi_hba))
2507 goto err_out;
2508 }
2509
d9a00459 2510 error = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
d9a00459 2511 if (error) {
a6f2c7ff
JG		 2512 dev_err(dev, "No usable DMA addressing method\n");
2513 goto err_out;
2514 }
2515
c0c1a71e 2516 hisi_hba->regs = devm_platform_ioremap_resource(pdev, 0);
e26b2f40
JG		 2517 if (IS_ERR(hisi_hba->regs))
2518 goto err_out;
2519
6379c560
XT		 2520 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
2521 if (res) {
2522 hisi_hba->sgpio_regs = devm_ioremap_resource(dev, res);
2523 if (IS_ERR(hisi_hba->sgpio_regs))
2524 goto err_out;
2525 }
2526
ae68b566 2527 if (hisi_sas_alloc(hisi_hba)) {
89d53322 2528 hisi_sas_free(hisi_hba);
6be6de18 2529 goto err_out;
89d53322 2530 }
6be6de18 2531
7eb7869f
JG		 2532 return shost;
2533err_out:
76aae5f6 2534 scsi_host_put(shost);
7eb7869f
JG		 2535 dev_err(dev, "shost alloc failed\n");
2536 return NULL;
2537}
2538
74a29219
JG		 2539static int hisi_sas_interrupt_preinit(struct hisi_hba *hisi_hba)
2540{
2541 if (hisi_hba->hw->interrupt_preinit)
2542 return hisi_hba->hw->interrupt_preinit(hisi_hba);
2543 return 0;
2544}
2545
7eb7869f 2546int hisi_sas_probe(struct platform_device *pdev,
235bfc7f 2547 const struct hisi_sas_hw *hw)
7eb7869f
JG		 2548{
2549 struct Scsi_Host *shost;
2550 struct hisi_hba *hisi_hba;
2551 struct device *dev = &pdev->dev;
2552 struct asd_sas_phy **arr_phy;
2553 struct asd_sas_port **arr_port;
2554 struct sas_ha_struct *sha;
2555 int rc, phy_nr, port_nr, i;
2556
2557 shost = hisi_sas_shost_alloc(pdev, hw);
d37a0082
XT		 2558 if (!shost)
2559 return -ENOMEM;
7eb7869f
JG		 2560
2561 sha = SHOST_TO_SAS_HA(shost);
2562 hisi_hba = shost_priv(shost);
2563 platform_set_drvdata(pdev, sha);
50cb916f 2564
7eb7869f
JG		 2565 phy_nr = port_nr = hisi_hba->n_phy;
2566
2567 arr_phy = devm_kcalloc(dev, phy_nr, sizeof(void *), GFP_KERNEL);
2568 arr_port = devm_kcalloc(dev, port_nr, sizeof(void *), GFP_KERNEL);
d37a0082
XT		 2569 if (!arr_phy || !arr_port) {
2570 rc = -ENOMEM;
2571 goto err_out_ha;
2572 }
7eb7869f
JG		 2573
2574 sha->sas_phy = arr_phy;
2575 sha->sas_port = arr_port;
7eb7869f
JG		 2576 sha->lldd_ha = hisi_hba;
2577
2578 shost->transportt = hisi_sas_stt;
2579 shost->max_id = HISI_SAS_MAX_DEVICES;
2580 shost->max_lun = ~0;
2581 shost->max_channel = 1;
4ca7fe99 2582 shost->max_cmd_len = HISI_SAS_MAX_CDB_LEN;
784b46b7 2583 if (hisi_hba->hw->slot_index_alloc) {
93352abc
JG		 2584 shost->can_queue = HISI_SAS_MAX_COMMANDS;
2585 shost->cmd_per_lun = HISI_SAS_MAX_COMMANDS;
784b46b7 2586 } else {
93352abc
JG		 2587 shost->can_queue = HISI_SAS_UNRESERVED_IPTT;
2588 shost->cmd_per_lun = HISI_SAS_UNRESERVED_IPTT;
784b46b7 2589 }
7eb7869f
JG		 2590
2591 sha->sas_ha_name = DRV_NAME;
11b75249 2592 sha->dev = hisi_hba->dev;
7eb7869f
JG		 2593 sha->sas_addr = &hisi_hba->sas_addr[0];
2594 sha->num_phys = hisi_hba->n_phy;
1136a022 2595 sha->shost = hisi_hba->shost;
7eb7869f
JG		 2596
2597 for (i = 0; i < hisi_hba->n_phy; i++) {
2598 sha->sas_phy[i] = &hisi_hba->phy[i].sas_phy;
2599 sha->sas_port[i] = &hisi_hba->port[i].sas_port;
2600 }
2601
74a29219
JG		 2602 rc = hisi_sas_interrupt_preinit(hisi_hba);
2603 if (rc)
2604 goto err_out_ha;
2605
7eb7869f
JG		 2606 rc = scsi_add_host(shost, &pdev->dev);
2607 if (rc)
2608 goto err_out_ha;
2609
2610 rc = sas_register_ha(sha);
2611 if (rc)
2612 goto err_out_register_ha;
2613
0757f041
XC		 2614 rc = hisi_hba->hw->hw_init(hisi_hba);
2615 if (rc)
f4676665 2616 goto err_out_hw_init;
0757f041 2617
7eb7869f
JG		 2618 scsi_scan_host(shost);
2619
2620 return 0;
2621
f4676665
XC		 2622err_out_hw_init:
2623 sas_unregister_ha(sha);
7eb7869f
JG		 2624err_out_register_ha:
2625 scsi_remove_host(shost);
2626err_out_ha:
d37a0082 2627 hisi_sas_free(hisi_hba);
76aae5f6 2628 scsi_host_put(shost);
7eb7869f
JG		 2629 return rc;
2630}
2631EXPORT_SYMBOL_GPL(hisi_sas_probe);
2632
8cd6d0a3 2633void hisi_sas_remove(struct platform_device *pdev)
bbe0a7b3 2634{
89d53322
JG		 2635 struct sas_ha_struct *sha = platform_get_drvdata(pdev);
2636 struct hisi_hba *hisi_hba = sha->lldd_ha;
1136a022 2637 struct Scsi_Host *shost = sha->shost;
bbe0a7b3 2638
8fa7292f 2639 timer_delete_sync(&hisi_hba->timer);
bbe0a7b3 2640
89d53322 2641 sas_unregister_ha(sha);
1136a022 2642 sas_remove_host(shost);
bbe0a7b3 2643
89d53322 2644 hisi_sas_free(hisi_hba);
76aae5f6 2645 scsi_host_put(shost);
bbe0a7b3 2646}
89d53322 2647EXPORT_SYMBOL_GPL(hisi_sas_remove);
bbe0a7b3 2648
1dbe61bf
LJ		 2649#if IS_ENABLED(CONFIG_SCSI_HISI_SAS_DEBUGFS_DEFAULT_ENABLE)
2650#define DEBUGFS_ENABLE_DEFAULT "enabled"
2651bool hisi_sas_debugfs_enable = true;
2652u32 hisi_sas_debugfs_dump_count = 50;
2653#else
2654#define DEBUGFS_ENABLE_DEFAULT "disabled"
ef63464b 2655bool hisi_sas_debugfs_enable;
1dbe61bf
LJ		 2656u32 hisi_sas_debugfs_dump_count = 1;
2657#endif
2658
ef63464b
LJ		 2659EXPORT_SYMBOL_GPL(hisi_sas_debugfs_enable);
2660module_param_named(debugfs_enable, hisi_sas_debugfs_enable, bool, 0444);
1dbe61bf
LJ		 2661MODULE_PARM_DESC(hisi_sas_debugfs_enable,
2662 "Enable driver debugfs (default "DEBUGFS_ENABLE_DEFAULT")");
49159a5e 2663
905ab01f
LJ		 2664EXPORT_SYMBOL_GPL(hisi_sas_debugfs_dump_count);
2665module_param_named(debugfs_dump_count, hisi_sas_debugfs_dump_count, uint, 0444);
2666MODULE_PARM_DESC(hisi_sas_debugfs_dump_count, "Number of debugfs dumps to allow");
7c5e1363 2667
623a4b6d
LJ		 2668struct dentry *hisi_sas_debugfs_dir;
2669EXPORT_SYMBOL_GPL(hisi_sas_debugfs_dir);
905ab01f 2670
e8899fad
JG		 2671static __init int hisi_sas_init(void)
2672{
e8899fad
JG		 2673 hisi_sas_stt = sas_domain_attach_transport(&hisi_sas_transport_ops);
2674 if (!hisi_sas_stt)
2675 return -ENOMEM;
2676
905ab01f 2677 if (hisi_sas_debugfs_enable) {
ef63464b 2678 hisi_sas_debugfs_dir = debugfs_create_dir("hisi_sas", NULL);
905ab01f
LJ		 2679 if (hisi_sas_debugfs_dump_count > HISI_SAS_MAX_DEBUGFS_DUMP) {
2680 pr_info("hisi_sas: Limiting debugfs dump count\n");
2681 hisi_sas_debugfs_dump_count = HISI_SAS_MAX_DEBUGFS_DUMP;
2682 }
2683 }
ef63464b 2684
e8899fad
JG		 2685 return 0;
2686}
2687
2688static __exit void hisi_sas_exit(void)
2689{
69097a63
YL		 2690 if (hisi_sas_debugfs_enable)
2691 debugfs_remove(hisi_sas_debugfs_dir);
e6702e39
YL		 2692
2693 sas_release_transport(hisi_sas_stt);
e8899fad
JG		 2694}
2695
2696module_init(hisi_sas_init);
2697module_exit(hisi_sas_exit);
2698
e8899fad
JG		 2699MODULE_LICENSE("GPL");
2700MODULE_AUTHOR("John Garry <john.garry@huawei.com>");
2701MODULE_DESCRIPTION("HISILICON SAS controller driver");
2702MODULE_ALIAS("platform:" DRV_NAME);
Linux 6.x block layer and io_uring tree(s)