Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * Generic Generic NCR5380 driver | |
24c43341 | 3 | * |
1da177e4 | 4 | * Copyright 1993, Drew Eckhardt |
24c43341 FT |
5 | * Visionary Computing |
6 | * (Unix and Linux consulting and custom programming) | |
7 | * drew@colorado.edu | |
8 | * +1 (303) 440-4894 | |
1da177e4 LT |
9 | * |
10 | * NCR53C400 extensions (c) 1994,1995,1996, Kevin Lentin | |
24c43341 | 11 | * K.Lentin@cs.monash.edu.au |
1da177e4 LT |
12 | * |
13 | * NCR53C400A extensions (c) 1996, Ingmar Baumgart | |
24c43341 | 14 | * ingmar@gonzo.schwaben.de |
1da177e4 LT |
15 | * |
16 | * DTC3181E extensions (c) 1997, Ronald van Cuijlenborg | |
17 | * ronald.van.cuijlenborg@tip.nl or nutty@dds.nl | |
18 | * | |
19 | * Added ISAPNP support for DTC436 adapters, | |
20 | * Thomas Sailer, sailer@ife.ee.ethz.ch | |
1da177e4 | 21 | * |
9c41ab27 | 22 | * See Documentation/scsi/g_NCR5380.txt for more info. |
1da177e4 LT |
23 | */ |
24 | ||
1da177e4 | 25 | #include <asm/io.h> |
1da177e4 | 26 | #include <linux/blkdev.h> |
161c0059 | 27 | #include <linux/module.h> |
1da177e4 | 28 | #include <scsi/scsi_host.h> |
1da177e4 LT |
29 | #include <linux/init.h> |
30 | #include <linux/ioport.h> | |
a8cfbcae OZ |
31 | #include <linux/isa.h> |
32 | #include <linux/pnp.h> | |
1da177e4 LT |
33 | #include <linux/interrupt.h> |
34 | ||
14d739f6 FT |
35 | /* Definitions for the core NCR5380 driver. */ |
36 | ||
37 | #define NCR5380_read(reg) \ | |
38 | ioread8(hostdata->io + hostdata->offset + (reg)) | |
39 | #define NCR5380_write(reg, value) \ | |
40 | iowrite8(value, hostdata->io + hostdata->offset + (reg)) | |
41 | ||
42 | #define NCR5380_implementation_fields \ | |
43 | int offset; \ | |
44 | int c400_ctl_status; \ | |
45 | int c400_blk_cnt; \ | |
46 | int c400_host_buf; \ | |
e9dbadf7 | 47 | int io_width; \ |
facfc963 OZ |
48 | int pdma_residual; \ |
49 | int board | |
14d739f6 FT |
50 | |
51 | #define NCR5380_dma_xfer_len generic_NCR5380_dma_xfer_len | |
ab2ace2d FT |
52 | #define NCR5380_dma_recv_setup generic_NCR5380_precv |
53 | #define NCR5380_dma_send_setup generic_NCR5380_psend | |
e9dbadf7 | 54 | #define NCR5380_dma_residual generic_NCR5380_dma_residual |
14d739f6 FT |
55 | |
56 | #define NCR5380_intr generic_NCR5380_intr | |
57 | #define NCR5380_queue_command generic_NCR5380_queue_command | |
58 | #define NCR5380_abort generic_NCR5380_abort | |
12e5fc66 | 59 | #define NCR5380_host_reset generic_NCR5380_host_reset |
14d739f6 FT |
60 | #define NCR5380_info generic_NCR5380_info |
61 | ||
62 | #define NCR5380_io_delay(x) udelay(x) | |
63 | ||
64 | #include "NCR5380.h" | |
65 | ||
66 | #define DRV_MODULE_NAME "g_NCR5380" | |
67 | ||
68 | #define NCR53C400_mem_base 0x3880 | |
69 | #define NCR53C400_host_buffer 0x3900 | |
70 | #define NCR53C400_region_size 0x3a00 | |
71 | ||
72 | #define BOARD_NCR5380 0 | |
73 | #define BOARD_NCR53C400 1 | |
74 | #define BOARD_NCR53C400A 2 | |
75 | #define BOARD_DTC3181E 3 | |
76 | #define BOARD_HP_C2502 4 | |
77 | ||
78 | #define IRQ_AUTO 254 | |
79 | ||
a8cfbcae | 80 | #define MAX_CARDS 8 |
12b859b7 | 81 | #define DMA_MAX_SIZE 32768 |
a8cfbcae OZ |
82 | |
83 | /* old-style parameters for compatibility */ | |
70439e93 | 84 | static int ncr_irq = -1; |
c0965e63 FT |
85 | static int ncr_addr; |
86 | static int ncr_5380; | |
87 | static int ncr_53c400; | |
88 | static int ncr_53c400a; | |
89 | static int dtc_3181e; | |
c6084cbc | 90 | static int hp_c2502; |
88f06b76 DH |
91 | module_param_hw(ncr_irq, int, irq, 0); |
92 | module_param_hw(ncr_addr, int, ioport, 0); | |
a8cfbcae OZ |
93 | module_param(ncr_5380, int, 0); |
94 | module_param(ncr_53c400, int, 0); | |
95 | module_param(ncr_53c400a, int, 0); | |
96 | module_param(dtc_3181e, int, 0); | |
97 | module_param(hp_c2502, int, 0); | |
98 | ||
70439e93 | 99 | static int irq[] = { -1, -1, -1, -1, -1, -1, -1, -1 }; |
88f06b76 | 100 | module_param_hw_array(irq, int, irq, NULL, 0); |
70439e93 | 101 | MODULE_PARM_DESC(irq, "IRQ number(s) (0=none, 254=auto [default])"); |
1da177e4 | 102 | |
a8cfbcae | 103 | static int base[] = { 0, 0, 0, 0, 0, 0, 0, 0 }; |
88f06b76 | 104 | module_param_hw_array(base, int, ioport, NULL, 0); |
a8cfbcae OZ |
105 | MODULE_PARM_DESC(base, "base address(es)"); |
106 | ||
107 | static int card[] = { -1, -1, -1, -1, -1, -1, -1, -1 }; | |
108 | module_param_array(card, int, NULL, 0); | |
109 | MODULE_PARM_DESC(card, "card type (0=NCR5380, 1=NCR53C400, 2=NCR53C400A, 3=DTC3181E, 4=HP C2502)"); | |
110 | ||
b61bacbc | 111 | MODULE_ALIAS("g_NCR5380_mmio"); |
a8cfbcae | 112 | MODULE_LICENSE("GPL"); |
1da177e4 | 113 | |
906e4a3c OZ |
114 | static void g_NCR5380_trigger_irq(struct Scsi_Host *instance) |
115 | { | |
116 | struct NCR5380_hostdata *hostdata = shost_priv(instance); | |
117 | ||
118 | /* | |
119 | * An interrupt is triggered whenever BSY = false, SEL = true | |
120 | * and a bit set in the SELECT_ENABLE_REG is asserted on the | |
121 | * SCSI bus. | |
122 | * | |
123 | * Note that the bus is only driven when the phase control signals | |
124 | * (I/O, C/D, and MSG) match those in the TCR. | |
125 | */ | |
126 | NCR5380_write(TARGET_COMMAND_REG, | |
127 | PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK)); | |
128 | NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); | |
129 | NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask); | |
130 | NCR5380_write(INITIATOR_COMMAND_REG, | |
131 | ICR_BASE | ICR_ASSERT_DATA | ICR_ASSERT_SEL); | |
132 | ||
133 | msleep(1); | |
134 | ||
135 | NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); | |
136 | NCR5380_write(SELECT_ENABLE_REG, 0); | |
137 | NCR5380_write(TARGET_COMMAND_REG, 0); | |
138 | } | |
139 | ||
140 | /** | |
141 | * g_NCR5380_probe_irq - find the IRQ of a NCR5380 or equivalent | |
142 | * @instance: SCSI host instance | |
143 | * | |
144 | * Autoprobe for the IRQ line used by the card by triggering an IRQ | |
145 | * and then looking to see what interrupt actually turned up. | |
146 | */ | |
147 | ||
148 | static int g_NCR5380_probe_irq(struct Scsi_Host *instance) | |
149 | { | |
150 | struct NCR5380_hostdata *hostdata = shost_priv(instance); | |
151 | int irq_mask, irq; | |
152 | ||
153 | NCR5380_read(RESET_PARITY_INTERRUPT_REG); | |
154 | irq_mask = probe_irq_on(); | |
155 | g_NCR5380_trigger_irq(instance); | |
156 | irq = probe_irq_off(irq_mask); | |
157 | NCR5380_read(RESET_PARITY_INTERRUPT_REG); | |
158 | ||
159 | if (irq <= 0) | |
160 | return NO_IRQ; | |
161 | return irq; | |
162 | } | |
163 | ||
c6084cbc OZ |
164 | /* |
165 | * Configure I/O address of 53C400A or DTC436 by writing magic numbers | |
166 | * to ports 0x779 and 0x379. | |
167 | */ | |
168 | static void magic_configure(int idx, u8 irq, u8 magic[]) | |
169 | { | |
170 | u8 cfg = 0; | |
171 | ||
172 | outb(magic[0], 0x779); | |
173 | outb(magic[1], 0x379); | |
174 | outb(magic[2], 0x379); | |
175 | outb(magic[3], 0x379); | |
176 | outb(magic[4], 0x379); | |
177 | ||
145c3ae4 FT |
178 | if (irq == 9) |
179 | irq = 2; | |
180 | ||
c6084cbc OZ |
181 | if (idx >= 0 && idx <= 7) |
182 | cfg = 0x80 | idx | (irq << 4); | |
183 | outb(cfg, 0x379); | |
184 | } | |
b61bacbc | 185 | |
145c3ae4 FT |
186 | static irqreturn_t legacy_empty_irq_handler(int irq, void *dev_id) |
187 | { | |
188 | return IRQ_HANDLED; | |
189 | } | |
190 | ||
191 | static int legacy_find_free_irq(int *irq_table) | |
192 | { | |
193 | while (*irq_table != -1) { | |
194 | if (!request_irq(*irq_table, legacy_empty_irq_handler, | |
195 | IRQF_PROBE_SHARED, "Test IRQ", | |
196 | (void *)irq_table)) { | |
197 | free_irq(*irq_table, (void *) irq_table); | |
198 | return *irq_table; | |
199 | } | |
200 | irq_table++; | |
201 | } | |
202 | return -1; | |
203 | } | |
204 | ||
b61bacbc OZ |
205 | static unsigned int ncr_53c400a_ports[] = { |
206 | 0x280, 0x290, 0x300, 0x310, 0x330, 0x340, 0x348, 0x350, 0 | |
207 | }; | |
208 | static unsigned int dtc_3181e_ports[] = { | |
209 | 0x220, 0x240, 0x280, 0x2a0, 0x2c0, 0x300, 0x320, 0x340, 0 | |
210 | }; | |
211 | static u8 ncr_53c400a_magic[] = { /* 53C400A & DTC436 */ | |
212 | 0x59, 0xb9, 0xc5, 0xae, 0xa6 | |
213 | }; | |
214 | static u8 hp_c2502_magic[] = { /* HP C2502 */ | |
215 | 0x0f, 0x22, 0xf0, 0x20, 0x80 | |
216 | }; | |
145c3ae4 FT |
217 | static int hp_c2502_irqs[] = { |
218 | 9, 5, 7, 3, 4, -1 | |
219 | }; | |
c6084cbc | 220 | |
a8cfbcae OZ |
221 | static int generic_NCR5380_init_one(struct scsi_host_template *tpnt, |
222 | struct device *pdev, int base, int irq, int board) | |
1da177e4 | 223 | { |
b61bacbc OZ |
224 | bool is_pmio = base <= 0xffff; |
225 | int ret; | |
226 | int flags = 0; | |
227 | unsigned int *ports = NULL; | |
c6084cbc | 228 | u8 *magic = NULL; |
702a98c6 | 229 | int i; |
c6084cbc | 230 | int port_idx = -1; |
9d376402 | 231 | unsigned long region_size; |
1da177e4 | 232 | struct Scsi_Host *instance; |
12150797 | 233 | struct NCR5380_hostdata *hostdata; |
820682b1 | 234 | u8 __iomem *iomem; |
1da177e4 | 235 | |
a8cfbcae | 236 | switch (board) { |
d91f5afe OZ |
237 | case BOARD_NCR5380: |
238 | flags = FLAG_NO_PSEUDO_DMA | FLAG_DMA_FIXUP; | |
239 | break; | |
240 | case BOARD_NCR53C400A: | |
241 | ports = ncr_53c400a_ports; | |
242 | magic = ncr_53c400a_magic; | |
243 | break; | |
244 | case BOARD_HP_C2502: | |
245 | ports = ncr_53c400a_ports; | |
246 | magic = hp_c2502_magic; | |
247 | break; | |
248 | case BOARD_DTC3181E: | |
249 | ports = dtc_3181e_ports; | |
250 | magic = ncr_53c400a_magic; | |
251 | break; | |
252 | } | |
1da177e4 | 253 | |
b61bacbc | 254 | if (is_pmio && ports && magic) { |
d91f5afe | 255 | /* wakeup sequence for the NCR53C400A and DTC3181E */ |
1da177e4 | 256 | |
d91f5afe OZ |
257 | /* Disable the adapter and look for a free io port */ |
258 | magic_configure(-1, 0, magic); | |
1da177e4 | 259 | |
d91f5afe | 260 | region_size = 16; |
a8cfbcae | 261 | if (base) |
d91f5afe | 262 | for (i = 0; ports[i]; i++) { |
a8cfbcae OZ |
263 | if (base == ports[i]) { /* index found */ |
264 | if (!request_region(ports[i], | |
265 | region_size, | |
266 | "ncr53c80")) | |
267 | return -EBUSY; | |
d91f5afe | 268 | break; |
a8cfbcae OZ |
269 | } |
270 | } | |
271 | else | |
d91f5afe | 272 | for (i = 0; ports[i]; i++) { |
a8cfbcae OZ |
273 | if (!request_region(ports[i], region_size, |
274 | "ncr53c80")) | |
d91f5afe OZ |
275 | continue; |
276 | if (inb(ports[i]) == 0xff) | |
277 | break; | |
278 | release_region(ports[i], region_size); | |
279 | } | |
280 | if (ports[i]) { | |
281 | /* At this point we have our region reserved */ | |
282 | magic_configure(i, 0, magic); /* no IRQ yet */ | |
7b93ca43 OZ |
283 | base = ports[i]; |
284 | outb(0xc0, base + 9); | |
285 | if (inb(base + 9) != 0x80) { | |
a8cfbcae OZ |
286 | ret = -ENODEV; |
287 | goto out_release; | |
288 | } | |
d91f5afe OZ |
289 | port_idx = i; |
290 | } else | |
a8cfbcae | 291 | return -EINVAL; |
b61bacbc | 292 | } else if (is_pmio) { |
a8cfbcae | 293 | /* NCR5380 - no configuration, just grab */ |
d91f5afe | 294 | region_size = 8; |
a8cfbcae OZ |
295 | if (!base || !request_region(base, region_size, "ncr5380")) |
296 | return -EBUSY; | |
b61bacbc OZ |
297 | } else { /* MMIO */ |
298 | region_size = NCR53C400_region_size; | |
299 | if (!request_mem_region(base, region_size, "ncr5380")) | |
300 | return -EBUSY; | |
d91f5afe | 301 | } |
b61bacbc OZ |
302 | |
303 | if (is_pmio) | |
304 | iomem = ioport_map(base, region_size); | |
305 | else | |
306 | iomem = ioremap(base, region_size); | |
307 | ||
d91f5afe | 308 | if (!iomem) { |
b61bacbc OZ |
309 | ret = -ENOMEM; |
310 | goto out_release; | |
d91f5afe | 311 | } |
b61bacbc | 312 | |
a8cfbcae OZ |
313 | instance = scsi_host_alloc(tpnt, sizeof(struct NCR5380_hostdata)); |
314 | if (instance == NULL) { | |
315 | ret = -ENOMEM; | |
b61bacbc | 316 | goto out_unmap; |
a8cfbcae | 317 | } |
d91f5afe | 318 | hostdata = shost_priv(instance); |
1da177e4 | 319 | |
facfc963 | 320 | hostdata->board = board; |
820682b1 FT |
321 | hostdata->io = iomem; |
322 | hostdata->region_size = region_size; | |
b61bacbc OZ |
323 | |
324 | if (is_pmio) { | |
820682b1 | 325 | hostdata->io_port = base; |
b61bacbc OZ |
326 | hostdata->io_width = 1; /* 8-bit PDMA by default */ |
327 | hostdata->offset = 0; | |
328 | ||
329 | /* | |
330 | * On NCR53C400 boards, NCR5380 registers are mapped 8 past | |
331 | * the base address. | |
332 | */ | |
333 | switch (board) { | |
334 | case BOARD_NCR53C400: | |
820682b1 | 335 | hostdata->io_port += 8; |
b61bacbc OZ |
336 | hostdata->c400_ctl_status = 0; |
337 | hostdata->c400_blk_cnt = 1; | |
338 | hostdata->c400_host_buf = 4; | |
339 | break; | |
340 | case BOARD_DTC3181E: | |
341 | hostdata->io_width = 2; /* 16-bit PDMA */ | |
342 | /* fall through */ | |
343 | case BOARD_NCR53C400A: | |
344 | case BOARD_HP_C2502: | |
345 | hostdata->c400_ctl_status = 9; | |
346 | hostdata->c400_blk_cnt = 10; | |
347 | hostdata->c400_host_buf = 8; | |
348 | break; | |
349 | } | |
350 | } else { | |
820682b1 | 351 | hostdata->base = base; |
b61bacbc OZ |
352 | hostdata->offset = NCR53C400_mem_base; |
353 | switch (board) { | |
354 | case BOARD_NCR53C400: | |
355 | hostdata->c400_ctl_status = 0x100; | |
356 | hostdata->c400_blk_cnt = 0x101; | |
357 | hostdata->c400_host_buf = 0x104; | |
358 | break; | |
359 | case BOARD_DTC3181E: | |
360 | case BOARD_NCR53C400A: | |
361 | case BOARD_HP_C2502: | |
362 | pr_err(DRV_MODULE_NAME ": unknown register offsets\n"); | |
363 | ret = -EINVAL; | |
364 | goto out_unregister; | |
365 | } | |
d91f5afe | 366 | } |
1da177e4 | 367 | |
89fa9b5c OZ |
368 | /* Check for vacant slot */ |
369 | NCR5380_write(MODE_REG, 0); | |
370 | if (NCR5380_read(MODE_REG) != 0) { | |
371 | ret = -ENODEV; | |
372 | goto out_unregister; | |
373 | } | |
374 | ||
a8cfbcae OZ |
375 | ret = NCR5380_init(instance, flags | FLAG_LATE_DMA_SETUP); |
376 | if (ret) | |
d91f5afe | 377 | goto out_unregister; |
1da177e4 | 378 | |
a8cfbcae | 379 | switch (board) { |
d91f5afe OZ |
380 | case BOARD_NCR53C400: |
381 | case BOARD_DTC3181E: | |
382 | case BOARD_NCR53C400A: | |
383 | case BOARD_HP_C2502: | |
384 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); | |
385 | } | |
4d8c08c7 | 386 | |
d91f5afe | 387 | NCR5380_maybe_reset_bus(instance); |
b6488f97 | 388 | |
d91f5afe | 389 | /* Compatibility with documented NCR5380 kernel parameters */ |
145c3ae4 FT |
390 | if (irq == 255 || irq == 0) |
391 | irq = NO_IRQ; | |
70439e93 FT |
392 | else if (irq == -1) |
393 | irq = IRQ_AUTO; | |
145c3ae4 FT |
394 | |
395 | if (board == BOARD_HP_C2502) { | |
396 | int *irq_table = hp_c2502_irqs; | |
397 | int board_irq = -1; | |
398 | ||
399 | switch (irq) { | |
400 | case NO_IRQ: | |
401 | board_irq = 0; | |
402 | break; | |
403 | case IRQ_AUTO: | |
404 | board_irq = legacy_find_free_irq(irq_table); | |
405 | break; | |
406 | default: | |
407 | while (*irq_table != -1) | |
408 | if (*irq_table++ == irq) | |
409 | board_irq = irq; | |
410 | } | |
411 | ||
412 | if (board_irq <= 0) { | |
413 | board_irq = 0; | |
414 | irq = NO_IRQ; | |
415 | } | |
416 | ||
417 | magic_configure(port_idx, board_irq, magic); | |
418 | } | |
419 | ||
70439e93 | 420 | if (irq == IRQ_AUTO) { |
145c3ae4 | 421 | instance->irq = g_NCR5380_probe_irq(instance); |
70439e93 FT |
422 | if (instance->irq == NO_IRQ) |
423 | shost_printk(KERN_INFO, instance, "no irq detected\n"); | |
424 | } else { | |
145c3ae4 | 425 | instance->irq = irq; |
70439e93 FT |
426 | if (instance->irq == NO_IRQ) |
427 | shost_printk(KERN_INFO, instance, "no irq provided\n"); | |
428 | } | |
22f5f10d | 429 | |
d91f5afe | 430 | if (instance->irq != NO_IRQ) { |
d91f5afe OZ |
431 | if (request_irq(instance->irq, generic_NCR5380_intr, |
432 | 0, "NCR5380", instance)) { | |
d91f5afe | 433 | instance->irq = NO_IRQ; |
70439e93 FT |
434 | shost_printk(KERN_INFO, instance, |
435 | "irq %d denied\n", instance->irq); | |
436 | } else { | |
437 | shost_printk(KERN_INFO, instance, | |
438 | "irq %d acquired\n", instance->irq); | |
1da177e4 | 439 | } |
d91f5afe | 440 | } |
1da177e4 | 441 | |
a8cfbcae OZ |
442 | ret = scsi_add_host(instance, pdev); |
443 | if (ret) | |
444 | goto out_free_irq; | |
445 | scsi_scan_host(instance); | |
446 | dev_set_drvdata(pdev, instance); | |
447 | return 0; | |
0ad0eff9 | 448 | |
a8cfbcae OZ |
449 | out_free_irq: |
450 | if (instance->irq != NO_IRQ) | |
451 | free_irq(instance->irq, instance); | |
452 | NCR5380_exit(instance); | |
0ad0eff9 | 453 | out_unregister: |
a8cfbcae | 454 | scsi_host_put(instance); |
b61bacbc | 455 | out_unmap: |
0ad0eff9 | 456 | iounmap(iomem); |
b61bacbc OZ |
457 | out_release: |
458 | if (is_pmio) | |
459 | release_region(base, region_size); | |
460 | else | |
461 | release_mem_region(base, region_size); | |
a8cfbcae | 462 | return ret; |
1da177e4 LT |
463 | } |
464 | ||
a8cfbcae | 465 | static void generic_NCR5380_release_resources(struct Scsi_Host *instance) |
1da177e4 | 466 | { |
b61bacbc | 467 | struct NCR5380_hostdata *hostdata = shost_priv(instance); |
820682b1 FT |
468 | void __iomem *iomem = hostdata->io; |
469 | unsigned long io_port = hostdata->io_port; | |
470 | unsigned long base = hostdata->base; | |
471 | unsigned long region_size = hostdata->region_size; | |
b61bacbc | 472 | |
a8cfbcae | 473 | scsi_remove_host(instance); |
22f5f10d | 474 | if (instance->irq != NO_IRQ) |
1e641664 | 475 | free_irq(instance->irq, instance); |
1da177e4 | 476 | NCR5380_exit(instance); |
a8cfbcae | 477 | scsi_host_put(instance); |
820682b1 FT |
478 | iounmap(iomem); |
479 | if (io_port) | |
480 | release_region(io_port, region_size); | |
481 | else | |
482 | release_mem_region(base, region_size); | |
1da177e4 | 483 | } |
1da177e4 | 484 | |
99a974e6 OZ |
485 | /* wait_for_53c80_access - wait for 53C80 registers to become accessible |
486 | * @hostdata: scsi host private data | |
487 | * | |
488 | * The registers within the 53C80 logic block are inaccessible until | |
489 | * bit 7 in the 53C400 control status register gets asserted. | |
490 | */ | |
491 | ||
492 | static void wait_for_53c80_access(struct NCR5380_hostdata *hostdata) | |
493 | { | |
494 | int count = 10000; | |
495 | ||
496 | do { | |
facfc963 OZ |
497 | if (hostdata->board == BOARD_DTC3181E) |
498 | udelay(4); /* DTC436 chip hangs without this */ | |
99a974e6 OZ |
499 | if (NCR5380_read(hostdata->c400_ctl_status) & CSR_53C80_REG) |
500 | return; | |
501 | } while (--count > 0); | |
502 | ||
503 | scmd_printk(KERN_ERR, hostdata->connected, | |
504 | "53c80 registers not accessible, device will be reset\n"); | |
505 | NCR5380_write(hostdata->c400_ctl_status, CSR_RESET); | |
506 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); | |
507 | } | |
508 | ||
1da177e4 | 509 | /** |
ab2ace2d | 510 | * generic_NCR5380_precv - pseudo DMA receive |
24c43341 FT |
511 | * @hostdata: scsi host private data |
512 | * @dst: buffer to write into | |
513 | * @len: transfer size | |
1da177e4 | 514 | * |
24c43341 | 515 | * Perform a pseudo DMA mode receive from a 53C400 or equivalent device. |
1da177e4 | 516 | */ |
24c43341 | 517 | |
ab2ace2d | 518 | static inline int generic_NCR5380_precv(struct NCR5380_hostdata *hostdata, |
6c4b88ca | 519 | unsigned char *dst, int len) |
1da177e4 | 520 | { |
99a974e6 | 521 | int residual; |
1da177e4 | 522 | int start = 0; |
1da177e4 | 523 | |
12150797 | 524 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE | CSR_TRANS_DIR); |
99a974e6 OZ |
525 | NCR5380_write(hostdata->c400_blk_cnt, len / 128); |
526 | ||
527 | do { | |
528 | if (start == len - 128) { | |
529 | /* Ignore End of DMA interrupt for the final buffer */ | |
530 | if (NCR5380_poll_politely(hostdata, hostdata->c400_ctl_status, | |
531 | CSR_HOST_BUF_NOT_RDY, 0, HZ / 64) < 0) | |
532 | break; | |
533 | } else { | |
534 | if (NCR5380_poll_politely2(hostdata, hostdata->c400_ctl_status, | |
535 | CSR_HOST_BUF_NOT_RDY, 0, | |
536 | hostdata->c400_ctl_status, | |
537 | CSR_GATED_53C80_IRQ, | |
538 | CSR_GATED_53C80_IRQ, HZ / 64) < 0 || | |
539 | NCR5380_read(hostdata->c400_ctl_status) & CSR_HOST_BUF_NOT_RDY) | |
540 | break; | |
541 | } | |
1da177e4 | 542 | |
820682b1 FT |
543 | if (hostdata->io_port && hostdata->io_width == 2) |
544 | insw(hostdata->io_port + hostdata->c400_host_buf, | |
24c43341 | 545 | dst + start, 64); |
820682b1 FT |
546 | else if (hostdata->io_port) |
547 | insb(hostdata->io_port + hostdata->c400_host_buf, | |
24c43341 | 548 | dst + start, 128); |
b61bacbc OZ |
549 | else |
550 | memcpy_fromio(dst + start, | |
820682b1 | 551 | hostdata->io + NCR53C400_host_buffer, 128); |
1da177e4 | 552 | start += 128; |
99a974e6 | 553 | } while (start < len); |
1da177e4 | 554 | |
99a974e6 | 555 | residual = len - start; |
b61bacbc | 556 | |
99a974e6 OZ |
557 | if (residual != 0) { |
558 | /* 53c80 interrupt or transfer timeout. Reset 53c400 logic. */ | |
559 | NCR5380_write(hostdata->c400_ctl_status, CSR_RESET); | |
560 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); | |
1da177e4 | 561 | } |
99a974e6 | 562 | wait_for_53c80_access(hostdata); |
1da177e4 | 563 | |
99a974e6 OZ |
564 | if (residual == 0 && NCR5380_poll_politely(hostdata, BUS_AND_STATUS_REG, |
565 | BASR_END_DMA_TRANSFER, | |
566 | BASR_END_DMA_TRANSFER, | |
567 | HZ / 64) < 0) | |
568 | scmd_printk(KERN_ERR, hostdata->connected, "%s: End of DMA timeout\n", | |
569 | __func__); | |
e9dbadf7 | 570 | |
99a974e6 | 571 | hostdata->pdma_residual = residual; |
e9dbadf7 | 572 | |
1da177e4 LT |
573 | return 0; |
574 | } | |
575 | ||
576 | /** | |
ab2ace2d | 577 | * generic_NCR5380_psend - pseudo DMA send |
24c43341 FT |
578 | * @hostdata: scsi host private data |
579 | * @src: buffer to read from | |
580 | * @len: transfer size | |
1da177e4 | 581 | * |
24c43341 | 582 | * Perform a pseudo DMA mode send to a 53C400 or equivalent device. |
1da177e4 LT |
583 | */ |
584 | ||
ab2ace2d FT |
585 | static inline int generic_NCR5380_psend(struct NCR5380_hostdata *hostdata, |
586 | unsigned char *src, int len) | |
1da177e4 | 587 | { |
99a974e6 | 588 | int residual; |
1da177e4 | 589 | int start = 0; |
1da177e4 | 590 | |
12150797 | 591 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); |
99a974e6 OZ |
592 | NCR5380_write(hostdata->c400_blk_cnt, len / 128); |
593 | ||
594 | do { | |
595 | if (NCR5380_poll_politely2(hostdata, hostdata->c400_ctl_status, | |
596 | CSR_HOST_BUF_NOT_RDY, 0, | |
597 | hostdata->c400_ctl_status, | |
598 | CSR_GATED_53C80_IRQ, | |
599 | CSR_GATED_53C80_IRQ, HZ / 64) < 0 || | |
600 | NCR5380_read(hostdata->c400_ctl_status) & CSR_HOST_BUF_NOT_RDY) { | |
601 | /* Both 128 B buffers are in use */ | |
602 | if (start >= 128) | |
603 | start -= 128; | |
604 | if (start >= 128) | |
605 | start -= 128; | |
606 | break; | |
607 | } | |
1da177e4 | 608 | |
99a974e6 | 609 | if (start >= len && NCR5380_read(hostdata->c400_blk_cnt) == 0) |
1da177e4 | 610 | break; |
b61bacbc | 611 | |
99a974e6 OZ |
612 | if (NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ) { |
613 | /* Host buffer is empty, other one is in use */ | |
614 | if (start >= 128) | |
615 | start -= 128; | |
616 | break; | |
617 | } | |
b61bacbc | 618 | |
99a974e6 OZ |
619 | if (start >= len) |
620 | continue; | |
1da177e4 | 621 | |
820682b1 FT |
622 | if (hostdata->io_port && hostdata->io_width == 2) |
623 | outsw(hostdata->io_port + hostdata->c400_host_buf, | |
24c43341 | 624 | src + start, 64); |
820682b1 FT |
625 | else if (hostdata->io_port) |
626 | outsb(hostdata->io_port + hostdata->c400_host_buf, | |
24c43341 | 627 | src + start, 128); |
b61bacbc | 628 | else |
820682b1 | 629 | memcpy_toio(hostdata->io + NCR53C400_host_buffer, |
b61bacbc | 630 | src + start, 128); |
1da177e4 | 631 | start += 128; |
99a974e6 | 632 | } while (1); |
1da177e4 | 633 | |
99a974e6 | 634 | residual = len - start; |
e9dbadf7 | 635 | |
99a974e6 OZ |
636 | if (residual != 0) { |
637 | /* 53c80 interrupt or transfer timeout. Reset 53c400 logic. */ | |
638 | NCR5380_write(hostdata->c400_ctl_status, CSR_RESET); | |
639 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); | |
640 | } | |
641 | wait_for_53c80_access(hostdata); | |
642 | ||
643 | if (residual == 0) { | |
644 | if (NCR5380_poll_politely(hostdata, TARGET_COMMAND_REG, | |
645 | TCR_LAST_BYTE_SENT, TCR_LAST_BYTE_SENT, | |
646 | HZ / 64) < 0) | |
647 | scmd_printk(KERN_ERR, hostdata->connected, | |
648 | "%s: Last Byte Sent timeout\n", __func__); | |
649 | ||
650 | if (NCR5380_poll_politely(hostdata, BUS_AND_STATUS_REG, | |
651 | BASR_END_DMA_TRANSFER, BASR_END_DMA_TRANSFER, | |
652 | HZ / 64) < 0) | |
653 | scmd_printk(KERN_ERR, hostdata->connected, "%s: End of DMA timeout\n", | |
654 | __func__); | |
aeb51152 | 655 | } |
1da177e4 | 656 | |
99a974e6 | 657 | hostdata->pdma_residual = residual; |
e9dbadf7 | 658 | |
1da177e4 LT |
659 | return 0; |
660 | } | |
ff3d4578 | 661 | |
4a98f896 | 662 | static int generic_NCR5380_dma_xfer_len(struct NCR5380_hostdata *hostdata, |
7e9ec8d9 | 663 | struct scsi_cmnd *cmd) |
ff3d4578 | 664 | { |
12b859b7 | 665 | int transfersize = cmd->SCp.this_residual; |
ff3d4578 | 666 | |
7e9ec8d9 FT |
667 | if (hostdata->flags & FLAG_NO_PSEUDO_DMA) |
668 | return 0; | |
669 | ||
f0394621 OZ |
670 | /* 53C400 datasheet: non-modulo-128-byte transfers should use PIO */ |
671 | if (transfersize % 128) | |
facfc963 OZ |
672 | return 0; |
673 | ||
674 | /* Limit PDMA send to 512 B to avoid random corruption on DTC3181E */ | |
675 | if (hostdata->board == BOARD_DTC3181E && | |
676 | cmd->sc_data_direction == DMA_TO_DEVICE) | |
677 | transfersize = min(cmd->SCp.this_residual, 512); | |
f0394621 | 678 | |
12b859b7 | 679 | return min(transfersize, DMA_MAX_SIZE); |
ff3d4578 FT |
680 | } |
681 | ||
e9dbadf7 OZ |
682 | static int generic_NCR5380_dma_residual(struct NCR5380_hostdata *hostdata) |
683 | { | |
684 | return hostdata->pdma_residual; | |
685 | } | |
686 | ||
24c43341 FT |
687 | /* Include the core driver code. */ |
688 | ||
1da177e4 LT |
689 | #include "NCR5380.c" |
690 | ||
d0be4a7d | 691 | static struct scsi_host_template driver_template = { |
a8cfbcae | 692 | .module = THIS_MODULE, |
aa2e2cb1 | 693 | .proc_name = DRV_MODULE_NAME, |
aa2e2cb1 | 694 | .name = "Generic NCR5380/NCR53C400 SCSI", |
aa2e2cb1 FT |
695 | .info = generic_NCR5380_info, |
696 | .queuecommand = generic_NCR5380_queue_command, | |
1da177e4 | 697 | .eh_abort_handler = generic_NCR5380_abort, |
12e5fc66 | 698 | .eh_host_reset_handler = generic_NCR5380_host_reset, |
aa2e2cb1 FT |
699 | .can_queue = 16, |
700 | .this_id = 7, | |
701 | .sg_tablesize = SG_ALL, | |
702 | .cmd_per_lun = 2, | |
703 | .use_clustering = DISABLE_CLUSTERING, | |
32b26a10 | 704 | .cmd_size = NCR5380_CMD_SIZE, |
0a4e3612 | 705 | .max_sectors = 128, |
1da177e4 | 706 | }; |
161c0059 | 707 | |
a8cfbcae OZ |
708 | static int generic_NCR5380_isa_match(struct device *pdev, unsigned int ndev) |
709 | { | |
710 | int ret = generic_NCR5380_init_one(&driver_template, pdev, base[ndev], | |
24c43341 | 711 | irq[ndev], card[ndev]); |
a8cfbcae OZ |
712 | if (ret) { |
713 | if (base[ndev]) | |
714 | printk(KERN_WARNING "Card not found at address 0x%03x\n", | |
715 | base[ndev]); | |
716 | return 0; | |
717 | } | |
1da177e4 | 718 | |
a8cfbcae OZ |
719 | return 1; |
720 | } | |
721 | ||
722 | static int generic_NCR5380_isa_remove(struct device *pdev, | |
24c43341 | 723 | unsigned int ndev) |
a8cfbcae OZ |
724 | { |
725 | generic_NCR5380_release_resources(dev_get_drvdata(pdev)); | |
726 | dev_set_drvdata(pdev, NULL); | |
727 | return 0; | |
728 | } | |
729 | ||
730 | static struct isa_driver generic_NCR5380_isa_driver = { | |
731 | .match = generic_NCR5380_isa_match, | |
732 | .remove = generic_NCR5380_isa_remove, | |
733 | .driver = { | |
734 | .name = DRV_MODULE_NAME | |
735 | }, | |
736 | }; | |
737 | ||
b61bacbc | 738 | #ifdef CONFIG_PNP |
60747936 | 739 | static const struct pnp_device_id generic_NCR5380_pnp_ids[] = { |
a8cfbcae OZ |
740 | { .id = "DTC436e", .driver_data = BOARD_DTC3181E }, |
741 | { .id = "" } | |
742 | }; | |
743 | MODULE_DEVICE_TABLE(pnp, generic_NCR5380_pnp_ids); | |
744 | ||
745 | static int generic_NCR5380_pnp_probe(struct pnp_dev *pdev, | |
24c43341 | 746 | const struct pnp_device_id *id) |
a8cfbcae OZ |
747 | { |
748 | int base, irq; | |
749 | ||
750 | if (pnp_activate_dev(pdev) < 0) | |
751 | return -EBUSY; | |
752 | ||
753 | base = pnp_port_start(pdev, 0); | |
754 | irq = pnp_irq(pdev, 0); | |
755 | ||
756 | return generic_NCR5380_init_one(&driver_template, &pdev->dev, base, irq, | |
24c43341 | 757 | id->driver_data); |
a8cfbcae OZ |
758 | } |
759 | ||
760 | static void generic_NCR5380_pnp_remove(struct pnp_dev *pdev) | |
761 | { | |
762 | generic_NCR5380_release_resources(pnp_get_drvdata(pdev)); | |
763 | pnp_set_drvdata(pdev, NULL); | |
764 | } | |
765 | ||
766 | static struct pnp_driver generic_NCR5380_pnp_driver = { | |
767 | .name = DRV_MODULE_NAME, | |
768 | .id_table = generic_NCR5380_pnp_ids, | |
769 | .probe = generic_NCR5380_pnp_probe, | |
770 | .remove = generic_NCR5380_pnp_remove, | |
1da177e4 | 771 | }; |
b61bacbc | 772 | #endif /* defined(CONFIG_PNP) */ |
1da177e4 | 773 | |
a8cfbcae OZ |
774 | static int pnp_registered, isa_registered; |
775 | ||
776 | static int __init generic_NCR5380_init(void) | |
777 | { | |
778 | int ret = 0; | |
779 | ||
780 | /* compatibility with old-style parameters */ | |
70439e93 | 781 | if (irq[0] == -1 && base[0] == 0 && card[0] == -1) { |
a8cfbcae OZ |
782 | irq[0] = ncr_irq; |
783 | base[0] = ncr_addr; | |
784 | if (ncr_5380) | |
785 | card[0] = BOARD_NCR5380; | |
786 | if (ncr_53c400) | |
787 | card[0] = BOARD_NCR53C400; | |
788 | if (ncr_53c400a) | |
789 | card[0] = BOARD_NCR53C400A; | |
790 | if (dtc_3181e) | |
791 | card[0] = BOARD_DTC3181E; | |
792 | if (hp_c2502) | |
793 | card[0] = BOARD_HP_C2502; | |
794 | } | |
795 | ||
b61bacbc | 796 | #ifdef CONFIG_PNP |
a8cfbcae OZ |
797 | if (!pnp_register_driver(&generic_NCR5380_pnp_driver)) |
798 | pnp_registered = 1; | |
702a98c6 | 799 | #endif |
a8cfbcae OZ |
800 | ret = isa_register_driver(&generic_NCR5380_isa_driver, MAX_CARDS); |
801 | if (!ret) | |
802 | isa_registered = 1; | |
803 | ||
804 | return (pnp_registered || isa_registered) ? 0 : ret; | |
805 | } | |
806 | ||
807 | static void __exit generic_NCR5380_exit(void) | |
808 | { | |
b61bacbc | 809 | #ifdef CONFIG_PNP |
a8cfbcae OZ |
810 | if (pnp_registered) |
811 | pnp_unregister_driver(&generic_NCR5380_pnp_driver); | |
812 | #endif | |
813 | if (isa_registered) | |
814 | isa_unregister_driver(&generic_NCR5380_isa_driver); | |
815 | } | |
816 | ||
817 | module_init(generic_NCR5380_init); | |
818 | module_exit(generic_NCR5380_exit); |