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09c434b8 | 1 | // SPDX-License-Identifier: GPL-2.0-only |
1da177e4 LT |
2 | /* |
3 | * Generic Generic NCR5380 driver | |
24c43341 | 4 | * |
1da177e4 | 5 | * Copyright 1993, Drew Eckhardt |
24c43341 FT |
6 | * Visionary Computing |
7 | * (Unix and Linux consulting and custom programming) | |
8 | * drew@colorado.edu | |
9 | * +1 (303) 440-4894 | |
1da177e4 LT |
10 | * |
11 | * NCR53C400 extensions (c) 1994,1995,1996, Kevin Lentin | |
24c43341 | 12 | * K.Lentin@cs.monash.edu.au |
1da177e4 LT |
13 | * |
14 | * NCR53C400A extensions (c) 1996, Ingmar Baumgart | |
24c43341 | 15 | * ingmar@gonzo.schwaben.de |
1da177e4 LT |
16 | * |
17 | * DTC3181E extensions (c) 1997, Ronald van Cuijlenborg | |
18 | * ronald.van.cuijlenborg@tip.nl or nutty@dds.nl | |
19 | * | |
20 | * Added ISAPNP support for DTC436 adapters, | |
21 | * Thomas Sailer, sailer@ife.ee.ethz.ch | |
1da177e4 | 22 | * |
3c1e681b | 23 | * See Documentation/scsi/g_NCR5380.rst for more info. |
1da177e4 LT |
24 | */ |
25 | ||
1da177e4 | 26 | #include <asm/io.h> |
1da177e4 | 27 | #include <linux/blkdev.h> |
161c0059 | 28 | #include <linux/module.h> |
1da177e4 | 29 | #include <scsi/scsi_host.h> |
1da177e4 LT |
30 | #include <linux/init.h> |
31 | #include <linux/ioport.h> | |
a8cfbcae OZ |
32 | #include <linux/isa.h> |
33 | #include <linux/pnp.h> | |
1da177e4 LT |
34 | #include <linux/interrupt.h> |
35 | ||
14d739f6 FT |
36 | /* Definitions for the core NCR5380 driver. */ |
37 | ||
38 | #define NCR5380_read(reg) \ | |
39 | ioread8(hostdata->io + hostdata->offset + (reg)) | |
40 | #define NCR5380_write(reg, value) \ | |
41 | iowrite8(value, hostdata->io + hostdata->offset + (reg)) | |
42 | ||
43 | #define NCR5380_implementation_fields \ | |
44 | int offset; \ | |
45 | int c400_ctl_status; \ | |
46 | int c400_blk_cnt; \ | |
47 | int c400_host_buf; \ | |
e9dbadf7 | 48 | int io_width; \ |
facfc963 OZ |
49 | int pdma_residual; \ |
50 | int board | |
14d739f6 FT |
51 | |
52 | #define NCR5380_dma_xfer_len generic_NCR5380_dma_xfer_len | |
ab2ace2d FT |
53 | #define NCR5380_dma_recv_setup generic_NCR5380_precv |
54 | #define NCR5380_dma_send_setup generic_NCR5380_psend | |
e9dbadf7 | 55 | #define NCR5380_dma_residual generic_NCR5380_dma_residual |
14d739f6 FT |
56 | |
57 | #define NCR5380_intr generic_NCR5380_intr | |
58 | #define NCR5380_queue_command generic_NCR5380_queue_command | |
59 | #define NCR5380_abort generic_NCR5380_abort | |
12e5fc66 | 60 | #define NCR5380_host_reset generic_NCR5380_host_reset |
14d739f6 FT |
61 | #define NCR5380_info generic_NCR5380_info |
62 | ||
63 | #define NCR5380_io_delay(x) udelay(x) | |
64 | ||
65 | #include "NCR5380.h" | |
66 | ||
67 | #define DRV_MODULE_NAME "g_NCR5380" | |
68 | ||
69 | #define NCR53C400_mem_base 0x3880 | |
70 | #define NCR53C400_host_buffer 0x3900 | |
71 | #define NCR53C400_region_size 0x3a00 | |
72 | ||
73 | #define BOARD_NCR5380 0 | |
74 | #define BOARD_NCR53C400 1 | |
75 | #define BOARD_NCR53C400A 2 | |
76 | #define BOARD_DTC3181E 3 | |
77 | #define BOARD_HP_C2502 4 | |
78 | ||
79 | #define IRQ_AUTO 254 | |
80 | ||
a8cfbcae | 81 | #define MAX_CARDS 8 |
12b859b7 | 82 | #define DMA_MAX_SIZE 32768 |
a8cfbcae OZ |
83 | |
84 | /* old-style parameters for compatibility */ | |
70439e93 | 85 | static int ncr_irq = -1; |
c0965e63 FT |
86 | static int ncr_addr; |
87 | static int ncr_5380; | |
88 | static int ncr_53c400; | |
89 | static int ncr_53c400a; | |
90 | static int dtc_3181e; | |
c6084cbc | 91 | static int hp_c2502; |
88f06b76 DH |
92 | module_param_hw(ncr_irq, int, irq, 0); |
93 | module_param_hw(ncr_addr, int, ioport, 0); | |
a8cfbcae OZ |
94 | module_param(ncr_5380, int, 0); |
95 | module_param(ncr_53c400, int, 0); | |
96 | module_param(ncr_53c400a, int, 0); | |
97 | module_param(dtc_3181e, int, 0); | |
98 | module_param(hp_c2502, int, 0); | |
99 | ||
70439e93 | 100 | static int irq[] = { -1, -1, -1, -1, -1, -1, -1, -1 }; |
88f06b76 | 101 | module_param_hw_array(irq, int, irq, NULL, 0); |
70439e93 | 102 | MODULE_PARM_DESC(irq, "IRQ number(s) (0=none, 254=auto [default])"); |
1da177e4 | 103 | |
a8cfbcae | 104 | static int base[] = { 0, 0, 0, 0, 0, 0, 0, 0 }; |
88f06b76 | 105 | module_param_hw_array(base, int, ioport, NULL, 0); |
a8cfbcae OZ |
106 | MODULE_PARM_DESC(base, "base address(es)"); |
107 | ||
108 | static int card[] = { -1, -1, -1, -1, -1, -1, -1, -1 }; | |
109 | module_param_array(card, int, NULL, 0); | |
110 | MODULE_PARM_DESC(card, "card type (0=NCR5380, 1=NCR53C400, 2=NCR53C400A, 3=DTC3181E, 4=HP C2502)"); | |
111 | ||
b61bacbc | 112 | MODULE_ALIAS("g_NCR5380_mmio"); |
a8cfbcae | 113 | MODULE_LICENSE("GPL"); |
1da177e4 | 114 | |
906e4a3c OZ |
115 | static void g_NCR5380_trigger_irq(struct Scsi_Host *instance) |
116 | { | |
117 | struct NCR5380_hostdata *hostdata = shost_priv(instance); | |
118 | ||
119 | /* | |
120 | * An interrupt is triggered whenever BSY = false, SEL = true | |
121 | * and a bit set in the SELECT_ENABLE_REG is asserted on the | |
122 | * SCSI bus. | |
123 | * | |
124 | * Note that the bus is only driven when the phase control signals | |
125 | * (I/O, C/D, and MSG) match those in the TCR. | |
126 | */ | |
127 | NCR5380_write(TARGET_COMMAND_REG, | |
128 | PHASE_SR_TO_TCR(NCR5380_read(STATUS_REG) & PHASE_MASK)); | |
129 | NCR5380_write(SELECT_ENABLE_REG, hostdata->id_mask); | |
130 | NCR5380_write(OUTPUT_DATA_REG, hostdata->id_mask); | |
131 | NCR5380_write(INITIATOR_COMMAND_REG, | |
132 | ICR_BASE | ICR_ASSERT_DATA | ICR_ASSERT_SEL); | |
133 | ||
134 | msleep(1); | |
135 | ||
136 | NCR5380_write(INITIATOR_COMMAND_REG, ICR_BASE); | |
137 | NCR5380_write(SELECT_ENABLE_REG, 0); | |
138 | NCR5380_write(TARGET_COMMAND_REG, 0); | |
139 | } | |
140 | ||
141 | /** | |
142 | * g_NCR5380_probe_irq - find the IRQ of a NCR5380 or equivalent | |
143 | * @instance: SCSI host instance | |
144 | * | |
145 | * Autoprobe for the IRQ line used by the card by triggering an IRQ | |
146 | * and then looking to see what interrupt actually turned up. | |
147 | */ | |
148 | ||
149 | static int g_NCR5380_probe_irq(struct Scsi_Host *instance) | |
150 | { | |
151 | struct NCR5380_hostdata *hostdata = shost_priv(instance); | |
152 | int irq_mask, irq; | |
153 | ||
154 | NCR5380_read(RESET_PARITY_INTERRUPT_REG); | |
155 | irq_mask = probe_irq_on(); | |
156 | g_NCR5380_trigger_irq(instance); | |
157 | irq = probe_irq_off(irq_mask); | |
158 | NCR5380_read(RESET_PARITY_INTERRUPT_REG); | |
159 | ||
160 | if (irq <= 0) | |
161 | return NO_IRQ; | |
162 | return irq; | |
163 | } | |
164 | ||
c6084cbc OZ |
165 | /* |
166 | * Configure I/O address of 53C400A or DTC436 by writing magic numbers | |
167 | * to ports 0x779 and 0x379. | |
168 | */ | |
169 | static void magic_configure(int idx, u8 irq, u8 magic[]) | |
170 | { | |
171 | u8 cfg = 0; | |
172 | ||
173 | outb(magic[0], 0x779); | |
174 | outb(magic[1], 0x379); | |
175 | outb(magic[2], 0x379); | |
176 | outb(magic[3], 0x379); | |
177 | outb(magic[4], 0x379); | |
178 | ||
145c3ae4 FT |
179 | if (irq == 9) |
180 | irq = 2; | |
181 | ||
c6084cbc OZ |
182 | if (idx >= 0 && idx <= 7) |
183 | cfg = 0x80 | idx | (irq << 4); | |
184 | outb(cfg, 0x379); | |
185 | } | |
b61bacbc | 186 | |
145c3ae4 FT |
187 | static irqreturn_t legacy_empty_irq_handler(int irq, void *dev_id) |
188 | { | |
189 | return IRQ_HANDLED; | |
190 | } | |
191 | ||
192 | static int legacy_find_free_irq(int *irq_table) | |
193 | { | |
194 | while (*irq_table != -1) { | |
195 | if (!request_irq(*irq_table, legacy_empty_irq_handler, | |
196 | IRQF_PROBE_SHARED, "Test IRQ", | |
197 | (void *)irq_table)) { | |
198 | free_irq(*irq_table, (void *) irq_table); | |
199 | return *irq_table; | |
200 | } | |
201 | irq_table++; | |
202 | } | |
203 | return -1; | |
204 | } | |
205 | ||
b61bacbc OZ |
206 | static unsigned int ncr_53c400a_ports[] = { |
207 | 0x280, 0x290, 0x300, 0x310, 0x330, 0x340, 0x348, 0x350, 0 | |
208 | }; | |
209 | static unsigned int dtc_3181e_ports[] = { | |
210 | 0x220, 0x240, 0x280, 0x2a0, 0x2c0, 0x300, 0x320, 0x340, 0 | |
211 | }; | |
212 | static u8 ncr_53c400a_magic[] = { /* 53C400A & DTC436 */ | |
213 | 0x59, 0xb9, 0xc5, 0xae, 0xa6 | |
214 | }; | |
215 | static u8 hp_c2502_magic[] = { /* HP C2502 */ | |
216 | 0x0f, 0x22, 0xf0, 0x20, 0x80 | |
217 | }; | |
145c3ae4 FT |
218 | static int hp_c2502_irqs[] = { |
219 | 9, 5, 7, 3, 4, -1 | |
220 | }; | |
c6084cbc | 221 | |
bd5e469a | 222 | static int generic_NCR5380_init_one(const struct scsi_host_template *tpnt, |
a8cfbcae | 223 | struct device *pdev, int base, int irq, int board) |
1da177e4 | 224 | { |
b61bacbc OZ |
225 | bool is_pmio = base <= 0xffff; |
226 | int ret; | |
227 | int flags = 0; | |
228 | unsigned int *ports = NULL; | |
c6084cbc | 229 | u8 *magic = NULL; |
702a98c6 | 230 | int i; |
c6084cbc | 231 | int port_idx = -1; |
9d376402 | 232 | unsigned long region_size; |
1da177e4 | 233 | struct Scsi_Host *instance; |
12150797 | 234 | struct NCR5380_hostdata *hostdata; |
820682b1 | 235 | u8 __iomem *iomem; |
1da177e4 | 236 | |
a8cfbcae | 237 | switch (board) { |
d91f5afe OZ |
238 | case BOARD_NCR5380: |
239 | flags = FLAG_NO_PSEUDO_DMA | FLAG_DMA_FIXUP; | |
240 | break; | |
241 | case BOARD_NCR53C400A: | |
242 | ports = ncr_53c400a_ports; | |
243 | magic = ncr_53c400a_magic; | |
244 | break; | |
245 | case BOARD_HP_C2502: | |
246 | ports = ncr_53c400a_ports; | |
247 | magic = hp_c2502_magic; | |
248 | break; | |
249 | case BOARD_DTC3181E: | |
250 | ports = dtc_3181e_ports; | |
251 | magic = ncr_53c400a_magic; | |
252 | break; | |
253 | } | |
1da177e4 | 254 | |
b61bacbc | 255 | if (is_pmio && ports && magic) { |
d91f5afe | 256 | /* wakeup sequence for the NCR53C400A and DTC3181E */ |
1da177e4 | 257 | |
d91f5afe OZ |
258 | /* Disable the adapter and look for a free io port */ |
259 | magic_configure(-1, 0, magic); | |
1da177e4 | 260 | |
d91f5afe | 261 | region_size = 16; |
a8cfbcae | 262 | if (base) |
d91f5afe | 263 | for (i = 0; ports[i]; i++) { |
a8cfbcae OZ |
264 | if (base == ports[i]) { /* index found */ |
265 | if (!request_region(ports[i], | |
266 | region_size, | |
267 | "ncr53c80")) | |
268 | return -EBUSY; | |
d91f5afe | 269 | break; |
a8cfbcae OZ |
270 | } |
271 | } | |
272 | else | |
d91f5afe | 273 | for (i = 0; ports[i]; i++) { |
a8cfbcae OZ |
274 | if (!request_region(ports[i], region_size, |
275 | "ncr53c80")) | |
d91f5afe OZ |
276 | continue; |
277 | if (inb(ports[i]) == 0xff) | |
278 | break; | |
279 | release_region(ports[i], region_size); | |
280 | } | |
281 | if (ports[i]) { | |
282 | /* At this point we have our region reserved */ | |
283 | magic_configure(i, 0, magic); /* no IRQ yet */ | |
7b93ca43 OZ |
284 | base = ports[i]; |
285 | outb(0xc0, base + 9); | |
286 | if (inb(base + 9) != 0x80) { | |
a8cfbcae OZ |
287 | ret = -ENODEV; |
288 | goto out_release; | |
289 | } | |
d91f5afe OZ |
290 | port_idx = i; |
291 | } else | |
a8cfbcae | 292 | return -EINVAL; |
b61bacbc | 293 | } else if (is_pmio) { |
a8cfbcae | 294 | /* NCR5380 - no configuration, just grab */ |
d91f5afe | 295 | region_size = 8; |
a8cfbcae OZ |
296 | if (!base || !request_region(base, region_size, "ncr5380")) |
297 | return -EBUSY; | |
b61bacbc OZ |
298 | } else { /* MMIO */ |
299 | region_size = NCR53C400_region_size; | |
300 | if (!request_mem_region(base, region_size, "ncr5380")) | |
301 | return -EBUSY; | |
d91f5afe | 302 | } |
b61bacbc OZ |
303 | |
304 | if (is_pmio) | |
305 | iomem = ioport_map(base, region_size); | |
306 | else | |
307 | iomem = ioremap(base, region_size); | |
308 | ||
d91f5afe | 309 | if (!iomem) { |
b61bacbc OZ |
310 | ret = -ENOMEM; |
311 | goto out_release; | |
d91f5afe | 312 | } |
b61bacbc | 313 | |
a8cfbcae OZ |
314 | instance = scsi_host_alloc(tpnt, sizeof(struct NCR5380_hostdata)); |
315 | if (instance == NULL) { | |
316 | ret = -ENOMEM; | |
b61bacbc | 317 | goto out_unmap; |
a8cfbcae | 318 | } |
d91f5afe | 319 | hostdata = shost_priv(instance); |
1da177e4 | 320 | |
facfc963 | 321 | hostdata->board = board; |
820682b1 FT |
322 | hostdata->io = iomem; |
323 | hostdata->region_size = region_size; | |
b61bacbc OZ |
324 | |
325 | if (is_pmio) { | |
820682b1 | 326 | hostdata->io_port = base; |
b61bacbc OZ |
327 | hostdata->io_width = 1; /* 8-bit PDMA by default */ |
328 | hostdata->offset = 0; | |
329 | ||
330 | /* | |
331 | * On NCR53C400 boards, NCR5380 registers are mapped 8 past | |
332 | * the base address. | |
333 | */ | |
334 | switch (board) { | |
335 | case BOARD_NCR53C400: | |
820682b1 | 336 | hostdata->io_port += 8; |
b61bacbc OZ |
337 | hostdata->c400_ctl_status = 0; |
338 | hostdata->c400_blk_cnt = 1; | |
339 | hostdata->c400_host_buf = 4; | |
340 | break; | |
341 | case BOARD_DTC3181E: | |
342 | hostdata->io_width = 2; /* 16-bit PDMA */ | |
df561f66 | 343 | fallthrough; |
b61bacbc OZ |
344 | case BOARD_NCR53C400A: |
345 | case BOARD_HP_C2502: | |
346 | hostdata->c400_ctl_status = 9; | |
347 | hostdata->c400_blk_cnt = 10; | |
348 | hostdata->c400_host_buf = 8; | |
349 | break; | |
350 | } | |
351 | } else { | |
820682b1 | 352 | hostdata->base = base; |
b61bacbc OZ |
353 | hostdata->offset = NCR53C400_mem_base; |
354 | switch (board) { | |
355 | case BOARD_NCR53C400: | |
356 | hostdata->c400_ctl_status = 0x100; | |
357 | hostdata->c400_blk_cnt = 0x101; | |
358 | hostdata->c400_host_buf = 0x104; | |
359 | break; | |
360 | case BOARD_DTC3181E: | |
361 | case BOARD_NCR53C400A: | |
362 | case BOARD_HP_C2502: | |
363 | pr_err(DRV_MODULE_NAME ": unknown register offsets\n"); | |
364 | ret = -EINVAL; | |
365 | goto out_unregister; | |
366 | } | |
d91f5afe | 367 | } |
1da177e4 | 368 | |
89fa9b5c OZ |
369 | /* Check for vacant slot */ |
370 | NCR5380_write(MODE_REG, 0); | |
371 | if (NCR5380_read(MODE_REG) != 0) { | |
372 | ret = -ENODEV; | |
373 | goto out_unregister; | |
374 | } | |
375 | ||
a8cfbcae OZ |
376 | ret = NCR5380_init(instance, flags | FLAG_LATE_DMA_SETUP); |
377 | if (ret) | |
d91f5afe | 378 | goto out_unregister; |
1da177e4 | 379 | |
a8cfbcae | 380 | switch (board) { |
d91f5afe OZ |
381 | case BOARD_NCR53C400: |
382 | case BOARD_DTC3181E: | |
383 | case BOARD_NCR53C400A: | |
384 | case BOARD_HP_C2502: | |
385 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); | |
386 | } | |
4d8c08c7 | 387 | |
d91f5afe | 388 | NCR5380_maybe_reset_bus(instance); |
b6488f97 | 389 | |
d91f5afe | 390 | /* Compatibility with documented NCR5380 kernel parameters */ |
145c3ae4 FT |
391 | if (irq == 255 || irq == 0) |
392 | irq = NO_IRQ; | |
70439e93 FT |
393 | else if (irq == -1) |
394 | irq = IRQ_AUTO; | |
145c3ae4 FT |
395 | |
396 | if (board == BOARD_HP_C2502) { | |
397 | int *irq_table = hp_c2502_irqs; | |
398 | int board_irq = -1; | |
399 | ||
400 | switch (irq) { | |
401 | case NO_IRQ: | |
402 | board_irq = 0; | |
403 | break; | |
404 | case IRQ_AUTO: | |
405 | board_irq = legacy_find_free_irq(irq_table); | |
406 | break; | |
407 | default: | |
408 | while (*irq_table != -1) | |
409 | if (*irq_table++ == irq) | |
410 | board_irq = irq; | |
411 | } | |
412 | ||
413 | if (board_irq <= 0) { | |
414 | board_irq = 0; | |
415 | irq = NO_IRQ; | |
416 | } | |
417 | ||
418 | magic_configure(port_idx, board_irq, magic); | |
419 | } | |
420 | ||
70439e93 | 421 | if (irq == IRQ_AUTO) { |
145c3ae4 | 422 | instance->irq = g_NCR5380_probe_irq(instance); |
70439e93 FT |
423 | if (instance->irq == NO_IRQ) |
424 | shost_printk(KERN_INFO, instance, "no irq detected\n"); | |
425 | } else { | |
145c3ae4 | 426 | instance->irq = irq; |
70439e93 FT |
427 | if (instance->irq == NO_IRQ) |
428 | shost_printk(KERN_INFO, instance, "no irq provided\n"); | |
429 | } | |
22f5f10d | 430 | |
d91f5afe | 431 | if (instance->irq != NO_IRQ) { |
d91f5afe OZ |
432 | if (request_irq(instance->irq, generic_NCR5380_intr, |
433 | 0, "NCR5380", instance)) { | |
d91f5afe | 434 | instance->irq = NO_IRQ; |
70439e93 FT |
435 | shost_printk(KERN_INFO, instance, |
436 | "irq %d denied\n", instance->irq); | |
437 | } else { | |
438 | shost_printk(KERN_INFO, instance, | |
439 | "irq %d acquired\n", instance->irq); | |
1da177e4 | 440 | } |
d91f5afe | 441 | } |
1da177e4 | 442 | |
a8cfbcae OZ |
443 | ret = scsi_add_host(instance, pdev); |
444 | if (ret) | |
445 | goto out_free_irq; | |
446 | scsi_scan_host(instance); | |
447 | dev_set_drvdata(pdev, instance); | |
448 | return 0; | |
0ad0eff9 | 449 | |
a8cfbcae OZ |
450 | out_free_irq: |
451 | if (instance->irq != NO_IRQ) | |
452 | free_irq(instance->irq, instance); | |
453 | NCR5380_exit(instance); | |
0ad0eff9 | 454 | out_unregister: |
a8cfbcae | 455 | scsi_host_put(instance); |
b61bacbc | 456 | out_unmap: |
0ad0eff9 | 457 | iounmap(iomem); |
b61bacbc OZ |
458 | out_release: |
459 | if (is_pmio) | |
460 | release_region(base, region_size); | |
461 | else | |
462 | release_mem_region(base, region_size); | |
a8cfbcae | 463 | return ret; |
1da177e4 LT |
464 | } |
465 | ||
a8cfbcae | 466 | static void generic_NCR5380_release_resources(struct Scsi_Host *instance) |
1da177e4 | 467 | { |
b61bacbc | 468 | struct NCR5380_hostdata *hostdata = shost_priv(instance); |
820682b1 FT |
469 | void __iomem *iomem = hostdata->io; |
470 | unsigned long io_port = hostdata->io_port; | |
471 | unsigned long base = hostdata->base; | |
472 | unsigned long region_size = hostdata->region_size; | |
b61bacbc | 473 | |
a8cfbcae | 474 | scsi_remove_host(instance); |
22f5f10d | 475 | if (instance->irq != NO_IRQ) |
1e641664 | 476 | free_irq(instance->irq, instance); |
1da177e4 | 477 | NCR5380_exit(instance); |
a8cfbcae | 478 | scsi_host_put(instance); |
820682b1 FT |
479 | iounmap(iomem); |
480 | if (io_port) | |
481 | release_region(io_port, region_size); | |
482 | else | |
483 | release_mem_region(base, region_size); | |
1da177e4 | 484 | } |
1da177e4 | 485 | |
99a974e6 OZ |
486 | /* wait_for_53c80_access - wait for 53C80 registers to become accessible |
487 | * @hostdata: scsi host private data | |
488 | * | |
489 | * The registers within the 53C80 logic block are inaccessible until | |
490 | * bit 7 in the 53C400 control status register gets asserted. | |
491 | */ | |
492 | ||
493 | static void wait_for_53c80_access(struct NCR5380_hostdata *hostdata) | |
494 | { | |
495 | int count = 10000; | |
496 | ||
497 | do { | |
facfc963 OZ |
498 | if (hostdata->board == BOARD_DTC3181E) |
499 | udelay(4); /* DTC436 chip hangs without this */ | |
99a974e6 OZ |
500 | if (NCR5380_read(hostdata->c400_ctl_status) & CSR_53C80_REG) |
501 | return; | |
502 | } while (--count > 0); | |
503 | ||
504 | scmd_printk(KERN_ERR, hostdata->connected, | |
505 | "53c80 registers not accessible, device will be reset\n"); | |
506 | NCR5380_write(hostdata->c400_ctl_status, CSR_RESET); | |
507 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); | |
508 | } | |
509 | ||
1da177e4 | 510 | /** |
ab2ace2d | 511 | * generic_NCR5380_precv - pseudo DMA receive |
24c43341 FT |
512 | * @hostdata: scsi host private data |
513 | * @dst: buffer to write into | |
514 | * @len: transfer size | |
1da177e4 | 515 | * |
24c43341 | 516 | * Perform a pseudo DMA mode receive from a 53C400 or equivalent device. |
1da177e4 | 517 | */ |
24c43341 | 518 | |
ab2ace2d | 519 | static inline int generic_NCR5380_precv(struct NCR5380_hostdata *hostdata, |
6c4b88ca | 520 | unsigned char *dst, int len) |
1da177e4 | 521 | { |
99a974e6 | 522 | int residual; |
1da177e4 | 523 | int start = 0; |
1da177e4 | 524 | |
12150797 | 525 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE | CSR_TRANS_DIR); |
99a974e6 OZ |
526 | NCR5380_write(hostdata->c400_blk_cnt, len / 128); |
527 | ||
528 | do { | |
529 | if (start == len - 128) { | |
530 | /* Ignore End of DMA interrupt for the final buffer */ | |
531 | if (NCR5380_poll_politely(hostdata, hostdata->c400_ctl_status, | |
e7734ef1 | 532 | CSR_HOST_BUF_NOT_RDY, 0, 0) < 0) |
99a974e6 OZ |
533 | break; |
534 | } else { | |
535 | if (NCR5380_poll_politely2(hostdata, hostdata->c400_ctl_status, | |
536 | CSR_HOST_BUF_NOT_RDY, 0, | |
537 | hostdata->c400_ctl_status, | |
538 | CSR_GATED_53C80_IRQ, | |
e7734ef1 | 539 | CSR_GATED_53C80_IRQ, 0) < 0 || |
99a974e6 OZ |
540 | NCR5380_read(hostdata->c400_ctl_status) & CSR_HOST_BUF_NOT_RDY) |
541 | break; | |
542 | } | |
1da177e4 | 543 | |
820682b1 FT |
544 | if (hostdata->io_port && hostdata->io_width == 2) |
545 | insw(hostdata->io_port + hostdata->c400_host_buf, | |
24c43341 | 546 | dst + start, 64); |
820682b1 FT |
547 | else if (hostdata->io_port) |
548 | insb(hostdata->io_port + hostdata->c400_host_buf, | |
24c43341 | 549 | dst + start, 128); |
b61bacbc OZ |
550 | else |
551 | memcpy_fromio(dst + start, | |
820682b1 | 552 | hostdata->io + NCR53C400_host_buffer, 128); |
1da177e4 | 553 | start += 128; |
99a974e6 | 554 | } while (start < len); |
1da177e4 | 555 | |
99a974e6 | 556 | residual = len - start; |
b61bacbc | 557 | |
99a974e6 OZ |
558 | if (residual != 0) { |
559 | /* 53c80 interrupt or transfer timeout. Reset 53c400 logic. */ | |
560 | NCR5380_write(hostdata->c400_ctl_status, CSR_RESET); | |
561 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); | |
1da177e4 | 562 | } |
99a974e6 | 563 | wait_for_53c80_access(hostdata); |
1da177e4 | 564 | |
99a974e6 OZ |
565 | if (residual == 0 && NCR5380_poll_politely(hostdata, BUS_AND_STATUS_REG, |
566 | BASR_END_DMA_TRANSFER, | |
567 | BASR_END_DMA_TRANSFER, | |
e7734ef1 | 568 | 0) < 0) |
99a974e6 OZ |
569 | scmd_printk(KERN_ERR, hostdata->connected, "%s: End of DMA timeout\n", |
570 | __func__); | |
e9dbadf7 | 571 | |
99a974e6 | 572 | hostdata->pdma_residual = residual; |
e9dbadf7 | 573 | |
1da177e4 LT |
574 | return 0; |
575 | } | |
576 | ||
577 | /** | |
ab2ace2d | 578 | * generic_NCR5380_psend - pseudo DMA send |
24c43341 FT |
579 | * @hostdata: scsi host private data |
580 | * @src: buffer to read from | |
581 | * @len: transfer size | |
1da177e4 | 582 | * |
24c43341 | 583 | * Perform a pseudo DMA mode send to a 53C400 or equivalent device. |
1da177e4 LT |
584 | */ |
585 | ||
ab2ace2d FT |
586 | static inline int generic_NCR5380_psend(struct NCR5380_hostdata *hostdata, |
587 | unsigned char *src, int len) | |
1da177e4 | 588 | { |
99a974e6 | 589 | int residual; |
1da177e4 | 590 | int start = 0; |
1da177e4 | 591 | |
12150797 | 592 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); |
99a974e6 OZ |
593 | NCR5380_write(hostdata->c400_blk_cnt, len / 128); |
594 | ||
595 | do { | |
596 | if (NCR5380_poll_politely2(hostdata, hostdata->c400_ctl_status, | |
597 | CSR_HOST_BUF_NOT_RDY, 0, | |
598 | hostdata->c400_ctl_status, | |
599 | CSR_GATED_53C80_IRQ, | |
e7734ef1 | 600 | CSR_GATED_53C80_IRQ, 0) < 0 || |
99a974e6 OZ |
601 | NCR5380_read(hostdata->c400_ctl_status) & CSR_HOST_BUF_NOT_RDY) { |
602 | /* Both 128 B buffers are in use */ | |
603 | if (start >= 128) | |
604 | start -= 128; | |
605 | if (start >= 128) | |
606 | start -= 128; | |
607 | break; | |
608 | } | |
1da177e4 | 609 | |
99a974e6 | 610 | if (start >= len && NCR5380_read(hostdata->c400_blk_cnt) == 0) |
1da177e4 | 611 | break; |
b61bacbc | 612 | |
99a974e6 OZ |
613 | if (NCR5380_read(hostdata->c400_ctl_status) & CSR_GATED_53C80_IRQ) { |
614 | /* Host buffer is empty, other one is in use */ | |
615 | if (start >= 128) | |
616 | start -= 128; | |
617 | break; | |
618 | } | |
b61bacbc | 619 | |
99a974e6 OZ |
620 | if (start >= len) |
621 | continue; | |
1da177e4 | 622 | |
820682b1 FT |
623 | if (hostdata->io_port && hostdata->io_width == 2) |
624 | outsw(hostdata->io_port + hostdata->c400_host_buf, | |
24c43341 | 625 | src + start, 64); |
820682b1 FT |
626 | else if (hostdata->io_port) |
627 | outsb(hostdata->io_port + hostdata->c400_host_buf, | |
24c43341 | 628 | src + start, 128); |
b61bacbc | 629 | else |
820682b1 | 630 | memcpy_toio(hostdata->io + NCR53C400_host_buffer, |
b61bacbc | 631 | src + start, 128); |
1da177e4 | 632 | start += 128; |
99a974e6 | 633 | } while (1); |
1da177e4 | 634 | |
99a974e6 | 635 | residual = len - start; |
e9dbadf7 | 636 | |
99a974e6 OZ |
637 | if (residual != 0) { |
638 | /* 53c80 interrupt or transfer timeout. Reset 53c400 logic. */ | |
639 | NCR5380_write(hostdata->c400_ctl_status, CSR_RESET); | |
640 | NCR5380_write(hostdata->c400_ctl_status, CSR_BASE); | |
641 | } | |
642 | wait_for_53c80_access(hostdata); | |
643 | ||
644 | if (residual == 0) { | |
645 | if (NCR5380_poll_politely(hostdata, TARGET_COMMAND_REG, | |
646 | TCR_LAST_BYTE_SENT, TCR_LAST_BYTE_SENT, | |
e7734ef1 | 647 | 0) < 0) |
99a974e6 OZ |
648 | scmd_printk(KERN_ERR, hostdata->connected, |
649 | "%s: Last Byte Sent timeout\n", __func__); | |
650 | ||
651 | if (NCR5380_poll_politely(hostdata, BUS_AND_STATUS_REG, | |
652 | BASR_END_DMA_TRANSFER, BASR_END_DMA_TRANSFER, | |
e7734ef1 | 653 | 0) < 0) |
99a974e6 OZ |
654 | scmd_printk(KERN_ERR, hostdata->connected, "%s: End of DMA timeout\n", |
655 | __func__); | |
aeb51152 | 656 | } |
1da177e4 | 657 | |
99a974e6 | 658 | hostdata->pdma_residual = residual; |
e9dbadf7 | 659 | |
1da177e4 LT |
660 | return 0; |
661 | } | |
ff3d4578 | 662 | |
4a98f896 | 663 | static int generic_NCR5380_dma_xfer_len(struct NCR5380_hostdata *hostdata, |
7e9ec8d9 | 664 | struct scsi_cmnd *cmd) |
ff3d4578 | 665 | { |
ff1269cb | 666 | int transfersize = NCR5380_to_ncmd(cmd)->this_residual; |
ff3d4578 | 667 | |
7e9ec8d9 FT |
668 | if (hostdata->flags & FLAG_NO_PSEUDO_DMA) |
669 | return 0; | |
670 | ||
f0394621 OZ |
671 | /* 53C400 datasheet: non-modulo-128-byte transfers should use PIO */ |
672 | if (transfersize % 128) | |
facfc963 OZ |
673 | return 0; |
674 | ||
675 | /* Limit PDMA send to 512 B to avoid random corruption on DTC3181E */ | |
676 | if (hostdata->board == BOARD_DTC3181E && | |
677 | cmd->sc_data_direction == DMA_TO_DEVICE) | |
ff1269cb | 678 | transfersize = min(transfersize, 512); |
f0394621 | 679 | |
12b859b7 | 680 | return min(transfersize, DMA_MAX_SIZE); |
ff3d4578 FT |
681 | } |
682 | ||
e9dbadf7 OZ |
683 | static int generic_NCR5380_dma_residual(struct NCR5380_hostdata *hostdata) |
684 | { | |
685 | return hostdata->pdma_residual; | |
686 | } | |
687 | ||
24c43341 FT |
688 | /* Include the core driver code. */ |
689 | ||
1da177e4 LT |
690 | #include "NCR5380.c" |
691 | ||
bd5e469a | 692 | static const struct scsi_host_template driver_template = { |
a8cfbcae | 693 | .module = THIS_MODULE, |
aa2e2cb1 | 694 | .proc_name = DRV_MODULE_NAME, |
aa2e2cb1 | 695 | .name = "Generic NCR5380/NCR53C400 SCSI", |
aa2e2cb1 FT |
696 | .info = generic_NCR5380_info, |
697 | .queuecommand = generic_NCR5380_queue_command, | |
1da177e4 | 698 | .eh_abort_handler = generic_NCR5380_abort, |
12e5fc66 | 699 | .eh_host_reset_handler = generic_NCR5380_host_reset, |
aa2e2cb1 FT |
700 | .can_queue = 16, |
701 | .this_id = 7, | |
702 | .sg_tablesize = SG_ALL, | |
703 | .cmd_per_lun = 2, | |
4af14d11 | 704 | .dma_boundary = PAGE_SIZE - 1, |
cd614642 | 705 | .cmd_size = sizeof(struct NCR5380_cmd), |
0a4e3612 | 706 | .max_sectors = 128, |
1da177e4 | 707 | }; |
161c0059 | 708 | |
a8cfbcae OZ |
709 | static int generic_NCR5380_isa_match(struct device *pdev, unsigned int ndev) |
710 | { | |
711 | int ret = generic_NCR5380_init_one(&driver_template, pdev, base[ndev], | |
24c43341 | 712 | irq[ndev], card[ndev]); |
a8cfbcae OZ |
713 | if (ret) { |
714 | if (base[ndev]) | |
715 | printk(KERN_WARNING "Card not found at address 0x%03x\n", | |
716 | base[ndev]); | |
717 | return 0; | |
718 | } | |
1da177e4 | 719 | |
a8cfbcae OZ |
720 | return 1; |
721 | } | |
722 | ||
30e88d01 UKK |
723 | static void generic_NCR5380_isa_remove(struct device *pdev, |
724 | unsigned int ndev) | |
a8cfbcae OZ |
725 | { |
726 | generic_NCR5380_release_resources(dev_get_drvdata(pdev)); | |
727 | dev_set_drvdata(pdev, NULL); | |
a8cfbcae OZ |
728 | } |
729 | ||
730 | static struct isa_driver generic_NCR5380_isa_driver = { | |
731 | .match = generic_NCR5380_isa_match, | |
732 | .remove = generic_NCR5380_isa_remove, | |
733 | .driver = { | |
734 | .name = DRV_MODULE_NAME | |
735 | }, | |
736 | }; | |
737 | ||
b61bacbc | 738 | #ifdef CONFIG_PNP |
60747936 | 739 | static const struct pnp_device_id generic_NCR5380_pnp_ids[] = { |
a8cfbcae OZ |
740 | { .id = "DTC436e", .driver_data = BOARD_DTC3181E }, |
741 | { .id = "" } | |
742 | }; | |
743 | MODULE_DEVICE_TABLE(pnp, generic_NCR5380_pnp_ids); | |
744 | ||
745 | static int generic_NCR5380_pnp_probe(struct pnp_dev *pdev, | |
24c43341 | 746 | const struct pnp_device_id *id) |
a8cfbcae OZ |
747 | { |
748 | int base, irq; | |
749 | ||
750 | if (pnp_activate_dev(pdev) < 0) | |
751 | return -EBUSY; | |
752 | ||
753 | base = pnp_port_start(pdev, 0); | |
754 | irq = pnp_irq(pdev, 0); | |
755 | ||
756 | return generic_NCR5380_init_one(&driver_template, &pdev->dev, base, irq, | |
24c43341 | 757 | id->driver_data); |
a8cfbcae OZ |
758 | } |
759 | ||
760 | static void generic_NCR5380_pnp_remove(struct pnp_dev *pdev) | |
761 | { | |
762 | generic_NCR5380_release_resources(pnp_get_drvdata(pdev)); | |
763 | pnp_set_drvdata(pdev, NULL); | |
764 | } | |
765 | ||
766 | static struct pnp_driver generic_NCR5380_pnp_driver = { | |
767 | .name = DRV_MODULE_NAME, | |
768 | .id_table = generic_NCR5380_pnp_ids, | |
769 | .probe = generic_NCR5380_pnp_probe, | |
770 | .remove = generic_NCR5380_pnp_remove, | |
1da177e4 | 771 | }; |
b61bacbc | 772 | #endif /* defined(CONFIG_PNP) */ |
1da177e4 | 773 | |
a8cfbcae OZ |
774 | static int pnp_registered, isa_registered; |
775 | ||
776 | static int __init generic_NCR5380_init(void) | |
777 | { | |
778 | int ret = 0; | |
779 | ||
780 | /* compatibility with old-style parameters */ | |
70439e93 | 781 | if (irq[0] == -1 && base[0] == 0 && card[0] == -1) { |
a8cfbcae OZ |
782 | irq[0] = ncr_irq; |
783 | base[0] = ncr_addr; | |
784 | if (ncr_5380) | |
785 | card[0] = BOARD_NCR5380; | |
786 | if (ncr_53c400) | |
787 | card[0] = BOARD_NCR53C400; | |
788 | if (ncr_53c400a) | |
789 | card[0] = BOARD_NCR53C400A; | |
790 | if (dtc_3181e) | |
791 | card[0] = BOARD_DTC3181E; | |
792 | if (hp_c2502) | |
793 | card[0] = BOARD_HP_C2502; | |
794 | } | |
795 | ||
b61bacbc | 796 | #ifdef CONFIG_PNP |
a8cfbcae OZ |
797 | if (!pnp_register_driver(&generic_NCR5380_pnp_driver)) |
798 | pnp_registered = 1; | |
702a98c6 | 799 | #endif |
a8cfbcae OZ |
800 | ret = isa_register_driver(&generic_NCR5380_isa_driver, MAX_CARDS); |
801 | if (!ret) | |
802 | isa_registered = 1; | |
803 | ||
804 | return (pnp_registered || isa_registered) ? 0 : ret; | |
805 | } | |
806 | ||
807 | static void __exit generic_NCR5380_exit(void) | |
808 | { | |
b61bacbc | 809 | #ifdef CONFIG_PNP |
a8cfbcae OZ |
810 | if (pnp_registered) |
811 | pnp_unregister_driver(&generic_NCR5380_pnp_driver); | |
812 | #endif | |
813 | if (isa_registered) | |
814 | isa_unregister_driver(&generic_NCR5380_isa_driver); | |
815 | } | |
816 | ||
817 | module_init(generic_NCR5380_init); | |
818 | module_exit(generic_NCR5380_exit); |