Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
a87bf293 | 2 | /* esp_scsi.h: Defines and structures for the ESP driver. |
cd9ad58d DM |
3 | * |
4 | * Copyright (C) 2007 David S. Miller (davem@davemloft.net) | |
5 | */ | |
6 | ||
7 | #ifndef _ESP_SCSI_H | |
8 | #define _ESP_SCSI_H | |
9 | ||
10 | /* Access Description Offset */ | |
11 | #define ESP_TCLOW 0x00UL /* rw Low bits transfer count 0x00 */ | |
12 | #define ESP_TCMED 0x01UL /* rw Mid bits transfer count 0x04 */ | |
13 | #define ESP_FDATA 0x02UL /* rw FIFO data bits 0x08 */ | |
14 | #define ESP_CMD 0x03UL /* rw SCSI command bits 0x0c */ | |
15 | #define ESP_STATUS 0x04UL /* ro ESP status register 0x10 */ | |
16 | #define ESP_BUSID ESP_STATUS /* wo BusID for sel/resel 0x10 */ | |
17 | #define ESP_INTRPT 0x05UL /* ro Kind of interrupt 0x14 */ | |
18 | #define ESP_TIMEO ESP_INTRPT /* wo Timeout for sel/resel 0x14 */ | |
19 | #define ESP_SSTEP 0x06UL /* ro Sequence step register 0x18 */ | |
20 | #define ESP_STP ESP_SSTEP /* wo Transfer period/sync 0x18 */ | |
21 | #define ESP_FFLAGS 0x07UL /* ro Bits current FIFO info 0x1c */ | |
22 | #define ESP_SOFF ESP_FFLAGS /* wo Sync offset 0x1c */ | |
23 | #define ESP_CFG1 0x08UL /* rw First cfg register 0x20 */ | |
24 | #define ESP_CFACT 0x09UL /* wo Clock conv factor 0x24 */ | |
25 | #define ESP_STATUS2 ESP_CFACT /* ro HME status2 register 0x24 */ | |
26 | #define ESP_CTEST 0x0aUL /* wo Chip test register 0x28 */ | |
27 | #define ESP_CFG2 0x0bUL /* rw Second cfg register 0x2c */ | |
28 | #define ESP_CFG3 0x0cUL /* rw Third cfg register 0x30 */ | |
eeea2f9c | 29 | #define ESP_CFG4 0x0dUL /* rw Fourth cfg register 0x34 */ |
cd9ad58d DM |
30 | #define ESP_TCHI 0x0eUL /* rw High bits transf count 0x38 */ |
31 | #define ESP_UID ESP_TCHI /* ro Unique ID code 0x38 */ | |
32 | #define FAS_RLO ESP_TCHI /* rw HME extended counter 0x38 */ | |
33 | #define ESP_FGRND 0x0fUL /* rw Data base for fifo 0x3c */ | |
34 | #define FAS_RHI ESP_FGRND /* rw HME extended counter 0x3c */ | |
35 | ||
36 | #define SBUS_ESP_REG_SIZE 0x40UL | |
37 | ||
38 | /* Bitfield meanings for the above registers. */ | |
39 | ||
40 | /* ESP config reg 1, read-write, found on all ESP chips */ | |
41 | #define ESP_CONFIG1_ID 0x07 /* My BUS ID bits */ | |
42 | #define ESP_CONFIG1_CHTEST 0x08 /* Enable ESP chip tests */ | |
43 | #define ESP_CONFIG1_PENABLE 0x10 /* Enable parity checks */ | |
44 | #define ESP_CONFIG1_PARTEST 0x20 /* Parity test mode enabled? */ | |
45 | #define ESP_CONFIG1_SRRDISAB 0x40 /* Disable SCSI reset reports */ | |
46 | #define ESP_CONFIG1_SLCABLE 0x80 /* Enable slow cable mode */ | |
47 | ||
48 | /* ESP config reg 2, read-write, found only on esp100a+esp200+esp236 chips */ | |
49 | #define ESP_CONFIG2_DMAPARITY 0x01 /* enable DMA Parity (200,236) */ | |
50 | #define ESP_CONFIG2_REGPARITY 0x02 /* enable reg Parity (200,236) */ | |
51 | #define ESP_CONFIG2_BADPARITY 0x04 /* Bad parity target abort */ | |
52 | #define ESP_CONFIG2_SCSI2ENAB 0x08 /* Enable SCSI-2 features (tgtmode) */ | |
53 | #define ESP_CONFIG2_HI 0x10 /* High Impedance DREQ ??? */ | |
54 | #define ESP_CONFIG2_HMEFENAB 0x10 /* HME features enable */ | |
55 | #define ESP_CONFIG2_BCM 0x20 /* Enable byte-ctrl (236) */ | |
56 | #define ESP_CONFIG2_DISPINT 0x20 /* Disable pause irq (hme) */ | |
57 | #define ESP_CONFIG2_FENAB 0x40 /* Enable features (fas100,216) */ | |
58 | #define ESP_CONFIG2_SPL 0x40 /* Enable status-phase latch (236) */ | |
59 | #define ESP_CONFIG2_MKDONE 0x40 /* HME magic feature */ | |
60 | #define ESP_CONFIG2_HME32 0x80 /* HME 32 extended */ | |
61 | #define ESP_CONFIG2_MAGIC 0xe0 /* Invalid bits... */ | |
62 | ||
63 | /* ESP config register 3 read-write, found only esp236+fas236+fas100a+hme chips */ | |
64 | #define ESP_CONFIG3_FCLOCK 0x01 /* FAST SCSI clock rate (esp100a/hme) */ | |
65 | #define ESP_CONFIG3_TEM 0x01 /* Enable thresh-8 mode (esp/fas236) */ | |
66 | #define ESP_CONFIG3_FAST 0x02 /* Enable FAST SCSI (esp100a/hme) */ | |
67 | #define ESP_CONFIG3_ADMA 0x02 /* Enable alternate-dma (esp/fas236) */ | |
68 | #define ESP_CONFIG3_TENB 0x04 /* group2 SCSI2 support (esp100a/hme) */ | |
69 | #define ESP_CONFIG3_SRB 0x04 /* Save residual byte (esp/fas236) */ | |
70 | #define ESP_CONFIG3_TMS 0x08 /* Three-byte msg's ok (esp100a/hme) */ | |
71 | #define ESP_CONFIG3_FCLK 0x08 /* Fast SCSI clock rate (esp/fas236) */ | |
72 | #define ESP_CONFIG3_IDMSG 0x10 /* ID message checking (esp100a/hme) */ | |
73 | #define ESP_CONFIG3_FSCSI 0x10 /* Enable FAST SCSI (esp/fas236) */ | |
74 | #define ESP_CONFIG3_GTM 0x20 /* group2 SCSI2 support (esp/fas236) */ | |
75 | #define ESP_CONFIG3_IDBIT3 0x20 /* Bit 3 of HME SCSI-ID (hme) */ | |
76 | #define ESP_CONFIG3_TBMS 0x40 /* Three-byte msg's ok (esp/fas236) */ | |
77 | #define ESP_CONFIG3_EWIDE 0x40 /* Enable Wide-SCSI (hme) */ | |
78 | #define ESP_CONFIG3_IMS 0x80 /* ID msg chk'ng (esp/fas236) */ | |
79 | #define ESP_CONFIG3_OBPUSH 0x80 /* Push odd-byte to dma (hme) */ | |
80 | ||
eeea2f9c HR |
81 | /* ESP config register 4 read-write, found only on am53c974 chips */ |
82 | #define ESP_CONFIG4_RADE 0x04 /* Active negation */ | |
83 | #define ESP_CONFIG4_RAE 0x08 /* Active negation on REQ and ACK */ | |
84 | #define ESP_CONFIG4_PWD 0x20 /* Reduced power feature */ | |
85 | #define ESP_CONFIG4_GE0 0x40 /* Glitch eater bit 0 */ | |
86 | #define ESP_CONFIG4_GE1 0x80 /* Glitch eater bit 1 */ | |
87 | ||
88 | #define ESP_CONFIG_GE_12NS (0) | |
89 | #define ESP_CONFIG_GE_25NS (ESP_CONFIG_GE1) | |
90 | #define ESP_CONFIG_GE_35NS (ESP_CONFIG_GE0) | |
91 | #define ESP_CONFIG_GE_0NS (ESP_CONFIG_GE0 | ESP_CONFIG_GE1) | |
92 | ||
cd9ad58d DM |
93 | /* ESP command register read-write */ |
94 | /* Group 1 commands: These may be sent at any point in time to the ESP | |
95 | * chip. None of them can generate interrupts 'cept | |
96 | * the "SCSI bus reset" command if you have not disabled | |
97 | * SCSI reset interrupts in the config1 ESP register. | |
98 | */ | |
99 | #define ESP_CMD_NULL 0x00 /* Null command, ie. a nop */ | |
100 | #define ESP_CMD_FLUSH 0x01 /* FIFO Flush */ | |
101 | #define ESP_CMD_RC 0x02 /* Chip reset */ | |
102 | #define ESP_CMD_RS 0x03 /* SCSI bus reset */ | |
103 | ||
104 | /* Group 2 commands: ESP must be an initiator and connected to a target | |
105 | * for these commands to work. | |
106 | */ | |
107 | #define ESP_CMD_TI 0x10 /* Transfer Information */ | |
108 | #define ESP_CMD_ICCSEQ 0x11 /* Initiator cmd complete sequence */ | |
109 | #define ESP_CMD_MOK 0x12 /* Message okie-dokie */ | |
110 | #define ESP_CMD_TPAD 0x18 /* Transfer Pad */ | |
111 | #define ESP_CMD_SATN 0x1a /* Set ATN */ | |
112 | #define ESP_CMD_RATN 0x1b /* De-assert ATN */ | |
113 | ||
114 | /* Group 3 commands: ESP must be in the MSGOUT or MSGIN state and be connected | |
115 | * to a target as the initiator for these commands to work. | |
116 | */ | |
117 | #define ESP_CMD_SMSG 0x20 /* Send message */ | |
118 | #define ESP_CMD_SSTAT 0x21 /* Send status */ | |
119 | #define ESP_CMD_SDATA 0x22 /* Send data */ | |
120 | #define ESP_CMD_DSEQ 0x23 /* Discontinue Sequence */ | |
121 | #define ESP_CMD_TSEQ 0x24 /* Terminate Sequence */ | |
122 | #define ESP_CMD_TCCSEQ 0x25 /* Target cmd cmplt sequence */ | |
123 | #define ESP_CMD_DCNCT 0x27 /* Disconnect */ | |
124 | #define ESP_CMD_RMSG 0x28 /* Receive Message */ | |
125 | #define ESP_CMD_RCMD 0x29 /* Receive Command */ | |
126 | #define ESP_CMD_RDATA 0x2a /* Receive Data */ | |
127 | #define ESP_CMD_RCSEQ 0x2b /* Receive cmd sequence */ | |
128 | ||
129 | /* Group 4 commands: The ESP must be in the disconnected state and must | |
130 | * not be connected to any targets as initiator for | |
131 | * these commands to work. | |
132 | */ | |
133 | #define ESP_CMD_RSEL 0x40 /* Reselect */ | |
134 | #define ESP_CMD_SEL 0x41 /* Select w/o ATN */ | |
135 | #define ESP_CMD_SELA 0x42 /* Select w/ATN */ | |
136 | #define ESP_CMD_SELAS 0x43 /* Select w/ATN & STOP */ | |
137 | #define ESP_CMD_ESEL 0x44 /* Enable selection */ | |
138 | #define ESP_CMD_DSEL 0x45 /* Disable selections */ | |
139 | #define ESP_CMD_SA3 0x46 /* Select w/ATN3 */ | |
140 | #define ESP_CMD_RSEL3 0x47 /* Reselect3 */ | |
141 | ||
142 | /* This bit enables the ESP's DMA on the SBus */ | |
143 | #define ESP_CMD_DMA 0x80 /* Do DMA? */ | |
144 | ||
145 | /* ESP status register read-only */ | |
146 | #define ESP_STAT_PIO 0x01 /* IO phase bit */ | |
147 | #define ESP_STAT_PCD 0x02 /* CD phase bit */ | |
148 | #define ESP_STAT_PMSG 0x04 /* MSG phase bit */ | |
149 | #define ESP_STAT_PMASK 0x07 /* Mask of phase bits */ | |
150 | #define ESP_STAT_TDONE 0x08 /* Transfer Completed */ | |
151 | #define ESP_STAT_TCNT 0x10 /* Transfer Counter Is Zero */ | |
152 | #define ESP_STAT_PERR 0x20 /* Parity error */ | |
153 | #define ESP_STAT_SPAM 0x40 /* Real bad error */ | |
154 | /* This indicates the 'interrupt pending' condition on esp236, it is a reserved | |
155 | * bit on other revs of the ESP. | |
156 | */ | |
157 | #define ESP_STAT_INTR 0x80 /* Interrupt */ | |
158 | ||
159 | /* The status register can be masked with ESP_STAT_PMASK and compared | |
160 | * with the following values to determine the current phase the ESP | |
161 | * (at least thinks it) is in. For our purposes we also add our own | |
162 | * software 'done' bit for our phase management engine. | |
163 | */ | |
164 | #define ESP_DOP (0) /* Data Out */ | |
165 | #define ESP_DIP (ESP_STAT_PIO) /* Data In */ | |
166 | #define ESP_CMDP (ESP_STAT_PCD) /* Command */ | |
167 | #define ESP_STATP (ESP_STAT_PCD|ESP_STAT_PIO) /* Status */ | |
168 | #define ESP_MOP (ESP_STAT_PMSG|ESP_STAT_PCD) /* Message Out */ | |
169 | #define ESP_MIP (ESP_STAT_PMSG|ESP_STAT_PCD|ESP_STAT_PIO) /* Message In */ | |
170 | ||
171 | /* HME only: status 2 register */ | |
172 | #define ESP_STAT2_SCHBIT 0x01 /* Upper bits 3-7 of sstep enabled */ | |
173 | #define ESP_STAT2_FFLAGS 0x02 /* The fifo flags are now latched */ | |
174 | #define ESP_STAT2_XCNT 0x04 /* The transfer counter is latched */ | |
175 | #define ESP_STAT2_CREGA 0x08 /* The command reg is active now */ | |
176 | #define ESP_STAT2_WIDE 0x10 /* Interface on this adapter is wide */ | |
177 | #define ESP_STAT2_F1BYTE 0x20 /* There is one byte at top of fifo */ | |
178 | #define ESP_STAT2_FMSB 0x40 /* Next byte in fifo is most significant */ | |
179 | #define ESP_STAT2_FEMPTY 0x80 /* FIFO is empty */ | |
180 | ||
181 | /* ESP interrupt register read-only */ | |
182 | #define ESP_INTR_S 0x01 /* Select w/o ATN */ | |
183 | #define ESP_INTR_SATN 0x02 /* Select w/ATN */ | |
184 | #define ESP_INTR_RSEL 0x04 /* Reselected */ | |
185 | #define ESP_INTR_FDONE 0x08 /* Function done */ | |
186 | #define ESP_INTR_BSERV 0x10 /* Bus service */ | |
187 | #define ESP_INTR_DC 0x20 /* Disconnect */ | |
188 | #define ESP_INTR_IC 0x40 /* Illegal command given */ | |
189 | #define ESP_INTR_SR 0x80 /* SCSI bus reset detected */ | |
190 | ||
191 | /* ESP sequence step register read-only */ | |
192 | #define ESP_STEP_VBITS 0x07 /* Valid bits */ | |
193 | #define ESP_STEP_ASEL 0x00 /* Selection&Arbitrate cmplt */ | |
194 | #define ESP_STEP_SID 0x01 /* One msg byte sent */ | |
195 | #define ESP_STEP_NCMD 0x02 /* Was not in command phase */ | |
196 | #define ESP_STEP_PPC 0x03 /* Early phase chg caused cmnd | |
197 | * bytes to be lost | |
198 | */ | |
199 | #define ESP_STEP_FINI4 0x04 /* Command was sent ok */ | |
200 | ||
201 | /* Ho hum, some ESP's set the step register to this as well... */ | |
202 | #define ESP_STEP_FINI5 0x05 | |
203 | #define ESP_STEP_FINI6 0x06 | |
204 | #define ESP_STEP_FINI7 0x07 | |
205 | ||
206 | /* ESP chip-test register read-write */ | |
207 | #define ESP_TEST_TARG 0x01 /* Target test mode */ | |
208 | #define ESP_TEST_INI 0x02 /* Initiator test mode */ | |
209 | #define ESP_TEST_TS 0x04 /* Tristate test mode */ | |
210 | ||
211 | /* ESP unique ID register read-only, found on fas236+fas100a only */ | |
212 | #define ESP_UID_F100A 0x00 /* ESP FAS100A */ | |
213 | #define ESP_UID_F236 0x02 /* ESP FAS236 */ | |
214 | #define ESP_UID_REV 0x07 /* ESP revision */ | |
215 | #define ESP_UID_FAM 0xf8 /* ESP family */ | |
216 | ||
217 | /* ESP fifo flags register read-only */ | |
218 | /* Note that the following implies a 16 byte FIFO on the ESP. */ | |
219 | #define ESP_FF_FBYTES 0x1f /* Num bytes in FIFO */ | |
220 | #define ESP_FF_ONOTZERO 0x20 /* offset ctr not zero (esp100) */ | |
221 | #define ESP_FF_SSTEP 0xe0 /* Sequence step */ | |
222 | ||
223 | /* ESP clock conversion factor register write-only */ | |
224 | #define ESP_CCF_F0 0x00 /* 35.01MHz - 40MHz */ | |
225 | #define ESP_CCF_NEVER 0x01 /* Set it to this and die */ | |
226 | #define ESP_CCF_F2 0x02 /* 10MHz */ | |
227 | #define ESP_CCF_F3 0x03 /* 10.01MHz - 15MHz */ | |
228 | #define ESP_CCF_F4 0x04 /* 15.01MHz - 20MHz */ | |
229 | #define ESP_CCF_F5 0x05 /* 20.01MHz - 25MHz */ | |
230 | #define ESP_CCF_F6 0x06 /* 25.01MHz - 30MHz */ | |
231 | #define ESP_CCF_F7 0x07 /* 30.01MHz - 35MHz */ | |
232 | ||
233 | /* HME only... */ | |
234 | #define ESP_BUSID_RESELID 0x10 | |
235 | #define ESP_BUSID_CTR32BIT 0x40 | |
236 | ||
96d32215 | 237 | #define ESP_BUS_TIMEOUT 250 /* In milli-seconds */ |
cd9ad58d DM |
238 | #define ESP_TIMEO_CONST 8192 |
239 | #define ESP_NEG_DEFP(mhz, cfact) \ | |
240 | ((ESP_BUS_TIMEOUT * ((mhz) / 1000)) / (8192 * (cfact))) | |
6fe07aaf | 241 | #define ESP_HZ_TO_CYCLE(hertz) ((1000000000) / ((hertz) / 1000)) |
cd9ad58d DM |
242 | #define ESP_TICK(ccf, cycle) ((7682 * (ccf) * (cycle) / 1000)) |
243 | ||
244 | /* For slow to medium speed input clock rates we shoot for 5mb/s, but for high | |
245 | * input clock rates we try to do 10mb/s although I don't think a transfer can | |
246 | * even run that fast with an ESP even with DMA2 scatter gather pipelining. | |
247 | */ | |
248 | #define SYNC_DEFP_SLOW 0x32 /* 5mb/s */ | |
249 | #define SYNC_DEFP_FAST 0x19 /* 10mb/s */ | |
250 | ||
251 | struct esp_cmd_priv { | |
86117d7f | 252 | int num_sg; |
582fb6c0 | 253 | int cur_residue; |
ee5a1dbf | 254 | struct scatterlist *prv_sg; |
cd9ad58d | 255 | struct scatterlist *cur_sg; |
582fb6c0 | 256 | int tot_residue; |
cd9ad58d DM |
257 | }; |
258 | #define ESP_CMD_PRIV(CMD) ((struct esp_cmd_priv *)(&(CMD)->SCp)) | |
259 | ||
260 | enum esp_rev { | |
261 | ESP100 = 0x00, /* NCR53C90 - very broken */ | |
262 | ESP100A = 0x01, /* NCR53C90A */ | |
263 | ESP236 = 0x02, | |
264 | FAS236 = 0x03, | |
265 | FAS100A = 0x04, | |
266 | FAST = 0x05, | |
267 | FASHME = 0x06, | |
eeea2f9c | 268 | PCSCSI = 0x07, /* AM53c974 */ |
cd9ad58d DM |
269 | }; |
270 | ||
271 | struct esp_cmd_entry { | |
272 | struct list_head list; | |
273 | ||
274 | struct scsi_cmnd *cmd; | |
275 | ||
276 | unsigned int saved_cur_residue; | |
ee5a1dbf | 277 | struct scatterlist *saved_prv_sg; |
cd9ad58d DM |
278 | struct scatterlist *saved_cur_sg; |
279 | unsigned int saved_tot_residue; | |
280 | ||
281 | u8 flags; | |
282 | #define ESP_CMD_FLAG_WRITE 0x01 /* DMA is a write */ | |
cd9ad58d | 283 | #define ESP_CMD_FLAG_AUTOSENSE 0x04 /* Doing automatic REQUEST_SENSE */ |
6df388f2 | 284 | #define ESP_CMD_FLAG_RESIDUAL 0x08 /* AM53c974 BLAST residual */ |
cd9ad58d DM |
285 | |
286 | u8 tag[2]; | |
21af8107 | 287 | u8 orig_tag[2]; |
cd9ad58d DM |
288 | |
289 | u8 status; | |
290 | u8 message; | |
291 | ||
292 | unsigned char *sense_ptr; | |
293 | unsigned char *saved_sense_ptr; | |
294 | dma_addr_t sense_dma; | |
295 | ||
296 | struct completion *eh_done; | |
297 | }; | |
298 | ||
cd9ad58d DM |
299 | #define ESP_DEFAULT_TAGS 16 |
300 | ||
301 | #define ESP_MAX_TARGET 16 | |
302 | #define ESP_MAX_LUN 8 | |
303 | #define ESP_MAX_TAG 256 | |
304 | ||
305 | struct esp_lun_data { | |
306 | struct esp_cmd_entry *non_tagged_cmd; | |
307 | int num_tagged; | |
308 | int hold; | |
309 | struct esp_cmd_entry *tagged_cmds[ESP_MAX_TAG]; | |
310 | }; | |
311 | ||
312 | struct esp_target_data { | |
313 | /* These are the ESP_STP, ESP_SOFF, and ESP_CFG3 register values which | |
314 | * match the currently negotiated settings for this target. The SCSI | |
315 | * protocol values are maintained in spi_{offset,period,wide}(starget). | |
316 | */ | |
317 | u8 esp_period; | |
318 | u8 esp_offset; | |
319 | u8 esp_config3; | |
320 | ||
321 | u8 flags; | |
322 | #define ESP_TGT_WIDE 0x01 | |
323 | #define ESP_TGT_DISCONNECT 0x02 | |
324 | #define ESP_TGT_NEGO_WIDE 0x04 | |
325 | #define ESP_TGT_NEGO_SYNC 0x08 | |
326 | #define ESP_TGT_CHECK_NEGO 0x40 | |
327 | #define ESP_TGT_BROKEN 0x80 | |
328 | ||
329 | /* When ESP_TGT_CHECK_NEGO is set, on the next scsi command to this | |
330 | * device we will try to negotiate the following parameters. | |
331 | */ | |
332 | u8 nego_goal_period; | |
333 | u8 nego_goal_offset; | |
334 | u8 nego_goal_width; | |
335 | u8 nego_goal_tags; | |
336 | ||
337 | struct scsi_target *starget; | |
338 | }; | |
339 | ||
340 | struct esp_event_ent { | |
341 | u8 type; | |
342 | #define ESP_EVENT_TYPE_EVENT 0x01 | |
343 | #define ESP_EVENT_TYPE_CMD 0x02 | |
344 | u8 val; | |
345 | ||
346 | u8 sreg; | |
347 | u8 seqreg; | |
348 | u8 sreg2; | |
349 | u8 ireg; | |
350 | u8 select_state; | |
351 | u8 event; | |
352 | u8 __pad; | |
353 | }; | |
354 | ||
355 | struct esp; | |
356 | struct esp_driver_ops { | |
357 | /* Read and write the ESP 8-bit registers. On some | |
358 | * applications of the ESP chip the registers are at 4-byte | |
359 | * instead of 1-byte intervals. | |
360 | */ | |
361 | void (*esp_write8)(struct esp *esp, u8 val, unsigned long reg); | |
362 | u8 (*esp_read8)(struct esp *esp, unsigned long reg); | |
363 | ||
cd9ad58d DM |
364 | /* Return non-zero if there is an IRQ pending. Usually this |
365 | * status bit lives in the DMA controller sitting in front of | |
366 | * the ESP. This has to be accurate or else the ESP interrupt | |
367 | * handler will not run. | |
368 | */ | |
369 | int (*irq_pending)(struct esp *esp); | |
370 | ||
6fe07aaf FT |
371 | /* Return the maximum allowable size of a DMA transfer for a |
372 | * given buffer. | |
373 | */ | |
374 | u32 (*dma_length_limit)(struct esp *esp, u32 dma_addr, | |
375 | u32 dma_len); | |
376 | ||
cd9ad58d DM |
377 | /* Reset the DMA engine entirely. On return, ESP interrupts |
378 | * should be enabled. Often the interrupt enabling is | |
379 | * controlled in the DMA engine. | |
380 | */ | |
381 | void (*reset_dma)(struct esp *esp); | |
382 | ||
383 | /* Drain any pending DMA in the DMA engine after a transfer. | |
384 | * This is for writes to memory. | |
385 | */ | |
386 | void (*dma_drain)(struct esp *esp); | |
387 | ||
388 | /* Invalidate the DMA engine after a DMA transfer. */ | |
389 | void (*dma_invalidate)(struct esp *esp); | |
390 | ||
391 | /* Setup an ESP command that will use a DMA transfer. | |
392 | * The 'esp_count' specifies what transfer length should be | |
393 | * programmed into the ESP transfer counter registers, whereas | |
394 | * the 'dma_count' is the length that should be programmed into | |
395 | * the DMA controller. Usually they are the same. If 'write' | |
396 | * is non-zero, this transfer is a write into memory. 'cmd' | |
397 | * holds the ESP command that should be issued by calling | |
398 | * scsi_esp_cmd() at the appropriate time while programming | |
399 | * the DMA hardware. | |
400 | */ | |
401 | void (*send_dma_cmd)(struct esp *esp, u32 dma_addr, u32 esp_count, | |
402 | u32 dma_count, int write, u8 cmd); | |
403 | ||
404 | /* Return non-zero if the DMA engine is reporting an error | |
405 | * currently. | |
406 | */ | |
407 | int (*dma_error)(struct esp *esp); | |
408 | }; | |
409 | ||
410 | #define ESP_MAX_MSG_SZ 8 | |
411 | #define ESP_EVENT_LOG_SZ 32 | |
412 | ||
413 | #define ESP_QUICKIRQ_LIMIT 100 | |
414 | #define ESP_RESELECT_TAG_LIMIT 2500 | |
415 | ||
416 | struct esp { | |
417 | void __iomem *regs; | |
418 | void __iomem *dma_regs; | |
419 | ||
420 | const struct esp_driver_ops *ops; | |
421 | ||
422 | struct Scsi_Host *host; | |
98cda6a2 | 423 | struct device *dev; |
cd9ad58d DM |
424 | |
425 | struct esp_cmd_entry *active_cmd; | |
426 | ||
427 | struct list_head queued_cmds; | |
428 | struct list_head active_cmds; | |
429 | ||
430 | u8 *command_block; | |
431 | dma_addr_t command_block_dma; | |
432 | ||
433 | unsigned int data_dma_len; | |
434 | ||
435 | /* The following are used to determine the cause of an IRQ. Upon every | |
436 | * IRQ entry we synchronize these with the hardware registers. | |
437 | */ | |
438 | u8 sreg; | |
439 | u8 seqreg; | |
440 | u8 sreg2; | |
441 | u8 ireg; | |
442 | ||
443 | u32 prev_hme_dmacsr; | |
444 | u8 prev_soff; | |
445 | u8 prev_stp; | |
446 | u8 prev_cfg3; | |
3707a186 | 447 | u8 num_tags; |
cd9ad58d DM |
448 | |
449 | struct list_head esp_cmd_pool; | |
450 | ||
451 | struct esp_target_data target[ESP_MAX_TARGET]; | |
452 | ||
453 | int fifo_cnt; | |
454 | u8 fifo[16]; | |
455 | ||
456 | struct esp_event_ent esp_event_log[ESP_EVENT_LOG_SZ]; | |
457 | int esp_event_cur; | |
458 | ||
459 | u8 msg_out[ESP_MAX_MSG_SZ]; | |
460 | int msg_out_len; | |
461 | ||
462 | u8 msg_in[ESP_MAX_MSG_SZ]; | |
463 | int msg_in_len; | |
464 | ||
465 | u8 bursts; | |
466 | u8 config1; | |
467 | u8 config2; | |
eeea2f9c | 468 | u8 config4; |
cd9ad58d DM |
469 | |
470 | u8 scsi_id; | |
471 | u32 scsi_id_mask; | |
472 | ||
473 | enum esp_rev rev; | |
474 | ||
475 | u32 flags; | |
476 | #define ESP_FLAG_DIFFERENTIAL 0x00000001 | |
477 | #define ESP_FLAG_RESETTING 0x00000002 | |
cd9ad58d DM |
478 | #define ESP_FLAG_WIDE_CAPABLE 0x00000008 |
479 | #define ESP_FLAG_QUICKIRQ_CHECK 0x00000010 | |
6fe07aaf | 480 | #define ESP_FLAG_DISABLE_SYNC 0x00000020 |
3170866f | 481 | #define ESP_FLAG_USE_FIFO 0x00000040 |
3f9295b6 | 482 | #define ESP_FLAG_NO_DMA_MAP 0x00000080 |
cd9ad58d DM |
483 | |
484 | u8 select_state; | |
485 | #define ESP_SELECT_NONE 0x00 /* Not selecting */ | |
486 | #define ESP_SELECT_BASIC 0x01 /* Select w/o MSGOUT phase */ | |
487 | #define ESP_SELECT_MSGOUT 0x02 /* Select with MSGOUT */ | |
488 | ||
489 | /* When we are not selecting, we are expecting an event. */ | |
490 | u8 event; | |
491 | #define ESP_EVENT_NONE 0x00 | |
492 | #define ESP_EVENT_CMD_START 0x01 | |
493 | #define ESP_EVENT_CMD_DONE 0x02 | |
494 | #define ESP_EVENT_DATA_IN 0x03 | |
495 | #define ESP_EVENT_DATA_OUT 0x04 | |
496 | #define ESP_EVENT_DATA_DONE 0x05 | |
497 | #define ESP_EVENT_MSGIN 0x06 | |
498 | #define ESP_EVENT_MSGIN_MORE 0x07 | |
499 | #define ESP_EVENT_MSGIN_DONE 0x08 | |
500 | #define ESP_EVENT_MSGOUT 0x09 | |
501 | #define ESP_EVENT_MSGOUT_DONE 0x0a | |
502 | #define ESP_EVENT_STATUS 0x0b | |
503 | #define ESP_EVENT_FREE_BUS 0x0c | |
504 | #define ESP_EVENT_CHECK_PHASE 0x0d | |
505 | #define ESP_EVENT_RESET 0x10 | |
506 | ||
507 | /* Probed in esp_get_clock_params() */ | |
508 | u32 cfact; | |
509 | u32 cfreq; | |
510 | u32 ccycle; | |
511 | u32 ctick; | |
512 | u32 neg_defp; | |
513 | u32 sync_defp; | |
514 | ||
515 | /* Computed in esp_reset_esp() */ | |
516 | u32 max_period; | |
517 | u32 min_period; | |
518 | u32 radelay; | |
519 | ||
8bca2143 | 520 | /* ESP_CMD_SELAS command state */ |
cd9ad58d DM |
521 | u8 *cmd_bytes_ptr; |
522 | int cmd_bytes_left; | |
523 | ||
524 | struct completion *eh_reset; | |
525 | ||
334ae614 DM |
526 | void *dma; |
527 | int dmarev; | |
fd47d919 | 528 | |
53dce332 FT |
529 | /* These are used by esp_send_pio_cmd() */ |
530 | u8 __iomem *fifo_reg; | |
531 | int send_cmd_error; | |
fd47d919 | 532 | u32 send_cmd_residual; |
cd9ad58d DM |
533 | }; |
534 | ||
cd9ad58d DM |
535 | /* A front-end driver for the ESP chip should do the following in |
536 | * it's device probe routine: | |
537 | * 1) Allocate the host and private area using scsi_host_alloc() | |
538 | * with size 'sizeof(struct esp)'. The first argument to | |
539 | * scsi_host_alloc() should be &scsi_esp_template. | |
540 | * 2) Set host->max_id as appropriate. | |
541 | * 3) Set esp->host to the scsi_host itself, and esp->dev | |
542 | * to the device object pointer. | |
543 | * 4) Hook up esp->ops to the front-end implementation. | |
544 | * 5) If the ESP chip supports wide transfers, set ESP_FLAG_WIDE_CAPABLE | |
545 | * in esp->flags. | |
546 | * 6) Map the DMA and ESP chip registers. | |
547 | * 7) DMA map the ESP command block, store the DMA address | |
548 | * in esp->command_block_dma. | |
549 | * 8) Register the scsi_esp_intr() interrupt handler. | |
550 | * 9) Probe for and provide the following chip properties: | |
551 | * esp->scsi_id (assign to esp->host->this_id too) | |
552 | * esp->scsi_id_mask | |
553 | * If ESP bus is differential, set ESP_FLAG_DIFFERENTIAL | |
554 | * esp->cfreq | |
555 | * DMA burst bit mask in esp->bursts, if necessary | |
556 | * 10) Perform any actions necessary before the ESP device can | |
557 | * be programmed for the first time. On some configs, for | |
558 | * example, the DMA engine has to be reset before ESP can | |
559 | * be programmed. | |
560 | * 11) If necessary, call dev_set_drvdata() as needed. | |
44b1b4d2 | 561 | * 12) Call scsi_esp_register() with prepared 'esp' structure. |
cd9ad58d DM |
562 | * 13) Check scsi_esp_register() return value, release all resources |
563 | * if an error was returned. | |
564 | */ | |
565 | extern struct scsi_host_template scsi_esp_template; | |
44b1b4d2 | 566 | extern int scsi_esp_register(struct esp *); |
cd9ad58d DM |
567 | |
568 | extern void scsi_esp_unregister(struct esp *); | |
569 | extern irqreturn_t scsi_esp_intr(int, void *); | |
570 | extern void scsi_esp_cmd(struct esp *, u8); | |
571 | ||
53dce332 FT |
572 | extern void esp_send_pio_cmd(struct esp *esp, u32 dma_addr, u32 esp_count, |
573 | u32 dma_count, int write, u8 cmd); | |
574 | ||
cd9ad58d | 575 | #endif /* !(_ESP_SCSI_H) */ |