Commit | Line | Data |
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c21e0bbf MO |
1 | /* |
2 | * CXL Flash Device Driver | |
3 | * | |
4 | * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation | |
5 | * Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation | |
6 | * | |
7 | * Copyright (C) 2015 IBM Corporation | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License | |
11 | * as published by the Free Software Foundation; either version | |
12 | * 2 of the License, or (at your option) any later version. | |
13 | */ | |
14 | ||
15 | #ifndef _CXLFLASH_MAIN_H | |
16 | #define _CXLFLASH_MAIN_H | |
17 | ||
18 | #include <linux/list.h> | |
19 | #include <linux/types.h> | |
20 | #include <scsi/scsi.h> | |
21 | #include <scsi/scsi_device.h> | |
22 | ||
de5d35af UK |
23 | #include "backend.h" |
24 | ||
c21e0bbf MO |
25 | #define CXLFLASH_NAME "cxlflash" |
26 | #define CXLFLASH_ADAPTER_NAME "IBM POWER CXL Flash Adapter" | |
a834a36b | 27 | #define CXLFLASH_MAX_ADAPTERS 32 |
c21e0bbf | 28 | |
a2746fb1 MK |
29 | #define PCI_DEVICE_ID_IBM_CORSA 0x04F0 |
30 | #define PCI_DEVICE_ID_IBM_FLASH_GT 0x0600 | |
94344520 | 31 | #define PCI_DEVICE_ID_IBM_BRIARD 0x0624 |
c21e0bbf MO |
32 | |
33 | /* Since there is only one target, make it 0 */ | |
34 | #define CXLFLASH_TARGET 0 | |
35 | #define CXLFLASH_MAX_CDB_LEN 16 | |
36 | ||
37 | /* Really only one target per bus since the Texan is directly attached */ | |
38 | #define CXLFLASH_MAX_NUM_TARGETS_PER_BUS 1 | |
39 | #define CXLFLASH_MAX_NUM_LUNS_PER_TARGET 65536 | |
40 | ||
41 | #define CXLFLASH_PCI_ERROR_RECOVERY_TIMEOUT (120 * HZ) | |
42 | ||
c21e0bbf MO |
43 | /* FC defines */ |
44 | #define FC_MTIP_CMDCONFIG 0x010 | |
45 | #define FC_MTIP_STATUS 0x018 | |
9cf43a36 MO |
46 | #define FC_MAX_NUM_LUNS 0x080 /* Max LUNs host can provision for port */ |
47 | #define FC_CUR_NUM_LUNS 0x088 /* Cur number LUNs provisioned for port */ | |
48 | #define FC_MAX_CAP_PORT 0x090 /* Max capacity all LUNs for port (4K blocks) */ | |
49 | #define FC_CUR_CAP_PORT 0x098 /* Cur capacity all LUNs for port (4K blocks) */ | |
c21e0bbf MO |
50 | |
51 | #define FC_PNAME 0x300 | |
52 | #define FC_CONFIG 0x320 | |
53 | #define FC_CONFIG2 0x328 | |
54 | #define FC_STATUS 0x330 | |
55 | #define FC_ERROR 0x380 | |
56 | #define FC_ERRCAP 0x388 | |
57 | #define FC_ERRMSK 0x390 | |
58 | #define FC_CNT_CRCERR 0x538 | |
59 | #define FC_CRC_THRESH 0x580 | |
60 | ||
61 | #define FC_MTIP_CMDCONFIG_ONLINE 0x20ULL | |
62 | #define FC_MTIP_CMDCONFIG_OFFLINE 0x40ULL | |
63 | ||
64 | #define FC_MTIP_STATUS_MASK 0x30ULL | |
65 | #define FC_MTIP_STATUS_ONLINE 0x20ULL | |
66 | #define FC_MTIP_STATUS_OFFLINE 0x10ULL | |
67 | ||
68 | /* TIMEOUT and RETRY definitions */ | |
69 | ||
70 | /* AFU command timeout values */ | |
71 | #define MC_AFU_SYNC_TIMEOUT 5 /* 5 secs */ | |
9cf43a36 | 72 | #define MC_LUN_PROV_TIMEOUT 5 /* 5 secs */ |
bc88ac47 | 73 | #define MC_AFU_DEBUG_TIMEOUT 5 /* 5 secs */ |
c21e0bbf MO |
74 | |
75 | /* AFU command room retry limit */ | |
76 | #define MC_ROOM_RETRY_CNT 10 | |
77 | ||
78 | /* FC CRC clear periodic timer */ | |
79 | #define MC_CRC_THRESH 100 /* threshold in 5 mins */ | |
80 | ||
81 | #define FC_PORT_STATUS_RETRY_CNT 100 /* 100 100ms retries = 10 seconds */ | |
82 | #define FC_PORT_STATUS_RETRY_INTERVAL_US 100000 /* microseconds */ | |
83 | ||
84 | /* VPD defines */ | |
85 | #define CXLFLASH_VPD_LEN 256 | |
86 | #define WWPN_LEN 16 | |
87 | #define WWPN_BUF_LEN (WWPN_LEN + 1) | |
88 | ||
89 | enum undo_level { | |
9526f360 | 90 | UNDO_NOOP = 0, |
c21e0bbf MO |
91 | FREE_IRQ, |
92 | UNMAP_ONE, | |
93 | UNMAP_TWO, | |
9526f360 | 94 | UNMAP_THREE |
c21e0bbf MO |
95 | }; |
96 | ||
97 | struct dev_dependent_vals { | |
98 | u64 max_sectors; | |
96e1b660 | 99 | u64 flags; |
0d419130 MO |
100 | #define CXLFLASH_NOTIFY_SHUTDOWN 0x0000000000000001ULL |
101 | #define CXLFLASH_WWPN_VPD_REQUIRED 0x0000000000000002ULL | |
07d0c52f | 102 | #define CXLFLASH_OCXL_DEV 0x0000000000000004ULL |
c21e0bbf MO |
103 | }; |
104 | ||
de5d35af UK |
105 | static inline const struct cxlflash_backend_ops * |
106 | cxlflash_assign_ops(struct dev_dependent_vals *ddv) | |
107 | { | |
108 | const struct cxlflash_backend_ops *ops = NULL; | |
109 | ||
943e59fe | 110 | #ifdef CONFIG_OCXL_BASE |
de5d35af UK |
111 | if (ddv->flags & CXLFLASH_OCXL_DEV) |
112 | ops = &cxlflash_ocxl_ops; | |
cd43c221 UK |
113 | #endif |
114 | ||
943e59fe | 115 | #ifdef CONFIG_CXL_BASE |
de5d35af UK |
116 | if (!(ddv->flags & CXLFLASH_OCXL_DEV)) |
117 | ops = &cxlflash_cxl_ops; | |
cd43c221 | 118 | #endif |
de5d35af UK |
119 | |
120 | return ops; | |
121 | } | |
122 | ||
c21e0bbf MO |
123 | struct asyc_intr_info { |
124 | u64 status; | |
125 | char *desc; | |
126 | u8 port; | |
127 | u8 action; | |
128 | #define CLR_FC_ERROR 0x01 | |
129 | #define LINK_RESET 0x02 | |
ef51074a | 130 | #define SCAN_HOST 0x04 |
c21e0bbf MO |
131 | }; |
132 | ||
133 | #endif /* _CXLFLASH_MAIN_H */ |