[linux-block.git] / drivers / scsi / cxlflash / common.h

/* SPDX-License-Identifier: GPL-2.0-or-later */
/*
 * CXL Flash Device Driver
 *
 * Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
 *             Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
 *
 * Copyright (C) 2015 IBM Corporation
 */

#ifndef _CXLFLASH_COMMON_H
#define _CXLFLASH_COMMON_H

#include <linux/async.h>
#include <linux/cdev.h>
#include <linux/irq_poll.h>
#include <linux/list.h>
#include <linux/rwsem.h>
#include <linux/types.h>
#include <scsi/scsi.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi_device.h>

#include "backend.h"

extern const struct file_operations cxlflash_cxl_fops;

#define MAX_CONTEXT	CXLFLASH_MAX_CONTEXT	/* num contexts per afu */
#define MAX_FC_PORTS	CXLFLASH_MAX_FC_PORTS	/* max ports per AFU */
#define LEGACY_FC_PORTS	2			/* legacy ports per AFU */

#define CHAN2PORTBANK(_x)	((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK))
#define CHAN2BANKPORT(_x)	((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1))

#define CHAN2PORTMASK(_x)	(1 << (_x))	/* channel to port mask */
#define PORTMASK2CHAN(_x)	(ilog2((_x)))	/* port mask to channel */
#define PORTNUM2CHAN(_x)	((_x) - 1)	/* port number to channel */

#define CXLFLASH_BLOCK_SIZE	4096		/* 4K blocks */
#define CXLFLASH_MAX_XFER_SIZE	16777216	/* 16MB transfer */
#define CXLFLASH_MAX_SECTORS	(CXLFLASH_MAX_XFER_SIZE/512)	/* SCSI wants
								 * max_sectors
								 * in units of
								 * 512 byte
								 * sectors
								 */

#define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))

/* AFU command retry limit */
#define MC_RETRY_CNT	5	/* Sufficient for SCSI and certain AFU errors */

/* Command management definitions */
#define CXLFLASH_MAX_CMDS               256
#define CXLFLASH_MAX_CMDS_PER_LUN       CXLFLASH_MAX_CMDS

/* RRQ for master issued cmds */
#define NUM_RRQ_ENTRY                   CXLFLASH_MAX_CMDS

/* SQ for master issued cmds */
#define NUM_SQ_ENTRY			CXLFLASH_MAX_CMDS

/* Hardware queue definitions */
#define CXLFLASH_DEF_HWQS		1
#define CXLFLASH_MAX_HWQS		8
#define PRIMARY_HWQ			0


static inline void check_sizes(void)
{
	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK);
	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS);
}

/* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
#define CMD_BUFSIZE     SIZE_4K

enum cxlflash_lr_state {
	LINK_RESET_INVALID,
	LINK_RESET_REQUIRED,
	LINK_RESET_COMPLETE
};

enum cxlflash_init_state {
	INIT_STATE_NONE,
	INIT_STATE_PCI,
	INIT_STATE_AFU,
	INIT_STATE_SCSI,
	INIT_STATE_CDEV
};

enum cxlflash_state {
	STATE_PROBING,	/* Initial state during probe */
	STATE_PROBED,	/* Temporary state, probe completed but EEH occurred */
	STATE_NORMAL,	/* Normal running state, everything good */
	STATE_RESET,	/* Reset state, trying to reset/recover */
	STATE_FAILTERM	/* Failed/terminating state, error out users/threads */
};

enum cxlflash_hwq_mode {
	HWQ_MODE_RR,	/* Roundrobin (default) */
	HWQ_MODE_TAG,	/* Distribute based on block MQ tag */
	HWQ_MODE_CPU,	/* CPU affinity */
	MAX_HWQ_MODE
};

/*
 * Each context has its own set of resource handles that is visible
 * only from that context.
 */

struct cxlflash_cfg {
	struct afu *afu;

	const struct cxlflash_backend_ops *ops;
	struct pci_dev *dev;
	struct pci_device_id *dev_id;
	struct Scsi_Host *host;
	int num_fc_ports;
	struct cdev cdev;
	struct device *chardev;

	ulong cxlflash_regs_pci;

	struct work_struct work_q;
	enum cxlflash_init_state init_state;
	enum cxlflash_lr_state lr_state;
	int lr_port;
	atomic_t scan_host_needed;

	void *afu_cookie;

	atomic_t recovery_threads;
	struct mutex ctx_recovery_mutex;
	struct mutex ctx_tbl_list_mutex;
	struct rw_semaphore ioctl_rwsem;
	struct ctx_info *ctx_tbl[MAX_CONTEXT];
	struct list_head ctx_err_recovery; /* contexts w/ recovery pending */
	struct file_operations cxl_fops;

	/* Parameters that are LUN table related */
	int last_lun_index[MAX_FC_PORTS];
	int promote_lun_index;
	struct list_head lluns; /* list of llun_info structs */

	wait_queue_head_t tmf_waitq;
	spinlock_t tmf_slock;
	bool tmf_active;
	bool ws_unmap;		/* Write-same unmap supported */
	wait_queue_head_t reset_waitq;
	enum cxlflash_state state;
	async_cookie_t async_reset_cookie;
};

struct afu_cmd {
	struct sisl_ioarcb rcb;	/* IOARCB (cache line aligned) */
	struct sisl_ioasa sa;	/* IOASA must follow IOARCB */
	struct afu *parent;
	struct scsi_cmnd *scp;
	struct completion cevent;
	struct list_head queue;
	u32 hwq_index;

	u8 cmd_tmf:1,
	   cmd_aborted:1;

	struct list_head list;	/* Pending commands link */

	/* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
	 * However for performance reasons the IOARCB/IOASA should be
	 * cache line aligned.
	 */
} __aligned(cache_line_size());

static inline struct afu_cmd *sc_to_afuc(struct scsi_cmnd *sc)
{
	return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd));
}

static inline struct afu_cmd *sc_to_afuci(struct scsi_cmnd *sc)
{
	struct afu_cmd *afuc = sc_to_afuc(sc);

	INIT_LIST_HEAD(&afuc->queue);
	return afuc;
}

static inline struct afu_cmd *sc_to_afucz(struct scsi_cmnd *sc)
{
	struct afu_cmd *afuc = sc_to_afuc(sc);

	memset(afuc, 0, sizeof(*afuc));
	return sc_to_afuci(sc);
}

struct hwq {
	/* Stuff requiring alignment go first. */
	struct sisl_ioarcb sq[NUM_SQ_ENTRY];		/* 16K SQ */
	u64 rrq_entry[NUM_RRQ_ENTRY];			/* 2K RRQ */

	/* Beware of alignment till here. Preferably introduce new
	 * fields after this point
	 */
	struct afu *afu;
	void *ctx_cookie;
	struct sisl_host_map __iomem *host_map;		/* MC host map */
	struct sisl_ctrl_map __iomem *ctrl_map;		/* MC control map */
	ctx_hndl_t ctx_hndl;	/* master's context handle */
	u32 index;		/* Index of this hwq */
	int num_irqs;		/* Number of interrupts requested for context */
	struct list_head pending_cmds;	/* Commands pending completion */

	atomic_t hsq_credits;
	spinlock_t hsq_slock;	/* Hardware send queue lock */
	struct sisl_ioarcb *hsq_start;
	struct sisl_ioarcb *hsq_end;
	struct sisl_ioarcb *hsq_curr;
	spinlock_t hrrq_slock;
	u64 *hrrq_start;
	u64 *hrrq_end;
	u64 *hrrq_curr;
	bool toggle;
	bool hrrq_online;

	s64 room;

	struct irq_poll irqpoll;
} __aligned(cache_line_size());

struct afu {
	struct hwq hwqs[CXLFLASH_MAX_HWQS];
	int (*send_cmd)(struct afu *afu, struct afu_cmd *cmd);
	int (*context_reset)(struct hwq *hwq);

	/* AFU HW */
	struct cxlflash_afu_map __iomem *afu_map;	/* entire MMIO map */

	atomic_t cmds_active;	/* Number of currently active AFU commands */
	struct mutex sync_active;	/* Mutex to serialize AFU commands */
	u64 hb;
	u32 internal_lun;	/* User-desired LUN mode for this AFU */

	u32 num_hwqs;		/* Number of hardware queues */
	u32 desired_hwqs;	/* Desired h/w queues, effective on AFU reset */
	enum cxlflash_hwq_mode hwq_mode; /* Steering mode for h/w queues */
	u32 hwq_rr_count;	/* Count to distribute traffic for roundrobin */

	char version[16];
	u64 interface_version;

	u32 irqpoll_weight;
	struct cxlflash_cfg *parent; /* Pointer back to parent cxlflash_cfg */
};

static inline struct hwq *get_hwq(struct afu *afu, u32 index)
{
	WARN_ON(index >= CXLFLASH_MAX_HWQS);

	return &afu->hwqs[index];
}

static inline bool afu_is_irqpoll_enabled(struct afu *afu)
{
	return !!afu->irqpoll_weight;
}

static inline bool afu_has_cap(struct afu *afu, u64 cap)
{
	u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT;

	return afu_cap & cap;
}

static inline bool afu_is_ocxl_lisn(struct afu *afu)
{
	return afu_has_cap(afu, SISL_INTVER_CAP_OCXL_LISN);
}

static inline bool afu_is_afu_debug(struct afu *afu)
{
	return afu_has_cap(afu, SISL_INTVER_CAP_AFU_DEBUG);
}

static inline bool afu_is_lun_provision(struct afu *afu)
{
	return afu_has_cap(afu, SISL_INTVER_CAP_LUN_PROVISION);
}

static inline bool afu_is_sq_cmd_mode(struct afu *afu)
{
	return afu_has_cap(afu, SISL_INTVER_CAP_SQ_CMD_MODE);
}

static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu)
{
	return afu_has_cap(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE);
}

static inline u64 lun_to_lunid(u64 lun)
{
	__be64 lun_id;

	int_to_scsilun(lun, (struct scsi_lun *)&lun_id);
	return be64_to_cpu(lun_id);
}

static inline struct fc_port_bank __iomem *get_fc_port_bank(
					    struct cxlflash_cfg *cfg, int i)
{
	struct afu *afu = cfg->afu;

	return &afu->afu_map->global.bank[CHAN2PORTBANK(i)];
}

static inline __be64 __iomem *get_fc_port_regs(struct cxlflash_cfg *cfg, int i)
{
	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);

	return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0];
}

static inline __be64 __iomem *get_fc_port_luns(struct cxlflash_cfg *cfg, int i)
{
	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);

	return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0];
}

int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode);
void cxlflash_list_init(void);
void cxlflash_term_global_luns(void);
void cxlflash_free_errpage(void);
int cxlflash_ioctl(struct scsi_device *sdev, unsigned int cmd,
		   void __user *arg);
void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg);
int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg);
void cxlflash_term_local_luns(struct cxlflash_cfg *cfg);
void cxlflash_restore_luntable(struct cxlflash_cfg *cfg);

#endif /* ifndef _CXLFLASH_COMMON_H */
Commit	Line	Data
2874c5fd	1	/* SPDX-License-Identifier: GPL-2.0-or-later */
c21e0bbf MO	2	/*
	3	* CXL Flash Device Driver
	4	*
	5	* Written by: Manoj N. Kumar <manoj@linux.vnet.ibm.com>, IBM Corporation
	6	* Matthew R. Ochs <mrochs@linux.vnet.ibm.com>, IBM Corporation
	7	*
	8	* Copyright (C) 2015 IBM Corporation
c21e0bbf MO	9	*/
	10
	11	#ifndef _CXLFLASH_COMMON_H
	12	#define _CXLFLASH_COMMON_H
	13
0b09e711	14	#include <linux/async.h>
a834a36b	15	#include <linux/cdev.h>
cba06e6d	16	#include <linux/irq_poll.h>
c21e0bbf	17	#include <linux/list.h>
0a27ae51	18	#include <linux/rwsem.h>
c21e0bbf MO	19	#include <linux/types.h>
c21e0bbf MO	20	#include <scsi/scsi.h>
5fbb96c8	21	#include <scsi/scsi_cmnd.h>
c21e0bbf MO	22	#include <scsi/scsi_device.h>
c21e0bbf MO	23
25b8e08e MO	24	#include "backend.h"
25b8e08e MO	25
17ead26f	26	extern const struct file_operations cxlflash_cxl_fops;
c21e0bbf	27
78ae028e	28	#define MAX_CONTEXT CXLFLASH_MAX_CONTEXT /* num contexts per afu */
56518072 MO	29	#define MAX_FC_PORTS CXLFLASH_MAX_FC_PORTS /* max ports per AFU */
	30	#define LEGACY_FC_PORTS 2 /* legacy ports per AFU */
	31
	32	#define CHAN2PORTBANK(_x) ((_x) >> ilog2(CXLFLASH_NUM_FC_PORTS_PER_BANK))
	33	#define CHAN2BANKPORT(_x) ((_x) & (CXLFLASH_NUM_FC_PORTS_PER_BANK - 1))
c21e0bbf	34
8fa4f177 MO	35	#define CHAN2PORTMASK(_x) (1 << (_x)) /* channel to port mask */
	36	#define PORTMASK2CHAN(_x) (ilog2((_x))) /* port mask to channel */
	37	#define PORTNUM2CHAN(_x) ((_x) - 1) /* port number to channel */
	38
fcc87e74	39	#define CXLFLASH_BLOCK_SIZE 4096 /* 4K blocks */
c21e0bbf MO	40	#define CXLFLASH_MAX_XFER_SIZE 16777216 /* 16MB transfer */
c21e0bbf MO	41	#define CXLFLASH_MAX_SECTORS (CXLFLASH_MAX_XFER_SIZE/512) /* SCSI wants
fcc87e74 MO	42	* max_sectors
	43	* in units of
	44	* 512 byte
	45	* sectors
	46	*/
c21e0bbf	47
c21e0bbf MO	48	#define MAX_RHT_PER_CONTEXT (PAGE_SIZE / sizeof(struct sisl_rht_entry))
	49
	50	/* AFU command retry limit */
fcc87e74	51	#define MC_RETRY_CNT 5 /* Sufficient for SCSI and certain AFU errors */
c21e0bbf MO	52
c21e0bbf MO	53	/* Command management definitions */
83430833	54	#define CXLFLASH_MAX_CMDS 256
c21e0bbf MO	55	#define CXLFLASH_MAX_CMDS_PER_LUN CXLFLASH_MAX_CMDS
c21e0bbf MO	56
83430833 MK	57	/* RRQ for master issued cmds */
	58	#define NUM_RRQ_ENTRY CXLFLASH_MAX_CMDS
	59
696d0b0c MO	60	/* SQ for master issued cmds */
	61	#define NUM_SQ_ENTRY CXLFLASH_MAX_CMDS
	62
3065267a MO	63	/* Hardware queue definitions */
	64	#define CXLFLASH_DEF_HWQS 1
	65	#define CXLFLASH_MAX_HWQS 8
bfc0bab1 UK	66	#define PRIMARY_HWQ 0
bfc0bab1 UK	67
c21e0bbf MO	68
	69	static inline void check_sizes(void)
	70	{
56518072	71	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_NUM_FC_PORTS_PER_BANK);
cd41e18d	72	BUILD_BUG_ON_NOT_POWER_OF_2(CXLFLASH_MAX_CMDS);
c21e0bbf MO	73	}
	74
	75	/* AFU defines a fixed size of 4K for command buffers (borrow 4K page define) */
	76	#define CMD_BUFSIZE SIZE_4K
	77
c21e0bbf MO	78	enum cxlflash_lr_state {
	79	LINK_RESET_INVALID,
	80	LINK_RESET_REQUIRED,
	81	LINK_RESET_COMPLETE
	82	};
	83
	84	enum cxlflash_init_state {
	85	INIT_STATE_NONE,
	86	INIT_STATE_PCI,
	87	INIT_STATE_AFU,
a834a36b UK	88	INIT_STATE_SCSI,
a834a36b UK	89	INIT_STATE_CDEV
c21e0bbf MO	90	};
c21e0bbf MO	91
5cdac81a	92	enum cxlflash_state {
323e3342 MO	93	STATE_PROBING, /* Initial state during probe */
323e3342 MO	94	STATE_PROBED, /* Temporary state, probe completed but EEH occurred */
5cdac81a	95	STATE_NORMAL, /* Normal running state, everything good */
439e85c1	96	STATE_RESET, /* Reset state, trying to reset/recover */
5cdac81a MO	97	STATE_FAILTERM /* Failed/terminating state, error out users/threads */
	98	};
	99
1dd0c0e4 MO	100	enum cxlflash_hwq_mode {
	101	HWQ_MODE_RR, /* Roundrobin (default) */
	102	HWQ_MODE_TAG, /* Distribute based on block MQ tag */
	103	HWQ_MODE_CPU, /* CPU affinity */
	104	MAX_HWQ_MODE
	105	};
	106
c21e0bbf MO	107	/*
	108	* Each context has its own set of resource handles that is visible
	109	* only from that context.
	110	*/
	111
	112	struct cxlflash_cfg {
	113	struct afu *afu;
c21e0bbf	114
25b8e08e	115	const struct cxlflash_backend_ops *ops;
c21e0bbf MO	116	struct pci_dev *dev;
	117	struct pci_device_id *dev_id;
	118	struct Scsi_Host *host;
78ae028e	119	int num_fc_ports;
a834a36b UK	120	struct cdev cdev;
a834a36b UK	121	struct device *chardev;
c21e0bbf MO	122
	123	ulong cxlflash_regs_pci;
	124
c21e0bbf MO	125	struct work_struct work_q;
	126	enum cxlflash_init_state init_state;
	127	enum cxlflash_lr_state lr_state;
	128	int lr_port;
ef51074a	129	atomic_t scan_host_needed;
c21e0bbf	130
b070545d	131	void *afu_cookie;
c21e0bbf	132
65be2c79 MO	133	atomic_t recovery_threads;
	134	struct mutex ctx_recovery_mutex;
	135	struct mutex ctx_tbl_list_mutex;
0a27ae51	136	struct rw_semaphore ioctl_rwsem;
65be2c79 MO	137	struct ctx_info *ctx_tbl[MAX_CONTEXT];
	138	struct list_head ctx_err_recovery; /* contexts w/ recovery pending */
	139	struct file_operations cxl_fops;
	140
2cb79266	141	/* Parameters that are LUN table related */
78ae028e	142	int last_lun_index[MAX_FC_PORTS];
2cb79266	143	int promote_lun_index;
65be2c79 MO	144	struct list_head lluns; /* list of llun_info structs */
65be2c79 MO	145
c21e0bbf	146	wait_queue_head_t tmf_waitq;
018d1dc9	147	spinlock_t tmf_slock;
c21e0bbf	148	bool tmf_active;
3223c01a	149	bool ws_unmap; /* Write-same unmap supported */
439e85c1	150	wait_queue_head_t reset_waitq;
5cdac81a	151	enum cxlflash_state state;
0b09e711	152	async_cookie_t async_reset_cookie;
c21e0bbf MO	153	};
	154
	155	struct afu_cmd {
	156	struct sisl_ioarcb rcb; /* IOARCB (cache line aligned) */
	157	struct sisl_ioasa sa; /* IOASA must follow IOARCB */
c21e0bbf	158	struct afu *parent;
fe7f9698	159	struct scsi_cmnd *scp;
9ba848ac	160	struct completion cevent;
f918b4a8	161	struct list_head queue;
1dd0c0e4	162	u32 hwq_index;
c21e0bbf	163
a1ea04b3 UK	164	u8 cmd_tmf:1,
	165	cmd_aborted:1;
	166
a002bf83	167	struct list_head list; /* Pending commands link */
c21e0bbf MO	168
	169	/* As per the SISLITE spec the IOARCB EA has to be 16-byte aligned.
	170	* However for performance reasons the IOARCB/IOASA should be
	171	* cache line aligned.
	172	*/
	173	} __aligned(cache_line_size());
	174
5fbb96c8 MO	175	static inline struct afu_cmd sc_to_afuc(struct scsi_cmnd sc)
	176	{
	177	return PTR_ALIGN(scsi_cmd_priv(sc), __alignof__(struct afu_cmd));
	178	}
	179
479ad8e9	180	static inline struct afu_cmd sc_to_afuci(struct scsi_cmnd sc)
5fbb96c8 MO	181	{
	182	struct afu_cmd *afuc = sc_to_afuc(sc);
	183
a1ea04b3	184	INIT_LIST_HEAD(&afuc->queue);
5fbb96c8 MO	185	return afuc;
	186	}
	187
479ad8e9 MO	188	static inline struct afu_cmd sc_to_afucz(struct scsi_cmnd sc)
	189	{
	190	struct afu_cmd *afuc = sc_to_afuc(sc);
	191
	192	memset(afuc, 0, sizeof(*afuc));
	193	return sc_to_afuci(sc);
	194	}
	195
bfc0bab1	196	struct hwq {
c21e0bbf	197	/* Stuff requiring alignment go first. */
696d0b0c MO	198	struct sisl_ioarcb sq[NUM_SQ_ENTRY]; /* 16K SQ */
696d0b0c MO	199	u64 rrq_entry[NUM_RRQ_ENTRY]; /* 2K RRQ */
c21e0bbf MO	200
	201	/* Beware of alignment till here. Preferably introduce new
	202	* fields after this point
	203	*/
bfc0bab1	204	struct afu *afu;
b070545d	205	void *ctx_cookie;
1786f4a0 MO	206	struct sisl_host_map __iomem host_map; / MC host map */
1786f4a0 MO	207	struct sisl_ctrl_map __iomem ctrl_map; / MC control map */
c21e0bbf	208	ctx_hndl_t ctx_hndl; /* master's context handle */
bfc0bab1	209	u32 index; /* Index of this hwq */
e11e0ff8	210	int num_irqs; /* Number of interrupts requested for context */
a002bf83	211	struct list_head pending_cmds; /* Commands pending completion */
696d0b0c MO	212
696d0b0c MO	213	atomic_t hsq_credits;
66ea9bcc	214	spinlock_t hsq_slock; /* Hardware send queue lock */
696d0b0c MO	215	struct sisl_ioarcb *hsq_start;
	216	struct sisl_ioarcb *hsq_end;
	217	struct sisl_ioarcb *hsq_curr;
f918b4a8	218	spinlock_t hrrq_slock;
c21e0bbf MO	219	u64 *hrrq_start;
	220	u64 *hrrq_end;
	221	u64 *hrrq_curr;
	222	bool toggle;
d2d354a6	223	bool hrrq_online;
bfc0bab1	224
11f7b184	225	s64 room;
bfc0bab1 UK	226
	227	struct irq_poll irqpoll;
	228	} __aligned(cache_line_size());
	229
	230	struct afu {
3065267a	231	struct hwq hwqs[CXLFLASH_MAX_HWQS];
fb77e528 UK	232	int (send_cmd)(struct afu afu, struct afu_cmd *cmd);
fb77e528 UK	233	int (context_reset)(struct hwq hwq);
bfc0bab1 UK	234
	235	/* AFU HW */
	236	struct cxlflash_afu_map __iomem afu_map; / entire MMIO map */
	237
	238	atomic_t cmds_active; /* Number of currently active AFU commands */
e63a8d88	239	struct mutex sync_active; /* Mutex to serialize AFU commands */
c21e0bbf	240	u64 hb;
c21e0bbf	241	u32 internal_lun; /* User-desired LUN mode for this AFU */
1dd0c0e4	242
3065267a MO	243	u32 num_hwqs; /* Number of hardware queues */
3065267a MO	244	u32 desired_hwqs; /* Desired h/w queues, effective on AFU reset */
1dd0c0e4 MO	245	enum cxlflash_hwq_mode hwq_mode; /* Steering mode for h/w queues */
1dd0c0e4 MO	246	u32 hwq_rr_count; /* Count to distribute traffic for roundrobin */
c21e0bbf	247
e5ce067b	248	char version[16];
c21e0bbf MO	249	u64 interface_version;
c21e0bbf MO	250
cba06e6d	251	u32 irqpoll_weight;
c21e0bbf	252	struct cxlflash_cfg parent; / Pointer back to parent cxlflash_cfg */
c21e0bbf MO	253	};
c21e0bbf MO	254
bfc0bab1 UK	255	static inline struct hwq get_hwq(struct afu afu, u32 index)
bfc0bab1 UK	256	{
3065267a	257	WARN_ON(index >= CXLFLASH_MAX_HWQS);
bfc0bab1 UK	258
	259	return &afu->hwqs[index];
	260	}
	261
cba06e6d MO	262	static inline bool afu_is_irqpoll_enabled(struct afu *afu)
	263	{
	264	return !!afu->irqpoll_weight;
	265	}
	266
efa1c818	267	static inline bool afu_has_cap(struct afu *afu, u64 cap)
696d0b0c MO	268	{
	269	u64 afu_cap = afu->interface_version >> SISL_INTVER_CAP_SHIFT;
	270
efa1c818	271	return afu_cap & cap;
696d0b0c MO	272	}
696d0b0c MO	273
23239eec UK	274	static inline bool afu_is_ocxl_lisn(struct afu *afu)
	275	{
	276	return afu_has_cap(afu, SISL_INTVER_CAP_OCXL_LISN);
	277	}
	278
bc88ac47 MO	279	static inline bool afu_is_afu_debug(struct afu *afu)
	280	{
	281	return afu_has_cap(afu, SISL_INTVER_CAP_AFU_DEBUG);
	282	}
	283
9cf43a36 MO	284	static inline bool afu_is_lun_provision(struct afu *afu)
	285	{
	286	return afu_has_cap(afu, SISL_INTVER_CAP_LUN_PROVISION);
	287	}
	288
696d0b0c MO	289	static inline bool afu_is_sq_cmd_mode(struct afu *afu)
696d0b0c MO	290	{
efa1c818	291	return afu_has_cap(afu, SISL_INTVER_CAP_SQ_CMD_MODE);
696d0b0c MO	292	}
	293
	294	static inline bool afu_is_ioarrin_cmd_mode(struct afu *afu)
	295	{
efa1c818	296	return afu_has_cap(afu, SISL_INTVER_CAP_IOARRIN_CMD_MODE);
696d0b0c MO	297	}
696d0b0c MO	298
c21e0bbf MO	299	static inline u64 lun_to_lunid(u64 lun)
c21e0bbf MO	300	{
1786f4a0	301	__be64 lun_id;
c21e0bbf MO	302
c21e0bbf MO	303	int_to_scsilun(lun, (struct scsi_lun *)&lun_id);
1786f4a0	304	return be64_to_cpu(lun_id);
c21e0bbf MO	305	}
c21e0bbf MO	306
56518072 MO	307	static inline struct fc_port_bank __iomem *get_fc_port_bank(
56518072 MO	308	struct cxlflash_cfg *cfg, int i)
0aa14887 MO	309	{
	310	struct afu *afu = cfg->afu;
	311
56518072 MO	312	return &afu->afu_map->global.bank[CHAN2PORTBANK(i)];
	313	}
	314
	315	static inline __be64 __iomem get_fc_port_regs(struct cxlflash_cfg cfg, int i)
	316	{
	317	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
	318
	319	return &fcpb->fc_port_regs[CHAN2BANKPORT(i)][0];
0aa14887 MO	320	}
	321
	322	static inline __be64 __iomem get_fc_port_luns(struct cxlflash_cfg cfg, int i)
	323	{
56518072	324	struct fc_port_bank __iomem *fcpb = get_fc_port_bank(cfg, i);
0aa14887	325
56518072	326	return &fcpb->fc_port_luns[CHAN2BANKPORT(i)][0];
0aa14887 MO	327	}
0aa14887 MO	328
fcc87e74	329	int cxlflash_afu_sync(struct afu *afu, ctx_hndl_t c, res_hndl_t r, u8 mode);
65be2c79 MO	330	void cxlflash_list_init(void);
	331	void cxlflash_term_global_luns(void);
	332	void cxlflash_free_errpage(void);
6f4e626f NC	333	int cxlflash_ioctl(struct scsi_device *sdev, unsigned int cmd,
6f4e626f NC	334	void __user *arg);
fcc87e74 MO	335	void cxlflash_stop_term_user_contexts(struct cxlflash_cfg *cfg);
	336	int cxlflash_mark_contexts_error(struct cxlflash_cfg *cfg);
	337	void cxlflash_term_local_luns(struct cxlflash_cfg *cfg);
	338	void cxlflash_restore_luntable(struct cxlflash_cfg *cfg);
65be2c79	339
c21e0bbf	340	#endif /* ifndef _CXLFLASH_COMMON_H */