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[SCSI] be2iscsi: Issue MBX Cmd for login to boot target in crashdump mode
[linux-2.6-block.git] / drivers / scsi / be2iscsi / be_main.h
CommitLineData
6733b39a 1/**
255fa9a3 2 * Copyright (C) 2005 - 2011 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
255fa9a3 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
6733b39a
JK		 11 *
12 * Contact Information:
255fa9a3 13 * linux-drivers@emulex.com
6733b39a 14 *
255fa9a3
JK		 15 * Emulex
16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a
JK		 18 */
19
20#ifndef _BEISCSI_MAIN_
21#define _BEISCSI_MAIN_
22
6733b39a
JK		 23#include <linux/kernel.h>
24#include <linux/pci.h>
82c57028 25#include <linux/if_ether.h>
6733b39a 26#include <linux/in.h>
6733b39a
JK		 27#include <scsi/scsi.h>
28#include <scsi/scsi_cmnd.h>
29#include <scsi/scsi_device.h>
30#include <scsi/scsi_host.h>
31#include <scsi/iscsi_proto.h>
32#include <scsi/libiscsi.h>
33#include <scsi/scsi_transport_iscsi.h>
34
35#include "be.h"
6733b39a 36#define DRV_NAME "be2iscsi"
76d15dbd 37#define BUILD_STR "4.2.162.0"
2f635883
JK		 38#define BE_NAME "Emulex OneConnect" \
39 "Open-iSCSI Driver version" BUILD_STR
6733b39a
JK		 40#define DRV_DESC BE_NAME " " "Driver"
41
457ff3b7 42#define BE_VENDOR_ID 0x19A2
f98c96b0 43/* DEVICE ID's for BE2 */
6733b39a
JK		 44#define BE_DEVICE_ID1 0x212
45#define OC_DEVICE_ID1 0x702
46#define OC_DEVICE_ID2 0x703
f98c96b0
JK		 47
48/* DEVICE ID's for BE3 */
49#define BE_DEVICE_ID2 0x222
bfead3b2 50#define OC_DEVICE_ID3 0x712
6733b39a 51
7da50879
JK		 52#define BE2_IO_DEPTH 1024
53#define BE2_MAX_SESSIONS 256
6733b39a 54#define BE2_CMDS_PER_CXN 128
6733b39a
JK		 55#define BE2_TMFS 16
56#define BE2_NOPOUT_REQ 16
6733b39a
JK		 57#define BE2_SGE 32
58#define BE2_DEFPDU_HDR_SZ 64
59#define BE2_DEFPDU_DATA_SZ 8192
6733b39a 60
bfead3b2 61#define MAX_CPUS 31
aa359032 62#define BEISCSI_SGLIST_ELEMENTS 30
6733b39a 63
6733b39a 64#define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
e919dee8 65#define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */
6733b39a
JK		 66
67#define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
68#define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
69#define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
70#define BEISCSI_MAX_FRAGS_INIT 192
457ff3b7 71#define BE_NUM_MSIX_ENTRIES 1
e9b91193
JK		 72
73#define MPU_EP_CONTROL 0
74#define MPU_EP_SEMAPHORE 0xac
75#define BE2_SOFT_RESET 0x5c
76#define BE2_PCI_ONLINE0 0xb0
77#define BE2_PCI_ONLINE1 0xb4
78#define BE2_SET_RESET 0x80
79#define BE2_MPU_IRAM_ONLINE 0x00000080
6733b39a
JK		 80
81#define BE_SENSE_INFO_SIZE 258
82#define BE_ISCSI_PDU_HEADER_SIZE 64
83#define BE_MIN_MEM_SIZE 16384
bfead3b2 84#define MAX_CMD_SZ 65536
6733b39a
JK		 85#define IIOC_SCSI_DATA 0x05 /* Write Operation */
86
9aef4200 87#define INVALID_SESS_HANDLE 0xFFFFFFFF
6733b39a
JK		 88#define DBG_LVL 0x00000001
89#define DBG_LVL_1 0x00000001
90#define DBG_LVL_2 0x00000002
91#define DBG_LVL_3 0x00000004
92#define DBG_LVL_4 0x00000008
93#define DBG_LVL_5 0x00000010
94#define DBG_LVL_6 0x00000020
95#define DBG_LVL_7 0x00000040
96#define DBG_LVL_8 0x00000080
97
98#define SE_DEBUG(debug_mask, fmt, args...) \
99do { \
100 if (debug_mask & DBG_LVL) { \
101 printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\
102 printk(fmt, ##args); \
103 } \
104} while (0);
105
bfead3b2
JK		 106#define BE_ADAPTER_UP 0x00000000
107#define BE_ADAPTER_LINK_DOWN 0x00000001
6733b39a
JK		 108/**
109 * hardware needs the async PDU buffers to be posted in multiples of 8
110 * So have atleast 8 of them by default
111 */
112
113#define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx)
114
115/********* Memory BAR register ************/
457ff3b7 116#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
6733b39a
JK		 117/**
118 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
119 * Disable" may still globally block interrupts in addition to individual
120 * interrupt masks; a mechanism for the device driver to block all interrupts
121 * atomically without having to arbitrate for the PCI Interrupt Disable bit
122 * with the OS.
123 */
124#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
125
126/********* ISR0 Register offset **********/
457ff3b7 127#define CEV_ISR0_OFFSET 0xC18
6733b39a
JK		 128#define CEV_ISR_SIZE 4
129
130/**
131 * Macros for reading/writing a protection domain or CSR registers
132 * in BladeEngine.
133 */
134
135#define DB_TXULP0_OFFSET 0x40
136#define DB_RXULP0_OFFSET 0xA0
137/********* Event Q door bell *************/
138#define DB_EQ_OFFSET DB_CQ_OFFSET
139#define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */
140/* Clear the interrupt for this eq */
141#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
142/* Must be 1 */
143#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
144/* Number of event entries processed */
145#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
146/* Rearm bit */
147#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
148
149/********* Compl Q door bell *************/
457ff3b7 150#define DB_CQ_OFFSET 0x120
6733b39a
JK		 151#define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
152/* Number of event entries processed */
457ff3b7 153#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
6733b39a 154/* Rearm bit */
457ff3b7 155#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
6733b39a
JK		 156
157#define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
158#define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\
159 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id)
160#define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\
161 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id)
162
163#define PAGES_REQUIRED(x) \
164 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
165
8fcfb210
JK		 166#define BEISCSI_MSI_NAME 20 /* size of msi_name string */
167
6733b39a
JK		 168enum be_mem_enum {
169 HWI_MEM_ADDN_CONTEXT,
6733b39a
JK		 170 HWI_MEM_WRB,
171 HWI_MEM_WRBH,
bfead3b2 172 HWI_MEM_SGLH,
6733b39a 173 HWI_MEM_SGE,
457ff3b7 174 HWI_MEM_ASYNC_HEADER_BUF, /* 5 */
6733b39a
JK		 175 HWI_MEM_ASYNC_DATA_BUF,
176 HWI_MEM_ASYNC_HEADER_RING,
bfead3b2 177 HWI_MEM_ASYNC_DATA_RING,
6733b39a 178 HWI_MEM_ASYNC_HEADER_HANDLE,
457ff3b7 179 HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */
6733b39a
JK		 180 HWI_MEM_ASYNC_PDU_CONTEXT,
181 ISCSI_MEM_GLOBAL_HEADER,
bfead3b2 182 SE_MEM_MAX
6733b39a
JK		 183};
184
185struct be_bus_address32 {
186 unsigned int address_lo;
187 unsigned int address_hi;
188};
189
190struct be_bus_address64 {
191 unsigned long long address;
192};
193
194struct be_bus_address {
195 union {
196 struct be_bus_address32 a32;
197 struct be_bus_address64 a64;
198 } u;
199};
200
201struct mem_array {
202 struct be_bus_address bus_address; /* Bus address of location */
203 void *virtual_address; /* virtual address to the location */
204 unsigned int size; /* Size required by memory block */
205};
206
207struct be_mem_descriptor {
208 unsigned int index; /* Index of this memory parameter */
209 unsigned int category; /* type indicates cached/non-cached */
210 unsigned int num_elements; /* number of elements in this
211 * descriptor
212 */
213 unsigned int alignment_mask; /* Alignment mask for this block */
214 unsigned int size_in_bytes; /* Size required by memory block */
215 struct mem_array *mem_array;
216};
217
218struct sgl_handle {
219 unsigned int sgl_index;
bfead3b2
JK		 220 unsigned int type;
221 unsigned int cid;
222 struct iscsi_task *task;
6733b39a
JK		 223 struct iscsi_sge *pfrag;
224};
225
226struct hba_parameters {
227 unsigned int ios_per_ctrl;
228 unsigned int cxns_per_ctrl;
229 unsigned int asyncpdus_per_ctrl;
230 unsigned int icds_per_ctrl;
231 unsigned int num_sge_per_io;
232 unsigned int defpdu_hdr_sz;
233 unsigned int defpdu_data_sz;
234 unsigned int num_cq_entries;
235 unsigned int num_eq_entries;
236 unsigned int wrbs_per_cxn;
237 unsigned int crashmode;
238 unsigned int hba_num;
239
240 unsigned int mgmt_ws_sz;
241 unsigned int hwi_ws_sz;
242
243 unsigned int eto;
244 unsigned int ldto;
245
246 unsigned int dbg_flags;
247 unsigned int num_cxn;
248
249 unsigned int eq_timer;
250 /**
251 * These are calculated from other params. They're here
252 * for debug purposes
253 */
254 unsigned int num_mcc_pages;
255 unsigned int num_mcc_cq_pages;
256 unsigned int num_cq_pages;
257 unsigned int num_eq_pages;
258
259 unsigned int num_async_pdu_buf_pages;
260 unsigned int num_async_pdu_buf_sgl_pages;
261 unsigned int num_async_pdu_buf_cq_pages;
262
263 unsigned int num_async_pdu_hdr_pages;
264 unsigned int num_async_pdu_hdr_sgl_pages;
265 unsigned int num_async_pdu_hdr_cq_pages;
266
267 unsigned int num_sge;
268};
269
4183122d
JK		 270struct invalidate_command_table {
271 unsigned short icd;
272 unsigned short cid;
273} __packed;
274
6733b39a
JK		 275struct beiscsi_hba {
276 struct hba_parameters params;
277 struct hwi_controller *phwi_ctrlr;
278 unsigned int mem_req[SE_MEM_MAX];
279 /* PCI BAR mapped addresses */
280 u8 __iomem *csr_va; /* CSR */
281 u8 __iomem *db_va; /* Door Bell */
282 u8 __iomem *pci_va; /* PCI Config */
283 struct be_bus_address csr_pa; /* CSR */
284 struct be_bus_address db_pa; /* CSR */
285 struct be_bus_address pci_pa; /* CSR */
286 /* PCI representation of our HBA */
287 struct pci_dev *pcidev;
288 unsigned int state;
289 unsigned short asic_revision;
bfead3b2
JK		 290 unsigned int num_cpus;
291 unsigned int nxt_cqid;
292 struct msix_entry msix_entries[MAX_CPUS + 1];
8fcfb210 293 char *msi_name[MAX_CPUS + 1];
bfead3b2 294 bool msix_enabled;
6733b39a
JK		 295 struct be_mem_descriptor *init_mem;
296
297 unsigned short io_sgl_alloc_index;
298 unsigned short io_sgl_free_index;
299 unsigned short io_sgl_hndl_avbl;
300 struct sgl_handle **io_sgl_hndl_base;
bfead3b2 301 struct sgl_handle **sgl_hndl_array;
6733b39a
JK		 302
303 unsigned short eh_sgl_alloc_index;
304 unsigned short eh_sgl_free_index;
305 unsigned short eh_sgl_hndl_avbl;
306 struct sgl_handle **eh_sgl_hndl_base;
307 spinlock_t io_sgl_lock;
308 spinlock_t mgmt_sgl_lock;
309 spinlock_t isr_lock;
310 unsigned int age;
311 unsigned short avlbl_cids;
312 unsigned short cid_alloc;
313 unsigned short cid_free;
314 struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2];
315 struct list_head hba_queue;
316 unsigned short *cid_array;
317 struct iscsi_endpoint **ep_array;
c7acc5b8 318 struct iscsi_boot_kset *boot_kset;
6733b39a 319 struct Scsi_Host *shost;
0e43895e
MC		 320 struct iscsi_iface *ipv4_iface;
321 struct iscsi_iface *ipv6_iface;
6733b39a
JK		 322 struct {
323 /**
324 * group together since they are used most frequently
325 * for cid to cri conversion
326 */
327 unsigned int iscsi_cid_start;
328 unsigned int phys_port;
329
330 unsigned int isr_offset;
331 unsigned int iscsi_icd_start;
332 unsigned int iscsi_cid_count;
333 unsigned int iscsi_icd_count;
334 unsigned int pci_function;
335
336 unsigned short cid_alloc;
337 unsigned short cid_free;
338 unsigned short avlbl_cids;
bfead3b2 339 unsigned short iscsi_features;
6733b39a
JK		 340 spinlock_t cid_lock;
341 } fw_config;
342
343 u8 mac_address[ETH_ALEN];
344 unsigned short todo_cq;
345 unsigned short todo_mcc_cq;
346 char wq_name[20];
347 struct workqueue_struct *wq; /* The actuak work queue */
348 struct work_struct work_cqs; /* The work being queued */
349 struct be_ctrl_info ctrl;
f98c96b0 350 unsigned int generation;
0e43895e 351 unsigned int interface_handle;
c7acc5b8 352 struct mgmt_session_info boot_sess;
4183122d
JK		 353 struct invalidate_command_table inv_tbl[128];
354
6733b39a
JK		 355};
356
b8b9e1b8
JK		 357struct beiscsi_session {
358 struct pci_pool *bhs_pool;
359};
360
6733b39a
JK		 361/**
362 * struct beiscsi_conn - iscsi connection structure
363 */
364struct beiscsi_conn {
365 struct iscsi_conn *conn;
366 struct beiscsi_hba *phba;
367 u32 exp_statsn;
368 u32 beiscsi_conn_cid;
369 struct beiscsi_endpoint *ep;
370 unsigned short login_in_progress;
d2cecf0d 371 struct wrb_handle *plogin_wrb_handle;
6733b39a 372 struct sgl_handle *plogin_sgl_handle;
b8b9e1b8 373 struct beiscsi_session *beiscsi_sess;
bfead3b2 374 struct iscsi_task *task;
6733b39a
JK		 375};
376
377/* This structure is used by the chip */
378struct pdu_data_out {
379 u32 dw[12];
380};
381/**
382 * Pseudo amap definition in which each bit of the actual structure is defined
383 * as a byte: used to calculate offset/shift/mask of each field
384 */
385struct amap_pdu_data_out {
386 u8 opcode[6]; /* opcode */
387 u8 rsvd0[2]; /* should be 0 */
388 u8 rsvd1[7];
389 u8 final_bit; /* F bit */
390 u8 rsvd2[16];
391 u8 ahs_length[8]; /* no AHS */
392 u8 data_len_hi[8];
393 u8 data_len_lo[16]; /* DataSegmentLength */
394 u8 lun[64];
395 u8 itt[32]; /* ITT; initiator task tag */
396 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
397 u8 rsvd3[32];
398 u8 exp_stat_sn[32];
399 u8 rsvd4[32];
400 u8 data_sn[32];
401 u8 buffer_offset[32];
402 u8 rsvd5[32];
403};
404
405struct be_cmd_bhs {
12352183 406 struct iscsi_scsi_req iscsi_hdr;
6733b39a
JK		 407 unsigned char pad1[16];
408 struct pdu_data_out iscsi_data_pdu;
409 unsigned char pad2[BE_SENSE_INFO_SIZE -
410 sizeof(struct pdu_data_out)];
411};
412
413struct beiscsi_io_task {
414 struct wrb_handle *pwrb_handle;
415 struct sgl_handle *psgl_handle;
416 struct beiscsi_conn *conn;
417 struct scsi_cmnd *scsi_cmnd;
418 unsigned int cmd_sn;
419 unsigned int flags;
420 unsigned short cid;
421 unsigned short header_len;
bfead3b2 422 itt_t libiscsi_itt;
6733b39a
JK		 423 struct be_cmd_bhs *cmd_bhs;
424 struct be_bus_address bhs_pa;
425 unsigned short bhs_len;
426};
427
428struct be_nonio_bhs {
429 struct iscsi_hdr iscsi_hdr;
430 unsigned char pad1[16];
431 struct pdu_data_out iscsi_data_pdu;
432 unsigned char pad2[BE_SENSE_INFO_SIZE -
433 sizeof(struct pdu_data_out)];
434};
435
436struct be_status_bhs {
12352183 437 struct iscsi_scsi_req iscsi_hdr;
6733b39a
JK		 438 unsigned char pad1[16];
439 /**
440 * The plus 2 below is to hold the sense info length that gets
441 * DMA'ed by RxULP
442 */
443 unsigned char sense_info[BE_SENSE_INFO_SIZE];
444};
445
446struct iscsi_sge {
447 u32 dw[4];
448};
449
450/**
451 * Pseudo amap definition in which each bit of the actual structure is defined
452 * as a byte: used to calculate offset/shift/mask of each field
453 */
454struct amap_iscsi_sge {
455 u8 addr_hi[32];
456 u8 addr_lo[32];
457 u8 sge_offset[22]; /* DWORD 2 */
458 u8 rsvd0[9]; /* DWORD 2 */
459 u8 last_sge; /* DWORD 2 */
460 u8 len[17]; /* DWORD 3 */
461 u8 rsvd1[15]; /* DWORD 3 */
462};
463
464struct beiscsi_offload_params {
465 u32 dw[5];
466};
467
468#define OFFLD_PARAMS_ERL 0x00000003
469#define OFFLD_PARAMS_DDE 0x00000004
470#define OFFLD_PARAMS_HDE 0x00000008
471#define OFFLD_PARAMS_IR2T 0x00000010
472#define OFFLD_PARAMS_IMD 0x00000020
473
474/**
475 * Pseudo amap definition in which each bit of the actual structure is defined
476 * as a byte: used to calculate offset/shift/mask of each field
477 */
478struct amap_beiscsi_offload_params {
479 u8 max_burst_length[32];
480 u8 max_send_data_segment_length[32];
481 u8 first_burst_length[32];
482 u8 erl[2];
483 u8 dde[1];
484 u8 hde[1];
485 u8 ir2t[1];
486 u8 imd[1];
487 u8 pad[26];
488 u8 exp_statsn[32];
489};
490
491/* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
492 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
493
494struct async_pdu_handle {
495 struct list_head link;
496 struct be_bus_address pa;
497 void *pbuffer;
498 unsigned int consumed;
499 unsigned char index;
500 unsigned char is_header;
501 unsigned short cri;
502 unsigned long buffer_len;
503};
504
505struct hwi_async_entry {
506 struct {
507 unsigned char hdr_received;
508 unsigned char hdr_len;
509 unsigned short bytes_received;
510 unsigned int bytes_needed;
511 struct list_head list;
512 } wait_queue;
513
514 struct list_head header_busy_list;
515 struct list_head data_busy_list;
516};
517
6733b39a
JK		 518struct hwi_async_pdu_context {
519 struct {
520 struct be_bus_address pa_base;
521 void *va_base;
522 void *ring_base;
523 struct async_pdu_handle *handle_base;
524
525 unsigned int host_write_ptr;
526 unsigned int ep_read_ptr;
527 unsigned int writables;
528
529 unsigned int free_entries;
530 unsigned int busy_entries;
6733b39a
JK		 531
532 struct list_head free_list;
533 } async_header;
534
535 struct {
536 struct be_bus_address pa_base;
537 void *va_base;
538 void *ring_base;
539 struct async_pdu_handle *handle_base;
540
541 unsigned int host_write_ptr;
542 unsigned int ep_read_ptr;
543 unsigned int writables;
544
545 unsigned int free_entries;
546 unsigned int busy_entries;
6733b39a 547 struct list_head free_list;
6733b39a
JK		 548 } async_data;
549
dc63aac6
JK		 550 unsigned int buffer_size;
551 unsigned int num_entries;
552
6733b39a
JK		 553 /**
554 * This is a varying size list! Do not add anything
555 * after this entry!!
556 */
ed58ea2a 557 struct hwi_async_entry async_entry[BE2_MAX_SESSIONS * 2];
6733b39a
JK		 558};
559
560#define PDUCQE_CODE_MASK 0x0000003F
561#define PDUCQE_DPL_MASK 0xFFFF0000
562#define PDUCQE_INDEX_MASK 0x0000FFFF
563
564struct i_t_dpdu_cqe {
565 u32 dw[4];
566} __packed;
567
568/**
569 * Pseudo amap definition in which each bit of the actual structure is defined
570 * as a byte: used to calculate offset/shift/mask of each field
571 */
572struct amap_i_t_dpdu_cqe {
573 u8 db_addr_hi[32];
574 u8 db_addr_lo[32];
575 u8 code[6];
576 u8 cid[10];
577 u8 dpl[16];
578 u8 index[16];
579 u8 num_cons[10];
580 u8 rsvd0[4];
581 u8 final;
582 u8 valid;
583} __packed;
584
585#define CQE_VALID_MASK 0x80000000
586#define CQE_CODE_MASK 0x0000003F
587#define CQE_CID_MASK 0x0000FFC0
588
589#define EQE_VALID_MASK 0x00000001
590#define EQE_MAJORCODE_MASK 0x0000000E
591#define EQE_RESID_MASK 0xFFFF0000
592
593struct be_eq_entry {
594 u32 dw[1];
595} __packed;
596
597/**
598 * Pseudo amap definition in which each bit of the actual structure is defined
599 * as a byte: used to calculate offset/shift/mask of each field
600 */
601struct amap_eq_entry {
602 u8 valid; /* DWORD 0 */
603 u8 major_code[3]; /* DWORD 0 */
604 u8 minor_code[12]; /* DWORD 0 */
605 u8 resource_id[16]; /* DWORD 0 */
606
607} __packed;
608
609struct cq_db {
610 u32 dw[1];
611} __packed;
612
613/**
614 * Pseudo amap definition in which each bit of the actual structure is defined
615 * as a byte: used to calculate offset/shift/mask of each field
616 */
617struct amap_cq_db {
618 u8 qid[10];
619 u8 event[1];
620 u8 rsvd0[5];
621 u8 num_popped[13];
622 u8 rearm[1];
623 u8 rsvd1[2];
624} __packed;
625
626void beiscsi_process_eq(struct beiscsi_hba *phba);
627
6733b39a
JK		 628struct iscsi_wrb {
629 u32 dw[16];
630} __packed;
631
632#define WRB_TYPE_MASK 0xF0000000
633
634/**
635 * Pseudo amap definition in which each bit of the actual structure is defined
636 * as a byte: used to calculate offset/shift/mask of each field
637 */
638struct amap_iscsi_wrb {
639 u8 lun[14]; /* DWORD 0 */
640 u8 lt; /* DWORD 0 */
641 u8 invld; /* DWORD 0 */
642 u8 wrb_idx[8]; /* DWORD 0 */
643 u8 dsp; /* DWORD 0 */
644 u8 dmsg; /* DWORD 0 */
645 u8 undr_run; /* DWORD 0 */
646 u8 over_run; /* DWORD 0 */
647 u8 type[4]; /* DWORD 0 */
648 u8 ptr2nextwrb[8]; /* DWORD 1 */
649 u8 r2t_exp_dtl[24]; /* DWORD 1 */
650 u8 sgl_icd_idx[12]; /* DWORD 2 */
651 u8 rsvd0[20]; /* DWORD 2 */
652 u8 exp_data_sn[32]; /* DWORD 3 */
653 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
654 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
655 u8 cmdsn_itt[32]; /* DWORD 6 */
656 u8 dif_ref_tag[32]; /* DWORD 7 */
657 u8 sge0_addr_hi[32]; /* DWORD 8 */
658 u8 sge0_addr_lo[32]; /* DWORD 9 */
659 u8 sge0_offset[22]; /* DWORD 10 */
660 u8 pbs; /* DWORD 10 */
661 u8 dif_mode[2]; /* DWORD 10 */
662 u8 rsvd1[6]; /* DWORD 10 */
663 u8 sge0_last; /* DWORD 10 */
664 u8 sge0_len[17]; /* DWORD 11 */
665 u8 dif_meta_tag[14]; /* DWORD 11 */
666 u8 sge0_in_ddr; /* DWORD 11 */
667 u8 sge1_addr_hi[32]; /* DWORD 12 */
668 u8 sge1_addr_lo[32]; /* DWORD 13 */
669 u8 sge1_r2t_offset[22]; /* DWORD 14 */
670 u8 rsvd2[9]; /* DWORD 14 */
671 u8 sge1_last; /* DWORD 14 */
672 u8 sge1_len[17]; /* DWORD 15 */
673 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
674 u8 rsvd3[2]; /* DWORD 15 */
675 u8 sge1_in_ddr; /* DWORD 15 */
676
677} __packed;
678
d5431488 679struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid);
6733b39a
JK		 680void
681free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
682
756d29c8
JK		 683void beiscsi_process_all_cqs(struct work_struct *work);
684
6733b39a
JK		 685struct pdu_nop_out {
686 u32 dw[12];
687};
688
689/**
690 * Pseudo amap definition in which each bit of the actual structure is defined
691 * as a byte: used to calculate offset/shift/mask of each field
692 */
693struct amap_pdu_nop_out {
694 u8 opcode[6]; /* opcode 0x00 */
695 u8 i_bit; /* I Bit */
696 u8 x_bit; /* reserved; should be 0 */
697 u8 fp_bit_filler1[7];
698 u8 f_bit; /* always 1 */
699 u8 reserved1[16];
700 u8 ahs_length[8]; /* no AHS */
701 u8 data_len_hi[8];
702 u8 data_len_lo[16]; /* DataSegmentLength */
703 u8 lun[64];
704 u8 itt[32]; /* initiator id for ping or 0xffffffff */
705 u8 ttt[32]; /* target id for ping or 0xffffffff */
706 u8 cmd_sn[32];
707 u8 exp_stat_sn[32];
708 u8 reserved5[128];
709};
710
711#define PDUBASE_OPCODE_MASK 0x0000003F
712#define PDUBASE_DATALENHI_MASK 0x0000FF00
713#define PDUBASE_DATALENLO_MASK 0xFFFF0000
714
715struct pdu_base {
716 u32 dw[16];
717} __packed;
718
719/**
720 * Pseudo amap definition in which each bit of the actual structure is defined
721 * as a byte: used to calculate offset/shift/mask of each field
722 */
723struct amap_pdu_base {
724 u8 opcode[6];
725 u8 i_bit; /* immediate bit */
726 u8 x_bit; /* reserved, always 0 */
727 u8 reserved1[24]; /* opcode-specific fields */
728 u8 ahs_length[8]; /* length units is 4 byte words */
729 u8 data_len_hi[8];
730 u8 data_len_lo[16]; /* DatasegmentLength */
731 u8 lun[64]; /* lun or opcode-specific fields */
732 u8 itt[32]; /* initiator task tag */
733 u8 reserved4[224];
734};
735
736struct iscsi_target_context_update_wrb {
737 u32 dw[16];
738} __packed;
739
740/**
741 * Pseudo amap definition in which each bit of the actual structure is defined
742 * as a byte: used to calculate offset/shift/mask of each field
743 */
744struct amap_iscsi_target_context_update_wrb {
745 u8 lun[14]; /* DWORD 0 */
746 u8 lt; /* DWORD 0 */
747 u8 invld; /* DWORD 0 */
748 u8 wrb_idx[8]; /* DWORD 0 */
749 u8 dsp; /* DWORD 0 */
750 u8 dmsg; /* DWORD 0 */
751 u8 undr_run; /* DWORD 0 */
752 u8 over_run; /* DWORD 0 */
753 u8 type[4]; /* DWORD 0 */
754 u8 ptr2nextwrb[8]; /* DWORD 1 */
755 u8 max_burst_length[19]; /* DWORD 1 */
756 u8 rsvd0[5]; /* DWORD 1 */
757 u8 rsvd1[15]; /* DWORD 2 */
758 u8 max_send_data_segment_length[17]; /* DWORD 2 */
759 u8 first_burst_length[14]; /* DWORD 3 */
760 u8 rsvd2[2]; /* DWORD 3 */
761 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
762 u8 rsvd3[5]; /* DWORD 3 */
763 u8 session_state[3]; /* DWORD 3 */
764 u8 rsvd4[16]; /* DWORD 4 */
765 u8 tx_jumbo; /* DWORD 4 */
766 u8 hde; /* DWORD 4 */
767 u8 dde; /* DWORD 4 */
768 u8 erl[2]; /* DWORD 4 */
769 u8 domain_id[5]; /* DWORD 4 */
770 u8 mode; /* DWORD 4 */
771 u8 imd; /* DWORD 4 */
772 u8 ir2t; /* DWORD 4 */
773 u8 notpredblq[2]; /* DWORD 4 */
774 u8 compltonack; /* DWORD 4 */
775 u8 stat_sn[32]; /* DWORD 5 */
776 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
777 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
778 u8 pad_addr_hi[32]; /* DWORD 8 */
779 u8 pad_addr_lo[32]; /* DWORD 9 */
780 u8 rsvd5[32]; /* DWORD 10 */
781 u8 rsvd6[32]; /* DWORD 11 */
782 u8 rsvd7[32]; /* DWORD 12 */
783 u8 rsvd8[32]; /* DWORD 13 */
784 u8 rsvd9[32]; /* DWORD 14 */
785 u8 rsvd10[32]; /* DWORD 15 */
786
787} __packed;
788
789struct be_ring {
790 u32 pages; /* queue size in pages */
791 u32 id; /* queue id assigned by beklib */
792 u32 num; /* number of elements in queue */
793 u32 cidx; /* consumer index */
794 u32 pidx; /* producer index -- not used by most rings */
795 u32 item_size; /* size in bytes of one object */
796
797 void *va; /* The virtual address of the ring. This
798 * should be last to allow 32 & 64 bit debugger
799 * extensions to work.
800 */
801};
802
803struct hwi_wrb_context {
804 struct list_head wrb_handle_list;
805 struct list_head wrb_handle_drvr_list;
806 struct wrb_handle **pwrb_handle_base;
807 struct wrb_handle **pwrb_handle_basestd;
808 struct iscsi_wrb *plast_wrb;
809 unsigned short alloc_index;
810 unsigned short free_index;
811 unsigned short wrb_handles_available;
812 unsigned short cid;
813};
814
815struct hwi_controller {
816 struct list_head io_sgl_list;
817 struct list_head eh_sgl_list;
818 struct sgl_handle *psgl_handle_base;
819 unsigned int wrb_mem_index;
820
821 struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2];
822 struct mcc_wrb *pmcc_wrb_base;
823 struct be_ring default_pdu_hdr;
824 struct be_ring default_pdu_data;
825 struct hwi_context_memory *phwi_ctxt;
6733b39a
JK		 826};
827
828enum hwh_type_enum {
829 HWH_TYPE_IO = 1,
830 HWH_TYPE_LOGOUT = 2,
831 HWH_TYPE_TMF = 3,
832 HWH_TYPE_NOP = 4,
833 HWH_TYPE_IO_RD = 5,
834 HWH_TYPE_LOGIN = 11,
835 HWH_TYPE_INVALID = 0xFFFFFFFF
836};
837
838struct wrb_handle {
839 enum hwh_type_enum type;
840 unsigned short wrb_index;
841 unsigned short nxt_wrb_index;
842
843 struct iscsi_task *pio_handle;
844 struct iscsi_wrb *pwrb;
845};
846
847struct hwi_context_memory {
bfead3b2
JK		 848 /* Adaptive interrupt coalescing (AIC) info */
849 u16 min_eqd; /* in usecs */
850 u16 max_eqd; /* in usecs */
851 u16 cur_eqd; /* in usecs */
852 struct be_eq_obj be_eq[MAX_CPUS];
853 struct be_queue_info be_cq[MAX_CPUS];
6733b39a
JK		 854
855 struct be_queue_info be_def_hdrq;
856 struct be_queue_info be_def_dataq;
857
858 struct be_queue_info be_wrbq[BE2_MAX_SESSIONS];
859 struct be_mcc_wrb_context *pbe_mcc_context;
860
861 struct hwi_async_pdu_context *pasync_ctx;
862};
863
864#endif
Linux 6.x block layer and io_uring tree(s)