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be2iscsi: Use macros for MCC WRB and CQE fields
[linux-2.6-block.git] / drivers / scsi / be2iscsi / be_main.h
CommitLineData
6733b39a 1/**
c4f39bda 2 * Copyright (C) 2005 - 2015 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
4627de93 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@avagotech.com)
6733b39a
JK		 11 *
12 * Contact Information:
4627de93 13 * linux-drivers@avagotech.com
6733b39a 14 *
c4f39bda 15 * Emulex
255fa9a3
JK		 16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a
JK		 18 */
19
20#ifndef _BEISCSI_MAIN_
21#define _BEISCSI_MAIN_
22
6733b39a
JK		 23#include <linux/kernel.h>
24#include <linux/pci.h>
82c57028 25#include <linux/if_ether.h>
6733b39a 26#include <linux/in.h>
99bc5d55
JSJ		 27#include <linux/ctype.h>
28#include <linux/module.h>
3567f36a 29#include <linux/aer.h>
6733b39a
JK		 30#include <scsi/scsi.h>
31#include <scsi/scsi_cmnd.h>
32#include <scsi/scsi_device.h>
33#include <scsi/scsi_host.h>
34#include <scsi/iscsi_proto.h>
35#include <scsi/libiscsi.h>
36#include <scsi/scsi_transport_iscsi.h>
37
6733b39a 38#define DRV_NAME "be2iscsi"
1db1194f 39#define BUILD_STR "11.0.0.0"
c4f39bda 40#define BE_NAME "Emulex OneConnect" \
2f635883 41 "Open-iSCSI Driver version" BUILD_STR
6733b39a
JK		 42#define DRV_DESC BE_NAME " " "Driver"
43
457ff3b7 44#define BE_VENDOR_ID 0x19A2
139a1b1e 45#define ELX_VENDOR_ID 0x10DF
f98c96b0 46/* DEVICE ID's for BE2 */
6733b39a
JK		 47#define BE_DEVICE_ID1 0x212
48#define OC_DEVICE_ID1 0x702
49#define OC_DEVICE_ID2 0x703
f98c96b0
JK		 50
51/* DEVICE ID's for BE3 */
52#define BE_DEVICE_ID2 0x222
bfead3b2 53#define OC_DEVICE_ID3 0x712
6733b39a 54
139a1b1e
JSJ		 55/* DEVICE ID for SKH */
56#define OC_SKH_ID1 0x722
57
7da50879
JK		 58#define BE2_IO_DEPTH 1024
59#define BE2_MAX_SESSIONS 256
6733b39a 60#define BE2_CMDS_PER_CXN 128
6733b39a
JK		 61#define BE2_TMFS 16
62#define BE2_NOPOUT_REQ 16
6733b39a
JK		 63#define BE2_SGE 32
64#define BE2_DEFPDU_HDR_SZ 64
65#define BE2_DEFPDU_DATA_SZ 8192
1094cf68 66#define BE2_MAX_NUM_CQ_PROC 512
6733b39a 67
22abeef0
JSJ		 68#define MAX_CPUS 64
69#define BEISCSI_MAX_NUM_CPUS 7
22abeef0 70
22661e25 71#define BEISCSI_VER_STRLEN 32
22abeef0 72
aa359032 73#define BEISCSI_SGLIST_ELEMENTS 30
6733b39a 74
73af08e1
JK		 75#define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
76#define BEISCSI_MAX_SECTORS 1024 /* scsi_host->max_sectors */
15a90fe0 77#define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
6733b39a
JK		 78
79#define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
80#define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
81#define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
82#define BEISCSI_MAX_FRAGS_INIT 192
457ff3b7 83#define BE_NUM_MSIX_ENTRIES 1
e9b91193
JK		 84
85#define MPU_EP_CONTROL 0
86#define MPU_EP_SEMAPHORE 0xac
87#define BE2_SOFT_RESET 0x5c
88#define BE2_PCI_ONLINE0 0xb0
89#define BE2_PCI_ONLINE1 0xb4
90#define BE2_SET_RESET 0x80
91#define BE2_MPU_IRAM_ONLINE 0x00000080
6733b39a
JK		 92
93#define BE_SENSE_INFO_SIZE 258
94#define BE_ISCSI_PDU_HEADER_SIZE 64
95#define BE_MIN_MEM_SIZE 16384
bfead3b2 96#define MAX_CMD_SZ 65536
6733b39a
JK		 97#define IIOC_SCSI_DATA 0x05 /* Write Operation */
98
9aef4200 99#define INVALID_SESS_HANDLE 0xFFFFFFFF
6733b39a 100
9343be74
JK		 101/**
102 * Adapter States
103 **/
3567f36a
JK		 104#define BE_ADAPTER_LINK_UP 0x001
105#define BE_ADAPTER_LINK_DOWN 0x002
106#define BE_ADAPTER_PCI_ERR 0x004
cdaa4ded 107#define BE_ADAPTER_CHECK_BOOT 0x008
9343be74 108
3567f36a
JK		 109
110#define BEISCSI_CLEAN_UNLOAD 0x01
111#define BEISCSI_EEH_UNLOAD 0x02
3efde862
JSJ		 112
113#define BE_GET_BOOT_RETRIES 45
114#define BE_GET_BOOT_TO 20
6733b39a
JK		 115/**
116 * hardware needs the async PDU buffers to be posted in multiples of 8
117 * So have atleast 8 of them by default
118 */
119
8a86e833
JK		 120#define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num) \
121 (phwi->phwi_ctxt->pasync_ctx[ulp_num])
6733b39a
JK		 122
123/********* Memory BAR register ************/
457ff3b7 124#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
6733b39a
JK		 125/**
126 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
127 * Disable" may still globally block interrupts in addition to individual
128 * interrupt masks; a mechanism for the device driver to block all interrupts
129 * atomically without having to arbitrate for the PCI Interrupt Disable bit
130 * with the OS.
131 */
132#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
133
134/********* ISR0 Register offset **********/
457ff3b7 135#define CEV_ISR0_OFFSET 0xC18
6733b39a
JK		 136#define CEV_ISR_SIZE 4
137
138/**
139 * Macros for reading/writing a protection domain or CSR registers
140 * in BladeEngine.
141 */
142
143#define DB_TXULP0_OFFSET 0x40
144#define DB_RXULP0_OFFSET 0xA0
145/********* Event Q door bell *************/
146#define DB_EQ_OFFSET DB_CQ_OFFSET
e08b3c8b 147#define DB_EQ_RING_ID_LOW_MASK 0x1FF /* bits 0 - 8 */
6733b39a
JK		 148/* Clear the interrupt for this eq */
149#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
150/* Must be 1 */
151#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
e08b3c8b
JK		 152/* Higher Order EQ_ID bit */
153#define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
154#define DB_EQ_HIGH_SET_SHIFT 11
155#define DB_EQ_HIGH_FEILD_SHIFT 9
6733b39a
JK		 156/* Number of event entries processed */
157#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
158/* Rearm bit */
159#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
160
161/********* Compl Q door bell *************/
457ff3b7 162#define DB_CQ_OFFSET 0x120
e08b3c8b
JK		 163#define DB_CQ_RING_ID_LOW_MASK 0x3FF /* bits 0 - 9 */
164/* Higher Order CQ_ID bit */
165#define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
166#define DB_CQ_HIGH_SET_SHIFT 11
167#define DB_CQ_HIGH_FEILD_SHIFT 10
168
6733b39a 169/* Number of event entries processed */
457ff3b7 170#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
6733b39a 171/* Rearm bit */
457ff3b7 172#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
6733b39a
JK		 173
174#define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
8a86e833
JK		 175#define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
176 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
177#define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
178 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
6733b39a
JK		 179
180#define PAGES_REQUIRED(x) \
181 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
182
8fcfb210
JK		 183#define BEISCSI_MSI_NAME 20 /* size of msi_name string */
184
a129d92f 185#define MEM_DESCR_OFFSET 8
8a86e833
JK		 186#define BEISCSI_DEFQ_HDR 1
187#define BEISCSI_DEFQ_DATA 0
6733b39a
JK		 188enum be_mem_enum {
189 HWI_MEM_ADDN_CONTEXT,
6733b39a
JK		 190 HWI_MEM_WRB,
191 HWI_MEM_WRBH,
bfead3b2 192 HWI_MEM_SGLH,
6733b39a 193 HWI_MEM_SGE,
a129d92f
JK		 194 HWI_MEM_TEMPLATE_HDR_ULP0,
195 HWI_MEM_ASYNC_HEADER_BUF_ULP0, /* 6 */
8a86e833
JK		 196 HWI_MEM_ASYNC_DATA_BUF_ULP0,
197 HWI_MEM_ASYNC_HEADER_RING_ULP0,
198 HWI_MEM_ASYNC_DATA_RING_ULP0,
199 HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
a129d92f 200 HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
8a86e833 201 HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
a129d92f
JK		 202 HWI_MEM_TEMPLATE_HDR_ULP1,
203 HWI_MEM_ASYNC_HEADER_BUF_ULP1, /* 14 */
8a86e833
JK		 204 HWI_MEM_ASYNC_DATA_BUF_ULP1,
205 HWI_MEM_ASYNC_HEADER_RING_ULP1,
206 HWI_MEM_ASYNC_DATA_RING_ULP1,
207 HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
a129d92f 208 HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
8a86e833 209 HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
6733b39a 210 ISCSI_MEM_GLOBAL_HEADER,
bfead3b2 211 SE_MEM_MAX
6733b39a
JK		 212};
213
214struct be_bus_address32 {
215 unsigned int address_lo;
216 unsigned int address_hi;
217};
218
219struct be_bus_address64 {
220 unsigned long long address;
221};
222
223struct be_bus_address {
224 union {
225 struct be_bus_address32 a32;
226 struct be_bus_address64 a64;
227 } u;
228};
229
230struct mem_array {
231 struct be_bus_address bus_address; /* Bus address of location */
232 void *virtual_address; /* virtual address to the location */
233 unsigned int size; /* Size required by memory block */
234};
235
236struct be_mem_descriptor {
237 unsigned int index; /* Index of this memory parameter */
238 unsigned int category; /* type indicates cached/non-cached */
239 unsigned int num_elements; /* number of elements in this
240 * descriptor
241 */
242 unsigned int alignment_mask; /* Alignment mask for this block */
243 unsigned int size_in_bytes; /* Size required by memory block */
244 struct mem_array *mem_array;
245};
246
247struct sgl_handle {
248 unsigned int sgl_index;
bfead3b2
JK		 249 unsigned int type;
250 unsigned int cid;
251 struct iscsi_task *task;
6733b39a
JK		 252 struct iscsi_sge *pfrag;
253};
254
255struct hba_parameters {
256 unsigned int ios_per_ctrl;
257 unsigned int cxns_per_ctrl;
258 unsigned int asyncpdus_per_ctrl;
259 unsigned int icds_per_ctrl;
260 unsigned int num_sge_per_io;
261 unsigned int defpdu_hdr_sz;
262 unsigned int defpdu_data_sz;
263 unsigned int num_cq_entries;
264 unsigned int num_eq_entries;
265 unsigned int wrbs_per_cxn;
266 unsigned int crashmode;
267 unsigned int hba_num;
268
269 unsigned int mgmt_ws_sz;
270 unsigned int hwi_ws_sz;
271
272 unsigned int eto;
273 unsigned int ldto;
274
275 unsigned int dbg_flags;
276 unsigned int num_cxn;
277
278 unsigned int eq_timer;
279 /**
280 * These are calculated from other params. They're here
281 * for debug purposes
282 */
283 unsigned int num_mcc_pages;
284 unsigned int num_mcc_cq_pages;
285 unsigned int num_cq_pages;
286 unsigned int num_eq_pages;
287
288 unsigned int num_async_pdu_buf_pages;
289 unsigned int num_async_pdu_buf_sgl_pages;
290 unsigned int num_async_pdu_buf_cq_pages;
291
292 unsigned int num_async_pdu_hdr_pages;
293 unsigned int num_async_pdu_hdr_sgl_pages;
294 unsigned int num_async_pdu_hdr_cq_pages;
295
296 unsigned int num_sge;
297};
298
4183122d
JK		 299struct invalidate_command_table {
300 unsigned short icd;
301 unsigned short cid;
302} __packed;
303
4eea99d5
JK		 304#define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
305 (phwi_ctrlr->wrb_context[cri].ulp_num)
306struct hwi_wrb_context {
307 struct list_head wrb_handle_list;
308 struct list_head wrb_handle_drvr_list;
309 struct wrb_handle **pwrb_handle_base;
310 struct wrb_handle **pwrb_handle_basestd;
311 struct iscsi_wrb *plast_wrb;
312 unsigned short alloc_index;
313 unsigned short free_index;
314 unsigned short wrb_handles_available;
315 unsigned short cid;
316 uint8_t ulp_num; /* ULP to which CID binded */
317 uint16_t register_set;
318 uint16_t doorbell_format;
319 uint32_t doorbell_offset;
320};
321
0a3db7c0
JK		 322struct ulp_cid_info {
323 unsigned short *cid_array;
324 unsigned short avlbl_cids;
325 unsigned short cid_alloc;
326 unsigned short cid_free;
327};
328
4eea99d5 329#include "be.h"
2c9dfd36
JK		 330#define chip_be2(phba) (phba->generation == BE_GEN2)
331#define chip_be3_r(phba) (phba->generation == BE_GEN3)
332#define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
843ae752
JK		 333
334#define BEISCSI_ULP0 0
335#define BEISCSI_ULP1 1
336#define BEISCSI_ULP_COUNT 2
337#define BEISCSI_ULP0_LOADED 0x01
338#define BEISCSI_ULP1_LOADED 0x02
0a3db7c0
JK		 339
340#define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
341 (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
342#define BEISCSI_ULP0_AVLBL_CID(phba) \
343 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
344#define BEISCSI_ULP1_AVLBL_CID(phba) \
345 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
346
6733b39a
JK		 347struct beiscsi_hba {
348 struct hba_parameters params;
349 struct hwi_controller *phwi_ctrlr;
350 unsigned int mem_req[SE_MEM_MAX];
351 /* PCI BAR mapped addresses */
352 u8 __iomem *csr_va; /* CSR */
353 u8 __iomem *db_va; /* Door Bell */
354 u8 __iomem *pci_va; /* PCI Config */
355 struct be_bus_address csr_pa; /* CSR */
356 struct be_bus_address db_pa; /* CSR */
357 struct be_bus_address pci_pa; /* CSR */
358 /* PCI representation of our HBA */
359 struct pci_dev *pcidev;
6733b39a 360 unsigned short asic_revision;
bfead3b2
JK		 361 unsigned int num_cpus;
362 unsigned int nxt_cqid;
22abeef0
JSJ		 363 struct msix_entry msix_entries[MAX_CPUS];
364 char *msi_name[MAX_CPUS];
bfead3b2 365 bool msix_enabled;
6733b39a
JK		 366 struct be_mem_descriptor *init_mem;
367
368 unsigned short io_sgl_alloc_index;
369 unsigned short io_sgl_free_index;
370 unsigned short io_sgl_hndl_avbl;
371 struct sgl_handle **io_sgl_hndl_base;
bfead3b2 372 struct sgl_handle **sgl_hndl_array;
6733b39a
JK		 373
374 unsigned short eh_sgl_alloc_index;
375 unsigned short eh_sgl_free_index;
376 unsigned short eh_sgl_hndl_avbl;
377 struct sgl_handle **eh_sgl_hndl_base;
378 spinlock_t io_sgl_lock;
379 spinlock_t mgmt_sgl_lock;
380 spinlock_t isr_lock;
8f09a3b9 381 spinlock_t async_pdu_lock;
6733b39a 382 unsigned int age;
6733b39a 383 struct list_head hba_queue;
a7909b39
JK		 384#define BE_MAX_SESSION 2048
385#define BE_SET_CID_TO_CRI(cri_index, cid) \
386 (phba->cid_to_cri_map[cid] = cri_index)
387#define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
388 unsigned short cid_to_cri_map[BE_MAX_SESSION];
0a3db7c0 389 struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
6733b39a 390 struct iscsi_endpoint **ep_array;
a7909b39 391 struct beiscsi_conn **conn_table;
c7acc5b8 392 struct iscsi_boot_kset *boot_kset;
6733b39a 393 struct Scsi_Host *shost;
0e43895e
MC		 394 struct iscsi_iface *ipv4_iface;
395 struct iscsi_iface *ipv6_iface;
6733b39a
JK		 396 struct {
397 /**
398 * group together since they are used most frequently
399 * for cid to cri conversion
400 */
4570f161 401#define BEISCSI_PHYS_PORT_MAX 4
6733b39a 402 unsigned int phys_port;
4570f161 403 /* valid values of phys_port id are 0, 1, 2, 3 */
68c26a3a
JK		 404 unsigned int eqid_count;
405 unsigned int cqid_count;
843ae752
JK		 406 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
407#define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
8a86e833 408 (phba->fw_config.iscsi_cid_count[ulp_num])
843ae752
JK		 409 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
410 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
411 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
412 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
413 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
6733b39a 414
bfead3b2 415 unsigned short iscsi_features;
843ae752
JK		 416 uint16_t dual_ulp_aware;
417 unsigned long ulp_supported;
6733b39a
JK		 418 } fw_config;
419
e175defe 420 unsigned int state;
53aefe25 421 u8 optic_state;
3efde862 422 int get_boot;
e175defe
JSJ		 423 bool fw_timeout;
424 bool ue_detected;
425 struct delayed_work beiscsi_hw_check_task;
426
6c83185a 427 bool mac_addr_set;
6733b39a 428 u8 mac_address[ETH_ALEN];
53aefe25 429 u8 port_name;
048084c2 430 u8 port_speed;
22661e25 431 char fw_ver_str[BEISCSI_VER_STRLEN];
6733b39a
JK		 432 char wq_name[20];
433 struct workqueue_struct *wq; /* The actuak work queue */
6733b39a 434 struct be_ctrl_info ctrl;
f98c96b0 435 unsigned int generation;
0e43895e 436 unsigned int interface_handle;
c7acc5b8 437 struct mgmt_session_info boot_sess;
4183122d
JK		 438 struct invalidate_command_table inv_tbl[128];
439
73af08e1 440 struct be_aic_obj aic_obj[MAX_CPUS];
99bc5d55 441 unsigned int attr_log_enable;
09a1093a
JSJ		 442 int (*iotask_fn)(struct iscsi_task *,
443 struct scatterlist *sg,
444 uint32_t num_sg, uint32_t xferlen,
445 uint32_t writedir);
6733b39a
JK		 446};
447
b8b9e1b8
JK		 448struct beiscsi_session {
449 struct pci_pool *bhs_pool;
450};
451
6733b39a
JK		 452/**
453 * struct beiscsi_conn - iscsi connection structure
454 */
455struct beiscsi_conn {
456 struct iscsi_conn *conn;
457 struct beiscsi_hba *phba;
458 u32 exp_statsn;
1e4be6ff 459 u32 doorbell_offset;
6733b39a
JK		 460 u32 beiscsi_conn_cid;
461 struct beiscsi_endpoint *ep;
462 unsigned short login_in_progress;
d2cecf0d 463 struct wrb_handle *plogin_wrb_handle;
6733b39a 464 struct sgl_handle *plogin_sgl_handle;
b8b9e1b8 465 struct beiscsi_session *beiscsi_sess;
bfead3b2 466 struct iscsi_task *task;
6733b39a
JK		 467};
468
469/* This structure is used by the chip */
470struct pdu_data_out {
471 u32 dw[12];
472};
473/**
474 * Pseudo amap definition in which each bit of the actual structure is defined
475 * as a byte: used to calculate offset/shift/mask of each field
476 */
477struct amap_pdu_data_out {
478 u8 opcode[6]; /* opcode */
479 u8 rsvd0[2]; /* should be 0 */
480 u8 rsvd1[7];
481 u8 final_bit; /* F bit */
482 u8 rsvd2[16];
483 u8 ahs_length[8]; /* no AHS */
484 u8 data_len_hi[8];
485 u8 data_len_lo[16]; /* DataSegmentLength */
486 u8 lun[64];
487 u8 itt[32]; /* ITT; initiator task tag */
488 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
489 u8 rsvd3[32];
490 u8 exp_stat_sn[32];
491 u8 rsvd4[32];
492 u8 data_sn[32];
493 u8 buffer_offset[32];
494 u8 rsvd5[32];
495};
496
497struct be_cmd_bhs {
12352183 498 struct iscsi_scsi_req iscsi_hdr;
6733b39a
JK		 499 unsigned char pad1[16];
500 struct pdu_data_out iscsi_data_pdu;
501 unsigned char pad2[BE_SENSE_INFO_SIZE -
502 sizeof(struct pdu_data_out)];
503};
504
505struct beiscsi_io_task {
506 struct wrb_handle *pwrb_handle;
507 struct sgl_handle *psgl_handle;
508 struct beiscsi_conn *conn;
509 struct scsi_cmnd *scsi_cmnd;
340c99e9 510 struct hwi_wrb_context *pwrb_context;
6733b39a
JK		 511 unsigned int cmd_sn;
512 unsigned int flags;
513 unsigned short cid;
514 unsigned short header_len;
bfead3b2 515 itt_t libiscsi_itt;
6733b39a
JK		 516 struct be_cmd_bhs *cmd_bhs;
517 struct be_bus_address bhs_pa;
518 unsigned short bhs_len;
d629c471
JSJ		 519 dma_addr_t mtask_addr;
520 uint32_t mtask_data_count;
09a1093a 521 uint8_t wrb_type;
6733b39a
JK		 522};
523
524struct be_nonio_bhs {
525 struct iscsi_hdr iscsi_hdr;
526 unsigned char pad1[16];
527 struct pdu_data_out iscsi_data_pdu;
528 unsigned char pad2[BE_SENSE_INFO_SIZE -
529 sizeof(struct pdu_data_out)];
530};
531
532struct be_status_bhs {
12352183 533 struct iscsi_scsi_req iscsi_hdr;
6733b39a
JK		 534 unsigned char pad1[16];
535 /**
536 * The plus 2 below is to hold the sense info length that gets
537 * DMA'ed by RxULP
538 */
539 unsigned char sense_info[BE_SENSE_INFO_SIZE];
540};
541
542struct iscsi_sge {
543 u32 dw[4];
544};
545
546/**
547 * Pseudo amap definition in which each bit of the actual structure is defined
548 * as a byte: used to calculate offset/shift/mask of each field
549 */
550struct amap_iscsi_sge {
551 u8 addr_hi[32];
552 u8 addr_lo[32];
553 u8 sge_offset[22]; /* DWORD 2 */
554 u8 rsvd0[9]; /* DWORD 2 */
555 u8 last_sge; /* DWORD 2 */
556 u8 len[17]; /* DWORD 3 */
557 u8 rsvd1[15]; /* DWORD 3 */
558};
559
560struct beiscsi_offload_params {
7331613e 561 u32 dw[6];
6733b39a
JK		 562};
563
564#define OFFLD_PARAMS_ERL 0x00000003
565#define OFFLD_PARAMS_DDE 0x00000004
566#define OFFLD_PARAMS_HDE 0x00000008
567#define OFFLD_PARAMS_IR2T 0x00000010
568#define OFFLD_PARAMS_IMD 0x00000020
acb9693c
JSJ		 569#define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040
570#define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080
571#define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
6733b39a
JK		 572
573/**
574 * Pseudo amap definition in which each bit of the actual structure is defined
575 * as a byte: used to calculate offset/shift/mask of each field
576 */
577struct amap_beiscsi_offload_params {
578 u8 max_burst_length[32];
579 u8 max_send_data_segment_length[32];
580 u8 first_burst_length[32];
581 u8 erl[2];
582 u8 dde[1];
583 u8 hde[1];
584 u8 ir2t[1];
585 u8 imd[1];
acb9693c
JSJ		 586 u8 data_seq_inorder[1];
587 u8 pdu_seq_inorder[1];
588 u8 max_r2t[16];
589 u8 pad[8];
6733b39a 590 u8 exp_statsn[32];
7331613e 591 u8 max_recv_data_segment_length[32];
6733b39a
JK		 592};
593
594/* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
595 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
596
597struct async_pdu_handle {
598 struct list_head link;
599 struct be_bus_address pa;
600 void *pbuffer;
601 unsigned int consumed;
602 unsigned char index;
603 unsigned char is_header;
604 unsigned short cri;
605 unsigned long buffer_len;
606};
607
608struct hwi_async_entry {
609 struct {
610 unsigned char hdr_received;
611 unsigned char hdr_len;
612 unsigned short bytes_received;
613 unsigned int bytes_needed;
614 struct list_head list;
615 } wait_queue;
616
617 struct list_head header_busy_list;
618 struct list_head data_busy_list;
619};
620
6733b39a
JK		 621struct hwi_async_pdu_context {
622 struct {
623 struct be_bus_address pa_base;
624 void *va_base;
625 void *ring_base;
626 struct async_pdu_handle *handle_base;
627
628 unsigned int host_write_ptr;
629 unsigned int ep_read_ptr;
630 unsigned int writables;
631
632 unsigned int free_entries;
633 unsigned int busy_entries;
6733b39a
JK		 634
635 struct list_head free_list;
636 } async_header;
637
638 struct {
639 struct be_bus_address pa_base;
640 void *va_base;
641 void *ring_base;
642 struct async_pdu_handle *handle_base;
643
644 unsigned int host_write_ptr;
645 unsigned int ep_read_ptr;
646 unsigned int writables;
647
648 unsigned int free_entries;
649 unsigned int busy_entries;
6733b39a 650 struct list_head free_list;
6733b39a
JK		 651 } async_data;
652
dc63aac6
JK		 653 unsigned int buffer_size;
654 unsigned int num_entries;
8a86e833
JK		 655#define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
656 unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
6733b39a
JK		 657 /**
658 * This is a varying size list! Do not add anything
659 * after this entry!!
660 */
a7909b39 661 struct hwi_async_entry *async_entry;
6733b39a
JK		 662};
663
664#define PDUCQE_CODE_MASK 0x0000003F
665#define PDUCQE_DPL_MASK 0xFFFF0000
666#define PDUCQE_INDEX_MASK 0x0000FFFF
667
668struct i_t_dpdu_cqe {
669 u32 dw[4];
670} __packed;
671
672/**
673 * Pseudo amap definition in which each bit of the actual structure is defined
674 * as a byte: used to calculate offset/shift/mask of each field
675 */
676struct amap_i_t_dpdu_cqe {
677 u8 db_addr_hi[32];
678 u8 db_addr_lo[32];
679 u8 code[6];
680 u8 cid[10];
681 u8 dpl[16];
682 u8 index[16];
683 u8 num_cons[10];
684 u8 rsvd0[4];
685 u8 final;
686 u8 valid;
687} __packed;
688
73133261
JSJ		 689struct amap_i_t_dpdu_cqe_v2 {
690 u8 db_addr_hi[32]; /* DWORD 0 */
691 u8 db_addr_lo[32]; /* DWORD 1 */
692 u8 code[6]; /* DWORD 2 */
693 u8 num_cons; /* DWORD 2*/
694 u8 rsvd0[8]; /* DWORD 2 */
695 u8 dpl[17]; /* DWORD 2 */
696 u8 index[16]; /* DWORD 3 */
697 u8 cid[13]; /* DWORD 3 */
698 u8 rsvd1; /* DWORD 3 */
699 u8 final; /* DWORD 3 */
700 u8 valid; /* DWORD 3 */
701} __packed;
702
6733b39a
JK		 703#define CQE_VALID_MASK 0x80000000
704#define CQE_CODE_MASK 0x0000003F
705#define CQE_CID_MASK 0x0000FFC0
706
707#define EQE_VALID_MASK 0x00000001
708#define EQE_MAJORCODE_MASK 0x0000000E
709#define EQE_RESID_MASK 0xFFFF0000
710
711struct be_eq_entry {
712 u32 dw[1];
713} __packed;
714
715/**
716 * Pseudo amap definition in which each bit of the actual structure is defined
717 * as a byte: used to calculate offset/shift/mask of each field
718 */
719struct amap_eq_entry {
720 u8 valid; /* DWORD 0 */
721 u8 major_code[3]; /* DWORD 0 */
722 u8 minor_code[12]; /* DWORD 0 */
723 u8 resource_id[16]; /* DWORD 0 */
724
725} __packed;
726
727struct cq_db {
728 u32 dw[1];
729} __packed;
730
731/**
732 * Pseudo amap definition in which each bit of the actual structure is defined
733 * as a byte: used to calculate offset/shift/mask of each field
734 */
735struct amap_cq_db {
736 u8 qid[10];
737 u8 event[1];
738 u8 rsvd0[5];
739 u8 num_popped[13];
740 u8 rearm[1];
741 u8 rsvd1[2];
742} __packed;
743
744void beiscsi_process_eq(struct beiscsi_hba *phba);
745
6733b39a
JK		 746struct iscsi_wrb {
747 u32 dw[16];
748} __packed;
749
750#define WRB_TYPE_MASK 0xF0000000
09a1093a
JSJ		 751#define SKH_WRB_TYPE_OFFSET 27
752#define BE_WRB_TYPE_OFFSET 28
753
754#define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
755 (pwrb->dw[0] |= (wrb_type << type_offset))
6733b39a
JK		 756
757/**
758 * Pseudo amap definition in which each bit of the actual structure is defined
759 * as a byte: used to calculate offset/shift/mask of each field
760 */
761struct amap_iscsi_wrb {
762 u8 lun[14]; /* DWORD 0 */
763 u8 lt; /* DWORD 0 */
764 u8 invld; /* DWORD 0 */
765 u8 wrb_idx[8]; /* DWORD 0 */
766 u8 dsp; /* DWORD 0 */
767 u8 dmsg; /* DWORD 0 */
768 u8 undr_run; /* DWORD 0 */
769 u8 over_run; /* DWORD 0 */
770 u8 type[4]; /* DWORD 0 */
771 u8 ptr2nextwrb[8]; /* DWORD 1 */
772 u8 r2t_exp_dtl[24]; /* DWORD 1 */
773 u8 sgl_icd_idx[12]; /* DWORD 2 */
774 u8 rsvd0[20]; /* DWORD 2 */
775 u8 exp_data_sn[32]; /* DWORD 3 */
776 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
777 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
778 u8 cmdsn_itt[32]; /* DWORD 6 */
779 u8 dif_ref_tag[32]; /* DWORD 7 */
780 u8 sge0_addr_hi[32]; /* DWORD 8 */
781 u8 sge0_addr_lo[32]; /* DWORD 9 */
782 u8 sge0_offset[22]; /* DWORD 10 */
783 u8 pbs; /* DWORD 10 */
784 u8 dif_mode[2]; /* DWORD 10 */
785 u8 rsvd1[6]; /* DWORD 10 */
786 u8 sge0_last; /* DWORD 10 */
787 u8 sge0_len[17]; /* DWORD 11 */
788 u8 dif_meta_tag[14]; /* DWORD 11 */
789 u8 sge0_in_ddr; /* DWORD 11 */
790 u8 sge1_addr_hi[32]; /* DWORD 12 */
791 u8 sge1_addr_lo[32]; /* DWORD 13 */
792 u8 sge1_r2t_offset[22]; /* DWORD 14 */
793 u8 rsvd2[9]; /* DWORD 14 */
794 u8 sge1_last; /* DWORD 14 */
795 u8 sge1_len[17]; /* DWORD 15 */
796 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
797 u8 rsvd3[2]; /* DWORD 15 */
798 u8 sge1_in_ddr; /* DWORD 15 */
799
800} __packed;
801
09a1093a
JSJ		 802struct amap_iscsi_wrb_v2 {
803 u8 r2t_exp_dtl[25]; /* DWORD 0 */
804 u8 rsvd0[2]; /* DWORD 0*/
805 u8 type[5]; /* DWORD 0 */
806 u8 ptr2nextwrb[8]; /* DWORD 1 */
807 u8 wrb_idx[8]; /* DWORD 1 */
808 u8 lun[16]; /* DWORD 1 */
809 u8 sgl_idx[16]; /* DWORD 2 */
810 u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
811 u8 exp_data_sn[32]; /* DWORD 3 */
812 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
813 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
814 u8 cq_id[16]; /* DWORD 6 */
815 u8 rsvd1[16]; /* DWORD 6 */
816 u8 cmdsn_itt[32]; /* DWORD 7 */
817 u8 sge0_addr_hi[32]; /* DWORD 8 */
818 u8 sge0_addr_lo[32]; /* DWORD 9 */
819 u8 sge0_offset[24]; /* DWORD 10 */
820 u8 rsvd2[7]; /* DWORD 10 */
821 u8 sge0_last; /* DWORD 10 */
822 u8 sge0_len[17]; /* DWORD 11 */
823 u8 rsvd3[7]; /* DWORD 11 */
824 u8 diff_enbl; /* DWORD 11 */
825 u8 u_run; /* DWORD 11 */
826 u8 o_run; /* DWORD 11 */
827 u8 invalid; /* DWORD 11 */
828 u8 dsp; /* DWORD 11 */
829 u8 dmsg; /* DWORD 11 */
830 u8 rsvd4; /* DWORD 11 */
831 u8 lt; /* DWORD 11 */
832 u8 sge1_addr_hi[32]; /* DWORD 12 */
833 u8 sge1_addr_lo[32]; /* DWORD 13 */
834 u8 sge1_r2t_offset[24]; /* DWORD 14 */
835 u8 rsvd5[7]; /* DWORD 14 */
836 u8 sge1_last; /* DWORD 14 */
837 u8 sge1_len[17]; /* DWORD 15 */
838 u8 rsvd6[15]; /* DWORD 15 */
839} __packed;
840
841
340c99e9
JSJ		 842struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
843 struct hwi_wrb_context **pcontext);
6733b39a
JK		 844void
845free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
846
756d29c8 847void beiscsi_process_all_cqs(struct work_struct *work);
4a4a11b9
JK		 848void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
849 struct iscsi_task *task);
756d29c8 850
e08b3c8b
JK		 851void hwi_ring_cq_db(struct beiscsi_hba *phba,
852 unsigned int id, unsigned int num_processed,
1094cf68 853 unsigned char rearm);
b7ab35b1 854
1094cf68 855unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget);
b7ab35b1 856
7a158003
JSJ		 857static inline bool beiscsi_error(struct beiscsi_hba *phba)
858{
859 return phba->ue_detected || phba->fw_timeout;
860}
861
6733b39a
JK		 862struct pdu_nop_out {
863 u32 dw[12];
864};
865
866/**
867 * Pseudo amap definition in which each bit of the actual structure is defined
868 * as a byte: used to calculate offset/shift/mask of each field
869 */
870struct amap_pdu_nop_out {
871 u8 opcode[6]; /* opcode 0x00 */
872 u8 i_bit; /* I Bit */
873 u8 x_bit; /* reserved; should be 0 */
874 u8 fp_bit_filler1[7];
875 u8 f_bit; /* always 1 */
876 u8 reserved1[16];
877 u8 ahs_length[8]; /* no AHS */
878 u8 data_len_hi[8];
879 u8 data_len_lo[16]; /* DataSegmentLength */
880 u8 lun[64];
881 u8 itt[32]; /* initiator id for ping or 0xffffffff */
882 u8 ttt[32]; /* target id for ping or 0xffffffff */
883 u8 cmd_sn[32];
884 u8 exp_stat_sn[32];
885 u8 reserved5[128];
886};
887
888#define PDUBASE_OPCODE_MASK 0x0000003F
889#define PDUBASE_DATALENHI_MASK 0x0000FF00
890#define PDUBASE_DATALENLO_MASK 0xFFFF0000
891
892struct pdu_base {
893 u32 dw[16];
894} __packed;
895
896/**
897 * Pseudo amap definition in which each bit of the actual structure is defined
898 * as a byte: used to calculate offset/shift/mask of each field
899 */
900struct amap_pdu_base {
901 u8 opcode[6];
902 u8 i_bit; /* immediate bit */
903 u8 x_bit; /* reserved, always 0 */
904 u8 reserved1[24]; /* opcode-specific fields */
905 u8 ahs_length[8]; /* length units is 4 byte words */
906 u8 data_len_hi[8];
907 u8 data_len_lo[16]; /* DatasegmentLength */
908 u8 lun[64]; /* lun or opcode-specific fields */
909 u8 itt[32]; /* initiator task tag */
910 u8 reserved4[224];
911};
912
913struct iscsi_target_context_update_wrb {
914 u32 dw[16];
915} __packed;
916
917/**
918 * Pseudo amap definition in which each bit of the actual structure is defined
919 * as a byte: used to calculate offset/shift/mask of each field
920 */
acb9693c 921#define BE_TGT_CTX_UPDT_CMD 0x07
6733b39a
JK		 922struct amap_iscsi_target_context_update_wrb {
923 u8 lun[14]; /* DWORD 0 */
924 u8 lt; /* DWORD 0 */
925 u8 invld; /* DWORD 0 */
926 u8 wrb_idx[8]; /* DWORD 0 */
927 u8 dsp; /* DWORD 0 */
928 u8 dmsg; /* DWORD 0 */
929 u8 undr_run; /* DWORD 0 */
930 u8 over_run; /* DWORD 0 */
931 u8 type[4]; /* DWORD 0 */
932 u8 ptr2nextwrb[8]; /* DWORD 1 */
933 u8 max_burst_length[19]; /* DWORD 1 */
934 u8 rsvd0[5]; /* DWORD 1 */
935 u8 rsvd1[15]; /* DWORD 2 */
936 u8 max_send_data_segment_length[17]; /* DWORD 2 */
937 u8 first_burst_length[14]; /* DWORD 3 */
938 u8 rsvd2[2]; /* DWORD 3 */
939 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
940 u8 rsvd3[5]; /* DWORD 3 */
941 u8 session_state[3]; /* DWORD 3 */
942 u8 rsvd4[16]; /* DWORD 4 */
943 u8 tx_jumbo; /* DWORD 4 */
944 u8 hde; /* DWORD 4 */
945 u8 dde; /* DWORD 4 */
946 u8 erl[2]; /* DWORD 4 */
947 u8 domain_id[5]; /* DWORD 4 */
948 u8 mode; /* DWORD 4 */
949 u8 imd; /* DWORD 4 */
950 u8 ir2t; /* DWORD 4 */
951 u8 notpredblq[2]; /* DWORD 4 */
952 u8 compltonack; /* DWORD 4 */
953 u8 stat_sn[32]; /* DWORD 5 */
954 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
955 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
956 u8 pad_addr_hi[32]; /* DWORD 8 */
957 u8 pad_addr_lo[32]; /* DWORD 9 */
958 u8 rsvd5[32]; /* DWORD 10 */
959 u8 rsvd6[32]; /* DWORD 11 */
960 u8 rsvd7[32]; /* DWORD 12 */
961 u8 rsvd8[32]; /* DWORD 13 */
962 u8 rsvd9[32]; /* DWORD 14 */
963 u8 rsvd10[32]; /* DWORD 15 */
964
965} __packed;
966
acb9693c
JSJ		 967#define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024)
968#define BEISCSI_MAX_CXNS 1
969struct amap_iscsi_target_context_update_wrb_v2 {
970 u8 max_burst_length[24]; /* DWORD 0 */
971 u8 rsvd0[3]; /* DWORD 0 */
972 u8 type[5]; /* DWORD 0 */
973 u8 ptr2nextwrb[8]; /* DWORD 1 */
974 u8 wrb_idx[8]; /* DWORD 1 */
975 u8 rsvd1[16]; /* DWORD 1 */
976 u8 max_send_data_segment_length[24]; /* DWORD 2 */
977 u8 rsvd2[8]; /* DWORD 2 */
978 u8 first_burst_length[24]; /* DWORD 3 */
979 u8 rsvd3[8]; /* DOWRD 3 */
980 u8 max_r2t[16]; /* DWORD 4 */
7331613e 981 u8 rsvd4; /* DWORD 4 */
acb9693c
JSJ		 982 u8 hde; /* DWORD 4 */
983 u8 dde; /* DWORD 4 */
984 u8 erl[2]; /* DWORD 4 */
7331613e 985 u8 rsvd5[6]; /* DWORD 4 */
acb9693c
JSJ		 986 u8 imd; /* DWORD 4 */
987 u8 ir2t; /* DWORD 4 */
7331613e 988 u8 rsvd6[3]; /* DWORD 4 */
acb9693c 989 u8 stat_sn[32]; /* DWORD 5 */
7331613e
JK		 990 u8 rsvd7[32]; /* DWORD 6 */
991 u8 rsvd8[32]; /* DWORD 7 */
acb9693c 992 u8 max_recv_dataseg_len[24]; /* DWORD 8 */
7331613e
JK		 993 u8 rsvd9[8]; /* DWORD 8 */
994 u8 rsvd10[32]; /* DWORD 9 */
995 u8 rsvd11[32]; /* DWORD 10 */
acb9693c 996 u8 max_cxns[16]; /* DWORD 11 */
7331613e 997 u8 rsvd12[11]; /* DWORD 11*/
acb9693c 998 u8 invld; /* DWORD 11 */
7331613e 999 u8 rsvd13;/* DWORD 11*/
acb9693c
JSJ		 1000 u8 dmsg; /* DWORD 11 */
1001 u8 data_seq_inorder; /* DWORD 11 */
1002 u8 pdu_seq_inorder; /* DWORD 11 */
7331613e
JK		 1003 u8 rsvd14[32]; /*DWORD 12 */
1004 u8 rsvd15[32]; /* DWORD 13 */
1005 u8 rsvd16[32]; /* DWORD 14 */
1006 u8 rsvd17[32]; /* DWORD 15 */
acb9693c
JSJ		 1007} __packed;
1008
1009
6733b39a
JK		 1010struct be_ring {
1011 u32 pages; /* queue size in pages */
1012 u32 id; /* queue id assigned by beklib */
1013 u32 num; /* number of elements in queue */
1014 u32 cidx; /* consumer index */
1015 u32 pidx; /* producer index -- not used by most rings */
1016 u32 item_size; /* size in bytes of one object */
8a86e833
JK		 1017 u8 ulp_num; /* ULP to which CID binded */
1018 u16 register_set;
1019 u16 doorbell_format;
1020 u32 doorbell_offset;
6733b39a
JK		 1021
1022 void *va; /* The virtual address of the ring. This
1023 * should be last to allow 32 & 64 bit debugger
1024 * extensions to work.
1025 */
1026};
1027
6733b39a
JK		 1028struct hwi_controller {
1029 struct list_head io_sgl_list;
1030 struct list_head eh_sgl_list;
1031 struct sgl_handle *psgl_handle_base;
1032 unsigned int wrb_mem_index;
1033
a7909b39 1034 struct hwi_wrb_context *wrb_context;
6733b39a 1035 struct mcc_wrb *pmcc_wrb_base;
8a86e833
JK		 1036 struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
1037 struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
6733b39a 1038 struct hwi_context_memory *phwi_ctxt;
6733b39a
JK		 1039};
1040
1041enum hwh_type_enum {
1042 HWH_TYPE_IO = 1,
1043 HWH_TYPE_LOGOUT = 2,
1044 HWH_TYPE_TMF = 3,
1045 HWH_TYPE_NOP = 4,
1046 HWH_TYPE_IO_RD = 5,
1047 HWH_TYPE_LOGIN = 11,
1048 HWH_TYPE_INVALID = 0xFFFFFFFF
1049};
1050
1051struct wrb_handle {
1052 enum hwh_type_enum type;
1053 unsigned short wrb_index;
6733b39a
JK		 1054
1055 struct iscsi_task *pio_handle;
1056 struct iscsi_wrb *pwrb;
1057};
1058
1059struct hwi_context_memory {
bfead3b2
JK		 1060 /* Adaptive interrupt coalescing (AIC) info */
1061 u16 min_eqd; /* in usecs */
1062 u16 max_eqd; /* in usecs */
1063 u16 cur_eqd; /* in usecs */
1064 struct be_eq_obj be_eq[MAX_CPUS];
22abeef0 1065 struct be_queue_info be_cq[MAX_CPUS - 1];
6733b39a 1066
a7909b39 1067 struct be_queue_info *be_wrbq;
8a86e833
JK		 1068 struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1069 struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1070 struct hwi_async_pdu_context *pasync_ctx[BEISCSI_ULP_COUNT];
6733b39a
JK		 1071};
1072
99bc5d55
JSJ		 1073/* Logging related definitions */
1074#define BEISCSI_LOG_INIT 0x0001 /* Initialization events */
1075#define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */
1076#define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */
1077#define BEISCSI_LOG_EH 0x0008 /* Error Handler */
1078#define BEISCSI_LOG_IO 0x0010 /* IO Code Path */
1079#define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */
afb96058 1080#define BEISCSI_LOG_ISCSI 0x0040 /* SCSI/iSCSI Protocol related Logs */
99bc5d55 1081
53aefe25
JB		 1082#define __beiscsi_log(phba, level, fmt, arg...) \
1083 shost_printk(level, phba->shost, fmt, __LINE__, ##arg)
1084
99bc5d55
JSJ		 1085#define beiscsi_log(phba, level, mask, fmt, arg...) \
1086do { \
1087 uint32_t log_value = phba->attr_log_enable; \
1088 if (((mask) & log_value) || (level[1] <= '3')) \
53aefe25
JB		 1089 __beiscsi_log(phba, level, fmt, ##arg); \
1090} while (0);
99bc5d55 1091
6733b39a 1092#endif
Linux 6.x block layer and io_uring tree(s)