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be2iscsi: Fix to handle misconfigured optics events
[linux-2.6-block.git] / drivers / scsi / be2iscsi / be_main.h
CommitLineData
6733b39a 1/**
c4f39bda 2 * Copyright (C) 2005 - 2015 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
4627de93 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@avagotech.com)
6733b39a
JK		 11 *
12 * Contact Information:
4627de93 13 * linux-drivers@avagotech.com
6733b39a 14 *
c4f39bda 15 * Emulex
255fa9a3
JK		 16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a
JK		 18 */
19
20#ifndef _BEISCSI_MAIN_
21#define _BEISCSI_MAIN_
22
6733b39a
JK		 23#include <linux/kernel.h>
24#include <linux/pci.h>
82c57028 25#include <linux/if_ether.h>
6733b39a 26#include <linux/in.h>
99bc5d55
JSJ		 27#include <linux/ctype.h>
28#include <linux/module.h>
3567f36a 29#include <linux/aer.h>
6733b39a
JK		 30#include <scsi/scsi.h>
31#include <scsi/scsi_cmnd.h>
32#include <scsi/scsi_device.h>
33#include <scsi/scsi_host.h>
34#include <scsi/iscsi_proto.h>
35#include <scsi/libiscsi.h>
36#include <scsi/scsi_transport_iscsi.h>
37
6733b39a 38#define DRV_NAME "be2iscsi"
fb9c54dc 39#define BUILD_STR "10.6.0.1"
c4f39bda 40#define BE_NAME "Emulex OneConnect" \
2f635883 41 "Open-iSCSI Driver version" BUILD_STR
6733b39a
JK		 42#define DRV_DESC BE_NAME " " "Driver"
43
457ff3b7 44#define BE_VENDOR_ID 0x19A2
139a1b1e 45#define ELX_VENDOR_ID 0x10DF
f98c96b0 46/* DEVICE ID's for BE2 */
6733b39a
JK		 47#define BE_DEVICE_ID1 0x212
48#define OC_DEVICE_ID1 0x702
49#define OC_DEVICE_ID2 0x703
f98c96b0
JK		 50
51/* DEVICE ID's for BE3 */
52#define BE_DEVICE_ID2 0x222
bfead3b2 53#define OC_DEVICE_ID3 0x712
6733b39a 54
139a1b1e
JSJ		 55/* DEVICE ID for SKH */
56#define OC_SKH_ID1 0x722
57
7da50879
JK		 58#define BE2_IO_DEPTH 1024
59#define BE2_MAX_SESSIONS 256
6733b39a 60#define BE2_CMDS_PER_CXN 128
6733b39a
JK		 61#define BE2_TMFS 16
62#define BE2_NOPOUT_REQ 16
6733b39a
JK		 63#define BE2_SGE 32
64#define BE2_DEFPDU_HDR_SZ 64
65#define BE2_DEFPDU_DATA_SZ 8192
6733b39a 66
22abeef0
JSJ		 67#define MAX_CPUS 64
68#define BEISCSI_MAX_NUM_CPUS 7
22abeef0 69
22661e25 70#define BEISCSI_VER_STRLEN 32
22abeef0 71
aa359032 72#define BEISCSI_SGLIST_ELEMENTS 30
6733b39a 73
73af08e1
JK		 74#define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
75#define BEISCSI_MAX_SECTORS 1024 /* scsi_host->max_sectors */
15a90fe0 76#define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
6733b39a
JK		 77
78#define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
79#define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
80#define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
81#define BEISCSI_MAX_FRAGS_INIT 192
457ff3b7 82#define BE_NUM_MSIX_ENTRIES 1
e9b91193
JK		 83
84#define MPU_EP_CONTROL 0
85#define MPU_EP_SEMAPHORE 0xac
86#define BE2_SOFT_RESET 0x5c
87#define BE2_PCI_ONLINE0 0xb0
88#define BE2_PCI_ONLINE1 0xb4
89#define BE2_SET_RESET 0x80
90#define BE2_MPU_IRAM_ONLINE 0x00000080
6733b39a
JK		 91
92#define BE_SENSE_INFO_SIZE 258
93#define BE_ISCSI_PDU_HEADER_SIZE 64
94#define BE_MIN_MEM_SIZE 16384
bfead3b2 95#define MAX_CMD_SZ 65536
6733b39a
JK		 96#define IIOC_SCSI_DATA 0x05 /* Write Operation */
97
9aef4200 98#define INVALID_SESS_HANDLE 0xFFFFFFFF
6733b39a 99
9343be74
JK		 100/**
101 * Adapter States
102 **/
3567f36a
JK		 103#define BE_ADAPTER_LINK_UP 0x001
104#define BE_ADAPTER_LINK_DOWN 0x002
105#define BE_ADAPTER_PCI_ERR 0x004
cdaa4ded 106#define BE_ADAPTER_CHECK_BOOT 0x008
9343be74 107
3567f36a
JK		 108
109#define BEISCSI_CLEAN_UNLOAD 0x01
110#define BEISCSI_EEH_UNLOAD 0x02
3efde862
JSJ		 111
112#define BE_GET_BOOT_RETRIES 45
113#define BE_GET_BOOT_TO 20
6733b39a
JK		 114/**
115 * hardware needs the async PDU buffers to be posted in multiples of 8
116 * So have atleast 8 of them by default
117 */
118
8a86e833
JK		 119#define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num) \
120 (phwi->phwi_ctxt->pasync_ctx[ulp_num])
6733b39a
JK		 121
122/********* Memory BAR register ************/
457ff3b7 123#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
6733b39a
JK		 124/**
125 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
126 * Disable" may still globally block interrupts in addition to individual
127 * interrupt masks; a mechanism for the device driver to block all interrupts
128 * atomically without having to arbitrate for the PCI Interrupt Disable bit
129 * with the OS.
130 */
131#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
132
133/********* ISR0 Register offset **********/
457ff3b7 134#define CEV_ISR0_OFFSET 0xC18
6733b39a
JK		 135#define CEV_ISR_SIZE 4
136
137/**
138 * Macros for reading/writing a protection domain or CSR registers
139 * in BladeEngine.
140 */
141
142#define DB_TXULP0_OFFSET 0x40
143#define DB_RXULP0_OFFSET 0xA0
144/********* Event Q door bell *************/
145#define DB_EQ_OFFSET DB_CQ_OFFSET
e08b3c8b 146#define DB_EQ_RING_ID_LOW_MASK 0x1FF /* bits 0 - 8 */
6733b39a
JK		 147/* Clear the interrupt for this eq */
148#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
149/* Must be 1 */
150#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
e08b3c8b
JK		 151/* Higher Order EQ_ID bit */
152#define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
153#define DB_EQ_HIGH_SET_SHIFT 11
154#define DB_EQ_HIGH_FEILD_SHIFT 9
6733b39a
JK		 155/* Number of event entries processed */
156#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
157/* Rearm bit */
158#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
159
160/********* Compl Q door bell *************/
457ff3b7 161#define DB_CQ_OFFSET 0x120
e08b3c8b
JK		 162#define DB_CQ_RING_ID_LOW_MASK 0x3FF /* bits 0 - 9 */
163/* Higher Order CQ_ID bit */
164#define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
165#define DB_CQ_HIGH_SET_SHIFT 11
166#define DB_CQ_HIGH_FEILD_SHIFT 10
167
6733b39a 168/* Number of event entries processed */
457ff3b7 169#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
6733b39a 170/* Rearm bit */
457ff3b7 171#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
6733b39a
JK		 172
173#define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
8a86e833
JK		 174#define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
175 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
176#define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
177 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
6733b39a
JK		 178
179#define PAGES_REQUIRED(x) \
180 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
181
8fcfb210
JK		 182#define BEISCSI_MSI_NAME 20 /* size of msi_name string */
183
a129d92f 184#define MEM_DESCR_OFFSET 8
8a86e833
JK		 185#define BEISCSI_DEFQ_HDR 1
186#define BEISCSI_DEFQ_DATA 0
6733b39a
JK		 187enum be_mem_enum {
188 HWI_MEM_ADDN_CONTEXT,
6733b39a
JK		 189 HWI_MEM_WRB,
190 HWI_MEM_WRBH,
bfead3b2 191 HWI_MEM_SGLH,
6733b39a 192 HWI_MEM_SGE,
a129d92f
JK		 193 HWI_MEM_TEMPLATE_HDR_ULP0,
194 HWI_MEM_ASYNC_HEADER_BUF_ULP0, /* 6 */
8a86e833
JK		 195 HWI_MEM_ASYNC_DATA_BUF_ULP0,
196 HWI_MEM_ASYNC_HEADER_RING_ULP0,
197 HWI_MEM_ASYNC_DATA_RING_ULP0,
198 HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
a129d92f 199 HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
8a86e833 200 HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
a129d92f
JK		 201 HWI_MEM_TEMPLATE_HDR_ULP1,
202 HWI_MEM_ASYNC_HEADER_BUF_ULP1, /* 14 */
8a86e833
JK		 203 HWI_MEM_ASYNC_DATA_BUF_ULP1,
204 HWI_MEM_ASYNC_HEADER_RING_ULP1,
205 HWI_MEM_ASYNC_DATA_RING_ULP1,
206 HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
a129d92f 207 HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
8a86e833 208 HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
6733b39a 209 ISCSI_MEM_GLOBAL_HEADER,
bfead3b2 210 SE_MEM_MAX
6733b39a
JK		 211};
212
213struct be_bus_address32 {
214 unsigned int address_lo;
215 unsigned int address_hi;
216};
217
218struct be_bus_address64 {
219 unsigned long long address;
220};
221
222struct be_bus_address {
223 union {
224 struct be_bus_address32 a32;
225 struct be_bus_address64 a64;
226 } u;
227};
228
229struct mem_array {
230 struct be_bus_address bus_address; /* Bus address of location */
231 void *virtual_address; /* virtual address to the location */
232 unsigned int size; /* Size required by memory block */
233};
234
235struct be_mem_descriptor {
236 unsigned int index; /* Index of this memory parameter */
237 unsigned int category; /* type indicates cached/non-cached */
238 unsigned int num_elements; /* number of elements in this
239 * descriptor
240 */
241 unsigned int alignment_mask; /* Alignment mask for this block */
242 unsigned int size_in_bytes; /* Size required by memory block */
243 struct mem_array *mem_array;
244};
245
246struct sgl_handle {
247 unsigned int sgl_index;
bfead3b2
JK		 248 unsigned int type;
249 unsigned int cid;
250 struct iscsi_task *task;
6733b39a
JK		 251 struct iscsi_sge *pfrag;
252};
253
254struct hba_parameters {
255 unsigned int ios_per_ctrl;
256 unsigned int cxns_per_ctrl;
257 unsigned int asyncpdus_per_ctrl;
258 unsigned int icds_per_ctrl;
259 unsigned int num_sge_per_io;
260 unsigned int defpdu_hdr_sz;
261 unsigned int defpdu_data_sz;
262 unsigned int num_cq_entries;
263 unsigned int num_eq_entries;
264 unsigned int wrbs_per_cxn;
265 unsigned int crashmode;
266 unsigned int hba_num;
267
268 unsigned int mgmt_ws_sz;
269 unsigned int hwi_ws_sz;
270
271 unsigned int eto;
272 unsigned int ldto;
273
274 unsigned int dbg_flags;
275 unsigned int num_cxn;
276
277 unsigned int eq_timer;
278 /**
279 * These are calculated from other params. They're here
280 * for debug purposes
281 */
282 unsigned int num_mcc_pages;
283 unsigned int num_mcc_cq_pages;
284 unsigned int num_cq_pages;
285 unsigned int num_eq_pages;
286
287 unsigned int num_async_pdu_buf_pages;
288 unsigned int num_async_pdu_buf_sgl_pages;
289 unsigned int num_async_pdu_buf_cq_pages;
290
291 unsigned int num_async_pdu_hdr_pages;
292 unsigned int num_async_pdu_hdr_sgl_pages;
293 unsigned int num_async_pdu_hdr_cq_pages;
294
295 unsigned int num_sge;
296};
297
4183122d
JK		 298struct invalidate_command_table {
299 unsigned short icd;
300 unsigned short cid;
301} __packed;
302
4eea99d5
JK		 303#define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
304 (phwi_ctrlr->wrb_context[cri].ulp_num)
305struct hwi_wrb_context {
306 struct list_head wrb_handle_list;
307 struct list_head wrb_handle_drvr_list;
308 struct wrb_handle **pwrb_handle_base;
309 struct wrb_handle **pwrb_handle_basestd;
310 struct iscsi_wrb *plast_wrb;
311 unsigned short alloc_index;
312 unsigned short free_index;
313 unsigned short wrb_handles_available;
314 unsigned short cid;
315 uint8_t ulp_num; /* ULP to which CID binded */
316 uint16_t register_set;
317 uint16_t doorbell_format;
318 uint32_t doorbell_offset;
319};
320
0a3db7c0
JK		 321struct ulp_cid_info {
322 unsigned short *cid_array;
323 unsigned short avlbl_cids;
324 unsigned short cid_alloc;
325 unsigned short cid_free;
326};
327
4eea99d5 328#include "be.h"
2c9dfd36
JK		 329#define chip_be2(phba) (phba->generation == BE_GEN2)
330#define chip_be3_r(phba) (phba->generation == BE_GEN3)
331#define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
843ae752
JK		 332
333#define BEISCSI_ULP0 0
334#define BEISCSI_ULP1 1
335#define BEISCSI_ULP_COUNT 2
336#define BEISCSI_ULP0_LOADED 0x01
337#define BEISCSI_ULP1_LOADED 0x02
0a3db7c0
JK		 338
339#define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
340 (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
341#define BEISCSI_ULP0_AVLBL_CID(phba) \
342 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
343#define BEISCSI_ULP1_AVLBL_CID(phba) \
344 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
345
6733b39a
JK		 346struct beiscsi_hba {
347 struct hba_parameters params;
348 struct hwi_controller *phwi_ctrlr;
349 unsigned int mem_req[SE_MEM_MAX];
350 /* PCI BAR mapped addresses */
351 u8 __iomem *csr_va; /* CSR */
352 u8 __iomem *db_va; /* Door Bell */
353 u8 __iomem *pci_va; /* PCI Config */
354 struct be_bus_address csr_pa; /* CSR */
355 struct be_bus_address db_pa; /* CSR */
356 struct be_bus_address pci_pa; /* CSR */
357 /* PCI representation of our HBA */
358 struct pci_dev *pcidev;
6733b39a 359 unsigned short asic_revision;
bfead3b2
JK		 360 unsigned int num_cpus;
361 unsigned int nxt_cqid;
22abeef0
JSJ		 362 struct msix_entry msix_entries[MAX_CPUS];
363 char *msi_name[MAX_CPUS];
bfead3b2 364 bool msix_enabled;
6733b39a
JK		 365 struct be_mem_descriptor *init_mem;
366
367 unsigned short io_sgl_alloc_index;
368 unsigned short io_sgl_free_index;
369 unsigned short io_sgl_hndl_avbl;
370 struct sgl_handle **io_sgl_hndl_base;
bfead3b2 371 struct sgl_handle **sgl_hndl_array;
6733b39a
JK		 372
373 unsigned short eh_sgl_alloc_index;
374 unsigned short eh_sgl_free_index;
375 unsigned short eh_sgl_hndl_avbl;
376 struct sgl_handle **eh_sgl_hndl_base;
377 spinlock_t io_sgl_lock;
378 spinlock_t mgmt_sgl_lock;
379 spinlock_t isr_lock;
8f09a3b9 380 spinlock_t async_pdu_lock;
6733b39a 381 unsigned int age;
6733b39a 382 struct list_head hba_queue;
a7909b39
JK		 383#define BE_MAX_SESSION 2048
384#define BE_SET_CID_TO_CRI(cri_index, cid) \
385 (phba->cid_to_cri_map[cid] = cri_index)
386#define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
387 unsigned short cid_to_cri_map[BE_MAX_SESSION];
0a3db7c0 388 struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
6733b39a 389 struct iscsi_endpoint **ep_array;
a7909b39 390 struct beiscsi_conn **conn_table;
c7acc5b8 391 struct iscsi_boot_kset *boot_kset;
6733b39a 392 struct Scsi_Host *shost;
0e43895e
MC		 393 struct iscsi_iface *ipv4_iface;
394 struct iscsi_iface *ipv6_iface;
6733b39a
JK		 395 struct {
396 /**
397 * group together since they are used most frequently
398 * for cid to cri conversion
399 */
6733b39a 400 unsigned int phys_port;
68c26a3a
JK		 401 unsigned int eqid_count;
402 unsigned int cqid_count;
843ae752
JK		 403 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
404#define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
8a86e833 405 (phba->fw_config.iscsi_cid_count[ulp_num])
843ae752
JK		 406 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
407 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
408 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
409 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
410 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
6733b39a 411
bfead3b2 412 unsigned short iscsi_features;
843ae752
JK		 413 uint16_t dual_ulp_aware;
414 unsigned long ulp_supported;
6733b39a
JK		 415 } fw_config;
416
e175defe 417 unsigned int state;
53aefe25 418 u8 optic_state;
3efde862 419 int get_boot;
e175defe
JSJ		 420 bool fw_timeout;
421 bool ue_detected;
422 struct delayed_work beiscsi_hw_check_task;
423
6c83185a 424 bool mac_addr_set;
6733b39a 425 u8 mac_address[ETH_ALEN];
53aefe25 426 u8 port_name;
22661e25 427 char fw_ver_str[BEISCSI_VER_STRLEN];
6733b39a
JK		 428 char wq_name[20];
429 struct workqueue_struct *wq; /* The actuak work queue */
6733b39a 430 struct be_ctrl_info ctrl;
f98c96b0 431 unsigned int generation;
0e43895e 432 unsigned int interface_handle;
c7acc5b8 433 struct mgmt_session_info boot_sess;
4183122d
JK		 434 struct invalidate_command_table inv_tbl[128];
435
73af08e1 436 struct be_aic_obj aic_obj[MAX_CPUS];
99bc5d55 437 unsigned int attr_log_enable;
09a1093a
JSJ		 438 int (*iotask_fn)(struct iscsi_task *,
439 struct scatterlist *sg,
440 uint32_t num_sg, uint32_t xferlen,
441 uint32_t writedir);
6733b39a
JK		 442};
443
b8b9e1b8
JK		 444struct beiscsi_session {
445 struct pci_pool *bhs_pool;
446};
447
6733b39a
JK		 448/**
449 * struct beiscsi_conn - iscsi connection structure
450 */
451struct beiscsi_conn {
452 struct iscsi_conn *conn;
453 struct beiscsi_hba *phba;
454 u32 exp_statsn;
1e4be6ff 455 u32 doorbell_offset;
6733b39a
JK		 456 u32 beiscsi_conn_cid;
457 struct beiscsi_endpoint *ep;
458 unsigned short login_in_progress;
d2cecf0d 459 struct wrb_handle *plogin_wrb_handle;
6733b39a 460 struct sgl_handle *plogin_sgl_handle;
b8b9e1b8 461 struct beiscsi_session *beiscsi_sess;
bfead3b2 462 struct iscsi_task *task;
6733b39a
JK		 463};
464
465/* This structure is used by the chip */
466struct pdu_data_out {
467 u32 dw[12];
468};
469/**
470 * Pseudo amap definition in which each bit of the actual structure is defined
471 * as a byte: used to calculate offset/shift/mask of each field
472 */
473struct amap_pdu_data_out {
474 u8 opcode[6]; /* opcode */
475 u8 rsvd0[2]; /* should be 0 */
476 u8 rsvd1[7];
477 u8 final_bit; /* F bit */
478 u8 rsvd2[16];
479 u8 ahs_length[8]; /* no AHS */
480 u8 data_len_hi[8];
481 u8 data_len_lo[16]; /* DataSegmentLength */
482 u8 lun[64];
483 u8 itt[32]; /* ITT; initiator task tag */
484 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
485 u8 rsvd3[32];
486 u8 exp_stat_sn[32];
487 u8 rsvd4[32];
488 u8 data_sn[32];
489 u8 buffer_offset[32];
490 u8 rsvd5[32];
491};
492
493struct be_cmd_bhs {
12352183 494 struct iscsi_scsi_req iscsi_hdr;
6733b39a
JK		 495 unsigned char pad1[16];
496 struct pdu_data_out iscsi_data_pdu;
497 unsigned char pad2[BE_SENSE_INFO_SIZE -
498 sizeof(struct pdu_data_out)];
499};
500
501struct beiscsi_io_task {
502 struct wrb_handle *pwrb_handle;
503 struct sgl_handle *psgl_handle;
504 struct beiscsi_conn *conn;
505 struct scsi_cmnd *scsi_cmnd;
340c99e9 506 struct hwi_wrb_context *pwrb_context;
6733b39a
JK		 507 unsigned int cmd_sn;
508 unsigned int flags;
509 unsigned short cid;
510 unsigned short header_len;
bfead3b2 511 itt_t libiscsi_itt;
6733b39a
JK		 512 struct be_cmd_bhs *cmd_bhs;
513 struct be_bus_address bhs_pa;
514 unsigned short bhs_len;
d629c471
JSJ		 515 dma_addr_t mtask_addr;
516 uint32_t mtask_data_count;
09a1093a 517 uint8_t wrb_type;
6733b39a
JK		 518};
519
520struct be_nonio_bhs {
521 struct iscsi_hdr iscsi_hdr;
522 unsigned char pad1[16];
523 struct pdu_data_out iscsi_data_pdu;
524 unsigned char pad2[BE_SENSE_INFO_SIZE -
525 sizeof(struct pdu_data_out)];
526};
527
528struct be_status_bhs {
12352183 529 struct iscsi_scsi_req iscsi_hdr;
6733b39a
JK		 530 unsigned char pad1[16];
531 /**
532 * The plus 2 below is to hold the sense info length that gets
533 * DMA'ed by RxULP
534 */
535 unsigned char sense_info[BE_SENSE_INFO_SIZE];
536};
537
538struct iscsi_sge {
539 u32 dw[4];
540};
541
542/**
543 * Pseudo amap definition in which each bit of the actual structure is defined
544 * as a byte: used to calculate offset/shift/mask of each field
545 */
546struct amap_iscsi_sge {
547 u8 addr_hi[32];
548 u8 addr_lo[32];
549 u8 sge_offset[22]; /* DWORD 2 */
550 u8 rsvd0[9]; /* DWORD 2 */
551 u8 last_sge; /* DWORD 2 */
552 u8 len[17]; /* DWORD 3 */
553 u8 rsvd1[15]; /* DWORD 3 */
554};
555
556struct beiscsi_offload_params {
7331613e 557 u32 dw[6];
6733b39a
JK		 558};
559
560#define OFFLD_PARAMS_ERL 0x00000003
561#define OFFLD_PARAMS_DDE 0x00000004
562#define OFFLD_PARAMS_HDE 0x00000008
563#define OFFLD_PARAMS_IR2T 0x00000010
564#define OFFLD_PARAMS_IMD 0x00000020
acb9693c
JSJ		 565#define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040
566#define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080
567#define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
6733b39a
JK		 568
569/**
570 * Pseudo amap definition in which each bit of the actual structure is defined
571 * as a byte: used to calculate offset/shift/mask of each field
572 */
573struct amap_beiscsi_offload_params {
574 u8 max_burst_length[32];
575 u8 max_send_data_segment_length[32];
576 u8 first_burst_length[32];
577 u8 erl[2];
578 u8 dde[1];
579 u8 hde[1];
580 u8 ir2t[1];
581 u8 imd[1];
acb9693c
JSJ		 582 u8 data_seq_inorder[1];
583 u8 pdu_seq_inorder[1];
584 u8 max_r2t[16];
585 u8 pad[8];
6733b39a 586 u8 exp_statsn[32];
7331613e 587 u8 max_recv_data_segment_length[32];
6733b39a
JK		 588};
589
590/* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
591 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
592
593struct async_pdu_handle {
594 struct list_head link;
595 struct be_bus_address pa;
596 void *pbuffer;
597 unsigned int consumed;
598 unsigned char index;
599 unsigned char is_header;
600 unsigned short cri;
601 unsigned long buffer_len;
602};
603
604struct hwi_async_entry {
605 struct {
606 unsigned char hdr_received;
607 unsigned char hdr_len;
608 unsigned short bytes_received;
609 unsigned int bytes_needed;
610 struct list_head list;
611 } wait_queue;
612
613 struct list_head header_busy_list;
614 struct list_head data_busy_list;
615};
616
6733b39a
JK		 617struct hwi_async_pdu_context {
618 struct {
619 struct be_bus_address pa_base;
620 void *va_base;
621 void *ring_base;
622 struct async_pdu_handle *handle_base;
623
624 unsigned int host_write_ptr;
625 unsigned int ep_read_ptr;
626 unsigned int writables;
627
628 unsigned int free_entries;
629 unsigned int busy_entries;
6733b39a
JK		 630
631 struct list_head free_list;
632 } async_header;
633
634 struct {
635 struct be_bus_address pa_base;
636 void *va_base;
637 void *ring_base;
638 struct async_pdu_handle *handle_base;
639
640 unsigned int host_write_ptr;
641 unsigned int ep_read_ptr;
642 unsigned int writables;
643
644 unsigned int free_entries;
645 unsigned int busy_entries;
6733b39a 646 struct list_head free_list;
6733b39a
JK		 647 } async_data;
648
dc63aac6
JK		 649 unsigned int buffer_size;
650 unsigned int num_entries;
8a86e833
JK		 651#define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
652 unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
6733b39a
JK		 653 /**
654 * This is a varying size list! Do not add anything
655 * after this entry!!
656 */
a7909b39 657 struct hwi_async_entry *async_entry;
6733b39a
JK		 658};
659
660#define PDUCQE_CODE_MASK 0x0000003F
661#define PDUCQE_DPL_MASK 0xFFFF0000
662#define PDUCQE_INDEX_MASK 0x0000FFFF
663
664struct i_t_dpdu_cqe {
665 u32 dw[4];
666} __packed;
667
668/**
669 * Pseudo amap definition in which each bit of the actual structure is defined
670 * as a byte: used to calculate offset/shift/mask of each field
671 */
672struct amap_i_t_dpdu_cqe {
673 u8 db_addr_hi[32];
674 u8 db_addr_lo[32];
675 u8 code[6];
676 u8 cid[10];
677 u8 dpl[16];
678 u8 index[16];
679 u8 num_cons[10];
680 u8 rsvd0[4];
681 u8 final;
682 u8 valid;
683} __packed;
684
73133261
JSJ		 685struct amap_i_t_dpdu_cqe_v2 {
686 u8 db_addr_hi[32]; /* DWORD 0 */
687 u8 db_addr_lo[32]; /* DWORD 1 */
688 u8 code[6]; /* DWORD 2 */
689 u8 num_cons; /* DWORD 2*/
690 u8 rsvd0[8]; /* DWORD 2 */
691 u8 dpl[17]; /* DWORD 2 */
692 u8 index[16]; /* DWORD 3 */
693 u8 cid[13]; /* DWORD 3 */
694 u8 rsvd1; /* DWORD 3 */
695 u8 final; /* DWORD 3 */
696 u8 valid; /* DWORD 3 */
697} __packed;
698
6733b39a
JK		 699#define CQE_VALID_MASK 0x80000000
700#define CQE_CODE_MASK 0x0000003F
701#define CQE_CID_MASK 0x0000FFC0
702
703#define EQE_VALID_MASK 0x00000001
704#define EQE_MAJORCODE_MASK 0x0000000E
705#define EQE_RESID_MASK 0xFFFF0000
706
707struct be_eq_entry {
708 u32 dw[1];
709} __packed;
710
711/**
712 * Pseudo amap definition in which each bit of the actual structure is defined
713 * as a byte: used to calculate offset/shift/mask of each field
714 */
715struct amap_eq_entry {
716 u8 valid; /* DWORD 0 */
717 u8 major_code[3]; /* DWORD 0 */
718 u8 minor_code[12]; /* DWORD 0 */
719 u8 resource_id[16]; /* DWORD 0 */
720
721} __packed;
722
723struct cq_db {
724 u32 dw[1];
725} __packed;
726
727/**
728 * Pseudo amap definition in which each bit of the actual structure is defined
729 * as a byte: used to calculate offset/shift/mask of each field
730 */
731struct amap_cq_db {
732 u8 qid[10];
733 u8 event[1];
734 u8 rsvd0[5];
735 u8 num_popped[13];
736 u8 rearm[1];
737 u8 rsvd1[2];
738} __packed;
739
740void beiscsi_process_eq(struct beiscsi_hba *phba);
741
6733b39a
JK		 742struct iscsi_wrb {
743 u32 dw[16];
744} __packed;
745
746#define WRB_TYPE_MASK 0xF0000000
09a1093a
JSJ		 747#define SKH_WRB_TYPE_OFFSET 27
748#define BE_WRB_TYPE_OFFSET 28
749
750#define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
751 (pwrb->dw[0] |= (wrb_type << type_offset))
6733b39a
JK		 752
753/**
754 * Pseudo amap definition in which each bit of the actual structure is defined
755 * as a byte: used to calculate offset/shift/mask of each field
756 */
757struct amap_iscsi_wrb {
758 u8 lun[14]; /* DWORD 0 */
759 u8 lt; /* DWORD 0 */
760 u8 invld; /* DWORD 0 */
761 u8 wrb_idx[8]; /* DWORD 0 */
762 u8 dsp; /* DWORD 0 */
763 u8 dmsg; /* DWORD 0 */
764 u8 undr_run; /* DWORD 0 */
765 u8 over_run; /* DWORD 0 */
766 u8 type[4]; /* DWORD 0 */
767 u8 ptr2nextwrb[8]; /* DWORD 1 */
768 u8 r2t_exp_dtl[24]; /* DWORD 1 */
769 u8 sgl_icd_idx[12]; /* DWORD 2 */
770 u8 rsvd0[20]; /* DWORD 2 */
771 u8 exp_data_sn[32]; /* DWORD 3 */
772 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
773 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
774 u8 cmdsn_itt[32]; /* DWORD 6 */
775 u8 dif_ref_tag[32]; /* DWORD 7 */
776 u8 sge0_addr_hi[32]; /* DWORD 8 */
777 u8 sge0_addr_lo[32]; /* DWORD 9 */
778 u8 sge0_offset[22]; /* DWORD 10 */
779 u8 pbs; /* DWORD 10 */
780 u8 dif_mode[2]; /* DWORD 10 */
781 u8 rsvd1[6]; /* DWORD 10 */
782 u8 sge0_last; /* DWORD 10 */
783 u8 sge0_len[17]; /* DWORD 11 */
784 u8 dif_meta_tag[14]; /* DWORD 11 */
785 u8 sge0_in_ddr; /* DWORD 11 */
786 u8 sge1_addr_hi[32]; /* DWORD 12 */
787 u8 sge1_addr_lo[32]; /* DWORD 13 */
788 u8 sge1_r2t_offset[22]; /* DWORD 14 */
789 u8 rsvd2[9]; /* DWORD 14 */
790 u8 sge1_last; /* DWORD 14 */
791 u8 sge1_len[17]; /* DWORD 15 */
792 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
793 u8 rsvd3[2]; /* DWORD 15 */
794 u8 sge1_in_ddr; /* DWORD 15 */
795
796} __packed;
797
09a1093a
JSJ		 798struct amap_iscsi_wrb_v2 {
799 u8 r2t_exp_dtl[25]; /* DWORD 0 */
800 u8 rsvd0[2]; /* DWORD 0*/
801 u8 type[5]; /* DWORD 0 */
802 u8 ptr2nextwrb[8]; /* DWORD 1 */
803 u8 wrb_idx[8]; /* DWORD 1 */
804 u8 lun[16]; /* DWORD 1 */
805 u8 sgl_idx[16]; /* DWORD 2 */
806 u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
807 u8 exp_data_sn[32]; /* DWORD 3 */
808 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
809 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
810 u8 cq_id[16]; /* DWORD 6 */
811 u8 rsvd1[16]; /* DWORD 6 */
812 u8 cmdsn_itt[32]; /* DWORD 7 */
813 u8 sge0_addr_hi[32]; /* DWORD 8 */
814 u8 sge0_addr_lo[32]; /* DWORD 9 */
815 u8 sge0_offset[24]; /* DWORD 10 */
816 u8 rsvd2[7]; /* DWORD 10 */
817 u8 sge0_last; /* DWORD 10 */
818 u8 sge0_len[17]; /* DWORD 11 */
819 u8 rsvd3[7]; /* DWORD 11 */
820 u8 diff_enbl; /* DWORD 11 */
821 u8 u_run; /* DWORD 11 */
822 u8 o_run; /* DWORD 11 */
823 u8 invalid; /* DWORD 11 */
824 u8 dsp; /* DWORD 11 */
825 u8 dmsg; /* DWORD 11 */
826 u8 rsvd4; /* DWORD 11 */
827 u8 lt; /* DWORD 11 */
828 u8 sge1_addr_hi[32]; /* DWORD 12 */
829 u8 sge1_addr_lo[32]; /* DWORD 13 */
830 u8 sge1_r2t_offset[24]; /* DWORD 14 */
831 u8 rsvd5[7]; /* DWORD 14 */
832 u8 sge1_last; /* DWORD 14 */
833 u8 sge1_len[17]; /* DWORD 15 */
834 u8 rsvd6[15]; /* DWORD 15 */
835} __packed;
836
837
340c99e9
JSJ		 838struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
839 struct hwi_wrb_context **pcontext);
6733b39a
JK		 840void
841free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
842
756d29c8 843void beiscsi_process_all_cqs(struct work_struct *work);
4a4a11b9
JK		 844void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
845 struct iscsi_task *task);
756d29c8 846
e08b3c8b
JK		 847void hwi_ring_cq_db(struct beiscsi_hba *phba,
848 unsigned int id, unsigned int num_processed,
849 unsigned char rearm, unsigned char event);
b7ab35b1
JK		 850
851unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq);
852
7a158003
JSJ		 853static inline bool beiscsi_error(struct beiscsi_hba *phba)
854{
855 return phba->ue_detected || phba->fw_timeout;
856}
857
6733b39a
JK		 858struct pdu_nop_out {
859 u32 dw[12];
860};
861
862/**
863 * Pseudo amap definition in which each bit of the actual structure is defined
864 * as a byte: used to calculate offset/shift/mask of each field
865 */
866struct amap_pdu_nop_out {
867 u8 opcode[6]; /* opcode 0x00 */
868 u8 i_bit; /* I Bit */
869 u8 x_bit; /* reserved; should be 0 */
870 u8 fp_bit_filler1[7];
871 u8 f_bit; /* always 1 */
872 u8 reserved1[16];
873 u8 ahs_length[8]; /* no AHS */
874 u8 data_len_hi[8];
875 u8 data_len_lo[16]; /* DataSegmentLength */
876 u8 lun[64];
877 u8 itt[32]; /* initiator id for ping or 0xffffffff */
878 u8 ttt[32]; /* target id for ping or 0xffffffff */
879 u8 cmd_sn[32];
880 u8 exp_stat_sn[32];
881 u8 reserved5[128];
882};
883
884#define PDUBASE_OPCODE_MASK 0x0000003F
885#define PDUBASE_DATALENHI_MASK 0x0000FF00
886#define PDUBASE_DATALENLO_MASK 0xFFFF0000
887
888struct pdu_base {
889 u32 dw[16];
890} __packed;
891
892/**
893 * Pseudo amap definition in which each bit of the actual structure is defined
894 * as a byte: used to calculate offset/shift/mask of each field
895 */
896struct amap_pdu_base {
897 u8 opcode[6];
898 u8 i_bit; /* immediate bit */
899 u8 x_bit; /* reserved, always 0 */
900 u8 reserved1[24]; /* opcode-specific fields */
901 u8 ahs_length[8]; /* length units is 4 byte words */
902 u8 data_len_hi[8];
903 u8 data_len_lo[16]; /* DatasegmentLength */
904 u8 lun[64]; /* lun or opcode-specific fields */
905 u8 itt[32]; /* initiator task tag */
906 u8 reserved4[224];
907};
908
909struct iscsi_target_context_update_wrb {
910 u32 dw[16];
911} __packed;
912
913/**
914 * Pseudo amap definition in which each bit of the actual structure is defined
915 * as a byte: used to calculate offset/shift/mask of each field
916 */
acb9693c 917#define BE_TGT_CTX_UPDT_CMD 0x07
6733b39a
JK		 918struct amap_iscsi_target_context_update_wrb {
919 u8 lun[14]; /* DWORD 0 */
920 u8 lt; /* DWORD 0 */
921 u8 invld; /* DWORD 0 */
922 u8 wrb_idx[8]; /* DWORD 0 */
923 u8 dsp; /* DWORD 0 */
924 u8 dmsg; /* DWORD 0 */
925 u8 undr_run; /* DWORD 0 */
926 u8 over_run; /* DWORD 0 */
927 u8 type[4]; /* DWORD 0 */
928 u8 ptr2nextwrb[8]; /* DWORD 1 */
929 u8 max_burst_length[19]; /* DWORD 1 */
930 u8 rsvd0[5]; /* DWORD 1 */
931 u8 rsvd1[15]; /* DWORD 2 */
932 u8 max_send_data_segment_length[17]; /* DWORD 2 */
933 u8 first_burst_length[14]; /* DWORD 3 */
934 u8 rsvd2[2]; /* DWORD 3 */
935 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
936 u8 rsvd3[5]; /* DWORD 3 */
937 u8 session_state[3]; /* DWORD 3 */
938 u8 rsvd4[16]; /* DWORD 4 */
939 u8 tx_jumbo; /* DWORD 4 */
940 u8 hde; /* DWORD 4 */
941 u8 dde; /* DWORD 4 */
942 u8 erl[2]; /* DWORD 4 */
943 u8 domain_id[5]; /* DWORD 4 */
944 u8 mode; /* DWORD 4 */
945 u8 imd; /* DWORD 4 */
946 u8 ir2t; /* DWORD 4 */
947 u8 notpredblq[2]; /* DWORD 4 */
948 u8 compltonack; /* DWORD 4 */
949 u8 stat_sn[32]; /* DWORD 5 */
950 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
951 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
952 u8 pad_addr_hi[32]; /* DWORD 8 */
953 u8 pad_addr_lo[32]; /* DWORD 9 */
954 u8 rsvd5[32]; /* DWORD 10 */
955 u8 rsvd6[32]; /* DWORD 11 */
956 u8 rsvd7[32]; /* DWORD 12 */
957 u8 rsvd8[32]; /* DWORD 13 */
958 u8 rsvd9[32]; /* DWORD 14 */
959 u8 rsvd10[32]; /* DWORD 15 */
960
961} __packed;
962
acb9693c
JSJ		 963#define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024)
964#define BEISCSI_MAX_CXNS 1
965struct amap_iscsi_target_context_update_wrb_v2 {
966 u8 max_burst_length[24]; /* DWORD 0 */
967 u8 rsvd0[3]; /* DWORD 0 */
968 u8 type[5]; /* DWORD 0 */
969 u8 ptr2nextwrb[8]; /* DWORD 1 */
970 u8 wrb_idx[8]; /* DWORD 1 */
971 u8 rsvd1[16]; /* DWORD 1 */
972 u8 max_send_data_segment_length[24]; /* DWORD 2 */
973 u8 rsvd2[8]; /* DWORD 2 */
974 u8 first_burst_length[24]; /* DWORD 3 */
975 u8 rsvd3[8]; /* DOWRD 3 */
976 u8 max_r2t[16]; /* DWORD 4 */
7331613e 977 u8 rsvd4; /* DWORD 4 */
acb9693c
JSJ		 978 u8 hde; /* DWORD 4 */
979 u8 dde; /* DWORD 4 */
980 u8 erl[2]; /* DWORD 4 */
7331613e 981 u8 rsvd5[6]; /* DWORD 4 */
acb9693c
JSJ		 982 u8 imd; /* DWORD 4 */
983 u8 ir2t; /* DWORD 4 */
7331613e 984 u8 rsvd6[3]; /* DWORD 4 */
acb9693c 985 u8 stat_sn[32]; /* DWORD 5 */
7331613e
JK		 986 u8 rsvd7[32]; /* DWORD 6 */
987 u8 rsvd8[32]; /* DWORD 7 */
acb9693c 988 u8 max_recv_dataseg_len[24]; /* DWORD 8 */
7331613e
JK		 989 u8 rsvd9[8]; /* DWORD 8 */
990 u8 rsvd10[32]; /* DWORD 9 */
991 u8 rsvd11[32]; /* DWORD 10 */
acb9693c 992 u8 max_cxns[16]; /* DWORD 11 */
7331613e 993 u8 rsvd12[11]; /* DWORD 11*/
acb9693c 994 u8 invld; /* DWORD 11 */
7331613e 995 u8 rsvd13;/* DWORD 11*/
acb9693c
JSJ		 996 u8 dmsg; /* DWORD 11 */
997 u8 data_seq_inorder; /* DWORD 11 */
998 u8 pdu_seq_inorder; /* DWORD 11 */
7331613e
JK		 999 u8 rsvd14[32]; /*DWORD 12 */
1000 u8 rsvd15[32]; /* DWORD 13 */
1001 u8 rsvd16[32]; /* DWORD 14 */
1002 u8 rsvd17[32]; /* DWORD 15 */
acb9693c
JSJ		 1003} __packed;
1004
1005
6733b39a
JK		 1006struct be_ring {
1007 u32 pages; /* queue size in pages */
1008 u32 id; /* queue id assigned by beklib */
1009 u32 num; /* number of elements in queue */
1010 u32 cidx; /* consumer index */
1011 u32 pidx; /* producer index -- not used by most rings */
1012 u32 item_size; /* size in bytes of one object */
8a86e833
JK		 1013 u8 ulp_num; /* ULP to which CID binded */
1014 u16 register_set;
1015 u16 doorbell_format;
1016 u32 doorbell_offset;
6733b39a
JK		 1017
1018 void *va; /* The virtual address of the ring. This
1019 * should be last to allow 32 & 64 bit debugger
1020 * extensions to work.
1021 */
1022};
1023
6733b39a
JK		 1024struct hwi_controller {
1025 struct list_head io_sgl_list;
1026 struct list_head eh_sgl_list;
1027 struct sgl_handle *psgl_handle_base;
1028 unsigned int wrb_mem_index;
1029
a7909b39 1030 struct hwi_wrb_context *wrb_context;
6733b39a 1031 struct mcc_wrb *pmcc_wrb_base;
8a86e833
JK		 1032 struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
1033 struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
6733b39a 1034 struct hwi_context_memory *phwi_ctxt;
6733b39a
JK		 1035};
1036
1037enum hwh_type_enum {
1038 HWH_TYPE_IO = 1,
1039 HWH_TYPE_LOGOUT = 2,
1040 HWH_TYPE_TMF = 3,
1041 HWH_TYPE_NOP = 4,
1042 HWH_TYPE_IO_RD = 5,
1043 HWH_TYPE_LOGIN = 11,
1044 HWH_TYPE_INVALID = 0xFFFFFFFF
1045};
1046
1047struct wrb_handle {
1048 enum hwh_type_enum type;
1049 unsigned short wrb_index;
6733b39a
JK		 1050
1051 struct iscsi_task *pio_handle;
1052 struct iscsi_wrb *pwrb;
1053};
1054
1055struct hwi_context_memory {
bfead3b2
JK		 1056 /* Adaptive interrupt coalescing (AIC) info */
1057 u16 min_eqd; /* in usecs */
1058 u16 max_eqd; /* in usecs */
1059 u16 cur_eqd; /* in usecs */
1060 struct be_eq_obj be_eq[MAX_CPUS];
22abeef0 1061 struct be_queue_info be_cq[MAX_CPUS - 1];
6733b39a 1062
a7909b39 1063 struct be_queue_info *be_wrbq;
8a86e833
JK		 1064 struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1065 struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1066 struct hwi_async_pdu_context *pasync_ctx[BEISCSI_ULP_COUNT];
6733b39a
JK		 1067};
1068
99bc5d55
JSJ		 1069/* Logging related definitions */
1070#define BEISCSI_LOG_INIT 0x0001 /* Initialization events */
1071#define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */
1072#define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */
1073#define BEISCSI_LOG_EH 0x0008 /* Error Handler */
1074#define BEISCSI_LOG_IO 0x0010 /* IO Code Path */
1075#define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */
afb96058 1076#define BEISCSI_LOG_ISCSI 0x0040 /* SCSI/iSCSI Protocol related Logs */
99bc5d55 1077
53aefe25
JB		 1078#define __beiscsi_log(phba, level, fmt, arg...) \
1079 shost_printk(level, phba->shost, fmt, __LINE__, ##arg)
1080
99bc5d55
JSJ		 1081#define beiscsi_log(phba, level, mask, fmt, arg...) \
1082do { \
1083 uint32_t log_value = phba->attr_log_enable; \
1084 if (((mask) & log_value) || (level[1] <= '3')) \
53aefe25
JB		 1085 __beiscsi_log(phba, level, fmt, ##arg); \
1086} while (0);
99bc5d55 1087
6733b39a 1088#endif
Linux 6.x block layer and io_uring tree(s)