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scsi: be2iscsi: Fix to make boot discovery non-blocking
[linux-2.6-block.git] / drivers / scsi / be2iscsi / be_main.h
CommitLineData
6733b39a 1/**
c4f39bda 2 * Copyright (C) 2005 - 2015 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
4627de93 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@avagotech.com)
6733b39a
JK		 11 *
12 * Contact Information:
4627de93 13 * linux-drivers@avagotech.com
6733b39a 14 *
c4f39bda 15 * Emulex
255fa9a3
JK		 16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a
JK		 18 */
19
20#ifndef _BEISCSI_MAIN_
21#define _BEISCSI_MAIN_
22
6733b39a
JK		 23#include <linux/kernel.h>
24#include <linux/pci.h>
82c57028 25#include <linux/if_ether.h>
6733b39a 26#include <linux/in.h>
99bc5d55
JSJ		 27#include <linux/ctype.h>
28#include <linux/module.h>
3567f36a 29#include <linux/aer.h>
6733b39a
JK		 30#include <scsi/scsi.h>
31#include <scsi/scsi_cmnd.h>
32#include <scsi/scsi_device.h>
33#include <scsi/scsi_host.h>
34#include <scsi/iscsi_proto.h>
35#include <scsi/libiscsi.h>
36#include <scsi/scsi_transport_iscsi.h>
37
6733b39a 38#define DRV_NAME "be2iscsi"
1db1194f 39#define BUILD_STR "11.0.0.0"
c4f39bda 40#define BE_NAME "Emulex OneConnect" \
2f635883 41 "Open-iSCSI Driver version" BUILD_STR
6733b39a
JK		 42#define DRV_DESC BE_NAME " " "Driver"
43
457ff3b7 44#define BE_VENDOR_ID 0x19A2
139a1b1e 45#define ELX_VENDOR_ID 0x10DF
f98c96b0 46/* DEVICE ID's for BE2 */
6733b39a
JK		 47#define BE_DEVICE_ID1 0x212
48#define OC_DEVICE_ID1 0x702
49#define OC_DEVICE_ID2 0x703
f98c96b0
JK		 50
51/* DEVICE ID's for BE3 */
52#define BE_DEVICE_ID2 0x222
bfead3b2 53#define OC_DEVICE_ID3 0x712
6733b39a 54
139a1b1e
JSJ		 55/* DEVICE ID for SKH */
56#define OC_SKH_ID1 0x722
57
7da50879
JK		 58#define BE2_IO_DEPTH 1024
59#define BE2_MAX_SESSIONS 256
6733b39a 60#define BE2_CMDS_PER_CXN 128
6733b39a
JK		 61#define BE2_TMFS 16
62#define BE2_NOPOUT_REQ 16
6733b39a
JK		 63#define BE2_SGE 32
64#define BE2_DEFPDU_HDR_SZ 64
65#define BE2_DEFPDU_DATA_SZ 8192
1094cf68 66#define BE2_MAX_NUM_CQ_PROC 512
6733b39a 67
22abeef0
JSJ		 68#define MAX_CPUS 64
69#define BEISCSI_MAX_NUM_CPUS 7
22abeef0 70
22661e25 71#define BEISCSI_VER_STRLEN 32
22abeef0 72
aa359032 73#define BEISCSI_SGLIST_ELEMENTS 30
6733b39a 74
73af08e1
JK		 75#define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
76#define BEISCSI_MAX_SECTORS 1024 /* scsi_host->max_sectors */
15a90fe0 77#define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
6733b39a
JK		 78
79#define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
80#define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
81#define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
82#define BEISCSI_MAX_FRAGS_INIT 192
457ff3b7 83#define BE_NUM_MSIX_ENTRIES 1
e9b91193
JK		 84
85#define MPU_EP_CONTROL 0
86#define MPU_EP_SEMAPHORE 0xac
87#define BE2_SOFT_RESET 0x5c
88#define BE2_PCI_ONLINE0 0xb0
89#define BE2_PCI_ONLINE1 0xb4
90#define BE2_SET_RESET 0x80
91#define BE2_MPU_IRAM_ONLINE 0x00000080
6733b39a
JK		 92
93#define BE_SENSE_INFO_SIZE 258
94#define BE_ISCSI_PDU_HEADER_SIZE 64
95#define BE_MIN_MEM_SIZE 16384
bfead3b2 96#define MAX_CMD_SZ 65536
6733b39a
JK		 97#define IIOC_SCSI_DATA 0x05 /* Write Operation */
98
6733b39a
JK		 99/**
100 * hardware needs the async PDU buffers to be posted in multiples of 8
101 * So have atleast 8 of them by default
102 */
103
8a86e833
JK		 104#define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num) \
105 (phwi->phwi_ctxt->pasync_ctx[ulp_num])
6733b39a
JK		 106
107/********* Memory BAR register ************/
457ff3b7 108#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
6733b39a
JK		 109/**
110 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
111 * Disable" may still globally block interrupts in addition to individual
112 * interrupt masks; a mechanism for the device driver to block all interrupts
113 * atomically without having to arbitrate for the PCI Interrupt Disable bit
114 * with the OS.
115 */
116#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
117
118/********* ISR0 Register offset **********/
457ff3b7 119#define CEV_ISR0_OFFSET 0xC18
6733b39a
JK		 120#define CEV_ISR_SIZE 4
121
122/**
123 * Macros for reading/writing a protection domain or CSR registers
124 * in BladeEngine.
125 */
126
127#define DB_TXULP0_OFFSET 0x40
128#define DB_RXULP0_OFFSET 0xA0
129/********* Event Q door bell *************/
130#define DB_EQ_OFFSET DB_CQ_OFFSET
e08b3c8b 131#define DB_EQ_RING_ID_LOW_MASK 0x1FF /* bits 0 - 8 */
6733b39a
JK		 132/* Clear the interrupt for this eq */
133#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
134/* Must be 1 */
135#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
e08b3c8b
JK		 136/* Higher Order EQ_ID bit */
137#define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
138#define DB_EQ_HIGH_SET_SHIFT 11
139#define DB_EQ_HIGH_FEILD_SHIFT 9
6733b39a
JK		 140/* Number of event entries processed */
141#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
142/* Rearm bit */
143#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
144
145/********* Compl Q door bell *************/
457ff3b7 146#define DB_CQ_OFFSET 0x120
e08b3c8b
JK		 147#define DB_CQ_RING_ID_LOW_MASK 0x3FF /* bits 0 - 9 */
148/* Higher Order CQ_ID bit */
149#define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
150#define DB_CQ_HIGH_SET_SHIFT 11
151#define DB_CQ_HIGH_FEILD_SHIFT 10
152
6733b39a 153/* Number of event entries processed */
457ff3b7 154#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
6733b39a 155/* Rearm bit */
457ff3b7 156#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
6733b39a
JK		 157
158#define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
8a86e833
JK		 159#define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
160 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
161#define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
162 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
6733b39a
JK		 163
164#define PAGES_REQUIRED(x) \
165 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
166
8fcfb210
JK		 167#define BEISCSI_MSI_NAME 20 /* size of msi_name string */
168
a129d92f 169#define MEM_DESCR_OFFSET 8
8a86e833
JK		 170#define BEISCSI_DEFQ_HDR 1
171#define BEISCSI_DEFQ_DATA 0
6733b39a
JK		 172enum be_mem_enum {
173 HWI_MEM_ADDN_CONTEXT,
6733b39a
JK		 174 HWI_MEM_WRB,
175 HWI_MEM_WRBH,
bfead3b2 176 HWI_MEM_SGLH,
6733b39a 177 HWI_MEM_SGE,
a129d92f
JK		 178 HWI_MEM_TEMPLATE_HDR_ULP0,
179 HWI_MEM_ASYNC_HEADER_BUF_ULP0, /* 6 */
8a86e833
JK		 180 HWI_MEM_ASYNC_DATA_BUF_ULP0,
181 HWI_MEM_ASYNC_HEADER_RING_ULP0,
182 HWI_MEM_ASYNC_DATA_RING_ULP0,
183 HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
a129d92f 184 HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
8a86e833 185 HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
a129d92f
JK		 186 HWI_MEM_TEMPLATE_HDR_ULP1,
187 HWI_MEM_ASYNC_HEADER_BUF_ULP1, /* 14 */
8a86e833
JK		 188 HWI_MEM_ASYNC_DATA_BUF_ULP1,
189 HWI_MEM_ASYNC_HEADER_RING_ULP1,
190 HWI_MEM_ASYNC_DATA_RING_ULP1,
191 HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
a129d92f 192 HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
8a86e833 193 HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
6733b39a 194 ISCSI_MEM_GLOBAL_HEADER,
bfead3b2 195 SE_MEM_MAX
6733b39a
JK		 196};
197
198struct be_bus_address32 {
199 unsigned int address_lo;
200 unsigned int address_hi;
201};
202
203struct be_bus_address64 {
204 unsigned long long address;
205};
206
207struct be_bus_address {
208 union {
209 struct be_bus_address32 a32;
210 struct be_bus_address64 a64;
211 } u;
212};
213
214struct mem_array {
215 struct be_bus_address bus_address; /* Bus address of location */
216 void *virtual_address; /* virtual address to the location */
217 unsigned int size; /* Size required by memory block */
218};
219
220struct be_mem_descriptor {
221 unsigned int index; /* Index of this memory parameter */
222 unsigned int category; /* type indicates cached/non-cached */
223 unsigned int num_elements; /* number of elements in this
224 * descriptor
225 */
226 unsigned int alignment_mask; /* Alignment mask for this block */
227 unsigned int size_in_bytes; /* Size required by memory block */
228 struct mem_array *mem_array;
229};
230
231struct sgl_handle {
232 unsigned int sgl_index;
bfead3b2
JK		 233 unsigned int type;
234 unsigned int cid;
235 struct iscsi_task *task;
6733b39a
JK		 236 struct iscsi_sge *pfrag;
237};
238
239struct hba_parameters {
240 unsigned int ios_per_ctrl;
241 unsigned int cxns_per_ctrl;
242 unsigned int asyncpdus_per_ctrl;
243 unsigned int icds_per_ctrl;
244 unsigned int num_sge_per_io;
245 unsigned int defpdu_hdr_sz;
246 unsigned int defpdu_data_sz;
247 unsigned int num_cq_entries;
248 unsigned int num_eq_entries;
249 unsigned int wrbs_per_cxn;
250 unsigned int crashmode;
251 unsigned int hba_num;
252
253 unsigned int mgmt_ws_sz;
254 unsigned int hwi_ws_sz;
255
256 unsigned int eto;
257 unsigned int ldto;
258
259 unsigned int dbg_flags;
260 unsigned int num_cxn;
261
262 unsigned int eq_timer;
263 /**
264 * These are calculated from other params. They're here
265 * for debug purposes
266 */
267 unsigned int num_mcc_pages;
268 unsigned int num_mcc_cq_pages;
269 unsigned int num_cq_pages;
270 unsigned int num_eq_pages;
271
272 unsigned int num_async_pdu_buf_pages;
273 unsigned int num_async_pdu_buf_sgl_pages;
274 unsigned int num_async_pdu_buf_cq_pages;
275
276 unsigned int num_async_pdu_hdr_pages;
277 unsigned int num_async_pdu_hdr_sgl_pages;
278 unsigned int num_async_pdu_hdr_cq_pages;
279
280 unsigned int num_sge;
281};
282
4183122d
JK		 283struct invalidate_command_table {
284 unsigned short icd;
285 unsigned short cid;
286} __packed;
287
4eea99d5
JK		 288#define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
289 (phwi_ctrlr->wrb_context[cri].ulp_num)
290struct hwi_wrb_context {
f64d92e6 291 spinlock_t wrb_lock;
4eea99d5
JK		 292 struct list_head wrb_handle_list;
293 struct list_head wrb_handle_drvr_list;
294 struct wrb_handle **pwrb_handle_base;
295 struct wrb_handle **pwrb_handle_basestd;
296 struct iscsi_wrb *plast_wrb;
297 unsigned short alloc_index;
298 unsigned short free_index;
299 unsigned short wrb_handles_available;
300 unsigned short cid;
301 uint8_t ulp_num; /* ULP to which CID binded */
302 uint16_t register_set;
303 uint16_t doorbell_format;
304 uint32_t doorbell_offset;
305};
306
0a3db7c0
JK		 307struct ulp_cid_info {
308 unsigned short *cid_array;
309 unsigned short avlbl_cids;
310 unsigned short cid_alloc;
311 unsigned short cid_free;
312};
313
4eea99d5 314#include "be.h"
2c9dfd36
JK		 315#define chip_be2(phba) (phba->generation == BE_GEN2)
316#define chip_be3_r(phba) (phba->generation == BE_GEN3)
317#define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
843ae752
JK		 318
319#define BEISCSI_ULP0 0
320#define BEISCSI_ULP1 1
321#define BEISCSI_ULP_COUNT 2
322#define BEISCSI_ULP0_LOADED 0x01
323#define BEISCSI_ULP1_LOADED 0x02
0a3db7c0
JK		 324
325#define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
326 (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
327#define BEISCSI_ULP0_AVLBL_CID(phba) \
328 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
329#define BEISCSI_ULP1_AVLBL_CID(phba) \
330 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
331
6733b39a
JK		 332struct beiscsi_hba {
333 struct hba_parameters params;
334 struct hwi_controller *phwi_ctrlr;
335 unsigned int mem_req[SE_MEM_MAX];
336 /* PCI BAR mapped addresses */
337 u8 __iomem *csr_va; /* CSR */
338 u8 __iomem *db_va; /* Door Bell */
339 u8 __iomem *pci_va; /* PCI Config */
340 struct be_bus_address csr_pa; /* CSR */
341 struct be_bus_address db_pa; /* CSR */
342 struct be_bus_address pci_pa; /* CSR */
343 /* PCI representation of our HBA */
344 struct pci_dev *pcidev;
6733b39a 345 unsigned short asic_revision;
bfead3b2
JK		 346 unsigned int num_cpus;
347 unsigned int nxt_cqid;
22abeef0
JSJ		 348 struct msix_entry msix_entries[MAX_CPUS];
349 char *msi_name[MAX_CPUS];
bfead3b2 350 bool msix_enabled;
6733b39a
JK		 351 struct be_mem_descriptor *init_mem;
352
353 unsigned short io_sgl_alloc_index;
354 unsigned short io_sgl_free_index;
355 unsigned short io_sgl_hndl_avbl;
356 struct sgl_handle **io_sgl_hndl_base;
bfead3b2 357 struct sgl_handle **sgl_hndl_array;
6733b39a
JK		 358
359 unsigned short eh_sgl_alloc_index;
360 unsigned short eh_sgl_free_index;
361 unsigned short eh_sgl_hndl_avbl;
362 struct sgl_handle **eh_sgl_hndl_base;
363 spinlock_t io_sgl_lock;
364 spinlock_t mgmt_sgl_lock;
8f09a3b9 365 spinlock_t async_pdu_lock;
6733b39a 366 unsigned int age;
6733b39a 367 struct list_head hba_queue;
a7909b39
JK		 368#define BE_MAX_SESSION 2048
369#define BE_SET_CID_TO_CRI(cri_index, cid) \
370 (phba->cid_to_cri_map[cid] = cri_index)
371#define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
372 unsigned short cid_to_cri_map[BE_MAX_SESSION];
0a3db7c0 373 struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
6733b39a 374 struct iscsi_endpoint **ep_array;
a7909b39 375 struct beiscsi_conn **conn_table;
6733b39a 376 struct Scsi_Host *shost;
0e43895e
MC		 377 struct iscsi_iface *ipv4_iface;
378 struct iscsi_iface *ipv6_iface;
6733b39a
JK		 379 struct {
380 /**
381 * group together since they are used most frequently
382 * for cid to cri conversion
383 */
4570f161 384#define BEISCSI_PHYS_PORT_MAX 4
6733b39a 385 unsigned int phys_port;
4570f161 386 /* valid values of phys_port id are 0, 1, 2, 3 */
68c26a3a
JK		 387 unsigned int eqid_count;
388 unsigned int cqid_count;
843ae752
JK		 389 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
390#define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
8a86e833 391 (phba->fw_config.iscsi_cid_count[ulp_num])
843ae752
JK		 392 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
393 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
394 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
395 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
396 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
6733b39a 397
bfead3b2 398 unsigned short iscsi_features;
843ae752
JK		 399 uint16_t dual_ulp_aware;
400 unsigned long ulp_supported;
6733b39a
JK		 401 } fw_config;
402
9122e991
JB		 403 unsigned long state;
404#define BEISCSI_HBA_RUNNING 0
405#define BEISCSI_HBA_LINK_UP 1
406#define BEISCSI_HBA_BOOT_FOUND 2
50a4b824
JB		 407#define BEISCSI_HBA_BOOT_WORK 3
408#define BEISCSI_HBA_PCI_ERR 4
409#define BEISCSI_HBA_FW_TIMEOUT 5
410#define BEISCSI_HBA_IN_UE 6
9122e991
JB		 411/* error bits */
412#define BEISCSI_HBA_IN_ERR ((1 << BEISCSI_HBA_PCI_ERR) | \
413 (1 << BEISCSI_HBA_FW_TIMEOUT) | \
414 (1 << BEISCSI_HBA_IN_UE))
415
53aefe25 416 u8 optic_state;
e175defe
JSJ		 417 struct delayed_work beiscsi_hw_check_task;
418
6c83185a 419 bool mac_addr_set;
6733b39a 420 u8 mac_address[ETH_ALEN];
53aefe25 421 u8 port_name;
048084c2 422 u8 port_speed;
22661e25 423 char fw_ver_str[BEISCSI_VER_STRLEN];
6733b39a
JK		 424 char wq_name[20];
425 struct workqueue_struct *wq; /* The actuak work queue */
6733b39a 426 struct be_ctrl_info ctrl;
f98c96b0 427 unsigned int generation;
0e43895e 428 unsigned int interface_handle;
4183122d
JK		 429 struct invalidate_command_table inv_tbl[128];
430
73af08e1 431 struct be_aic_obj aic_obj[MAX_CPUS];
99bc5d55 432 unsigned int attr_log_enable;
09a1093a
JSJ		 433 int (*iotask_fn)(struct iscsi_task *,
434 struct scatterlist *sg,
435 uint32_t num_sg, uint32_t xferlen,
436 uint32_t writedir);
50a4b824
JB		 437 struct boot_struct {
438 int retry;
439 unsigned int tag;
440 unsigned int s_handle;
441 struct be_dma_mem nonemb_cmd;
442 enum {
443 BEISCSI_BOOT_REOPEN_SESS = 1,
444 BEISCSI_BOOT_GET_SHANDLE,
445 BEISCSI_BOOT_GET_SINFO,
446 BEISCSI_BOOT_LOGOUT_SESS,
447 BEISCSI_BOOT_CREATE_KSET,
448 } action;
449 struct mgmt_session_info boot_sess;
450 struct iscsi_boot_kset *boot_kset;
451 } boot_struct;
452 struct work_struct boot_work;
6733b39a
JK		 453};
454
9122e991
JB		 455#define beiscsi_hba_in_error(phba) ((phba)->state & BEISCSI_HBA_IN_ERR)
456
b8b9e1b8
JK		 457struct beiscsi_session {
458 struct pci_pool *bhs_pool;
459};
460
6733b39a
JK		 461/**
462 * struct beiscsi_conn - iscsi connection structure
463 */
464struct beiscsi_conn {
465 struct iscsi_conn *conn;
466 struct beiscsi_hba *phba;
467 u32 exp_statsn;
1e4be6ff 468 u32 doorbell_offset;
6733b39a
JK		 469 u32 beiscsi_conn_cid;
470 struct beiscsi_endpoint *ep;
471 unsigned short login_in_progress;
d2cecf0d 472 struct wrb_handle *plogin_wrb_handle;
6733b39a 473 struct sgl_handle *plogin_sgl_handle;
b8b9e1b8 474 struct beiscsi_session *beiscsi_sess;
bfead3b2 475 struct iscsi_task *task;
6733b39a
JK		 476};
477
478/* This structure is used by the chip */
479struct pdu_data_out {
480 u32 dw[12];
481};
482/**
483 * Pseudo amap definition in which each bit of the actual structure is defined
484 * as a byte: used to calculate offset/shift/mask of each field
485 */
486struct amap_pdu_data_out {
487 u8 opcode[6]; /* opcode */
488 u8 rsvd0[2]; /* should be 0 */
489 u8 rsvd1[7];
490 u8 final_bit; /* F bit */
491 u8 rsvd2[16];
492 u8 ahs_length[8]; /* no AHS */
493 u8 data_len_hi[8];
494 u8 data_len_lo[16]; /* DataSegmentLength */
495 u8 lun[64];
496 u8 itt[32]; /* ITT; initiator task tag */
497 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
498 u8 rsvd3[32];
499 u8 exp_stat_sn[32];
500 u8 rsvd4[32];
501 u8 data_sn[32];
502 u8 buffer_offset[32];
503 u8 rsvd5[32];
504};
505
506struct be_cmd_bhs {
12352183 507 struct iscsi_scsi_req iscsi_hdr;
6733b39a
JK		 508 unsigned char pad1[16];
509 struct pdu_data_out iscsi_data_pdu;
510 unsigned char pad2[BE_SENSE_INFO_SIZE -
511 sizeof(struct pdu_data_out)];
512};
513
514struct beiscsi_io_task {
515 struct wrb_handle *pwrb_handle;
516 struct sgl_handle *psgl_handle;
517 struct beiscsi_conn *conn;
518 struct scsi_cmnd *scsi_cmnd;
9122e991 519 int num_sg;
340c99e9 520 struct hwi_wrb_context *pwrb_context;
6733b39a
JK		 521 unsigned int cmd_sn;
522 unsigned int flags;
523 unsigned short cid;
524 unsigned short header_len;
bfead3b2 525 itt_t libiscsi_itt;
6733b39a
JK		 526 struct be_cmd_bhs *cmd_bhs;
527 struct be_bus_address bhs_pa;
528 unsigned short bhs_len;
d629c471
JSJ		 529 dma_addr_t mtask_addr;
530 uint32_t mtask_data_count;
09a1093a 531 uint8_t wrb_type;
6733b39a
JK		 532};
533
534struct be_nonio_bhs {
535 struct iscsi_hdr iscsi_hdr;
536 unsigned char pad1[16];
537 struct pdu_data_out iscsi_data_pdu;
538 unsigned char pad2[BE_SENSE_INFO_SIZE -
539 sizeof(struct pdu_data_out)];
540};
541
542struct be_status_bhs {
12352183 543 struct iscsi_scsi_req iscsi_hdr;
6733b39a
JK		 544 unsigned char pad1[16];
545 /**
546 * The plus 2 below is to hold the sense info length that gets
547 * DMA'ed by RxULP
548 */
549 unsigned char sense_info[BE_SENSE_INFO_SIZE];
550};
551
552struct iscsi_sge {
553 u32 dw[4];
554};
555
556/**
557 * Pseudo amap definition in which each bit of the actual structure is defined
558 * as a byte: used to calculate offset/shift/mask of each field
559 */
560struct amap_iscsi_sge {
561 u8 addr_hi[32];
562 u8 addr_lo[32];
563 u8 sge_offset[22]; /* DWORD 2 */
564 u8 rsvd0[9]; /* DWORD 2 */
565 u8 last_sge; /* DWORD 2 */
566 u8 len[17]; /* DWORD 3 */
567 u8 rsvd1[15]; /* DWORD 3 */
568};
569
570struct beiscsi_offload_params {
7331613e 571 u32 dw[6];
6733b39a
JK		 572};
573
574#define OFFLD_PARAMS_ERL 0x00000003
575#define OFFLD_PARAMS_DDE 0x00000004
576#define OFFLD_PARAMS_HDE 0x00000008
577#define OFFLD_PARAMS_IR2T 0x00000010
578#define OFFLD_PARAMS_IMD 0x00000020
acb9693c
JSJ		 579#define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040
580#define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080
581#define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
6733b39a
JK		 582
583/**
584 * Pseudo amap definition in which each bit of the actual structure is defined
585 * as a byte: used to calculate offset/shift/mask of each field
586 */
587struct amap_beiscsi_offload_params {
588 u8 max_burst_length[32];
589 u8 max_send_data_segment_length[32];
590 u8 first_burst_length[32];
591 u8 erl[2];
592 u8 dde[1];
593 u8 hde[1];
594 u8 ir2t[1];
595 u8 imd[1];
acb9693c
JSJ		 596 u8 data_seq_inorder[1];
597 u8 pdu_seq_inorder[1];
598 u8 max_r2t[16];
599 u8 pad[8];
6733b39a 600 u8 exp_statsn[32];
7331613e 601 u8 max_recv_data_segment_length[32];
6733b39a
JK		 602};
603
604/* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
605 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
606
607struct async_pdu_handle {
608 struct list_head link;
609 struct be_bus_address pa;
610 void *pbuffer;
611 unsigned int consumed;
612 unsigned char index;
613 unsigned char is_header;
614 unsigned short cri;
615 unsigned long buffer_len;
616};
617
618struct hwi_async_entry {
619 struct {
620 unsigned char hdr_received;
621 unsigned char hdr_len;
622 unsigned short bytes_received;
623 unsigned int bytes_needed;
624 struct list_head list;
625 } wait_queue;
626
627 struct list_head header_busy_list;
628 struct list_head data_busy_list;
629};
630
6733b39a
JK		 631struct hwi_async_pdu_context {
632 struct {
633 struct be_bus_address pa_base;
634 void *va_base;
635 void *ring_base;
636 struct async_pdu_handle *handle_base;
637
638 unsigned int host_write_ptr;
639 unsigned int ep_read_ptr;
640 unsigned int writables;
641
642 unsigned int free_entries;
643 unsigned int busy_entries;
6733b39a
JK		 644
645 struct list_head free_list;
646 } async_header;
647
648 struct {
649 struct be_bus_address pa_base;
650 void *va_base;
651 void *ring_base;
652 struct async_pdu_handle *handle_base;
653
654 unsigned int host_write_ptr;
655 unsigned int ep_read_ptr;
656 unsigned int writables;
657
658 unsigned int free_entries;
659 unsigned int busy_entries;
6733b39a 660 struct list_head free_list;
6733b39a
JK		 661 } async_data;
662
dc63aac6
JK		 663 unsigned int buffer_size;
664 unsigned int num_entries;
8a86e833
JK		 665#define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
666 unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
6733b39a
JK		 667 /**
668 * This is a varying size list! Do not add anything
669 * after this entry!!
670 */
a7909b39 671 struct hwi_async_entry *async_entry;
6733b39a
JK		 672};
673
674#define PDUCQE_CODE_MASK 0x0000003F
675#define PDUCQE_DPL_MASK 0xFFFF0000
676#define PDUCQE_INDEX_MASK 0x0000FFFF
677
678struct i_t_dpdu_cqe {
679 u32 dw[4];
680} __packed;
681
682/**
683 * Pseudo amap definition in which each bit of the actual structure is defined
684 * as a byte: used to calculate offset/shift/mask of each field
685 */
686struct amap_i_t_dpdu_cqe {
687 u8 db_addr_hi[32];
688 u8 db_addr_lo[32];
689 u8 code[6];
690 u8 cid[10];
691 u8 dpl[16];
692 u8 index[16];
693 u8 num_cons[10];
694 u8 rsvd0[4];
695 u8 final;
696 u8 valid;
697} __packed;
698
73133261
JSJ		 699struct amap_i_t_dpdu_cqe_v2 {
700 u8 db_addr_hi[32]; /* DWORD 0 */
701 u8 db_addr_lo[32]; /* DWORD 1 */
702 u8 code[6]; /* DWORD 2 */
703 u8 num_cons; /* DWORD 2*/
704 u8 rsvd0[8]; /* DWORD 2 */
705 u8 dpl[17]; /* DWORD 2 */
706 u8 index[16]; /* DWORD 3 */
707 u8 cid[13]; /* DWORD 3 */
708 u8 rsvd1; /* DWORD 3 */
709 u8 final; /* DWORD 3 */
710 u8 valid; /* DWORD 3 */
711} __packed;
712
6733b39a
JK		 713#define CQE_VALID_MASK 0x80000000
714#define CQE_CODE_MASK 0x0000003F
715#define CQE_CID_MASK 0x0000FFC0
716
717#define EQE_VALID_MASK 0x00000001
718#define EQE_MAJORCODE_MASK 0x0000000E
719#define EQE_RESID_MASK 0xFFFF0000
720
721struct be_eq_entry {
722 u32 dw[1];
723} __packed;
724
725/**
726 * Pseudo amap definition in which each bit of the actual structure is defined
727 * as a byte: used to calculate offset/shift/mask of each field
728 */
729struct amap_eq_entry {
730 u8 valid; /* DWORD 0 */
731 u8 major_code[3]; /* DWORD 0 */
732 u8 minor_code[12]; /* DWORD 0 */
733 u8 resource_id[16]; /* DWORD 0 */
734
735} __packed;
736
737struct cq_db {
738 u32 dw[1];
739} __packed;
740
741/**
742 * Pseudo amap definition in which each bit of the actual structure is defined
743 * as a byte: used to calculate offset/shift/mask of each field
744 */
745struct amap_cq_db {
746 u8 qid[10];
747 u8 event[1];
748 u8 rsvd0[5];
749 u8 num_popped[13];
750 u8 rearm[1];
751 u8 rsvd1[2];
752} __packed;
753
754void beiscsi_process_eq(struct beiscsi_hba *phba);
755
6733b39a
JK		 756struct iscsi_wrb {
757 u32 dw[16];
758} __packed;
759
760#define WRB_TYPE_MASK 0xF0000000
09a1093a
JSJ		 761#define SKH_WRB_TYPE_OFFSET 27
762#define BE_WRB_TYPE_OFFSET 28
763
764#define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
765 (pwrb->dw[0] |= (wrb_type << type_offset))
6733b39a
JK		 766
767/**
768 * Pseudo amap definition in which each bit of the actual structure is defined
769 * as a byte: used to calculate offset/shift/mask of each field
770 */
771struct amap_iscsi_wrb {
772 u8 lun[14]; /* DWORD 0 */
773 u8 lt; /* DWORD 0 */
774 u8 invld; /* DWORD 0 */
775 u8 wrb_idx[8]; /* DWORD 0 */
776 u8 dsp; /* DWORD 0 */
777 u8 dmsg; /* DWORD 0 */
778 u8 undr_run; /* DWORD 0 */
779 u8 over_run; /* DWORD 0 */
780 u8 type[4]; /* DWORD 0 */
781 u8 ptr2nextwrb[8]; /* DWORD 1 */
782 u8 r2t_exp_dtl[24]; /* DWORD 1 */
783 u8 sgl_icd_idx[12]; /* DWORD 2 */
784 u8 rsvd0[20]; /* DWORD 2 */
785 u8 exp_data_sn[32]; /* DWORD 3 */
786 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
787 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
788 u8 cmdsn_itt[32]; /* DWORD 6 */
789 u8 dif_ref_tag[32]; /* DWORD 7 */
790 u8 sge0_addr_hi[32]; /* DWORD 8 */
791 u8 sge0_addr_lo[32]; /* DWORD 9 */
792 u8 sge0_offset[22]; /* DWORD 10 */
793 u8 pbs; /* DWORD 10 */
794 u8 dif_mode[2]; /* DWORD 10 */
795 u8 rsvd1[6]; /* DWORD 10 */
796 u8 sge0_last; /* DWORD 10 */
797 u8 sge0_len[17]; /* DWORD 11 */
798 u8 dif_meta_tag[14]; /* DWORD 11 */
799 u8 sge0_in_ddr; /* DWORD 11 */
800 u8 sge1_addr_hi[32]; /* DWORD 12 */
801 u8 sge1_addr_lo[32]; /* DWORD 13 */
802 u8 sge1_r2t_offset[22]; /* DWORD 14 */
803 u8 rsvd2[9]; /* DWORD 14 */
804 u8 sge1_last; /* DWORD 14 */
805 u8 sge1_len[17]; /* DWORD 15 */
806 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
807 u8 rsvd3[2]; /* DWORD 15 */
808 u8 sge1_in_ddr; /* DWORD 15 */
809
810} __packed;
811
09a1093a
JSJ		 812struct amap_iscsi_wrb_v2 {
813 u8 r2t_exp_dtl[25]; /* DWORD 0 */
814 u8 rsvd0[2]; /* DWORD 0*/
815 u8 type[5]; /* DWORD 0 */
816 u8 ptr2nextwrb[8]; /* DWORD 1 */
817 u8 wrb_idx[8]; /* DWORD 1 */
818 u8 lun[16]; /* DWORD 1 */
819 u8 sgl_idx[16]; /* DWORD 2 */
820 u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
821 u8 exp_data_sn[32]; /* DWORD 3 */
822 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
823 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
824 u8 cq_id[16]; /* DWORD 6 */
825 u8 rsvd1[16]; /* DWORD 6 */
826 u8 cmdsn_itt[32]; /* DWORD 7 */
827 u8 sge0_addr_hi[32]; /* DWORD 8 */
828 u8 sge0_addr_lo[32]; /* DWORD 9 */
829 u8 sge0_offset[24]; /* DWORD 10 */
830 u8 rsvd2[7]; /* DWORD 10 */
831 u8 sge0_last; /* DWORD 10 */
832 u8 sge0_len[17]; /* DWORD 11 */
833 u8 rsvd3[7]; /* DWORD 11 */
834 u8 diff_enbl; /* DWORD 11 */
835 u8 u_run; /* DWORD 11 */
836 u8 o_run; /* DWORD 11 */
837 u8 invalid; /* DWORD 11 */
838 u8 dsp; /* DWORD 11 */
839 u8 dmsg; /* DWORD 11 */
840 u8 rsvd4; /* DWORD 11 */
841 u8 lt; /* DWORD 11 */
842 u8 sge1_addr_hi[32]; /* DWORD 12 */
843 u8 sge1_addr_lo[32]; /* DWORD 13 */
844 u8 sge1_r2t_offset[24]; /* DWORD 14 */
845 u8 rsvd5[7]; /* DWORD 14 */
846 u8 sge1_last; /* DWORD 14 */
847 u8 sge1_len[17]; /* DWORD 15 */
848 u8 rsvd6[15]; /* DWORD 15 */
849} __packed;
850
851
340c99e9
JSJ		 852struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
853 struct hwi_wrb_context **pcontext);
6733b39a
JK		 854void
855free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
856
4a4a11b9
JK		 857void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
858 struct iscsi_task *task);
756d29c8 859
e08b3c8b
JK		 860void hwi_ring_cq_db(struct beiscsi_hba *phba,
861 unsigned int id, unsigned int num_processed,
1094cf68 862 unsigned char rearm);
b7ab35b1 863
1094cf68 864unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget);
2e4e8f65 865void beiscsi_process_mcc_cq(struct beiscsi_hba *phba);
b7ab35b1 866
6733b39a
JK		 867struct pdu_nop_out {
868 u32 dw[12];
869};
870
871/**
872 * Pseudo amap definition in which each bit of the actual structure is defined
873 * as a byte: used to calculate offset/shift/mask of each field
874 */
875struct amap_pdu_nop_out {
876 u8 opcode[6]; /* opcode 0x00 */
877 u8 i_bit; /* I Bit */
878 u8 x_bit; /* reserved; should be 0 */
879 u8 fp_bit_filler1[7];
880 u8 f_bit; /* always 1 */
881 u8 reserved1[16];
882 u8 ahs_length[8]; /* no AHS */
883 u8 data_len_hi[8];
884 u8 data_len_lo[16]; /* DataSegmentLength */
885 u8 lun[64];
886 u8 itt[32]; /* initiator id for ping or 0xffffffff */
887 u8 ttt[32]; /* target id for ping or 0xffffffff */
888 u8 cmd_sn[32];
889 u8 exp_stat_sn[32];
890 u8 reserved5[128];
891};
892
893#define PDUBASE_OPCODE_MASK 0x0000003F
894#define PDUBASE_DATALENHI_MASK 0x0000FF00
895#define PDUBASE_DATALENLO_MASK 0xFFFF0000
896
897struct pdu_base {
898 u32 dw[16];
899} __packed;
900
901/**
902 * Pseudo amap definition in which each bit of the actual structure is defined
903 * as a byte: used to calculate offset/shift/mask of each field
904 */
905struct amap_pdu_base {
906 u8 opcode[6];
907 u8 i_bit; /* immediate bit */
908 u8 x_bit; /* reserved, always 0 */
909 u8 reserved1[24]; /* opcode-specific fields */
910 u8 ahs_length[8]; /* length units is 4 byte words */
911 u8 data_len_hi[8];
912 u8 data_len_lo[16]; /* DatasegmentLength */
913 u8 lun[64]; /* lun or opcode-specific fields */
914 u8 itt[32]; /* initiator task tag */
915 u8 reserved4[224];
916};
917
918struct iscsi_target_context_update_wrb {
919 u32 dw[16];
920} __packed;
921
922/**
923 * Pseudo amap definition in which each bit of the actual structure is defined
924 * as a byte: used to calculate offset/shift/mask of each field
925 */
acb9693c 926#define BE_TGT_CTX_UPDT_CMD 0x07
6733b39a
JK		 927struct amap_iscsi_target_context_update_wrb {
928 u8 lun[14]; /* DWORD 0 */
929 u8 lt; /* DWORD 0 */
930 u8 invld; /* DWORD 0 */
931 u8 wrb_idx[8]; /* DWORD 0 */
932 u8 dsp; /* DWORD 0 */
933 u8 dmsg; /* DWORD 0 */
934 u8 undr_run; /* DWORD 0 */
935 u8 over_run; /* DWORD 0 */
936 u8 type[4]; /* DWORD 0 */
937 u8 ptr2nextwrb[8]; /* DWORD 1 */
938 u8 max_burst_length[19]; /* DWORD 1 */
939 u8 rsvd0[5]; /* DWORD 1 */
940 u8 rsvd1[15]; /* DWORD 2 */
941 u8 max_send_data_segment_length[17]; /* DWORD 2 */
942 u8 first_burst_length[14]; /* DWORD 3 */
943 u8 rsvd2[2]; /* DWORD 3 */
944 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
945 u8 rsvd3[5]; /* DWORD 3 */
946 u8 session_state[3]; /* DWORD 3 */
947 u8 rsvd4[16]; /* DWORD 4 */
948 u8 tx_jumbo; /* DWORD 4 */
949 u8 hde; /* DWORD 4 */
950 u8 dde; /* DWORD 4 */
951 u8 erl[2]; /* DWORD 4 */
952 u8 domain_id[5]; /* DWORD 4 */
953 u8 mode; /* DWORD 4 */
954 u8 imd; /* DWORD 4 */
955 u8 ir2t; /* DWORD 4 */
956 u8 notpredblq[2]; /* DWORD 4 */
957 u8 compltonack; /* DWORD 4 */
958 u8 stat_sn[32]; /* DWORD 5 */
959 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
960 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
961 u8 pad_addr_hi[32]; /* DWORD 8 */
962 u8 pad_addr_lo[32]; /* DWORD 9 */
963 u8 rsvd5[32]; /* DWORD 10 */
964 u8 rsvd6[32]; /* DWORD 11 */
965 u8 rsvd7[32]; /* DWORD 12 */
966 u8 rsvd8[32]; /* DWORD 13 */
967 u8 rsvd9[32]; /* DWORD 14 */
968 u8 rsvd10[32]; /* DWORD 15 */
969
970} __packed;
971
acb9693c
JSJ		 972#define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024)
973#define BEISCSI_MAX_CXNS 1
974struct amap_iscsi_target_context_update_wrb_v2 {
975 u8 max_burst_length[24]; /* DWORD 0 */
976 u8 rsvd0[3]; /* DWORD 0 */
977 u8 type[5]; /* DWORD 0 */
978 u8 ptr2nextwrb[8]; /* DWORD 1 */
979 u8 wrb_idx[8]; /* DWORD 1 */
980 u8 rsvd1[16]; /* DWORD 1 */
981 u8 max_send_data_segment_length[24]; /* DWORD 2 */
982 u8 rsvd2[8]; /* DWORD 2 */
983 u8 first_burst_length[24]; /* DWORD 3 */
984 u8 rsvd3[8]; /* DOWRD 3 */
985 u8 max_r2t[16]; /* DWORD 4 */
7331613e 986 u8 rsvd4; /* DWORD 4 */
acb9693c
JSJ		 987 u8 hde; /* DWORD 4 */
988 u8 dde; /* DWORD 4 */
989 u8 erl[2]; /* DWORD 4 */
7331613e 990 u8 rsvd5[6]; /* DWORD 4 */
acb9693c
JSJ		 991 u8 imd; /* DWORD 4 */
992 u8 ir2t; /* DWORD 4 */
7331613e 993 u8 rsvd6[3]; /* DWORD 4 */
acb9693c 994 u8 stat_sn[32]; /* DWORD 5 */
7331613e
JK		 995 u8 rsvd7[32]; /* DWORD 6 */
996 u8 rsvd8[32]; /* DWORD 7 */
acb9693c 997 u8 max_recv_dataseg_len[24]; /* DWORD 8 */
7331613e
JK		 998 u8 rsvd9[8]; /* DWORD 8 */
999 u8 rsvd10[32]; /* DWORD 9 */
1000 u8 rsvd11[32]; /* DWORD 10 */
acb9693c 1001 u8 max_cxns[16]; /* DWORD 11 */
7331613e 1002 u8 rsvd12[11]; /* DWORD 11*/
acb9693c 1003 u8 invld; /* DWORD 11 */
7331613e 1004 u8 rsvd13;/* DWORD 11*/
acb9693c
JSJ		 1005 u8 dmsg; /* DWORD 11 */
1006 u8 data_seq_inorder; /* DWORD 11 */
1007 u8 pdu_seq_inorder; /* DWORD 11 */
7331613e
JK		 1008 u8 rsvd14[32]; /*DWORD 12 */
1009 u8 rsvd15[32]; /* DWORD 13 */
1010 u8 rsvd16[32]; /* DWORD 14 */
1011 u8 rsvd17[32]; /* DWORD 15 */
acb9693c
JSJ		 1012} __packed;
1013
1014
6733b39a
JK		 1015struct be_ring {
1016 u32 pages; /* queue size in pages */
1017 u32 id; /* queue id assigned by beklib */
1018 u32 num; /* number of elements in queue */
1019 u32 cidx; /* consumer index */
1020 u32 pidx; /* producer index -- not used by most rings */
1021 u32 item_size; /* size in bytes of one object */
8a86e833
JK		 1022 u8 ulp_num; /* ULP to which CID binded */
1023 u16 register_set;
1024 u16 doorbell_format;
1025 u32 doorbell_offset;
6733b39a
JK		 1026
1027 void *va; /* The virtual address of the ring. This
1028 * should be last to allow 32 & 64 bit debugger
1029 * extensions to work.
1030 */
1031};
1032
6733b39a
JK		 1033struct hwi_controller {
1034 struct list_head io_sgl_list;
1035 struct list_head eh_sgl_list;
1036 struct sgl_handle *psgl_handle_base;
1037 unsigned int wrb_mem_index;
1038
a7909b39 1039 struct hwi_wrb_context *wrb_context;
6733b39a 1040 struct mcc_wrb *pmcc_wrb_base;
8a86e833
JK		 1041 struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
1042 struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
6733b39a 1043 struct hwi_context_memory *phwi_ctxt;
6733b39a
JK		 1044};
1045
1046enum hwh_type_enum {
1047 HWH_TYPE_IO = 1,
1048 HWH_TYPE_LOGOUT = 2,
1049 HWH_TYPE_TMF = 3,
1050 HWH_TYPE_NOP = 4,
1051 HWH_TYPE_IO_RD = 5,
1052 HWH_TYPE_LOGIN = 11,
1053 HWH_TYPE_INVALID = 0xFFFFFFFF
1054};
1055
1056struct wrb_handle {
1057 enum hwh_type_enum type;
1058 unsigned short wrb_index;
6733b39a
JK		 1059
1060 struct iscsi_task *pio_handle;
1061 struct iscsi_wrb *pwrb;
1062};
1063
1064struct hwi_context_memory {
bfead3b2
JK		 1065 /* Adaptive interrupt coalescing (AIC) info */
1066 u16 min_eqd; /* in usecs */
1067 u16 max_eqd; /* in usecs */
1068 u16 cur_eqd; /* in usecs */
1069 struct be_eq_obj be_eq[MAX_CPUS];
22abeef0 1070 struct be_queue_info be_cq[MAX_CPUS - 1];
6733b39a 1071
a7909b39 1072 struct be_queue_info *be_wrbq;
8a86e833
JK		 1073 struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1074 struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1075 struct hwi_async_pdu_context *pasync_ctx[BEISCSI_ULP_COUNT];
6733b39a
JK		 1076};
1077
50a4b824
JB		 1078void beiscsi_start_boot_work(struct beiscsi_hba *phba, unsigned int s_handle);
1079
99bc5d55
JSJ		 1080/* Logging related definitions */
1081#define BEISCSI_LOG_INIT 0x0001 /* Initialization events */
1082#define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */
1083#define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */
1084#define BEISCSI_LOG_EH 0x0008 /* Error Handler */
1085#define BEISCSI_LOG_IO 0x0010 /* IO Code Path */
1086#define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */
afb96058 1087#define BEISCSI_LOG_ISCSI 0x0040 /* SCSI/iSCSI Protocol related Logs */
99bc5d55 1088
53aefe25
JB		 1089#define __beiscsi_log(phba, level, fmt, arg...) \
1090 shost_printk(level, phba->shost, fmt, __LINE__, ##arg)
1091
99bc5d55
JSJ		 1092#define beiscsi_log(phba, level, mask, fmt, arg...) \
1093do { \
1094 uint32_t log_value = phba->attr_log_enable; \
1095 if (((mask) & log_value) || (level[1] <= '3')) \
53aefe25
JB		 1096 __beiscsi_log(phba, level, fmt, ##arg); \
1097} while (0);
99bc5d55 1098
6733b39a 1099#endif
Linux 6.x block layer and io_uring tree(s)