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scsi: be2iscsi: Add FUNCTION_RESET during driver unload
[linux-2.6-block.git] / drivers / scsi / be2iscsi / be_main.h
CommitLineData
6733b39a 1/**
c4f39bda 2 * Copyright (C) 2005 - 2015 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
4627de93 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@avagotech.com)
6733b39a
JK		 11 *
12 * Contact Information:
4627de93 13 * linux-drivers@avagotech.com
6733b39a 14 *
c4f39bda 15 * Emulex
255fa9a3
JK		 16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a
JK		 18 */
19
20#ifndef _BEISCSI_MAIN_
21#define _BEISCSI_MAIN_
22
6733b39a
JK		 23#include <linux/kernel.h>
24#include <linux/pci.h>
82c57028 25#include <linux/if_ether.h>
6733b39a 26#include <linux/in.h>
99bc5d55
JSJ		 27#include <linux/ctype.h>
28#include <linux/module.h>
3567f36a 29#include <linux/aer.h>
6733b39a
JK		 30#include <scsi/scsi.h>
31#include <scsi/scsi_cmnd.h>
32#include <scsi/scsi_device.h>
33#include <scsi/scsi_host.h>
34#include <scsi/iscsi_proto.h>
35#include <scsi/libiscsi.h>
36#include <scsi/scsi_transport_iscsi.h>
37
6733b39a 38#define DRV_NAME "be2iscsi"
1db1194f 39#define BUILD_STR "11.0.0.0"
c4f39bda 40#define BE_NAME "Emulex OneConnect" \
2f635883 41 "Open-iSCSI Driver version" BUILD_STR
6733b39a
JK		 42#define DRV_DESC BE_NAME " " "Driver"
43
457ff3b7 44#define BE_VENDOR_ID 0x19A2
139a1b1e 45#define ELX_VENDOR_ID 0x10DF
f98c96b0 46/* DEVICE ID's for BE2 */
6733b39a
JK		 47#define BE_DEVICE_ID1 0x212
48#define OC_DEVICE_ID1 0x702
49#define OC_DEVICE_ID2 0x703
f98c96b0
JK		 50
51/* DEVICE ID's for BE3 */
52#define BE_DEVICE_ID2 0x222
bfead3b2 53#define OC_DEVICE_ID3 0x712
6733b39a 54
139a1b1e
JSJ		 55/* DEVICE ID for SKH */
56#define OC_SKH_ID1 0x722
57
7da50879
JK		 58#define BE2_IO_DEPTH 1024
59#define BE2_MAX_SESSIONS 256
6733b39a 60#define BE2_CMDS_PER_CXN 128
6733b39a
JK		 61#define BE2_TMFS 16
62#define BE2_NOPOUT_REQ 16
6733b39a
JK		 63#define BE2_SGE 32
64#define BE2_DEFPDU_HDR_SZ 64
65#define BE2_DEFPDU_DATA_SZ 8192
1094cf68 66#define BE2_MAX_NUM_CQ_PROC 512
6733b39a 67
22abeef0
JSJ		 68#define MAX_CPUS 64
69#define BEISCSI_MAX_NUM_CPUS 7
22abeef0 70
22661e25 71#define BEISCSI_VER_STRLEN 32
22abeef0 72
aa359032 73#define BEISCSI_SGLIST_ELEMENTS 30
6733b39a 74
73af08e1
JK		 75#define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */
76#define BEISCSI_MAX_SECTORS 1024 /* scsi_host->max_sectors */
15a90fe0 77#define BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE 128 /* Template size per cxn */
6733b39a
JK		 78
79#define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */
80#define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */
81#define BEISCSI_NUM_DEVICES_SUPPORTED 0x01
82#define BEISCSI_MAX_FRAGS_INIT 192
457ff3b7 83#define BE_NUM_MSIX_ENTRIES 1
e9b91193 84
6733b39a
JK		 85#define BE_SENSE_INFO_SIZE 258
86#define BE_ISCSI_PDU_HEADER_SIZE 64
87#define BE_MIN_MEM_SIZE 16384
bfead3b2 88#define MAX_CMD_SZ 65536
6733b39a
JK		 89#define IIOC_SCSI_DATA 0x05 /* Write Operation */
90
6733b39a
JK		 91/**
92 * hardware needs the async PDU buffers to be posted in multiples of 8
93 * So have atleast 8 of them by default
94 */
95
8a86e833
JK		 96#define HWI_GET_ASYNC_PDU_CTX(phwi, ulp_num) \
97 (phwi->phwi_ctxt->pasync_ctx[ulp_num])
6733b39a
JK		 98
99/********* Memory BAR register ************/
457ff3b7 100#define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc
6733b39a
JK		 101/**
102 * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt
103 * Disable" may still globally block interrupts in addition to individual
104 * interrupt masks; a mechanism for the device driver to block all interrupts
105 * atomically without having to arbitrate for the PCI Interrupt Disable bit
106 * with the OS.
107 */
108#define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */
109
110/********* ISR0 Register offset **********/
457ff3b7 111#define CEV_ISR0_OFFSET 0xC18
6733b39a
JK		 112#define CEV_ISR_SIZE 4
113
114/**
115 * Macros for reading/writing a protection domain or CSR registers
116 * in BladeEngine.
117 */
118
119#define DB_TXULP0_OFFSET 0x40
120#define DB_RXULP0_OFFSET 0xA0
121/********* Event Q door bell *************/
122#define DB_EQ_OFFSET DB_CQ_OFFSET
e08b3c8b 123#define DB_EQ_RING_ID_LOW_MASK 0x1FF /* bits 0 - 8 */
6733b39a
JK		 124/* Clear the interrupt for this eq */
125#define DB_EQ_CLR_SHIFT (9) /* bit 9 */
126/* Must be 1 */
127#define DB_EQ_EVNT_SHIFT (10) /* bit 10 */
e08b3c8b
JK		 128/* Higher Order EQ_ID bit */
129#define DB_EQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
130#define DB_EQ_HIGH_SET_SHIFT 11
131#define DB_EQ_HIGH_FEILD_SHIFT 9
6733b39a
JK		 132/* Number of event entries processed */
133#define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
134/* Rearm bit */
135#define DB_EQ_REARM_SHIFT (29) /* bit 29 */
136
137/********* Compl Q door bell *************/
457ff3b7 138#define DB_CQ_OFFSET 0x120
e08b3c8b
JK		 139#define DB_CQ_RING_ID_LOW_MASK 0x3FF /* bits 0 - 9 */
140/* Higher Order CQ_ID bit */
141#define DB_CQ_RING_ID_HIGH_MASK 0x1F /* bits 11 - 15 */
142#define DB_CQ_HIGH_SET_SHIFT 11
143#define DB_CQ_HIGH_FEILD_SHIFT 10
144
6733b39a 145/* Number of event entries processed */
457ff3b7 146#define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */
6733b39a 147/* Rearm bit */
457ff3b7 148#define DB_CQ_REARM_SHIFT (29) /* bit 29 */
6733b39a
JK		 149
150#define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr)
8a86e833
JK		 151#define HWI_GET_DEF_BUFQ_ID(pc, ulp_num) (((struct hwi_controller *)\
152 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data[ulp_num].id)
153#define HWI_GET_DEF_HDRQ_ID(pc, ulp_num) (((struct hwi_controller *)\
154 (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr[ulp_num].id)
6733b39a
JK		 155
156#define PAGES_REQUIRED(x) \
157 ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE))
158
8fcfb210
JK		 159#define BEISCSI_MSI_NAME 20 /* size of msi_name string */
160
a129d92f 161#define MEM_DESCR_OFFSET 8
8a86e833
JK		 162#define BEISCSI_DEFQ_HDR 1
163#define BEISCSI_DEFQ_DATA 0
6733b39a
JK		 164enum be_mem_enum {
165 HWI_MEM_ADDN_CONTEXT,
6733b39a
JK		 166 HWI_MEM_WRB,
167 HWI_MEM_WRBH,
bfead3b2 168 HWI_MEM_SGLH,
6733b39a 169 HWI_MEM_SGE,
a129d92f
JK		 170 HWI_MEM_TEMPLATE_HDR_ULP0,
171 HWI_MEM_ASYNC_HEADER_BUF_ULP0, /* 6 */
8a86e833
JK		 172 HWI_MEM_ASYNC_DATA_BUF_ULP0,
173 HWI_MEM_ASYNC_HEADER_RING_ULP0,
174 HWI_MEM_ASYNC_DATA_RING_ULP0,
175 HWI_MEM_ASYNC_HEADER_HANDLE_ULP0,
a129d92f 176 HWI_MEM_ASYNC_DATA_HANDLE_ULP0, /* 11 */
8a86e833 177 HWI_MEM_ASYNC_PDU_CONTEXT_ULP0,
a129d92f
JK		 178 HWI_MEM_TEMPLATE_HDR_ULP1,
179 HWI_MEM_ASYNC_HEADER_BUF_ULP1, /* 14 */
8a86e833
JK		 180 HWI_MEM_ASYNC_DATA_BUF_ULP1,
181 HWI_MEM_ASYNC_HEADER_RING_ULP1,
182 HWI_MEM_ASYNC_DATA_RING_ULP1,
183 HWI_MEM_ASYNC_HEADER_HANDLE_ULP1,
a129d92f 184 HWI_MEM_ASYNC_DATA_HANDLE_ULP1, /* 19 */
8a86e833 185 HWI_MEM_ASYNC_PDU_CONTEXT_ULP1,
6733b39a 186 ISCSI_MEM_GLOBAL_HEADER,
bfead3b2 187 SE_MEM_MAX
6733b39a
JK		 188};
189
190struct be_bus_address32 {
191 unsigned int address_lo;
192 unsigned int address_hi;
193};
194
195struct be_bus_address64 {
196 unsigned long long address;
197};
198
199struct be_bus_address {
200 union {
201 struct be_bus_address32 a32;
202 struct be_bus_address64 a64;
203 } u;
204};
205
206struct mem_array {
207 struct be_bus_address bus_address; /* Bus address of location */
208 void *virtual_address; /* virtual address to the location */
209 unsigned int size; /* Size required by memory block */
210};
211
212struct be_mem_descriptor {
213 unsigned int index; /* Index of this memory parameter */
214 unsigned int category; /* type indicates cached/non-cached */
215 unsigned int num_elements; /* number of elements in this
216 * descriptor
217 */
218 unsigned int alignment_mask; /* Alignment mask for this block */
219 unsigned int size_in_bytes; /* Size required by memory block */
220 struct mem_array *mem_array;
221};
222
223struct sgl_handle {
224 unsigned int sgl_index;
bfead3b2
JK		 225 unsigned int type;
226 unsigned int cid;
227 struct iscsi_task *task;
6733b39a
JK		 228 struct iscsi_sge *pfrag;
229};
230
231struct hba_parameters {
232 unsigned int ios_per_ctrl;
233 unsigned int cxns_per_ctrl;
234 unsigned int asyncpdus_per_ctrl;
235 unsigned int icds_per_ctrl;
236 unsigned int num_sge_per_io;
237 unsigned int defpdu_hdr_sz;
238 unsigned int defpdu_data_sz;
239 unsigned int num_cq_entries;
240 unsigned int num_eq_entries;
241 unsigned int wrbs_per_cxn;
242 unsigned int crashmode;
243 unsigned int hba_num;
244
245 unsigned int mgmt_ws_sz;
246 unsigned int hwi_ws_sz;
247
248 unsigned int eto;
249 unsigned int ldto;
250
251 unsigned int dbg_flags;
252 unsigned int num_cxn;
253
254 unsigned int eq_timer;
255 /**
256 * These are calculated from other params. They're here
257 * for debug purposes
258 */
259 unsigned int num_mcc_pages;
260 unsigned int num_mcc_cq_pages;
261 unsigned int num_cq_pages;
262 unsigned int num_eq_pages;
263
264 unsigned int num_async_pdu_buf_pages;
265 unsigned int num_async_pdu_buf_sgl_pages;
266 unsigned int num_async_pdu_buf_cq_pages;
267
268 unsigned int num_async_pdu_hdr_pages;
269 unsigned int num_async_pdu_hdr_sgl_pages;
270 unsigned int num_async_pdu_hdr_cq_pages;
271
272 unsigned int num_sge;
273};
274
4183122d
JK		 275struct invalidate_command_table {
276 unsigned short icd;
277 unsigned short cid;
278} __packed;
279
4eea99d5
JK		 280#define BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, cri) \
281 (phwi_ctrlr->wrb_context[cri].ulp_num)
282struct hwi_wrb_context {
f64d92e6 283 spinlock_t wrb_lock;
4eea99d5
JK		 284 struct list_head wrb_handle_list;
285 struct list_head wrb_handle_drvr_list;
286 struct wrb_handle **pwrb_handle_base;
287 struct wrb_handle **pwrb_handle_basestd;
288 struct iscsi_wrb *plast_wrb;
289 unsigned short alloc_index;
290 unsigned short free_index;
291 unsigned short wrb_handles_available;
292 unsigned short cid;
293 uint8_t ulp_num; /* ULP to which CID binded */
294 uint16_t register_set;
295 uint16_t doorbell_format;
296 uint32_t doorbell_offset;
297};
298
0a3db7c0
JK		 299struct ulp_cid_info {
300 unsigned short *cid_array;
301 unsigned short avlbl_cids;
302 unsigned short cid_alloc;
303 unsigned short cid_free;
304};
305
4eea99d5 306#include "be.h"
2c9dfd36
JK		 307#define chip_be2(phba) (phba->generation == BE_GEN2)
308#define chip_be3_r(phba) (phba->generation == BE_GEN3)
309#define is_chip_be2_be3r(phba) (chip_be3_r(phba) || (chip_be2(phba)))
843ae752
JK		 310
311#define BEISCSI_ULP0 0
312#define BEISCSI_ULP1 1
313#define BEISCSI_ULP_COUNT 2
314#define BEISCSI_ULP0_LOADED 0x01
315#define BEISCSI_ULP1_LOADED 0x02
0a3db7c0
JK		 316
317#define BEISCSI_ULP_AVLBL_CID(phba, ulp_num) \
318 (((struct ulp_cid_info *)phba->cid_array_info[ulp_num])->avlbl_cids)
319#define BEISCSI_ULP0_AVLBL_CID(phba) \
320 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP0)
321#define BEISCSI_ULP1_AVLBL_CID(phba) \
322 BEISCSI_ULP_AVLBL_CID(phba, BEISCSI_ULP1)
323
6733b39a
JK		 324struct beiscsi_hba {
325 struct hba_parameters params;
326 struct hwi_controller *phwi_ctrlr;
327 unsigned int mem_req[SE_MEM_MAX];
328 /* PCI BAR mapped addresses */
329 u8 __iomem *csr_va; /* CSR */
330 u8 __iomem *db_va; /* Door Bell */
331 u8 __iomem *pci_va; /* PCI Config */
332 struct be_bus_address csr_pa; /* CSR */
333 struct be_bus_address db_pa; /* CSR */
334 struct be_bus_address pci_pa; /* CSR */
335 /* PCI representation of our HBA */
336 struct pci_dev *pcidev;
6733b39a 337 unsigned short asic_revision;
bfead3b2
JK		 338 unsigned int num_cpus;
339 unsigned int nxt_cqid;
22abeef0
JSJ		 340 struct msix_entry msix_entries[MAX_CPUS];
341 char *msi_name[MAX_CPUS];
bfead3b2 342 bool msix_enabled;
6733b39a
JK		 343 struct be_mem_descriptor *init_mem;
344
345 unsigned short io_sgl_alloc_index;
346 unsigned short io_sgl_free_index;
347 unsigned short io_sgl_hndl_avbl;
348 struct sgl_handle **io_sgl_hndl_base;
bfead3b2 349 struct sgl_handle **sgl_hndl_array;
6733b39a
JK		 350
351 unsigned short eh_sgl_alloc_index;
352 unsigned short eh_sgl_free_index;
353 unsigned short eh_sgl_hndl_avbl;
354 struct sgl_handle **eh_sgl_hndl_base;
355 spinlock_t io_sgl_lock;
356 spinlock_t mgmt_sgl_lock;
8f09a3b9 357 spinlock_t async_pdu_lock;
6733b39a 358 unsigned int age;
6733b39a 359 struct list_head hba_queue;
a7909b39
JK		 360#define BE_MAX_SESSION 2048
361#define BE_SET_CID_TO_CRI(cri_index, cid) \
362 (phba->cid_to_cri_map[cid] = cri_index)
363#define BE_GET_CRI_FROM_CID(cid) (phba->cid_to_cri_map[cid])
364 unsigned short cid_to_cri_map[BE_MAX_SESSION];
0a3db7c0 365 struct ulp_cid_info *cid_array_info[BEISCSI_ULP_COUNT];
6733b39a 366 struct iscsi_endpoint **ep_array;
a7909b39 367 struct beiscsi_conn **conn_table;
6733b39a 368 struct Scsi_Host *shost;
0e43895e
MC		 369 struct iscsi_iface *ipv4_iface;
370 struct iscsi_iface *ipv6_iface;
6733b39a
JK		 371 struct {
372 /**
373 * group together since they are used most frequently
374 * for cid to cri conversion
375 */
4570f161 376#define BEISCSI_PHYS_PORT_MAX 4
6733b39a 377 unsigned int phys_port;
4570f161 378 /* valid values of phys_port id are 0, 1, 2, 3 */
68c26a3a
JK		 379 unsigned int eqid_count;
380 unsigned int cqid_count;
843ae752
JK		 381 unsigned int iscsi_cid_start[BEISCSI_ULP_COUNT];
382#define BEISCSI_GET_CID_COUNT(phba, ulp_num) \
8a86e833 383 (phba->fw_config.iscsi_cid_count[ulp_num])
843ae752
JK		 384 unsigned int iscsi_cid_count[BEISCSI_ULP_COUNT];
385 unsigned int iscsi_icd_count[BEISCSI_ULP_COUNT];
386 unsigned int iscsi_icd_start[BEISCSI_ULP_COUNT];
387 unsigned int iscsi_chain_start[BEISCSI_ULP_COUNT];
388 unsigned int iscsi_chain_count[BEISCSI_ULP_COUNT];
6733b39a 389
bfead3b2 390 unsigned short iscsi_features;
843ae752
JK		 391 uint16_t dual_ulp_aware;
392 unsigned long ulp_supported;
6733b39a
JK		 393 } fw_config;
394
9122e991 395 unsigned long state;
d1d5ca88 396#define BEISCSI_HBA_ONLINE 0
9122e991
JB		 397#define BEISCSI_HBA_LINK_UP 1
398#define BEISCSI_HBA_BOOT_FOUND 2
50a4b824 399#define BEISCSI_HBA_BOOT_WORK 3
6694095b
JB		 400#define BEISCSI_HBA_UER_SUPP 4
401#define BEISCSI_HBA_PCI_ERR 5
402#define BEISCSI_HBA_FW_TIMEOUT 6
403#define BEISCSI_HBA_IN_UE 7
404#define BEISCSI_HBA_IN_TPE 8
405
9122e991
JB		 406/* error bits */
407#define BEISCSI_HBA_IN_ERR ((1 << BEISCSI_HBA_PCI_ERR) | \
408 (1 << BEISCSI_HBA_FW_TIMEOUT) | \
6694095b
JB		 409 (1 << BEISCSI_HBA_IN_UE) | \
410 (1 << BEISCSI_HBA_IN_TPE))
9122e991 411
53aefe25 412 u8 optic_state;
10bcd47d
JB		 413 struct delayed_work eqd_update;
414 /* update EQ delay timer every 1000ms */
415#define BEISCSI_EQD_UPDATE_INTERVAL 1000
416 struct timer_list hw_check;
417 /* check for UE every 1000ms */
418#define BEISCSI_UE_DETECT_INTERVAL 1000
6694095b 419 u32 ue2rp;
d1d5ca88 420 struct delayed_work recover_port;
10e1a44a 421 struct work_struct sess_work;
e175defe 422
6c83185a 423 bool mac_addr_set;
6733b39a 424 u8 mac_address[ETH_ALEN];
53aefe25 425 u8 port_name;
048084c2 426 u8 port_speed;
22661e25 427 char fw_ver_str[BEISCSI_VER_STRLEN];
6733b39a
JK		 428 char wq_name[20];
429 struct workqueue_struct *wq; /* The actuak work queue */
6733b39a 430 struct be_ctrl_info ctrl;
f98c96b0 431 unsigned int generation;
0e43895e 432 unsigned int interface_handle;
4183122d
JK		 433 struct invalidate_command_table inv_tbl[128];
434
73af08e1 435 struct be_aic_obj aic_obj[MAX_CPUS];
99bc5d55 436 unsigned int attr_log_enable;
09a1093a
JSJ		 437 int (*iotask_fn)(struct iscsi_task *,
438 struct scatterlist *sg,
439 uint32_t num_sg, uint32_t xferlen,
440 uint32_t writedir);
50a4b824
JB		 441 struct boot_struct {
442 int retry;
443 unsigned int tag;
444 unsigned int s_handle;
445 struct be_dma_mem nonemb_cmd;
446 enum {
447 BEISCSI_BOOT_REOPEN_SESS = 1,
448 BEISCSI_BOOT_GET_SHANDLE,
449 BEISCSI_BOOT_GET_SINFO,
450 BEISCSI_BOOT_LOGOUT_SESS,
451 BEISCSI_BOOT_CREATE_KSET,
452 } action;
453 struct mgmt_session_info boot_sess;
454 struct iscsi_boot_kset *boot_kset;
455 } boot_struct;
456 struct work_struct boot_work;
6733b39a
JK		 457};
458
9122e991 459#define beiscsi_hba_in_error(phba) ((phba)->state & BEISCSI_HBA_IN_ERR)
d1d5ca88
JB		 460#define beiscsi_hba_is_online(phba) \
461 (!beiscsi_hba_in_error((phba)) && \
462 test_bit(BEISCSI_HBA_ONLINE, &phba->state))
9122e991 463
b8b9e1b8
JK		 464struct beiscsi_session {
465 struct pci_pool *bhs_pool;
466};
467
6733b39a
JK		 468/**
469 * struct beiscsi_conn - iscsi connection structure
470 */
471struct beiscsi_conn {
472 struct iscsi_conn *conn;
473 struct beiscsi_hba *phba;
474 u32 exp_statsn;
1e4be6ff 475 u32 doorbell_offset;
6733b39a
JK		 476 u32 beiscsi_conn_cid;
477 struct beiscsi_endpoint *ep;
478 unsigned short login_in_progress;
d2cecf0d 479 struct wrb_handle *plogin_wrb_handle;
6733b39a 480 struct sgl_handle *plogin_sgl_handle;
b8b9e1b8 481 struct beiscsi_session *beiscsi_sess;
bfead3b2 482 struct iscsi_task *task;
6733b39a
JK		 483};
484
485/* This structure is used by the chip */
486struct pdu_data_out {
487 u32 dw[12];
488};
489/**
490 * Pseudo amap definition in which each bit of the actual structure is defined
491 * as a byte: used to calculate offset/shift/mask of each field
492 */
493struct amap_pdu_data_out {
494 u8 opcode[6]; /* opcode */
495 u8 rsvd0[2]; /* should be 0 */
496 u8 rsvd1[7];
497 u8 final_bit; /* F bit */
498 u8 rsvd2[16];
499 u8 ahs_length[8]; /* no AHS */
500 u8 data_len_hi[8];
501 u8 data_len_lo[16]; /* DataSegmentLength */
502 u8 lun[64];
503 u8 itt[32]; /* ITT; initiator task tag */
504 u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */
505 u8 rsvd3[32];
506 u8 exp_stat_sn[32];
507 u8 rsvd4[32];
508 u8 data_sn[32];
509 u8 buffer_offset[32];
510 u8 rsvd5[32];
511};
512
513struct be_cmd_bhs {
12352183 514 struct iscsi_scsi_req iscsi_hdr;
6733b39a
JK		 515 unsigned char pad1[16];
516 struct pdu_data_out iscsi_data_pdu;
517 unsigned char pad2[BE_SENSE_INFO_SIZE -
518 sizeof(struct pdu_data_out)];
519};
520
521struct beiscsi_io_task {
522 struct wrb_handle *pwrb_handle;
523 struct sgl_handle *psgl_handle;
524 struct beiscsi_conn *conn;
525 struct scsi_cmnd *scsi_cmnd;
9122e991 526 int num_sg;
340c99e9 527 struct hwi_wrb_context *pwrb_context;
6733b39a
JK		 528 unsigned int cmd_sn;
529 unsigned int flags;
530 unsigned short cid;
531 unsigned short header_len;
bfead3b2 532 itt_t libiscsi_itt;
6733b39a
JK		 533 struct be_cmd_bhs *cmd_bhs;
534 struct be_bus_address bhs_pa;
535 unsigned short bhs_len;
d629c471
JSJ		 536 dma_addr_t mtask_addr;
537 uint32_t mtask_data_count;
09a1093a 538 uint8_t wrb_type;
6733b39a
JK		 539};
540
541struct be_nonio_bhs {
542 struct iscsi_hdr iscsi_hdr;
543 unsigned char pad1[16];
544 struct pdu_data_out iscsi_data_pdu;
545 unsigned char pad2[BE_SENSE_INFO_SIZE -
546 sizeof(struct pdu_data_out)];
547};
548
549struct be_status_bhs {
12352183 550 struct iscsi_scsi_req iscsi_hdr;
6733b39a
JK		 551 unsigned char pad1[16];
552 /**
553 * The plus 2 below is to hold the sense info length that gets
554 * DMA'ed by RxULP
555 */
556 unsigned char sense_info[BE_SENSE_INFO_SIZE];
557};
558
559struct iscsi_sge {
560 u32 dw[4];
561};
562
563/**
564 * Pseudo amap definition in which each bit of the actual structure is defined
565 * as a byte: used to calculate offset/shift/mask of each field
566 */
567struct amap_iscsi_sge {
568 u8 addr_hi[32];
569 u8 addr_lo[32];
570 u8 sge_offset[22]; /* DWORD 2 */
571 u8 rsvd0[9]; /* DWORD 2 */
572 u8 last_sge; /* DWORD 2 */
573 u8 len[17]; /* DWORD 3 */
574 u8 rsvd1[15]; /* DWORD 3 */
575};
576
577struct beiscsi_offload_params {
7331613e 578 u32 dw[6];
6733b39a
JK		 579};
580
581#define OFFLD_PARAMS_ERL 0x00000003
582#define OFFLD_PARAMS_DDE 0x00000004
583#define OFFLD_PARAMS_HDE 0x00000008
584#define OFFLD_PARAMS_IR2T 0x00000010
585#define OFFLD_PARAMS_IMD 0x00000020
acb9693c
JSJ		 586#define OFFLD_PARAMS_DATA_SEQ_INORDER 0x00000040
587#define OFFLD_PARAMS_PDU_SEQ_INORDER 0x00000080
588#define OFFLD_PARAMS_MAX_R2T 0x00FFFF00
6733b39a
JK		 589
590/**
591 * Pseudo amap definition in which each bit of the actual structure is defined
592 * as a byte: used to calculate offset/shift/mask of each field
593 */
594struct amap_beiscsi_offload_params {
595 u8 max_burst_length[32];
596 u8 max_send_data_segment_length[32];
597 u8 first_burst_length[32];
598 u8 erl[2];
599 u8 dde[1];
600 u8 hde[1];
601 u8 ir2t[1];
602 u8 imd[1];
acb9693c
JSJ		 603 u8 data_seq_inorder[1];
604 u8 pdu_seq_inorder[1];
605 u8 max_r2t[16];
606 u8 pad[8];
6733b39a 607 u8 exp_statsn[32];
7331613e 608 u8 max_recv_data_segment_length[32];
6733b39a
JK		 609};
610
611/* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
612 struct beiscsi_hba *phba, struct sol_cqe *psol);*/
613
614struct async_pdu_handle {
615 struct list_head link;
616 struct be_bus_address pa;
617 void *pbuffer;
618 unsigned int consumed;
619 unsigned char index;
620 unsigned char is_header;
621 unsigned short cri;
622 unsigned long buffer_len;
623};
624
625struct hwi_async_entry {
626 struct {
627 unsigned char hdr_received;
628 unsigned char hdr_len;
629 unsigned short bytes_received;
630 unsigned int bytes_needed;
631 struct list_head list;
632 } wait_queue;
633
634 struct list_head header_busy_list;
635 struct list_head data_busy_list;
636};
637
6733b39a
JK		 638struct hwi_async_pdu_context {
639 struct {
640 struct be_bus_address pa_base;
641 void *va_base;
642 void *ring_base;
643 struct async_pdu_handle *handle_base;
644
645 unsigned int host_write_ptr;
646 unsigned int ep_read_ptr;
647 unsigned int writables;
648
649 unsigned int free_entries;
650 unsigned int busy_entries;
6733b39a
JK		 651
652 struct list_head free_list;
653 } async_header;
654
655 struct {
656 struct be_bus_address pa_base;
657 void *va_base;
658 void *ring_base;
659 struct async_pdu_handle *handle_base;
660
661 unsigned int host_write_ptr;
662 unsigned int ep_read_ptr;
663 unsigned int writables;
664
665 unsigned int free_entries;
666 unsigned int busy_entries;
6733b39a 667 struct list_head free_list;
6733b39a
JK		 668 } async_data;
669
dc63aac6
JK		 670 unsigned int buffer_size;
671 unsigned int num_entries;
8a86e833
JK		 672#define BE_GET_ASYNC_CRI_FROM_CID(cid) (pasync_ctx->cid_to_async_cri_map[cid])
673 unsigned short cid_to_async_cri_map[BE_MAX_SESSION];
6733b39a
JK		 674 /**
675 * This is a varying size list! Do not add anything
676 * after this entry!!
677 */
a7909b39 678 struct hwi_async_entry *async_entry;
6733b39a
JK		 679};
680
681#define PDUCQE_CODE_MASK 0x0000003F
682#define PDUCQE_DPL_MASK 0xFFFF0000
683#define PDUCQE_INDEX_MASK 0x0000FFFF
684
685struct i_t_dpdu_cqe {
686 u32 dw[4];
687} __packed;
688
689/**
690 * Pseudo amap definition in which each bit of the actual structure is defined
691 * as a byte: used to calculate offset/shift/mask of each field
692 */
693struct amap_i_t_dpdu_cqe {
694 u8 db_addr_hi[32];
695 u8 db_addr_lo[32];
696 u8 code[6];
697 u8 cid[10];
698 u8 dpl[16];
699 u8 index[16];
700 u8 num_cons[10];
701 u8 rsvd0[4];
702 u8 final;
703 u8 valid;
704} __packed;
705
73133261
JSJ		 706struct amap_i_t_dpdu_cqe_v2 {
707 u8 db_addr_hi[32]; /* DWORD 0 */
708 u8 db_addr_lo[32]; /* DWORD 1 */
709 u8 code[6]; /* DWORD 2 */
710 u8 num_cons; /* DWORD 2*/
711 u8 rsvd0[8]; /* DWORD 2 */
712 u8 dpl[17]; /* DWORD 2 */
713 u8 index[16]; /* DWORD 3 */
714 u8 cid[13]; /* DWORD 3 */
715 u8 rsvd1; /* DWORD 3 */
716 u8 final; /* DWORD 3 */
717 u8 valid; /* DWORD 3 */
718} __packed;
719
6733b39a
JK		 720#define CQE_VALID_MASK 0x80000000
721#define CQE_CODE_MASK 0x0000003F
722#define CQE_CID_MASK 0x0000FFC0
723
724#define EQE_VALID_MASK 0x00000001
725#define EQE_MAJORCODE_MASK 0x0000000E
726#define EQE_RESID_MASK 0xFFFF0000
727
728struct be_eq_entry {
729 u32 dw[1];
730} __packed;
731
732/**
733 * Pseudo amap definition in which each bit of the actual structure is defined
734 * as a byte: used to calculate offset/shift/mask of each field
735 */
736struct amap_eq_entry {
737 u8 valid; /* DWORD 0 */
738 u8 major_code[3]; /* DWORD 0 */
739 u8 minor_code[12]; /* DWORD 0 */
740 u8 resource_id[16]; /* DWORD 0 */
741
742} __packed;
743
744struct cq_db {
745 u32 dw[1];
746} __packed;
747
748/**
749 * Pseudo amap definition in which each bit of the actual structure is defined
750 * as a byte: used to calculate offset/shift/mask of each field
751 */
752struct amap_cq_db {
753 u8 qid[10];
754 u8 event[1];
755 u8 rsvd0[5];
756 u8 num_popped[13];
757 u8 rearm[1];
758 u8 rsvd1[2];
759} __packed;
760
761void beiscsi_process_eq(struct beiscsi_hba *phba);
762
6733b39a
JK		 763struct iscsi_wrb {
764 u32 dw[16];
765} __packed;
766
767#define WRB_TYPE_MASK 0xF0000000
09a1093a
JSJ		 768#define SKH_WRB_TYPE_OFFSET 27
769#define BE_WRB_TYPE_OFFSET 28
770
771#define ADAPTER_SET_WRB_TYPE(pwrb, wrb_type, type_offset) \
772 (pwrb->dw[0] |= (wrb_type << type_offset))
6733b39a
JK		 773
774/**
775 * Pseudo amap definition in which each bit of the actual structure is defined
776 * as a byte: used to calculate offset/shift/mask of each field
777 */
778struct amap_iscsi_wrb {
779 u8 lun[14]; /* DWORD 0 */
780 u8 lt; /* DWORD 0 */
781 u8 invld; /* DWORD 0 */
782 u8 wrb_idx[8]; /* DWORD 0 */
783 u8 dsp; /* DWORD 0 */
784 u8 dmsg; /* DWORD 0 */
785 u8 undr_run; /* DWORD 0 */
786 u8 over_run; /* DWORD 0 */
787 u8 type[4]; /* DWORD 0 */
788 u8 ptr2nextwrb[8]; /* DWORD 1 */
789 u8 r2t_exp_dtl[24]; /* DWORD 1 */
790 u8 sgl_icd_idx[12]; /* DWORD 2 */
791 u8 rsvd0[20]; /* DWORD 2 */
792 u8 exp_data_sn[32]; /* DWORD 3 */
793 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
794 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
795 u8 cmdsn_itt[32]; /* DWORD 6 */
796 u8 dif_ref_tag[32]; /* DWORD 7 */
797 u8 sge0_addr_hi[32]; /* DWORD 8 */
798 u8 sge0_addr_lo[32]; /* DWORD 9 */
799 u8 sge0_offset[22]; /* DWORD 10 */
800 u8 pbs; /* DWORD 10 */
801 u8 dif_mode[2]; /* DWORD 10 */
802 u8 rsvd1[6]; /* DWORD 10 */
803 u8 sge0_last; /* DWORD 10 */
804 u8 sge0_len[17]; /* DWORD 11 */
805 u8 dif_meta_tag[14]; /* DWORD 11 */
806 u8 sge0_in_ddr; /* DWORD 11 */
807 u8 sge1_addr_hi[32]; /* DWORD 12 */
808 u8 sge1_addr_lo[32]; /* DWORD 13 */
809 u8 sge1_r2t_offset[22]; /* DWORD 14 */
810 u8 rsvd2[9]; /* DWORD 14 */
811 u8 sge1_last; /* DWORD 14 */
812 u8 sge1_len[17]; /* DWORD 15 */
813 u8 ref_sgl_icd_idx[12]; /* DWORD 15 */
814 u8 rsvd3[2]; /* DWORD 15 */
815 u8 sge1_in_ddr; /* DWORD 15 */
816
817} __packed;
818
09a1093a
JSJ		 819struct amap_iscsi_wrb_v2 {
820 u8 r2t_exp_dtl[25]; /* DWORD 0 */
821 u8 rsvd0[2]; /* DWORD 0*/
822 u8 type[5]; /* DWORD 0 */
823 u8 ptr2nextwrb[8]; /* DWORD 1 */
824 u8 wrb_idx[8]; /* DWORD 1 */
825 u8 lun[16]; /* DWORD 1 */
826 u8 sgl_idx[16]; /* DWORD 2 */
827 u8 ref_sgl_icd_idx[16]; /* DWORD 2 */
828 u8 exp_data_sn[32]; /* DWORD 3 */
829 u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */
830 u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */
831 u8 cq_id[16]; /* DWORD 6 */
832 u8 rsvd1[16]; /* DWORD 6 */
833 u8 cmdsn_itt[32]; /* DWORD 7 */
834 u8 sge0_addr_hi[32]; /* DWORD 8 */
835 u8 sge0_addr_lo[32]; /* DWORD 9 */
836 u8 sge0_offset[24]; /* DWORD 10 */
837 u8 rsvd2[7]; /* DWORD 10 */
838 u8 sge0_last; /* DWORD 10 */
839 u8 sge0_len[17]; /* DWORD 11 */
840 u8 rsvd3[7]; /* DWORD 11 */
841 u8 diff_enbl; /* DWORD 11 */
842 u8 u_run; /* DWORD 11 */
843 u8 o_run; /* DWORD 11 */
844 u8 invalid; /* DWORD 11 */
845 u8 dsp; /* DWORD 11 */
846 u8 dmsg; /* DWORD 11 */
847 u8 rsvd4; /* DWORD 11 */
848 u8 lt; /* DWORD 11 */
849 u8 sge1_addr_hi[32]; /* DWORD 12 */
850 u8 sge1_addr_lo[32]; /* DWORD 13 */
851 u8 sge1_r2t_offset[24]; /* DWORD 14 */
852 u8 rsvd5[7]; /* DWORD 14 */
853 u8 sge1_last; /* DWORD 14 */
854 u8 sge1_len[17]; /* DWORD 15 */
855 u8 rsvd6[15]; /* DWORD 15 */
856} __packed;
857
858
340c99e9
JSJ		 859struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
860 struct hwi_wrb_context **pcontext);
6733b39a
JK		 861void
862free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle);
863
4a4a11b9
JK		 864void beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
865 struct iscsi_task *task);
756d29c8 866
e08b3c8b
JK		 867void hwi_ring_cq_db(struct beiscsi_hba *phba,
868 unsigned int id, unsigned int num_processed,
1094cf68 869 unsigned char rearm);
b7ab35b1 870
1094cf68 871unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget);
2e4e8f65 872void beiscsi_process_mcc_cq(struct beiscsi_hba *phba);
b7ab35b1 873
6733b39a
JK		 874struct pdu_nop_out {
875 u32 dw[12];
876};
877
878/**
879 * Pseudo amap definition in which each bit of the actual structure is defined
880 * as a byte: used to calculate offset/shift/mask of each field
881 */
882struct amap_pdu_nop_out {
883 u8 opcode[6]; /* opcode 0x00 */
884 u8 i_bit; /* I Bit */
885 u8 x_bit; /* reserved; should be 0 */
886 u8 fp_bit_filler1[7];
887 u8 f_bit; /* always 1 */
888 u8 reserved1[16];
889 u8 ahs_length[8]; /* no AHS */
890 u8 data_len_hi[8];
891 u8 data_len_lo[16]; /* DataSegmentLength */
892 u8 lun[64];
893 u8 itt[32]; /* initiator id for ping or 0xffffffff */
894 u8 ttt[32]; /* target id for ping or 0xffffffff */
895 u8 cmd_sn[32];
896 u8 exp_stat_sn[32];
897 u8 reserved5[128];
898};
899
900#define PDUBASE_OPCODE_MASK 0x0000003F
901#define PDUBASE_DATALENHI_MASK 0x0000FF00
902#define PDUBASE_DATALENLO_MASK 0xFFFF0000
903
904struct pdu_base {
905 u32 dw[16];
906} __packed;
907
908/**
909 * Pseudo amap definition in which each bit of the actual structure is defined
910 * as a byte: used to calculate offset/shift/mask of each field
911 */
912struct amap_pdu_base {
913 u8 opcode[6];
914 u8 i_bit; /* immediate bit */
915 u8 x_bit; /* reserved, always 0 */
916 u8 reserved1[24]; /* opcode-specific fields */
917 u8 ahs_length[8]; /* length units is 4 byte words */
918 u8 data_len_hi[8];
919 u8 data_len_lo[16]; /* DatasegmentLength */
920 u8 lun[64]; /* lun or opcode-specific fields */
921 u8 itt[32]; /* initiator task tag */
922 u8 reserved4[224];
923};
924
925struct iscsi_target_context_update_wrb {
926 u32 dw[16];
927} __packed;
928
929/**
930 * Pseudo amap definition in which each bit of the actual structure is defined
931 * as a byte: used to calculate offset/shift/mask of each field
932 */
acb9693c 933#define BE_TGT_CTX_UPDT_CMD 0x07
6733b39a
JK		 934struct amap_iscsi_target_context_update_wrb {
935 u8 lun[14]; /* DWORD 0 */
936 u8 lt; /* DWORD 0 */
937 u8 invld; /* DWORD 0 */
938 u8 wrb_idx[8]; /* DWORD 0 */
939 u8 dsp; /* DWORD 0 */
940 u8 dmsg; /* DWORD 0 */
941 u8 undr_run; /* DWORD 0 */
942 u8 over_run; /* DWORD 0 */
943 u8 type[4]; /* DWORD 0 */
944 u8 ptr2nextwrb[8]; /* DWORD 1 */
945 u8 max_burst_length[19]; /* DWORD 1 */
946 u8 rsvd0[5]; /* DWORD 1 */
947 u8 rsvd1[15]; /* DWORD 2 */
948 u8 max_send_data_segment_length[17]; /* DWORD 2 */
949 u8 first_burst_length[14]; /* DWORD 3 */
950 u8 rsvd2[2]; /* DWORD 3 */
951 u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */
952 u8 rsvd3[5]; /* DWORD 3 */
953 u8 session_state[3]; /* DWORD 3 */
954 u8 rsvd4[16]; /* DWORD 4 */
955 u8 tx_jumbo; /* DWORD 4 */
956 u8 hde; /* DWORD 4 */
957 u8 dde; /* DWORD 4 */
958 u8 erl[2]; /* DWORD 4 */
959 u8 domain_id[5]; /* DWORD 4 */
960 u8 mode; /* DWORD 4 */
961 u8 imd; /* DWORD 4 */
962 u8 ir2t; /* DWORD 4 */
963 u8 notpredblq[2]; /* DWORD 4 */
964 u8 compltonack; /* DWORD 4 */
965 u8 stat_sn[32]; /* DWORD 5 */
966 u8 pad_buffer_addr_hi[32]; /* DWORD 6 */
967 u8 pad_buffer_addr_lo[32]; /* DWORD 7 */
968 u8 pad_addr_hi[32]; /* DWORD 8 */
969 u8 pad_addr_lo[32]; /* DWORD 9 */
970 u8 rsvd5[32]; /* DWORD 10 */
971 u8 rsvd6[32]; /* DWORD 11 */
972 u8 rsvd7[32]; /* DWORD 12 */
973 u8 rsvd8[32]; /* DWORD 13 */
974 u8 rsvd9[32]; /* DWORD 14 */
975 u8 rsvd10[32]; /* DWORD 15 */
976
977} __packed;
978
acb9693c
JSJ		 979#define BEISCSI_MAX_RECV_DATASEG_LEN (64 * 1024)
980#define BEISCSI_MAX_CXNS 1
981struct amap_iscsi_target_context_update_wrb_v2 {
982 u8 max_burst_length[24]; /* DWORD 0 */
983 u8 rsvd0[3]; /* DWORD 0 */
984 u8 type[5]; /* DWORD 0 */
985 u8 ptr2nextwrb[8]; /* DWORD 1 */
986 u8 wrb_idx[8]; /* DWORD 1 */
987 u8 rsvd1[16]; /* DWORD 1 */
988 u8 max_send_data_segment_length[24]; /* DWORD 2 */
989 u8 rsvd2[8]; /* DWORD 2 */
990 u8 first_burst_length[24]; /* DWORD 3 */
991 u8 rsvd3[8]; /* DOWRD 3 */
992 u8 max_r2t[16]; /* DWORD 4 */
7331613e 993 u8 rsvd4; /* DWORD 4 */
acb9693c
JSJ		 994 u8 hde; /* DWORD 4 */
995 u8 dde; /* DWORD 4 */
996 u8 erl[2]; /* DWORD 4 */
7331613e 997 u8 rsvd5[6]; /* DWORD 4 */
acb9693c
JSJ		 998 u8 imd; /* DWORD 4 */
999 u8 ir2t; /* DWORD 4 */
7331613e 1000 u8 rsvd6[3]; /* DWORD 4 */
acb9693c 1001 u8 stat_sn[32]; /* DWORD 5 */
7331613e
JK		 1002 u8 rsvd7[32]; /* DWORD 6 */
1003 u8 rsvd8[32]; /* DWORD 7 */
acb9693c 1004 u8 max_recv_dataseg_len[24]; /* DWORD 8 */
7331613e
JK		 1005 u8 rsvd9[8]; /* DWORD 8 */
1006 u8 rsvd10[32]; /* DWORD 9 */
1007 u8 rsvd11[32]; /* DWORD 10 */
acb9693c 1008 u8 max_cxns[16]; /* DWORD 11 */
7331613e 1009 u8 rsvd12[11]; /* DWORD 11*/
acb9693c 1010 u8 invld; /* DWORD 11 */
7331613e 1011 u8 rsvd13;/* DWORD 11*/
acb9693c
JSJ		 1012 u8 dmsg; /* DWORD 11 */
1013 u8 data_seq_inorder; /* DWORD 11 */
1014 u8 pdu_seq_inorder; /* DWORD 11 */
7331613e
JK		 1015 u8 rsvd14[32]; /*DWORD 12 */
1016 u8 rsvd15[32]; /* DWORD 13 */
1017 u8 rsvd16[32]; /* DWORD 14 */
1018 u8 rsvd17[32]; /* DWORD 15 */
acb9693c
JSJ		 1019} __packed;
1020
1021
6733b39a
JK		 1022struct be_ring {
1023 u32 pages; /* queue size in pages */
1024 u32 id; /* queue id assigned by beklib */
1025 u32 num; /* number of elements in queue */
1026 u32 cidx; /* consumer index */
1027 u32 pidx; /* producer index -- not used by most rings */
1028 u32 item_size; /* size in bytes of one object */
8a86e833
JK		 1029 u8 ulp_num; /* ULP to which CID binded */
1030 u16 register_set;
1031 u16 doorbell_format;
1032 u32 doorbell_offset;
6733b39a
JK		 1033
1034 void *va; /* The virtual address of the ring. This
1035 * should be last to allow 32 & 64 bit debugger
1036 * extensions to work.
1037 */
1038};
1039
6733b39a
JK		 1040struct hwi_controller {
1041 struct list_head io_sgl_list;
1042 struct list_head eh_sgl_list;
1043 struct sgl_handle *psgl_handle_base;
1044 unsigned int wrb_mem_index;
1045
a7909b39 1046 struct hwi_wrb_context *wrb_context;
6733b39a 1047 struct mcc_wrb *pmcc_wrb_base;
8a86e833
JK		 1048 struct be_ring default_pdu_hdr[BEISCSI_ULP_COUNT];
1049 struct be_ring default_pdu_data[BEISCSI_ULP_COUNT];
6733b39a 1050 struct hwi_context_memory *phwi_ctxt;
6733b39a
JK		 1051};
1052
1053enum hwh_type_enum {
1054 HWH_TYPE_IO = 1,
1055 HWH_TYPE_LOGOUT = 2,
1056 HWH_TYPE_TMF = 3,
1057 HWH_TYPE_NOP = 4,
1058 HWH_TYPE_IO_RD = 5,
1059 HWH_TYPE_LOGIN = 11,
1060 HWH_TYPE_INVALID = 0xFFFFFFFF
1061};
1062
1063struct wrb_handle {
1064 enum hwh_type_enum type;
1065 unsigned short wrb_index;
6733b39a
JK		 1066
1067 struct iscsi_task *pio_handle;
1068 struct iscsi_wrb *pwrb;
1069};
1070
1071struct hwi_context_memory {
bfead3b2
JK		 1072 /* Adaptive interrupt coalescing (AIC) info */
1073 u16 min_eqd; /* in usecs */
1074 u16 max_eqd; /* in usecs */
1075 u16 cur_eqd; /* in usecs */
1076 struct be_eq_obj be_eq[MAX_CPUS];
22abeef0 1077 struct be_queue_info be_cq[MAX_CPUS - 1];
6733b39a 1078
a7909b39 1079 struct be_queue_info *be_wrbq;
8a86e833
JK		 1080 struct be_queue_info be_def_hdrq[BEISCSI_ULP_COUNT];
1081 struct be_queue_info be_def_dataq[BEISCSI_ULP_COUNT];
1082 struct hwi_async_pdu_context *pasync_ctx[BEISCSI_ULP_COUNT];
6733b39a
JK		 1083};
1084
50a4b824
JB		 1085void beiscsi_start_boot_work(struct beiscsi_hba *phba, unsigned int s_handle);
1086
99bc5d55
JSJ		 1087/* Logging related definitions */
1088#define BEISCSI_LOG_INIT 0x0001 /* Initialization events */
1089#define BEISCSI_LOG_MBOX 0x0002 /* Mailbox Events */
1090#define BEISCSI_LOG_MISC 0x0004 /* Miscllaneous Events */
1091#define BEISCSI_LOG_EH 0x0008 /* Error Handler */
1092#define BEISCSI_LOG_IO 0x0010 /* IO Code Path */
1093#define BEISCSI_LOG_CONFIG 0x0020 /* CONFIG Code Path */
afb96058 1094#define BEISCSI_LOG_ISCSI 0x0040 /* SCSI/iSCSI Protocol related Logs */
99bc5d55 1095
53aefe25
JB		 1096#define __beiscsi_log(phba, level, fmt, arg...) \
1097 shost_printk(level, phba->shost, fmt, __LINE__, ##arg)
1098
99bc5d55
JSJ		 1099#define beiscsi_log(phba, level, mask, fmt, arg...) \
1100do { \
1101 uint32_t log_value = phba->attr_log_enable; \
1102 if (((mask) & log_value) || (level[1] <= '3')) \
53aefe25
JB		 1103 __beiscsi_log(phba, level, fmt, ##arg); \
1104} while (0);
99bc5d55 1105
6733b39a 1106#endif
Linux 6.x block layer and io_uring tree(s)