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6733b39a JK |
1 | /** |
2 | * Copyright (C) 2005 - 2009 ServerEngines | |
3 | * All rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
10 | * Written by: Jayamohan Kallickal (jayamohank@serverengines.com) | |
11 | * | |
12 | * Contact Information: | |
13 | * linux-drivers@serverengines.com | |
14 | * | |
15 | * ServerEngines | |
16 | * 209 N. Fair Oaks Ave | |
17 | * Sunnyvale, CA 94085 | |
18 | * | |
19 | */ | |
20 | ||
21 | #ifndef _BEISCSI_MAIN_ | |
22 | #define _BEISCSI_MAIN_ | |
23 | ||
6733b39a JK |
24 | #include <linux/kernel.h> |
25 | #include <linux/pci.h> | |
26 | #include <linux/in.h> | |
6733b39a JK |
27 | #include <scsi/scsi.h> |
28 | #include <scsi/scsi_cmnd.h> | |
29 | #include <scsi/scsi_device.h> | |
30 | #include <scsi/scsi_host.h> | |
31 | #include <scsi/iscsi_proto.h> | |
32 | #include <scsi/libiscsi.h> | |
33 | #include <scsi/scsi_transport_iscsi.h> | |
34 | ||
35 | #include "be.h" | |
6733b39a JK |
36 | #define DRV_NAME "be2iscsi" |
37 | #define BUILD_STR "2.0.527.0" | |
6733b39a JK |
38 | #define BE_NAME "ServerEngines BladeEngine2" \ |
39 | "Linux iSCSI Driver version" BUILD_STR | |
40 | #define DRV_DESC BE_NAME " " "Driver" | |
41 | ||
42 | #define BE_VENDOR_ID 0x19A2 | |
43 | #define BE_DEVICE_ID1 0x212 | |
44 | #define OC_DEVICE_ID1 0x702 | |
45 | #define OC_DEVICE_ID2 0x703 | |
bfead3b2 JK |
46 | #define OC_DEVICE_ID3 0x712 |
47 | #define OC_DEVICE_ID4 0x222 | |
6733b39a | 48 | |
7da50879 JK |
49 | #define BE2_IO_DEPTH 1024 |
50 | #define BE2_MAX_SESSIONS 256 | |
6733b39a | 51 | #define BE2_CMDS_PER_CXN 128 |
6733b39a JK |
52 | #define BE2_TMFS 16 |
53 | #define BE2_NOPOUT_REQ 16 | |
6733b39a JK |
54 | #define BE2_SGE 32 |
55 | #define BE2_DEFPDU_HDR_SZ 64 | |
56 | #define BE2_DEFPDU_DATA_SZ 8192 | |
6733b39a | 57 | |
bfead3b2 | 58 | #define MAX_CPUS 31 |
6733b39a JK |
59 | #define BEISCSI_SGLIST_ELEMENTS BE2_SGE |
60 | ||
6733b39a JK |
61 | #define BEISCSI_CMD_PER_LUN 128 /* scsi_host->cmd_per_lun */ |
62 | #define BEISCSI_MAX_SECTORS 2048 /* scsi_host->max_sectors */ | |
63 | ||
64 | #define BEISCSI_MAX_CMD_LEN 16 /* scsi_host->max_cmd_len */ | |
65 | #define BEISCSI_NUM_MAX_LUN 256 /* scsi_host->max_lun */ | |
66 | #define BEISCSI_NUM_DEVICES_SUPPORTED 0x01 | |
67 | #define BEISCSI_MAX_FRAGS_INIT 192 | |
68 | #define BE_NUM_MSIX_ENTRIES 1 | |
69 | #define MPU_EP_SEMAPHORE 0xac | |
70 | ||
71 | #define BE_SENSE_INFO_SIZE 258 | |
72 | #define BE_ISCSI_PDU_HEADER_SIZE 64 | |
73 | #define BE_MIN_MEM_SIZE 16384 | |
bfead3b2 | 74 | #define MAX_CMD_SZ 65536 |
6733b39a JK |
75 | #define IIOC_SCSI_DATA 0x05 /* Write Operation */ |
76 | ||
77 | #define DBG_LVL 0x00000001 | |
78 | #define DBG_LVL_1 0x00000001 | |
79 | #define DBG_LVL_2 0x00000002 | |
80 | #define DBG_LVL_3 0x00000004 | |
81 | #define DBG_LVL_4 0x00000008 | |
82 | #define DBG_LVL_5 0x00000010 | |
83 | #define DBG_LVL_6 0x00000020 | |
84 | #define DBG_LVL_7 0x00000040 | |
85 | #define DBG_LVL_8 0x00000080 | |
86 | ||
87 | #define SE_DEBUG(debug_mask, fmt, args...) \ | |
88 | do { \ | |
89 | if (debug_mask & DBG_LVL) { \ | |
90 | printk(KERN_ERR "(%s():%d):", __func__, __LINE__);\ | |
91 | printk(fmt, ##args); \ | |
92 | } \ | |
93 | } while (0); | |
94 | ||
bfead3b2 JK |
95 | #define BE_ADAPTER_UP 0x00000000 |
96 | #define BE_ADAPTER_LINK_DOWN 0x00000001 | |
6733b39a JK |
97 | /** |
98 | * hardware needs the async PDU buffers to be posted in multiples of 8 | |
99 | * So have atleast 8 of them by default | |
100 | */ | |
101 | ||
102 | #define HWI_GET_ASYNC_PDU_CTX(phwi) (phwi->phwi_ctxt->pasync_ctx) | |
103 | ||
104 | /********* Memory BAR register ************/ | |
105 | #define PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET 0xfc | |
106 | /** | |
107 | * Host Interrupt Enable, if set interrupts are enabled although "PCI Interrupt | |
108 | * Disable" may still globally block interrupts in addition to individual | |
109 | * interrupt masks; a mechanism for the device driver to block all interrupts | |
110 | * atomically without having to arbitrate for the PCI Interrupt Disable bit | |
111 | * with the OS. | |
112 | */ | |
113 | #define MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK (1 << 29) /* bit 29 */ | |
114 | ||
115 | /********* ISR0 Register offset **********/ | |
116 | #define CEV_ISR0_OFFSET 0xC18 | |
117 | #define CEV_ISR_SIZE 4 | |
118 | ||
119 | /** | |
120 | * Macros for reading/writing a protection domain or CSR registers | |
121 | * in BladeEngine. | |
122 | */ | |
123 | ||
124 | #define DB_TXULP0_OFFSET 0x40 | |
125 | #define DB_RXULP0_OFFSET 0xA0 | |
126 | /********* Event Q door bell *************/ | |
127 | #define DB_EQ_OFFSET DB_CQ_OFFSET | |
128 | #define DB_EQ_RING_ID_MASK 0x1FF /* bits 0 - 8 */ | |
129 | /* Clear the interrupt for this eq */ | |
130 | #define DB_EQ_CLR_SHIFT (9) /* bit 9 */ | |
131 | /* Must be 1 */ | |
132 | #define DB_EQ_EVNT_SHIFT (10) /* bit 10 */ | |
133 | /* Number of event entries processed */ | |
134 | #define DB_EQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ | |
135 | /* Rearm bit */ | |
136 | #define DB_EQ_REARM_SHIFT (29) /* bit 29 */ | |
137 | ||
138 | /********* Compl Q door bell *************/ | |
139 | #define DB_CQ_OFFSET 0x120 | |
140 | #define DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */ | |
141 | /* Number of event entries processed */ | |
142 | #define DB_CQ_NUM_POPPED_SHIFT (16) /* bits 16 - 28 */ | |
143 | /* Rearm bit */ | |
144 | #define DB_CQ_REARM_SHIFT (29) /* bit 29 */ | |
145 | ||
146 | #define GET_HWI_CONTROLLER_WS(pc) (pc->phwi_ctrlr) | |
147 | #define HWI_GET_DEF_BUFQ_ID(pc) (((struct hwi_controller *)\ | |
148 | (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_data.id) | |
149 | #define HWI_GET_DEF_HDRQ_ID(pc) (((struct hwi_controller *)\ | |
150 | (GET_HWI_CONTROLLER_WS(pc)))->default_pdu_hdr.id) | |
151 | ||
152 | #define PAGES_REQUIRED(x) \ | |
153 | ((x < PAGE_SIZE) ? 1 : ((x + PAGE_SIZE - 1) / PAGE_SIZE)) | |
154 | ||
155 | enum be_mem_enum { | |
156 | HWI_MEM_ADDN_CONTEXT, | |
6733b39a JK |
157 | HWI_MEM_WRB, |
158 | HWI_MEM_WRBH, | |
bfead3b2 | 159 | HWI_MEM_SGLH, |
6733b39a | 160 | HWI_MEM_SGE, |
bfead3b2 | 161 | HWI_MEM_ASYNC_HEADER_BUF, /* 5 */ |
6733b39a JK |
162 | HWI_MEM_ASYNC_DATA_BUF, |
163 | HWI_MEM_ASYNC_HEADER_RING, | |
bfead3b2 | 164 | HWI_MEM_ASYNC_DATA_RING, |
6733b39a | 165 | HWI_MEM_ASYNC_HEADER_HANDLE, |
bfead3b2 | 166 | HWI_MEM_ASYNC_DATA_HANDLE, /* 10 */ |
6733b39a JK |
167 | HWI_MEM_ASYNC_PDU_CONTEXT, |
168 | ISCSI_MEM_GLOBAL_HEADER, | |
bfead3b2 | 169 | SE_MEM_MAX |
6733b39a JK |
170 | }; |
171 | ||
172 | struct be_bus_address32 { | |
173 | unsigned int address_lo; | |
174 | unsigned int address_hi; | |
175 | }; | |
176 | ||
177 | struct be_bus_address64 { | |
178 | unsigned long long address; | |
179 | }; | |
180 | ||
181 | struct be_bus_address { | |
182 | union { | |
183 | struct be_bus_address32 a32; | |
184 | struct be_bus_address64 a64; | |
185 | } u; | |
186 | }; | |
187 | ||
188 | struct mem_array { | |
189 | struct be_bus_address bus_address; /* Bus address of location */ | |
190 | void *virtual_address; /* virtual address to the location */ | |
191 | unsigned int size; /* Size required by memory block */ | |
192 | }; | |
193 | ||
194 | struct be_mem_descriptor { | |
195 | unsigned int index; /* Index of this memory parameter */ | |
196 | unsigned int category; /* type indicates cached/non-cached */ | |
197 | unsigned int num_elements; /* number of elements in this | |
198 | * descriptor | |
199 | */ | |
200 | unsigned int alignment_mask; /* Alignment mask for this block */ | |
201 | unsigned int size_in_bytes; /* Size required by memory block */ | |
202 | struct mem_array *mem_array; | |
203 | }; | |
204 | ||
205 | struct sgl_handle { | |
206 | unsigned int sgl_index; | |
bfead3b2 JK |
207 | unsigned int type; |
208 | unsigned int cid; | |
209 | struct iscsi_task *task; | |
6733b39a JK |
210 | struct iscsi_sge *pfrag; |
211 | }; | |
212 | ||
213 | struct hba_parameters { | |
214 | unsigned int ios_per_ctrl; | |
215 | unsigned int cxns_per_ctrl; | |
216 | unsigned int asyncpdus_per_ctrl; | |
217 | unsigned int icds_per_ctrl; | |
218 | unsigned int num_sge_per_io; | |
219 | unsigned int defpdu_hdr_sz; | |
220 | unsigned int defpdu_data_sz; | |
221 | unsigned int num_cq_entries; | |
222 | unsigned int num_eq_entries; | |
223 | unsigned int wrbs_per_cxn; | |
224 | unsigned int crashmode; | |
225 | unsigned int hba_num; | |
226 | ||
227 | unsigned int mgmt_ws_sz; | |
228 | unsigned int hwi_ws_sz; | |
229 | ||
230 | unsigned int eto; | |
231 | unsigned int ldto; | |
232 | ||
233 | unsigned int dbg_flags; | |
234 | unsigned int num_cxn; | |
235 | ||
236 | unsigned int eq_timer; | |
237 | /** | |
238 | * These are calculated from other params. They're here | |
239 | * for debug purposes | |
240 | */ | |
241 | unsigned int num_mcc_pages; | |
242 | unsigned int num_mcc_cq_pages; | |
243 | unsigned int num_cq_pages; | |
244 | unsigned int num_eq_pages; | |
245 | ||
246 | unsigned int num_async_pdu_buf_pages; | |
247 | unsigned int num_async_pdu_buf_sgl_pages; | |
248 | unsigned int num_async_pdu_buf_cq_pages; | |
249 | ||
250 | unsigned int num_async_pdu_hdr_pages; | |
251 | unsigned int num_async_pdu_hdr_sgl_pages; | |
252 | unsigned int num_async_pdu_hdr_cq_pages; | |
253 | ||
254 | unsigned int num_sge; | |
255 | }; | |
256 | ||
257 | struct beiscsi_hba { | |
258 | struct hba_parameters params; | |
259 | struct hwi_controller *phwi_ctrlr; | |
260 | unsigned int mem_req[SE_MEM_MAX]; | |
261 | /* PCI BAR mapped addresses */ | |
262 | u8 __iomem *csr_va; /* CSR */ | |
263 | u8 __iomem *db_va; /* Door Bell */ | |
264 | u8 __iomem *pci_va; /* PCI Config */ | |
265 | struct be_bus_address csr_pa; /* CSR */ | |
266 | struct be_bus_address db_pa; /* CSR */ | |
267 | struct be_bus_address pci_pa; /* CSR */ | |
268 | /* PCI representation of our HBA */ | |
269 | struct pci_dev *pcidev; | |
270 | unsigned int state; | |
271 | unsigned short asic_revision; | |
bfead3b2 JK |
272 | unsigned int num_cpus; |
273 | unsigned int nxt_cqid; | |
274 | struct msix_entry msix_entries[MAX_CPUS + 1]; | |
275 | bool msix_enabled; | |
6733b39a JK |
276 | struct be_mem_descriptor *init_mem; |
277 | ||
278 | unsigned short io_sgl_alloc_index; | |
279 | unsigned short io_sgl_free_index; | |
280 | unsigned short io_sgl_hndl_avbl; | |
281 | struct sgl_handle **io_sgl_hndl_base; | |
bfead3b2 | 282 | struct sgl_handle **sgl_hndl_array; |
6733b39a JK |
283 | |
284 | unsigned short eh_sgl_alloc_index; | |
285 | unsigned short eh_sgl_free_index; | |
286 | unsigned short eh_sgl_hndl_avbl; | |
287 | struct sgl_handle **eh_sgl_hndl_base; | |
288 | spinlock_t io_sgl_lock; | |
289 | spinlock_t mgmt_sgl_lock; | |
290 | spinlock_t isr_lock; | |
291 | unsigned int age; | |
292 | unsigned short avlbl_cids; | |
293 | unsigned short cid_alloc; | |
294 | unsigned short cid_free; | |
295 | struct beiscsi_conn *conn_table[BE2_MAX_SESSIONS * 2]; | |
296 | struct list_head hba_queue; | |
297 | unsigned short *cid_array; | |
298 | struct iscsi_endpoint **ep_array; | |
299 | struct Scsi_Host *shost; | |
300 | struct { | |
301 | /** | |
302 | * group together since they are used most frequently | |
303 | * for cid to cri conversion | |
304 | */ | |
305 | unsigned int iscsi_cid_start; | |
306 | unsigned int phys_port; | |
307 | ||
308 | unsigned int isr_offset; | |
309 | unsigned int iscsi_icd_start; | |
310 | unsigned int iscsi_cid_count; | |
311 | unsigned int iscsi_icd_count; | |
312 | unsigned int pci_function; | |
313 | ||
314 | unsigned short cid_alloc; | |
315 | unsigned short cid_free; | |
316 | unsigned short avlbl_cids; | |
bfead3b2 | 317 | unsigned short iscsi_features; |
6733b39a JK |
318 | spinlock_t cid_lock; |
319 | } fw_config; | |
320 | ||
321 | u8 mac_address[ETH_ALEN]; | |
322 | unsigned short todo_cq; | |
323 | unsigned short todo_mcc_cq; | |
324 | char wq_name[20]; | |
325 | struct workqueue_struct *wq; /* The actuak work queue */ | |
326 | struct work_struct work_cqs; /* The work being queued */ | |
327 | struct be_ctrl_info ctrl; | |
328 | }; | |
329 | ||
b8b9e1b8 JK |
330 | struct beiscsi_session { |
331 | struct pci_pool *bhs_pool; | |
332 | }; | |
333 | ||
6733b39a JK |
334 | /** |
335 | * struct beiscsi_conn - iscsi connection structure | |
336 | */ | |
337 | struct beiscsi_conn { | |
338 | struct iscsi_conn *conn; | |
339 | struct beiscsi_hba *phba; | |
340 | u32 exp_statsn; | |
341 | u32 beiscsi_conn_cid; | |
342 | struct beiscsi_endpoint *ep; | |
343 | unsigned short login_in_progress; | |
344 | struct sgl_handle *plogin_sgl_handle; | |
b8b9e1b8 | 345 | struct beiscsi_session *beiscsi_sess; |
bfead3b2 | 346 | struct iscsi_task *task; |
6733b39a JK |
347 | }; |
348 | ||
349 | /* This structure is used by the chip */ | |
350 | struct pdu_data_out { | |
351 | u32 dw[12]; | |
352 | }; | |
353 | /** | |
354 | * Pseudo amap definition in which each bit of the actual structure is defined | |
355 | * as a byte: used to calculate offset/shift/mask of each field | |
356 | */ | |
357 | struct amap_pdu_data_out { | |
358 | u8 opcode[6]; /* opcode */ | |
359 | u8 rsvd0[2]; /* should be 0 */ | |
360 | u8 rsvd1[7]; | |
361 | u8 final_bit; /* F bit */ | |
362 | u8 rsvd2[16]; | |
363 | u8 ahs_length[8]; /* no AHS */ | |
364 | u8 data_len_hi[8]; | |
365 | u8 data_len_lo[16]; /* DataSegmentLength */ | |
366 | u8 lun[64]; | |
367 | u8 itt[32]; /* ITT; initiator task tag */ | |
368 | u8 ttt[32]; /* TTT; valid for R2T or 0xffffffff */ | |
369 | u8 rsvd3[32]; | |
370 | u8 exp_stat_sn[32]; | |
371 | u8 rsvd4[32]; | |
372 | u8 data_sn[32]; | |
373 | u8 buffer_offset[32]; | |
374 | u8 rsvd5[32]; | |
375 | }; | |
376 | ||
377 | struct be_cmd_bhs { | |
378 | struct iscsi_cmd iscsi_hdr; | |
379 | unsigned char pad1[16]; | |
380 | struct pdu_data_out iscsi_data_pdu; | |
381 | unsigned char pad2[BE_SENSE_INFO_SIZE - | |
382 | sizeof(struct pdu_data_out)]; | |
383 | }; | |
384 | ||
385 | struct beiscsi_io_task { | |
386 | struct wrb_handle *pwrb_handle; | |
387 | struct sgl_handle *psgl_handle; | |
388 | struct beiscsi_conn *conn; | |
389 | struct scsi_cmnd *scsi_cmnd; | |
390 | unsigned int cmd_sn; | |
391 | unsigned int flags; | |
392 | unsigned short cid; | |
393 | unsigned short header_len; | |
bfead3b2 | 394 | itt_t libiscsi_itt; |
6733b39a JK |
395 | struct be_cmd_bhs *cmd_bhs; |
396 | struct be_bus_address bhs_pa; | |
397 | unsigned short bhs_len; | |
398 | }; | |
399 | ||
400 | struct be_nonio_bhs { | |
401 | struct iscsi_hdr iscsi_hdr; | |
402 | unsigned char pad1[16]; | |
403 | struct pdu_data_out iscsi_data_pdu; | |
404 | unsigned char pad2[BE_SENSE_INFO_SIZE - | |
405 | sizeof(struct pdu_data_out)]; | |
406 | }; | |
407 | ||
408 | struct be_status_bhs { | |
409 | struct iscsi_cmd iscsi_hdr; | |
410 | unsigned char pad1[16]; | |
411 | /** | |
412 | * The plus 2 below is to hold the sense info length that gets | |
413 | * DMA'ed by RxULP | |
414 | */ | |
415 | unsigned char sense_info[BE_SENSE_INFO_SIZE]; | |
416 | }; | |
417 | ||
418 | struct iscsi_sge { | |
419 | u32 dw[4]; | |
420 | }; | |
421 | ||
422 | /** | |
423 | * Pseudo amap definition in which each bit of the actual structure is defined | |
424 | * as a byte: used to calculate offset/shift/mask of each field | |
425 | */ | |
426 | struct amap_iscsi_sge { | |
427 | u8 addr_hi[32]; | |
428 | u8 addr_lo[32]; | |
429 | u8 sge_offset[22]; /* DWORD 2 */ | |
430 | u8 rsvd0[9]; /* DWORD 2 */ | |
431 | u8 last_sge; /* DWORD 2 */ | |
432 | u8 len[17]; /* DWORD 3 */ | |
433 | u8 rsvd1[15]; /* DWORD 3 */ | |
434 | }; | |
435 | ||
436 | struct beiscsi_offload_params { | |
437 | u32 dw[5]; | |
438 | }; | |
439 | ||
440 | #define OFFLD_PARAMS_ERL 0x00000003 | |
441 | #define OFFLD_PARAMS_DDE 0x00000004 | |
442 | #define OFFLD_PARAMS_HDE 0x00000008 | |
443 | #define OFFLD_PARAMS_IR2T 0x00000010 | |
444 | #define OFFLD_PARAMS_IMD 0x00000020 | |
445 | ||
446 | /** | |
447 | * Pseudo amap definition in which each bit of the actual structure is defined | |
448 | * as a byte: used to calculate offset/shift/mask of each field | |
449 | */ | |
450 | struct amap_beiscsi_offload_params { | |
451 | u8 max_burst_length[32]; | |
452 | u8 max_send_data_segment_length[32]; | |
453 | u8 first_burst_length[32]; | |
454 | u8 erl[2]; | |
455 | u8 dde[1]; | |
456 | u8 hde[1]; | |
457 | u8 ir2t[1]; | |
458 | u8 imd[1]; | |
459 | u8 pad[26]; | |
460 | u8 exp_statsn[32]; | |
461 | }; | |
462 | ||
463 | /* void hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn, | |
464 | struct beiscsi_hba *phba, struct sol_cqe *psol);*/ | |
465 | ||
466 | struct async_pdu_handle { | |
467 | struct list_head link; | |
468 | struct be_bus_address pa; | |
469 | void *pbuffer; | |
470 | unsigned int consumed; | |
471 | unsigned char index; | |
472 | unsigned char is_header; | |
473 | unsigned short cri; | |
474 | unsigned long buffer_len; | |
475 | }; | |
476 | ||
477 | struct hwi_async_entry { | |
478 | struct { | |
479 | unsigned char hdr_received; | |
480 | unsigned char hdr_len; | |
481 | unsigned short bytes_received; | |
482 | unsigned int bytes_needed; | |
483 | struct list_head list; | |
484 | } wait_queue; | |
485 | ||
486 | struct list_head header_busy_list; | |
487 | struct list_head data_busy_list; | |
488 | }; | |
489 | ||
490 | #define BE_MIN_ASYNC_ENTRIES 128 | |
491 | ||
492 | struct hwi_async_pdu_context { | |
493 | struct { | |
494 | struct be_bus_address pa_base; | |
495 | void *va_base; | |
496 | void *ring_base; | |
497 | struct async_pdu_handle *handle_base; | |
498 | ||
499 | unsigned int host_write_ptr; | |
500 | unsigned int ep_read_ptr; | |
501 | unsigned int writables; | |
502 | ||
503 | unsigned int free_entries; | |
504 | unsigned int busy_entries; | |
505 | unsigned int buffer_size; | |
506 | unsigned int num_entries; | |
507 | ||
508 | struct list_head free_list; | |
509 | } async_header; | |
510 | ||
511 | struct { | |
512 | struct be_bus_address pa_base; | |
513 | void *va_base; | |
514 | void *ring_base; | |
515 | struct async_pdu_handle *handle_base; | |
516 | ||
517 | unsigned int host_write_ptr; | |
518 | unsigned int ep_read_ptr; | |
519 | unsigned int writables; | |
520 | ||
521 | unsigned int free_entries; | |
522 | unsigned int busy_entries; | |
523 | unsigned int buffer_size; | |
524 | struct list_head free_list; | |
525 | unsigned int num_entries; | |
526 | } async_data; | |
527 | ||
528 | /** | |
529 | * This is a varying size list! Do not add anything | |
530 | * after this entry!! | |
531 | */ | |
532 | struct hwi_async_entry async_entry[BE_MIN_ASYNC_ENTRIES]; | |
533 | }; | |
534 | ||
535 | #define PDUCQE_CODE_MASK 0x0000003F | |
536 | #define PDUCQE_DPL_MASK 0xFFFF0000 | |
537 | #define PDUCQE_INDEX_MASK 0x0000FFFF | |
538 | ||
539 | struct i_t_dpdu_cqe { | |
540 | u32 dw[4]; | |
541 | } __packed; | |
542 | ||
543 | /** | |
544 | * Pseudo amap definition in which each bit of the actual structure is defined | |
545 | * as a byte: used to calculate offset/shift/mask of each field | |
546 | */ | |
547 | struct amap_i_t_dpdu_cqe { | |
548 | u8 db_addr_hi[32]; | |
549 | u8 db_addr_lo[32]; | |
550 | u8 code[6]; | |
551 | u8 cid[10]; | |
552 | u8 dpl[16]; | |
553 | u8 index[16]; | |
554 | u8 num_cons[10]; | |
555 | u8 rsvd0[4]; | |
556 | u8 final; | |
557 | u8 valid; | |
558 | } __packed; | |
559 | ||
560 | #define CQE_VALID_MASK 0x80000000 | |
561 | #define CQE_CODE_MASK 0x0000003F | |
562 | #define CQE_CID_MASK 0x0000FFC0 | |
563 | ||
564 | #define EQE_VALID_MASK 0x00000001 | |
565 | #define EQE_MAJORCODE_MASK 0x0000000E | |
566 | #define EQE_RESID_MASK 0xFFFF0000 | |
567 | ||
568 | struct be_eq_entry { | |
569 | u32 dw[1]; | |
570 | } __packed; | |
571 | ||
572 | /** | |
573 | * Pseudo amap definition in which each bit of the actual structure is defined | |
574 | * as a byte: used to calculate offset/shift/mask of each field | |
575 | */ | |
576 | struct amap_eq_entry { | |
577 | u8 valid; /* DWORD 0 */ | |
578 | u8 major_code[3]; /* DWORD 0 */ | |
579 | u8 minor_code[12]; /* DWORD 0 */ | |
580 | u8 resource_id[16]; /* DWORD 0 */ | |
581 | ||
582 | } __packed; | |
583 | ||
584 | struct cq_db { | |
585 | u32 dw[1]; | |
586 | } __packed; | |
587 | ||
588 | /** | |
589 | * Pseudo amap definition in which each bit of the actual structure is defined | |
590 | * as a byte: used to calculate offset/shift/mask of each field | |
591 | */ | |
592 | struct amap_cq_db { | |
593 | u8 qid[10]; | |
594 | u8 event[1]; | |
595 | u8 rsvd0[5]; | |
596 | u8 num_popped[13]; | |
597 | u8 rearm[1]; | |
598 | u8 rsvd1[2]; | |
599 | } __packed; | |
600 | ||
601 | void beiscsi_process_eq(struct beiscsi_hba *phba); | |
602 | ||
6733b39a JK |
603 | struct iscsi_wrb { |
604 | u32 dw[16]; | |
605 | } __packed; | |
606 | ||
607 | #define WRB_TYPE_MASK 0xF0000000 | |
608 | ||
609 | /** | |
610 | * Pseudo amap definition in which each bit of the actual structure is defined | |
611 | * as a byte: used to calculate offset/shift/mask of each field | |
612 | */ | |
613 | struct amap_iscsi_wrb { | |
614 | u8 lun[14]; /* DWORD 0 */ | |
615 | u8 lt; /* DWORD 0 */ | |
616 | u8 invld; /* DWORD 0 */ | |
617 | u8 wrb_idx[8]; /* DWORD 0 */ | |
618 | u8 dsp; /* DWORD 0 */ | |
619 | u8 dmsg; /* DWORD 0 */ | |
620 | u8 undr_run; /* DWORD 0 */ | |
621 | u8 over_run; /* DWORD 0 */ | |
622 | u8 type[4]; /* DWORD 0 */ | |
623 | u8 ptr2nextwrb[8]; /* DWORD 1 */ | |
624 | u8 r2t_exp_dtl[24]; /* DWORD 1 */ | |
625 | u8 sgl_icd_idx[12]; /* DWORD 2 */ | |
626 | u8 rsvd0[20]; /* DWORD 2 */ | |
627 | u8 exp_data_sn[32]; /* DWORD 3 */ | |
628 | u8 iscsi_bhs_addr_hi[32]; /* DWORD 4 */ | |
629 | u8 iscsi_bhs_addr_lo[32]; /* DWORD 5 */ | |
630 | u8 cmdsn_itt[32]; /* DWORD 6 */ | |
631 | u8 dif_ref_tag[32]; /* DWORD 7 */ | |
632 | u8 sge0_addr_hi[32]; /* DWORD 8 */ | |
633 | u8 sge0_addr_lo[32]; /* DWORD 9 */ | |
634 | u8 sge0_offset[22]; /* DWORD 10 */ | |
635 | u8 pbs; /* DWORD 10 */ | |
636 | u8 dif_mode[2]; /* DWORD 10 */ | |
637 | u8 rsvd1[6]; /* DWORD 10 */ | |
638 | u8 sge0_last; /* DWORD 10 */ | |
639 | u8 sge0_len[17]; /* DWORD 11 */ | |
640 | u8 dif_meta_tag[14]; /* DWORD 11 */ | |
641 | u8 sge0_in_ddr; /* DWORD 11 */ | |
642 | u8 sge1_addr_hi[32]; /* DWORD 12 */ | |
643 | u8 sge1_addr_lo[32]; /* DWORD 13 */ | |
644 | u8 sge1_r2t_offset[22]; /* DWORD 14 */ | |
645 | u8 rsvd2[9]; /* DWORD 14 */ | |
646 | u8 sge1_last; /* DWORD 14 */ | |
647 | u8 sge1_len[17]; /* DWORD 15 */ | |
648 | u8 ref_sgl_icd_idx[12]; /* DWORD 15 */ | |
649 | u8 rsvd3[2]; /* DWORD 15 */ | |
650 | u8 sge1_in_ddr; /* DWORD 15 */ | |
651 | ||
652 | } __packed; | |
653 | ||
d5431488 | 654 | struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid); |
6733b39a JK |
655 | void |
656 | free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle); | |
657 | ||
756d29c8 JK |
658 | void beiscsi_process_all_cqs(struct work_struct *work); |
659 | ||
6733b39a JK |
660 | struct pdu_nop_out { |
661 | u32 dw[12]; | |
662 | }; | |
663 | ||
664 | /** | |
665 | * Pseudo amap definition in which each bit of the actual structure is defined | |
666 | * as a byte: used to calculate offset/shift/mask of each field | |
667 | */ | |
668 | struct amap_pdu_nop_out { | |
669 | u8 opcode[6]; /* opcode 0x00 */ | |
670 | u8 i_bit; /* I Bit */ | |
671 | u8 x_bit; /* reserved; should be 0 */ | |
672 | u8 fp_bit_filler1[7]; | |
673 | u8 f_bit; /* always 1 */ | |
674 | u8 reserved1[16]; | |
675 | u8 ahs_length[8]; /* no AHS */ | |
676 | u8 data_len_hi[8]; | |
677 | u8 data_len_lo[16]; /* DataSegmentLength */ | |
678 | u8 lun[64]; | |
679 | u8 itt[32]; /* initiator id for ping or 0xffffffff */ | |
680 | u8 ttt[32]; /* target id for ping or 0xffffffff */ | |
681 | u8 cmd_sn[32]; | |
682 | u8 exp_stat_sn[32]; | |
683 | u8 reserved5[128]; | |
684 | }; | |
685 | ||
686 | #define PDUBASE_OPCODE_MASK 0x0000003F | |
687 | #define PDUBASE_DATALENHI_MASK 0x0000FF00 | |
688 | #define PDUBASE_DATALENLO_MASK 0xFFFF0000 | |
689 | ||
690 | struct pdu_base { | |
691 | u32 dw[16]; | |
692 | } __packed; | |
693 | ||
694 | /** | |
695 | * Pseudo amap definition in which each bit of the actual structure is defined | |
696 | * as a byte: used to calculate offset/shift/mask of each field | |
697 | */ | |
698 | struct amap_pdu_base { | |
699 | u8 opcode[6]; | |
700 | u8 i_bit; /* immediate bit */ | |
701 | u8 x_bit; /* reserved, always 0 */ | |
702 | u8 reserved1[24]; /* opcode-specific fields */ | |
703 | u8 ahs_length[8]; /* length units is 4 byte words */ | |
704 | u8 data_len_hi[8]; | |
705 | u8 data_len_lo[16]; /* DatasegmentLength */ | |
706 | u8 lun[64]; /* lun or opcode-specific fields */ | |
707 | u8 itt[32]; /* initiator task tag */ | |
708 | u8 reserved4[224]; | |
709 | }; | |
710 | ||
711 | struct iscsi_target_context_update_wrb { | |
712 | u32 dw[16]; | |
713 | } __packed; | |
714 | ||
715 | /** | |
716 | * Pseudo amap definition in which each bit of the actual structure is defined | |
717 | * as a byte: used to calculate offset/shift/mask of each field | |
718 | */ | |
719 | struct amap_iscsi_target_context_update_wrb { | |
720 | u8 lun[14]; /* DWORD 0 */ | |
721 | u8 lt; /* DWORD 0 */ | |
722 | u8 invld; /* DWORD 0 */ | |
723 | u8 wrb_idx[8]; /* DWORD 0 */ | |
724 | u8 dsp; /* DWORD 0 */ | |
725 | u8 dmsg; /* DWORD 0 */ | |
726 | u8 undr_run; /* DWORD 0 */ | |
727 | u8 over_run; /* DWORD 0 */ | |
728 | u8 type[4]; /* DWORD 0 */ | |
729 | u8 ptr2nextwrb[8]; /* DWORD 1 */ | |
730 | u8 max_burst_length[19]; /* DWORD 1 */ | |
731 | u8 rsvd0[5]; /* DWORD 1 */ | |
732 | u8 rsvd1[15]; /* DWORD 2 */ | |
733 | u8 max_send_data_segment_length[17]; /* DWORD 2 */ | |
734 | u8 first_burst_length[14]; /* DWORD 3 */ | |
735 | u8 rsvd2[2]; /* DWORD 3 */ | |
736 | u8 tx_wrbindex_drv_msg[8]; /* DWORD 3 */ | |
737 | u8 rsvd3[5]; /* DWORD 3 */ | |
738 | u8 session_state[3]; /* DWORD 3 */ | |
739 | u8 rsvd4[16]; /* DWORD 4 */ | |
740 | u8 tx_jumbo; /* DWORD 4 */ | |
741 | u8 hde; /* DWORD 4 */ | |
742 | u8 dde; /* DWORD 4 */ | |
743 | u8 erl[2]; /* DWORD 4 */ | |
744 | u8 domain_id[5]; /* DWORD 4 */ | |
745 | u8 mode; /* DWORD 4 */ | |
746 | u8 imd; /* DWORD 4 */ | |
747 | u8 ir2t; /* DWORD 4 */ | |
748 | u8 notpredblq[2]; /* DWORD 4 */ | |
749 | u8 compltonack; /* DWORD 4 */ | |
750 | u8 stat_sn[32]; /* DWORD 5 */ | |
751 | u8 pad_buffer_addr_hi[32]; /* DWORD 6 */ | |
752 | u8 pad_buffer_addr_lo[32]; /* DWORD 7 */ | |
753 | u8 pad_addr_hi[32]; /* DWORD 8 */ | |
754 | u8 pad_addr_lo[32]; /* DWORD 9 */ | |
755 | u8 rsvd5[32]; /* DWORD 10 */ | |
756 | u8 rsvd6[32]; /* DWORD 11 */ | |
757 | u8 rsvd7[32]; /* DWORD 12 */ | |
758 | u8 rsvd8[32]; /* DWORD 13 */ | |
759 | u8 rsvd9[32]; /* DWORD 14 */ | |
760 | u8 rsvd10[32]; /* DWORD 15 */ | |
761 | ||
762 | } __packed; | |
763 | ||
764 | struct be_ring { | |
765 | u32 pages; /* queue size in pages */ | |
766 | u32 id; /* queue id assigned by beklib */ | |
767 | u32 num; /* number of elements in queue */ | |
768 | u32 cidx; /* consumer index */ | |
769 | u32 pidx; /* producer index -- not used by most rings */ | |
770 | u32 item_size; /* size in bytes of one object */ | |
771 | ||
772 | void *va; /* The virtual address of the ring. This | |
773 | * should be last to allow 32 & 64 bit debugger | |
774 | * extensions to work. | |
775 | */ | |
776 | }; | |
777 | ||
778 | struct hwi_wrb_context { | |
779 | struct list_head wrb_handle_list; | |
780 | struct list_head wrb_handle_drvr_list; | |
781 | struct wrb_handle **pwrb_handle_base; | |
782 | struct wrb_handle **pwrb_handle_basestd; | |
783 | struct iscsi_wrb *plast_wrb; | |
784 | unsigned short alloc_index; | |
785 | unsigned short free_index; | |
786 | unsigned short wrb_handles_available; | |
787 | unsigned short cid; | |
788 | }; | |
789 | ||
790 | struct hwi_controller { | |
791 | struct list_head io_sgl_list; | |
792 | struct list_head eh_sgl_list; | |
793 | struct sgl_handle *psgl_handle_base; | |
794 | unsigned int wrb_mem_index; | |
795 | ||
796 | struct hwi_wrb_context wrb_context[BE2_MAX_SESSIONS * 2]; | |
797 | struct mcc_wrb *pmcc_wrb_base; | |
798 | struct be_ring default_pdu_hdr; | |
799 | struct be_ring default_pdu_data; | |
800 | struct hwi_context_memory *phwi_ctxt; | |
6733b39a JK |
801 | }; |
802 | ||
803 | enum hwh_type_enum { | |
804 | HWH_TYPE_IO = 1, | |
805 | HWH_TYPE_LOGOUT = 2, | |
806 | HWH_TYPE_TMF = 3, | |
807 | HWH_TYPE_NOP = 4, | |
808 | HWH_TYPE_IO_RD = 5, | |
809 | HWH_TYPE_LOGIN = 11, | |
810 | HWH_TYPE_INVALID = 0xFFFFFFFF | |
811 | }; | |
812 | ||
813 | struct wrb_handle { | |
814 | enum hwh_type_enum type; | |
815 | unsigned short wrb_index; | |
816 | unsigned short nxt_wrb_index; | |
817 | ||
818 | struct iscsi_task *pio_handle; | |
819 | struct iscsi_wrb *pwrb; | |
820 | }; | |
821 | ||
822 | struct hwi_context_memory { | |
bfead3b2 JK |
823 | /* Adaptive interrupt coalescing (AIC) info */ |
824 | u16 min_eqd; /* in usecs */ | |
825 | u16 max_eqd; /* in usecs */ | |
826 | u16 cur_eqd; /* in usecs */ | |
827 | struct be_eq_obj be_eq[MAX_CPUS]; | |
828 | struct be_queue_info be_cq[MAX_CPUS]; | |
6733b39a JK |
829 | |
830 | struct be_queue_info be_def_hdrq; | |
831 | struct be_queue_info be_def_dataq; | |
832 | ||
833 | struct be_queue_info be_wrbq[BE2_MAX_SESSIONS]; | |
834 | struct be_mcc_wrb_context *pbe_mcc_context; | |
835 | ||
836 | struct hwi_async_pdu_context *pasync_ctx; | |
837 | }; | |
838 | ||
839 | #endif |