Commit | Line | Data |
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6733b39a | 1 | /** |
c4f39bda | 2 | * Copyright (C) 2005 - 2015 Emulex |
6733b39a JK |
3 | * All rights reserved. |
4 | * | |
5 | * This program is free software; you can redistribute it and/or | |
6 | * modify it under the terms of the GNU General Public License version 2 | |
7 | * as published by the Free Software Foundation. The full GNU General | |
8 | * Public License is included in this distribution in the file called COPYING. | |
9 | * | |
4627de93 | 10 | * Written by: Jayamohan Kallickal (jayamohan.kallickal@avagotech.com) |
6733b39a JK |
11 | * |
12 | * Contact Information: | |
4627de93 | 13 | * linux-drivers@avagotech.com |
6733b39a | 14 | * |
c4f39bda | 15 | * Emulex |
255fa9a3 JK |
16 | * 3333 Susan Street |
17 | * Costa Mesa, CA 92626 | |
6733b39a | 18 | */ |
255fa9a3 | 19 | |
6733b39a JK |
20 | #include <linux/reboot.h> |
21 | #include <linux/delay.h> | |
5a0e3ad6 | 22 | #include <linux/slab.h> |
6733b39a JK |
23 | #include <linux/interrupt.h> |
24 | #include <linux/blkdev.h> | |
25 | #include <linux/pci.h> | |
26 | #include <linux/string.h> | |
27 | #include <linux/kernel.h> | |
28 | #include <linux/semaphore.h> | |
c7acc5b8 | 29 | #include <linux/iscsi_boot_sysfs.h> |
acf3368f | 30 | #include <linux/module.h> |
ffce3e2e | 31 | #include <linux/bsg-lib.h> |
1094cf68 | 32 | #include <linux/irq_poll.h> |
6733b39a JK |
33 | |
34 | #include <scsi/libiscsi.h> | |
ffce3e2e JK |
35 | #include <scsi/scsi_bsg_iscsi.h> |
36 | #include <scsi/scsi_netlink.h> | |
6733b39a JK |
37 | #include <scsi/scsi_transport_iscsi.h> |
38 | #include <scsi/scsi_transport.h> | |
39 | #include <scsi/scsi_cmnd.h> | |
40 | #include <scsi/scsi_device.h> | |
41 | #include <scsi/scsi_host.h> | |
42 | #include <scsi/scsi.h> | |
43 | #include "be_main.h" | |
44 | #include "be_iscsi.h" | |
45 | #include "be_mgmt.h" | |
0a513dd8 | 46 | #include "be_cmds.h" |
6733b39a JK |
47 | |
48 | static unsigned int be_iopoll_budget = 10; | |
49 | static unsigned int be_max_phys_size = 64; | |
bfead3b2 | 50 | static unsigned int enable_msix = 1; |
6733b39a | 51 | |
6733b39a | 52 | MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR); |
76d15dbd | 53 | MODULE_VERSION(BUILD_STR); |
c4f39bda | 54 | MODULE_AUTHOR("Emulex Corporation"); |
6733b39a JK |
55 | MODULE_LICENSE("GPL"); |
56 | module_param(be_iopoll_budget, int, 0); | |
57 | module_param(enable_msix, int, 0); | |
58 | module_param(be_max_phys_size, uint, S_IRUGO); | |
99bc5d55 JSJ |
59 | MODULE_PARM_DESC(be_max_phys_size, |
60 | "Maximum Size (In Kilobytes) of physically contiguous " | |
61 | "memory that can be allocated. Range is 16 - 128"); | |
62 | ||
63 | #define beiscsi_disp_param(_name)\ | |
64 | ssize_t \ | |
65 | beiscsi_##_name##_disp(struct device *dev,\ | |
66 | struct device_attribute *attrib, char *buf) \ | |
67 | { \ | |
68 | struct Scsi_Host *shost = class_to_shost(dev);\ | |
69 | struct beiscsi_hba *phba = iscsi_host_priv(shost); \ | |
70 | uint32_t param_val = 0; \ | |
71 | param_val = phba->attr_##_name;\ | |
72 | return snprintf(buf, PAGE_SIZE, "%d\n",\ | |
73 | phba->attr_##_name);\ | |
74 | } | |
75 | ||
76 | #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\ | |
77 | int \ | |
78 | beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\ | |
79 | {\ | |
80 | if (val >= _minval && val <= _maxval) {\ | |
81 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\ | |
82 | "BA_%d : beiscsi_"#_name" updated "\ | |
83 | "from 0x%x ==> 0x%x\n",\ | |
84 | phba->attr_##_name, val); \ | |
85 | phba->attr_##_name = val;\ | |
86 | return 0;\ | |
87 | } \ | |
88 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \ | |
89 | "BA_%d beiscsi_"#_name" attribute "\ | |
90 | "cannot be updated to 0x%x, "\ | |
91 | "range allowed is ["#_minval" - "#_maxval"]\n", val);\ | |
92 | return -EINVAL;\ | |
93 | } | |
94 | ||
95 | #define beiscsi_store_param(_name) \ | |
96 | ssize_t \ | |
97 | beiscsi_##_name##_store(struct device *dev,\ | |
98 | struct device_attribute *attr, const char *buf,\ | |
99 | size_t count) \ | |
100 | { \ | |
101 | struct Scsi_Host *shost = class_to_shost(dev);\ | |
102 | struct beiscsi_hba *phba = iscsi_host_priv(shost);\ | |
103 | uint32_t param_val = 0;\ | |
104 | if (!isdigit(buf[0]))\ | |
105 | return -EINVAL;\ | |
106 | if (sscanf(buf, "%i", ¶m_val) != 1)\ | |
107 | return -EINVAL;\ | |
108 | if (beiscsi_##_name##_change(phba, param_val) == 0) \ | |
109 | return strlen(buf);\ | |
110 | else \ | |
111 | return -EINVAL;\ | |
112 | } | |
113 | ||
114 | #define beiscsi_init_param(_name, _minval, _maxval, _defval) \ | |
115 | int \ | |
116 | beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \ | |
117 | { \ | |
118 | if (val >= _minval && val <= _maxval) {\ | |
119 | phba->attr_##_name = val;\ | |
120 | return 0;\ | |
121 | } \ | |
122 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\ | |
123 | "BA_%d beiscsi_"#_name" attribute " \ | |
124 | "cannot be updated to 0x%x, "\ | |
125 | "range allowed is ["#_minval" - "#_maxval"]\n", val);\ | |
126 | phba->attr_##_name = _defval;\ | |
127 | return -EINVAL;\ | |
128 | } | |
129 | ||
130 | #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \ | |
131 | static uint beiscsi_##_name = _defval;\ | |
132 | module_param(beiscsi_##_name, uint, S_IRUGO);\ | |
133 | MODULE_PARM_DESC(beiscsi_##_name, _descp);\ | |
134 | beiscsi_disp_param(_name)\ | |
135 | beiscsi_change_param(_name, _minval, _maxval, _defval)\ | |
136 | beiscsi_store_param(_name)\ | |
137 | beiscsi_init_param(_name, _minval, _maxval, _defval)\ | |
138 | DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\ | |
139 | beiscsi_##_name##_disp, beiscsi_##_name##_store) | |
140 | ||
141 | /* | |
142 | * When new log level added update the | |
143 | * the MAX allowed value for log_enable | |
144 | */ | |
145 | BEISCSI_RW_ATTR(log_enable, 0x00, | |
146 | 0xFF, 0x00, "Enable logging Bit Mask\n" | |
147 | "\t\t\t\tInitialization Events : 0x01\n" | |
148 | "\t\t\t\tMailbox Events : 0x02\n" | |
149 | "\t\t\t\tMiscellaneous Events : 0x04\n" | |
150 | "\t\t\t\tError Handling : 0x08\n" | |
151 | "\t\t\t\tIO Path Events : 0x10\n" | |
afb96058 JK |
152 | "\t\t\t\tConfiguration Path : 0x20\n" |
153 | "\t\t\t\tiSCSI Protocol : 0x40\n"); | |
99bc5d55 | 154 | |
5cac7596 | 155 | DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL); |
26000db7 | 156 | DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL); |
22661e25 | 157 | DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL); |
d3fea9af | 158 | DEVICE_ATTR(beiscsi_phys_port, S_IRUGO, beiscsi_phys_port_disp, NULL); |
6103c1f7 JK |
159 | DEVICE_ATTR(beiscsi_active_session_count, S_IRUGO, |
160 | beiscsi_active_session_disp, NULL); | |
161 | DEVICE_ATTR(beiscsi_free_session_count, S_IRUGO, | |
162 | beiscsi_free_session_disp, NULL); | |
99bc5d55 JSJ |
163 | struct device_attribute *beiscsi_attrs[] = { |
164 | &dev_attr_beiscsi_log_enable, | |
5cac7596 | 165 | &dev_attr_beiscsi_drvr_ver, |
26000db7 | 166 | &dev_attr_beiscsi_adapter_family, |
22661e25 | 167 | &dev_attr_beiscsi_fw_ver, |
6103c1f7 JK |
168 | &dev_attr_beiscsi_active_session_count, |
169 | &dev_attr_beiscsi_free_session_count, | |
d3fea9af | 170 | &dev_attr_beiscsi_phys_port, |
99bc5d55 JSJ |
171 | NULL, |
172 | }; | |
6733b39a | 173 | |
6763daae JSJ |
174 | static char const *cqe_desc[] = { |
175 | "RESERVED_DESC", | |
176 | "SOL_CMD_COMPLETE", | |
177 | "SOL_CMD_KILLED_DATA_DIGEST_ERR", | |
178 | "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL", | |
179 | "CXN_KILLED_BURST_LEN_MISMATCH", | |
180 | "CXN_KILLED_AHS_RCVD", | |
181 | "CXN_KILLED_HDR_DIGEST_ERR", | |
182 | "CXN_KILLED_UNKNOWN_HDR", | |
183 | "CXN_KILLED_STALE_ITT_TTT_RCVD", | |
184 | "CXN_KILLED_INVALID_ITT_TTT_RCVD", | |
185 | "CXN_KILLED_RST_RCVD", | |
186 | "CXN_KILLED_TIMED_OUT", | |
187 | "CXN_KILLED_RST_SENT", | |
188 | "CXN_KILLED_FIN_RCVD", | |
189 | "CXN_KILLED_BAD_UNSOL_PDU_RCVD", | |
190 | "CXN_KILLED_BAD_WRB_INDEX_ERROR", | |
191 | "CXN_KILLED_OVER_RUN_RESIDUAL", | |
192 | "CXN_KILLED_UNDER_RUN_RESIDUAL", | |
193 | "CMD_KILLED_INVALID_STATSN_RCVD", | |
194 | "CMD_KILLED_INVALID_R2T_RCVD", | |
195 | "CMD_CXN_KILLED_LUN_INVALID", | |
196 | "CMD_CXN_KILLED_ICD_INVALID", | |
197 | "CMD_CXN_KILLED_ITT_INVALID", | |
198 | "CMD_CXN_KILLED_SEQ_OUTOFORDER", | |
199 | "CMD_CXN_KILLED_INVALID_DATASN_RCVD", | |
200 | "CXN_INVALIDATE_NOTIFY", | |
201 | "CXN_INVALIDATE_INDEX_NOTIFY", | |
202 | "CMD_INVALIDATED_NOTIFY", | |
203 | "UNSOL_HDR_NOTIFY", | |
204 | "UNSOL_DATA_NOTIFY", | |
205 | "UNSOL_DATA_DIGEST_ERROR_NOTIFY", | |
206 | "DRIVERMSG_NOTIFY", | |
207 | "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN", | |
208 | "SOL_CMD_KILLED_DIF_ERR", | |
209 | "CXN_KILLED_SYN_RCVD", | |
210 | "CXN_KILLED_IMM_DATA_RCVD" | |
211 | }; | |
212 | ||
6733b39a JK |
213 | static int beiscsi_slave_configure(struct scsi_device *sdev) |
214 | { | |
215 | blk_queue_max_segment_size(sdev->request_queue, 65536); | |
216 | return 0; | |
217 | } | |
218 | ||
4183122d JK |
219 | static int beiscsi_eh_abort(struct scsi_cmnd *sc) |
220 | { | |
221 | struct iscsi_cls_session *cls_session; | |
222 | struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr; | |
223 | struct beiscsi_io_task *aborted_io_task; | |
224 | struct iscsi_conn *conn; | |
225 | struct beiscsi_conn *beiscsi_conn; | |
226 | struct beiscsi_hba *phba; | |
227 | struct iscsi_session *session; | |
228 | struct invalidate_command_table *inv_tbl; | |
3cbb7a74 | 229 | struct be_dma_mem nonemb_cmd; |
4183122d | 230 | unsigned int cid, tag, num_invalidate; |
1957aa7f | 231 | int rc; |
4183122d JK |
232 | |
233 | cls_session = starget_to_session(scsi_target(sc->device)); | |
234 | session = cls_session->dd_data; | |
235 | ||
659743b0 | 236 | spin_lock_bh(&session->frwd_lock); |
4183122d JK |
237 | if (!aborted_task || !aborted_task->sc) { |
238 | /* we raced */ | |
659743b0 | 239 | spin_unlock_bh(&session->frwd_lock); |
4183122d JK |
240 | return SUCCESS; |
241 | } | |
242 | ||
243 | aborted_io_task = aborted_task->dd_data; | |
244 | if (!aborted_io_task->scsi_cmnd) { | |
245 | /* raced or invalid command */ | |
659743b0 | 246 | spin_unlock_bh(&session->frwd_lock); |
4183122d JK |
247 | return SUCCESS; |
248 | } | |
659743b0 | 249 | spin_unlock_bh(&session->frwd_lock); |
7626c06b JK |
250 | /* Invalidate WRB Posted for this Task */ |
251 | AMAP_SET_BITS(struct amap_iscsi_wrb, invld, | |
252 | aborted_io_task->pwrb_handle->pwrb, | |
253 | 1); | |
254 | ||
4183122d JK |
255 | conn = aborted_task->conn; |
256 | beiscsi_conn = conn->dd_data; | |
257 | phba = beiscsi_conn->phba; | |
258 | ||
259 | /* invalidate iocb */ | |
260 | cid = beiscsi_conn->beiscsi_conn_cid; | |
261 | inv_tbl = phba->inv_tbl; | |
262 | memset(inv_tbl, 0x0, sizeof(*inv_tbl)); | |
263 | inv_tbl->cid = cid; | |
264 | inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index; | |
265 | num_invalidate = 1; | |
3cbb7a74 JK |
266 | nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev, |
267 | sizeof(struct invalidate_commands_params_in), | |
268 | &nonemb_cmd.dma); | |
269 | if (nonemb_cmd.va == NULL) { | |
99bc5d55 JSJ |
270 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH, |
271 | "BM_%d : Failed to allocate memory for" | |
272 | "mgmt_invalidate_icds\n"); | |
3cbb7a74 JK |
273 | return FAILED; |
274 | } | |
275 | nonemb_cmd.size = sizeof(struct invalidate_commands_params_in); | |
276 | ||
277 | tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate, | |
278 | cid, &nonemb_cmd); | |
4183122d | 279 | if (!tag) { |
99bc5d55 JSJ |
280 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH, |
281 | "BM_%d : mgmt_invalidate_icds could not be" | |
282 | "submitted\n"); | |
3cbb7a74 JK |
283 | pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, |
284 | nonemb_cmd.va, nonemb_cmd.dma); | |
285 | ||
4183122d | 286 | return FAILED; |
4183122d | 287 | } |
e175defe | 288 | |
88840332 | 289 | rc = beiscsi_mccq_compl_wait(phba, tag, NULL, &nonemb_cmd); |
1957aa7f JK |
290 | if (rc != -EBUSY) |
291 | pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, | |
292 | nonemb_cmd.va, nonemb_cmd.dma); | |
293 | ||
4183122d JK |
294 | return iscsi_eh_abort(sc); |
295 | } | |
296 | ||
297 | static int beiscsi_eh_device_reset(struct scsi_cmnd *sc) | |
298 | { | |
299 | struct iscsi_task *abrt_task; | |
300 | struct beiscsi_io_task *abrt_io_task; | |
301 | struct iscsi_conn *conn; | |
302 | struct beiscsi_conn *beiscsi_conn; | |
303 | struct beiscsi_hba *phba; | |
304 | struct iscsi_session *session; | |
305 | struct iscsi_cls_session *cls_session; | |
306 | struct invalidate_command_table *inv_tbl; | |
3cbb7a74 | 307 | struct be_dma_mem nonemb_cmd; |
4183122d | 308 | unsigned int cid, tag, i, num_invalidate; |
1957aa7f | 309 | int rc; |
4183122d JK |
310 | |
311 | /* invalidate iocbs */ | |
312 | cls_session = starget_to_session(scsi_target(sc->device)); | |
313 | session = cls_session->dd_data; | |
659743b0 | 314 | spin_lock_bh(&session->frwd_lock); |
db7f7709 | 315 | if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) { |
659743b0 | 316 | spin_unlock_bh(&session->frwd_lock); |
db7f7709 JK |
317 | return FAILED; |
318 | } | |
4183122d JK |
319 | conn = session->leadconn; |
320 | beiscsi_conn = conn->dd_data; | |
321 | phba = beiscsi_conn->phba; | |
322 | cid = beiscsi_conn->beiscsi_conn_cid; | |
323 | inv_tbl = phba->inv_tbl; | |
324 | memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN); | |
325 | num_invalidate = 0; | |
326 | for (i = 0; i < conn->session->cmds_max; i++) { | |
327 | abrt_task = conn->session->cmds[i]; | |
328 | abrt_io_task = abrt_task->dd_data; | |
329 | if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE) | |
330 | continue; | |
331 | ||
126e964a | 332 | if (sc->device->lun != abrt_task->sc->device->lun) |
4183122d JK |
333 | continue; |
334 | ||
7626c06b JK |
335 | /* Invalidate WRB Posted for this Task */ |
336 | AMAP_SET_BITS(struct amap_iscsi_wrb, invld, | |
337 | abrt_io_task->pwrb_handle->pwrb, | |
338 | 1); | |
339 | ||
4183122d JK |
340 | inv_tbl->cid = cid; |
341 | inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index; | |
342 | num_invalidate++; | |
343 | inv_tbl++; | |
344 | } | |
659743b0 | 345 | spin_unlock_bh(&session->frwd_lock); |
4183122d JK |
346 | inv_tbl = phba->inv_tbl; |
347 | ||
3cbb7a74 JK |
348 | nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev, |
349 | sizeof(struct invalidate_commands_params_in), | |
350 | &nonemb_cmd.dma); | |
351 | if (nonemb_cmd.va == NULL) { | |
99bc5d55 JSJ |
352 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH, |
353 | "BM_%d : Failed to allocate memory for" | |
354 | "mgmt_invalidate_icds\n"); | |
3cbb7a74 JK |
355 | return FAILED; |
356 | } | |
357 | nonemb_cmd.size = sizeof(struct invalidate_commands_params_in); | |
358 | memset(nonemb_cmd.va, 0, nonemb_cmd.size); | |
359 | tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate, | |
360 | cid, &nonemb_cmd); | |
4183122d | 361 | if (!tag) { |
99bc5d55 JSJ |
362 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH, |
363 | "BM_%d : mgmt_invalidate_icds could not be" | |
364 | " submitted\n"); | |
3cbb7a74 JK |
365 | pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, |
366 | nonemb_cmd.va, nonemb_cmd.dma); | |
4183122d | 367 | return FAILED; |
4183122d | 368 | } |
e175defe | 369 | |
88840332 | 370 | rc = beiscsi_mccq_compl_wait(phba, tag, NULL, &nonemb_cmd); |
1957aa7f JK |
371 | if (rc != -EBUSY) |
372 | pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, | |
373 | nonemb_cmd.va, nonemb_cmd.dma); | |
4183122d | 374 | return iscsi_eh_device_reset(sc); |
4183122d JK |
375 | } |
376 | ||
c7acc5b8 JK |
377 | static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf) |
378 | { | |
379 | struct beiscsi_hba *phba = data; | |
f457a46f MC |
380 | struct mgmt_session_info *boot_sess = &phba->boot_sess; |
381 | struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0]; | |
c7acc5b8 JK |
382 | char *str = buf; |
383 | int rc; | |
384 | ||
385 | switch (type) { | |
386 | case ISCSI_BOOT_TGT_NAME: | |
387 | rc = sprintf(buf, "%.*s\n", | |
f457a46f MC |
388 | (int)strlen(boot_sess->target_name), |
389 | (char *)&boot_sess->target_name); | |
c7acc5b8 JK |
390 | break; |
391 | case ISCSI_BOOT_TGT_IP_ADDR: | |
f457a46f | 392 | if (boot_conn->dest_ipaddr.ip_type == 0x1) |
c7acc5b8 | 393 | rc = sprintf(buf, "%pI4\n", |
0e43895e | 394 | (char *)&boot_conn->dest_ipaddr.addr); |
c7acc5b8 JK |
395 | else |
396 | rc = sprintf(str, "%pI6\n", | |
0e43895e | 397 | (char *)&boot_conn->dest_ipaddr.addr); |
c7acc5b8 JK |
398 | break; |
399 | case ISCSI_BOOT_TGT_PORT: | |
f457a46f | 400 | rc = sprintf(str, "%d\n", boot_conn->dest_port); |
c7acc5b8 JK |
401 | break; |
402 | ||
403 | case ISCSI_BOOT_TGT_CHAP_NAME: | |
404 | rc = sprintf(str, "%.*s\n", | |
f457a46f MC |
405 | boot_conn->negotiated_login_options.auth_data.chap. |
406 | target_chap_name_length, | |
407 | (char *)&boot_conn->negotiated_login_options. | |
408 | auth_data.chap.target_chap_name); | |
c7acc5b8 JK |
409 | break; |
410 | case ISCSI_BOOT_TGT_CHAP_SECRET: | |
411 | rc = sprintf(str, "%.*s\n", | |
f457a46f MC |
412 | boot_conn->negotiated_login_options.auth_data.chap. |
413 | target_secret_length, | |
414 | (char *)&boot_conn->negotiated_login_options. | |
415 | auth_data.chap.target_secret); | |
c7acc5b8 JK |
416 | break; |
417 | case ISCSI_BOOT_TGT_REV_CHAP_NAME: | |
418 | rc = sprintf(str, "%.*s\n", | |
f457a46f MC |
419 | boot_conn->negotiated_login_options.auth_data.chap. |
420 | intr_chap_name_length, | |
421 | (char *)&boot_conn->negotiated_login_options. | |
422 | auth_data.chap.intr_chap_name); | |
c7acc5b8 JK |
423 | break; |
424 | case ISCSI_BOOT_TGT_REV_CHAP_SECRET: | |
f457a46f MC |
425 | rc = sprintf(str, "%.*s\n", |
426 | boot_conn->negotiated_login_options.auth_data.chap. | |
427 | intr_secret_length, | |
428 | (char *)&boot_conn->negotiated_login_options. | |
429 | auth_data.chap.intr_secret); | |
c7acc5b8 JK |
430 | break; |
431 | case ISCSI_BOOT_TGT_FLAGS: | |
f457a46f | 432 | rc = sprintf(str, "2\n"); |
c7acc5b8 JK |
433 | break; |
434 | case ISCSI_BOOT_TGT_NIC_ASSOC: | |
f457a46f | 435 | rc = sprintf(str, "0\n"); |
c7acc5b8 JK |
436 | break; |
437 | default: | |
438 | rc = -ENOSYS; | |
439 | break; | |
440 | } | |
441 | return rc; | |
442 | } | |
443 | ||
444 | static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf) | |
445 | { | |
446 | struct beiscsi_hba *phba = data; | |
447 | char *str = buf; | |
448 | int rc; | |
449 | ||
450 | switch (type) { | |
451 | case ISCSI_BOOT_INI_INITIATOR_NAME: | |
452 | rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname); | |
453 | break; | |
454 | default: | |
455 | rc = -ENOSYS; | |
456 | break; | |
457 | } | |
458 | return rc; | |
459 | } | |
460 | ||
461 | static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf) | |
462 | { | |
463 | struct beiscsi_hba *phba = data; | |
464 | char *str = buf; | |
465 | int rc; | |
466 | ||
467 | switch (type) { | |
468 | case ISCSI_BOOT_ETH_FLAGS: | |
f457a46f | 469 | rc = sprintf(str, "2\n"); |
c7acc5b8 JK |
470 | break; |
471 | case ISCSI_BOOT_ETH_INDEX: | |
f457a46f | 472 | rc = sprintf(str, "0\n"); |
c7acc5b8 JK |
473 | break; |
474 | case ISCSI_BOOT_ETH_MAC: | |
0e43895e MC |
475 | rc = beiscsi_get_macaddr(str, phba); |
476 | break; | |
c7acc5b8 JK |
477 | default: |
478 | rc = -ENOSYS; | |
479 | break; | |
480 | } | |
481 | return rc; | |
482 | } | |
483 | ||
484 | ||
587a1f16 | 485 | static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type) |
c7acc5b8 | 486 | { |
587a1f16 | 487 | umode_t rc; |
c7acc5b8 JK |
488 | |
489 | switch (type) { | |
490 | case ISCSI_BOOT_TGT_NAME: | |
491 | case ISCSI_BOOT_TGT_IP_ADDR: | |
492 | case ISCSI_BOOT_TGT_PORT: | |
493 | case ISCSI_BOOT_TGT_CHAP_NAME: | |
494 | case ISCSI_BOOT_TGT_CHAP_SECRET: | |
495 | case ISCSI_BOOT_TGT_REV_CHAP_NAME: | |
496 | case ISCSI_BOOT_TGT_REV_CHAP_SECRET: | |
497 | case ISCSI_BOOT_TGT_NIC_ASSOC: | |
498 | case ISCSI_BOOT_TGT_FLAGS: | |
499 | rc = S_IRUGO; | |
500 | break; | |
501 | default: | |
502 | rc = 0; | |
503 | break; | |
504 | } | |
505 | return rc; | |
506 | } | |
507 | ||
587a1f16 | 508 | static umode_t beiscsi_ini_get_attr_visibility(void *data, int type) |
c7acc5b8 | 509 | { |
587a1f16 | 510 | umode_t rc; |
c7acc5b8 JK |
511 | |
512 | switch (type) { | |
513 | case ISCSI_BOOT_INI_INITIATOR_NAME: | |
514 | rc = S_IRUGO; | |
515 | break; | |
516 | default: | |
517 | rc = 0; | |
518 | break; | |
519 | } | |
520 | return rc; | |
521 | } | |
522 | ||
523 | ||
587a1f16 | 524 | static umode_t beiscsi_eth_get_attr_visibility(void *data, int type) |
c7acc5b8 | 525 | { |
587a1f16 | 526 | umode_t rc; |
c7acc5b8 JK |
527 | |
528 | switch (type) { | |
529 | case ISCSI_BOOT_ETH_FLAGS: | |
530 | case ISCSI_BOOT_ETH_MAC: | |
531 | case ISCSI_BOOT_ETH_INDEX: | |
532 | rc = S_IRUGO; | |
533 | break; | |
534 | default: | |
535 | rc = 0; | |
536 | break; | |
537 | } | |
538 | return rc; | |
539 | } | |
540 | ||
bfead3b2 | 541 | /*------------------- PCI Driver operations and data ----------------- */ |
9baa3c34 | 542 | static const struct pci_device_id beiscsi_pci_id_table[] = { |
bfead3b2 | 543 | { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) }, |
f98c96b0 | 544 | { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) }, |
bfead3b2 JK |
545 | { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) }, |
546 | { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) }, | |
547 | { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) }, | |
139a1b1e | 548 | { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) }, |
bfead3b2 JK |
549 | { 0 } |
550 | }; | |
551 | MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table); | |
552 | ||
99bc5d55 | 553 | |
6733b39a JK |
554 | static struct scsi_host_template beiscsi_sht = { |
555 | .module = THIS_MODULE, | |
c4f39bda | 556 | .name = "Emulex 10Gbe open-iscsi Initiator Driver", |
6733b39a JK |
557 | .proc_name = DRV_NAME, |
558 | .queuecommand = iscsi_queuecommand, | |
db5ed4df | 559 | .change_queue_depth = scsi_change_queue_depth, |
6733b39a JK |
560 | .slave_configure = beiscsi_slave_configure, |
561 | .target_alloc = iscsi_target_alloc, | |
4183122d JK |
562 | .eh_abort_handler = beiscsi_eh_abort, |
563 | .eh_device_reset_handler = beiscsi_eh_device_reset, | |
309ce156 | 564 | .eh_target_reset_handler = iscsi_eh_session_reset, |
99bc5d55 | 565 | .shost_attrs = beiscsi_attrs, |
6733b39a JK |
566 | .sg_tablesize = BEISCSI_SGLIST_ELEMENTS, |
567 | .can_queue = BE2_IO_DEPTH, | |
568 | .this_id = -1, | |
569 | .max_sectors = BEISCSI_MAX_SECTORS, | |
570 | .cmd_per_lun = BEISCSI_CMD_PER_LUN, | |
571 | .use_clustering = ENABLE_CLUSTERING, | |
ffce3e2e | 572 | .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID, |
c40ecc12 | 573 | .track_queue_depth = 1, |
6733b39a | 574 | }; |
6733b39a | 575 | |
bfead3b2 | 576 | static struct scsi_transport_template *beiscsi_scsi_transport; |
6733b39a JK |
577 | |
578 | static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev) | |
579 | { | |
580 | struct beiscsi_hba *phba; | |
581 | struct Scsi_Host *shost; | |
582 | ||
583 | shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0); | |
584 | if (!shost) { | |
99bc5d55 JSJ |
585 | dev_err(&pcidev->dev, |
586 | "beiscsi_hba_alloc - iscsi_host_alloc failed\n"); | |
6733b39a JK |
587 | return NULL; |
588 | } | |
6733b39a JK |
589 | shost->max_id = BE2_MAX_SESSIONS; |
590 | shost->max_channel = 0; | |
591 | shost->max_cmd_len = BEISCSI_MAX_CMD_LEN; | |
592 | shost->max_lun = BEISCSI_NUM_MAX_LUN; | |
593 | shost->transportt = beiscsi_scsi_transport; | |
6733b39a JK |
594 | phba = iscsi_host_priv(shost); |
595 | memset(phba, 0, sizeof(*phba)); | |
596 | phba->shost = shost; | |
597 | phba->pcidev = pci_dev_get(pcidev); | |
2807afb7 | 598 | pci_set_drvdata(pcidev, phba); |
0e43895e | 599 | phba->interface_handle = 0xFFFFFFFF; |
6733b39a | 600 | |
6733b39a | 601 | return phba; |
6733b39a JK |
602 | } |
603 | ||
604 | static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba) | |
605 | { | |
606 | if (phba->csr_va) { | |
607 | iounmap(phba->csr_va); | |
608 | phba->csr_va = NULL; | |
609 | } | |
610 | if (phba->db_va) { | |
611 | iounmap(phba->db_va); | |
612 | phba->db_va = NULL; | |
613 | } | |
614 | if (phba->pci_va) { | |
615 | iounmap(phba->pci_va); | |
616 | phba->pci_va = NULL; | |
617 | } | |
618 | } | |
619 | ||
620 | static int beiscsi_map_pci_bars(struct beiscsi_hba *phba, | |
621 | struct pci_dev *pcidev) | |
622 | { | |
623 | u8 __iomem *addr; | |
f98c96b0 | 624 | int pcicfg_reg; |
6733b39a JK |
625 | |
626 | addr = ioremap_nocache(pci_resource_start(pcidev, 2), | |
627 | pci_resource_len(pcidev, 2)); | |
628 | if (addr == NULL) | |
629 | return -ENOMEM; | |
630 | phba->ctrl.csr = addr; | |
631 | phba->csr_va = addr; | |
632 | phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2); | |
633 | ||
634 | addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024); | |
635 | if (addr == NULL) | |
636 | goto pci_map_err; | |
637 | phba->ctrl.db = addr; | |
638 | phba->db_va = addr; | |
639 | phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4); | |
640 | ||
f98c96b0 JK |
641 | if (phba->generation == BE_GEN2) |
642 | pcicfg_reg = 1; | |
643 | else | |
644 | pcicfg_reg = 0; | |
645 | ||
646 | addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg), | |
647 | pci_resource_len(pcidev, pcicfg_reg)); | |
648 | ||
6733b39a JK |
649 | if (addr == NULL) |
650 | goto pci_map_err; | |
651 | phba->ctrl.pcicfg = addr; | |
652 | phba->pci_va = addr; | |
f98c96b0 | 653 | phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg); |
6733b39a JK |
654 | return 0; |
655 | ||
656 | pci_map_err: | |
657 | beiscsi_unmap_pci_function(phba); | |
658 | return -ENOMEM; | |
659 | } | |
660 | ||
661 | static int beiscsi_enable_pci(struct pci_dev *pcidev) | |
662 | { | |
663 | int ret; | |
664 | ||
665 | ret = pci_enable_device(pcidev); | |
666 | if (ret) { | |
99bc5d55 JSJ |
667 | dev_err(&pcidev->dev, |
668 | "beiscsi_enable_pci - enable device failed\n"); | |
6733b39a JK |
669 | return ret; |
670 | } | |
671 | ||
e307f3ac JSJ |
672 | ret = pci_request_regions(pcidev, DRV_NAME); |
673 | if (ret) { | |
674 | dev_err(&pcidev->dev, | |
675 | "beiscsi_enable_pci - request region failed\n"); | |
676 | goto pci_dev_disable; | |
677 | } | |
678 | ||
bfead3b2 | 679 | pci_set_master(pcidev); |
6c57625b JK |
680 | ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(64)); |
681 | if (ret) { | |
682 | ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32)); | |
683 | if (ret) { | |
684 | dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n"); | |
e307f3ac | 685 | goto pci_region_release; |
6c57625b JK |
686 | } else { |
687 | ret = pci_set_consistent_dma_mask(pcidev, | |
688 | DMA_BIT_MASK(32)); | |
689 | } | |
690 | } else { | |
691 | ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64)); | |
6733b39a JK |
692 | if (ret) { |
693 | dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n"); | |
e307f3ac | 694 | goto pci_region_release; |
6733b39a JK |
695 | } |
696 | } | |
697 | return 0; | |
e307f3ac JSJ |
698 | |
699 | pci_region_release: | |
700 | pci_release_regions(pcidev); | |
701 | pci_dev_disable: | |
702 | pci_disable_device(pcidev); | |
703 | ||
704 | return ret; | |
6733b39a JK |
705 | } |
706 | ||
707 | static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev) | |
708 | { | |
709 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
710 | struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced; | |
711 | struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem; | |
712 | int status = 0; | |
713 | ||
714 | ctrl->pdev = pdev; | |
715 | status = beiscsi_map_pci_bars(phba, pdev); | |
716 | if (status) | |
717 | return status; | |
6733b39a JK |
718 | mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16; |
719 | mbox_mem_alloc->va = pci_alloc_consistent(pdev, | |
720 | mbox_mem_alloc->size, | |
721 | &mbox_mem_alloc->dma); | |
722 | if (!mbox_mem_alloc->va) { | |
723 | beiscsi_unmap_pci_function(phba); | |
a49e06d5 | 724 | return -ENOMEM; |
6733b39a JK |
725 | } |
726 | ||
727 | mbox_mem_align->size = sizeof(struct be_mcc_mailbox); | |
728 | mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16); | |
729 | mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16); | |
730 | memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox)); | |
c03a50f7 | 731 | mutex_init(&ctrl->mbox_lock); |
bfead3b2 | 732 | spin_lock_init(&phba->ctrl.mcc_lock); |
bfead3b2 | 733 | |
6733b39a JK |
734 | return status; |
735 | } | |
736 | ||
843ae752 JK |
737 | /** |
738 | * beiscsi_get_params()- Set the config paramters | |
739 | * @phba: ptr device priv structure | |
740 | **/ | |
6733b39a JK |
741 | static void beiscsi_get_params(struct beiscsi_hba *phba) |
742 | { | |
843ae752 JK |
743 | uint32_t total_cid_count = 0; |
744 | uint32_t total_icd_count = 0; | |
745 | uint8_t ulp_num = 0; | |
746 | ||
747 | total_cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) + | |
748 | BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1); | |
749 | ||
cf987b79 JK |
750 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
751 | uint32_t align_mask = 0; | |
752 | uint32_t icd_post_per_page = 0; | |
753 | uint32_t icd_count_unavailable = 0; | |
754 | uint32_t icd_start = 0, icd_count = 0; | |
755 | uint32_t icd_start_align = 0, icd_count_align = 0; | |
756 | ||
843ae752 | 757 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { |
cf987b79 JK |
758 | icd_start = phba->fw_config.iscsi_icd_start[ulp_num]; |
759 | icd_count = phba->fw_config.iscsi_icd_count[ulp_num]; | |
760 | ||
761 | /* Get ICD count that can be posted on each page */ | |
762 | icd_post_per_page = (PAGE_SIZE / (BE2_SGE * | |
763 | sizeof(struct iscsi_sge))); | |
764 | align_mask = (icd_post_per_page - 1); | |
765 | ||
766 | /* Check if icd_start is aligned ICD per page posting */ | |
767 | if (icd_start % icd_post_per_page) { | |
768 | icd_start_align = ((icd_start + | |
769 | icd_post_per_page) & | |
770 | ~(align_mask)); | |
771 | phba->fw_config. | |
772 | iscsi_icd_start[ulp_num] = | |
773 | icd_start_align; | |
774 | } | |
775 | ||
776 | icd_count_align = (icd_count & ~align_mask); | |
777 | ||
778 | /* ICD discarded in the process of alignment */ | |
779 | if (icd_start_align) | |
780 | icd_count_unavailable = ((icd_start_align - | |
781 | icd_start) + | |
782 | (icd_count - | |
783 | icd_count_align)); | |
784 | ||
785 | /* Updated ICD count available */ | |
786 | phba->fw_config.iscsi_icd_count[ulp_num] = (icd_count - | |
787 | icd_count_unavailable); | |
788 | ||
789 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
790 | "BM_%d : Aligned ICD values\n" | |
791 | "\t ICD Start : %d\n" | |
792 | "\t ICD Count : %d\n" | |
793 | "\t ICD Discarded : %d\n", | |
794 | phba->fw_config. | |
795 | iscsi_icd_start[ulp_num], | |
796 | phba->fw_config. | |
797 | iscsi_icd_count[ulp_num], | |
798 | icd_count_unavailable); | |
843ae752 JK |
799 | break; |
800 | } | |
cf987b79 | 801 | } |
843ae752 | 802 | |
cf987b79 | 803 | total_icd_count = phba->fw_config.iscsi_icd_count[ulp_num]; |
843ae752 JK |
804 | phba->params.ios_per_ctrl = (total_icd_count - |
805 | (total_cid_count + | |
806 | BE2_TMFS + BE2_NOPOUT_REQ)); | |
807 | phba->params.cxns_per_ctrl = total_cid_count; | |
808 | phba->params.asyncpdus_per_ctrl = total_cid_count; | |
809 | phba->params.icds_per_ctrl = total_icd_count; | |
6733b39a JK |
810 | phba->params.num_sge_per_io = BE2_SGE; |
811 | phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ; | |
812 | phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ; | |
813 | phba->params.eq_timer = 64; | |
843ae752 JK |
814 | phba->params.num_eq_entries = 1024; |
815 | phba->params.num_cq_entries = 1024; | |
6733b39a JK |
816 | phba->params.wrbs_per_cxn = 256; |
817 | } | |
818 | ||
819 | static void hwi_ring_eq_db(struct beiscsi_hba *phba, | |
820 | unsigned int id, unsigned int clr_interrupt, | |
821 | unsigned int num_processed, | |
822 | unsigned char rearm, unsigned char event) | |
823 | { | |
824 | u32 val = 0; | |
e08b3c8b | 825 | |
6733b39a JK |
826 | if (rearm) |
827 | val |= 1 << DB_EQ_REARM_SHIFT; | |
828 | if (clr_interrupt) | |
829 | val |= 1 << DB_EQ_CLR_SHIFT; | |
830 | if (event) | |
831 | val |= 1 << DB_EQ_EVNT_SHIFT; | |
e08b3c8b | 832 | |
6733b39a | 833 | val |= num_processed << DB_EQ_NUM_POPPED_SHIFT; |
e08b3c8b JK |
834 | /* Setting lower order EQ_ID Bits */ |
835 | val |= (id & DB_EQ_RING_ID_LOW_MASK); | |
836 | ||
837 | /* Setting Higher order EQ_ID Bits */ | |
838 | val |= (((id >> DB_EQ_HIGH_FEILD_SHIFT) & | |
839 | DB_EQ_RING_ID_HIGH_MASK) | |
840 | << DB_EQ_HIGH_SET_SHIFT); | |
841 | ||
6733b39a JK |
842 | iowrite32(val, phba->db_va + DB_EQ_OFFSET); |
843 | } | |
844 | ||
bfead3b2 JK |
845 | /** |
846 | * be_isr_mcc - The isr routine of the driver. | |
847 | * @irq: Not used | |
848 | * @dev_id: Pointer to host adapter structure | |
849 | */ | |
850 | static irqreturn_t be_isr_mcc(int irq, void *dev_id) | |
851 | { | |
852 | struct beiscsi_hba *phba; | |
853 | struct be_eq_entry *eqe = NULL; | |
854 | struct be_queue_info *eq; | |
855 | struct be_queue_info *mcc; | |
856 | unsigned int num_eq_processed; | |
857 | struct be_eq_obj *pbe_eq; | |
858 | unsigned long flags; | |
859 | ||
860 | pbe_eq = dev_id; | |
861 | eq = &pbe_eq->q; | |
862 | phba = pbe_eq->phba; | |
863 | mcc = &phba->ctrl.mcc_obj.cq; | |
864 | eqe = queue_tail_node(eq); | |
bfead3b2 JK |
865 | |
866 | num_eq_processed = 0; | |
867 | ||
868 | while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] | |
869 | & EQE_VALID_MASK) { | |
870 | if (((eqe->dw[offsetof(struct amap_eq_entry, | |
871 | resource_id) / 32] & | |
872 | EQE_RESID_MASK) >> 16) == mcc->id) { | |
873 | spin_lock_irqsave(&phba->isr_lock, flags); | |
72fb46a9 | 874 | pbe_eq->todo_mcc_cq = true; |
bfead3b2 JK |
875 | spin_unlock_irqrestore(&phba->isr_lock, flags); |
876 | } | |
877 | AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); | |
878 | queue_tail_inc(eq); | |
879 | eqe = queue_tail_node(eq); | |
880 | num_eq_processed++; | |
881 | } | |
72fb46a9 JSJ |
882 | if (pbe_eq->todo_mcc_cq) |
883 | queue_work(phba->wq, &pbe_eq->work_cqs); | |
bfead3b2 JK |
884 | if (num_eq_processed) |
885 | hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1); | |
886 | ||
887 | return IRQ_HANDLED; | |
888 | } | |
889 | ||
890 | /** | |
891 | * be_isr_msix - The isr routine of the driver. | |
892 | * @irq: Not used | |
893 | * @dev_id: Pointer to host adapter structure | |
894 | */ | |
895 | static irqreturn_t be_isr_msix(int irq, void *dev_id) | |
896 | { | |
897 | struct beiscsi_hba *phba; | |
bfead3b2 | 898 | struct be_queue_info *eq; |
bfead3b2 | 899 | struct be_eq_obj *pbe_eq; |
bfead3b2 JK |
900 | |
901 | pbe_eq = dev_id; | |
902 | eq = &pbe_eq->q; | |
bfead3b2 JK |
903 | |
904 | phba = pbe_eq->phba; | |
bfead3b2 | 905 | |
1094cf68 JB |
906 | /* disable interrupt till iopoll completes */ |
907 | hwi_ring_eq_db(phba, eq->id, 1, 0, 0, 1); | |
908 | irq_poll_sched(&pbe_eq->iopoll); | |
72fb46a9 JSJ |
909 | |
910 | return IRQ_HANDLED; | |
bfead3b2 JK |
911 | } |
912 | ||
6733b39a JK |
913 | /** |
914 | * be_isr - The isr routine of the driver. | |
915 | * @irq: Not used | |
916 | * @dev_id: Pointer to host adapter structure | |
917 | */ | |
918 | static irqreturn_t be_isr(int irq, void *dev_id) | |
919 | { | |
920 | struct beiscsi_hba *phba; | |
921 | struct hwi_controller *phwi_ctrlr; | |
922 | struct hwi_context_memory *phwi_context; | |
923 | struct be_eq_entry *eqe = NULL; | |
924 | struct be_queue_info *eq; | |
bfead3b2 | 925 | struct be_queue_info *mcc; |
6733b39a | 926 | unsigned long flags, index; |
bfead3b2 | 927 | unsigned int num_mcceq_processed, num_ioeq_processed; |
6733b39a | 928 | struct be_ctrl_info *ctrl; |
bfead3b2 | 929 | struct be_eq_obj *pbe_eq; |
6733b39a JK |
930 | int isr; |
931 | ||
932 | phba = dev_id; | |
6eab04a8 | 933 | ctrl = &phba->ctrl; |
bfead3b2 JK |
934 | isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET + |
935 | (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE)); | |
936 | if (!isr) | |
937 | return IRQ_NONE; | |
6733b39a JK |
938 | |
939 | phwi_ctrlr = phba->phwi_ctrlr; | |
940 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
bfead3b2 JK |
941 | pbe_eq = &phwi_context->be_eq[0]; |
942 | ||
943 | eq = &phwi_context->be_eq[0].q; | |
944 | mcc = &phba->ctrl.mcc_obj.cq; | |
6733b39a JK |
945 | index = 0; |
946 | eqe = queue_tail_node(eq); | |
6733b39a | 947 | |
bfead3b2 JK |
948 | num_ioeq_processed = 0; |
949 | num_mcceq_processed = 0; | |
89f8b33c JA |
950 | while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] |
951 | & EQE_VALID_MASK) { | |
952 | if (((eqe->dw[offsetof(struct amap_eq_entry, | |
953 | resource_id) / 32] & | |
954 | EQE_RESID_MASK) >> 16) == mcc->id) { | |
955 | spin_lock_irqsave(&phba->isr_lock, flags); | |
956 | pbe_eq->todo_mcc_cq = true; | |
957 | spin_unlock_irqrestore(&phba->isr_lock, flags); | |
958 | num_mcceq_processed++; | |
959 | } else { | |
ea51190c | 960 | irq_poll_sched(&pbe_eq->iopoll); |
bfead3b2 | 961 | num_ioeq_processed++; |
6733b39a | 962 | } |
89f8b33c JA |
963 | AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); |
964 | queue_tail_inc(eq); | |
965 | eqe = queue_tail_node(eq); | |
966 | } | |
967 | if (num_ioeq_processed || num_mcceq_processed) { | |
968 | if (pbe_eq->todo_mcc_cq) | |
72fb46a9 | 969 | queue_work(phba->wq, &pbe_eq->work_cqs); |
6733b39a | 970 | |
89f8b33c | 971 | if ((num_mcceq_processed) && (!num_ioeq_processed)) |
bfead3b2 | 972 | hwi_ring_eq_db(phba, eq->id, 0, |
89f8b33c JA |
973 | (num_ioeq_processed + |
974 | num_mcceq_processed) , 1, 1); | |
975 | else | |
976 | hwi_ring_eq_db(phba, eq->id, 0, | |
977 | (num_ioeq_processed + | |
978 | num_mcceq_processed), 0, 1); | |
979 | ||
980 | return IRQ_HANDLED; | |
981 | } else | |
982 | return IRQ_NONE; | |
6733b39a JK |
983 | } |
984 | ||
1094cf68 | 985 | |
6733b39a JK |
986 | static int beiscsi_init_irqs(struct beiscsi_hba *phba) |
987 | { | |
988 | struct pci_dev *pcidev = phba->pcidev; | |
bfead3b2 JK |
989 | struct hwi_controller *phwi_ctrlr; |
990 | struct hwi_context_memory *phwi_context; | |
4f5af07e | 991 | int ret, msix_vec, i, j; |
6733b39a | 992 | |
bfead3b2 JK |
993 | phwi_ctrlr = phba->phwi_ctrlr; |
994 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
995 | ||
996 | if (phba->msix_enabled) { | |
997 | for (i = 0; i < phba->num_cpus; i++) { | |
8fcfb210 JK |
998 | phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, |
999 | GFP_KERNEL); | |
1000 | if (!phba->msi_name[i]) { | |
1001 | ret = -ENOMEM; | |
1002 | goto free_msix_irqs; | |
1003 | } | |
1004 | ||
1005 | sprintf(phba->msi_name[i], "beiscsi_%02x_%02x", | |
1006 | phba->shost->host_no, i); | |
bfead3b2 | 1007 | msix_vec = phba->msix_entries[i].vector; |
8fcfb210 JK |
1008 | ret = request_irq(msix_vec, be_isr_msix, 0, |
1009 | phba->msi_name[i], | |
bfead3b2 | 1010 | &phwi_context->be_eq[i]); |
4f5af07e | 1011 | if (ret) { |
99bc5d55 JSJ |
1012 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
1013 | "BM_%d : beiscsi_init_irqs-Failed to" | |
1014 | "register msix for i = %d\n", | |
1015 | i); | |
8fcfb210 | 1016 | kfree(phba->msi_name[i]); |
4f5af07e JK |
1017 | goto free_msix_irqs; |
1018 | } | |
bfead3b2 | 1019 | } |
8fcfb210 JK |
1020 | phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL); |
1021 | if (!phba->msi_name[i]) { | |
1022 | ret = -ENOMEM; | |
1023 | goto free_msix_irqs; | |
1024 | } | |
1025 | sprintf(phba->msi_name[i], "beiscsi_mcc_%02x", | |
1026 | phba->shost->host_no); | |
bfead3b2 | 1027 | msix_vec = phba->msix_entries[i].vector; |
8fcfb210 | 1028 | ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i], |
bfead3b2 | 1029 | &phwi_context->be_eq[i]); |
4f5af07e | 1030 | if (ret) { |
99bc5d55 JSJ |
1031 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT , |
1032 | "BM_%d : beiscsi_init_irqs-" | |
1033 | "Failed to register beiscsi_msix_mcc\n"); | |
8fcfb210 | 1034 | kfree(phba->msi_name[i]); |
4f5af07e JK |
1035 | goto free_msix_irqs; |
1036 | } | |
1037 | ||
bfead3b2 JK |
1038 | } else { |
1039 | ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED, | |
1040 | "beiscsi", phba); | |
1041 | if (ret) { | |
99bc5d55 JSJ |
1042 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
1043 | "BM_%d : beiscsi_init_irqs-" | |
1044 | "Failed to register irq\\n"); | |
bfead3b2 JK |
1045 | return ret; |
1046 | } | |
6733b39a JK |
1047 | } |
1048 | return 0; | |
4f5af07e | 1049 | free_msix_irqs: |
8fcfb210 JK |
1050 | for (j = i - 1; j >= 0; j--) { |
1051 | kfree(phba->msi_name[j]); | |
1052 | msix_vec = phba->msix_entries[j].vector; | |
4f5af07e | 1053 | free_irq(msix_vec, &phwi_context->be_eq[j]); |
8fcfb210 | 1054 | } |
4f5af07e | 1055 | return ret; |
6733b39a JK |
1056 | } |
1057 | ||
e08b3c8b | 1058 | void hwi_ring_cq_db(struct beiscsi_hba *phba, |
6733b39a | 1059 | unsigned int id, unsigned int num_processed, |
1094cf68 | 1060 | unsigned char rearm) |
6733b39a JK |
1061 | { |
1062 | u32 val = 0; | |
e08b3c8b | 1063 | |
6733b39a JK |
1064 | if (rearm) |
1065 | val |= 1 << DB_CQ_REARM_SHIFT; | |
e08b3c8b | 1066 | |
6733b39a | 1067 | val |= num_processed << DB_CQ_NUM_POPPED_SHIFT; |
e08b3c8b JK |
1068 | |
1069 | /* Setting lower order CQ_ID Bits */ | |
1070 | val |= (id & DB_CQ_RING_ID_LOW_MASK); | |
1071 | ||
1072 | /* Setting Higher order CQ_ID Bits */ | |
1073 | val |= (((id >> DB_CQ_HIGH_FEILD_SHIFT) & | |
1074 | DB_CQ_RING_ID_HIGH_MASK) | |
1075 | << DB_CQ_HIGH_SET_SHIFT); | |
1076 | ||
6733b39a JK |
1077 | iowrite32(val, phba->db_va + DB_CQ_OFFSET); |
1078 | } | |
1079 | ||
6733b39a JK |
1080 | static unsigned int |
1081 | beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn, | |
1082 | struct beiscsi_hba *phba, | |
6733b39a JK |
1083 | struct pdu_base *ppdu, |
1084 | unsigned long pdu_len, | |
1085 | void *pbuffer, unsigned long buf_len) | |
1086 | { | |
1087 | struct iscsi_conn *conn = beiscsi_conn->conn; | |
1088 | struct iscsi_session *session = conn->session; | |
bfead3b2 JK |
1089 | struct iscsi_task *task; |
1090 | struct beiscsi_io_task *io_task; | |
1091 | struct iscsi_hdr *login_hdr; | |
6733b39a JK |
1092 | |
1093 | switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] & | |
1094 | PDUBASE_OPCODE_MASK) { | |
1095 | case ISCSI_OP_NOOP_IN: | |
1096 | pbuffer = NULL; | |
1097 | buf_len = 0; | |
1098 | break; | |
1099 | case ISCSI_OP_ASYNC_EVENT: | |
1100 | break; | |
1101 | case ISCSI_OP_REJECT: | |
1102 | WARN_ON(!pbuffer); | |
1103 | WARN_ON(!(buf_len == 48)); | |
99bc5d55 JSJ |
1104 | beiscsi_log(phba, KERN_ERR, |
1105 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
1106 | "BM_%d : In ISCSI_OP_REJECT\n"); | |
6733b39a JK |
1107 | break; |
1108 | case ISCSI_OP_LOGIN_RSP: | |
7bd6e25c | 1109 | case ISCSI_OP_TEXT_RSP: |
bfead3b2 JK |
1110 | task = conn->login_task; |
1111 | io_task = task->dd_data; | |
1112 | login_hdr = (struct iscsi_hdr *)ppdu; | |
1113 | login_hdr->itt = io_task->libiscsi_itt; | |
6733b39a JK |
1114 | break; |
1115 | default: | |
99bc5d55 JSJ |
1116 | beiscsi_log(phba, KERN_WARNING, |
1117 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
1118 | "BM_%d : Unrecognized opcode 0x%x in async msg\n", | |
1119 | (ppdu-> | |
6733b39a | 1120 | dw[offsetof(struct amap_pdu_base, opcode) / 32] |
99bc5d55 | 1121 | & PDUBASE_OPCODE_MASK)); |
6733b39a JK |
1122 | return 1; |
1123 | } | |
1124 | ||
659743b0 | 1125 | spin_lock_bh(&session->back_lock); |
6733b39a | 1126 | __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len); |
659743b0 | 1127 | spin_unlock_bh(&session->back_lock); |
6733b39a JK |
1128 | return 0; |
1129 | } | |
1130 | ||
1131 | static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba) | |
1132 | { | |
1133 | struct sgl_handle *psgl_handle; | |
1134 | ||
10139fe0 | 1135 | spin_lock_bh(&phba->io_sgl_lock); |
6733b39a | 1136 | if (phba->io_sgl_hndl_avbl) { |
99bc5d55 JSJ |
1137 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, |
1138 | "BM_%d : In alloc_io_sgl_handle," | |
1139 | " io_sgl_alloc_index=%d\n", | |
1140 | phba->io_sgl_alloc_index); | |
1141 | ||
6733b39a JK |
1142 | psgl_handle = phba->io_sgl_hndl_base[phba-> |
1143 | io_sgl_alloc_index]; | |
1144 | phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL; | |
1145 | phba->io_sgl_hndl_avbl--; | |
bfead3b2 JK |
1146 | if (phba->io_sgl_alloc_index == (phba->params. |
1147 | ios_per_ctrl - 1)) | |
6733b39a JK |
1148 | phba->io_sgl_alloc_index = 0; |
1149 | else | |
1150 | phba->io_sgl_alloc_index++; | |
1151 | } else | |
1152 | psgl_handle = NULL; | |
10139fe0 | 1153 | spin_unlock_bh(&phba->io_sgl_lock); |
6733b39a JK |
1154 | return psgl_handle; |
1155 | } | |
1156 | ||
1157 | static void | |
1158 | free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle) | |
1159 | { | |
10139fe0 | 1160 | spin_lock_bh(&phba->io_sgl_lock); |
99bc5d55 JSJ |
1161 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, |
1162 | "BM_%d : In free_,io_sgl_free_index=%d\n", | |
1163 | phba->io_sgl_free_index); | |
1164 | ||
6733b39a JK |
1165 | if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) { |
1166 | /* | |
1167 | * this can happen if clean_task is called on a task that | |
1168 | * failed in xmit_task or alloc_pdu. | |
1169 | */ | |
99bc5d55 JSJ |
1170 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO, |
1171 | "BM_%d : Double Free in IO SGL io_sgl_free_index=%d," | |
1172 | "value there=%p\n", phba->io_sgl_free_index, | |
1173 | phba->io_sgl_hndl_base | |
1174 | [phba->io_sgl_free_index]); | |
10139fe0 | 1175 | spin_unlock_bh(&phba->io_sgl_lock); |
6733b39a JK |
1176 | return; |
1177 | } | |
1178 | phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle; | |
1179 | phba->io_sgl_hndl_avbl++; | |
1180 | if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1)) | |
1181 | phba->io_sgl_free_index = 0; | |
1182 | else | |
1183 | phba->io_sgl_free_index++; | |
10139fe0 | 1184 | spin_unlock_bh(&phba->io_sgl_lock); |
6733b39a JK |
1185 | } |
1186 | ||
cb564c6b JB |
1187 | static inline struct wrb_handle * |
1188 | beiscsi_get_wrb_handle(struct hwi_wrb_context *pwrb_context, | |
1189 | unsigned int wrbs_per_cxn) | |
1190 | { | |
1191 | struct wrb_handle *pwrb_handle; | |
1192 | ||
f64d92e6 | 1193 | spin_lock_bh(&pwrb_context->wrb_lock); |
cb564c6b JB |
1194 | pwrb_handle = pwrb_context->pwrb_handle_base[pwrb_context->alloc_index]; |
1195 | pwrb_context->wrb_handles_available--; | |
1196 | if (pwrb_context->alloc_index == (wrbs_per_cxn - 1)) | |
1197 | pwrb_context->alloc_index = 0; | |
1198 | else | |
1199 | pwrb_context->alloc_index++; | |
f64d92e6 | 1200 | spin_unlock_bh(&pwrb_context->wrb_lock); |
cb564c6b JB |
1201 | |
1202 | return pwrb_handle; | |
1203 | } | |
1204 | ||
6733b39a JK |
1205 | /** |
1206 | * alloc_wrb_handle - To allocate a wrb handle | |
1207 | * @phba: The hba pointer | |
1208 | * @cid: The cid to use for allocation | |
340c99e9 | 1209 | * @pwrb_context: ptr to ptr to wrb context |
6733b39a JK |
1210 | * |
1211 | * This happens under session_lock until submission to chip | |
1212 | */ | |
340c99e9 | 1213 | struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid, |
cb564c6b | 1214 | struct hwi_wrb_context **pcontext) |
6733b39a JK |
1215 | { |
1216 | struct hwi_wrb_context *pwrb_context; | |
1217 | struct hwi_controller *phwi_ctrlr; | |
a7909b39 | 1218 | uint16_t cri_index = BE_GET_CRI_FROM_CID(cid); |
6733b39a JK |
1219 | |
1220 | phwi_ctrlr = phba->phwi_ctrlr; | |
a7909b39 | 1221 | pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; |
cb564c6b JB |
1222 | /* return the context address */ |
1223 | *pcontext = pwrb_context; | |
1224 | return beiscsi_get_wrb_handle(pwrb_context, phba->params.wrbs_per_cxn); | |
1225 | } | |
340c99e9 | 1226 | |
cb564c6b JB |
1227 | static inline void |
1228 | beiscsi_put_wrb_handle(struct hwi_wrb_context *pwrb_context, | |
1229 | struct wrb_handle *pwrb_handle, | |
1230 | unsigned int wrbs_per_cxn) | |
1231 | { | |
f64d92e6 | 1232 | spin_lock_bh(&pwrb_context->wrb_lock); |
cb564c6b JB |
1233 | pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle; |
1234 | pwrb_context->wrb_handles_available++; | |
1235 | if (pwrb_context->free_index == (wrbs_per_cxn - 1)) | |
1236 | pwrb_context->free_index = 0; | |
1237 | else | |
1238 | pwrb_context->free_index++; | |
f64d92e6 | 1239 | spin_unlock_bh(&pwrb_context->wrb_lock); |
6733b39a JK |
1240 | } |
1241 | ||
1242 | /** | |
1243 | * free_wrb_handle - To free the wrb handle back to pool | |
1244 | * @phba: The hba pointer | |
1245 | * @pwrb_context: The context to free from | |
1246 | * @pwrb_handle: The wrb_handle to free | |
1247 | * | |
1248 | * This happens under session_lock until submission to chip | |
1249 | */ | |
1250 | static void | |
1251 | free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context, | |
1252 | struct wrb_handle *pwrb_handle) | |
1253 | { | |
cb564c6b JB |
1254 | beiscsi_put_wrb_handle(pwrb_context, |
1255 | pwrb_handle, | |
1256 | phba->params.wrbs_per_cxn); | |
99bc5d55 JSJ |
1257 | beiscsi_log(phba, KERN_INFO, |
1258 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
1259 | "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x" | |
1260 | "wrb_handles_available=%d\n", | |
1261 | pwrb_handle, pwrb_context->free_index, | |
1262 | pwrb_context->wrb_handles_available); | |
6733b39a JK |
1263 | } |
1264 | ||
1265 | static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba) | |
1266 | { | |
1267 | struct sgl_handle *psgl_handle; | |
1268 | ||
10139fe0 | 1269 | spin_lock_bh(&phba->mgmt_sgl_lock); |
6733b39a JK |
1270 | if (phba->eh_sgl_hndl_avbl) { |
1271 | psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index]; | |
1272 | phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL; | |
99bc5d55 JSJ |
1273 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG, |
1274 | "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n", | |
1275 | phba->eh_sgl_alloc_index, | |
1276 | phba->eh_sgl_alloc_index); | |
1277 | ||
6733b39a JK |
1278 | phba->eh_sgl_hndl_avbl--; |
1279 | if (phba->eh_sgl_alloc_index == | |
1280 | (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - | |
1281 | 1)) | |
1282 | phba->eh_sgl_alloc_index = 0; | |
1283 | else | |
1284 | phba->eh_sgl_alloc_index++; | |
1285 | } else | |
1286 | psgl_handle = NULL; | |
10139fe0 | 1287 | spin_unlock_bh(&phba->mgmt_sgl_lock); |
6733b39a JK |
1288 | return psgl_handle; |
1289 | } | |
1290 | ||
1291 | void | |
1292 | free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle) | |
1293 | { | |
10139fe0 | 1294 | spin_lock_bh(&phba->mgmt_sgl_lock); |
99bc5d55 JSJ |
1295 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG, |
1296 | "BM_%d : In free_mgmt_sgl_handle," | |
1297 | "eh_sgl_free_index=%d\n", | |
1298 | phba->eh_sgl_free_index); | |
1299 | ||
6733b39a JK |
1300 | if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) { |
1301 | /* | |
1302 | * this can happen if clean_task is called on a task that | |
1303 | * failed in xmit_task or alloc_pdu. | |
1304 | */ | |
99bc5d55 JSJ |
1305 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG, |
1306 | "BM_%d : Double Free in eh SGL ," | |
1307 | "eh_sgl_free_index=%d\n", | |
1308 | phba->eh_sgl_free_index); | |
10139fe0 | 1309 | spin_unlock_bh(&phba->mgmt_sgl_lock); |
6733b39a JK |
1310 | return; |
1311 | } | |
1312 | phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle; | |
1313 | phba->eh_sgl_hndl_avbl++; | |
1314 | if (phba->eh_sgl_free_index == | |
1315 | (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1)) | |
1316 | phba->eh_sgl_free_index = 0; | |
1317 | else | |
1318 | phba->eh_sgl_free_index++; | |
10139fe0 | 1319 | spin_unlock_bh(&phba->mgmt_sgl_lock); |
6733b39a JK |
1320 | } |
1321 | ||
1322 | static void | |
1323 | be_complete_io(struct beiscsi_conn *beiscsi_conn, | |
73133261 JSJ |
1324 | struct iscsi_task *task, |
1325 | struct common_sol_cqe *csol_cqe) | |
6733b39a JK |
1326 | { |
1327 | struct beiscsi_io_task *io_task = task->dd_data; | |
1328 | struct be_status_bhs *sts_bhs = | |
1329 | (struct be_status_bhs *)io_task->cmd_bhs; | |
1330 | struct iscsi_conn *conn = beiscsi_conn->conn; | |
6733b39a JK |
1331 | unsigned char *sense; |
1332 | u32 resid = 0, exp_cmdsn, max_cmdsn; | |
1333 | u8 rsp, status, flags; | |
1334 | ||
73133261 JSJ |
1335 | exp_cmdsn = csol_cqe->exp_cmdsn; |
1336 | max_cmdsn = (csol_cqe->exp_cmdsn + | |
1337 | csol_cqe->cmd_wnd - 1); | |
1338 | rsp = csol_cqe->i_resp; | |
1339 | status = csol_cqe->i_sts; | |
1340 | flags = csol_cqe->i_flags; | |
1341 | resid = csol_cqe->res_cnt; | |
1342 | ||
bd535451 | 1343 | if (!task->sc) { |
da334977 | 1344 | if (io_task->scsi_cmnd) { |
bd535451 | 1345 | scsi_dma_unmap(io_task->scsi_cmnd); |
da334977 JK |
1346 | io_task->scsi_cmnd = NULL; |
1347 | } | |
6733b39a | 1348 | |
bd535451 JK |
1349 | return; |
1350 | } | |
6733b39a JK |
1351 | task->sc->result = (DID_OK << 16) | status; |
1352 | if (rsp != ISCSI_STATUS_CMD_COMPLETED) { | |
1353 | task->sc->result = DID_ERROR << 16; | |
1354 | goto unmap; | |
1355 | } | |
1356 | ||
1357 | /* bidi not initially supported */ | |
1358 | if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) { | |
6733b39a JK |
1359 | if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW)) |
1360 | task->sc->result = DID_ERROR << 16; | |
1361 | ||
1362 | if (flags & ISCSI_FLAG_CMD_UNDERFLOW) { | |
1363 | scsi_set_resid(task->sc, resid); | |
1364 | if (!status && (scsi_bufflen(task->sc) - resid < | |
1365 | task->sc->underflow)) | |
1366 | task->sc->result = DID_ERROR << 16; | |
1367 | } | |
1368 | } | |
1369 | ||
1370 | if (status == SAM_STAT_CHECK_CONDITION) { | |
4053a4be | 1371 | u16 sense_len; |
bfead3b2 | 1372 | unsigned short *slen = (unsigned short *)sts_bhs->sense_info; |
4053a4be | 1373 | |
6733b39a | 1374 | sense = sts_bhs->sense_info + sizeof(unsigned short); |
4053a4be | 1375 | sense_len = be16_to_cpu(*slen); |
6733b39a JK |
1376 | memcpy(task->sc->sense_buffer, sense, |
1377 | min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE)); | |
1378 | } | |
756d29c8 | 1379 | |
73133261 JSJ |
1380 | if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ) |
1381 | conn->rxdata_octets += resid; | |
6733b39a | 1382 | unmap: |
eb1c4692 JSJ |
1383 | if (io_task->scsi_cmnd) { |
1384 | scsi_dma_unmap(io_task->scsi_cmnd); | |
1385 | io_task->scsi_cmnd = NULL; | |
1386 | } | |
6733b39a JK |
1387 | iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn); |
1388 | } | |
1389 | ||
1390 | static void | |
1391 | be_complete_logout(struct beiscsi_conn *beiscsi_conn, | |
73133261 JSJ |
1392 | struct iscsi_task *task, |
1393 | struct common_sol_cqe *csol_cqe) | |
6733b39a JK |
1394 | { |
1395 | struct iscsi_logout_rsp *hdr; | |
bfead3b2 | 1396 | struct beiscsi_io_task *io_task = task->dd_data; |
6733b39a JK |
1397 | struct iscsi_conn *conn = beiscsi_conn->conn; |
1398 | ||
1399 | hdr = (struct iscsi_logout_rsp *)task->hdr; | |
7bd6e25c | 1400 | hdr->opcode = ISCSI_OP_LOGOUT_RSP; |
6733b39a JK |
1401 | hdr->t2wait = 5; |
1402 | hdr->t2retain = 0; | |
73133261 JSJ |
1403 | hdr->flags = csol_cqe->i_flags; |
1404 | hdr->response = csol_cqe->i_resp; | |
702dc5e8 JK |
1405 | hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); |
1406 | hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + | |
1407 | csol_cqe->cmd_wnd - 1); | |
73133261 | 1408 | |
7bd6e25c JK |
1409 | hdr->dlength[0] = 0; |
1410 | hdr->dlength[1] = 0; | |
1411 | hdr->dlength[2] = 0; | |
6733b39a | 1412 | hdr->hlength = 0; |
bfead3b2 | 1413 | hdr->itt = io_task->libiscsi_itt; |
6733b39a JK |
1414 | __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); |
1415 | } | |
1416 | ||
1417 | static void | |
1418 | be_complete_tmf(struct beiscsi_conn *beiscsi_conn, | |
73133261 JSJ |
1419 | struct iscsi_task *task, |
1420 | struct common_sol_cqe *csol_cqe) | |
6733b39a JK |
1421 | { |
1422 | struct iscsi_tm_rsp *hdr; | |
1423 | struct iscsi_conn *conn = beiscsi_conn->conn; | |
bfead3b2 | 1424 | struct beiscsi_io_task *io_task = task->dd_data; |
6733b39a JK |
1425 | |
1426 | hdr = (struct iscsi_tm_rsp *)task->hdr; | |
7bd6e25c | 1427 | hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP; |
73133261 JSJ |
1428 | hdr->flags = csol_cqe->i_flags; |
1429 | hdr->response = csol_cqe->i_resp; | |
702dc5e8 JK |
1430 | hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); |
1431 | hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + | |
1432 | csol_cqe->cmd_wnd - 1); | |
73133261 | 1433 | |
bfead3b2 | 1434 | hdr->itt = io_task->libiscsi_itt; |
6733b39a JK |
1435 | __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); |
1436 | } | |
1437 | ||
1438 | static void | |
1439 | hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn, | |
1440 | struct beiscsi_hba *phba, struct sol_cqe *psol) | |
1441 | { | |
1442 | struct hwi_wrb_context *pwrb_context; | |
bfead3b2 | 1443 | struct wrb_handle *pwrb_handle = NULL; |
6733b39a | 1444 | struct hwi_controller *phwi_ctrlr; |
bfead3b2 JK |
1445 | struct iscsi_task *task; |
1446 | struct beiscsi_io_task *io_task; | |
a7909b39 | 1447 | uint16_t wrb_index, cid, cri_index; |
6733b39a JK |
1448 | |
1449 | phwi_ctrlr = phba->phwi_ctrlr; | |
2c9dfd36 JK |
1450 | if (is_chip_be2_be3r(phba)) { |
1451 | wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe, | |
73133261 | 1452 | wrb_idx, psol); |
2c9dfd36 | 1453 | cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe, |
73133261 JSJ |
1454 | cid, psol); |
1455 | } else { | |
2c9dfd36 | 1456 | wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2, |
73133261 | 1457 | wrb_idx, psol); |
2c9dfd36 | 1458 | cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2, |
73133261 JSJ |
1459 | cid, psol); |
1460 | } | |
1461 | ||
a7909b39 JK |
1462 | cri_index = BE_GET_CRI_FROM_CID(cid); |
1463 | pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; | |
73133261 | 1464 | pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index]; |
32951dd8 | 1465 | task = pwrb_handle->pio_handle; |
35e66019 | 1466 | |
bfead3b2 | 1467 | io_task = task->dd_data; |
4a4a11b9 JK |
1468 | memset(io_task->pwrb_handle->pwrb, 0, sizeof(struct iscsi_wrb)); |
1469 | iscsi_put_task(task); | |
6733b39a JK |
1470 | } |
1471 | ||
1472 | static void | |
1473 | be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn, | |
73133261 JSJ |
1474 | struct iscsi_task *task, |
1475 | struct common_sol_cqe *csol_cqe) | |
6733b39a JK |
1476 | { |
1477 | struct iscsi_nopin *hdr; | |
1478 | struct iscsi_conn *conn = beiscsi_conn->conn; | |
bfead3b2 | 1479 | struct beiscsi_io_task *io_task = task->dd_data; |
6733b39a JK |
1480 | |
1481 | hdr = (struct iscsi_nopin *)task->hdr; | |
73133261 JSJ |
1482 | hdr->flags = csol_cqe->i_flags; |
1483 | hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn); | |
702dc5e8 JK |
1484 | hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn + |
1485 | csol_cqe->cmd_wnd - 1); | |
73133261 | 1486 | |
6733b39a | 1487 | hdr->opcode = ISCSI_OP_NOOP_IN; |
bfead3b2 | 1488 | hdr->itt = io_task->libiscsi_itt; |
6733b39a JK |
1489 | __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0); |
1490 | } | |
1491 | ||
73133261 JSJ |
1492 | static void adapter_get_sol_cqe(struct beiscsi_hba *phba, |
1493 | struct sol_cqe *psol, | |
1494 | struct common_sol_cqe *csol_cqe) | |
1495 | { | |
2c9dfd36 JK |
1496 | if (is_chip_be2_be3r(phba)) { |
1497 | csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe, | |
1498 | i_exp_cmd_sn, psol); | |
1499 | csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe, | |
1500 | i_res_cnt, psol); | |
1501 | csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe, | |
1502 | i_cmd_wnd, psol); | |
1503 | csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe, | |
1504 | wrb_index, psol); | |
1505 | csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe, | |
1506 | cid, psol); | |
1507 | csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe, | |
1508 | hw_sts, psol); | |
1509 | csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe, | |
1510 | i_resp, psol); | |
1511 | csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe, | |
1512 | i_sts, psol); | |
1513 | csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe, | |
1514 | i_flags, psol); | |
1515 | } else { | |
73133261 JSJ |
1516 | csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2, |
1517 | i_exp_cmd_sn, psol); | |
1518 | csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1519 | i_res_cnt, psol); | |
1520 | csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1521 | wrb_index, psol); | |
1522 | csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1523 | cid, psol); | |
1524 | csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1525 | hw_sts, psol); | |
702dc5e8 | 1526 | csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2, |
73133261 JSJ |
1527 | i_cmd_wnd, psol); |
1528 | if (AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1529 | cmd_cmpl, psol)) | |
1530 | csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1531 | i_sts, psol); | |
1532 | else | |
1533 | csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1534 | i_sts, psol); | |
1535 | if (AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1536 | u, psol)) | |
1537 | csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW; | |
1538 | ||
1539 | if (AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
1540 | o, psol)) | |
1541 | csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW; | |
73133261 JSJ |
1542 | } |
1543 | } | |
1544 | ||
1545 | ||
6733b39a JK |
1546 | static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn, |
1547 | struct beiscsi_hba *phba, struct sol_cqe *psol) | |
1548 | { | |
1549 | struct hwi_wrb_context *pwrb_context; | |
1550 | struct wrb_handle *pwrb_handle; | |
1551 | struct iscsi_wrb *pwrb = NULL; | |
1552 | struct hwi_controller *phwi_ctrlr; | |
1553 | struct iscsi_task *task; | |
bfead3b2 | 1554 | unsigned int type; |
6733b39a JK |
1555 | struct iscsi_conn *conn = beiscsi_conn->conn; |
1556 | struct iscsi_session *session = conn->session; | |
73133261 | 1557 | struct common_sol_cqe csol_cqe = {0}; |
a7909b39 | 1558 | uint16_t cri_index = 0; |
6733b39a JK |
1559 | |
1560 | phwi_ctrlr = phba->phwi_ctrlr; | |
73133261 JSJ |
1561 | |
1562 | /* Copy the elements to a common structure */ | |
1563 | adapter_get_sol_cqe(phba, psol, &csol_cqe); | |
1564 | ||
a7909b39 JK |
1565 | cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid); |
1566 | pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; | |
73133261 JSJ |
1567 | |
1568 | pwrb_handle = pwrb_context->pwrb_handle_basestd[ | |
1569 | csol_cqe.wrb_index]; | |
1570 | ||
32951dd8 JK |
1571 | task = pwrb_handle->pio_handle; |
1572 | pwrb = pwrb_handle->pwrb; | |
73133261 | 1573 | type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type; |
32951dd8 | 1574 | |
659743b0 | 1575 | spin_lock_bh(&session->back_lock); |
bfead3b2 | 1576 | switch (type) { |
6733b39a JK |
1577 | case HWH_TYPE_IO: |
1578 | case HWH_TYPE_IO_RD: | |
1579 | if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == | |
dafab8e0 | 1580 | ISCSI_OP_NOOP_OUT) |
73133261 | 1581 | be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe); |
dafab8e0 | 1582 | else |
73133261 | 1583 | be_complete_io(beiscsi_conn, task, &csol_cqe); |
6733b39a JK |
1584 | break; |
1585 | ||
1586 | case HWH_TYPE_LOGOUT: | |
dafab8e0 | 1587 | if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT) |
73133261 | 1588 | be_complete_logout(beiscsi_conn, task, &csol_cqe); |
dafab8e0 | 1589 | else |
73133261 | 1590 | be_complete_tmf(beiscsi_conn, task, &csol_cqe); |
6733b39a JK |
1591 | break; |
1592 | ||
1593 | case HWH_TYPE_LOGIN: | |
99bc5d55 JSJ |
1594 | beiscsi_log(phba, KERN_ERR, |
1595 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
1596 | "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in" | |
1597 | " hwi_complete_cmd- Solicited path\n"); | |
6733b39a JK |
1598 | break; |
1599 | ||
6733b39a | 1600 | case HWH_TYPE_NOP: |
73133261 | 1601 | be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe); |
6733b39a JK |
1602 | break; |
1603 | ||
1604 | default: | |
99bc5d55 JSJ |
1605 | beiscsi_log(phba, KERN_WARNING, |
1606 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
1607 | "BM_%d : In hwi_complete_cmd, unknown type = %d" | |
1608 | "wrb_index 0x%x CID 0x%x\n", type, | |
73133261 JSJ |
1609 | csol_cqe.wrb_index, |
1610 | csol_cqe.cid); | |
6733b39a JK |
1611 | break; |
1612 | } | |
35e66019 | 1613 | |
659743b0 | 1614 | spin_unlock_bh(&session->back_lock); |
6733b39a JK |
1615 | } |
1616 | ||
1617 | static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context | |
1618 | *pasync_ctx, unsigned int is_header, | |
1619 | unsigned int host_write_ptr) | |
1620 | { | |
1621 | if (is_header) | |
1622 | return &pasync_ctx->async_entry[host_write_ptr]. | |
1623 | header_busy_list; | |
1624 | else | |
1625 | return &pasync_ctx->async_entry[host_write_ptr].data_busy_list; | |
1626 | } | |
1627 | ||
1628 | static struct async_pdu_handle * | |
1629 | hwi_get_async_handle(struct beiscsi_hba *phba, | |
1630 | struct beiscsi_conn *beiscsi_conn, | |
1631 | struct hwi_async_pdu_context *pasync_ctx, | |
1632 | struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index) | |
1633 | { | |
1634 | struct be_bus_address phys_addr; | |
1635 | struct list_head *pbusy_list; | |
1636 | struct async_pdu_handle *pasync_handle = NULL; | |
6733b39a | 1637 | unsigned char is_header = 0; |
73133261 JSJ |
1638 | unsigned int index, dpl; |
1639 | ||
2c9dfd36 JK |
1640 | if (is_chip_be2_be3r(phba)) { |
1641 | dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, | |
73133261 | 1642 | dpl, pdpdu_cqe); |
2c9dfd36 | 1643 | index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe, |
73133261 JSJ |
1644 | index, pdpdu_cqe); |
1645 | } else { | |
2c9dfd36 | 1646 | dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2, |
73133261 | 1647 | dpl, pdpdu_cqe); |
2c9dfd36 | 1648 | index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2, |
73133261 JSJ |
1649 | index, pdpdu_cqe); |
1650 | } | |
6733b39a JK |
1651 | |
1652 | phys_addr.u.a32.address_lo = | |
73133261 JSJ |
1653 | (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, |
1654 | db_addr_lo) / 32] - dpl); | |
6733b39a | 1655 | phys_addr.u.a32.address_hi = |
73133261 JSJ |
1656 | pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, |
1657 | db_addr_hi) / 32]; | |
6733b39a JK |
1658 | |
1659 | phys_addr.u.a64.address = | |
1660 | *((unsigned long long *)(&phys_addr.u.a64.address)); | |
1661 | ||
1662 | switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32] | |
1663 | & PDUCQE_CODE_MASK) { | |
1664 | case UNSOL_HDR_NOTIFY: | |
1665 | is_header = 1; | |
1666 | ||
73133261 JSJ |
1667 | pbusy_list = hwi_get_async_busy_list(pasync_ctx, |
1668 | is_header, index); | |
6733b39a JK |
1669 | break; |
1670 | case UNSOL_DATA_NOTIFY: | |
73133261 JSJ |
1671 | pbusy_list = hwi_get_async_busy_list(pasync_ctx, |
1672 | is_header, index); | |
6733b39a JK |
1673 | break; |
1674 | default: | |
1675 | pbusy_list = NULL; | |
99bc5d55 JSJ |
1676 | beiscsi_log(phba, KERN_WARNING, |
1677 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
1678 | "BM_%d : Unexpected code=%d\n", | |
1679 | pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, | |
1680 | code) / 32] & PDUCQE_CODE_MASK); | |
6733b39a JK |
1681 | return NULL; |
1682 | } | |
1683 | ||
6733b39a JK |
1684 | WARN_ON(list_empty(pbusy_list)); |
1685 | list_for_each_entry(pasync_handle, pbusy_list, link) { | |
dc63aac6 | 1686 | if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address) |
6733b39a JK |
1687 | break; |
1688 | } | |
1689 | ||
1690 | WARN_ON(!pasync_handle); | |
1691 | ||
8a86e833 JK |
1692 | pasync_handle->cri = BE_GET_ASYNC_CRI_FROM_CID( |
1693 | beiscsi_conn->beiscsi_conn_cid); | |
6733b39a | 1694 | pasync_handle->is_header = is_header; |
73133261 JSJ |
1695 | pasync_handle->buffer_len = dpl; |
1696 | *pcq_index = index; | |
6733b39a | 1697 | |
6733b39a JK |
1698 | return pasync_handle; |
1699 | } | |
1700 | ||
1701 | static unsigned int | |
99bc5d55 JSJ |
1702 | hwi_update_async_writables(struct beiscsi_hba *phba, |
1703 | struct hwi_async_pdu_context *pasync_ctx, | |
1704 | unsigned int is_header, unsigned int cq_index) | |
6733b39a JK |
1705 | { |
1706 | struct list_head *pbusy_list; | |
1707 | struct async_pdu_handle *pasync_handle; | |
1708 | unsigned int num_entries, writables = 0; | |
1709 | unsigned int *pep_read_ptr, *pwritables; | |
1710 | ||
dc63aac6 | 1711 | num_entries = pasync_ctx->num_entries; |
6733b39a JK |
1712 | if (is_header) { |
1713 | pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr; | |
1714 | pwritables = &pasync_ctx->async_header.writables; | |
6733b39a JK |
1715 | } else { |
1716 | pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr; | |
1717 | pwritables = &pasync_ctx->async_data.writables; | |
6733b39a JK |
1718 | } |
1719 | ||
1720 | while ((*pep_read_ptr) != cq_index) { | |
1721 | (*pep_read_ptr)++; | |
1722 | *pep_read_ptr = (*pep_read_ptr) % num_entries; | |
1723 | ||
1724 | pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header, | |
1725 | *pep_read_ptr); | |
1726 | if (writables == 0) | |
1727 | WARN_ON(list_empty(pbusy_list)); | |
1728 | ||
1729 | if (!list_empty(pbusy_list)) { | |
1730 | pasync_handle = list_entry(pbusy_list->next, | |
1731 | struct async_pdu_handle, | |
1732 | link); | |
1733 | WARN_ON(!pasync_handle); | |
1734 | pasync_handle->consumed = 1; | |
1735 | } | |
1736 | ||
1737 | writables++; | |
1738 | } | |
1739 | ||
1740 | if (!writables) { | |
99bc5d55 JSJ |
1741 | beiscsi_log(phba, KERN_ERR, |
1742 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
1743 | "BM_%d : Duplicate notification received - index 0x%x!!\n", | |
1744 | cq_index); | |
6733b39a JK |
1745 | WARN_ON(1); |
1746 | } | |
1747 | ||
1748 | *pwritables = *pwritables + writables; | |
1749 | return 0; | |
1750 | } | |
1751 | ||
9728d8d0 | 1752 | static void hwi_free_async_msg(struct beiscsi_hba *phba, |
8a86e833 JK |
1753 | struct hwi_async_pdu_context *pasync_ctx, |
1754 | unsigned int cri) | |
6733b39a | 1755 | { |
6733b39a JK |
1756 | struct async_pdu_handle *pasync_handle, *tmp_handle; |
1757 | struct list_head *plist; | |
6733b39a | 1758 | |
6733b39a | 1759 | plist = &pasync_ctx->async_entry[cri].wait_queue.list; |
6733b39a JK |
1760 | list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) { |
1761 | list_del(&pasync_handle->link); | |
1762 | ||
9728d8d0 | 1763 | if (pasync_handle->is_header) { |
6733b39a JK |
1764 | list_add_tail(&pasync_handle->link, |
1765 | &pasync_ctx->async_header.free_list); | |
1766 | pasync_ctx->async_header.free_entries++; | |
6733b39a JK |
1767 | } else { |
1768 | list_add_tail(&pasync_handle->link, | |
1769 | &pasync_ctx->async_data.free_list); | |
1770 | pasync_ctx->async_data.free_entries++; | |
6733b39a JK |
1771 | } |
1772 | } | |
1773 | ||
1774 | INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list); | |
1775 | pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0; | |
1776 | pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0; | |
6733b39a JK |
1777 | } |
1778 | ||
1779 | static struct phys_addr * | |
1780 | hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx, | |
1781 | unsigned int is_header, unsigned int host_write_ptr) | |
1782 | { | |
1783 | struct phys_addr *pasync_sge = NULL; | |
1784 | ||
1785 | if (is_header) | |
1786 | pasync_sge = pasync_ctx->async_header.ring_base; | |
1787 | else | |
1788 | pasync_sge = pasync_ctx->async_data.ring_base; | |
1789 | ||
1790 | return pasync_sge + host_write_ptr; | |
1791 | } | |
1792 | ||
1793 | static void hwi_post_async_buffers(struct beiscsi_hba *phba, | |
8a86e833 | 1794 | unsigned int is_header, uint8_t ulp_num) |
6733b39a JK |
1795 | { |
1796 | struct hwi_controller *phwi_ctrlr; | |
1797 | struct hwi_async_pdu_context *pasync_ctx; | |
1798 | struct async_pdu_handle *pasync_handle; | |
1799 | struct list_head *pfree_link, *pbusy_list; | |
1800 | struct phys_addr *pasync_sge; | |
1801 | unsigned int ring_id, num_entries; | |
8a86e833 | 1802 | unsigned int host_write_num, doorbell_offset; |
6733b39a JK |
1803 | unsigned int writables; |
1804 | unsigned int i = 0; | |
1805 | u32 doorbell = 0; | |
1806 | ||
1807 | phwi_ctrlr = phba->phwi_ctrlr; | |
8a86e833 | 1808 | pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num); |
dc63aac6 | 1809 | num_entries = pasync_ctx->num_entries; |
6733b39a JK |
1810 | |
1811 | if (is_header) { | |
6733b39a JK |
1812 | writables = min(pasync_ctx->async_header.writables, |
1813 | pasync_ctx->async_header.free_entries); | |
1814 | pfree_link = pasync_ctx->async_header.free_list.next; | |
1815 | host_write_num = pasync_ctx->async_header.host_write_ptr; | |
8a86e833 JK |
1816 | ring_id = phwi_ctrlr->default_pdu_hdr[ulp_num].id; |
1817 | doorbell_offset = phwi_ctrlr->default_pdu_hdr[ulp_num]. | |
1818 | doorbell_offset; | |
6733b39a | 1819 | } else { |
6733b39a JK |
1820 | writables = min(pasync_ctx->async_data.writables, |
1821 | pasync_ctx->async_data.free_entries); | |
1822 | pfree_link = pasync_ctx->async_data.free_list.next; | |
1823 | host_write_num = pasync_ctx->async_data.host_write_ptr; | |
8a86e833 JK |
1824 | ring_id = phwi_ctrlr->default_pdu_data[ulp_num].id; |
1825 | doorbell_offset = phwi_ctrlr->default_pdu_data[ulp_num]. | |
1826 | doorbell_offset; | |
6733b39a JK |
1827 | } |
1828 | ||
1829 | writables = (writables / 8) * 8; | |
1830 | if (writables) { | |
1831 | for (i = 0; i < writables; i++) { | |
1832 | pbusy_list = | |
1833 | hwi_get_async_busy_list(pasync_ctx, is_header, | |
1834 | host_write_num); | |
1835 | pasync_handle = | |
1836 | list_entry(pfree_link, struct async_pdu_handle, | |
1837 | link); | |
1838 | WARN_ON(!pasync_handle); | |
1839 | pasync_handle->consumed = 0; | |
1840 | ||
1841 | pfree_link = pfree_link->next; | |
1842 | ||
1843 | pasync_sge = hwi_get_ring_address(pasync_ctx, | |
1844 | is_header, host_write_num); | |
1845 | ||
1846 | pasync_sge->hi = pasync_handle->pa.u.a32.address_lo; | |
1847 | pasync_sge->lo = pasync_handle->pa.u.a32.address_hi; | |
1848 | ||
1849 | list_move(&pasync_handle->link, pbusy_list); | |
1850 | ||
1851 | host_write_num++; | |
1852 | host_write_num = host_write_num % num_entries; | |
1853 | } | |
1854 | ||
1855 | if (is_header) { | |
1856 | pasync_ctx->async_header.host_write_ptr = | |
1857 | host_write_num; | |
1858 | pasync_ctx->async_header.free_entries -= writables; | |
1859 | pasync_ctx->async_header.writables -= writables; | |
1860 | pasync_ctx->async_header.busy_entries += writables; | |
1861 | } else { | |
1862 | pasync_ctx->async_data.host_write_ptr = host_write_num; | |
1863 | pasync_ctx->async_data.free_entries -= writables; | |
1864 | pasync_ctx->async_data.writables -= writables; | |
1865 | pasync_ctx->async_data.busy_entries += writables; | |
1866 | } | |
1867 | ||
1868 | doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK; | |
1869 | doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT; | |
1870 | doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT; | |
1871 | doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK) | |
1872 | << DB_DEF_PDU_CQPROC_SHIFT; | |
1873 | ||
8a86e833 | 1874 | iowrite32(doorbell, phba->db_va + doorbell_offset); |
6733b39a JK |
1875 | } |
1876 | } | |
1877 | ||
1878 | static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba, | |
1879 | struct beiscsi_conn *beiscsi_conn, | |
1880 | struct i_t_dpdu_cqe *pdpdu_cqe) | |
1881 | { | |
1882 | struct hwi_controller *phwi_ctrlr; | |
1883 | struct hwi_async_pdu_context *pasync_ctx; | |
1884 | struct async_pdu_handle *pasync_handle = NULL; | |
1885 | unsigned int cq_index = -1; | |
8a86e833 JK |
1886 | uint16_t cri_index = BE_GET_CRI_FROM_CID( |
1887 | beiscsi_conn->beiscsi_conn_cid); | |
6733b39a JK |
1888 | |
1889 | phwi_ctrlr = phba->phwi_ctrlr; | |
8a86e833 JK |
1890 | pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, |
1891 | BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, | |
1892 | cri_index)); | |
6733b39a JK |
1893 | |
1894 | pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx, | |
1895 | pdpdu_cqe, &cq_index); | |
1896 | BUG_ON(pasync_handle->is_header != 0); | |
1897 | if (pasync_handle->consumed == 0) | |
99bc5d55 JSJ |
1898 | hwi_update_async_writables(phba, pasync_ctx, |
1899 | pasync_handle->is_header, cq_index); | |
6733b39a | 1900 | |
8a86e833 JK |
1901 | hwi_free_async_msg(phba, pasync_ctx, pasync_handle->cri); |
1902 | hwi_post_async_buffers(phba, pasync_handle->is_header, | |
1903 | BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, | |
1904 | cri_index)); | |
6733b39a JK |
1905 | } |
1906 | ||
1907 | static unsigned int | |
1908 | hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn, | |
1909 | struct beiscsi_hba *phba, | |
1910 | struct hwi_async_pdu_context *pasync_ctx, unsigned short cri) | |
1911 | { | |
1912 | struct list_head *plist; | |
1913 | struct async_pdu_handle *pasync_handle; | |
1914 | void *phdr = NULL; | |
1915 | unsigned int hdr_len = 0, buf_len = 0; | |
1916 | unsigned int status, index = 0, offset = 0; | |
1917 | void *pfirst_buffer = NULL; | |
1918 | unsigned int num_buf = 0; | |
1919 | ||
1920 | plist = &pasync_ctx->async_entry[cri].wait_queue.list; | |
1921 | ||
1922 | list_for_each_entry(pasync_handle, plist, link) { | |
1923 | if (index == 0) { | |
1924 | phdr = pasync_handle->pbuffer; | |
1925 | hdr_len = pasync_handle->buffer_len; | |
1926 | } else { | |
1927 | buf_len = pasync_handle->buffer_len; | |
1928 | if (!num_buf) { | |
1929 | pfirst_buffer = pasync_handle->pbuffer; | |
1930 | num_buf++; | |
1931 | } | |
1932 | memcpy(pfirst_buffer + offset, | |
1933 | pasync_handle->pbuffer, buf_len); | |
f2ba02b8 | 1934 | offset += buf_len; |
6733b39a JK |
1935 | } |
1936 | index++; | |
1937 | } | |
1938 | ||
1939 | status = beiscsi_process_async_pdu(beiscsi_conn, phba, | |
7da50879 | 1940 | phdr, hdr_len, pfirst_buffer, |
f2ba02b8 | 1941 | offset); |
6733b39a | 1942 | |
8a86e833 | 1943 | hwi_free_async_msg(phba, pasync_ctx, cri); |
6733b39a JK |
1944 | return 0; |
1945 | } | |
1946 | ||
1947 | static unsigned int | |
1948 | hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn, | |
1949 | struct beiscsi_hba *phba, | |
1950 | struct async_pdu_handle *pasync_handle) | |
1951 | { | |
1952 | struct hwi_async_pdu_context *pasync_ctx; | |
1953 | struct hwi_controller *phwi_ctrlr; | |
1954 | unsigned int bytes_needed = 0, status = 0; | |
1955 | unsigned short cri = pasync_handle->cri; | |
1956 | struct pdu_base *ppdu; | |
1957 | ||
1958 | phwi_ctrlr = phba->phwi_ctrlr; | |
8a86e833 JK |
1959 | pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, |
1960 | BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, | |
1961 | BE_GET_CRI_FROM_CID(beiscsi_conn-> | |
1962 | beiscsi_conn_cid))); | |
6733b39a JK |
1963 | |
1964 | list_del(&pasync_handle->link); | |
1965 | if (pasync_handle->is_header) { | |
1966 | pasync_ctx->async_header.busy_entries--; | |
1967 | if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) { | |
8a86e833 | 1968 | hwi_free_async_msg(phba, pasync_ctx, cri); |
6733b39a JK |
1969 | BUG(); |
1970 | } | |
1971 | ||
1972 | pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0; | |
1973 | pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1; | |
1974 | pasync_ctx->async_entry[cri].wait_queue.hdr_len = | |
1975 | (unsigned short)pasync_handle->buffer_len; | |
1976 | list_add_tail(&pasync_handle->link, | |
1977 | &pasync_ctx->async_entry[cri].wait_queue.list); | |
1978 | ||
1979 | ppdu = pasync_handle->pbuffer; | |
1980 | bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base, | |
1981 | data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) & | |
1982 | 0xFFFF0000) | ((be16_to_cpu((ppdu-> | |
1983 | dw[offsetof(struct amap_pdu_base, data_len_lo) / 32] | |
1984 | & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF)); | |
1985 | ||
1986 | if (status == 0) { | |
1987 | pasync_ctx->async_entry[cri].wait_queue.bytes_needed = | |
1988 | bytes_needed; | |
1989 | ||
1990 | if (bytes_needed == 0) | |
1991 | status = hwi_fwd_async_msg(beiscsi_conn, phba, | |
1992 | pasync_ctx, cri); | |
1993 | } | |
1994 | } else { | |
1995 | pasync_ctx->async_data.busy_entries--; | |
1996 | if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) { | |
1997 | list_add_tail(&pasync_handle->link, | |
1998 | &pasync_ctx->async_entry[cri].wait_queue. | |
1999 | list); | |
2000 | pasync_ctx->async_entry[cri].wait_queue. | |
2001 | bytes_received += | |
2002 | (unsigned short)pasync_handle->buffer_len; | |
2003 | ||
2004 | if (pasync_ctx->async_entry[cri].wait_queue. | |
2005 | bytes_received >= | |
2006 | pasync_ctx->async_entry[cri].wait_queue. | |
2007 | bytes_needed) | |
2008 | status = hwi_fwd_async_msg(beiscsi_conn, phba, | |
2009 | pasync_ctx, cri); | |
2010 | } | |
2011 | } | |
2012 | return status; | |
2013 | } | |
2014 | ||
2015 | static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn, | |
2016 | struct beiscsi_hba *phba, | |
2017 | struct i_t_dpdu_cqe *pdpdu_cqe) | |
2018 | { | |
2019 | struct hwi_controller *phwi_ctrlr; | |
2020 | struct hwi_async_pdu_context *pasync_ctx; | |
2021 | struct async_pdu_handle *pasync_handle = NULL; | |
2022 | unsigned int cq_index = -1; | |
8a86e833 JK |
2023 | uint16_t cri_index = BE_GET_CRI_FROM_CID( |
2024 | beiscsi_conn->beiscsi_conn_cid); | |
6733b39a JK |
2025 | |
2026 | phwi_ctrlr = phba->phwi_ctrlr; | |
8a86e833 JK |
2027 | pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, |
2028 | BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr, | |
2029 | cri_index)); | |
2030 | ||
6733b39a JK |
2031 | pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx, |
2032 | pdpdu_cqe, &cq_index); | |
2033 | ||
2034 | if (pasync_handle->consumed == 0) | |
99bc5d55 JSJ |
2035 | hwi_update_async_writables(phba, pasync_ctx, |
2036 | pasync_handle->is_header, cq_index); | |
2037 | ||
6733b39a | 2038 | hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle); |
8a86e833 JK |
2039 | hwi_post_async_buffers(phba, pasync_handle->is_header, |
2040 | BEISCSI_GET_ULP_FROM_CRI( | |
2041 | phwi_ctrlr, cri_index)); | |
6733b39a JK |
2042 | } |
2043 | ||
2e4e8f65 | 2044 | void beiscsi_process_mcc_cq(struct beiscsi_hba *phba) |
756d29c8 JK |
2045 | { |
2046 | struct be_queue_info *mcc_cq; | |
2047 | struct be_mcc_compl *mcc_compl; | |
2048 | unsigned int num_processed = 0; | |
2049 | ||
2050 | mcc_cq = &phba->ctrl.mcc_obj.cq; | |
2051 | mcc_compl = queue_tail_node(mcc_cq); | |
2052 | mcc_compl->flags = le32_to_cpu(mcc_compl->flags); | |
2053 | while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) { | |
756d29c8 JK |
2054 | if (num_processed >= 32) { |
2055 | hwi_ring_cq_db(phba, mcc_cq->id, | |
1094cf68 | 2056 | num_processed, 0); |
756d29c8 JK |
2057 | num_processed = 0; |
2058 | } | |
2059 | if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) { | |
53aefe25 | 2060 | beiscsi_process_async_event(phba, mcc_compl); |
756d29c8 | 2061 | } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) { |
2e4e8f65 | 2062 | beiscsi_process_mcc_compl(&phba->ctrl, mcc_compl); |
756d29c8 JK |
2063 | } |
2064 | ||
2065 | mcc_compl->flags = 0; | |
2066 | queue_tail_inc(mcc_cq); | |
2067 | mcc_compl = queue_tail_node(mcc_cq); | |
2068 | mcc_compl->flags = le32_to_cpu(mcc_compl->flags); | |
2069 | num_processed++; | |
2070 | } | |
2071 | ||
2072 | if (num_processed > 0) | |
1094cf68 | 2073 | hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1); |
756d29c8 | 2074 | } |
bfead3b2 | 2075 | |
6763daae JSJ |
2076 | /** |
2077 | * beiscsi_process_cq()- Process the Completion Queue | |
2078 | * @pbe_eq: Event Q on which the Completion has come | |
1094cf68 | 2079 | * @budget: Max number of events to processed |
6763daae JSJ |
2080 | * |
2081 | * return | |
2082 | * Number of Completion Entries processed. | |
2083 | **/ | |
1094cf68 | 2084 | unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget) |
6733b39a | 2085 | { |
6733b39a JK |
2086 | struct be_queue_info *cq; |
2087 | struct sol_cqe *sol; | |
2088 | struct dmsg_cqe *dmsg; | |
1094cf68 | 2089 | unsigned int total = 0; |
6733b39a | 2090 | unsigned int num_processed = 0; |
0a513dd8 | 2091 | unsigned short code = 0, cid = 0; |
a7909b39 | 2092 | uint16_t cri_index = 0; |
6733b39a | 2093 | struct beiscsi_conn *beiscsi_conn; |
c2462288 JK |
2094 | struct beiscsi_endpoint *beiscsi_ep; |
2095 | struct iscsi_endpoint *ep; | |
bfead3b2 | 2096 | struct beiscsi_hba *phba; |
6733b39a | 2097 | |
bfead3b2 | 2098 | cq = pbe_eq->cq; |
6733b39a | 2099 | sol = queue_tail_node(cq); |
bfead3b2 | 2100 | phba = pbe_eq->phba; |
6733b39a JK |
2101 | |
2102 | while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] & | |
2103 | CQE_VALID_MASK) { | |
2104 | be_dws_le_to_cpu(sol, sizeof(struct sol_cqe)); | |
2105 | ||
73133261 JSJ |
2106 | code = (sol->dw[offsetof(struct amap_sol_cqe, code) / |
2107 | 32] & CQE_CODE_MASK); | |
2108 | ||
2109 | /* Get the CID */ | |
2c9dfd36 JK |
2110 | if (is_chip_be2_be3r(phba)) { |
2111 | cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol); | |
2112 | } else { | |
73133261 JSJ |
2113 | if ((code == DRIVERMSG_NOTIFY) || |
2114 | (code == UNSOL_HDR_NOTIFY) || | |
2115 | (code == UNSOL_DATA_NOTIFY)) | |
2116 | cid = AMAP_GET_BITS( | |
2117 | struct amap_i_t_dpdu_cqe_v2, | |
2118 | cid, sol); | |
2119 | else | |
2120 | cid = AMAP_GET_BITS(struct amap_sol_cqe_v2, | |
2121 | cid, sol); | |
2c9dfd36 | 2122 | } |
32951dd8 | 2123 | |
a7909b39 JK |
2124 | cri_index = BE_GET_CRI_FROM_CID(cid); |
2125 | ep = phba->ep_array[cri_index]; | |
b7ab35b1 JK |
2126 | |
2127 | if (ep == NULL) { | |
2128 | /* connection has already been freed | |
2129 | * just move on to next one | |
2130 | */ | |
2131 | beiscsi_log(phba, KERN_WARNING, | |
2132 | BEISCSI_LOG_INIT, | |
2133 | "BM_%d : proc cqe of disconn ep: cid %d\n", | |
2134 | cid); | |
2135 | goto proc_next_cqe; | |
2136 | } | |
2137 | ||
c2462288 JK |
2138 | beiscsi_ep = ep->dd_data; |
2139 | beiscsi_conn = beiscsi_ep->conn; | |
756d29c8 | 2140 | |
1094cf68 JB |
2141 | /* replenish cq */ |
2142 | if (num_processed == 32) { | |
2143 | hwi_ring_cq_db(phba, cq->id, 32, 0); | |
6733b39a JK |
2144 | num_processed = 0; |
2145 | } | |
1094cf68 | 2146 | total++; |
6733b39a | 2147 | |
0a513dd8 | 2148 | switch (code) { |
6733b39a JK |
2149 | case SOL_CMD_COMPLETE: |
2150 | hwi_complete_cmd(beiscsi_conn, phba, sol); | |
2151 | break; | |
2152 | case DRIVERMSG_NOTIFY: | |
99bc5d55 JSJ |
2153 | beiscsi_log(phba, KERN_INFO, |
2154 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
6763daae JSJ |
2155 | "BM_%d : Received %s[%d] on CID : %d\n", |
2156 | cqe_desc[code], code, cid); | |
99bc5d55 | 2157 | |
6733b39a JK |
2158 | dmsg = (struct dmsg_cqe *)sol; |
2159 | hwi_complete_drvr_msgs(beiscsi_conn, phba, sol); | |
2160 | break; | |
2161 | case UNSOL_HDR_NOTIFY: | |
99bc5d55 JSJ |
2162 | beiscsi_log(phba, KERN_INFO, |
2163 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
6763daae JSJ |
2164 | "BM_%d : Received %s[%d] on CID : %d\n", |
2165 | cqe_desc[code], code, cid); | |
99bc5d55 | 2166 | |
8f09a3b9 | 2167 | spin_lock_bh(&phba->async_pdu_lock); |
bfead3b2 JK |
2168 | hwi_process_default_pdu_ring(beiscsi_conn, phba, |
2169 | (struct i_t_dpdu_cqe *)sol); | |
8f09a3b9 | 2170 | spin_unlock_bh(&phba->async_pdu_lock); |
bfead3b2 | 2171 | break; |
6733b39a | 2172 | case UNSOL_DATA_NOTIFY: |
99bc5d55 JSJ |
2173 | beiscsi_log(phba, KERN_INFO, |
2174 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
6763daae JSJ |
2175 | "BM_%d : Received %s[%d] on CID : %d\n", |
2176 | cqe_desc[code], code, cid); | |
99bc5d55 | 2177 | |
8f09a3b9 | 2178 | spin_lock_bh(&phba->async_pdu_lock); |
6733b39a JK |
2179 | hwi_process_default_pdu_ring(beiscsi_conn, phba, |
2180 | (struct i_t_dpdu_cqe *)sol); | |
8f09a3b9 | 2181 | spin_unlock_bh(&phba->async_pdu_lock); |
6733b39a JK |
2182 | break; |
2183 | case CXN_INVALIDATE_INDEX_NOTIFY: | |
2184 | case CMD_INVALIDATED_NOTIFY: | |
2185 | case CXN_INVALIDATE_NOTIFY: | |
99bc5d55 JSJ |
2186 | beiscsi_log(phba, KERN_ERR, |
2187 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
6763daae JSJ |
2188 | "BM_%d : Ignoring %s[%d] on CID : %d\n", |
2189 | cqe_desc[code], code, cid); | |
6733b39a | 2190 | break; |
1094cf68 | 2191 | case CXN_KILLED_HDR_DIGEST_ERR: |
6733b39a | 2192 | case SOL_CMD_KILLED_DATA_DIGEST_ERR: |
1094cf68 JB |
2193 | beiscsi_log(phba, KERN_ERR, |
2194 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
2195 | "BM_%d : Cmd Notification %s[%d] on CID : %d\n", | |
2196 | cqe_desc[code], code, cid); | |
2197 | break; | |
6733b39a JK |
2198 | case CMD_KILLED_INVALID_STATSN_RCVD: |
2199 | case CMD_KILLED_INVALID_R2T_RCVD: | |
2200 | case CMD_CXN_KILLED_LUN_INVALID: | |
2201 | case CMD_CXN_KILLED_ICD_INVALID: | |
2202 | case CMD_CXN_KILLED_ITT_INVALID: | |
2203 | case CMD_CXN_KILLED_SEQ_OUTOFORDER: | |
2204 | case CMD_CXN_KILLED_INVALID_DATASN_RCVD: | |
99bc5d55 JSJ |
2205 | beiscsi_log(phba, KERN_ERR, |
2206 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
6763daae JSJ |
2207 | "BM_%d : Cmd Notification %s[%d] on CID : %d\n", |
2208 | cqe_desc[code], code, cid); | |
6733b39a JK |
2209 | break; |
2210 | case UNSOL_DATA_DIGEST_ERROR_NOTIFY: | |
99bc5d55 JSJ |
2211 | beiscsi_log(phba, KERN_ERR, |
2212 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
6763daae JSJ |
2213 | "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n", |
2214 | cqe_desc[code], code, cid); | |
8f09a3b9 | 2215 | spin_lock_bh(&phba->async_pdu_lock); |
6733b39a JK |
2216 | hwi_flush_default_pdu_buffer(phba, beiscsi_conn, |
2217 | (struct i_t_dpdu_cqe *) sol); | |
8f09a3b9 | 2218 | spin_unlock_bh(&phba->async_pdu_lock); |
6733b39a JK |
2219 | break; |
2220 | case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL: | |
2221 | case CXN_KILLED_BURST_LEN_MISMATCH: | |
2222 | case CXN_KILLED_AHS_RCVD: | |
6733b39a JK |
2223 | case CXN_KILLED_UNKNOWN_HDR: |
2224 | case CXN_KILLED_STALE_ITT_TTT_RCVD: | |
2225 | case CXN_KILLED_INVALID_ITT_TTT_RCVD: | |
2226 | case CXN_KILLED_TIMED_OUT: | |
2227 | case CXN_KILLED_FIN_RCVD: | |
6763daae JSJ |
2228 | case CXN_KILLED_RST_SENT: |
2229 | case CXN_KILLED_RST_RCVD: | |
6733b39a JK |
2230 | case CXN_KILLED_BAD_UNSOL_PDU_RCVD: |
2231 | case CXN_KILLED_BAD_WRB_INDEX_ERROR: | |
2232 | case CXN_KILLED_OVER_RUN_RESIDUAL: | |
2233 | case CXN_KILLED_UNDER_RUN_RESIDUAL: | |
2234 | case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN: | |
99bc5d55 JSJ |
2235 | beiscsi_log(phba, KERN_ERR, |
2236 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
6763daae JSJ |
2237 | "BM_%d : Event %s[%d] received on CID : %d\n", |
2238 | cqe_desc[code], code, cid); | |
0a513dd8 JSJ |
2239 | if (beiscsi_conn) |
2240 | iscsi_conn_failure(beiscsi_conn->conn, | |
2241 | ISCSI_ERR_CONN_FAILED); | |
6733b39a JK |
2242 | break; |
2243 | default: | |
99bc5d55 JSJ |
2244 | beiscsi_log(phba, KERN_ERR, |
2245 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
6763daae JSJ |
2246 | "BM_%d : Invalid CQE Event Received Code : %d" |
2247 | "CID 0x%x...\n", | |
0a513dd8 | 2248 | code, cid); |
6733b39a JK |
2249 | break; |
2250 | } | |
2251 | ||
b7ab35b1 | 2252 | proc_next_cqe: |
6733b39a JK |
2253 | AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0); |
2254 | queue_tail_inc(cq); | |
2255 | sol = queue_tail_node(cq); | |
2256 | num_processed++; | |
1094cf68 JB |
2257 | if (total == budget) |
2258 | break; | |
6733b39a JK |
2259 | } |
2260 | ||
1094cf68 JB |
2261 | hwi_ring_cq_db(phba, cq->id, num_processed, 1); |
2262 | return total; | |
6733b39a JK |
2263 | } |
2264 | ||
756d29c8 | 2265 | void beiscsi_process_all_cqs(struct work_struct *work) |
6733b39a JK |
2266 | { |
2267 | unsigned long flags; | |
bfead3b2 JK |
2268 | struct hwi_controller *phwi_ctrlr; |
2269 | struct hwi_context_memory *phwi_context; | |
72fb46a9 JSJ |
2270 | struct beiscsi_hba *phba; |
2271 | struct be_eq_obj *pbe_eq = | |
2272 | container_of(work, struct be_eq_obj, work_cqs); | |
6733b39a | 2273 | |
72fb46a9 | 2274 | phba = pbe_eq->phba; |
bfead3b2 JK |
2275 | phwi_ctrlr = phba->phwi_ctrlr; |
2276 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
bfead3b2 | 2277 | |
72fb46a9 | 2278 | if (pbe_eq->todo_mcc_cq) { |
6733b39a | 2279 | spin_lock_irqsave(&phba->isr_lock, flags); |
72fb46a9 | 2280 | pbe_eq->todo_mcc_cq = false; |
6733b39a | 2281 | spin_unlock_irqrestore(&phba->isr_lock, flags); |
2e4e8f65 | 2282 | beiscsi_process_mcc_cq(phba); |
6733b39a JK |
2283 | } |
2284 | ||
72fb46a9 | 2285 | if (pbe_eq->todo_cq) { |
6733b39a | 2286 | spin_lock_irqsave(&phba->isr_lock, flags); |
72fb46a9 | 2287 | pbe_eq->todo_cq = false; |
6733b39a | 2288 | spin_unlock_irqrestore(&phba->isr_lock, flags); |
1094cf68 | 2289 | beiscsi_process_cq(pbe_eq, BE2_MAX_NUM_CQ_PROC); |
6733b39a | 2290 | } |
72fb46a9 JSJ |
2291 | |
2292 | /* rearm EQ for further interrupts */ | |
2293 | hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1); | |
6733b39a JK |
2294 | } |
2295 | ||
511cbce2 | 2296 | static int be_iopoll(struct irq_poll *iop, int budget) |
6733b39a | 2297 | { |
1094cf68 | 2298 | unsigned int ret, num_eq_processed; |
6733b39a | 2299 | struct beiscsi_hba *phba; |
bfead3b2 | 2300 | struct be_eq_obj *pbe_eq; |
1094cf68 JB |
2301 | struct be_eq_entry *eqe = NULL; |
2302 | struct be_queue_info *eq; | |
6733b39a | 2303 | |
1094cf68 | 2304 | num_eq_processed = 0; |
bfead3b2 | 2305 | pbe_eq = container_of(iop, struct be_eq_obj, iopoll); |
1094cf68 JB |
2306 | phba = pbe_eq->phba; |
2307 | eq = &pbe_eq->q; | |
2308 | eqe = queue_tail_node(eq); | |
2309 | ||
2310 | while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] & | |
2311 | EQE_VALID_MASK) { | |
2312 | AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); | |
2313 | queue_tail_inc(eq); | |
2314 | eqe = queue_tail_node(eq); | |
2315 | num_eq_processed++; | |
2316 | } | |
2317 | ||
2318 | hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1); | |
2319 | ||
2320 | ret = beiscsi_process_cq(pbe_eq, budget); | |
73af08e1 | 2321 | pbe_eq->cq_count += ret; |
6733b39a | 2322 | if (ret < budget) { |
511cbce2 | 2323 | irq_poll_complete(iop); |
99bc5d55 JSJ |
2324 | beiscsi_log(phba, KERN_INFO, |
2325 | BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO, | |
1094cf68 JB |
2326 | "BM_%d : rearm pbe_eq->q.id =%d ret %d\n", |
2327 | pbe_eq->q.id, ret); | |
bfead3b2 | 2328 | hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1); |
6733b39a JK |
2329 | } |
2330 | return ret; | |
2331 | } | |
2332 | ||
09a1093a JSJ |
2333 | static void |
2334 | hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg, | |
2335 | unsigned int num_sg, struct beiscsi_io_task *io_task) | |
2336 | { | |
2337 | struct iscsi_sge *psgl; | |
2338 | unsigned int sg_len, index; | |
2339 | unsigned int sge_len = 0; | |
2340 | unsigned long long addr; | |
2341 | struct scatterlist *l_sg; | |
2342 | unsigned int offset; | |
2343 | ||
2344 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb, | |
2345 | io_task->bhs_pa.u.a32.address_lo); | |
2346 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb, | |
2347 | io_task->bhs_pa.u.a32.address_hi); | |
2348 | ||
2349 | l_sg = sg; | |
2350 | for (index = 0; (index < num_sg) && (index < 2); index++, | |
2351 | sg = sg_next(sg)) { | |
2352 | if (index == 0) { | |
2353 | sg_len = sg_dma_len(sg); | |
2354 | addr = (u64) sg_dma_address(sg); | |
2355 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, | |
2356 | sge0_addr_lo, pwrb, | |
2357 | lower_32_bits(addr)); | |
2358 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, | |
2359 | sge0_addr_hi, pwrb, | |
2360 | upper_32_bits(addr)); | |
2361 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, | |
2362 | sge0_len, pwrb, | |
2363 | sg_len); | |
2364 | sge_len = sg_len; | |
2365 | } else { | |
2366 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset, | |
2367 | pwrb, sge_len); | |
2368 | sg_len = sg_dma_len(sg); | |
2369 | addr = (u64) sg_dma_address(sg); | |
2370 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, | |
2371 | sge1_addr_lo, pwrb, | |
2372 | lower_32_bits(addr)); | |
2373 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, | |
2374 | sge1_addr_hi, pwrb, | |
2375 | upper_32_bits(addr)); | |
2376 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, | |
2377 | sge1_len, pwrb, | |
2378 | sg_len); | |
2379 | } | |
2380 | } | |
2381 | psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; | |
2382 | memset(psgl, 0, sizeof(*psgl) * BE2_SGE); | |
2383 | ||
2384 | AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2); | |
2385 | ||
2386 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, | |
2387 | io_task->bhs_pa.u.a32.address_hi); | |
2388 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, | |
2389 | io_task->bhs_pa.u.a32.address_lo); | |
2390 | ||
2391 | if (num_sg == 1) { | |
2392 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, | |
2393 | 1); | |
2394 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, | |
2395 | 0); | |
2396 | } else if (num_sg == 2) { | |
2397 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, | |
2398 | 0); | |
2399 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, | |
2400 | 1); | |
2401 | } else { | |
2402 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb, | |
2403 | 0); | |
2404 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb, | |
2405 | 0); | |
2406 | } | |
2407 | ||
2408 | sg = l_sg; | |
2409 | psgl++; | |
2410 | psgl++; | |
2411 | offset = 0; | |
2412 | for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) { | |
2413 | sg_len = sg_dma_len(sg); | |
2414 | addr = (u64) sg_dma_address(sg); | |
2415 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, | |
2416 | lower_32_bits(addr)); | |
2417 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, | |
2418 | upper_32_bits(addr)); | |
2419 | AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len); | |
2420 | AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset); | |
2421 | AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); | |
2422 | offset += sg_len; | |
2423 | } | |
2424 | psgl--; | |
2425 | AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); | |
2426 | } | |
2427 | ||
6733b39a JK |
2428 | static void |
2429 | hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg, | |
2430 | unsigned int num_sg, struct beiscsi_io_task *io_task) | |
2431 | { | |
2432 | struct iscsi_sge *psgl; | |
58ff4bd0 | 2433 | unsigned int sg_len, index; |
6733b39a JK |
2434 | unsigned int sge_len = 0; |
2435 | unsigned long long addr; | |
2436 | struct scatterlist *l_sg; | |
2437 | unsigned int offset; | |
2438 | ||
2439 | AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb, | |
2440 | io_task->bhs_pa.u.a32.address_lo); | |
2441 | AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb, | |
2442 | io_task->bhs_pa.u.a32.address_hi); | |
2443 | ||
2444 | l_sg = sg; | |
48bd86cf JK |
2445 | for (index = 0; (index < num_sg) && (index < 2); index++, |
2446 | sg = sg_next(sg)) { | |
6733b39a JK |
2447 | if (index == 0) { |
2448 | sg_len = sg_dma_len(sg); | |
2449 | addr = (u64) sg_dma_address(sg); | |
2450 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb, | |
457ff3b7 | 2451 | ((u32)(addr & 0xFFFFFFFF))); |
6733b39a | 2452 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb, |
457ff3b7 | 2453 | ((u32)(addr >> 32))); |
6733b39a JK |
2454 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb, |
2455 | sg_len); | |
2456 | sge_len = sg_len; | |
6733b39a | 2457 | } else { |
6733b39a JK |
2458 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset, |
2459 | pwrb, sge_len); | |
2460 | sg_len = sg_dma_len(sg); | |
2461 | addr = (u64) sg_dma_address(sg); | |
2462 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb, | |
457ff3b7 | 2463 | ((u32)(addr & 0xFFFFFFFF))); |
6733b39a | 2464 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb, |
457ff3b7 | 2465 | ((u32)(addr >> 32))); |
6733b39a JK |
2466 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb, |
2467 | sg_len); | |
2468 | } | |
2469 | } | |
2470 | psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; | |
2471 | memset(psgl, 0, sizeof(*psgl) * BE2_SGE); | |
2472 | ||
2473 | AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2); | |
2474 | ||
2475 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, | |
2476 | io_task->bhs_pa.u.a32.address_hi); | |
2477 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, | |
2478 | io_task->bhs_pa.u.a32.address_lo); | |
2479 | ||
caf818f1 JK |
2480 | if (num_sg == 1) { |
2481 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, | |
2482 | 1); | |
2483 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, | |
2484 | 0); | |
2485 | } else if (num_sg == 2) { | |
2486 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, | |
2487 | 0); | |
2488 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, | |
2489 | 1); | |
2490 | } else { | |
2491 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, | |
2492 | 0); | |
2493 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb, | |
2494 | 0); | |
2495 | } | |
6733b39a JK |
2496 | sg = l_sg; |
2497 | psgl++; | |
2498 | psgl++; | |
2499 | offset = 0; | |
48bd86cf | 2500 | for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) { |
6733b39a JK |
2501 | sg_len = sg_dma_len(sg); |
2502 | addr = (u64) sg_dma_address(sg); | |
2503 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, | |
2504 | (addr & 0xFFFFFFFF)); | |
2505 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, | |
2506 | (addr >> 32)); | |
2507 | AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len); | |
2508 | AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset); | |
2509 | AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); | |
2510 | offset += sg_len; | |
2511 | } | |
2512 | psgl--; | |
2513 | AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); | |
2514 | } | |
2515 | ||
d629c471 JSJ |
2516 | /** |
2517 | * hwi_write_buffer()- Populate the WRB with task info | |
2518 | * @pwrb: ptr to the WRB entry | |
2519 | * @task: iscsi task which is to be executed | |
2520 | **/ | |
e0493627 | 2521 | static int hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task) |
6733b39a JK |
2522 | { |
2523 | struct iscsi_sge *psgl; | |
6733b39a JK |
2524 | struct beiscsi_io_task *io_task = task->dd_data; |
2525 | struct beiscsi_conn *beiscsi_conn = io_task->conn; | |
2526 | struct beiscsi_hba *phba = beiscsi_conn->phba; | |
09a1093a | 2527 | uint8_t dsp_value = 0; |
6733b39a JK |
2528 | |
2529 | io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2; | |
2530 | AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb, | |
2531 | io_task->bhs_pa.u.a32.address_lo); | |
2532 | AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb, | |
2533 | io_task->bhs_pa.u.a32.address_hi); | |
2534 | ||
2535 | if (task->data) { | |
09a1093a JSJ |
2536 | |
2537 | /* Check for the data_count */ | |
2538 | dsp_value = (task->data_count) ? 1 : 0; | |
2539 | ||
2c9dfd36 JK |
2540 | if (is_chip_be2_be3r(phba)) |
2541 | AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, | |
09a1093a JSJ |
2542 | pwrb, dsp_value); |
2543 | else | |
2c9dfd36 | 2544 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, |
09a1093a JSJ |
2545 | pwrb, dsp_value); |
2546 | ||
2547 | /* Map addr only if there is data_count */ | |
2548 | if (dsp_value) { | |
d629c471 JSJ |
2549 | io_task->mtask_addr = pci_map_single(phba->pcidev, |
2550 | task->data, | |
2551 | task->data_count, | |
2552 | PCI_DMA_TODEVICE); | |
e0493627 AK |
2553 | if (pci_dma_mapping_error(phba->pcidev, |
2554 | io_task->mtask_addr)) | |
2555 | return -ENOMEM; | |
d629c471 | 2556 | io_task->mtask_data_count = task->data_count; |
09a1093a | 2557 | } else |
d629c471 | 2558 | io_task->mtask_addr = 0; |
09a1093a | 2559 | |
6733b39a | 2560 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb, |
d629c471 | 2561 | lower_32_bits(io_task->mtask_addr)); |
6733b39a | 2562 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb, |
d629c471 | 2563 | upper_32_bits(io_task->mtask_addr)); |
6733b39a JK |
2564 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb, |
2565 | task->data_count); | |
2566 | ||
2567 | AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1); | |
2568 | } else { | |
2569 | AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0); | |
d629c471 | 2570 | io_task->mtask_addr = 0; |
6733b39a JK |
2571 | } |
2572 | ||
2573 | psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag; | |
2574 | ||
2575 | AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len); | |
2576 | ||
2577 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, | |
2578 | io_task->bhs_pa.u.a32.address_hi); | |
2579 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, | |
2580 | io_task->bhs_pa.u.a32.address_lo); | |
2581 | if (task->data) { | |
2582 | psgl++; | |
2583 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0); | |
2584 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0); | |
2585 | AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0); | |
2586 | AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0); | |
2587 | AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0); | |
2588 | AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0); | |
2589 | ||
2590 | psgl++; | |
2591 | if (task->data) { | |
2592 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, | |
d629c471 | 2593 | lower_32_bits(io_task->mtask_addr)); |
6733b39a | 2594 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, |
d629c471 | 2595 | upper_32_bits(io_task->mtask_addr)); |
6733b39a JK |
2596 | } |
2597 | AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106); | |
2598 | } | |
2599 | AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1); | |
e0493627 | 2600 | return 0; |
6733b39a JK |
2601 | } |
2602 | ||
843ae752 JK |
2603 | /** |
2604 | * beiscsi_find_mem_req()- Find mem needed | |
2605 | * @phba: ptr to HBA struct | |
2606 | **/ | |
6733b39a JK |
2607 | static void beiscsi_find_mem_req(struct beiscsi_hba *phba) |
2608 | { | |
8a86e833 | 2609 | uint8_t mem_descr_index, ulp_num; |
bfead3b2 | 2610 | unsigned int num_cq_pages, num_async_pdu_buf_pages; |
6733b39a JK |
2611 | unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn; |
2612 | unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages; | |
2613 | ||
2614 | num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \ | |
2615 | sizeof(struct sol_cqe)); | |
6733b39a JK |
2616 | |
2617 | phba->params.hwi_ws_sz = sizeof(struct hwi_controller); | |
2618 | ||
2619 | phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 * | |
2620 | BE_ISCSI_PDU_HEADER_SIZE; | |
2621 | phba->mem_req[HWI_MEM_ADDN_CONTEXT] = | |
2622 | sizeof(struct hwi_context_memory); | |
2623 | ||
6733b39a JK |
2624 | |
2625 | phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb) | |
2626 | * (phba->params.wrbs_per_cxn) | |
2627 | * phba->params.cxns_per_ctrl; | |
2628 | wrb_sz_per_cxn = sizeof(struct wrb_handle) * | |
2629 | (phba->params.wrbs_per_cxn); | |
2630 | phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) * | |
2631 | phba->params.cxns_per_ctrl); | |
2632 | ||
2633 | phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) * | |
2634 | phba->params.icds_per_ctrl; | |
2635 | phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) * | |
2636 | phba->params.num_sge_per_io * phba->params.icds_per_ctrl; | |
8a86e833 JK |
2637 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
2638 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { | |
6733b39a | 2639 | |
8a86e833 JK |
2640 | num_async_pdu_buf_sgl_pages = |
2641 | PAGES_REQUIRED(BEISCSI_GET_CID_COUNT( | |
2642 | phba, ulp_num) * | |
2643 | sizeof(struct phys_addr)); | |
2644 | ||
2645 | num_async_pdu_buf_pages = | |
2646 | PAGES_REQUIRED(BEISCSI_GET_CID_COUNT( | |
2647 | phba, ulp_num) * | |
2648 | phba->params.defpdu_hdr_sz); | |
2649 | ||
2650 | num_async_pdu_data_pages = | |
2651 | PAGES_REQUIRED(BEISCSI_GET_CID_COUNT( | |
2652 | phba, ulp_num) * | |
2653 | phba->params.defpdu_data_sz); | |
2654 | ||
2655 | num_async_pdu_data_sgl_pages = | |
2656 | PAGES_REQUIRED(BEISCSI_GET_CID_COUNT( | |
2657 | phba, ulp_num) * | |
2658 | sizeof(struct phys_addr)); | |
2659 | ||
a129d92f JK |
2660 | mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 + |
2661 | (ulp_num * MEM_DESCR_OFFSET)); | |
2662 | phba->mem_req[mem_descr_index] = | |
2663 | BEISCSI_GET_CID_COUNT(phba, ulp_num) * | |
2664 | BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE; | |
2665 | ||
8a86e833 JK |
2666 | mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 + |
2667 | (ulp_num * MEM_DESCR_OFFSET)); | |
2668 | phba->mem_req[mem_descr_index] = | |
2669 | num_async_pdu_buf_pages * | |
2670 | PAGE_SIZE; | |
2671 | ||
2672 | mem_descr_index = (HWI_MEM_ASYNC_DATA_BUF_ULP0 + | |
2673 | (ulp_num * MEM_DESCR_OFFSET)); | |
2674 | phba->mem_req[mem_descr_index] = | |
2675 | num_async_pdu_data_pages * | |
2676 | PAGE_SIZE; | |
2677 | ||
2678 | mem_descr_index = (HWI_MEM_ASYNC_HEADER_RING_ULP0 + | |
2679 | (ulp_num * MEM_DESCR_OFFSET)); | |
2680 | phba->mem_req[mem_descr_index] = | |
2681 | num_async_pdu_buf_sgl_pages * | |
2682 | PAGE_SIZE; | |
2683 | ||
2684 | mem_descr_index = (HWI_MEM_ASYNC_DATA_RING_ULP0 + | |
2685 | (ulp_num * MEM_DESCR_OFFSET)); | |
2686 | phba->mem_req[mem_descr_index] = | |
2687 | num_async_pdu_data_sgl_pages * | |
2688 | PAGE_SIZE; | |
2689 | ||
2690 | mem_descr_index = (HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 + | |
2691 | (ulp_num * MEM_DESCR_OFFSET)); | |
2692 | phba->mem_req[mem_descr_index] = | |
2693 | BEISCSI_GET_CID_COUNT(phba, ulp_num) * | |
2694 | sizeof(struct async_pdu_handle); | |
2695 | ||
2696 | mem_descr_index = (HWI_MEM_ASYNC_DATA_HANDLE_ULP0 + | |
2697 | (ulp_num * MEM_DESCR_OFFSET)); | |
2698 | phba->mem_req[mem_descr_index] = | |
2699 | BEISCSI_GET_CID_COUNT(phba, ulp_num) * | |
2700 | sizeof(struct async_pdu_handle); | |
2701 | ||
2702 | mem_descr_index = (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 + | |
2703 | (ulp_num * MEM_DESCR_OFFSET)); | |
2704 | phba->mem_req[mem_descr_index] = | |
2705 | sizeof(struct hwi_async_pdu_context) + | |
2706 | (BEISCSI_GET_CID_COUNT(phba, ulp_num) * | |
2707 | sizeof(struct hwi_async_entry)); | |
2708 | } | |
2709 | } | |
6733b39a JK |
2710 | } |
2711 | ||
2712 | static int beiscsi_alloc_mem(struct beiscsi_hba *phba) | |
2713 | { | |
6733b39a | 2714 | dma_addr_t bus_add; |
a7909b39 JK |
2715 | struct hwi_controller *phwi_ctrlr; |
2716 | struct be_mem_descriptor *mem_descr; | |
6733b39a JK |
2717 | struct mem_array *mem_arr, *mem_arr_orig; |
2718 | unsigned int i, j, alloc_size, curr_alloc_size; | |
2719 | ||
3ec78271 | 2720 | phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL); |
6733b39a JK |
2721 | if (!phba->phwi_ctrlr) |
2722 | return -ENOMEM; | |
2723 | ||
a7909b39 JK |
2724 | /* Allocate memory for wrb_context */ |
2725 | phwi_ctrlr = phba->phwi_ctrlr; | |
2726 | phwi_ctrlr->wrb_context = kzalloc(sizeof(struct hwi_wrb_context) * | |
2727 | phba->params.cxns_per_ctrl, | |
2728 | GFP_KERNEL); | |
0c88740d ML |
2729 | if (!phwi_ctrlr->wrb_context) { |
2730 | kfree(phba->phwi_ctrlr); | |
a7909b39 | 2731 | return -ENOMEM; |
0c88740d | 2732 | } |
a7909b39 | 2733 | |
6733b39a JK |
2734 | phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr), |
2735 | GFP_KERNEL); | |
2736 | if (!phba->init_mem) { | |
a7909b39 | 2737 | kfree(phwi_ctrlr->wrb_context); |
6733b39a JK |
2738 | kfree(phba->phwi_ctrlr); |
2739 | return -ENOMEM; | |
2740 | } | |
2741 | ||
2742 | mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT, | |
2743 | GFP_KERNEL); | |
2744 | if (!mem_arr_orig) { | |
2745 | kfree(phba->init_mem); | |
a7909b39 | 2746 | kfree(phwi_ctrlr->wrb_context); |
6733b39a JK |
2747 | kfree(phba->phwi_ctrlr); |
2748 | return -ENOMEM; | |
2749 | } | |
2750 | ||
2751 | mem_descr = phba->init_mem; | |
2752 | for (i = 0; i < SE_MEM_MAX; i++) { | |
8a86e833 JK |
2753 | if (!phba->mem_req[i]) { |
2754 | mem_descr->mem_array = NULL; | |
2755 | mem_descr++; | |
2756 | continue; | |
2757 | } | |
2758 | ||
6733b39a JK |
2759 | j = 0; |
2760 | mem_arr = mem_arr_orig; | |
2761 | alloc_size = phba->mem_req[i]; | |
2762 | memset(mem_arr, 0, sizeof(struct mem_array) * | |
2763 | BEISCSI_MAX_FRAGS_INIT); | |
2764 | curr_alloc_size = min(be_max_phys_size * 1024, alloc_size); | |
2765 | do { | |
2766 | mem_arr->virtual_address = pci_alloc_consistent( | |
2767 | phba->pcidev, | |
2768 | curr_alloc_size, | |
2769 | &bus_add); | |
2770 | if (!mem_arr->virtual_address) { | |
2771 | if (curr_alloc_size <= BE_MIN_MEM_SIZE) | |
2772 | goto free_mem; | |
2773 | if (curr_alloc_size - | |
2774 | rounddown_pow_of_two(curr_alloc_size)) | |
2775 | curr_alloc_size = rounddown_pow_of_two | |
2776 | (curr_alloc_size); | |
2777 | else | |
2778 | curr_alloc_size = curr_alloc_size / 2; | |
2779 | } else { | |
2780 | mem_arr->bus_address.u. | |
2781 | a64.address = (__u64) bus_add; | |
2782 | mem_arr->size = curr_alloc_size; | |
2783 | alloc_size -= curr_alloc_size; | |
2784 | curr_alloc_size = min(be_max_phys_size * | |
2785 | 1024, alloc_size); | |
2786 | j++; | |
2787 | mem_arr++; | |
2788 | } | |
2789 | } while (alloc_size); | |
2790 | mem_descr->num_elements = j; | |
2791 | mem_descr->size_in_bytes = phba->mem_req[i]; | |
2792 | mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j, | |
2793 | GFP_KERNEL); | |
2794 | if (!mem_descr->mem_array) | |
2795 | goto free_mem; | |
2796 | ||
2797 | memcpy(mem_descr->mem_array, mem_arr_orig, | |
2798 | sizeof(struct mem_array) * j); | |
2799 | mem_descr++; | |
2800 | } | |
2801 | kfree(mem_arr_orig); | |
2802 | return 0; | |
2803 | free_mem: | |
2804 | mem_descr->num_elements = j; | |
2805 | while ((i) || (j)) { | |
2806 | for (j = mem_descr->num_elements; j > 0; j--) { | |
2807 | pci_free_consistent(phba->pcidev, | |
2808 | mem_descr->mem_array[j - 1].size, | |
2809 | mem_descr->mem_array[j - 1]. | |
2810 | virtual_address, | |
457ff3b7 JK |
2811 | (unsigned long)mem_descr-> |
2812 | mem_array[j - 1]. | |
6733b39a JK |
2813 | bus_address.u.a64.address); |
2814 | } | |
2815 | if (i) { | |
2816 | i--; | |
2817 | kfree(mem_descr->mem_array); | |
2818 | mem_descr--; | |
2819 | } | |
2820 | } | |
2821 | kfree(mem_arr_orig); | |
2822 | kfree(phba->init_mem); | |
a7909b39 | 2823 | kfree(phba->phwi_ctrlr->wrb_context); |
6733b39a JK |
2824 | kfree(phba->phwi_ctrlr); |
2825 | return -ENOMEM; | |
2826 | } | |
2827 | ||
2828 | static int beiscsi_get_memory(struct beiscsi_hba *phba) | |
2829 | { | |
2830 | beiscsi_find_mem_req(phba); | |
2831 | return beiscsi_alloc_mem(phba); | |
2832 | } | |
2833 | ||
2834 | static void iscsi_init_global_templates(struct beiscsi_hba *phba) | |
2835 | { | |
2836 | struct pdu_data_out *pdata_out; | |
2837 | struct pdu_nop_out *pnop_out; | |
2838 | struct be_mem_descriptor *mem_descr; | |
2839 | ||
2840 | mem_descr = phba->init_mem; | |
2841 | mem_descr += ISCSI_MEM_GLOBAL_HEADER; | |
2842 | pdata_out = | |
2843 | (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address; | |
2844 | memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE); | |
2845 | ||
2846 | AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out, | |
2847 | IIOC_SCSI_DATA); | |
2848 | ||
2849 | pnop_out = | |
2850 | (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0]. | |
2851 | virtual_address + BE_ISCSI_PDU_HEADER_SIZE); | |
2852 | ||
2853 | memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE); | |
2854 | AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF); | |
2855 | AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1); | |
2856 | AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0); | |
2857 | } | |
2858 | ||
3ec78271 | 2859 | static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba) |
6733b39a JK |
2860 | { |
2861 | struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb; | |
a7909b39 | 2862 | struct hwi_context_memory *phwi_ctxt; |
3ec78271 | 2863 | struct wrb_handle *pwrb_handle = NULL; |
6733b39a JK |
2864 | struct hwi_controller *phwi_ctrlr; |
2865 | struct hwi_wrb_context *pwrb_context; | |
3ec78271 JK |
2866 | struct iscsi_wrb *pwrb = NULL; |
2867 | unsigned int num_cxn_wrbh = 0; | |
2868 | unsigned int num_cxn_wrb = 0, j, idx = 0, index; | |
6733b39a JK |
2869 | |
2870 | mem_descr_wrbh = phba->init_mem; | |
2871 | mem_descr_wrbh += HWI_MEM_WRBH; | |
2872 | ||
2873 | mem_descr_wrb = phba->init_mem; | |
2874 | mem_descr_wrb += HWI_MEM_WRB; | |
6733b39a JK |
2875 | phwi_ctrlr = phba->phwi_ctrlr; |
2876 | ||
a7909b39 JK |
2877 | /* Allocate memory for WRBQ */ |
2878 | phwi_ctxt = phwi_ctrlr->phwi_ctxt; | |
2879 | phwi_ctxt->be_wrbq = kzalloc(sizeof(struct be_queue_info) * | |
843ae752 | 2880 | phba->params.cxns_per_ctrl, |
a7909b39 JK |
2881 | GFP_KERNEL); |
2882 | if (!phwi_ctxt->be_wrbq) { | |
2883 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
2884 | "BM_%d : WRBQ Mem Alloc Failed\n"); | |
2885 | return -ENOMEM; | |
2886 | } | |
2887 | ||
2888 | for (index = 0; index < phba->params.cxns_per_ctrl; index++) { | |
6733b39a | 2889 | pwrb_context = &phwi_ctrlr->wrb_context[index]; |
6733b39a JK |
2890 | pwrb_context->pwrb_handle_base = |
2891 | kzalloc(sizeof(struct wrb_handle *) * | |
2892 | phba->params.wrbs_per_cxn, GFP_KERNEL); | |
3ec78271 | 2893 | if (!pwrb_context->pwrb_handle_base) { |
99bc5d55 JSJ |
2894 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
2895 | "BM_%d : Mem Alloc Failed. Failing to load\n"); | |
3ec78271 JK |
2896 | goto init_wrb_hndl_failed; |
2897 | } | |
6733b39a JK |
2898 | pwrb_context->pwrb_handle_basestd = |
2899 | kzalloc(sizeof(struct wrb_handle *) * | |
2900 | phba->params.wrbs_per_cxn, GFP_KERNEL); | |
3ec78271 | 2901 | if (!pwrb_context->pwrb_handle_basestd) { |
99bc5d55 JSJ |
2902 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
2903 | "BM_%d : Mem Alloc Failed. Failing to load\n"); | |
3ec78271 JK |
2904 | goto init_wrb_hndl_failed; |
2905 | } | |
2906 | if (!num_cxn_wrbh) { | |
2907 | pwrb_handle = | |
2908 | mem_descr_wrbh->mem_array[idx].virtual_address; | |
2909 | num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) / | |
2910 | ((sizeof(struct wrb_handle)) * | |
2911 | phba->params.wrbs_per_cxn)); | |
2912 | idx++; | |
2913 | } | |
2914 | pwrb_context->alloc_index = 0; | |
2915 | pwrb_context->wrb_handles_available = 0; | |
2916 | pwrb_context->free_index = 0; | |
2917 | ||
6733b39a | 2918 | if (num_cxn_wrbh) { |
6733b39a JK |
2919 | for (j = 0; j < phba->params.wrbs_per_cxn; j++) { |
2920 | pwrb_context->pwrb_handle_base[j] = pwrb_handle; | |
2921 | pwrb_context->pwrb_handle_basestd[j] = | |
2922 | pwrb_handle; | |
2923 | pwrb_context->wrb_handles_available++; | |
bfead3b2 | 2924 | pwrb_handle->wrb_index = j; |
6733b39a JK |
2925 | pwrb_handle++; |
2926 | } | |
6733b39a JK |
2927 | num_cxn_wrbh--; |
2928 | } | |
f64d92e6 | 2929 | spin_lock_init(&pwrb_context->wrb_lock); |
6733b39a JK |
2930 | } |
2931 | idx = 0; | |
a7909b39 | 2932 | for (index = 0; index < phba->params.cxns_per_ctrl; index++) { |
6733b39a | 2933 | pwrb_context = &phwi_ctrlr->wrb_context[index]; |
3ec78271 | 2934 | if (!num_cxn_wrb) { |
6733b39a | 2935 | pwrb = mem_descr_wrb->mem_array[idx].virtual_address; |
7c56533c | 2936 | num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) / |
3ec78271 JK |
2937 | ((sizeof(struct iscsi_wrb) * |
2938 | phba->params.wrbs_per_cxn)); | |
2939 | idx++; | |
2940 | } | |
2941 | ||
2942 | if (num_cxn_wrb) { | |
6733b39a JK |
2943 | for (j = 0; j < phba->params.wrbs_per_cxn; j++) { |
2944 | pwrb_handle = pwrb_context->pwrb_handle_base[j]; | |
2945 | pwrb_handle->pwrb = pwrb; | |
2946 | pwrb++; | |
2947 | } | |
2948 | num_cxn_wrb--; | |
2949 | } | |
2950 | } | |
3ec78271 JK |
2951 | return 0; |
2952 | init_wrb_hndl_failed: | |
2953 | for (j = index; j > 0; j--) { | |
2954 | pwrb_context = &phwi_ctrlr->wrb_context[j]; | |
2955 | kfree(pwrb_context->pwrb_handle_base); | |
2956 | kfree(pwrb_context->pwrb_handle_basestd); | |
2957 | } | |
2958 | return -ENOMEM; | |
6733b39a JK |
2959 | } |
2960 | ||
a7909b39 | 2961 | static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba) |
6733b39a | 2962 | { |
8a86e833 | 2963 | uint8_t ulp_num; |
6733b39a JK |
2964 | struct hwi_controller *phwi_ctrlr; |
2965 | struct hba_parameters *p = &phba->params; | |
2966 | struct hwi_async_pdu_context *pasync_ctx; | |
2967 | struct async_pdu_handle *pasync_header_h, *pasync_data_h; | |
dc63aac6 | 2968 | unsigned int index, idx, num_per_mem, num_async_data; |
6733b39a JK |
2969 | struct be_mem_descriptor *mem_descr; |
2970 | ||
8a86e833 JK |
2971 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
2972 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { | |
6733b39a | 2973 | |
8a86e833 JK |
2974 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; |
2975 | mem_descr += (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 + | |
2976 | (ulp_num * MEM_DESCR_OFFSET)); | |
2977 | ||
2978 | phwi_ctrlr = phba->phwi_ctrlr; | |
2979 | phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num] = | |
2980 | (struct hwi_async_pdu_context *) | |
2981 | mem_descr->mem_array[0].virtual_address; | |
2982 | ||
2983 | pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num]; | |
2984 | memset(pasync_ctx, 0, sizeof(*pasync_ctx)); | |
2985 | ||
2986 | pasync_ctx->async_entry = | |
2987 | (struct hwi_async_entry *) | |
2988 | ((long unsigned int)pasync_ctx + | |
2989 | sizeof(struct hwi_async_pdu_context)); | |
2990 | ||
2991 | pasync_ctx->num_entries = BEISCSI_GET_CID_COUNT(phba, | |
2992 | ulp_num); | |
2993 | pasync_ctx->buffer_size = p->defpdu_hdr_sz; | |
2994 | ||
2995 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; | |
2996 | mem_descr += HWI_MEM_ASYNC_HEADER_BUF_ULP0 + | |
2997 | (ulp_num * MEM_DESCR_OFFSET); | |
2998 | if (mem_descr->mem_array[0].virtual_address) { | |
2999 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
3000 | "BM_%d : hwi_init_async_pdu_ctx" | |
3001 | " HWI_MEM_ASYNC_HEADER_BUF_ULP%d va=%p\n", | |
3002 | ulp_num, | |
3003 | mem_descr->mem_array[0]. | |
3004 | virtual_address); | |
3005 | } else | |
3006 | beiscsi_log(phba, KERN_WARNING, | |
3007 | BEISCSI_LOG_INIT, | |
3008 | "BM_%d : No Virtual address for ULP : %d\n", | |
3009 | ulp_num); | |
3010 | ||
3011 | pasync_ctx->async_header.va_base = | |
6733b39a | 3012 | mem_descr->mem_array[0].virtual_address; |
6733b39a | 3013 | |
8a86e833 JK |
3014 | pasync_ctx->async_header.pa_base.u.a64.address = |
3015 | mem_descr->mem_array[0]. | |
3016 | bus_address.u.a64.address; | |
6733b39a | 3017 | |
8a86e833 JK |
3018 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; |
3019 | mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 + | |
3020 | (ulp_num * MEM_DESCR_OFFSET); | |
3021 | if (mem_descr->mem_array[0].virtual_address) { | |
3022 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
3023 | "BM_%d : hwi_init_async_pdu_ctx" | |
3024 | " HWI_MEM_ASYNC_HEADER_RING_ULP%d va=%p\n", | |
3025 | ulp_num, | |
3026 | mem_descr->mem_array[0]. | |
3027 | virtual_address); | |
3028 | } else | |
3029 | beiscsi_log(phba, KERN_WARNING, | |
3030 | BEISCSI_LOG_INIT, | |
3031 | "BM_%d : No Virtual address for ULP : %d\n", | |
3032 | ulp_num); | |
3033 | ||
3034 | pasync_ctx->async_header.ring_base = | |
3035 | mem_descr->mem_array[0].virtual_address; | |
6733b39a | 3036 | |
8a86e833 JK |
3037 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; |
3038 | mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 + | |
3039 | (ulp_num * MEM_DESCR_OFFSET); | |
3040 | if (mem_descr->mem_array[0].virtual_address) { | |
3041 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
3042 | "BM_%d : hwi_init_async_pdu_ctx" | |
3043 | " HWI_MEM_ASYNC_HEADER_HANDLE_ULP%d va=%p\n", | |
3044 | ulp_num, | |
3045 | mem_descr->mem_array[0]. | |
3046 | virtual_address); | |
3047 | } else | |
3048 | beiscsi_log(phba, KERN_WARNING, | |
3049 | BEISCSI_LOG_INIT, | |
3050 | "BM_%d : No Virtual address for ULP : %d\n", | |
3051 | ulp_num); | |
3052 | ||
3053 | pasync_ctx->async_header.handle_base = | |
3054 | mem_descr->mem_array[0].virtual_address; | |
3055 | pasync_ctx->async_header.writables = 0; | |
3056 | INIT_LIST_HEAD(&pasync_ctx->async_header.free_list); | |
3057 | ||
3058 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; | |
3059 | mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 + | |
3060 | (ulp_num * MEM_DESCR_OFFSET); | |
3061 | if (mem_descr->mem_array[0].virtual_address) { | |
3062 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
3063 | "BM_%d : hwi_init_async_pdu_ctx" | |
3064 | " HWI_MEM_ASYNC_DATA_RING_ULP%d va=%p\n", | |
3065 | ulp_num, | |
3066 | mem_descr->mem_array[0]. | |
3067 | virtual_address); | |
3068 | } else | |
3069 | beiscsi_log(phba, KERN_WARNING, | |
3070 | BEISCSI_LOG_INIT, | |
3071 | "BM_%d : No Virtual address for ULP : %d\n", | |
3072 | ulp_num); | |
3073 | ||
3074 | pasync_ctx->async_data.ring_base = | |
3075 | mem_descr->mem_array[0].virtual_address; | |
6733b39a | 3076 | |
8a86e833 JK |
3077 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; |
3078 | mem_descr += HWI_MEM_ASYNC_DATA_HANDLE_ULP0 + | |
3079 | (ulp_num * MEM_DESCR_OFFSET); | |
3080 | if (!mem_descr->mem_array[0].virtual_address) | |
3081 | beiscsi_log(phba, KERN_WARNING, | |
3082 | BEISCSI_LOG_INIT, | |
3083 | "BM_%d : No Virtual address for ULP : %d\n", | |
3084 | ulp_num); | |
99bc5d55 | 3085 | |
8a86e833 JK |
3086 | pasync_ctx->async_data.handle_base = |
3087 | mem_descr->mem_array[0].virtual_address; | |
3088 | pasync_ctx->async_data.writables = 0; | |
3089 | INIT_LIST_HEAD(&pasync_ctx->async_data.free_list); | |
3090 | ||
3091 | pasync_header_h = | |
3092 | (struct async_pdu_handle *) | |
3093 | pasync_ctx->async_header.handle_base; | |
3094 | pasync_data_h = | |
3095 | (struct async_pdu_handle *) | |
3096 | pasync_ctx->async_data.handle_base; | |
3097 | ||
3098 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; | |
3099 | mem_descr += HWI_MEM_ASYNC_DATA_BUF_ULP0 + | |
3100 | (ulp_num * MEM_DESCR_OFFSET); | |
3101 | if (mem_descr->mem_array[0].virtual_address) { | |
3102 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
3103 | "BM_%d : hwi_init_async_pdu_ctx" | |
3104 | " HWI_MEM_ASYNC_DATA_BUF_ULP%d va=%p\n", | |
3105 | ulp_num, | |
3106 | mem_descr->mem_array[0]. | |
3107 | virtual_address); | |
3108 | } else | |
3109 | beiscsi_log(phba, KERN_WARNING, | |
3110 | BEISCSI_LOG_INIT, | |
3111 | "BM_%d : No Virtual address for ULP : %d\n", | |
3112 | ulp_num); | |
3113 | ||
3114 | idx = 0; | |
dc63aac6 JK |
3115 | pasync_ctx->async_data.va_base = |
3116 | mem_descr->mem_array[idx].virtual_address; | |
3117 | pasync_ctx->async_data.pa_base.u.a64.address = | |
3118 | mem_descr->mem_array[idx]. | |
3119 | bus_address.u.a64.address; | |
3120 | ||
3121 | num_async_data = ((mem_descr->mem_array[idx].size) / | |
3122 | phba->params.defpdu_data_sz); | |
8a86e833 | 3123 | num_per_mem = 0; |
6733b39a | 3124 | |
8a86e833 JK |
3125 | for (index = 0; index < BEISCSI_GET_CID_COUNT |
3126 | (phba, ulp_num); index++) { | |
3127 | pasync_header_h->cri = -1; | |
3128 | pasync_header_h->index = (char)index; | |
3129 | INIT_LIST_HEAD(&pasync_header_h->link); | |
3130 | pasync_header_h->pbuffer = | |
3131 | (void *)((unsigned long) | |
3132 | (pasync_ctx-> | |
3133 | async_header.va_base) + | |
3134 | (p->defpdu_hdr_sz * index)); | |
3135 | ||
3136 | pasync_header_h->pa.u.a64.address = | |
3137 | pasync_ctx->async_header.pa_base.u.a64. | |
3138 | address + (p->defpdu_hdr_sz * index); | |
3139 | ||
3140 | list_add_tail(&pasync_header_h->link, | |
3141 | &pasync_ctx->async_header. | |
3142 | free_list); | |
3143 | pasync_header_h++; | |
3144 | pasync_ctx->async_header.free_entries++; | |
3145 | pasync_ctx->async_header.writables++; | |
3146 | ||
3147 | INIT_LIST_HEAD(&pasync_ctx->async_entry[index]. | |
3148 | wait_queue.list); | |
3149 | INIT_LIST_HEAD(&pasync_ctx->async_entry[index]. | |
3150 | header_busy_list); | |
3151 | pasync_data_h->cri = -1; | |
3152 | pasync_data_h->index = (char)index; | |
3153 | INIT_LIST_HEAD(&pasync_data_h->link); | |
3154 | ||
3155 | if (!num_async_data) { | |
3156 | num_per_mem = 0; | |
3157 | idx++; | |
3158 | pasync_ctx->async_data.va_base = | |
3159 | mem_descr->mem_array[idx]. | |
3160 | virtual_address; | |
3161 | pasync_ctx->async_data.pa_base.u. | |
3162 | a64.address = | |
3163 | mem_descr->mem_array[idx]. | |
3164 | bus_address.u.a64.address; | |
3165 | num_async_data = | |
3166 | ((mem_descr->mem_array[idx]. | |
3167 | size) / | |
3168 | phba->params.defpdu_data_sz); | |
3169 | } | |
3170 | pasync_data_h->pbuffer = | |
3171 | (void *)((unsigned long) | |
3172 | (pasync_ctx->async_data.va_base) + | |
3173 | (p->defpdu_data_sz * num_per_mem)); | |
3174 | ||
3175 | pasync_data_h->pa.u.a64.address = | |
3176 | pasync_ctx->async_data.pa_base.u.a64. | |
3177 | address + (p->defpdu_data_sz * | |
3178 | num_per_mem); | |
3179 | num_per_mem++; | |
3180 | num_async_data--; | |
3181 | ||
3182 | list_add_tail(&pasync_data_h->link, | |
3183 | &pasync_ctx->async_data. | |
3184 | free_list); | |
3185 | pasync_data_h++; | |
3186 | pasync_ctx->async_data.free_entries++; | |
3187 | pasync_ctx->async_data.writables++; | |
3188 | ||
3189 | INIT_LIST_HEAD(&pasync_ctx->async_entry[index]. | |
3190 | data_busy_list); | |
3191 | } | |
6733b39a | 3192 | |
8a86e833 JK |
3193 | pasync_ctx->async_header.host_write_ptr = 0; |
3194 | pasync_ctx->async_header.ep_read_ptr = -1; | |
3195 | pasync_ctx->async_data.host_write_ptr = 0; | |
3196 | pasync_ctx->async_data.ep_read_ptr = -1; | |
3197 | } | |
6733b39a JK |
3198 | } |
3199 | ||
a7909b39 | 3200 | return 0; |
6733b39a JK |
3201 | } |
3202 | ||
3203 | static int | |
3204 | be_sgl_create_contiguous(void *virtual_address, | |
3205 | u64 physical_address, u32 length, | |
3206 | struct be_dma_mem *sgl) | |
3207 | { | |
3208 | WARN_ON(!virtual_address); | |
3209 | WARN_ON(!physical_address); | |
dd29dae0 | 3210 | WARN_ON(!length); |
6733b39a JK |
3211 | WARN_ON(!sgl); |
3212 | ||
3213 | sgl->va = virtual_address; | |
457ff3b7 | 3214 | sgl->dma = (unsigned long)physical_address; |
6733b39a JK |
3215 | sgl->size = length; |
3216 | ||
3217 | return 0; | |
3218 | } | |
3219 | ||
3220 | static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl) | |
3221 | { | |
3222 | memset(sgl, 0, sizeof(*sgl)); | |
3223 | } | |
3224 | ||
3225 | static void | |
3226 | hwi_build_be_sgl_arr(struct beiscsi_hba *phba, | |
3227 | struct mem_array *pmem, struct be_dma_mem *sgl) | |
3228 | { | |
3229 | if (sgl->va) | |
3230 | be_sgl_destroy_contiguous(sgl); | |
3231 | ||
3232 | be_sgl_create_contiguous(pmem->virtual_address, | |
3233 | pmem->bus_address.u.a64.address, | |
3234 | pmem->size, sgl); | |
3235 | } | |
3236 | ||
3237 | static void | |
3238 | hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba, | |
3239 | struct mem_array *pmem, struct be_dma_mem *sgl) | |
3240 | { | |
3241 | if (sgl->va) | |
3242 | be_sgl_destroy_contiguous(sgl); | |
3243 | ||
3244 | be_sgl_create_contiguous((unsigned char *)pmem->virtual_address, | |
3245 | pmem->bus_address.u.a64.address, | |
3246 | pmem->size, sgl); | |
3247 | } | |
3248 | ||
3249 | static int be_fill_queue(struct be_queue_info *q, | |
3250 | u16 len, u16 entry_size, void *vaddress) | |
3251 | { | |
3252 | struct be_dma_mem *mem = &q->dma_mem; | |
3253 | ||
3254 | memset(q, 0, sizeof(*q)); | |
3255 | q->len = len; | |
3256 | q->entry_size = entry_size; | |
3257 | mem->size = len * entry_size; | |
3258 | mem->va = vaddress; | |
3259 | if (!mem->va) | |
3260 | return -ENOMEM; | |
3261 | memset(mem->va, 0, mem->size); | |
3262 | return 0; | |
3263 | } | |
3264 | ||
bfead3b2 | 3265 | static int beiscsi_create_eqs(struct beiscsi_hba *phba, |
6733b39a JK |
3266 | struct hwi_context_memory *phwi_context) |
3267 | { | |
bfead3b2 | 3268 | unsigned int i, num_eq_pages; |
99bc5d55 | 3269 | int ret = 0, eq_for_mcc; |
6733b39a JK |
3270 | struct be_queue_info *eq; |
3271 | struct be_dma_mem *mem; | |
6733b39a | 3272 | void *eq_vaddress; |
bfead3b2 | 3273 | dma_addr_t paddr; |
6733b39a | 3274 | |
bfead3b2 JK |
3275 | num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \ |
3276 | sizeof(struct be_eq_entry)); | |
6733b39a | 3277 | |
bfead3b2 JK |
3278 | if (phba->msix_enabled) |
3279 | eq_for_mcc = 1; | |
3280 | else | |
3281 | eq_for_mcc = 0; | |
3282 | for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { | |
3283 | eq = &phwi_context->be_eq[i].q; | |
3284 | mem = &eq->dma_mem; | |
3285 | phwi_context->be_eq[i].phba = phba; | |
3286 | eq_vaddress = pci_alloc_consistent(phba->pcidev, | |
3287 | num_eq_pages * PAGE_SIZE, | |
3288 | &paddr); | |
3289 | if (!eq_vaddress) | |
3290 | goto create_eq_error; | |
3291 | ||
3292 | mem->va = eq_vaddress; | |
3293 | ret = be_fill_queue(eq, phba->params.num_eq_entries, | |
3294 | sizeof(struct be_eq_entry), eq_vaddress); | |
3295 | if (ret) { | |
99bc5d55 JSJ |
3296 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3297 | "BM_%d : be_fill_queue Failed for EQ\n"); | |
bfead3b2 JK |
3298 | goto create_eq_error; |
3299 | } | |
6733b39a | 3300 | |
bfead3b2 JK |
3301 | mem->dma = paddr; |
3302 | ret = beiscsi_cmd_eq_create(&phba->ctrl, eq, | |
3303 | phwi_context->cur_eqd); | |
3304 | if (ret) { | |
99bc5d55 JSJ |
3305 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3306 | "BM_%d : beiscsi_cmd_eq_create" | |
3307 | "Failed for EQ\n"); | |
bfead3b2 JK |
3308 | goto create_eq_error; |
3309 | } | |
99bc5d55 JSJ |
3310 | |
3311 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
3312 | "BM_%d : eqid = %d\n", | |
3313 | phwi_context->be_eq[i].q.id); | |
6733b39a | 3314 | } |
6733b39a | 3315 | return 0; |
bfead3b2 | 3316 | create_eq_error: |
107dfcba | 3317 | for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { |
bfead3b2 JK |
3318 | eq = &phwi_context->be_eq[i].q; |
3319 | mem = &eq->dma_mem; | |
3320 | if (mem->va) | |
3321 | pci_free_consistent(phba->pcidev, num_eq_pages | |
3322 | * PAGE_SIZE, | |
3323 | mem->va, mem->dma); | |
3324 | } | |
3325 | return ret; | |
6733b39a JK |
3326 | } |
3327 | ||
bfead3b2 | 3328 | static int beiscsi_create_cqs(struct beiscsi_hba *phba, |
6733b39a JK |
3329 | struct hwi_context_memory *phwi_context) |
3330 | { | |
bfead3b2 | 3331 | unsigned int i, num_cq_pages; |
99bc5d55 | 3332 | int ret = 0; |
6733b39a JK |
3333 | struct be_queue_info *cq, *eq; |
3334 | struct be_dma_mem *mem; | |
bfead3b2 | 3335 | struct be_eq_obj *pbe_eq; |
6733b39a | 3336 | void *cq_vaddress; |
bfead3b2 | 3337 | dma_addr_t paddr; |
6733b39a | 3338 | |
bfead3b2 JK |
3339 | num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \ |
3340 | sizeof(struct sol_cqe)); | |
6733b39a | 3341 | |
bfead3b2 JK |
3342 | for (i = 0; i < phba->num_cpus; i++) { |
3343 | cq = &phwi_context->be_cq[i]; | |
3344 | eq = &phwi_context->be_eq[i].q; | |
3345 | pbe_eq = &phwi_context->be_eq[i]; | |
3346 | pbe_eq->cq = cq; | |
3347 | pbe_eq->phba = phba; | |
3348 | mem = &cq->dma_mem; | |
3349 | cq_vaddress = pci_alloc_consistent(phba->pcidev, | |
3350 | num_cq_pages * PAGE_SIZE, | |
3351 | &paddr); | |
3352 | if (!cq_vaddress) | |
3353 | goto create_cq_error; | |
7da50879 | 3354 | ret = be_fill_queue(cq, phba->params.num_cq_entries, |
bfead3b2 JK |
3355 | sizeof(struct sol_cqe), cq_vaddress); |
3356 | if (ret) { | |
99bc5d55 JSJ |
3357 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3358 | "BM_%d : be_fill_queue Failed " | |
3359 | "for ISCSI CQ\n"); | |
bfead3b2 JK |
3360 | goto create_cq_error; |
3361 | } | |
3362 | ||
3363 | mem->dma = paddr; | |
3364 | ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false, | |
3365 | false, 0); | |
3366 | if (ret) { | |
99bc5d55 JSJ |
3367 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3368 | "BM_%d : beiscsi_cmd_eq_create" | |
3369 | "Failed for ISCSI CQ\n"); | |
bfead3b2 JK |
3370 | goto create_cq_error; |
3371 | } | |
99bc5d55 JSJ |
3372 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
3373 | "BM_%d : iscsi cq_id is %d for eq_id %d\n" | |
3374 | "iSCSI CQ CREATED\n", cq->id, eq->id); | |
6733b39a | 3375 | } |
6733b39a | 3376 | return 0; |
bfead3b2 JK |
3377 | |
3378 | create_cq_error: | |
3379 | for (i = 0; i < phba->num_cpus; i++) { | |
3380 | cq = &phwi_context->be_cq[i]; | |
3381 | mem = &cq->dma_mem; | |
3382 | if (mem->va) | |
3383 | pci_free_consistent(phba->pcidev, num_cq_pages | |
3384 | * PAGE_SIZE, | |
3385 | mem->va, mem->dma); | |
3386 | } | |
3387 | return ret; | |
3388 | ||
6733b39a JK |
3389 | } |
3390 | ||
3391 | static int | |
3392 | beiscsi_create_def_hdr(struct beiscsi_hba *phba, | |
3393 | struct hwi_context_memory *phwi_context, | |
3394 | struct hwi_controller *phwi_ctrlr, | |
8a86e833 | 3395 | unsigned int def_pdu_ring_sz, uint8_t ulp_num) |
6733b39a JK |
3396 | { |
3397 | unsigned int idx; | |
3398 | int ret; | |
3399 | struct be_queue_info *dq, *cq; | |
3400 | struct be_dma_mem *mem; | |
3401 | struct be_mem_descriptor *mem_descr; | |
3402 | void *dq_vaddress; | |
3403 | ||
3404 | idx = 0; | |
8a86e833 | 3405 | dq = &phwi_context->be_def_hdrq[ulp_num]; |
bfead3b2 | 3406 | cq = &phwi_context->be_cq[0]; |
6733b39a JK |
3407 | mem = &dq->dma_mem; |
3408 | mem_descr = phba->init_mem; | |
8a86e833 JK |
3409 | mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 + |
3410 | (ulp_num * MEM_DESCR_OFFSET); | |
6733b39a JK |
3411 | dq_vaddress = mem_descr->mem_array[idx].virtual_address; |
3412 | ret = be_fill_queue(dq, mem_descr->mem_array[0].size / | |
3413 | sizeof(struct phys_addr), | |
3414 | sizeof(struct phys_addr), dq_vaddress); | |
3415 | if (ret) { | |
99bc5d55 | 3416 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
8a86e833 JK |
3417 | "BM_%d : be_fill_queue Failed for DEF PDU HDR on ULP : %d\n", |
3418 | ulp_num); | |
3419 | ||
6733b39a JK |
3420 | return ret; |
3421 | } | |
457ff3b7 JK |
3422 | mem->dma = (unsigned long)mem_descr->mem_array[idx]. |
3423 | bus_address.u.a64.address; | |
6733b39a JK |
3424 | ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq, |
3425 | def_pdu_ring_sz, | |
8a86e833 JK |
3426 | phba->params.defpdu_hdr_sz, |
3427 | BEISCSI_DEFQ_HDR, ulp_num); | |
6733b39a | 3428 | if (ret) { |
99bc5d55 | 3429 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
8a86e833 JK |
3430 | "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR on ULP : %d\n", |
3431 | ulp_num); | |
3432 | ||
6733b39a JK |
3433 | return ret; |
3434 | } | |
99bc5d55 | 3435 | |
8a86e833 JK |
3436 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
3437 | "BM_%d : iscsi hdr def pdu id for ULP : %d is %d\n", | |
3438 | ulp_num, | |
3439 | phwi_context->be_def_hdrq[ulp_num].id); | |
3440 | hwi_post_async_buffers(phba, BEISCSI_DEFQ_HDR, ulp_num); | |
6733b39a JK |
3441 | return 0; |
3442 | } | |
3443 | ||
3444 | static int | |
3445 | beiscsi_create_def_data(struct beiscsi_hba *phba, | |
3446 | struct hwi_context_memory *phwi_context, | |
3447 | struct hwi_controller *phwi_ctrlr, | |
8a86e833 | 3448 | unsigned int def_pdu_ring_sz, uint8_t ulp_num) |
6733b39a JK |
3449 | { |
3450 | unsigned int idx; | |
3451 | int ret; | |
3452 | struct be_queue_info *dataq, *cq; | |
3453 | struct be_dma_mem *mem; | |
3454 | struct be_mem_descriptor *mem_descr; | |
3455 | void *dq_vaddress; | |
3456 | ||
3457 | idx = 0; | |
8a86e833 | 3458 | dataq = &phwi_context->be_def_dataq[ulp_num]; |
bfead3b2 | 3459 | cq = &phwi_context->be_cq[0]; |
6733b39a JK |
3460 | mem = &dataq->dma_mem; |
3461 | mem_descr = phba->init_mem; | |
8a86e833 JK |
3462 | mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 + |
3463 | (ulp_num * MEM_DESCR_OFFSET); | |
6733b39a JK |
3464 | dq_vaddress = mem_descr->mem_array[idx].virtual_address; |
3465 | ret = be_fill_queue(dataq, mem_descr->mem_array[0].size / | |
3466 | sizeof(struct phys_addr), | |
3467 | sizeof(struct phys_addr), dq_vaddress); | |
3468 | if (ret) { | |
99bc5d55 | 3469 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
8a86e833 JK |
3470 | "BM_%d : be_fill_queue Failed for DEF PDU " |
3471 | "DATA on ULP : %d\n", | |
3472 | ulp_num); | |
3473 | ||
6733b39a JK |
3474 | return ret; |
3475 | } | |
457ff3b7 JK |
3476 | mem->dma = (unsigned long)mem_descr->mem_array[idx]. |
3477 | bus_address.u.a64.address; | |
6733b39a JK |
3478 | ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq, |
3479 | def_pdu_ring_sz, | |
8a86e833 JK |
3480 | phba->params.defpdu_data_sz, |
3481 | BEISCSI_DEFQ_DATA, ulp_num); | |
6733b39a | 3482 | if (ret) { |
99bc5d55 JSJ |
3483 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3484 | "BM_%d be_cmd_create_default_pdu_queue" | |
8a86e833 JK |
3485 | " Failed for DEF PDU DATA on ULP : %d\n", |
3486 | ulp_num); | |
6733b39a JK |
3487 | return ret; |
3488 | } | |
8a86e833 | 3489 | |
99bc5d55 | 3490 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
8a86e833 JK |
3491 | "BM_%d : iscsi def data id on ULP : %d is %d\n", |
3492 | ulp_num, | |
3493 | phwi_context->be_def_dataq[ulp_num].id); | |
99bc5d55 | 3494 | |
8a86e833 | 3495 | hwi_post_async_buffers(phba, BEISCSI_DEFQ_DATA, ulp_num); |
99bc5d55 | 3496 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
8a86e833 JK |
3497 | "BM_%d : DEFAULT PDU DATA RING CREATED" |
3498 | "on ULP : %d\n", ulp_num); | |
99bc5d55 | 3499 | |
6733b39a JK |
3500 | return 0; |
3501 | } | |
3502 | ||
15a90fe0 JK |
3503 | |
3504 | static int | |
3505 | beiscsi_post_template_hdr(struct beiscsi_hba *phba) | |
3506 | { | |
3507 | struct be_mem_descriptor *mem_descr; | |
3508 | struct mem_array *pm_arr; | |
3509 | struct be_dma_mem sgl; | |
a129d92f | 3510 | int status, ulp_num; |
15a90fe0 | 3511 | |
a129d92f JK |
3512 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
3513 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { | |
3514 | mem_descr = (struct be_mem_descriptor *)phba->init_mem; | |
3515 | mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 + | |
3516 | (ulp_num * MEM_DESCR_OFFSET); | |
3517 | pm_arr = mem_descr->mem_array; | |
15a90fe0 | 3518 | |
a129d92f JK |
3519 | hwi_build_be_sgl_arr(phba, pm_arr, &sgl); |
3520 | status = be_cmd_iscsi_post_template_hdr( | |
3521 | &phba->ctrl, &sgl); | |
15a90fe0 | 3522 | |
a129d92f JK |
3523 | if (status != 0) { |
3524 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
3525 | "BM_%d : Post Template HDR Failed for" | |
3526 | "ULP_%d\n", ulp_num); | |
3527 | return status; | |
3528 | } | |
3529 | ||
3530 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
3531 | "BM_%d : Template HDR Pages Posted for" | |
3532 | "ULP_%d\n", ulp_num); | |
15a90fe0 JK |
3533 | } |
3534 | } | |
15a90fe0 JK |
3535 | return 0; |
3536 | } | |
3537 | ||
6733b39a JK |
3538 | static int |
3539 | beiscsi_post_pages(struct beiscsi_hba *phba) | |
3540 | { | |
3541 | struct be_mem_descriptor *mem_descr; | |
3542 | struct mem_array *pm_arr; | |
3543 | unsigned int page_offset, i; | |
3544 | struct be_dma_mem sgl; | |
843ae752 | 3545 | int status, ulp_num = 0; |
6733b39a JK |
3546 | |
3547 | mem_descr = phba->init_mem; | |
3548 | mem_descr += HWI_MEM_SGE; | |
3549 | pm_arr = mem_descr->mem_array; | |
3550 | ||
90622db3 JK |
3551 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) |
3552 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) | |
3553 | break; | |
3554 | ||
6733b39a | 3555 | page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io * |
843ae752 | 3556 | phba->fw_config.iscsi_icd_start[ulp_num]) / PAGE_SIZE; |
6733b39a JK |
3557 | for (i = 0; i < mem_descr->num_elements; i++) { |
3558 | hwi_build_be_sgl_arr(phba, pm_arr, &sgl); | |
3559 | status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl, | |
3560 | page_offset, | |
3561 | (pm_arr->size / PAGE_SIZE)); | |
3562 | page_offset += pm_arr->size / PAGE_SIZE; | |
3563 | if (status != 0) { | |
99bc5d55 JSJ |
3564 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3565 | "BM_%d : post sgl failed.\n"); | |
6733b39a JK |
3566 | return status; |
3567 | } | |
3568 | pm_arr++; | |
3569 | } | |
99bc5d55 JSJ |
3570 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
3571 | "BM_%d : POSTED PAGES\n"); | |
6733b39a JK |
3572 | return 0; |
3573 | } | |
3574 | ||
bfead3b2 JK |
3575 | static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q) |
3576 | { | |
3577 | struct be_dma_mem *mem = &q->dma_mem; | |
c8b25598 | 3578 | if (mem->va) { |
bfead3b2 JK |
3579 | pci_free_consistent(phba->pcidev, mem->size, |
3580 | mem->va, mem->dma); | |
c8b25598 JK |
3581 | mem->va = NULL; |
3582 | } | |
bfead3b2 JK |
3583 | } |
3584 | ||
3585 | static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q, | |
3586 | u16 len, u16 entry_size) | |
3587 | { | |
3588 | struct be_dma_mem *mem = &q->dma_mem; | |
3589 | ||
3590 | memset(q, 0, sizeof(*q)); | |
3591 | q->len = len; | |
3592 | q->entry_size = entry_size; | |
3593 | mem->size = len * entry_size; | |
7c845eb5 | 3594 | mem->va = pci_zalloc_consistent(phba->pcidev, mem->size, &mem->dma); |
bfead3b2 | 3595 | if (!mem->va) |
d3ad2bb3 | 3596 | return -ENOMEM; |
bfead3b2 JK |
3597 | return 0; |
3598 | } | |
3599 | ||
6733b39a JK |
3600 | static int |
3601 | beiscsi_create_wrb_rings(struct beiscsi_hba *phba, | |
3602 | struct hwi_context_memory *phwi_context, | |
3603 | struct hwi_controller *phwi_ctrlr) | |
3604 | { | |
3605 | unsigned int wrb_mem_index, offset, size, num_wrb_rings; | |
3606 | u64 pa_addr_lo; | |
4eea99d5 | 3607 | unsigned int idx, num, i, ulp_num; |
6733b39a JK |
3608 | struct mem_array *pwrb_arr; |
3609 | void *wrb_vaddr; | |
3610 | struct be_dma_mem sgl; | |
3611 | struct be_mem_descriptor *mem_descr; | |
a7909b39 | 3612 | struct hwi_wrb_context *pwrb_context; |
6733b39a | 3613 | int status; |
4eea99d5 JK |
3614 | uint8_t ulp_count = 0, ulp_base_num = 0; |
3615 | uint16_t cid_count_ulp[BEISCSI_ULP_COUNT] = { 0 }; | |
6733b39a JK |
3616 | |
3617 | idx = 0; | |
3618 | mem_descr = phba->init_mem; | |
3619 | mem_descr += HWI_MEM_WRB; | |
3620 | pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl, | |
3621 | GFP_KERNEL); | |
3622 | if (!pwrb_arr) { | |
99bc5d55 JSJ |
3623 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3624 | "BM_%d : Memory alloc failed in create wrb ring.\n"); | |
6733b39a JK |
3625 | return -ENOMEM; |
3626 | } | |
3627 | wrb_vaddr = mem_descr->mem_array[idx].virtual_address; | |
3628 | pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address; | |
3629 | num_wrb_rings = mem_descr->mem_array[idx].size / | |
3630 | (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb)); | |
3631 | ||
3632 | for (num = 0; num < phba->params.cxns_per_ctrl; num++) { | |
3633 | if (num_wrb_rings) { | |
3634 | pwrb_arr[num].virtual_address = wrb_vaddr; | |
3635 | pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo; | |
3636 | pwrb_arr[num].size = phba->params.wrbs_per_cxn * | |
3637 | sizeof(struct iscsi_wrb); | |
3638 | wrb_vaddr += pwrb_arr[num].size; | |
3639 | pa_addr_lo += pwrb_arr[num].size; | |
3640 | num_wrb_rings--; | |
3641 | } else { | |
3642 | idx++; | |
3643 | wrb_vaddr = mem_descr->mem_array[idx].virtual_address; | |
3644 | pa_addr_lo = mem_descr->mem_array[idx].\ | |
3645 | bus_address.u.a64.address; | |
3646 | num_wrb_rings = mem_descr->mem_array[idx].size / | |
3647 | (phba->params.wrbs_per_cxn * | |
3648 | sizeof(struct iscsi_wrb)); | |
3649 | pwrb_arr[num].virtual_address = wrb_vaddr; | |
3650 | pwrb_arr[num].bus_address.u.a64.address\ | |
3651 | = pa_addr_lo; | |
3652 | pwrb_arr[num].size = phba->params.wrbs_per_cxn * | |
3653 | sizeof(struct iscsi_wrb); | |
3654 | wrb_vaddr += pwrb_arr[num].size; | |
3655 | pa_addr_lo += pwrb_arr[num].size; | |
3656 | num_wrb_rings--; | |
3657 | } | |
3658 | } | |
4eea99d5 JK |
3659 | |
3660 | /* Get the ULP Count */ | |
3661 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) | |
3662 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { | |
3663 | ulp_count++; | |
3664 | ulp_base_num = ulp_num; | |
3665 | cid_count_ulp[ulp_num] = | |
3666 | BEISCSI_GET_CID_COUNT(phba, ulp_num); | |
3667 | } | |
3668 | ||
6733b39a JK |
3669 | for (i = 0; i < phba->params.cxns_per_ctrl; i++) { |
3670 | wrb_mem_index = 0; | |
3671 | offset = 0; | |
3672 | size = 0; | |
3673 | ||
4eea99d5 JK |
3674 | if (ulp_count > 1) { |
3675 | ulp_base_num = (ulp_base_num + 1) % BEISCSI_ULP_COUNT; | |
3676 | ||
3677 | if (!cid_count_ulp[ulp_base_num]) | |
3678 | ulp_base_num = (ulp_base_num + 1) % | |
3679 | BEISCSI_ULP_COUNT; | |
3680 | ||
3681 | cid_count_ulp[ulp_base_num]--; | |
3682 | } | |
3683 | ||
3684 | ||
6733b39a JK |
3685 | hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl); |
3686 | status = be_cmd_wrbq_create(&phba->ctrl, &sgl, | |
4eea99d5 JK |
3687 | &phwi_context->be_wrbq[i], |
3688 | &phwi_ctrlr->wrb_context[i], | |
3689 | ulp_base_num); | |
6733b39a | 3690 | if (status != 0) { |
99bc5d55 JSJ |
3691 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3692 | "BM_%d : wrbq create failed."); | |
1462b8ff | 3693 | kfree(pwrb_arr); |
6733b39a JK |
3694 | return status; |
3695 | } | |
a7909b39 | 3696 | pwrb_context = &phwi_ctrlr->wrb_context[i]; |
a7909b39 | 3697 | BE_SET_CID_TO_CRI(i, pwrb_context->cid); |
6733b39a JK |
3698 | } |
3699 | kfree(pwrb_arr); | |
3700 | return 0; | |
3701 | } | |
3702 | ||
3703 | static void free_wrb_handles(struct beiscsi_hba *phba) | |
3704 | { | |
3705 | unsigned int index; | |
3706 | struct hwi_controller *phwi_ctrlr; | |
3707 | struct hwi_wrb_context *pwrb_context; | |
3708 | ||
3709 | phwi_ctrlr = phba->phwi_ctrlr; | |
a7909b39 | 3710 | for (index = 0; index < phba->params.cxns_per_ctrl; index++) { |
6733b39a JK |
3711 | pwrb_context = &phwi_ctrlr->wrb_context[index]; |
3712 | kfree(pwrb_context->pwrb_handle_base); | |
3713 | kfree(pwrb_context->pwrb_handle_basestd); | |
3714 | } | |
3715 | } | |
3716 | ||
bfead3b2 JK |
3717 | static void be_mcc_queues_destroy(struct beiscsi_hba *phba) |
3718 | { | |
3719 | struct be_queue_info *q; | |
3720 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
3721 | ||
3722 | q = &phba->ctrl.mcc_obj.q; | |
4e2bdf7a | 3723 | if (q->created) { |
bfead3b2 | 3724 | beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ); |
4e2bdf7a JSJ |
3725 | be_queue_free(phba, q); |
3726 | } | |
bfead3b2 JK |
3727 | |
3728 | q = &phba->ctrl.mcc_obj.cq; | |
4e2bdf7a | 3729 | if (q->created) { |
bfead3b2 | 3730 | beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ); |
4e2bdf7a JSJ |
3731 | be_queue_free(phba, q); |
3732 | } | |
bfead3b2 JK |
3733 | } |
3734 | ||
6733b39a JK |
3735 | static void hwi_cleanup(struct beiscsi_hba *phba) |
3736 | { | |
3737 | struct be_queue_info *q; | |
3738 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
3739 | struct hwi_controller *phwi_ctrlr; | |
3740 | struct hwi_context_memory *phwi_context; | |
a7909b39 | 3741 | struct hwi_async_pdu_context *pasync_ctx; |
23188167 | 3742 | int i, eq_for_mcc, ulp_num; |
6733b39a JK |
3743 | |
3744 | phwi_ctrlr = phba->phwi_ctrlr; | |
3745 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
15a90fe0 JK |
3746 | |
3747 | be_cmd_iscsi_remove_template_hdr(ctrl); | |
3748 | ||
6733b39a JK |
3749 | for (i = 0; i < phba->params.cxns_per_ctrl; i++) { |
3750 | q = &phwi_context->be_wrbq[i]; | |
3751 | if (q->created) | |
3752 | beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ); | |
3753 | } | |
a7909b39 | 3754 | kfree(phwi_context->be_wrbq); |
6733b39a JK |
3755 | free_wrb_handles(phba); |
3756 | ||
8a86e833 JK |
3757 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
3758 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { | |
6733b39a | 3759 | |
8a86e833 JK |
3760 | q = &phwi_context->be_def_hdrq[ulp_num]; |
3761 | if (q->created) | |
3762 | beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ); | |
3763 | ||
3764 | q = &phwi_context->be_def_dataq[ulp_num]; | |
3765 | if (q->created) | |
3766 | beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ); | |
3767 | ||
3768 | pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num]; | |
3769 | } | |
3770 | } | |
6733b39a JK |
3771 | |
3772 | beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL); | |
3773 | ||
bfead3b2 JK |
3774 | for (i = 0; i < (phba->num_cpus); i++) { |
3775 | q = &phwi_context->be_cq[i]; | |
4e2bdf7a JSJ |
3776 | if (q->created) { |
3777 | be_queue_free(phba, q); | |
bfead3b2 | 3778 | beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ); |
4e2bdf7a | 3779 | } |
bfead3b2 | 3780 | } |
23188167 JK |
3781 | |
3782 | be_mcc_queues_destroy(phba); | |
bfead3b2 | 3783 | if (phba->msix_enabled) |
23188167 | 3784 | eq_for_mcc = 1; |
bfead3b2 | 3785 | else |
23188167 JK |
3786 | eq_for_mcc = 0; |
3787 | for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) { | |
bfead3b2 | 3788 | q = &phwi_context->be_eq[i].q; |
4e2bdf7a JSJ |
3789 | if (q->created) { |
3790 | be_queue_free(phba, q); | |
bfead3b2 | 3791 | beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ); |
4e2bdf7a | 3792 | } |
bfead3b2 | 3793 | } |
0283fbb1 | 3794 | be_cmd_fw_uninit(ctrl); |
bfead3b2 | 3795 | } |
6733b39a | 3796 | |
bfead3b2 JK |
3797 | static int be_mcc_queues_create(struct beiscsi_hba *phba, |
3798 | struct hwi_context_memory *phwi_context) | |
3799 | { | |
3800 | struct be_queue_info *q, *cq; | |
3801 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
3802 | ||
3803 | /* Alloc MCC compl queue */ | |
3804 | cq = &phba->ctrl.mcc_obj.cq; | |
3805 | if (be_queue_alloc(phba, cq, MCC_CQ_LEN, | |
3806 | sizeof(struct be_mcc_compl))) | |
3807 | goto err; | |
3808 | /* Ask BE to create MCC compl queue; */ | |
3809 | if (phba->msix_enabled) { | |
3810 | if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq | |
3811 | [phba->num_cpus].q, false, true, 0)) | |
3812 | goto mcc_cq_free; | |
3813 | } else { | |
3814 | if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q, | |
3815 | false, true, 0)) | |
3816 | goto mcc_cq_free; | |
3817 | } | |
3818 | ||
3819 | /* Alloc MCC queue */ | |
3820 | q = &phba->ctrl.mcc_obj.q; | |
3821 | if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb))) | |
3822 | goto mcc_cq_destroy; | |
3823 | ||
3824 | /* Ask BE to create MCC queue */ | |
35e66019 | 3825 | if (beiscsi_cmd_mccq_create(phba, q, cq)) |
bfead3b2 JK |
3826 | goto mcc_q_free; |
3827 | ||
3828 | return 0; | |
3829 | ||
3830 | mcc_q_free: | |
3831 | be_queue_free(phba, q); | |
3832 | mcc_cq_destroy: | |
3833 | beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ); | |
3834 | mcc_cq_free: | |
3835 | be_queue_free(phba, cq); | |
3836 | err: | |
d3ad2bb3 | 3837 | return -ENOMEM; |
bfead3b2 JK |
3838 | } |
3839 | ||
107dfcba JSJ |
3840 | /** |
3841 | * find_num_cpus()- Get the CPU online count | |
3842 | * @phba: ptr to priv structure | |
3843 | * | |
3844 | * CPU count is used for creating EQ. | |
3845 | **/ | |
3846 | static void find_num_cpus(struct beiscsi_hba *phba) | |
bfead3b2 JK |
3847 | { |
3848 | int num_cpus = 0; | |
3849 | ||
3850 | num_cpus = num_online_cpus(); | |
bfead3b2 | 3851 | |
22abeef0 JSJ |
3852 | switch (phba->generation) { |
3853 | case BE_GEN2: | |
3854 | case BE_GEN3: | |
3855 | phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ? | |
3856 | BEISCSI_MAX_NUM_CPUS : num_cpus; | |
3857 | break; | |
3858 | case BE_GEN4: | |
68c26a3a JK |
3859 | /* |
3860 | * If eqid_count == 1 fall back to | |
3861 | * INTX mechanism | |
3862 | **/ | |
3863 | if (phba->fw_config.eqid_count == 1) { | |
3864 | enable_msix = 0; | |
3865 | phba->num_cpus = 1; | |
3866 | return; | |
3867 | } | |
3868 | ||
3869 | phba->num_cpus = | |
3870 | (num_cpus > (phba->fw_config.eqid_count - 1)) ? | |
3871 | (phba->fw_config.eqid_count - 1) : num_cpus; | |
22abeef0 JSJ |
3872 | break; |
3873 | default: | |
3874 | phba->num_cpus = 1; | |
3875 | } | |
6733b39a JK |
3876 | } |
3877 | ||
3878 | static int hwi_init_port(struct beiscsi_hba *phba) | |
3879 | { | |
3880 | struct hwi_controller *phwi_ctrlr; | |
3881 | struct hwi_context_memory *phwi_context; | |
3882 | unsigned int def_pdu_ring_sz; | |
3883 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
8a86e833 | 3884 | int status, ulp_num; |
6733b39a | 3885 | |
6733b39a | 3886 | phwi_ctrlr = phba->phwi_ctrlr; |
6733b39a | 3887 | phwi_context = phwi_ctrlr->phwi_ctxt; |
73af08e1 | 3888 | phwi_context->max_eqd = 128; |
bfead3b2 | 3889 | phwi_context->min_eqd = 0; |
73af08e1 | 3890 | phwi_context->cur_eqd = 0; |
6733b39a | 3891 | be_cmd_fw_initialize(&phba->ctrl); |
53aefe25 JB |
3892 | /* set optic state to unknown */ |
3893 | phba->optic_state = 0xff; | |
bfead3b2 JK |
3894 | |
3895 | status = beiscsi_create_eqs(phba, phwi_context); | |
6733b39a | 3896 | if (status != 0) { |
99bc5d55 JSJ |
3897 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3898 | "BM_%d : EQ not created\n"); | |
6733b39a JK |
3899 | goto error; |
3900 | } | |
3901 | ||
bfead3b2 JK |
3902 | status = be_mcc_queues_create(phba, phwi_context); |
3903 | if (status != 0) | |
3904 | goto error; | |
3905 | ||
3906 | status = mgmt_check_supported_fw(ctrl, phba); | |
6733b39a | 3907 | if (status != 0) { |
99bc5d55 JSJ |
3908 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3909 | "BM_%d : Unsupported fw version\n"); | |
6733b39a JK |
3910 | goto error; |
3911 | } | |
3912 | ||
bfead3b2 | 3913 | status = beiscsi_create_cqs(phba, phwi_context); |
6733b39a | 3914 | if (status != 0) { |
99bc5d55 JSJ |
3915 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3916 | "BM_%d : CQ not created\n"); | |
6733b39a JK |
3917 | goto error; |
3918 | } | |
3919 | ||
8a86e833 JK |
3920 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
3921 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { | |
6733b39a | 3922 | |
8a86e833 JK |
3923 | def_pdu_ring_sz = |
3924 | BEISCSI_GET_CID_COUNT(phba, ulp_num) * | |
3925 | sizeof(struct phys_addr); | |
3926 | ||
3927 | status = beiscsi_create_def_hdr(phba, phwi_context, | |
3928 | phwi_ctrlr, | |
3929 | def_pdu_ring_sz, | |
3930 | ulp_num); | |
3931 | if (status != 0) { | |
3932 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
3933 | "BM_%d : Default Header not created for ULP : %d\n", | |
3934 | ulp_num); | |
3935 | goto error; | |
3936 | } | |
3937 | ||
3938 | status = beiscsi_create_def_data(phba, phwi_context, | |
3939 | phwi_ctrlr, | |
3940 | def_pdu_ring_sz, | |
3941 | ulp_num); | |
3942 | if (status != 0) { | |
3943 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
3944 | "BM_%d : Default Data not created for ULP : %d\n", | |
3945 | ulp_num); | |
3946 | goto error; | |
3947 | } | |
3948 | } | |
6733b39a JK |
3949 | } |
3950 | ||
3951 | status = beiscsi_post_pages(phba); | |
3952 | if (status != 0) { | |
99bc5d55 JSJ |
3953 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3954 | "BM_%d : Post SGL Pages Failed\n"); | |
6733b39a JK |
3955 | goto error; |
3956 | } | |
3957 | ||
15a90fe0 JK |
3958 | status = beiscsi_post_template_hdr(phba); |
3959 | if (status != 0) { | |
3960 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
3961 | "BM_%d : Template HDR Posting for CXN Failed\n"); | |
3962 | } | |
3963 | ||
6733b39a JK |
3964 | status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr); |
3965 | if (status != 0) { | |
99bc5d55 JSJ |
3966 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3967 | "BM_%d : WRB Rings not created\n"); | |
6733b39a JK |
3968 | goto error; |
3969 | } | |
3970 | ||
8a86e833 JK |
3971 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
3972 | uint16_t async_arr_idx = 0; | |
3973 | ||
3974 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) { | |
3975 | uint16_t cri = 0; | |
3976 | struct hwi_async_pdu_context *pasync_ctx; | |
3977 | ||
3978 | pasync_ctx = HWI_GET_ASYNC_PDU_CTX( | |
3979 | phwi_ctrlr, ulp_num); | |
3980 | for (cri = 0; cri < | |
3981 | phba->params.cxns_per_ctrl; cri++) { | |
3982 | if (ulp_num == BEISCSI_GET_ULP_FROM_CRI | |
3983 | (phwi_ctrlr, cri)) | |
3984 | pasync_ctx->cid_to_async_cri_map[ | |
3985 | phwi_ctrlr->wrb_context[cri].cid] = | |
3986 | async_arr_idx++; | |
3987 | } | |
3988 | } | |
3989 | } | |
3990 | ||
99bc5d55 JSJ |
3991 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
3992 | "BM_%d : hwi_init_port success\n"); | |
6733b39a JK |
3993 | return 0; |
3994 | ||
3995 | error: | |
99bc5d55 JSJ |
3996 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
3997 | "BM_%d : hwi_init_port failed"); | |
6733b39a | 3998 | hwi_cleanup(phba); |
a49e06d5 | 3999 | return status; |
6733b39a JK |
4000 | } |
4001 | ||
6733b39a JK |
4002 | static int hwi_init_controller(struct beiscsi_hba *phba) |
4003 | { | |
4004 | struct hwi_controller *phwi_ctrlr; | |
4005 | ||
4006 | phwi_ctrlr = phba->phwi_ctrlr; | |
4007 | if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) { | |
4008 | phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba-> | |
4009 | init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address; | |
99bc5d55 JSJ |
4010 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
4011 | "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n", | |
4012 | phwi_ctrlr->phwi_ctxt); | |
6733b39a | 4013 | } else { |
99bc5d55 JSJ |
4014 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4015 | "BM_%d : HWI_MEM_ADDN_CONTEXT is more " | |
4016 | "than one element.Failing to load\n"); | |
6733b39a JK |
4017 | return -ENOMEM; |
4018 | } | |
4019 | ||
4020 | iscsi_init_global_templates(phba); | |
3ec78271 JK |
4021 | if (beiscsi_init_wrb_handle(phba)) |
4022 | return -ENOMEM; | |
4023 | ||
a7909b39 JK |
4024 | if (hwi_init_async_pdu_ctx(phba)) { |
4025 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
4026 | "BM_%d : hwi_init_async_pdu_ctx failed\n"); | |
4027 | return -ENOMEM; | |
4028 | } | |
4029 | ||
6733b39a | 4030 | if (hwi_init_port(phba) != 0) { |
99bc5d55 JSJ |
4031 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4032 | "BM_%d : hwi_init_controller failed\n"); | |
4033 | ||
6733b39a JK |
4034 | return -ENOMEM; |
4035 | } | |
4036 | return 0; | |
4037 | } | |
4038 | ||
4039 | static void beiscsi_free_mem(struct beiscsi_hba *phba) | |
4040 | { | |
4041 | struct be_mem_descriptor *mem_descr; | |
4042 | int i, j; | |
4043 | ||
4044 | mem_descr = phba->init_mem; | |
4045 | i = 0; | |
4046 | j = 0; | |
4047 | for (i = 0; i < SE_MEM_MAX; i++) { | |
4048 | for (j = mem_descr->num_elements; j > 0; j--) { | |
4049 | pci_free_consistent(phba->pcidev, | |
4050 | mem_descr->mem_array[j - 1].size, | |
4051 | mem_descr->mem_array[j - 1].virtual_address, | |
457ff3b7 JK |
4052 | (unsigned long)mem_descr->mem_array[j - 1]. |
4053 | bus_address.u.a64.address); | |
6733b39a | 4054 | } |
8a86e833 | 4055 | |
6733b39a JK |
4056 | kfree(mem_descr->mem_array); |
4057 | mem_descr++; | |
4058 | } | |
4059 | kfree(phba->init_mem); | |
a7909b39 | 4060 | kfree(phba->phwi_ctrlr->wrb_context); |
6733b39a JK |
4061 | kfree(phba->phwi_ctrlr); |
4062 | } | |
4063 | ||
4064 | static int beiscsi_init_controller(struct beiscsi_hba *phba) | |
4065 | { | |
4066 | int ret = -ENOMEM; | |
4067 | ||
4068 | ret = beiscsi_get_memory(phba); | |
4069 | if (ret < 0) { | |
99bc5d55 JSJ |
4070 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4071 | "BM_%d : beiscsi_dev_probe -" | |
4072 | "Failed in beiscsi_alloc_memory\n"); | |
6733b39a JK |
4073 | return ret; |
4074 | } | |
4075 | ||
4076 | ret = hwi_init_controller(phba); | |
4077 | if (ret) | |
4078 | goto free_init; | |
99bc5d55 JSJ |
4079 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
4080 | "BM_%d : Return success from beiscsi_init_controller"); | |
4081 | ||
6733b39a JK |
4082 | return 0; |
4083 | ||
4084 | free_init: | |
4085 | beiscsi_free_mem(phba); | |
a49e06d5 | 4086 | return ret; |
6733b39a JK |
4087 | } |
4088 | ||
4089 | static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba) | |
4090 | { | |
4091 | struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg; | |
4092 | struct sgl_handle *psgl_handle; | |
4093 | struct iscsi_sge *pfrag; | |
90622db3 JK |
4094 | unsigned int arr_index, i, idx; |
4095 | unsigned int ulp_icd_start, ulp_num = 0; | |
6733b39a JK |
4096 | |
4097 | phba->io_sgl_hndl_avbl = 0; | |
4098 | phba->eh_sgl_hndl_avbl = 0; | |
bfead3b2 | 4099 | |
6733b39a JK |
4100 | mem_descr_sglh = phba->init_mem; |
4101 | mem_descr_sglh += HWI_MEM_SGLH; | |
4102 | if (1 == mem_descr_sglh->num_elements) { | |
4103 | phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) * | |
4104 | phba->params.ios_per_ctrl, | |
4105 | GFP_KERNEL); | |
4106 | if (!phba->io_sgl_hndl_base) { | |
99bc5d55 JSJ |
4107 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4108 | "BM_%d : Mem Alloc Failed. Failing to load\n"); | |
6733b39a JK |
4109 | return -ENOMEM; |
4110 | } | |
4111 | phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) * | |
4112 | (phba->params.icds_per_ctrl - | |
4113 | phba->params.ios_per_ctrl), | |
4114 | GFP_KERNEL); | |
4115 | if (!phba->eh_sgl_hndl_base) { | |
4116 | kfree(phba->io_sgl_hndl_base); | |
99bc5d55 JSJ |
4117 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4118 | "BM_%d : Mem Alloc Failed. Failing to load\n"); | |
6733b39a JK |
4119 | return -ENOMEM; |
4120 | } | |
4121 | } else { | |
99bc5d55 JSJ |
4122 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4123 | "BM_%d : HWI_MEM_SGLH is more than one element." | |
4124 | "Failing to load\n"); | |
6733b39a JK |
4125 | return -ENOMEM; |
4126 | } | |
4127 | ||
4128 | arr_index = 0; | |
4129 | idx = 0; | |
4130 | while (idx < mem_descr_sglh->num_elements) { | |
4131 | psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address; | |
4132 | ||
4133 | for (i = 0; i < (mem_descr_sglh->mem_array[idx].size / | |
4134 | sizeof(struct sgl_handle)); i++) { | |
4135 | if (arr_index < phba->params.ios_per_ctrl) { | |
4136 | phba->io_sgl_hndl_base[arr_index] = psgl_handle; | |
4137 | phba->io_sgl_hndl_avbl++; | |
4138 | arr_index++; | |
4139 | } else { | |
4140 | phba->eh_sgl_hndl_base[arr_index - | |
4141 | phba->params.ios_per_ctrl] = | |
4142 | psgl_handle; | |
4143 | arr_index++; | |
4144 | phba->eh_sgl_hndl_avbl++; | |
4145 | } | |
4146 | psgl_handle++; | |
4147 | } | |
4148 | idx++; | |
4149 | } | |
99bc5d55 JSJ |
4150 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
4151 | "BM_%d : phba->io_sgl_hndl_avbl=%d" | |
4152 | "phba->eh_sgl_hndl_avbl=%d\n", | |
4153 | phba->io_sgl_hndl_avbl, | |
4154 | phba->eh_sgl_hndl_avbl); | |
4155 | ||
6733b39a JK |
4156 | mem_descr_sg = phba->init_mem; |
4157 | mem_descr_sg += HWI_MEM_SGE; | |
99bc5d55 JSJ |
4158 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
4159 | "\n BM_%d : mem_descr_sg->num_elements=%d\n", | |
4160 | mem_descr_sg->num_elements); | |
4161 | ||
90622db3 JK |
4162 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) |
4163 | if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) | |
4164 | break; | |
4165 | ||
4166 | ulp_icd_start = phba->fw_config.iscsi_icd_start[ulp_num]; | |
4167 | ||
6733b39a JK |
4168 | arr_index = 0; |
4169 | idx = 0; | |
4170 | while (idx < mem_descr_sg->num_elements) { | |
4171 | pfrag = mem_descr_sg->mem_array[idx].virtual_address; | |
4172 | ||
4173 | for (i = 0; | |
4174 | i < (mem_descr_sg->mem_array[idx].size) / | |
4175 | (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io); | |
4176 | i++) { | |
4177 | if (arr_index < phba->params.ios_per_ctrl) | |
4178 | psgl_handle = phba->io_sgl_hndl_base[arr_index]; | |
4179 | else | |
4180 | psgl_handle = phba->eh_sgl_hndl_base[arr_index - | |
4181 | phba->params.ios_per_ctrl]; | |
4182 | psgl_handle->pfrag = pfrag; | |
4183 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0); | |
4184 | AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0); | |
4185 | pfrag += phba->params.num_sge_per_io; | |
90622db3 | 4186 | psgl_handle->sgl_index = ulp_icd_start + arr_index++; |
6733b39a JK |
4187 | } |
4188 | idx++; | |
4189 | } | |
4190 | phba->io_sgl_free_index = 0; | |
4191 | phba->io_sgl_alloc_index = 0; | |
4192 | phba->eh_sgl_free_index = 0; | |
4193 | phba->eh_sgl_alloc_index = 0; | |
4194 | return 0; | |
4195 | } | |
4196 | ||
4197 | static int hba_setup_cid_tbls(struct beiscsi_hba *phba) | |
4198 | { | |
0a3db7c0 JK |
4199 | int ret; |
4200 | uint16_t i, ulp_num; | |
4201 | struct ulp_cid_info *ptr_cid_info = NULL; | |
6733b39a | 4202 | |
0a3db7c0 JK |
4203 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
4204 | if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { | |
4205 | ptr_cid_info = kzalloc(sizeof(struct ulp_cid_info), | |
4206 | GFP_KERNEL); | |
4207 | ||
4208 | if (!ptr_cid_info) { | |
4209 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
4210 | "BM_%d : Failed to allocate memory" | |
4211 | "for ULP_CID_INFO for ULP : %d\n", | |
4212 | ulp_num); | |
4213 | ret = -ENOMEM; | |
4214 | goto free_memory; | |
4215 | ||
4216 | } | |
4217 | ||
4218 | /* Allocate memory for CID array */ | |
4219 | ptr_cid_info->cid_array = kzalloc(sizeof(void *) * | |
4220 | BEISCSI_GET_CID_COUNT(phba, | |
4221 | ulp_num), GFP_KERNEL); | |
4222 | if (!ptr_cid_info->cid_array) { | |
4223 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
4224 | "BM_%d : Failed to allocate memory" | |
4225 | "for CID_ARRAY for ULP : %d\n", | |
4226 | ulp_num); | |
4227 | kfree(ptr_cid_info); | |
4228 | ptr_cid_info = NULL; | |
4229 | ret = -ENOMEM; | |
4230 | ||
4231 | goto free_memory; | |
4232 | } | |
4233 | ptr_cid_info->avlbl_cids = BEISCSI_GET_CID_COUNT( | |
4234 | phba, ulp_num); | |
4235 | ||
4236 | /* Save the cid_info_array ptr */ | |
4237 | phba->cid_array_info[ulp_num] = ptr_cid_info; | |
4238 | } | |
6733b39a | 4239 | } |
c2462288 | 4240 | phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) * |
a7909b39 | 4241 | phba->params.cxns_per_ctrl, GFP_KERNEL); |
6733b39a | 4242 | if (!phba->ep_array) { |
99bc5d55 JSJ |
4243 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4244 | "BM_%d : Failed to allocate memory in " | |
4245 | "hba_setup_cid_tbls\n"); | |
0a3db7c0 JK |
4246 | ret = -ENOMEM; |
4247 | ||
4248 | goto free_memory; | |
6733b39a | 4249 | } |
a7909b39 JK |
4250 | |
4251 | phba->conn_table = kzalloc(sizeof(struct beiscsi_conn *) * | |
4252 | phba->params.cxns_per_ctrl, GFP_KERNEL); | |
4253 | if (!phba->conn_table) { | |
4254 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
4255 | "BM_%d : Failed to allocate memory in" | |
4256 | "hba_setup_cid_tbls\n"); | |
4257 | ||
a7909b39 | 4258 | kfree(phba->ep_array); |
a7909b39 | 4259 | phba->ep_array = NULL; |
0a3db7c0 | 4260 | ret = -ENOMEM; |
5f2d25ef TH |
4261 | |
4262 | goto free_memory; | |
6733b39a | 4263 | } |
a7909b39 | 4264 | |
0a3db7c0 JK |
4265 | for (i = 0; i < phba->params.cxns_per_ctrl; i++) { |
4266 | ulp_num = phba->phwi_ctrlr->wrb_context[i].ulp_num; | |
4267 | ||
4268 | ptr_cid_info = phba->cid_array_info[ulp_num]; | |
4269 | ptr_cid_info->cid_array[ptr_cid_info->cid_alloc++] = | |
4270 | phba->phwi_ctrlr->wrb_context[i].cid; | |
4271 | ||
4272 | } | |
4273 | ||
4274 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { | |
4275 | if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { | |
4276 | ptr_cid_info = phba->cid_array_info[ulp_num]; | |
a7909b39 | 4277 | |
0a3db7c0 JK |
4278 | ptr_cid_info->cid_alloc = 0; |
4279 | ptr_cid_info->cid_free = 0; | |
4280 | } | |
4281 | } | |
6733b39a | 4282 | return 0; |
0a3db7c0 JK |
4283 | |
4284 | free_memory: | |
4285 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { | |
4286 | if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { | |
4287 | ptr_cid_info = phba->cid_array_info[ulp_num]; | |
4288 | ||
4289 | if (ptr_cid_info) { | |
4290 | kfree(ptr_cid_info->cid_array); | |
4291 | kfree(ptr_cid_info); | |
4292 | phba->cid_array_info[ulp_num] = NULL; | |
4293 | } | |
4294 | } | |
4295 | } | |
4296 | ||
4297 | return ret; | |
6733b39a JK |
4298 | } |
4299 | ||
238f6b72 | 4300 | static void hwi_enable_intr(struct beiscsi_hba *phba) |
6733b39a JK |
4301 | { |
4302 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
4303 | struct hwi_controller *phwi_ctrlr; | |
4304 | struct hwi_context_memory *phwi_context; | |
4305 | struct be_queue_info *eq; | |
4306 | u8 __iomem *addr; | |
bfead3b2 | 4307 | u32 reg, i; |
6733b39a JK |
4308 | u32 enabled; |
4309 | ||
4310 | phwi_ctrlr = phba->phwi_ctrlr; | |
4311 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
4312 | ||
6733b39a JK |
4313 | addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg + |
4314 | PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET); | |
4315 | reg = ioread32(addr); | |
6733b39a JK |
4316 | |
4317 | enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | |
4318 | if (!enabled) { | |
4319 | reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | |
99bc5d55 JSJ |
4320 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
4321 | "BM_%d : reg =x%08x addr=%p\n", reg, addr); | |
6733b39a | 4322 | iowrite32(reg, addr); |
665d6d94 JK |
4323 | } |
4324 | ||
4325 | if (!phba->msix_enabled) { | |
4326 | eq = &phwi_context->be_eq[0].q; | |
99bc5d55 JSJ |
4327 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
4328 | "BM_%d : eq->id=%d\n", eq->id); | |
4329 | ||
665d6d94 JK |
4330 | hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); |
4331 | } else { | |
4332 | for (i = 0; i <= phba->num_cpus; i++) { | |
4333 | eq = &phwi_context->be_eq[i].q; | |
99bc5d55 JSJ |
4334 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
4335 | "BM_%d : eq->id=%d\n", eq->id); | |
bfead3b2 JK |
4336 | hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1); |
4337 | } | |
c03af1ae | 4338 | } |
6733b39a JK |
4339 | } |
4340 | ||
4341 | static void hwi_disable_intr(struct beiscsi_hba *phba) | |
4342 | { | |
4343 | struct be_ctrl_info *ctrl = &phba->ctrl; | |
4344 | ||
4345 | u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET; | |
4346 | u32 reg = ioread32(addr); | |
4347 | ||
4348 | u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | |
4349 | if (enabled) { | |
4350 | reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK; | |
4351 | iowrite32(reg, addr); | |
4352 | } else | |
99bc5d55 JSJ |
4353 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, |
4354 | "BM_%d : In hwi_disable_intr, Already Disabled\n"); | |
6733b39a JK |
4355 | } |
4356 | ||
9aef4200 JSJ |
4357 | /** |
4358 | * beiscsi_get_boot_info()- Get the boot session info | |
4359 | * @phba: The device priv structure instance | |
4360 | * | |
4361 | * Get the boot target info and store in driver priv structure | |
4362 | * | |
4363 | * return values | |
4364 | * Success: 0 | |
4365 | * Failure: Non-Zero Value | |
4366 | **/ | |
c7acc5b8 JK |
4367 | static int beiscsi_get_boot_info(struct beiscsi_hba *phba) |
4368 | { | |
0e43895e | 4369 | struct be_cmd_get_session_resp *session_resp; |
c7acc5b8 | 4370 | struct be_dma_mem nonemb_cmd; |
e175defe | 4371 | unsigned int tag; |
9aef4200 | 4372 | unsigned int s_handle; |
f457a46f | 4373 | int ret = -ENOMEM; |
c7acc5b8 | 4374 | |
9aef4200 JSJ |
4375 | /* Get the session handle of the boot target */ |
4376 | ret = be_mgmt_get_boot_shandle(phba, &s_handle); | |
4377 | if (ret) { | |
99bc5d55 JSJ |
4378 | beiscsi_log(phba, KERN_ERR, |
4379 | BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG, | |
4380 | "BM_%d : No boot session\n"); | |
3efde862 JSJ |
4381 | |
4382 | if (ret == -ENXIO) | |
4383 | phba->get_boot = 0; | |
4384 | ||
4385 | ||
9aef4200 | 4386 | return ret; |
c7acc5b8 | 4387 | } |
3efde862 | 4388 | phba->get_boot = 0; |
7c845eb5 JP |
4389 | nonemb_cmd.va = pci_zalloc_consistent(phba->ctrl.pdev, |
4390 | sizeof(*session_resp), | |
4391 | &nonemb_cmd.dma); | |
c7acc5b8 | 4392 | if (nonemb_cmd.va == NULL) { |
99bc5d55 JSJ |
4393 | beiscsi_log(phba, KERN_ERR, |
4394 | BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG, | |
4395 | "BM_%d : Failed to allocate memory for" | |
4396 | "beiscsi_get_session_info\n"); | |
4397 | ||
c7acc5b8 JK |
4398 | return -ENOMEM; |
4399 | } | |
4400 | ||
9aef4200 | 4401 | tag = mgmt_get_session_info(phba, s_handle, |
0e43895e | 4402 | &nonemb_cmd); |
c7acc5b8 | 4403 | if (!tag) { |
99bc5d55 JSJ |
4404 | beiscsi_log(phba, KERN_ERR, |
4405 | BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG, | |
4406 | "BM_%d : beiscsi_get_session_info" | |
4407 | " Failed\n"); | |
4408 | ||
c7acc5b8 | 4409 | goto boot_freemem; |
e175defe | 4410 | } |
c7acc5b8 | 4411 | |
88840332 | 4412 | ret = beiscsi_mccq_compl_wait(phba, tag, NULL, &nonemb_cmd); |
e175defe | 4413 | if (ret) { |
99bc5d55 JSJ |
4414 | beiscsi_log(phba, KERN_ERR, |
4415 | BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG, | |
e175defe | 4416 | "BM_%d : beiscsi_get_session_info Failed"); |
1957aa7f JK |
4417 | |
4418 | if (ret != -EBUSY) | |
4419 | goto boot_freemem; | |
4420 | else | |
4421 | return ret; | |
c7acc5b8 | 4422 | } |
e175defe | 4423 | |
c7acc5b8 | 4424 | session_resp = nonemb_cmd.va ; |
f457a46f | 4425 | |
c7acc5b8 JK |
4426 | memcpy(&phba->boot_sess, &session_resp->session_info, |
4427 | sizeof(struct mgmt_session_info)); | |
3f4134c1 JSJ |
4428 | |
4429 | beiscsi_logout_fw_sess(phba, | |
4430 | phba->boot_sess.session_handle); | |
f457a46f MC |
4431 | ret = 0; |
4432 | ||
c7acc5b8 JK |
4433 | boot_freemem: |
4434 | pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, | |
4435 | nonemb_cmd.va, nonemb_cmd.dma); | |
f457a46f MC |
4436 | return ret; |
4437 | } | |
4438 | ||
4439 | static void beiscsi_boot_release(void *data) | |
4440 | { | |
4441 | struct beiscsi_hba *phba = data; | |
4442 | ||
4443 | scsi_host_put(phba->shost); | |
4444 | } | |
4445 | ||
4446 | static int beiscsi_setup_boot_info(struct beiscsi_hba *phba) | |
4447 | { | |
4448 | struct iscsi_boot_kobj *boot_kobj; | |
4449 | ||
a3d313ea JK |
4450 | /* it has been created previously */ |
4451 | if (phba->boot_kset) | |
4452 | return 0; | |
4453 | ||
f457a46f MC |
4454 | /* get boot info using mgmt cmd */ |
4455 | if (beiscsi_get_boot_info(phba)) | |
4456 | /* Try to see if we can carry on without this */ | |
4457 | return 0; | |
4458 | ||
4459 | phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no); | |
4460 | if (!phba->boot_kset) | |
4461 | return -ENOMEM; | |
4462 | ||
4463 | /* get a ref because the show function will ref the phba */ | |
4464 | if (!scsi_host_get(phba->shost)) | |
4465 | goto free_kset; | |
4466 | boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba, | |
4467 | beiscsi_show_boot_tgt_info, | |
4468 | beiscsi_tgt_get_attr_visibility, | |
4469 | beiscsi_boot_release); | |
4470 | if (!boot_kobj) | |
4471 | goto put_shost; | |
4472 | ||
4473 | if (!scsi_host_get(phba->shost)) | |
4474 | goto free_kset; | |
4475 | boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba, | |
4476 | beiscsi_show_boot_ini_info, | |
4477 | beiscsi_ini_get_attr_visibility, | |
4478 | beiscsi_boot_release); | |
4479 | if (!boot_kobj) | |
4480 | goto put_shost; | |
4481 | ||
4482 | if (!scsi_host_get(phba->shost)) | |
4483 | goto free_kset; | |
4484 | boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba, | |
4485 | beiscsi_show_boot_eth_info, | |
4486 | beiscsi_eth_get_attr_visibility, | |
4487 | beiscsi_boot_release); | |
4488 | if (!boot_kobj) | |
4489 | goto put_shost; | |
4490 | return 0; | |
4491 | ||
4492 | put_shost: | |
4493 | scsi_host_put(phba->shost); | |
4494 | free_kset: | |
4495 | iscsi_boot_destroy_kset(phba->boot_kset); | |
c7acc5b8 JK |
4496 | return -ENOMEM; |
4497 | } | |
4498 | ||
6733b39a JK |
4499 | static int beiscsi_init_port(struct beiscsi_hba *phba) |
4500 | { | |
4501 | int ret; | |
4502 | ||
4503 | ret = beiscsi_init_controller(phba); | |
4504 | if (ret < 0) { | |
99bc5d55 JSJ |
4505 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4506 | "BM_%d : beiscsi_dev_probe - Failed in" | |
4507 | "beiscsi_init_controller\n"); | |
6733b39a JK |
4508 | return ret; |
4509 | } | |
4510 | ret = beiscsi_init_sgl_handle(phba); | |
4511 | if (ret < 0) { | |
99bc5d55 JSJ |
4512 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4513 | "BM_%d : beiscsi_dev_probe - Failed in" | |
4514 | "beiscsi_init_sgl_handle\n"); | |
6733b39a JK |
4515 | goto do_cleanup_ctrlr; |
4516 | } | |
4517 | ||
4518 | if (hba_setup_cid_tbls(phba)) { | |
99bc5d55 JSJ |
4519 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
4520 | "BM_%d : Failed in hba_setup_cid_tbls\n"); | |
6733b39a JK |
4521 | kfree(phba->io_sgl_hndl_base); |
4522 | kfree(phba->eh_sgl_hndl_base); | |
4523 | goto do_cleanup_ctrlr; | |
4524 | } | |
4525 | ||
4526 | return ret; | |
4527 | ||
4528 | do_cleanup_ctrlr: | |
4529 | hwi_cleanup(phba); | |
4530 | return ret; | |
4531 | } | |
4532 | ||
4533 | static void hwi_purge_eq(struct beiscsi_hba *phba) | |
4534 | { | |
4535 | struct hwi_controller *phwi_ctrlr; | |
4536 | struct hwi_context_memory *phwi_context; | |
4537 | struct be_queue_info *eq; | |
4538 | struct be_eq_entry *eqe = NULL; | |
bfead3b2 | 4539 | int i, eq_msix; |
756d29c8 | 4540 | unsigned int num_processed; |
6733b39a JK |
4541 | |
4542 | phwi_ctrlr = phba->phwi_ctrlr; | |
4543 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
bfead3b2 JK |
4544 | if (phba->msix_enabled) |
4545 | eq_msix = 1; | |
4546 | else | |
4547 | eq_msix = 0; | |
6733b39a | 4548 | |
bfead3b2 JK |
4549 | for (i = 0; i < (phba->num_cpus + eq_msix); i++) { |
4550 | eq = &phwi_context->be_eq[i].q; | |
6733b39a | 4551 | eqe = queue_tail_node(eq); |
756d29c8 | 4552 | num_processed = 0; |
bfead3b2 JK |
4553 | while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] |
4554 | & EQE_VALID_MASK) { | |
4555 | AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0); | |
4556 | queue_tail_inc(eq); | |
4557 | eqe = queue_tail_node(eq); | |
756d29c8 | 4558 | num_processed++; |
bfead3b2 | 4559 | } |
756d29c8 JK |
4560 | |
4561 | if (num_processed) | |
4562 | hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1); | |
6733b39a JK |
4563 | } |
4564 | } | |
4565 | ||
4566 | static void beiscsi_clean_port(struct beiscsi_hba *phba) | |
4567 | { | |
0a3db7c0 JK |
4568 | int mgmt_status, ulp_num; |
4569 | struct ulp_cid_info *ptr_cid_info = NULL; | |
6733b39a | 4570 | |
bd41c2bd JK |
4571 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { |
4572 | if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { | |
4573 | mgmt_status = mgmt_epfw_cleanup(phba, ulp_num); | |
4574 | if (mgmt_status) | |
4575 | beiscsi_log(phba, KERN_WARNING, | |
4576 | BEISCSI_LOG_INIT, | |
4577 | "BM_%d : mgmt_epfw_cleanup FAILED" | |
4578 | " for ULP_%d\n", ulp_num); | |
4579 | } | |
4580 | } | |
756d29c8 | 4581 | |
6733b39a | 4582 | hwi_purge_eq(phba); |
756d29c8 | 4583 | hwi_cleanup(phba); |
6733b39a JK |
4584 | kfree(phba->io_sgl_hndl_base); |
4585 | kfree(phba->eh_sgl_hndl_base); | |
6733b39a | 4586 | kfree(phba->ep_array); |
a7909b39 | 4587 | kfree(phba->conn_table); |
0a3db7c0 JK |
4588 | |
4589 | for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) { | |
4590 | if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) { | |
4591 | ptr_cid_info = phba->cid_array_info[ulp_num]; | |
4592 | ||
4593 | if (ptr_cid_info) { | |
4594 | kfree(ptr_cid_info->cid_array); | |
4595 | kfree(ptr_cid_info); | |
4596 | phba->cid_array_info[ulp_num] = NULL; | |
4597 | } | |
4598 | } | |
4599 | } | |
4600 | ||
6733b39a JK |
4601 | } |
4602 | ||
43f388b0 JK |
4603 | /** |
4604 | * beiscsi_free_mgmt_task_handles()- Free driver CXN resources | |
4605 | * @beiscsi_conn: ptr to the conn to be cleaned up | |
4a4a11b9 | 4606 | * @task: ptr to iscsi_task resource to be freed. |
43f388b0 JK |
4607 | * |
4608 | * Free driver mgmt resources binded to CXN. | |
4609 | **/ | |
4610 | void | |
4a4a11b9 JK |
4611 | beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn, |
4612 | struct iscsi_task *task) | |
43f388b0 JK |
4613 | { |
4614 | struct beiscsi_io_task *io_task; | |
4615 | struct beiscsi_hba *phba = beiscsi_conn->phba; | |
4616 | struct hwi_wrb_context *pwrb_context; | |
4617 | struct hwi_controller *phwi_ctrlr; | |
a7909b39 JK |
4618 | uint16_t cri_index = BE_GET_CRI_FROM_CID( |
4619 | beiscsi_conn->beiscsi_conn_cid); | |
43f388b0 JK |
4620 | |
4621 | phwi_ctrlr = phba->phwi_ctrlr; | |
a7909b39 JK |
4622 | pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; |
4623 | ||
4a4a11b9 | 4624 | io_task = task->dd_data; |
43f388b0 JK |
4625 | |
4626 | if (io_task->pwrb_handle) { | |
4627 | memset(io_task->pwrb_handle->pwrb, 0, | |
4628 | sizeof(struct iscsi_wrb)); | |
4629 | free_wrb_handle(phba, pwrb_context, | |
4630 | io_task->pwrb_handle); | |
4631 | io_task->pwrb_handle = NULL; | |
4632 | } | |
4633 | ||
4634 | if (io_task->psgl_handle) { | |
43f388b0 JK |
4635 | free_mgmt_sgl_handle(phba, |
4636 | io_task->psgl_handle); | |
43f388b0 JK |
4637 | io_task->psgl_handle = NULL; |
4638 | } | |
4639 | ||
eb1c4692 | 4640 | if (io_task->mtask_addr) { |
43f388b0 JK |
4641 | pci_unmap_single(phba->pcidev, |
4642 | io_task->mtask_addr, | |
4643 | io_task->mtask_data_count, | |
4644 | PCI_DMA_TODEVICE); | |
eb1c4692 JSJ |
4645 | io_task->mtask_addr = 0; |
4646 | } | |
43f388b0 JK |
4647 | } |
4648 | ||
d629c471 JSJ |
4649 | /** |
4650 | * beiscsi_cleanup_task()- Free driver resources of the task | |
4651 | * @task: ptr to the iscsi task | |
4652 | * | |
4653 | **/ | |
1282ab76 MC |
4654 | static void beiscsi_cleanup_task(struct iscsi_task *task) |
4655 | { | |
4656 | struct beiscsi_io_task *io_task = task->dd_data; | |
4657 | struct iscsi_conn *conn = task->conn; | |
4658 | struct beiscsi_conn *beiscsi_conn = conn->dd_data; | |
4659 | struct beiscsi_hba *phba = beiscsi_conn->phba; | |
4660 | struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess; | |
4661 | struct hwi_wrb_context *pwrb_context; | |
4662 | struct hwi_controller *phwi_ctrlr; | |
a7909b39 JK |
4663 | uint16_t cri_index = BE_GET_CRI_FROM_CID( |
4664 | beiscsi_conn->beiscsi_conn_cid); | |
1282ab76 MC |
4665 | |
4666 | phwi_ctrlr = phba->phwi_ctrlr; | |
a7909b39 | 4667 | pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; |
1282ab76 MC |
4668 | |
4669 | if (io_task->cmd_bhs) { | |
4670 | pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs, | |
4671 | io_task->bhs_pa.u.a64.address); | |
4672 | io_task->cmd_bhs = NULL; | |
4673 | } | |
4674 | ||
4675 | if (task->sc) { | |
4676 | if (io_task->pwrb_handle) { | |
4677 | free_wrb_handle(phba, pwrb_context, | |
4678 | io_task->pwrb_handle); | |
4679 | io_task->pwrb_handle = NULL; | |
4680 | } | |
4681 | ||
4682 | if (io_task->psgl_handle) { | |
1282ab76 | 4683 | free_io_sgl_handle(phba, io_task->psgl_handle); |
1282ab76 MC |
4684 | io_task->psgl_handle = NULL; |
4685 | } | |
da334977 JK |
4686 | |
4687 | if (io_task->scsi_cmnd) { | |
4688 | scsi_dma_unmap(io_task->scsi_cmnd); | |
4689 | io_task->scsi_cmnd = NULL; | |
4690 | } | |
1282ab76 | 4691 | } else { |
43f388b0 | 4692 | if (!beiscsi_conn->login_in_progress) |
4a4a11b9 | 4693 | beiscsi_free_mgmt_task_handles(beiscsi_conn, task); |
1282ab76 MC |
4694 | } |
4695 | } | |
4696 | ||
6733b39a JK |
4697 | void |
4698 | beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn, | |
4699 | struct beiscsi_offload_params *params) | |
4700 | { | |
4701 | struct wrb_handle *pwrb_handle; | |
340c99e9 | 4702 | struct hwi_wrb_context *pwrb_context = NULL; |
6733b39a | 4703 | struct beiscsi_hba *phba = beiscsi_conn->phba; |
1282ab76 MC |
4704 | struct iscsi_task *task = beiscsi_conn->task; |
4705 | struct iscsi_session *session = task->conn->session; | |
6733b39a JK |
4706 | u32 doorbell = 0; |
4707 | ||
4708 | /* | |
4709 | * We can always use 0 here because it is reserved by libiscsi for | |
4710 | * login/startup related tasks. | |
4711 | */ | |
1282ab76 | 4712 | beiscsi_conn->login_in_progress = 0; |
659743b0 | 4713 | spin_lock_bh(&session->back_lock); |
1282ab76 | 4714 | beiscsi_cleanup_task(task); |
659743b0 | 4715 | spin_unlock_bh(&session->back_lock); |
1282ab76 | 4716 | |
340c99e9 JSJ |
4717 | pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid, |
4718 | &pwrb_context); | |
6733b39a | 4719 | |
acb9693c | 4720 | /* Check for the adapter family */ |
2c9dfd36 | 4721 | if (is_chip_be2_be3r(phba)) |
acb9693c | 4722 | beiscsi_offload_cxn_v0(params, pwrb_handle, |
340c99e9 JSJ |
4723 | phba->init_mem, |
4724 | pwrb_context); | |
2c9dfd36 | 4725 | else |
340c99e9 JSJ |
4726 | beiscsi_offload_cxn_v2(params, pwrb_handle, |
4727 | pwrb_context); | |
6733b39a | 4728 | |
acb9693c JSJ |
4729 | be_dws_le_to_cpu(pwrb_handle->pwrb, |
4730 | sizeof(struct iscsi_target_context_update_wrb)); | |
6733b39a JK |
4731 | |
4732 | doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; | |
32951dd8 | 4733 | doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK) |
bfead3b2 | 4734 | << DB_DEF_PDU_WRB_INDEX_SHIFT; |
6733b39a | 4735 | doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; |
1e4be6ff JK |
4736 | iowrite32(doorbell, phba->db_va + |
4737 | beiscsi_conn->doorbell_offset); | |
cb564c6b JB |
4738 | |
4739 | /* | |
4740 | * There is no completion for CONTEXT_UPDATE. The completion of next | |
4741 | * WRB posted guarantees FW's processing and DMA'ing of it. | |
4742 | * Use beiscsi_put_wrb_handle to put it back in the pool which makes | |
4743 | * sure zero'ing or reuse of the WRB only after wrbs_per_cxn. | |
4744 | */ | |
4745 | beiscsi_put_wrb_handle(pwrb_context, pwrb_handle, | |
4746 | phba->params.wrbs_per_cxn); | |
4747 | beiscsi_log(phba, KERN_INFO, | |
4748 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
4749 | "BM_%d : put CONTEXT_UPDATE pwrb_handle=%p free_index=0x%x wrb_handles_available=%d\n", | |
4750 | pwrb_handle, pwrb_context->free_index, | |
4751 | pwrb_context->wrb_handles_available); | |
6733b39a JK |
4752 | } |
4753 | ||
4754 | static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt, | |
4755 | int *index, int *age) | |
4756 | { | |
bfead3b2 | 4757 | *index = (int)itt; |
6733b39a JK |
4758 | if (age) |
4759 | *age = conn->session->age; | |
4760 | } | |
4761 | ||
4762 | /** | |
4763 | * beiscsi_alloc_pdu - allocates pdu and related resources | |
4764 | * @task: libiscsi task | |
4765 | * @opcode: opcode of pdu for task | |
4766 | * | |
4767 | * This is called with the session lock held. It will allocate | |
4768 | * the wrb and sgl if needed for the command. And it will prep | |
4769 | * the pdu's itt. beiscsi_parse_pdu will later translate | |
4770 | * the pdu itt to the libiscsi task itt. | |
4771 | */ | |
4772 | static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode) | |
4773 | { | |
4774 | struct beiscsi_io_task *io_task = task->dd_data; | |
4775 | struct iscsi_conn *conn = task->conn; | |
4776 | struct beiscsi_conn *beiscsi_conn = conn->dd_data; | |
4777 | struct beiscsi_hba *phba = beiscsi_conn->phba; | |
4778 | struct hwi_wrb_context *pwrb_context; | |
4779 | struct hwi_controller *phwi_ctrlr; | |
4780 | itt_t itt; | |
a7909b39 | 4781 | uint16_t cri_index = 0; |
2afc95bf JK |
4782 | struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess; |
4783 | dma_addr_t paddr; | |
6733b39a | 4784 | |
2afc95bf | 4785 | io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool, |
bc7accec | 4786 | GFP_ATOMIC, &paddr); |
2afc95bf JK |
4787 | if (!io_task->cmd_bhs) |
4788 | return -ENOMEM; | |
2afc95bf | 4789 | io_task->bhs_pa.u.a64.address = paddr; |
bfead3b2 | 4790 | io_task->libiscsi_itt = (itt_t)task->itt; |
6733b39a JK |
4791 | io_task->conn = beiscsi_conn; |
4792 | ||
4793 | task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr; | |
4794 | task->hdr_max = sizeof(struct be_cmd_bhs); | |
d2cecf0d | 4795 | io_task->psgl_handle = NULL; |
3ec78271 | 4796 | io_task->pwrb_handle = NULL; |
6733b39a JK |
4797 | |
4798 | if (task->sc) { | |
6733b39a | 4799 | io_task->psgl_handle = alloc_io_sgl_handle(phba); |
8359c79b JSJ |
4800 | if (!io_task->psgl_handle) { |
4801 | beiscsi_log(phba, KERN_ERR, | |
4802 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
4803 | "BM_%d : Alloc of IO_SGL_ICD Failed" | |
4804 | "for the CID : %d\n", | |
4805 | beiscsi_conn->beiscsi_conn_cid); | |
2afc95bf | 4806 | goto free_hndls; |
8359c79b | 4807 | } |
d2cecf0d | 4808 | io_task->pwrb_handle = alloc_wrb_handle(phba, |
340c99e9 JSJ |
4809 | beiscsi_conn->beiscsi_conn_cid, |
4810 | &io_task->pwrb_context); | |
8359c79b JSJ |
4811 | if (!io_task->pwrb_handle) { |
4812 | beiscsi_log(phba, KERN_ERR, | |
4813 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
4814 | "BM_%d : Alloc of WRB_HANDLE Failed" | |
4815 | "for the CID : %d\n", | |
4816 | beiscsi_conn->beiscsi_conn_cid); | |
d2cecf0d | 4817 | goto free_io_hndls; |
8359c79b | 4818 | } |
6733b39a JK |
4819 | } else { |
4820 | io_task->scsi_cmnd = NULL; | |
d7aea67b | 4821 | if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) { |
43f388b0 | 4822 | beiscsi_conn->task = task; |
6733b39a | 4823 | if (!beiscsi_conn->login_in_progress) { |
6733b39a JK |
4824 | io_task->psgl_handle = (struct sgl_handle *) |
4825 | alloc_mgmt_sgl_handle(phba); | |
8359c79b JSJ |
4826 | if (!io_task->psgl_handle) { |
4827 | beiscsi_log(phba, KERN_ERR, | |
4828 | BEISCSI_LOG_IO | | |
4829 | BEISCSI_LOG_CONFIG, | |
4830 | "BM_%d : Alloc of MGMT_SGL_ICD Failed" | |
4831 | "for the CID : %d\n", | |
4832 | beiscsi_conn-> | |
4833 | beiscsi_conn_cid); | |
2afc95bf | 4834 | goto free_hndls; |
8359c79b | 4835 | } |
2afc95bf | 4836 | |
6733b39a JK |
4837 | beiscsi_conn->login_in_progress = 1; |
4838 | beiscsi_conn->plogin_sgl_handle = | |
4839 | io_task->psgl_handle; | |
d2cecf0d JK |
4840 | io_task->pwrb_handle = |
4841 | alloc_wrb_handle(phba, | |
340c99e9 JSJ |
4842 | beiscsi_conn->beiscsi_conn_cid, |
4843 | &io_task->pwrb_context); | |
8359c79b JSJ |
4844 | if (!io_task->pwrb_handle) { |
4845 | beiscsi_log(phba, KERN_ERR, | |
4846 | BEISCSI_LOG_IO | | |
4847 | BEISCSI_LOG_CONFIG, | |
4848 | "BM_%d : Alloc of WRB_HANDLE Failed" | |
4849 | "for the CID : %d\n", | |
4850 | beiscsi_conn-> | |
4851 | beiscsi_conn_cid); | |
4852 | goto free_mgmt_hndls; | |
4853 | } | |
d2cecf0d JK |
4854 | beiscsi_conn->plogin_wrb_handle = |
4855 | io_task->pwrb_handle; | |
4856 | ||
6733b39a JK |
4857 | } else { |
4858 | io_task->psgl_handle = | |
4859 | beiscsi_conn->plogin_sgl_handle; | |
d2cecf0d JK |
4860 | io_task->pwrb_handle = |
4861 | beiscsi_conn->plogin_wrb_handle; | |
6733b39a JK |
4862 | } |
4863 | } else { | |
6733b39a | 4864 | io_task->psgl_handle = alloc_mgmt_sgl_handle(phba); |
8359c79b JSJ |
4865 | if (!io_task->psgl_handle) { |
4866 | beiscsi_log(phba, KERN_ERR, | |
4867 | BEISCSI_LOG_IO | | |
4868 | BEISCSI_LOG_CONFIG, | |
4869 | "BM_%d : Alloc of MGMT_SGL_ICD Failed" | |
4870 | "for the CID : %d\n", | |
4871 | beiscsi_conn-> | |
4872 | beiscsi_conn_cid); | |
2afc95bf | 4873 | goto free_hndls; |
8359c79b | 4874 | } |
d2cecf0d JK |
4875 | io_task->pwrb_handle = |
4876 | alloc_wrb_handle(phba, | |
340c99e9 JSJ |
4877 | beiscsi_conn->beiscsi_conn_cid, |
4878 | &io_task->pwrb_context); | |
8359c79b JSJ |
4879 | if (!io_task->pwrb_handle) { |
4880 | beiscsi_log(phba, KERN_ERR, | |
4881 | BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG, | |
4882 | "BM_%d : Alloc of WRB_HANDLE Failed" | |
4883 | "for the CID : %d\n", | |
4884 | beiscsi_conn->beiscsi_conn_cid); | |
d2cecf0d | 4885 | goto free_mgmt_hndls; |
8359c79b | 4886 | } |
d2cecf0d | 4887 | |
6733b39a JK |
4888 | } |
4889 | } | |
bfead3b2 JK |
4890 | itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle-> |
4891 | wrb_index << 16) | (unsigned int) | |
4892 | (io_task->psgl_handle->sgl_index)); | |
32951dd8 | 4893 | io_task->pwrb_handle->pio_handle = task; |
bfead3b2 | 4894 | |
6733b39a JK |
4895 | io_task->cmd_bhs->iscsi_hdr.itt = itt; |
4896 | return 0; | |
2afc95bf | 4897 | |
d2cecf0d | 4898 | free_io_hndls: |
d2cecf0d | 4899 | free_io_sgl_handle(phba, io_task->psgl_handle); |
d2cecf0d JK |
4900 | goto free_hndls; |
4901 | free_mgmt_hndls: | |
d2cecf0d | 4902 | free_mgmt_sgl_handle(phba, io_task->psgl_handle); |
a7909b39 | 4903 | io_task->psgl_handle = NULL; |
2afc95bf JK |
4904 | free_hndls: |
4905 | phwi_ctrlr = phba->phwi_ctrlr; | |
a7909b39 JK |
4906 | cri_index = BE_GET_CRI_FROM_CID( |
4907 | beiscsi_conn->beiscsi_conn_cid); | |
4908 | pwrb_context = &phwi_ctrlr->wrb_context[cri_index]; | |
d2cecf0d JK |
4909 | if (io_task->pwrb_handle) |
4910 | free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle); | |
2afc95bf JK |
4911 | io_task->pwrb_handle = NULL; |
4912 | pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs, | |
4913 | io_task->bhs_pa.u.a64.address); | |
1282ab76 | 4914 | io_task->cmd_bhs = NULL; |
2afc95bf | 4915 | return -ENOMEM; |
6733b39a | 4916 | } |
09a1093a JSJ |
4917 | int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg, |
4918 | unsigned int num_sg, unsigned int xferlen, | |
4919 | unsigned int writedir) | |
4920 | { | |
4921 | ||
4922 | struct beiscsi_io_task *io_task = task->dd_data; | |
4923 | struct iscsi_conn *conn = task->conn; | |
4924 | struct beiscsi_conn *beiscsi_conn = conn->dd_data; | |
4925 | struct beiscsi_hba *phba = beiscsi_conn->phba; | |
4926 | struct iscsi_wrb *pwrb = NULL; | |
4927 | unsigned int doorbell = 0; | |
4928 | ||
4929 | pwrb = io_task->pwrb_handle->pwrb; | |
09a1093a | 4930 | |
09a1093a JSJ |
4931 | io_task->bhs_len = sizeof(struct be_cmd_bhs); |
4932 | ||
4933 | if (writedir) { | |
4934 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb, | |
4935 | INI_WR_CMD); | |
4936 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1); | |
4937 | } else { | |
4938 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb, | |
4939 | INI_RD_CMD); | |
4940 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0); | |
4941 | } | |
4942 | ||
4943 | io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2, | |
4944 | type, pwrb); | |
4945 | ||
4946 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb, | |
4947 | cpu_to_be16(*(unsigned short *) | |
4948 | &io_task->cmd_bhs->iscsi_hdr.lun)); | |
4949 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen); | |
4950 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb, | |
4951 | io_task->pwrb_handle->wrb_index); | |
4952 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb, | |
4953 | be32_to_cpu(task->cmdsn)); | |
4954 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb, | |
4955 | io_task->psgl_handle->sgl_index); | |
4956 | ||
4957 | hwi_write_sgl_v2(pwrb, sg, num_sg, io_task); | |
4958 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb, | |
340c99e9 JSJ |
4959 | io_task->pwrb_handle->wrb_index); |
4960 | if (io_task->pwrb_context->plast_wrb) | |
4961 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, | |
4962 | io_task->pwrb_context->plast_wrb, | |
4963 | io_task->pwrb_handle->wrb_index); | |
4964 | io_task->pwrb_context->plast_wrb = pwrb; | |
09a1093a JSJ |
4965 | |
4966 | be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb)); | |
4967 | ||
4968 | doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; | |
4969 | doorbell |= (io_task->pwrb_handle->wrb_index & | |
4970 | DB_DEF_PDU_WRB_INDEX_MASK) << | |
4971 | DB_DEF_PDU_WRB_INDEX_SHIFT; | |
4972 | doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; | |
1e4be6ff JK |
4973 | iowrite32(doorbell, phba->db_va + |
4974 | beiscsi_conn->doorbell_offset); | |
09a1093a JSJ |
4975 | return 0; |
4976 | } | |
6733b39a | 4977 | |
6733b39a JK |
4978 | static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg, |
4979 | unsigned int num_sg, unsigned int xferlen, | |
4980 | unsigned int writedir) | |
4981 | { | |
4982 | ||
4983 | struct beiscsi_io_task *io_task = task->dd_data; | |
4984 | struct iscsi_conn *conn = task->conn; | |
4985 | struct beiscsi_conn *beiscsi_conn = conn->dd_data; | |
4986 | struct beiscsi_hba *phba = beiscsi_conn->phba; | |
4987 | struct iscsi_wrb *pwrb = NULL; | |
4988 | unsigned int doorbell = 0; | |
4989 | ||
4990 | pwrb = io_task->pwrb_handle->pwrb; | |
6733b39a JK |
4991 | io_task->bhs_len = sizeof(struct be_cmd_bhs); |
4992 | ||
4993 | if (writedir) { | |
32951dd8 JK |
4994 | AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, |
4995 | INI_WR_CMD); | |
6733b39a | 4996 | AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1); |
6733b39a | 4997 | } else { |
32951dd8 JK |
4998 | AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb, |
4999 | INI_RD_CMD); | |
6733b39a JK |
5000 | AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0); |
5001 | } | |
6733b39a | 5002 | |
09a1093a JSJ |
5003 | io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb, |
5004 | type, pwrb); | |
5005 | ||
6733b39a | 5006 | AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb, |
dc63aac6 JK |
5007 | cpu_to_be16(*(unsigned short *) |
5008 | &io_task->cmd_bhs->iscsi_hdr.lun)); | |
6733b39a JK |
5009 | AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen); |
5010 | AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb, | |
5011 | io_task->pwrb_handle->wrb_index); | |
5012 | AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, | |
5013 | be32_to_cpu(task->cmdsn)); | |
5014 | AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb, | |
5015 | io_task->psgl_handle->sgl_index); | |
5016 | ||
5017 | hwi_write_sgl(pwrb, sg, num_sg, io_task); | |
5018 | ||
5019 | AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb, | |
340c99e9 JSJ |
5020 | io_task->pwrb_handle->wrb_index); |
5021 | if (io_task->pwrb_context->plast_wrb) | |
5022 | AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, | |
5023 | io_task->pwrb_context->plast_wrb, | |
5024 | io_task->pwrb_handle->wrb_index); | |
5025 | io_task->pwrb_context->plast_wrb = pwrb; | |
5026 | ||
6733b39a JK |
5027 | be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb)); |
5028 | ||
5029 | doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK; | |
32951dd8 | 5030 | doorbell |= (io_task->pwrb_handle->wrb_index & |
6733b39a JK |
5031 | DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT; |
5032 | doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; | |
5033 | ||
1e4be6ff JK |
5034 | iowrite32(doorbell, phba->db_va + |
5035 | beiscsi_conn->doorbell_offset); | |
6733b39a JK |
5036 | return 0; |
5037 | } | |
5038 | ||
5039 | static int beiscsi_mtask(struct iscsi_task *task) | |
5040 | { | |
dafab8e0 | 5041 | struct beiscsi_io_task *io_task = task->dd_data; |
6733b39a JK |
5042 | struct iscsi_conn *conn = task->conn; |
5043 | struct beiscsi_conn *beiscsi_conn = conn->dd_data; | |
5044 | struct beiscsi_hba *phba = beiscsi_conn->phba; | |
5045 | struct iscsi_wrb *pwrb = NULL; | |
5046 | unsigned int doorbell = 0; | |
dafab8e0 | 5047 | unsigned int cid; |
09a1093a | 5048 | unsigned int pwrb_typeoffset = 0; |
e0493627 | 5049 | int ret = 0; |
6733b39a | 5050 | |
bfead3b2 | 5051 | cid = beiscsi_conn->beiscsi_conn_cid; |
6733b39a | 5052 | pwrb = io_task->pwrb_handle->pwrb; |
caf818f1 | 5053 | memset(pwrb, 0, sizeof(*pwrb)); |
09a1093a | 5054 | |
2c9dfd36 | 5055 | if (is_chip_be2_be3r(phba)) { |
09a1093a JSJ |
5056 | AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, |
5057 | be32_to_cpu(task->cmdsn)); | |
5058 | AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb, | |
5059 | io_task->pwrb_handle->wrb_index); | |
5060 | AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb, | |
5061 | io_task->psgl_handle->sgl_index); | |
5062 | AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, | |
5063 | task->data_count); | |
5064 | AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb, | |
340c99e9 JSJ |
5065 | io_task->pwrb_handle->wrb_index); |
5066 | if (io_task->pwrb_context->plast_wrb) | |
5067 | AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, | |
5068 | io_task->pwrb_context->plast_wrb, | |
5069 | io_task->pwrb_handle->wrb_index); | |
5070 | io_task->pwrb_context->plast_wrb = pwrb; | |
5071 | ||
09a1093a | 5072 | pwrb_typeoffset = BE_WRB_TYPE_OFFSET; |
2c9dfd36 JK |
5073 | } else { |
5074 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb, | |
5075 | be32_to_cpu(task->cmdsn)); | |
5076 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb, | |
5077 | io_task->pwrb_handle->wrb_index); | |
5078 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb, | |
5079 | io_task->psgl_handle->sgl_index); | |
5080 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, | |
5081 | task->data_count); | |
5082 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb, | |
340c99e9 JSJ |
5083 | io_task->pwrb_handle->wrb_index); |
5084 | if (io_task->pwrb_context->plast_wrb) | |
5085 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, | |
5086 | io_task->pwrb_context->plast_wrb, | |
5087 | io_task->pwrb_handle->wrb_index); | |
5088 | io_task->pwrb_context->plast_wrb = pwrb; | |
5089 | ||
2c9dfd36 | 5090 | pwrb_typeoffset = SKH_WRB_TYPE_OFFSET; |
09a1093a JSJ |
5091 | } |
5092 | ||
dafab8e0 | 5093 | |
6733b39a JK |
5094 | switch (task->hdr->opcode & ISCSI_OPCODE_MASK) { |
5095 | case ISCSI_OP_LOGIN: | |
6733b39a | 5096 | AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1); |
09a1093a | 5097 | ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); |
e0493627 | 5098 | ret = hwi_write_buffer(pwrb, task); |
6733b39a JK |
5099 | break; |
5100 | case ISCSI_OP_NOOP_OUT: | |
1390b01b | 5101 | if (task->hdr->ttt != ISCSI_RESERVED_TAG) { |
09a1093a | 5102 | ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); |
2c9dfd36 JK |
5103 | if (is_chip_be2_be3r(phba)) |
5104 | AMAP_SET_BITS(struct amap_iscsi_wrb, | |
09a1093a JSJ |
5105 | dmsg, pwrb, 1); |
5106 | else | |
2c9dfd36 | 5107 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, |
09a1093a | 5108 | dmsg, pwrb, 1); |
1390b01b | 5109 | } else { |
09a1093a | 5110 | ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset); |
2c9dfd36 JK |
5111 | if (is_chip_be2_be3r(phba)) |
5112 | AMAP_SET_BITS(struct amap_iscsi_wrb, | |
09a1093a JSJ |
5113 | dmsg, pwrb, 0); |
5114 | else | |
2c9dfd36 | 5115 | AMAP_SET_BITS(struct amap_iscsi_wrb_v2, |
09a1093a | 5116 | dmsg, pwrb, 0); |
1390b01b | 5117 | } |
e0493627 | 5118 | ret = hwi_write_buffer(pwrb, task); |
6733b39a JK |
5119 | break; |
5120 | case ISCSI_OP_TEXT: | |
09a1093a | 5121 | ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset); |
e0493627 | 5122 | ret = hwi_write_buffer(pwrb, task); |
6733b39a JK |
5123 | break; |
5124 | case ISCSI_OP_SCSI_TMFUNC: | |
09a1093a | 5125 | ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset); |
e0493627 | 5126 | ret = hwi_write_buffer(pwrb, task); |
6733b39a JK |
5127 | break; |
5128 | case ISCSI_OP_LOGOUT: | |
09a1093a | 5129 | ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset); |
e0493627 | 5130 | ret = hwi_write_buffer(pwrb, task); |
6733b39a JK |
5131 | break; |
5132 | ||
5133 | default: | |
99bc5d55 JSJ |
5134 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, |
5135 | "BM_%d : opcode =%d Not supported\n", | |
5136 | task->hdr->opcode & ISCSI_OPCODE_MASK); | |
5137 | ||
6733b39a JK |
5138 | return -EINVAL; |
5139 | } | |
5140 | ||
e0493627 AK |
5141 | if (ret) |
5142 | return ret; | |
5143 | ||
09a1093a | 5144 | /* Set the task type */ |
2c9dfd36 JK |
5145 | io_task->wrb_type = (is_chip_be2_be3r(phba)) ? |
5146 | AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) : | |
5147 | AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb); | |
6733b39a | 5148 | |
bfead3b2 | 5149 | doorbell |= cid & DB_WRB_POST_CID_MASK; |
32951dd8 | 5150 | doorbell |= (io_task->pwrb_handle->wrb_index & |
6733b39a JK |
5151 | DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT; |
5152 | doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT; | |
1e4be6ff JK |
5153 | iowrite32(doorbell, phba->db_va + |
5154 | beiscsi_conn->doorbell_offset); | |
6733b39a JK |
5155 | return 0; |
5156 | } | |
5157 | ||
5158 | static int beiscsi_task_xmit(struct iscsi_task *task) | |
5159 | { | |
6733b39a JK |
5160 | struct beiscsi_io_task *io_task = task->dd_data; |
5161 | struct scsi_cmnd *sc = task->sc; | |
1868379b | 5162 | struct beiscsi_hba *phba; |
6733b39a JK |
5163 | struct scatterlist *sg; |
5164 | int num_sg; | |
5165 | unsigned int writedir = 0, xferlen = 0; | |
5166 | ||
1868379b JB |
5167 | if (!io_task->conn->login_in_progress) |
5168 | task->hdr->exp_statsn = 0; | |
09a1093a | 5169 | |
6733b39a JK |
5170 | if (!sc) |
5171 | return beiscsi_mtask(task); | |
5172 | ||
5173 | io_task->scsi_cmnd = sc; | |
5174 | num_sg = scsi_dma_map(sc); | |
1868379b | 5175 | phba = io_task->conn->phba; |
6733b39a | 5176 | if (num_sg < 0) { |
afb96058 JK |
5177 | beiscsi_log(phba, KERN_ERR, |
5178 | BEISCSI_LOG_IO | BEISCSI_LOG_ISCSI, | |
5179 | "BM_%d : scsi_dma_map Failed " | |
5180 | "Driver_ITT : 0x%x ITT : 0x%x Xferlen : 0x%x\n", | |
5181 | be32_to_cpu(io_task->cmd_bhs->iscsi_hdr.itt), | |
5182 | io_task->libiscsi_itt, scsi_bufflen(sc)); | |
99bc5d55 | 5183 | |
6733b39a JK |
5184 | return num_sg; |
5185 | } | |
6733b39a JK |
5186 | xferlen = scsi_bufflen(sc); |
5187 | sg = scsi_sglist(sc); | |
99bc5d55 | 5188 | if (sc->sc_data_direction == DMA_TO_DEVICE) |
6733b39a | 5189 | writedir = 1; |
99bc5d55 | 5190 | else |
6733b39a | 5191 | writedir = 0; |
99bc5d55 | 5192 | |
09a1093a | 5193 | return phba->iotask_fn(task, sg, num_sg, xferlen, writedir); |
6733b39a JK |
5194 | } |
5195 | ||
ffce3e2e JK |
5196 | /** |
5197 | * beiscsi_bsg_request - handle bsg request from ISCSI transport | |
5198 | * @job: job to handle | |
5199 | */ | |
5200 | static int beiscsi_bsg_request(struct bsg_job *job) | |
5201 | { | |
5202 | struct Scsi_Host *shost; | |
5203 | struct beiscsi_hba *phba; | |
5204 | struct iscsi_bsg_request *bsg_req = job->request; | |
5205 | int rc = -EINVAL; | |
5206 | unsigned int tag; | |
5207 | struct be_dma_mem nonemb_cmd; | |
5208 | struct be_cmd_resp_hdr *resp; | |
5209 | struct iscsi_bsg_reply *bsg_reply = job->reply; | |
5210 | unsigned short status, extd_status; | |
5211 | ||
5212 | shost = iscsi_job_to_shost(job); | |
5213 | phba = iscsi_host_priv(shost); | |
5214 | ||
5215 | switch (bsg_req->msgcode) { | |
5216 | case ISCSI_BSG_HST_VENDOR: | |
5217 | nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev, | |
5218 | job->request_payload.payload_len, | |
5219 | &nonemb_cmd.dma); | |
5220 | if (nonemb_cmd.va == NULL) { | |
99bc5d55 JSJ |
5221 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, |
5222 | "BM_%d : Failed to allocate memory for " | |
5223 | "beiscsi_bsg_request\n"); | |
8359c79b | 5224 | return -ENOMEM; |
ffce3e2e JK |
5225 | } |
5226 | tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job, | |
5227 | &nonemb_cmd); | |
5228 | if (!tag) { | |
99bc5d55 | 5229 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, |
8359c79b | 5230 | "BM_%d : MBX Tag Allocation Failed\n"); |
99bc5d55 | 5231 | |
ffce3e2e JK |
5232 | pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, |
5233 | nonemb_cmd.va, nonemb_cmd.dma); | |
5234 | return -EAGAIN; | |
e175defe JSJ |
5235 | } |
5236 | ||
5237 | rc = wait_event_interruptible_timeout( | |
5238 | phba->ctrl.mcc_wait[tag], | |
67296ad9 | 5239 | phba->ctrl.mcc_tag_status[tag], |
e175defe JSJ |
5240 | msecs_to_jiffies( |
5241 | BEISCSI_HOST_MBX_TIMEOUT)); | |
67296ad9 JB |
5242 | extd_status = (phba->ctrl.mcc_tag_status[tag] & |
5243 | CQE_STATUS_ADDL_MASK) >> CQE_STATUS_ADDL_SHIFT; | |
5244 | status = phba->ctrl.mcc_tag_status[tag] & CQE_STATUS_MASK; | |
090e2184 | 5245 | free_mcc_wrb(&phba->ctrl, tag); |
ffce3e2e JK |
5246 | resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va; |
5247 | sg_copy_from_buffer(job->reply_payload.sg_list, | |
5248 | job->reply_payload.sg_cnt, | |
5249 | nonemb_cmd.va, (resp->response_length | |
5250 | + sizeof(*resp))); | |
5251 | bsg_reply->reply_payload_rcv_len = resp->response_length; | |
5252 | bsg_reply->result = status; | |
5253 | bsg_job_done(job, bsg_reply->result, | |
5254 | bsg_reply->reply_payload_rcv_len); | |
5255 | pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size, | |
5256 | nonemb_cmd.va, nonemb_cmd.dma); | |
5257 | if (status || extd_status) { | |
99bc5d55 | 5258 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, |
8359c79b | 5259 | "BM_%d : MBX Cmd Failed" |
99bc5d55 JSJ |
5260 | " status = %d extd_status = %d\n", |
5261 | status, extd_status); | |
5262 | ||
ffce3e2e | 5263 | return -EIO; |
8359c79b JSJ |
5264 | } else { |
5265 | rc = 0; | |
ffce3e2e JK |
5266 | } |
5267 | break; | |
5268 | ||
5269 | default: | |
99bc5d55 JSJ |
5270 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG, |
5271 | "BM_%d : Unsupported bsg command: 0x%x\n", | |
5272 | bsg_req->msgcode); | |
ffce3e2e JK |
5273 | break; |
5274 | } | |
5275 | ||
5276 | return rc; | |
5277 | } | |
5278 | ||
99bc5d55 JSJ |
5279 | void beiscsi_hba_attrs_init(struct beiscsi_hba *phba) |
5280 | { | |
5281 | /* Set the logging parameter */ | |
5282 | beiscsi_log_enable_init(phba, beiscsi_log_enable); | |
5283 | } | |
5284 | ||
4d4d1ef8 JSJ |
5285 | /* |
5286 | * beiscsi_quiesce()- Cleanup Driver resources | |
5287 | * @phba: Instance Priv structure | |
3567f36a | 5288 | * @unload_state:i Clean or EEH unload state |
4d4d1ef8 JSJ |
5289 | * |
5290 | * Free the OS and HW resources held by the driver | |
5291 | **/ | |
3567f36a JK |
5292 | static void beiscsi_quiesce(struct beiscsi_hba *phba, |
5293 | uint32_t unload_state) | |
6733b39a | 5294 | { |
bfead3b2 JK |
5295 | struct hwi_controller *phwi_ctrlr; |
5296 | struct hwi_context_memory *phwi_context; | |
5297 | struct be_eq_obj *pbe_eq; | |
5298 | unsigned int i, msix_vec; | |
6733b39a | 5299 | |
bfead3b2 JK |
5300 | phwi_ctrlr = phba->phwi_ctrlr; |
5301 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
6733b39a | 5302 | hwi_disable_intr(phba); |
bfead3b2 JK |
5303 | if (phba->msix_enabled) { |
5304 | for (i = 0; i <= phba->num_cpus; i++) { | |
5305 | msix_vec = phba->msix_entries[i].vector; | |
3567f36a | 5306 | synchronize_irq(msix_vec); |
bfead3b2 | 5307 | free_irq(msix_vec, &phwi_context->be_eq[i]); |
8fcfb210 | 5308 | kfree(phba->msi_name[i]); |
bfead3b2 JK |
5309 | } |
5310 | } else | |
3567f36a JK |
5311 | if (phba->pcidev->irq) { |
5312 | synchronize_irq(phba->pcidev->irq); | |
bfead3b2 | 5313 | free_irq(phba->pcidev->irq, phba); |
3567f36a | 5314 | } |
bfead3b2 | 5315 | pci_disable_msix(phba->pcidev); |
53281edb | 5316 | cancel_delayed_work_sync(&phba->beiscsi_hw_check_task); |
3567f36a | 5317 | |
89f8b33c JA |
5318 | for (i = 0; i < phba->num_cpus; i++) { |
5319 | pbe_eq = &phwi_context->be_eq[i]; | |
511cbce2 | 5320 | irq_poll_disable(&pbe_eq->iopoll); |
89f8b33c | 5321 | } |
6733b39a | 5322 | |
3567f36a JK |
5323 | if (unload_state == BEISCSI_CLEAN_UNLOAD) { |
5324 | destroy_workqueue(phba->wq); | |
5325 | beiscsi_clean_port(phba); | |
5326 | beiscsi_free_mem(phba); | |
e9b91193 | 5327 | |
3567f36a JK |
5328 | beiscsi_unmap_pci_function(phba); |
5329 | pci_free_consistent(phba->pcidev, | |
5330 | phba->ctrl.mbox_mem_alloced.size, | |
5331 | phba->ctrl.mbox_mem_alloced.va, | |
5332 | phba->ctrl.mbox_mem_alloced.dma); | |
5333 | } else { | |
5334 | hwi_purge_eq(phba); | |
5335 | hwi_cleanup(phba); | |
5336 | } | |
7a158003 | 5337 | |
25602c97 JK |
5338 | } |
5339 | ||
5340 | static void beiscsi_remove(struct pci_dev *pcidev) | |
5341 | { | |
25602c97 JK |
5342 | struct beiscsi_hba *phba = NULL; |
5343 | ||
5344 | phba = pci_get_drvdata(pcidev); | |
5345 | if (!phba) { | |
5346 | dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n"); | |
5347 | return; | |
5348 | } | |
5349 | ||
0e43895e | 5350 | beiscsi_destroy_def_ifaces(phba); |
9d045163 | 5351 | iscsi_boot_destroy_kset(phba->boot_kset); |
6733b39a | 5352 | iscsi_host_remove(phba->shost); |
cdaa4ded | 5353 | beiscsi_quiesce(phba, BEISCSI_CLEAN_UNLOAD); |
6733b39a JK |
5354 | pci_dev_put(phba->pcidev); |
5355 | iscsi_host_free(phba->shost); | |
3567f36a JK |
5356 | pci_disable_pcie_error_reporting(pcidev); |
5357 | pci_set_drvdata(pcidev, NULL); | |
e307f3ac | 5358 | pci_release_regions(pcidev); |
8dce69ff | 5359 | pci_disable_device(pcidev); |
6733b39a JK |
5360 | } |
5361 | ||
bfead3b2 JK |
5362 | static void beiscsi_msix_enable(struct beiscsi_hba *phba) |
5363 | { | |
5364 | int i, status; | |
5365 | ||
5366 | for (i = 0; i <= phba->num_cpus; i++) | |
5367 | phba->msix_entries[i].entry = i; | |
5368 | ||
e149fc13 AG |
5369 | status = pci_enable_msix_range(phba->pcidev, phba->msix_entries, |
5370 | phba->num_cpus + 1, phba->num_cpus + 1); | |
5371 | if (status > 0) | |
bfead3b2 JK |
5372 | phba->msix_enabled = true; |
5373 | ||
5374 | return; | |
5375 | } | |
5376 | ||
73af08e1 JK |
5377 | static void be_eqd_update(struct beiscsi_hba *phba) |
5378 | { | |
5379 | struct be_set_eqd set_eqd[MAX_CPUS]; | |
5380 | struct be_aic_obj *aic; | |
5381 | struct be_eq_obj *pbe_eq; | |
5382 | struct hwi_controller *phwi_ctrlr; | |
5383 | struct hwi_context_memory *phwi_context; | |
5384 | int eqd, i, num = 0; | |
5385 | ulong now; | |
5386 | u32 pps, delta; | |
5387 | unsigned int tag; | |
5388 | ||
5389 | phwi_ctrlr = phba->phwi_ctrlr; | |
5390 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
5391 | ||
5392 | for (i = 0; i <= phba->num_cpus; i++) { | |
5393 | aic = &phba->aic_obj[i]; | |
5394 | pbe_eq = &phwi_context->be_eq[i]; | |
5395 | now = jiffies; | |
5396 | if (!aic->jiffs || time_before(now, aic->jiffs) || | |
5397 | pbe_eq->cq_count < aic->eq_prev) { | |
5398 | aic->jiffs = now; | |
5399 | aic->eq_prev = pbe_eq->cq_count; | |
5400 | continue; | |
5401 | } | |
5402 | delta = jiffies_to_msecs(now - aic->jiffs); | |
5403 | pps = (((u32)(pbe_eq->cq_count - aic->eq_prev) * 1000) / delta); | |
5404 | eqd = (pps / 1500) << 2; | |
5405 | ||
5406 | if (eqd < 8) | |
5407 | eqd = 0; | |
5408 | eqd = min_t(u32, eqd, phwi_context->max_eqd); | |
5409 | eqd = max_t(u32, eqd, phwi_context->min_eqd); | |
5410 | ||
5411 | aic->jiffs = now; | |
5412 | aic->eq_prev = pbe_eq->cq_count; | |
5413 | ||
5414 | if (eqd != aic->prev_eqd) { | |
5415 | set_eqd[num].delay_multiplier = (eqd * 65)/100; | |
5416 | set_eqd[num].eq_id = pbe_eq->q.id; | |
5417 | aic->prev_eqd = eqd; | |
5418 | num++; | |
5419 | } | |
5420 | } | |
5421 | if (num) { | |
5422 | tag = be_cmd_modify_eq_delay(phba, set_eqd, num); | |
5423 | if (tag) | |
88840332 | 5424 | beiscsi_mccq_compl_wait(phba, tag, NULL, NULL); |
73af08e1 JK |
5425 | } |
5426 | } | |
5427 | ||
a3d313ea JK |
5428 | static void be_check_boot_session(struct beiscsi_hba *phba) |
5429 | { | |
5430 | if (beiscsi_setup_boot_info(phba)) | |
5431 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5432 | "BM_%d : Could not set up " | |
5433 | "iSCSI boot info on async event.\n"); | |
5434 | } | |
5435 | ||
7a158003 JSJ |
5436 | /* |
5437 | * beiscsi_hw_health_check()- Check adapter health | |
5438 | * @work: work item to check HW health | |
5439 | * | |
5440 | * Check if adapter in an unrecoverable state or not. | |
5441 | **/ | |
5442 | static void | |
5443 | beiscsi_hw_health_check(struct work_struct *work) | |
5444 | { | |
5445 | struct beiscsi_hba *phba = | |
5446 | container_of(work, struct beiscsi_hba, | |
5447 | beiscsi_hw_check_task.work); | |
5448 | ||
73af08e1 JK |
5449 | be_eqd_update(phba); |
5450 | ||
a3d313ea | 5451 | if (phba->state & BE_ADAPTER_CHECK_BOOT) { |
3efde862 JSJ |
5452 | if ((phba->get_boot > 0) && (!phba->boot_kset)) { |
5453 | phba->get_boot--; | |
5454 | if (!(phba->get_boot % BE_GET_BOOT_TO)) | |
5455 | be_check_boot_session(phba); | |
5456 | } else { | |
5457 | phba->state &= ~BE_ADAPTER_CHECK_BOOT; | |
5458 | phba->get_boot = 0; | |
5459 | } | |
a3d313ea JK |
5460 | } |
5461 | ||
7a158003 JSJ |
5462 | beiscsi_ue_detect(phba); |
5463 | ||
5464 | schedule_delayed_work(&phba->beiscsi_hw_check_task, | |
5465 | msecs_to_jiffies(1000)); | |
5466 | } | |
5467 | ||
3567f36a JK |
5468 | |
5469 | static pci_ers_result_t beiscsi_eeh_err_detected(struct pci_dev *pdev, | |
5470 | pci_channel_state_t state) | |
5471 | { | |
5472 | struct beiscsi_hba *phba = NULL; | |
5473 | ||
5474 | phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); | |
5475 | phba->state |= BE_ADAPTER_PCI_ERR; | |
5476 | ||
5477 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5478 | "BM_%d : EEH error detected\n"); | |
5479 | ||
5480 | beiscsi_quiesce(phba, BEISCSI_EEH_UNLOAD); | |
5481 | ||
5482 | if (state == pci_channel_io_perm_failure) { | |
5483 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5484 | "BM_%d : EEH : State PERM Failure"); | |
5485 | return PCI_ERS_RESULT_DISCONNECT; | |
5486 | } | |
5487 | ||
5488 | pci_disable_device(pdev); | |
5489 | ||
5490 | /* The error could cause the FW to trigger a flash debug dump. | |
5491 | * Resetting the card while flash dump is in progress | |
5492 | * can cause it not to recover; wait for it to finish. | |
5493 | * Wait only for first function as it is needed only once per | |
5494 | * adapter. | |
5495 | **/ | |
5496 | if (pdev->devfn == 0) | |
5497 | ssleep(30); | |
5498 | ||
5499 | return PCI_ERS_RESULT_NEED_RESET; | |
5500 | } | |
5501 | ||
5502 | static pci_ers_result_t beiscsi_eeh_reset(struct pci_dev *pdev) | |
5503 | { | |
5504 | struct beiscsi_hba *phba = NULL; | |
5505 | int status = 0; | |
5506 | ||
5507 | phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); | |
5508 | ||
5509 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5510 | "BM_%d : EEH Reset\n"); | |
5511 | ||
5512 | status = pci_enable_device(pdev); | |
5513 | if (status) | |
5514 | return PCI_ERS_RESULT_DISCONNECT; | |
5515 | ||
5516 | pci_set_master(pdev); | |
5517 | pci_set_power_state(pdev, PCI_D0); | |
5518 | pci_restore_state(pdev); | |
5519 | ||
5520 | /* Wait for the CHIP Reset to complete */ | |
5521 | status = be_chk_reset_complete(phba); | |
5522 | if (!status) { | |
5523 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, | |
5524 | "BM_%d : EEH Reset Completed\n"); | |
5525 | } else { | |
5526 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, | |
5527 | "BM_%d : EEH Reset Completion Failure\n"); | |
5528 | return PCI_ERS_RESULT_DISCONNECT; | |
5529 | } | |
5530 | ||
5531 | pci_cleanup_aer_uncorrect_error_status(pdev); | |
5532 | return PCI_ERS_RESULT_RECOVERED; | |
5533 | } | |
5534 | ||
5535 | static void beiscsi_eeh_resume(struct pci_dev *pdev) | |
5536 | { | |
5537 | int ret = 0, i; | |
5538 | struct be_eq_obj *pbe_eq; | |
5539 | struct beiscsi_hba *phba = NULL; | |
5540 | struct hwi_controller *phwi_ctrlr; | |
5541 | struct hwi_context_memory *phwi_context; | |
5542 | ||
5543 | phba = (struct beiscsi_hba *)pci_get_drvdata(pdev); | |
5544 | pci_save_state(pdev); | |
5545 | ||
5546 | if (enable_msix) | |
5547 | find_num_cpus(phba); | |
5548 | else | |
5549 | phba->num_cpus = 1; | |
5550 | ||
5551 | if (enable_msix) { | |
5552 | beiscsi_msix_enable(phba); | |
5553 | if (!phba->msix_enabled) | |
5554 | phba->num_cpus = 1; | |
5555 | } | |
5556 | ||
5557 | ret = beiscsi_cmd_reset_function(phba); | |
5558 | if (ret) { | |
5559 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5560 | "BM_%d : Reset Failed\n"); | |
5561 | goto ret_err; | |
5562 | } | |
5563 | ||
5564 | ret = be_chk_reset_complete(phba); | |
5565 | if (ret) { | |
5566 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5567 | "BM_%d : Failed to get out of reset.\n"); | |
5568 | goto ret_err; | |
5569 | } | |
5570 | ||
5571 | beiscsi_get_params(phba); | |
5572 | phba->shost->max_id = phba->params.cxns_per_ctrl; | |
5573 | phba->shost->can_queue = phba->params.ios_per_ctrl; | |
5574 | ret = hwi_init_controller(phba); | |
5575 | ||
5576 | for (i = 0; i < MAX_MCC_CMD; i++) { | |
5577 | init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]); | |
5578 | phba->ctrl.mcc_tag[i] = i + 1; | |
67296ad9 | 5579 | phba->ctrl.mcc_tag_status[i + 1] = 0; |
3567f36a JK |
5580 | phba->ctrl.mcc_tag_available++; |
5581 | } | |
5582 | ||
5583 | phwi_ctrlr = phba->phwi_ctrlr; | |
5584 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
5585 | ||
89f8b33c | 5586 | for (i = 0; i < phba->num_cpus; i++) { |
3567f36a | 5587 | pbe_eq = &phwi_context->be_eq[i]; |
511cbce2 | 5588 | irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget, |
89f8b33c | 5589 | be_iopoll); |
3567f36a JK |
5590 | } |
5591 | ||
89f8b33c JA |
5592 | i = (phba->msix_enabled) ? i : 0; |
5593 | /* Work item for MCC handling */ | |
5594 | pbe_eq = &phwi_context->be_eq[i]; | |
5595 | INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs); | |
5596 | ||
3567f36a JK |
5597 | ret = beiscsi_init_irqs(phba); |
5598 | if (ret < 0) { | |
5599 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5600 | "BM_%d : beiscsi_eeh_resume - " | |
5601 | "Failed to beiscsi_init_irqs\n"); | |
5602 | goto ret_err; | |
5603 | } | |
5604 | ||
5605 | hwi_enable_intr(phba); | |
5606 | phba->state &= ~BE_ADAPTER_PCI_ERR; | |
5607 | ||
5608 | return; | |
5609 | ret_err: | |
5610 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
5611 | "BM_%d : AER EEH Resume Failed\n"); | |
5612 | } | |
5613 | ||
6f039790 GKH |
5614 | static int beiscsi_dev_probe(struct pci_dev *pcidev, |
5615 | const struct pci_device_id *id) | |
6733b39a JK |
5616 | { |
5617 | struct beiscsi_hba *phba = NULL; | |
bfead3b2 JK |
5618 | struct hwi_controller *phwi_ctrlr; |
5619 | struct hwi_context_memory *phwi_context; | |
5620 | struct be_eq_obj *pbe_eq; | |
3567f36a | 5621 | int ret = 0, i; |
6733b39a JK |
5622 | |
5623 | ret = beiscsi_enable_pci(pcidev); | |
5624 | if (ret < 0) { | |
99bc5d55 JSJ |
5625 | dev_err(&pcidev->dev, |
5626 | "beiscsi_dev_probe - Failed to enable pci device\n"); | |
6733b39a JK |
5627 | return ret; |
5628 | } | |
5629 | ||
5630 | phba = beiscsi_hba_alloc(pcidev); | |
5631 | if (!phba) { | |
99bc5d55 JSJ |
5632 | dev_err(&pcidev->dev, |
5633 | "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n"); | |
6733b39a JK |
5634 | goto disable_pci; |
5635 | } | |
5636 | ||
3567f36a JK |
5637 | /* Enable EEH reporting */ |
5638 | ret = pci_enable_pcie_error_reporting(pcidev); | |
5639 | if (ret) | |
5640 | beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT, | |
5641 | "BM_%d : PCIe Error Reporting " | |
5642 | "Enabling Failed\n"); | |
5643 | ||
5644 | pci_save_state(pcidev); | |
5645 | ||
99bc5d55 JSJ |
5646 | /* Initialize Driver configuration Paramters */ |
5647 | beiscsi_hba_attrs_init(phba); | |
5648 | ||
e175defe | 5649 | phba->fw_timeout = false; |
6c83185a | 5650 | phba->mac_addr_set = false; |
e175defe JSJ |
5651 | |
5652 | ||
f98c96b0 JK |
5653 | switch (pcidev->device) { |
5654 | case BE_DEVICE_ID1: | |
5655 | case OC_DEVICE_ID1: | |
5656 | case OC_DEVICE_ID2: | |
5657 | phba->generation = BE_GEN2; | |
09a1093a | 5658 | phba->iotask_fn = beiscsi_iotask; |
f98c96b0 JK |
5659 | break; |
5660 | case BE_DEVICE_ID2: | |
5661 | case OC_DEVICE_ID3: | |
5662 | phba->generation = BE_GEN3; | |
09a1093a | 5663 | phba->iotask_fn = beiscsi_iotask; |
f98c96b0 | 5664 | break; |
139a1b1e JSJ |
5665 | case OC_SKH_ID1: |
5666 | phba->generation = BE_GEN4; | |
09a1093a | 5667 | phba->iotask_fn = beiscsi_iotask_v2; |
bf9131cb | 5668 | break; |
f98c96b0 JK |
5669 | default: |
5670 | phba->generation = 0; | |
5671 | } | |
5672 | ||
6733b39a JK |
5673 | ret = be_ctrl_init(phba, pcidev); |
5674 | if (ret) { | |
99bc5d55 JSJ |
5675 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
5676 | "BM_%d : beiscsi_dev_probe-" | |
5677 | "Failed in be_ctrl_init\n"); | |
6733b39a JK |
5678 | goto hba_free; |
5679 | } | |
5680 | ||
cdaa4ded JB |
5681 | /* |
5682 | * FUNCTION_RESET should clean up any stale info in FW for this fn | |
5683 | */ | |
4d4d1ef8 JSJ |
5684 | ret = beiscsi_cmd_reset_function(phba); |
5685 | if (ret) { | |
5686 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
92665a66 | 5687 | "BM_%d : Reset Failed\n"); |
4d4d1ef8 JSJ |
5688 | goto hba_free; |
5689 | } | |
5690 | ret = be_chk_reset_complete(phba); | |
5691 | if (ret) { | |
5692 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, | |
92665a66 | 5693 | "BM_%d : Failed to get out of reset.\n"); |
4d4d1ef8 | 5694 | goto hba_free; |
e9b91193 JK |
5695 | } |
5696 | ||
6733b39a JK |
5697 | spin_lock_init(&phba->io_sgl_lock); |
5698 | spin_lock_init(&phba->mgmt_sgl_lock); | |
5699 | spin_lock_init(&phba->isr_lock); | |
8f09a3b9 | 5700 | spin_lock_init(&phba->async_pdu_lock); |
7da50879 JK |
5701 | ret = mgmt_get_fw_config(&phba->ctrl, phba); |
5702 | if (ret != 0) { | |
99bc5d55 JSJ |
5703 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
5704 | "BM_%d : Error getting fw config\n"); | |
7da50879 JK |
5705 | goto free_port; |
5706 | } | |
53aefe25 | 5707 | mgmt_get_port_name(&phba->ctrl, phba); |
4570f161 | 5708 | beiscsi_get_params(phba); |
68c26a3a JK |
5709 | |
5710 | if (enable_msix) | |
5711 | find_num_cpus(phba); | |
5712 | else | |
5713 | phba->num_cpus = 1; | |
5714 | ||
5715 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, | |
5716 | "BM_%d : num_cpus = %d\n", | |
5717 | phba->num_cpus); | |
5718 | ||
5719 | if (enable_msix) { | |
5720 | beiscsi_msix_enable(phba); | |
5721 | if (!phba->msix_enabled) | |
5722 | phba->num_cpus = 1; | |
5723 | } | |
5724 | ||
843ae752 | 5725 | phba->shost->max_id = phba->params.cxns_per_ctrl; |
aa874f07 | 5726 | phba->shost->can_queue = phba->params.ios_per_ctrl; |
6733b39a JK |
5727 | ret = beiscsi_init_port(phba); |
5728 | if (ret < 0) { | |
99bc5d55 JSJ |
5729 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
5730 | "BM_%d : beiscsi_dev_probe-" | |
5731 | "Failed in beiscsi_init_port\n"); | |
6733b39a JK |
5732 | goto free_port; |
5733 | } | |
5734 | ||
3567f36a | 5735 | for (i = 0; i < MAX_MCC_CMD; i++) { |
756d29c8 JK |
5736 | init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]); |
5737 | phba->ctrl.mcc_tag[i] = i + 1; | |
67296ad9 | 5738 | phba->ctrl.mcc_tag_status[i + 1] = 0; |
756d29c8 | 5739 | phba->ctrl.mcc_tag_available++; |
1957aa7f | 5740 | memset(&phba->ctrl.ptag_state[i].tag_mem_state, 0, |
8fc01eaa | 5741 | sizeof(struct be_dma_mem)); |
756d29c8 JK |
5742 | } |
5743 | ||
5744 | phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0; | |
5745 | ||
72fb46a9 | 5746 | snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq", |
6733b39a | 5747 | phba->shost->host_no); |
d8537548 | 5748 | phba->wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 1, phba->wq_name); |
6733b39a | 5749 | if (!phba->wq) { |
99bc5d55 JSJ |
5750 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
5751 | "BM_%d : beiscsi_dev_probe-" | |
5752 | "Failed to allocate work queue\n"); | |
6733b39a JK |
5753 | goto free_twq; |
5754 | } | |
5755 | ||
7a158003 JSJ |
5756 | INIT_DELAYED_WORK(&phba->beiscsi_hw_check_task, |
5757 | beiscsi_hw_health_check); | |
6733b39a | 5758 | |
bfead3b2 JK |
5759 | phwi_ctrlr = phba->phwi_ctrlr; |
5760 | phwi_context = phwi_ctrlr->phwi_ctxt; | |
72fb46a9 | 5761 | |
89f8b33c | 5762 | for (i = 0; i < phba->num_cpus; i++) { |
72fb46a9 | 5763 | pbe_eq = &phwi_context->be_eq[i]; |
511cbce2 | 5764 | irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget, |
89f8b33c | 5765 | be_iopoll); |
6733b39a | 5766 | } |
72fb46a9 | 5767 | |
89f8b33c JA |
5768 | i = (phba->msix_enabled) ? i : 0; |
5769 | /* Work item for MCC handling */ | |
5770 | pbe_eq = &phwi_context->be_eq[i]; | |
5771 | INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs); | |
5772 | ||
6733b39a JK |
5773 | ret = beiscsi_init_irqs(phba); |
5774 | if (ret < 0) { | |
99bc5d55 JSJ |
5775 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
5776 | "BM_%d : beiscsi_dev_probe-" | |
5777 | "Failed to beiscsi_init_irqs\n"); | |
6733b39a JK |
5778 | goto free_blkenbld; |
5779 | } | |
238f6b72 | 5780 | hwi_enable_intr(phba); |
f457a46f | 5781 | |
0598b8af JK |
5782 | if (iscsi_host_add(phba->shost, &phba->pcidev->dev)) |
5783 | goto free_blkenbld; | |
5784 | ||
f457a46f MC |
5785 | if (beiscsi_setup_boot_info(phba)) |
5786 | /* | |
5787 | * log error but continue, because we may not be using | |
5788 | * iscsi boot. | |
5789 | */ | |
99bc5d55 JSJ |
5790 | beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, |
5791 | "BM_%d : Could not set up " | |
5792 | "iSCSI boot info.\n"); | |
f457a46f | 5793 | |
0e43895e | 5794 | beiscsi_create_def_ifaces(phba); |
7a158003 JSJ |
5795 | schedule_delayed_work(&phba->beiscsi_hw_check_task, |
5796 | msecs_to_jiffies(1000)); | |
5797 | ||
99bc5d55 JSJ |
5798 | beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT, |
5799 | "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n"); | |
6733b39a JK |
5800 | return 0; |
5801 | ||
6733b39a JK |
5802 | free_blkenbld: |
5803 | destroy_workqueue(phba->wq); | |
89f8b33c JA |
5804 | for (i = 0; i < phba->num_cpus; i++) { |
5805 | pbe_eq = &phwi_context->be_eq[i]; | |
511cbce2 | 5806 | irq_poll_disable(&pbe_eq->iopoll); |
89f8b33c | 5807 | } |
6733b39a JK |
5808 | free_twq: |
5809 | beiscsi_clean_port(phba); | |
5810 | beiscsi_free_mem(phba); | |
5811 | free_port: | |
5812 | pci_free_consistent(phba->pcidev, | |
5813 | phba->ctrl.mbox_mem_alloced.size, | |
5814 | phba->ctrl.mbox_mem_alloced.va, | |
5815 | phba->ctrl.mbox_mem_alloced.dma); | |
5816 | beiscsi_unmap_pci_function(phba); | |
5817 | hba_free: | |
238f6b72 JK |
5818 | if (phba->msix_enabled) |
5819 | pci_disable_msix(phba->pcidev); | |
6733b39a JK |
5820 | pci_dev_put(phba->pcidev); |
5821 | iscsi_host_free(phba->shost); | |
2e7cee02 | 5822 | pci_set_drvdata(pcidev, NULL); |
6733b39a | 5823 | disable_pci: |
e307f3ac | 5824 | pci_release_regions(pcidev); |
6733b39a JK |
5825 | pci_disable_device(pcidev); |
5826 | return ret; | |
5827 | } | |
5828 | ||
3567f36a JK |
5829 | static struct pci_error_handlers beiscsi_eeh_handlers = { |
5830 | .error_detected = beiscsi_eeh_err_detected, | |
5831 | .slot_reset = beiscsi_eeh_reset, | |
5832 | .resume = beiscsi_eeh_resume, | |
5833 | }; | |
5834 | ||
6733b39a JK |
5835 | struct iscsi_transport beiscsi_iscsi_transport = { |
5836 | .owner = THIS_MODULE, | |
5837 | .name = DRV_NAME, | |
9db0fb3a | 5838 | .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO | |
6733b39a | 5839 | CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD, |
6733b39a JK |
5840 | .create_session = beiscsi_session_create, |
5841 | .destroy_session = beiscsi_session_destroy, | |
5842 | .create_conn = beiscsi_conn_create, | |
5843 | .bind_conn = beiscsi_conn_bind, | |
5844 | .destroy_conn = iscsi_conn_teardown, | |
3128c6c7 | 5845 | .attr_is_visible = be2iscsi_attr_is_visible, |
0e43895e MC |
5846 | .set_iface_param = be2iscsi_iface_set_param, |
5847 | .get_iface_param = be2iscsi_iface_get_param, | |
6733b39a | 5848 | .set_param = beiscsi_set_param, |
c7f7fd5b | 5849 | .get_conn_param = iscsi_conn_get_param, |
6733b39a JK |
5850 | .get_session_param = iscsi_session_get_param, |
5851 | .get_host_param = beiscsi_get_host_param, | |
5852 | .start_conn = beiscsi_conn_start, | |
fa95d206 | 5853 | .stop_conn = iscsi_conn_stop, |
6733b39a JK |
5854 | .send_pdu = iscsi_conn_send_pdu, |
5855 | .xmit_task = beiscsi_task_xmit, | |
5856 | .cleanup_task = beiscsi_cleanup_task, | |
5857 | .alloc_pdu = beiscsi_alloc_pdu, | |
5858 | .parse_pdu_itt = beiscsi_parse_pdu, | |
5859 | .get_stats = beiscsi_conn_get_stats, | |
c7f7fd5b | 5860 | .get_ep_param = beiscsi_ep_get_param, |
6733b39a JK |
5861 | .ep_connect = beiscsi_ep_connect, |
5862 | .ep_poll = beiscsi_ep_poll, | |
5863 | .ep_disconnect = beiscsi_ep_disconnect, | |
5864 | .session_recovery_timedout = iscsi_session_recovery_timedout, | |
ffce3e2e | 5865 | .bsg_request = beiscsi_bsg_request, |
6733b39a JK |
5866 | }; |
5867 | ||
5868 | static struct pci_driver beiscsi_pci_driver = { | |
5869 | .name = DRV_NAME, | |
5870 | .probe = beiscsi_dev_probe, | |
5871 | .remove = beiscsi_remove, | |
3567f36a JK |
5872 | .id_table = beiscsi_pci_id_table, |
5873 | .err_handler = &beiscsi_eeh_handlers | |
6733b39a JK |
5874 | }; |
5875 | ||
bfead3b2 | 5876 | |
6733b39a JK |
5877 | static int __init beiscsi_module_init(void) |
5878 | { | |
5879 | int ret; | |
5880 | ||
5881 | beiscsi_scsi_transport = | |
5882 | iscsi_register_transport(&beiscsi_iscsi_transport); | |
5883 | if (!beiscsi_scsi_transport) { | |
99bc5d55 JSJ |
5884 | printk(KERN_ERR |
5885 | "beiscsi_module_init - Unable to register beiscsi transport.\n"); | |
f55a24f2 | 5886 | return -ENOMEM; |
6733b39a | 5887 | } |
99bc5d55 JSJ |
5888 | printk(KERN_INFO "In beiscsi_module_init, tt=%p\n", |
5889 | &beiscsi_iscsi_transport); | |
6733b39a JK |
5890 | |
5891 | ret = pci_register_driver(&beiscsi_pci_driver); | |
5892 | if (ret) { | |
99bc5d55 JSJ |
5893 | printk(KERN_ERR |
5894 | "beiscsi_module_init - Unable to register beiscsi pci driver.\n"); | |
6733b39a JK |
5895 | goto unregister_iscsi_transport; |
5896 | } | |
5897 | return 0; | |
5898 | ||
5899 | unregister_iscsi_transport: | |
5900 | iscsi_unregister_transport(&beiscsi_iscsi_transport); | |
5901 | return ret; | |
5902 | } | |
5903 | ||
5904 | static void __exit beiscsi_module_exit(void) | |
5905 | { | |
5906 | pci_unregister_driver(&beiscsi_pci_driver); | |
5907 | iscsi_unregister_transport(&beiscsi_iscsi_transport); | |
5908 | } | |
5909 | ||
5910 | module_init(beiscsi_module_init); | |
5911 | module_exit(beiscsi_module_exit); |