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scsi: ufs: fix typo in comment
[linux-2.6-block.git] / drivers / scsi / be2iscsi / be_main.c
CommitLineData
6733b39a 1/**
c4f39bda 2 * Copyright (C) 2005 - 2015 Emulex
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
4627de93 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@avagotech.com)
6733b39a
JK		 11 *
12 * Contact Information:
4627de93 13 * linux-drivers@avagotech.com
6733b39a 14 *
c4f39bda 15 * Emulex
255fa9a3
JK		 16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a 18 */
255fa9a3 19
6733b39a
JK		 20#include <linux/reboot.h>
21#include <linux/delay.h>
5a0e3ad6 22#include <linux/slab.h>
6733b39a
JK		 23#include <linux/interrupt.h>
24#include <linux/blkdev.h>
25#include <linux/pci.h>
26#include <linux/string.h>
27#include <linux/kernel.h>
28#include <linux/semaphore.h>
c7acc5b8 29#include <linux/iscsi_boot_sysfs.h>
acf3368f 30#include <linux/module.h>
ffce3e2e 31#include <linux/bsg-lib.h>
1094cf68 32#include <linux/irq_poll.h>
6733b39a
JK		 33
34#include <scsi/libiscsi.h>
ffce3e2e
JK		 35#include <scsi/scsi_bsg_iscsi.h>
36#include <scsi/scsi_netlink.h>
6733b39a
JK		 37#include <scsi/scsi_transport_iscsi.h>
38#include <scsi/scsi_transport.h>
39#include <scsi/scsi_cmnd.h>
40#include <scsi/scsi_device.h>
41#include <scsi/scsi_host.h>
42#include <scsi/scsi.h>
43#include "be_main.h"
44#include "be_iscsi.h"
45#include "be_mgmt.h"
0a513dd8 46#include "be_cmds.h"
6733b39a
JK		 47
48static unsigned int be_iopoll_budget = 10;
49static unsigned int be_max_phys_size = 64;
bfead3b2 50static unsigned int enable_msix = 1;
6733b39a 51
6733b39a 52MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
76d15dbd 53MODULE_VERSION(BUILD_STR);
c4f39bda 54MODULE_AUTHOR("Emulex Corporation");
6733b39a
JK		 55MODULE_LICENSE("GPL");
56module_param(be_iopoll_budget, int, 0);
57module_param(enable_msix, int, 0);
58module_param(be_max_phys_size, uint, S_IRUGO);
99bc5d55
JSJ		 59MODULE_PARM_DESC(be_max_phys_size,
60 "Maximum Size (In Kilobytes) of physically contiguous "
61 "memory that can be allocated. Range is 16 - 128");
62
63#define beiscsi_disp_param(_name)\
64ssize_t \
65beiscsi_##_name##_disp(struct device *dev,\
66 struct device_attribute *attrib, char *buf) \
67{ \
68 struct Scsi_Host *shost = class_to_shost(dev);\
69 struct beiscsi_hba *phba = iscsi_host_priv(shost); \
70 uint32_t param_val = 0; \
71 param_val = phba->attr_##_name;\
72 return snprintf(buf, PAGE_SIZE, "%d\n",\
73 phba->attr_##_name);\
74}
75
76#define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
77int \
78beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
79{\
80 if (val >= _minval && val <= _maxval) {\
81 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
82 "BA_%d : beiscsi_"#_name" updated "\
83 "from 0x%x ==> 0x%x\n",\
84 phba->attr_##_name, val); \
85 phba->attr_##_name = val;\
86 return 0;\
87 } \
88 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
89 "BA_%d beiscsi_"#_name" attribute "\
90 "cannot be updated to 0x%x, "\
91 "range allowed is ["#_minval" - "#_maxval"]\n", val);\
92 return -EINVAL;\
93}
94
95#define beiscsi_store_param(_name) \
96ssize_t \
97beiscsi_##_name##_store(struct device *dev,\
98 struct device_attribute *attr, const char *buf,\
99 size_t count) \
100{ \
101 struct Scsi_Host *shost = class_to_shost(dev);\
102 struct beiscsi_hba *phba = iscsi_host_priv(shost);\
103 uint32_t param_val = 0;\
104 if (!isdigit(buf[0]))\
105 return -EINVAL;\
106 if (sscanf(buf, "%i", &param_val) != 1)\
107 return -EINVAL;\
108 if (beiscsi_##_name##_change(phba, param_val) == 0) \
109 return strlen(buf);\
110 else \
111 return -EINVAL;\
112}
113
114#define beiscsi_init_param(_name, _minval, _maxval, _defval) \
115int \
116beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
117{ \
118 if (val >= _minval && val <= _maxval) {\
119 phba->attr_##_name = val;\
120 return 0;\
121 } \
122 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
123 "BA_%d beiscsi_"#_name" attribute " \
124 "cannot be updated to 0x%x, "\
125 "range allowed is ["#_minval" - "#_maxval"]\n", val);\
126 phba->attr_##_name = _defval;\
127 return -EINVAL;\
128}
129
130#define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
131static uint beiscsi_##_name = _defval;\
132module_param(beiscsi_##_name, uint, S_IRUGO);\
133MODULE_PARM_DESC(beiscsi_##_name, _descp);\
134beiscsi_disp_param(_name)\
135beiscsi_change_param(_name, _minval, _maxval, _defval)\
136beiscsi_store_param(_name)\
137beiscsi_init_param(_name, _minval, _maxval, _defval)\
138DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
139 beiscsi_##_name##_disp, beiscsi_##_name##_store)
140
141/*
142 * When new log level added update the
143 * the MAX allowed value for log_enable
144 */
145BEISCSI_RW_ATTR(log_enable, 0x00,
146 0xFF, 0x00, "Enable logging Bit Mask\n"
147 "\t\t\t\tInitialization Events : 0x01\n"
148 "\t\t\t\tMailbox Events : 0x02\n"
149 "\t\t\t\tMiscellaneous Events : 0x04\n"
150 "\t\t\t\tError Handling : 0x08\n"
151 "\t\t\t\tIO Path Events : 0x10\n"
afb96058
JK		 152 "\t\t\t\tConfiguration Path : 0x20\n"
153 "\t\t\t\tiSCSI Protocol : 0x40\n");
99bc5d55 154
5cac7596 155DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
26000db7 156DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL);
22661e25 157DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL);
d3fea9af 158DEVICE_ATTR(beiscsi_phys_port, S_IRUGO, beiscsi_phys_port_disp, NULL);
6103c1f7
JK		 159DEVICE_ATTR(beiscsi_active_session_count, S_IRUGO,
160 beiscsi_active_session_disp, NULL);
161DEVICE_ATTR(beiscsi_free_session_count, S_IRUGO,
162 beiscsi_free_session_disp, NULL);
99bc5d55
JSJ		 163struct device_attribute *beiscsi_attrs[] = {
164 &dev_attr_beiscsi_log_enable,
5cac7596 165 &dev_attr_beiscsi_drvr_ver,
26000db7 166 &dev_attr_beiscsi_adapter_family,
22661e25 167 &dev_attr_beiscsi_fw_ver,
6103c1f7
JK		 168 &dev_attr_beiscsi_active_session_count,
169 &dev_attr_beiscsi_free_session_count,
d3fea9af 170 &dev_attr_beiscsi_phys_port,
99bc5d55
JSJ		 171 NULL,
172};
6733b39a 173
6763daae
JSJ		 174static char const *cqe_desc[] = {
175 "RESERVED_DESC",
176 "SOL_CMD_COMPLETE",
177 "SOL_CMD_KILLED_DATA_DIGEST_ERR",
178 "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
179 "CXN_KILLED_BURST_LEN_MISMATCH",
180 "CXN_KILLED_AHS_RCVD",
181 "CXN_KILLED_HDR_DIGEST_ERR",
182 "CXN_KILLED_UNKNOWN_HDR",
183 "CXN_KILLED_STALE_ITT_TTT_RCVD",
184 "CXN_KILLED_INVALID_ITT_TTT_RCVD",
185 "CXN_KILLED_RST_RCVD",
186 "CXN_KILLED_TIMED_OUT",
187 "CXN_KILLED_RST_SENT",
188 "CXN_KILLED_FIN_RCVD",
189 "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
190 "CXN_KILLED_BAD_WRB_INDEX_ERROR",
191 "CXN_KILLED_OVER_RUN_RESIDUAL",
192 "CXN_KILLED_UNDER_RUN_RESIDUAL",
193 "CMD_KILLED_INVALID_STATSN_RCVD",
194 "CMD_KILLED_INVALID_R2T_RCVD",
195 "CMD_CXN_KILLED_LUN_INVALID",
196 "CMD_CXN_KILLED_ICD_INVALID",
197 "CMD_CXN_KILLED_ITT_INVALID",
198 "CMD_CXN_KILLED_SEQ_OUTOFORDER",
199 "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
200 "CXN_INVALIDATE_NOTIFY",
201 "CXN_INVALIDATE_INDEX_NOTIFY",
202 "CMD_INVALIDATED_NOTIFY",
203 "UNSOL_HDR_NOTIFY",
204 "UNSOL_DATA_NOTIFY",
205 "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
206 "DRIVERMSG_NOTIFY",
207 "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
208 "SOL_CMD_KILLED_DIF_ERR",
209 "CXN_KILLED_SYN_RCVD",
210 "CXN_KILLED_IMM_DATA_RCVD"
211};
212
6733b39a
JK		 213static int beiscsi_slave_configure(struct scsi_device *sdev)
214{
215 blk_queue_max_segment_size(sdev->request_queue, 65536);
216 return 0;
217}
218
4183122d
JK		 219static int beiscsi_eh_abort(struct scsi_cmnd *sc)
220{
221 struct iscsi_cls_session *cls_session;
222 struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
223 struct beiscsi_io_task *aborted_io_task;
224 struct iscsi_conn *conn;
225 struct beiscsi_conn *beiscsi_conn;
226 struct beiscsi_hba *phba;
227 struct iscsi_session *session;
228 struct invalidate_command_table *inv_tbl;
3cbb7a74 229 struct be_dma_mem nonemb_cmd;
4183122d 230 unsigned int cid, tag, num_invalidate;
1957aa7f 231 int rc;
4183122d
JK		 232
233 cls_session = starget_to_session(scsi_target(sc->device));
234 session = cls_session->dd_data;
235
659743b0 236 spin_lock_bh(&session->frwd_lock);
4183122d
JK		 237 if (!aborted_task || !aborted_task->sc) {
238 /* we raced */
659743b0 239 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 240 return SUCCESS;
241 }
242
243 aborted_io_task = aborted_task->dd_data;
244 if (!aborted_io_task->scsi_cmnd) {
245 /* raced or invalid command */
659743b0 246 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 247 return SUCCESS;
248 }
659743b0 249 spin_unlock_bh(&session->frwd_lock);
7626c06b
JK		 250 /* Invalidate WRB Posted for this Task */
251 AMAP_SET_BITS(struct amap_iscsi_wrb, invld,
252 aborted_io_task->pwrb_handle->pwrb,
253 1);
254
4183122d
JK		 255 conn = aborted_task->conn;
256 beiscsi_conn = conn->dd_data;
257 phba = beiscsi_conn->phba;
258
259 /* invalidate iocb */
260 cid = beiscsi_conn->beiscsi_conn_cid;
261 inv_tbl = phba->inv_tbl;
262 memset(inv_tbl, 0x0, sizeof(*inv_tbl));
263 inv_tbl->cid = cid;
264 inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
265 num_invalidate = 1;
3cbb7a74
JK		 266 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
267 sizeof(struct invalidate_commands_params_in),
268 &nonemb_cmd.dma);
269 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 270 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
271 "BM_%d : Failed to allocate memory for"
272 "mgmt_invalidate_icds\n");
3cbb7a74
JK		 273 return FAILED;
274 }
275 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
276
277 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
278 cid, &nonemb_cmd);
4183122d 279 if (!tag) {
99bc5d55
JSJ		 280 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
281 "BM_%d : mgmt_invalidate_icds could not be"
282 "submitted\n");
3cbb7a74
JK		 283 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
284 nonemb_cmd.va, nonemb_cmd.dma);
285
4183122d 286 return FAILED;
4183122d 287 }
e175defe 288
88840332 289 rc = beiscsi_mccq_compl_wait(phba, tag, NULL, &nonemb_cmd);
1957aa7f
JK		 290 if (rc != -EBUSY)
291 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
292 nonemb_cmd.va, nonemb_cmd.dma);
293
4183122d
JK		 294 return iscsi_eh_abort(sc);
295}
296
297static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
298{
299 struct iscsi_task *abrt_task;
300 struct beiscsi_io_task *abrt_io_task;
301 struct iscsi_conn *conn;
302 struct beiscsi_conn *beiscsi_conn;
303 struct beiscsi_hba *phba;
304 struct iscsi_session *session;
305 struct iscsi_cls_session *cls_session;
306 struct invalidate_command_table *inv_tbl;
3cbb7a74 307 struct be_dma_mem nonemb_cmd;
4183122d 308 unsigned int cid, tag, i, num_invalidate;
1957aa7f 309 int rc;
4183122d
JK		 310
311 /* invalidate iocbs */
312 cls_session = starget_to_session(scsi_target(sc->device));
313 session = cls_session->dd_data;
659743b0 314 spin_lock_bh(&session->frwd_lock);
db7f7709 315 if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
659743b0 316 spin_unlock_bh(&session->frwd_lock);
db7f7709
JK		 317 return FAILED;
318 }
4183122d
JK		 319 conn = session->leadconn;
320 beiscsi_conn = conn->dd_data;
321 phba = beiscsi_conn->phba;
322 cid = beiscsi_conn->beiscsi_conn_cid;
323 inv_tbl = phba->inv_tbl;
324 memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
325 num_invalidate = 0;
326 for (i = 0; i < conn->session->cmds_max; i++) {
327 abrt_task = conn->session->cmds[i];
328 abrt_io_task = abrt_task->dd_data;
329 if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
330 continue;
331
126e964a 332 if (sc->device->lun != abrt_task->sc->device->lun)
4183122d
JK		 333 continue;
334
7626c06b
JK		 335 /* Invalidate WRB Posted for this Task */
336 AMAP_SET_BITS(struct amap_iscsi_wrb, invld,
337 abrt_io_task->pwrb_handle->pwrb,
338 1);
339
4183122d
JK		 340 inv_tbl->cid = cid;
341 inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
342 num_invalidate++;
343 inv_tbl++;
344 }
659743b0 345 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 346 inv_tbl = phba->inv_tbl;
347
3cbb7a74
JK		 348 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
349 sizeof(struct invalidate_commands_params_in),
350 &nonemb_cmd.dma);
351 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 352 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
353 "BM_%d : Failed to allocate memory for"
354 "mgmt_invalidate_icds\n");
3cbb7a74
JK		 355 return FAILED;
356 }
357 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
358 memset(nonemb_cmd.va, 0, nonemb_cmd.size);
359 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
360 cid, &nonemb_cmd);
4183122d 361 if (!tag) {
99bc5d55
JSJ		 362 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
363 "BM_%d : mgmt_invalidate_icds could not be"
364 " submitted\n");
3cbb7a74
JK		 365 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
366 nonemb_cmd.va, nonemb_cmd.dma);
4183122d 367 return FAILED;
4183122d 368 }
e175defe 369
88840332 370 rc = beiscsi_mccq_compl_wait(phba, tag, NULL, &nonemb_cmd);
1957aa7f
JK		 371 if (rc != -EBUSY)
372 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
373 nonemb_cmd.va, nonemb_cmd.dma);
4183122d 374 return iscsi_eh_device_reset(sc);
4183122d
JK		 375}
376
c7acc5b8
JK		 377static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
378{
379 struct beiscsi_hba *phba = data;
f457a46f
MC		 380 struct mgmt_session_info *boot_sess = &phba->boot_sess;
381 struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
c7acc5b8
JK		 382 char *str = buf;
383 int rc;
384
385 switch (type) {
386 case ISCSI_BOOT_TGT_NAME:
387 rc = sprintf(buf, "%.*s\n",
f457a46f
MC		 388 (int)strlen(boot_sess->target_name),
389 (char *)&boot_sess->target_name);
c7acc5b8
JK		 390 break;
391 case ISCSI_BOOT_TGT_IP_ADDR:
f457a46f 392 if (boot_conn->dest_ipaddr.ip_type == 0x1)
c7acc5b8 393 rc = sprintf(buf, "%pI4\n",
0e43895e 394 (char *)&boot_conn->dest_ipaddr.addr);
c7acc5b8
JK		 395 else
396 rc = sprintf(str, "%pI6\n",
0e43895e 397 (char *)&boot_conn->dest_ipaddr.addr);
c7acc5b8
JK		 398 break;
399 case ISCSI_BOOT_TGT_PORT:
f457a46f 400 rc = sprintf(str, "%d\n", boot_conn->dest_port);
c7acc5b8
JK		 401 break;
402
403 case ISCSI_BOOT_TGT_CHAP_NAME:
404 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 405 boot_conn->negotiated_login_options.auth_data.chap.
406 target_chap_name_length,
407 (char *)&boot_conn->negotiated_login_options.
408 auth_data.chap.target_chap_name);
c7acc5b8
JK		 409 break;
410 case ISCSI_BOOT_TGT_CHAP_SECRET:
411 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 412 boot_conn->negotiated_login_options.auth_data.chap.
413 target_secret_length,
414 (char *)&boot_conn->negotiated_login_options.
415 auth_data.chap.target_secret);
c7acc5b8
JK		 416 break;
417 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
418 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 419 boot_conn->negotiated_login_options.auth_data.chap.
420 intr_chap_name_length,
421 (char *)&boot_conn->negotiated_login_options.
422 auth_data.chap.intr_chap_name);
c7acc5b8
JK		 423 break;
424 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
f457a46f
MC		 425 rc = sprintf(str, "%.*s\n",
426 boot_conn->negotiated_login_options.auth_data.chap.
427 intr_secret_length,
428 (char *)&boot_conn->negotiated_login_options.
429 auth_data.chap.intr_secret);
c7acc5b8
JK		 430 break;
431 case ISCSI_BOOT_TGT_FLAGS:
f457a46f 432 rc = sprintf(str, "2\n");
c7acc5b8
JK		 433 break;
434 case ISCSI_BOOT_TGT_NIC_ASSOC:
f457a46f 435 rc = sprintf(str, "0\n");
c7acc5b8
JK		 436 break;
437 default:
438 rc = -ENOSYS;
439 break;
440 }
441 return rc;
442}
443
444static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
445{
446 struct beiscsi_hba *phba = data;
447 char *str = buf;
448 int rc;
449
450 switch (type) {
451 case ISCSI_BOOT_INI_INITIATOR_NAME:
452 rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
453 break;
454 default:
455 rc = -ENOSYS;
456 break;
457 }
458 return rc;
459}
460
461static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
462{
463 struct beiscsi_hba *phba = data;
464 char *str = buf;
465 int rc;
466
467 switch (type) {
468 case ISCSI_BOOT_ETH_FLAGS:
f457a46f 469 rc = sprintf(str, "2\n");
c7acc5b8
JK		 470 break;
471 case ISCSI_BOOT_ETH_INDEX:
f457a46f 472 rc = sprintf(str, "0\n");
c7acc5b8
JK		 473 break;
474 case ISCSI_BOOT_ETH_MAC:
0e43895e
MC		 475 rc = beiscsi_get_macaddr(str, phba);
476 break;
c7acc5b8
JK		 477 default:
478 rc = -ENOSYS;
479 break;
480 }
481 return rc;
482}
483
484
587a1f16 485static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
c7acc5b8 486{
587a1f16 487 umode_t rc;
c7acc5b8
JK		 488
489 switch (type) {
490 case ISCSI_BOOT_TGT_NAME:
491 case ISCSI_BOOT_TGT_IP_ADDR:
492 case ISCSI_BOOT_TGT_PORT:
493 case ISCSI_BOOT_TGT_CHAP_NAME:
494 case ISCSI_BOOT_TGT_CHAP_SECRET:
495 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
496 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
497 case ISCSI_BOOT_TGT_NIC_ASSOC:
498 case ISCSI_BOOT_TGT_FLAGS:
499 rc = S_IRUGO;
500 break;
501 default:
502 rc = 0;
503 break;
504 }
505 return rc;
506}
507
587a1f16 508static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
c7acc5b8 509{
587a1f16 510 umode_t rc;
c7acc5b8
JK		 511
512 switch (type) {
513 case ISCSI_BOOT_INI_INITIATOR_NAME:
514 rc = S_IRUGO;
515 break;
516 default:
517 rc = 0;
518 break;
519 }
520 return rc;
521}
522
523
587a1f16 524static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
c7acc5b8 525{
587a1f16 526 umode_t rc;
c7acc5b8
JK		 527
528 switch (type) {
529 case ISCSI_BOOT_ETH_FLAGS:
530 case ISCSI_BOOT_ETH_MAC:
531 case ISCSI_BOOT_ETH_INDEX:
532 rc = S_IRUGO;
533 break;
534 default:
535 rc = 0;
536 break;
537 }
538 return rc;
539}
540
bfead3b2 541/*------------------- PCI Driver operations and data ----------------- */
9baa3c34 542static const struct pci_device_id beiscsi_pci_id_table[] = {
bfead3b2 543 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
f98c96b0 544 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
bfead3b2
JK		 545 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
546 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
547 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
139a1b1e 548 { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) },
bfead3b2
JK		 549 { 0 }
550};
551MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
552
99bc5d55 553
6733b39a
JK		 554static struct scsi_host_template beiscsi_sht = {
555 .module = THIS_MODULE,
c4f39bda 556 .name = "Emulex 10Gbe open-iscsi Initiator Driver",
6733b39a
JK		 557 .proc_name = DRV_NAME,
558 .queuecommand = iscsi_queuecommand,
db5ed4df 559 .change_queue_depth = scsi_change_queue_depth,
6733b39a
JK		 560 .slave_configure = beiscsi_slave_configure,
561 .target_alloc = iscsi_target_alloc,
4183122d
JK		 562 .eh_abort_handler = beiscsi_eh_abort,
563 .eh_device_reset_handler = beiscsi_eh_device_reset,
309ce156 564 .eh_target_reset_handler = iscsi_eh_session_reset,
99bc5d55 565 .shost_attrs = beiscsi_attrs,
6733b39a
JK		 566 .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
567 .can_queue = BE2_IO_DEPTH,
568 .this_id = -1,
569 .max_sectors = BEISCSI_MAX_SECTORS,
570 .cmd_per_lun = BEISCSI_CMD_PER_LUN,
571 .use_clustering = ENABLE_CLUSTERING,
ffce3e2e 572 .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
c40ecc12 573 .track_queue_depth = 1,
6733b39a 574};
6733b39a 575
bfead3b2 576static struct scsi_transport_template *beiscsi_scsi_transport;
6733b39a
JK		 577
578static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
579{
580 struct beiscsi_hba *phba;
581 struct Scsi_Host *shost;
582
583 shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
584 if (!shost) {
99bc5d55
JSJ		 585 dev_err(&pcidev->dev,
586 "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
6733b39a
JK		 587 return NULL;
588 }
6733b39a
JK		 589 shost->max_id = BE2_MAX_SESSIONS;
590 shost->max_channel = 0;
591 shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
592 shost->max_lun = BEISCSI_NUM_MAX_LUN;
593 shost->transportt = beiscsi_scsi_transport;
6733b39a
JK		 594 phba = iscsi_host_priv(shost);
595 memset(phba, 0, sizeof(*phba));
596 phba->shost = shost;
597 phba->pcidev = pci_dev_get(pcidev);
2807afb7 598 pci_set_drvdata(pcidev, phba);
0e43895e 599 phba->interface_handle = 0xFFFFFFFF;
6733b39a 600
6733b39a 601 return phba;
6733b39a
JK		 602}
603
604static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
605{
606 if (phba->csr_va) {
607 iounmap(phba->csr_va);
608 phba->csr_va = NULL;
609 }
610 if (phba->db_va) {
611 iounmap(phba->db_va);
612 phba->db_va = NULL;
613 }
614 if (phba->pci_va) {
615 iounmap(phba->pci_va);
616 phba->pci_va = NULL;
617 }
618}
619
620static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
621 struct pci_dev *pcidev)
622{
623 u8 __iomem *addr;
f98c96b0 624 int pcicfg_reg;
6733b39a
JK		 625
626 addr = ioremap_nocache(pci_resource_start(pcidev, 2),
627 pci_resource_len(pcidev, 2));
628 if (addr == NULL)
629 return -ENOMEM;
630 phba->ctrl.csr = addr;
631 phba->csr_va = addr;
632 phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
633
634 addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
635 if (addr == NULL)
636 goto pci_map_err;
637 phba->ctrl.db = addr;
638 phba->db_va = addr;
639 phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
640
f98c96b0
JK		 641 if (phba->generation == BE_GEN2)
642 pcicfg_reg = 1;
643 else
644 pcicfg_reg = 0;
645
646 addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
647 pci_resource_len(pcidev, pcicfg_reg));
648
6733b39a
JK		 649 if (addr == NULL)
650 goto pci_map_err;
651 phba->ctrl.pcicfg = addr;
652 phba->pci_va = addr;
f98c96b0 653 phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
6733b39a
JK		 654 return 0;
655
656pci_map_err:
657 beiscsi_unmap_pci_function(phba);
658 return -ENOMEM;
659}
660
661static int beiscsi_enable_pci(struct pci_dev *pcidev)
662{
663 int ret;
664
665 ret = pci_enable_device(pcidev);
666 if (ret) {
99bc5d55
JSJ		 667 dev_err(&pcidev->dev,
668 "beiscsi_enable_pci - enable device failed\n");
6733b39a
JK		 669 return ret;
670 }
671
e307f3ac
JSJ		 672 ret = pci_request_regions(pcidev, DRV_NAME);
673 if (ret) {
674 dev_err(&pcidev->dev,
675 "beiscsi_enable_pci - request region failed\n");
676 goto pci_dev_disable;
677 }
678
bfead3b2 679 pci_set_master(pcidev);
6c57625b
JK		 680 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(64));
681 if (ret) {
682 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
683 if (ret) {
684 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
e307f3ac 685 goto pci_region_release;
6c57625b
JK		 686 } else {
687 ret = pci_set_consistent_dma_mask(pcidev,
688 DMA_BIT_MASK(32));
689 }
690 } else {
691 ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
6733b39a
JK		 692 if (ret) {
693 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
e307f3ac 694 goto pci_region_release;
6733b39a
JK		 695 }
696 }
697 return 0;
e307f3ac
JSJ		 698
699pci_region_release:
700 pci_release_regions(pcidev);
701pci_dev_disable:
702 pci_disable_device(pcidev);
703
704 return ret;
6733b39a
JK		 705}
706
707static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
708{
709 struct be_ctrl_info *ctrl = &phba->ctrl;
710 struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
711 struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
712 int status = 0;
713
714 ctrl->pdev = pdev;
715 status = beiscsi_map_pci_bars(phba, pdev);
716 if (status)
717 return status;
6733b39a
JK		 718 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
719 mbox_mem_alloc->va = pci_alloc_consistent(pdev,
720 mbox_mem_alloc->size,
721 &mbox_mem_alloc->dma);
722 if (!mbox_mem_alloc->va) {
723 beiscsi_unmap_pci_function(phba);
a49e06d5 724 return -ENOMEM;
6733b39a
JK		 725 }
726
727 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
728 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
729 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
730 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
c03a50f7 731 mutex_init(&ctrl->mbox_lock);
bfead3b2 732 spin_lock_init(&phba->ctrl.mcc_lock);
bfead3b2 733
6733b39a
JK		 734 return status;
735}
736
843ae752
JK		 737/**
738 * beiscsi_get_params()- Set the config paramters
739 * @phba: ptr device priv structure
740 **/
6733b39a
JK		 741static void beiscsi_get_params(struct beiscsi_hba *phba)
742{
843ae752
JK		 743 uint32_t total_cid_count = 0;
744 uint32_t total_icd_count = 0;
745 uint8_t ulp_num = 0;
746
747 total_cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) +
748 BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1);
749
cf987b79
JK		 750 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
751 uint32_t align_mask = 0;
752 uint32_t icd_post_per_page = 0;
753 uint32_t icd_count_unavailable = 0;
754 uint32_t icd_start = 0, icd_count = 0;
755 uint32_t icd_start_align = 0, icd_count_align = 0;
756
843ae752 757 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
cf987b79
JK		 758 icd_start = phba->fw_config.iscsi_icd_start[ulp_num];
759 icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
760
761 /* Get ICD count that can be posted on each page */
762 icd_post_per_page = (PAGE_SIZE / (BE2_SGE *
763 sizeof(struct iscsi_sge)));
764 align_mask = (icd_post_per_page - 1);
765
766 /* Check if icd_start is aligned ICD per page posting */
767 if (icd_start % icd_post_per_page) {
768 icd_start_align = ((icd_start +
769 icd_post_per_page) &
770 ~(align_mask));
771 phba->fw_config.
772 iscsi_icd_start[ulp_num] =
773 icd_start_align;
774 }
775
776 icd_count_align = (icd_count & ~align_mask);
777
778 /* ICD discarded in the process of alignment */
779 if (icd_start_align)
780 icd_count_unavailable = ((icd_start_align -
781 icd_start) +
782 (icd_count -
783 icd_count_align));
784
785 /* Updated ICD count available */
786 phba->fw_config.iscsi_icd_count[ulp_num] = (icd_count -
787 icd_count_unavailable);
788
789 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
790 "BM_%d : Aligned ICD values\n"
791 "\t ICD Start : %d\n"
792 "\t ICD Count : %d\n"
793 "\t ICD Discarded : %d\n",
794 phba->fw_config.
795 iscsi_icd_start[ulp_num],
796 phba->fw_config.
797 iscsi_icd_count[ulp_num],
798 icd_count_unavailable);
843ae752
JK		 799 break;
800 }
cf987b79 801 }
843ae752 802
cf987b79 803 total_icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
843ae752
JK		 804 phba->params.ios_per_ctrl = (total_icd_count -
805 (total_cid_count +
806 BE2_TMFS + BE2_NOPOUT_REQ));
807 phba->params.cxns_per_ctrl = total_cid_count;
808 phba->params.asyncpdus_per_ctrl = total_cid_count;
809 phba->params.icds_per_ctrl = total_icd_count;
6733b39a
JK		 810 phba->params.num_sge_per_io = BE2_SGE;
811 phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
812 phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
813 phba->params.eq_timer = 64;
843ae752
JK		 814 phba->params.num_eq_entries = 1024;
815 phba->params.num_cq_entries = 1024;
6733b39a
JK		 816 phba->params.wrbs_per_cxn = 256;
817}
818
819static void hwi_ring_eq_db(struct beiscsi_hba *phba,
820 unsigned int id, unsigned int clr_interrupt,
821 unsigned int num_processed,
822 unsigned char rearm, unsigned char event)
823{
824 u32 val = 0;
e08b3c8b 825
6733b39a
JK		 826 if (rearm)
827 val |= 1 << DB_EQ_REARM_SHIFT;
828 if (clr_interrupt)
829 val |= 1 << DB_EQ_CLR_SHIFT;
830 if (event)
831 val |= 1 << DB_EQ_EVNT_SHIFT;
e08b3c8b 832
6733b39a 833 val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
e08b3c8b
JK		 834 /* Setting lower order EQ_ID Bits */
835 val |= (id & DB_EQ_RING_ID_LOW_MASK);
836
837 /* Setting Higher order EQ_ID Bits */
838 val |= (((id >> DB_EQ_HIGH_FEILD_SHIFT) &
839 DB_EQ_RING_ID_HIGH_MASK)
840 << DB_EQ_HIGH_SET_SHIFT);
841
6733b39a
JK		 842 iowrite32(val, phba->db_va + DB_EQ_OFFSET);
843}
844
bfead3b2
JK		 845/**
846 * be_isr_mcc - The isr routine of the driver.
847 * @irq: Not used
848 * @dev_id: Pointer to host adapter structure
849 */
850static irqreturn_t be_isr_mcc(int irq, void *dev_id)
851{
852 struct beiscsi_hba *phba;
853 struct be_eq_entry *eqe = NULL;
854 struct be_queue_info *eq;
855 struct be_queue_info *mcc;
856 unsigned int num_eq_processed;
857 struct be_eq_obj *pbe_eq;
858 unsigned long flags;
859
860 pbe_eq = dev_id;
861 eq = &pbe_eq->q;
862 phba = pbe_eq->phba;
863 mcc = &phba->ctrl.mcc_obj.cq;
864 eqe = queue_tail_node(eq);
bfead3b2
JK		 865
866 num_eq_processed = 0;
867
868 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
869 & EQE_VALID_MASK) {
870 if (((eqe->dw[offsetof(struct amap_eq_entry,
871 resource_id) / 32] &
872 EQE_RESID_MASK) >> 16) == mcc->id) {
873 spin_lock_irqsave(&phba->isr_lock, flags);
72fb46a9 874 pbe_eq->todo_mcc_cq = true;
bfead3b2
JK		 875 spin_unlock_irqrestore(&phba->isr_lock, flags);
876 }
877 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
878 queue_tail_inc(eq);
879 eqe = queue_tail_node(eq);
880 num_eq_processed++;
881 }
72fb46a9
JSJ		 882 if (pbe_eq->todo_mcc_cq)
883 queue_work(phba->wq, &pbe_eq->work_cqs);
bfead3b2
JK		 884 if (num_eq_processed)
885 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
886
887 return IRQ_HANDLED;
888}
889
890/**
891 * be_isr_msix - The isr routine of the driver.
892 * @irq: Not used
893 * @dev_id: Pointer to host adapter structure
894 */
895static irqreturn_t be_isr_msix(int irq, void *dev_id)
896{
897 struct beiscsi_hba *phba;
bfead3b2 898 struct be_queue_info *eq;
bfead3b2 899 struct be_eq_obj *pbe_eq;
bfead3b2
JK		 900
901 pbe_eq = dev_id;
902 eq = &pbe_eq->q;
bfead3b2
JK		 903
904 phba = pbe_eq->phba;
bfead3b2 905
1094cf68
JB		 906 /* disable interrupt till iopoll completes */
907 hwi_ring_eq_db(phba, eq->id, 1, 0, 0, 1);
908 irq_poll_sched(&pbe_eq->iopoll);
72fb46a9
JSJ		 909
910 return IRQ_HANDLED;
bfead3b2
JK		 911}
912
6733b39a
JK		 913/**
914 * be_isr - The isr routine of the driver.
915 * @irq: Not used
916 * @dev_id: Pointer to host adapter structure
917 */
918static irqreturn_t be_isr(int irq, void *dev_id)
919{
920 struct beiscsi_hba *phba;
921 struct hwi_controller *phwi_ctrlr;
922 struct hwi_context_memory *phwi_context;
923 struct be_eq_entry *eqe = NULL;
924 struct be_queue_info *eq;
bfead3b2 925 struct be_queue_info *mcc;
6733b39a 926 unsigned long flags, index;
bfead3b2 927 unsigned int num_mcceq_processed, num_ioeq_processed;
6733b39a 928 struct be_ctrl_info *ctrl;
bfead3b2 929 struct be_eq_obj *pbe_eq;
6733b39a
JK		 930 int isr;
931
932 phba = dev_id;
6eab04a8 933 ctrl = &phba->ctrl;
bfead3b2
JK		 934 isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
935 (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
936 if (!isr)
937 return IRQ_NONE;
6733b39a
JK		 938
939 phwi_ctrlr = phba->phwi_ctrlr;
940 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 941 pbe_eq = &phwi_context->be_eq[0];
942
943 eq = &phwi_context->be_eq[0].q;
944 mcc = &phba->ctrl.mcc_obj.cq;
6733b39a
JK		 945 index = 0;
946 eqe = queue_tail_node(eq);
6733b39a 947
bfead3b2
JK		 948 num_ioeq_processed = 0;
949 num_mcceq_processed = 0;
89f8b33c
JA		 950 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
951 & EQE_VALID_MASK) {
952 if (((eqe->dw[offsetof(struct amap_eq_entry,
953 resource_id) / 32] &
954 EQE_RESID_MASK) >> 16) == mcc->id) {
955 spin_lock_irqsave(&phba->isr_lock, flags);
956 pbe_eq->todo_mcc_cq = true;
957 spin_unlock_irqrestore(&phba->isr_lock, flags);
958 num_mcceq_processed++;
959 } else {
ea51190c 960 irq_poll_sched(&pbe_eq->iopoll);
bfead3b2 961 num_ioeq_processed++;
6733b39a 962 }
89f8b33c
JA		 963 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
964 queue_tail_inc(eq);
965 eqe = queue_tail_node(eq);
966 }
967 if (num_ioeq_processed || num_mcceq_processed) {
968 if (pbe_eq->todo_mcc_cq)
72fb46a9 969 queue_work(phba->wq, &pbe_eq->work_cqs);
6733b39a 970
89f8b33c 971 if ((num_mcceq_processed) && (!num_ioeq_processed))
bfead3b2 972 hwi_ring_eq_db(phba, eq->id, 0,
89f8b33c
JA		 973 (num_ioeq_processed +
974 num_mcceq_processed) , 1, 1);
975 else
976 hwi_ring_eq_db(phba, eq->id, 0,
977 (num_ioeq_processed +
978 num_mcceq_processed), 0, 1);
979
980 return IRQ_HANDLED;
981 } else
982 return IRQ_NONE;
6733b39a
JK		 983}
984
1094cf68 985
6733b39a
JK		 986static int beiscsi_init_irqs(struct beiscsi_hba *phba)
987{
988 struct pci_dev *pcidev = phba->pcidev;
bfead3b2
JK		 989 struct hwi_controller *phwi_ctrlr;
990 struct hwi_context_memory *phwi_context;
4f5af07e 991 int ret, msix_vec, i, j;
6733b39a 992
bfead3b2
JK		 993 phwi_ctrlr = phba->phwi_ctrlr;
994 phwi_context = phwi_ctrlr->phwi_ctxt;
995
996 if (phba->msix_enabled) {
997 for (i = 0; i < phba->num_cpus; i++) {
8fcfb210
JK		 998 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
999 GFP_KERNEL);
1000 if (!phba->msi_name[i]) {
1001 ret = -ENOMEM;
1002 goto free_msix_irqs;
1003 }
1004
1005 sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
1006 phba->shost->host_no, i);
bfead3b2 1007 msix_vec = phba->msix_entries[i].vector;
8fcfb210
JK		 1008 ret = request_irq(msix_vec, be_isr_msix, 0,
1009 phba->msi_name[i],
bfead3b2 1010 &phwi_context->be_eq[i]);
4f5af07e 1011 if (ret) {
99bc5d55
JSJ		 1012 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1013 "BM_%d : beiscsi_init_irqs-Failed to"
1014 "register msix for i = %d\n",
1015 i);
8fcfb210 1016 kfree(phba->msi_name[i]);
4f5af07e
JK		 1017 goto free_msix_irqs;
1018 }
bfead3b2 1019 }
8fcfb210
JK		 1020 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
1021 if (!phba->msi_name[i]) {
1022 ret = -ENOMEM;
1023 goto free_msix_irqs;
1024 }
1025 sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
1026 phba->shost->host_no);
bfead3b2 1027 msix_vec = phba->msix_entries[i].vector;
8fcfb210 1028 ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
bfead3b2 1029 &phwi_context->be_eq[i]);
4f5af07e 1030 if (ret) {
99bc5d55
JSJ		 1031 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
1032 "BM_%d : beiscsi_init_irqs-"
1033 "Failed to register beiscsi_msix_mcc\n");
8fcfb210 1034 kfree(phba->msi_name[i]);
4f5af07e
JK		 1035 goto free_msix_irqs;
1036 }
1037
bfead3b2
JK		 1038 } else {
1039 ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
1040 "beiscsi", phba);
1041 if (ret) {
99bc5d55
JSJ		 1042 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1043 "BM_%d : beiscsi_init_irqs-"
1044 "Failed to register irq\\n");
bfead3b2
JK		 1045 return ret;
1046 }
6733b39a
JK		 1047 }
1048 return 0;
4f5af07e 1049free_msix_irqs:
8fcfb210
JK		 1050 for (j = i - 1; j >= 0; j--) {
1051 kfree(phba->msi_name[j]);
1052 msix_vec = phba->msix_entries[j].vector;
4f5af07e 1053 free_irq(msix_vec, &phwi_context->be_eq[j]);
8fcfb210 1054 }
4f5af07e 1055 return ret;
6733b39a
JK		 1056}
1057
e08b3c8b 1058void hwi_ring_cq_db(struct beiscsi_hba *phba,
6733b39a 1059 unsigned int id, unsigned int num_processed,
1094cf68 1060 unsigned char rearm)
6733b39a
JK		 1061{
1062 u32 val = 0;
e08b3c8b 1063
6733b39a
JK		 1064 if (rearm)
1065 val |= 1 << DB_CQ_REARM_SHIFT;
e08b3c8b 1066
6733b39a 1067 val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
e08b3c8b
JK		 1068
1069 /* Setting lower order CQ_ID Bits */
1070 val |= (id & DB_CQ_RING_ID_LOW_MASK);
1071
1072 /* Setting Higher order CQ_ID Bits */
1073 val |= (((id >> DB_CQ_HIGH_FEILD_SHIFT) &
1074 DB_CQ_RING_ID_HIGH_MASK)
1075 << DB_CQ_HIGH_SET_SHIFT);
1076
6733b39a
JK		 1077 iowrite32(val, phba->db_va + DB_CQ_OFFSET);
1078}
1079
6733b39a
JK		 1080static unsigned int
1081beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
1082 struct beiscsi_hba *phba,
6733b39a
JK		 1083 struct pdu_base *ppdu,
1084 unsigned long pdu_len,
1085 void *pbuffer, unsigned long buf_len)
1086{
1087 struct iscsi_conn *conn = beiscsi_conn->conn;
1088 struct iscsi_session *session = conn->session;
bfead3b2
JK		 1089 struct iscsi_task *task;
1090 struct beiscsi_io_task *io_task;
1091 struct iscsi_hdr *login_hdr;
6733b39a
JK		 1092
1093 switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
1094 PDUBASE_OPCODE_MASK) {
1095 case ISCSI_OP_NOOP_IN:
1096 pbuffer = NULL;
1097 buf_len = 0;
1098 break;
1099 case ISCSI_OP_ASYNC_EVENT:
1100 break;
1101 case ISCSI_OP_REJECT:
1102 WARN_ON(!pbuffer);
1103 WARN_ON(!(buf_len == 48));
99bc5d55
JSJ		 1104 beiscsi_log(phba, KERN_ERR,
1105 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1106 "BM_%d : In ISCSI_OP_REJECT\n");
6733b39a
JK		 1107 break;
1108 case ISCSI_OP_LOGIN_RSP:
7bd6e25c 1109 case ISCSI_OP_TEXT_RSP:
bfead3b2
JK		 1110 task = conn->login_task;
1111 io_task = task->dd_data;
1112 login_hdr = (struct iscsi_hdr *)ppdu;
1113 login_hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1114 break;
1115 default:
99bc5d55
JSJ		 1116 beiscsi_log(phba, KERN_WARNING,
1117 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1118 "BM_%d : Unrecognized opcode 0x%x in async msg\n",
1119 (ppdu->
6733b39a 1120 dw[offsetof(struct amap_pdu_base, opcode) / 32]
99bc5d55 1121 & PDUBASE_OPCODE_MASK));
6733b39a
JK		 1122 return 1;
1123 }
1124
659743b0 1125 spin_lock_bh(&session->back_lock);
6733b39a 1126 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
659743b0 1127 spin_unlock_bh(&session->back_lock);
6733b39a
JK		 1128 return 0;
1129}
1130
1131static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
1132{
1133 struct sgl_handle *psgl_handle;
1134
10139fe0 1135 spin_lock_bh(&phba->io_sgl_lock);
6733b39a 1136 if (phba->io_sgl_hndl_avbl) {
99bc5d55
JSJ		 1137 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
1138 "BM_%d : In alloc_io_sgl_handle,"
1139 " io_sgl_alloc_index=%d\n",
1140 phba->io_sgl_alloc_index);
1141
6733b39a
JK		 1142 psgl_handle = phba->io_sgl_hndl_base[phba->
1143 io_sgl_alloc_index];
1144 phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
1145 phba->io_sgl_hndl_avbl--;
bfead3b2
JK		 1146 if (phba->io_sgl_alloc_index == (phba->params.
1147 ios_per_ctrl - 1))
6733b39a
JK		 1148 phba->io_sgl_alloc_index = 0;
1149 else
1150 phba->io_sgl_alloc_index++;
1151 } else
1152 psgl_handle = NULL;
10139fe0 1153 spin_unlock_bh(&phba->io_sgl_lock);
6733b39a
JK		 1154 return psgl_handle;
1155}
1156
1157static void
1158free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
1159{
10139fe0 1160 spin_lock_bh(&phba->io_sgl_lock);
99bc5d55
JSJ		 1161 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
1162 "BM_%d : In free_,io_sgl_free_index=%d\n",
1163 phba->io_sgl_free_index);
1164
6733b39a
JK		 1165 if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
1166 /*
1167 * this can happen if clean_task is called on a task that
1168 * failed in xmit_task or alloc_pdu.
1169 */
99bc5d55
JSJ		 1170 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
1171 "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
1172 "value there=%p\n", phba->io_sgl_free_index,
1173 phba->io_sgl_hndl_base
1174 [phba->io_sgl_free_index]);
10139fe0 1175 spin_unlock_bh(&phba->io_sgl_lock);
6733b39a
JK		 1176 return;
1177 }
1178 phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
1179 phba->io_sgl_hndl_avbl++;
1180 if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
1181 phba->io_sgl_free_index = 0;
1182 else
1183 phba->io_sgl_free_index++;
10139fe0 1184 spin_unlock_bh(&phba->io_sgl_lock);
6733b39a
JK		 1185}
1186
cb564c6b
JB		 1187static inline struct wrb_handle *
1188beiscsi_get_wrb_handle(struct hwi_wrb_context *pwrb_context,
1189 unsigned int wrbs_per_cxn)
1190{
1191 struct wrb_handle *pwrb_handle;
1192
f64d92e6 1193 spin_lock_bh(&pwrb_context->wrb_lock);
cb564c6b
JB		 1194 pwrb_handle = pwrb_context->pwrb_handle_base[pwrb_context->alloc_index];
1195 pwrb_context->wrb_handles_available--;
1196 if (pwrb_context->alloc_index == (wrbs_per_cxn - 1))
1197 pwrb_context->alloc_index = 0;
1198 else
1199 pwrb_context->alloc_index++;
f64d92e6 1200 spin_unlock_bh(&pwrb_context->wrb_lock);
cb564c6b
JB		 1201
1202 return pwrb_handle;
1203}
1204
6733b39a
JK		 1205/**
1206 * alloc_wrb_handle - To allocate a wrb handle
1207 * @phba: The hba pointer
1208 * @cid: The cid to use for allocation
340c99e9 1209 * @pwrb_context: ptr to ptr to wrb context
6733b39a
JK		 1210 *
1211 * This happens under session_lock until submission to chip
1212 */
340c99e9 1213struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid,
cb564c6b 1214 struct hwi_wrb_context **pcontext)
6733b39a
JK		 1215{
1216 struct hwi_wrb_context *pwrb_context;
1217 struct hwi_controller *phwi_ctrlr;
a7909b39 1218 uint16_t cri_index = BE_GET_CRI_FROM_CID(cid);
6733b39a
JK		 1219
1220 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 1221 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
cb564c6b
JB		 1222 /* return the context address */
1223 *pcontext = pwrb_context;
1224 return beiscsi_get_wrb_handle(pwrb_context, phba->params.wrbs_per_cxn);
1225}
340c99e9 1226
cb564c6b
JB		 1227static inline void
1228beiscsi_put_wrb_handle(struct hwi_wrb_context *pwrb_context,
1229 struct wrb_handle *pwrb_handle,
1230 unsigned int wrbs_per_cxn)
1231{
f64d92e6 1232 spin_lock_bh(&pwrb_context->wrb_lock);
cb564c6b
JB		 1233 pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
1234 pwrb_context->wrb_handles_available++;
1235 if (pwrb_context->free_index == (wrbs_per_cxn - 1))
1236 pwrb_context->free_index = 0;
1237 else
1238 pwrb_context->free_index++;
f64d92e6 1239 spin_unlock_bh(&pwrb_context->wrb_lock);
6733b39a
JK		 1240}
1241
1242/**
1243 * free_wrb_handle - To free the wrb handle back to pool
1244 * @phba: The hba pointer
1245 * @pwrb_context: The context to free from
1246 * @pwrb_handle: The wrb_handle to free
1247 *
1248 * This happens under session_lock until submission to chip
1249 */
1250static void
1251free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
1252 struct wrb_handle *pwrb_handle)
1253{
cb564c6b
JB		 1254 beiscsi_put_wrb_handle(pwrb_context,
1255 pwrb_handle,
1256 phba->params.wrbs_per_cxn);
99bc5d55
JSJ		 1257 beiscsi_log(phba, KERN_INFO,
1258 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1259 "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
1260 "wrb_handles_available=%d\n",
1261 pwrb_handle, pwrb_context->free_index,
1262 pwrb_context->wrb_handles_available);
6733b39a
JK		 1263}
1264
1265static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
1266{
1267 struct sgl_handle *psgl_handle;
1268
10139fe0 1269 spin_lock_bh(&phba->mgmt_sgl_lock);
6733b39a
JK		 1270 if (phba->eh_sgl_hndl_avbl) {
1271 psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
1272 phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
99bc5d55
JSJ		 1273 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
1274 "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
1275 phba->eh_sgl_alloc_index,
1276 phba->eh_sgl_alloc_index);
1277
6733b39a
JK		 1278 phba->eh_sgl_hndl_avbl--;
1279 if (phba->eh_sgl_alloc_index ==
1280 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
1281 1))
1282 phba->eh_sgl_alloc_index = 0;
1283 else
1284 phba->eh_sgl_alloc_index++;
1285 } else
1286 psgl_handle = NULL;
10139fe0 1287 spin_unlock_bh(&phba->mgmt_sgl_lock);
6733b39a
JK		 1288 return psgl_handle;
1289}
1290
1291void
1292free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
1293{
10139fe0 1294 spin_lock_bh(&phba->mgmt_sgl_lock);
99bc5d55
JSJ		 1295 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
1296 "BM_%d : In free_mgmt_sgl_handle,"
1297 "eh_sgl_free_index=%d\n",
1298 phba->eh_sgl_free_index);
1299
6733b39a
JK		 1300 if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
1301 /*
1302 * this can happen if clean_task is called on a task that
1303 * failed in xmit_task or alloc_pdu.
1304 */
99bc5d55
JSJ		 1305 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
1306 "BM_%d : Double Free in eh SGL ,"
1307 "eh_sgl_free_index=%d\n",
1308 phba->eh_sgl_free_index);
10139fe0 1309 spin_unlock_bh(&phba->mgmt_sgl_lock);
6733b39a
JK		 1310 return;
1311 }
1312 phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
1313 phba->eh_sgl_hndl_avbl++;
1314 if (phba->eh_sgl_free_index ==
1315 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
1316 phba->eh_sgl_free_index = 0;
1317 else
1318 phba->eh_sgl_free_index++;
10139fe0 1319 spin_unlock_bh(&phba->mgmt_sgl_lock);
6733b39a
JK		 1320}
1321
1322static void
1323be_complete_io(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1324 struct iscsi_task *task,
1325 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1326{
1327 struct beiscsi_io_task *io_task = task->dd_data;
1328 struct be_status_bhs *sts_bhs =
1329 (struct be_status_bhs *)io_task->cmd_bhs;
1330 struct iscsi_conn *conn = beiscsi_conn->conn;
6733b39a
JK		 1331 unsigned char *sense;
1332 u32 resid = 0, exp_cmdsn, max_cmdsn;
1333 u8 rsp, status, flags;
1334
73133261
JSJ		 1335 exp_cmdsn = csol_cqe->exp_cmdsn;
1336 max_cmdsn = (csol_cqe->exp_cmdsn +
1337 csol_cqe->cmd_wnd - 1);
1338 rsp = csol_cqe->i_resp;
1339 status = csol_cqe->i_sts;
1340 flags = csol_cqe->i_flags;
1341 resid = csol_cqe->res_cnt;
1342
bd535451 1343 if (!task->sc) {
da334977 1344 if (io_task->scsi_cmnd) {
bd535451 1345 scsi_dma_unmap(io_task->scsi_cmnd);
da334977
JK		 1346 io_task->scsi_cmnd = NULL;
1347 }
6733b39a 1348
bd535451
JK		 1349 return;
1350 }
6733b39a
JK		 1351 task->sc->result = (DID_OK << 16) | status;
1352 if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
1353 task->sc->result = DID_ERROR << 16;
1354 goto unmap;
1355 }
1356
1357 /* bidi not initially supported */
1358 if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
6733b39a
JK		 1359 if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
1360 task->sc->result = DID_ERROR << 16;
1361
1362 if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
1363 scsi_set_resid(task->sc, resid);
1364 if (!status && (scsi_bufflen(task->sc) - resid <
1365 task->sc->underflow))
1366 task->sc->result = DID_ERROR << 16;
1367 }
1368 }
1369
1370 if (status == SAM_STAT_CHECK_CONDITION) {
4053a4be 1371 u16 sense_len;
bfead3b2 1372 unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
4053a4be 1373
6733b39a 1374 sense = sts_bhs->sense_info + sizeof(unsigned short);
4053a4be 1375 sense_len = be16_to_cpu(*slen);
6733b39a
JK		 1376 memcpy(task->sc->sense_buffer, sense,
1377 min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
1378 }
756d29c8 1379
73133261
JSJ		 1380 if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ)
1381 conn->rxdata_octets += resid;
6733b39a 1382unmap:
eb1c4692
JSJ		 1383 if (io_task->scsi_cmnd) {
1384 scsi_dma_unmap(io_task->scsi_cmnd);
1385 io_task->scsi_cmnd = NULL;
1386 }
6733b39a
JK		 1387 iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
1388}
1389
1390static void
1391be_complete_logout(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1392 struct iscsi_task *task,
1393 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1394{
1395 struct iscsi_logout_rsp *hdr;
bfead3b2 1396 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1397 struct iscsi_conn *conn = beiscsi_conn->conn;
1398
1399 hdr = (struct iscsi_logout_rsp *)task->hdr;
7bd6e25c 1400 hdr->opcode = ISCSI_OP_LOGOUT_RSP;
6733b39a
JK		 1401 hdr->t2wait = 5;
1402 hdr->t2retain = 0;
73133261
JSJ		 1403 hdr->flags = csol_cqe->i_flags;
1404 hdr->response = csol_cqe->i_resp;
702dc5e8
JK		 1405 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
1406 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1407 csol_cqe->cmd_wnd - 1);
73133261 1408
7bd6e25c
JK		 1409 hdr->dlength[0] = 0;
1410 hdr->dlength[1] = 0;
1411 hdr->dlength[2] = 0;
6733b39a 1412 hdr->hlength = 0;
bfead3b2 1413 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1414 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1415}
1416
1417static void
1418be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1419 struct iscsi_task *task,
1420 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1421{
1422 struct iscsi_tm_rsp *hdr;
1423 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1424 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1425
1426 hdr = (struct iscsi_tm_rsp *)task->hdr;
7bd6e25c 1427 hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
73133261
JSJ		 1428 hdr->flags = csol_cqe->i_flags;
1429 hdr->response = csol_cqe->i_resp;
702dc5e8
JK		 1430 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
1431 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1432 csol_cqe->cmd_wnd - 1);
73133261 1433
bfead3b2 1434 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1435 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1436}
1437
1438static void
1439hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
1440 struct beiscsi_hba *phba, struct sol_cqe *psol)
1441{
1442 struct hwi_wrb_context *pwrb_context;
bfead3b2 1443 struct wrb_handle *pwrb_handle = NULL;
6733b39a 1444 struct hwi_controller *phwi_ctrlr;
bfead3b2
JK		 1445 struct iscsi_task *task;
1446 struct beiscsi_io_task *io_task;
a7909b39 1447 uint16_t wrb_index, cid, cri_index;
6733b39a
JK		 1448
1449 phwi_ctrlr = phba->phwi_ctrlr;
2c9dfd36
JK		 1450 if (is_chip_be2_be3r(phba)) {
1451 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
73133261 1452 wrb_idx, psol);
2c9dfd36 1453 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
73133261
JSJ		 1454 cid, psol);
1455 } else {
2c9dfd36 1456 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
73133261 1457 wrb_idx, psol);
2c9dfd36 1458 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
73133261
JSJ		 1459 cid, psol);
1460 }
1461
a7909b39
JK		 1462 cri_index = BE_GET_CRI_FROM_CID(cid);
1463 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
73133261 1464 pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index];
32951dd8 1465 task = pwrb_handle->pio_handle;
35e66019 1466
bfead3b2 1467 io_task = task->dd_data;
4a4a11b9
JK		 1468 memset(io_task->pwrb_handle->pwrb, 0, sizeof(struct iscsi_wrb));
1469 iscsi_put_task(task);
6733b39a
JK		 1470}
1471
1472static void
1473be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1474 struct iscsi_task *task,
1475 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1476{
1477 struct iscsi_nopin *hdr;
1478 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1479 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1480
1481 hdr = (struct iscsi_nopin *)task->hdr;
73133261
JSJ		 1482 hdr->flags = csol_cqe->i_flags;
1483 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
702dc5e8
JK		 1484 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1485 csol_cqe->cmd_wnd - 1);
73133261 1486
6733b39a 1487 hdr->opcode = ISCSI_OP_NOOP_IN;
bfead3b2 1488 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1489 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1490}
1491
73133261
JSJ		 1492static void adapter_get_sol_cqe(struct beiscsi_hba *phba,
1493 struct sol_cqe *psol,
1494 struct common_sol_cqe *csol_cqe)
1495{
2c9dfd36
JK		 1496 if (is_chip_be2_be3r(phba)) {
1497 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe,
1498 i_exp_cmd_sn, psol);
1499 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe,
1500 i_res_cnt, psol);
1501 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
1502 i_cmd_wnd, psol);
1503 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe,
1504 wrb_index, psol);
1505 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe,
1506 cid, psol);
1507 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe,
1508 hw_sts, psol);
1509 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe,
1510 i_resp, psol);
1511 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe,
1512 i_sts, psol);
1513 csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe,
1514 i_flags, psol);
1515 } else {
73133261
JSJ		 1516 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1517 i_exp_cmd_sn, psol);
1518 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1519 i_res_cnt, psol);
1520 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1521 wrb_index, psol);
1522 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1523 cid, psol);
1524 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1525 hw_sts, psol);
702dc5e8 1526 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2,
73133261
JSJ		 1527 i_cmd_wnd, psol);
1528 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1529 cmd_cmpl, psol))
1530 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1531 i_sts, psol);
1532 else
1533 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1534 i_sts, psol);
1535 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1536 u, psol))
1537 csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW;
1538
1539 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1540 o, psol))
1541 csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW;
73133261
JSJ		 1542 }
1543}
1544
1545
6733b39a
JK		 1546static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
1547 struct beiscsi_hba *phba, struct sol_cqe *psol)
1548{
1549 struct hwi_wrb_context *pwrb_context;
1550 struct wrb_handle *pwrb_handle;
1551 struct iscsi_wrb *pwrb = NULL;
1552 struct hwi_controller *phwi_ctrlr;
1553 struct iscsi_task *task;
bfead3b2 1554 unsigned int type;
6733b39a
JK		 1555 struct iscsi_conn *conn = beiscsi_conn->conn;
1556 struct iscsi_session *session = conn->session;
73133261 1557 struct common_sol_cqe csol_cqe = {0};
a7909b39 1558 uint16_t cri_index = 0;
6733b39a
JK		 1559
1560 phwi_ctrlr = phba->phwi_ctrlr;
73133261
JSJ		 1561
1562 /* Copy the elements to a common structure */
1563 adapter_get_sol_cqe(phba, psol, &csol_cqe);
1564
a7909b39
JK		 1565 cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid);
1566 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
73133261
JSJ		 1567
1568 pwrb_handle = pwrb_context->pwrb_handle_basestd[
1569 csol_cqe.wrb_index];
1570
32951dd8
JK		 1571 task = pwrb_handle->pio_handle;
1572 pwrb = pwrb_handle->pwrb;
73133261 1573 type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type;
32951dd8 1574
659743b0 1575 spin_lock_bh(&session->back_lock);
bfead3b2 1576 switch (type) {
6733b39a
JK		 1577 case HWH_TYPE_IO:
1578 case HWH_TYPE_IO_RD:
1579 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
dafab8e0 1580 ISCSI_OP_NOOP_OUT)
73133261 1581 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
dafab8e0 1582 else
73133261 1583 be_complete_io(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1584 break;
1585
1586 case HWH_TYPE_LOGOUT:
dafab8e0 1587 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
73133261 1588 be_complete_logout(beiscsi_conn, task, &csol_cqe);
dafab8e0 1589 else
73133261 1590 be_complete_tmf(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1591 break;
1592
1593 case HWH_TYPE_LOGIN:
99bc5d55
JSJ		 1594 beiscsi_log(phba, KERN_ERR,
1595 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1596 "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
1597 " hwi_complete_cmd- Solicited path\n");
6733b39a
JK		 1598 break;
1599
6733b39a 1600 case HWH_TYPE_NOP:
73133261 1601 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1602 break;
1603
1604 default:
99bc5d55
JSJ		 1605 beiscsi_log(phba, KERN_WARNING,
1606 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1607 "BM_%d : In hwi_complete_cmd, unknown type = %d"
1608 "wrb_index 0x%x CID 0x%x\n", type,
73133261
JSJ		 1609 csol_cqe.wrb_index,
1610 csol_cqe.cid);
6733b39a
JK		 1611 break;
1612 }
35e66019 1613
659743b0 1614 spin_unlock_bh(&session->back_lock);
6733b39a
JK		 1615}
1616
1617static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
1618 *pasync_ctx, unsigned int is_header,
1619 unsigned int host_write_ptr)
1620{
1621 if (is_header)
1622 return &pasync_ctx->async_entry[host_write_ptr].
1623 header_busy_list;
1624 else
1625 return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
1626}
1627
1628static struct async_pdu_handle *
1629hwi_get_async_handle(struct beiscsi_hba *phba,
1630 struct beiscsi_conn *beiscsi_conn,
1631 struct hwi_async_pdu_context *pasync_ctx,
1632 struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
1633{
1634 struct be_bus_address phys_addr;
1635 struct list_head *pbusy_list;
1636 struct async_pdu_handle *pasync_handle = NULL;
6733b39a 1637 unsigned char is_header = 0;
73133261
JSJ		 1638 unsigned int index, dpl;
1639
2c9dfd36
JK		 1640 if (is_chip_be2_be3r(phba)) {
1641 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
73133261 1642 dpl, pdpdu_cqe);
2c9dfd36 1643 index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
73133261
JSJ		 1644 index, pdpdu_cqe);
1645 } else {
2c9dfd36 1646 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
73133261 1647 dpl, pdpdu_cqe);
2c9dfd36 1648 index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
73133261
JSJ		 1649 index, pdpdu_cqe);
1650 }
6733b39a
JK		 1651
1652 phys_addr.u.a32.address_lo =
73133261
JSJ		 1653 (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1654 db_addr_lo) / 32] - dpl);
6733b39a 1655 phys_addr.u.a32.address_hi =
73133261
JSJ		 1656 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1657 db_addr_hi) / 32];
6733b39a
JK		 1658
1659 phys_addr.u.a64.address =
1660 *((unsigned long long *)(&phys_addr.u.a64.address));
1661
1662 switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
1663 & PDUCQE_CODE_MASK) {
1664 case UNSOL_HDR_NOTIFY:
1665 is_header = 1;
1666
73133261
JSJ		 1667 pbusy_list = hwi_get_async_busy_list(pasync_ctx,
1668 is_header, index);
6733b39a
JK		 1669 break;
1670 case UNSOL_DATA_NOTIFY:
73133261
JSJ		 1671 pbusy_list = hwi_get_async_busy_list(pasync_ctx,
1672 is_header, index);
6733b39a
JK		 1673 break;
1674 default:
1675 pbusy_list = NULL;
99bc5d55
JSJ		 1676 beiscsi_log(phba, KERN_WARNING,
1677 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1678 "BM_%d : Unexpected code=%d\n",
1679 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1680 code) / 32] & PDUCQE_CODE_MASK);
6733b39a
JK		 1681 return NULL;
1682 }
1683
6733b39a
JK		 1684 WARN_ON(list_empty(pbusy_list));
1685 list_for_each_entry(pasync_handle, pbusy_list, link) {
dc63aac6 1686 if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
6733b39a
JK		 1687 break;
1688 }
1689
1690 WARN_ON(!pasync_handle);
1691
8a86e833
JK		 1692 pasync_handle->cri = BE_GET_ASYNC_CRI_FROM_CID(
1693 beiscsi_conn->beiscsi_conn_cid);
6733b39a 1694 pasync_handle->is_header = is_header;
73133261
JSJ		 1695 pasync_handle->buffer_len = dpl;
1696 *pcq_index = index;
6733b39a 1697
6733b39a
JK		 1698 return pasync_handle;
1699}
1700
1701static unsigned int
99bc5d55
JSJ		 1702hwi_update_async_writables(struct beiscsi_hba *phba,
1703 struct hwi_async_pdu_context *pasync_ctx,
1704 unsigned int is_header, unsigned int cq_index)
6733b39a
JK		 1705{
1706 struct list_head *pbusy_list;
1707 struct async_pdu_handle *pasync_handle;
1708 unsigned int num_entries, writables = 0;
1709 unsigned int *pep_read_ptr, *pwritables;
1710
dc63aac6 1711 num_entries = pasync_ctx->num_entries;
6733b39a
JK		 1712 if (is_header) {
1713 pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
1714 pwritables = &pasync_ctx->async_header.writables;
6733b39a
JK		 1715 } else {
1716 pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
1717 pwritables = &pasync_ctx->async_data.writables;
6733b39a
JK		 1718 }
1719
1720 while ((*pep_read_ptr) != cq_index) {
1721 (*pep_read_ptr)++;
1722 *pep_read_ptr = (*pep_read_ptr) % num_entries;
1723
1724 pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
1725 *pep_read_ptr);
1726 if (writables == 0)
1727 WARN_ON(list_empty(pbusy_list));
1728
1729 if (!list_empty(pbusy_list)) {
1730 pasync_handle = list_entry(pbusy_list->next,
1731 struct async_pdu_handle,
1732 link);
1733 WARN_ON(!pasync_handle);
1734 pasync_handle->consumed = 1;
1735 }
1736
1737 writables++;
1738 }
1739
1740 if (!writables) {
99bc5d55
JSJ		 1741 beiscsi_log(phba, KERN_ERR,
1742 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1743 "BM_%d : Duplicate notification received - index 0x%x!!\n",
1744 cq_index);
6733b39a
JK		 1745 WARN_ON(1);
1746 }
1747
1748 *pwritables = *pwritables + writables;
1749 return 0;
1750}
1751
9728d8d0 1752static void hwi_free_async_msg(struct beiscsi_hba *phba,
8a86e833
JK		 1753 struct hwi_async_pdu_context *pasync_ctx,
1754 unsigned int cri)
6733b39a 1755{
6733b39a
JK		 1756 struct async_pdu_handle *pasync_handle, *tmp_handle;
1757 struct list_head *plist;
6733b39a 1758
6733b39a 1759 plist = &pasync_ctx->async_entry[cri].wait_queue.list;
6733b39a
JK		 1760 list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
1761 list_del(&pasync_handle->link);
1762
9728d8d0 1763 if (pasync_handle->is_header) {
6733b39a
JK		 1764 list_add_tail(&pasync_handle->link,
1765 &pasync_ctx->async_header.free_list);
1766 pasync_ctx->async_header.free_entries++;
6733b39a
JK		 1767 } else {
1768 list_add_tail(&pasync_handle->link,
1769 &pasync_ctx->async_data.free_list);
1770 pasync_ctx->async_data.free_entries++;
6733b39a
JK		 1771 }
1772 }
1773
1774 INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
1775 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
1776 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
6733b39a
JK		 1777}
1778
1779static struct phys_addr *
1780hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
1781 unsigned int is_header, unsigned int host_write_ptr)
1782{
1783 struct phys_addr *pasync_sge = NULL;
1784
1785 if (is_header)
1786 pasync_sge = pasync_ctx->async_header.ring_base;
1787 else
1788 pasync_sge = pasync_ctx->async_data.ring_base;
1789
1790 return pasync_sge + host_write_ptr;
1791}
1792
1793static void hwi_post_async_buffers(struct beiscsi_hba *phba,
8a86e833 1794 unsigned int is_header, uint8_t ulp_num)
6733b39a
JK		 1795{
1796 struct hwi_controller *phwi_ctrlr;
1797 struct hwi_async_pdu_context *pasync_ctx;
1798 struct async_pdu_handle *pasync_handle;
1799 struct list_head *pfree_link, *pbusy_list;
1800 struct phys_addr *pasync_sge;
1801 unsigned int ring_id, num_entries;
8a86e833 1802 unsigned int host_write_num, doorbell_offset;
6733b39a
JK		 1803 unsigned int writables;
1804 unsigned int i = 0;
1805 u32 doorbell = 0;
1806
1807 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833 1808 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num);
dc63aac6 1809 num_entries = pasync_ctx->num_entries;
6733b39a
JK		 1810
1811 if (is_header) {
6733b39a
JK		 1812 writables = min(pasync_ctx->async_header.writables,
1813 pasync_ctx->async_header.free_entries);
1814 pfree_link = pasync_ctx->async_header.free_list.next;
1815 host_write_num = pasync_ctx->async_header.host_write_ptr;
8a86e833
JK		 1816 ring_id = phwi_ctrlr->default_pdu_hdr[ulp_num].id;
1817 doorbell_offset = phwi_ctrlr->default_pdu_hdr[ulp_num].
1818 doorbell_offset;
6733b39a 1819 } else {
6733b39a
JK		 1820 writables = min(pasync_ctx->async_data.writables,
1821 pasync_ctx->async_data.free_entries);
1822 pfree_link = pasync_ctx->async_data.free_list.next;
1823 host_write_num = pasync_ctx->async_data.host_write_ptr;
8a86e833
JK		 1824 ring_id = phwi_ctrlr->default_pdu_data[ulp_num].id;
1825 doorbell_offset = phwi_ctrlr->default_pdu_data[ulp_num].
1826 doorbell_offset;
6733b39a
JK		 1827 }
1828
1829 writables = (writables / 8) * 8;
1830 if (writables) {
1831 for (i = 0; i < writables; i++) {
1832 pbusy_list =
1833 hwi_get_async_busy_list(pasync_ctx, is_header,
1834 host_write_num);
1835 pasync_handle =
1836 list_entry(pfree_link, struct async_pdu_handle,
1837 link);
1838 WARN_ON(!pasync_handle);
1839 pasync_handle->consumed = 0;
1840
1841 pfree_link = pfree_link->next;
1842
1843 pasync_sge = hwi_get_ring_address(pasync_ctx,
1844 is_header, host_write_num);
1845
1846 pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
1847 pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
1848
1849 list_move(&pasync_handle->link, pbusy_list);
1850
1851 host_write_num++;
1852 host_write_num = host_write_num % num_entries;
1853 }
1854
1855 if (is_header) {
1856 pasync_ctx->async_header.host_write_ptr =
1857 host_write_num;
1858 pasync_ctx->async_header.free_entries -= writables;
1859 pasync_ctx->async_header.writables -= writables;
1860 pasync_ctx->async_header.busy_entries += writables;
1861 } else {
1862 pasync_ctx->async_data.host_write_ptr = host_write_num;
1863 pasync_ctx->async_data.free_entries -= writables;
1864 pasync_ctx->async_data.writables -= writables;
1865 pasync_ctx->async_data.busy_entries += writables;
1866 }
1867
1868 doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
1869 doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
1870 doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
1871 doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
1872 << DB_DEF_PDU_CQPROC_SHIFT;
1873
8a86e833 1874 iowrite32(doorbell, phba->db_va + doorbell_offset);
6733b39a
JK		 1875 }
1876}
1877
1878static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
1879 struct beiscsi_conn *beiscsi_conn,
1880 struct i_t_dpdu_cqe *pdpdu_cqe)
1881{
1882 struct hwi_controller *phwi_ctrlr;
1883 struct hwi_async_pdu_context *pasync_ctx;
1884 struct async_pdu_handle *pasync_handle = NULL;
1885 unsigned int cq_index = -1;
8a86e833
JK		 1886 uint16_t cri_index = BE_GET_CRI_FROM_CID(
1887 beiscsi_conn->beiscsi_conn_cid);
6733b39a
JK		 1888
1889 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833
JK		 1890 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
1891 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
1892 cri_index));
6733b39a
JK		 1893
1894 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
1895 pdpdu_cqe, &cq_index);
1896 BUG_ON(pasync_handle->is_header != 0);
1897 if (pasync_handle->consumed == 0)
99bc5d55
JSJ		 1898 hwi_update_async_writables(phba, pasync_ctx,
1899 pasync_handle->is_header, cq_index);
6733b39a 1900
8a86e833
JK		 1901 hwi_free_async_msg(phba, pasync_ctx, pasync_handle->cri);
1902 hwi_post_async_buffers(phba, pasync_handle->is_header,
1903 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
1904 cri_index));
6733b39a
JK		 1905}
1906
1907static unsigned int
1908hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
1909 struct beiscsi_hba *phba,
1910 struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
1911{
1912 struct list_head *plist;
1913 struct async_pdu_handle *pasync_handle;
1914 void *phdr = NULL;
1915 unsigned int hdr_len = 0, buf_len = 0;
1916 unsigned int status, index = 0, offset = 0;
1917 void *pfirst_buffer = NULL;
1918 unsigned int num_buf = 0;
1919
1920 plist = &pasync_ctx->async_entry[cri].wait_queue.list;
1921
1922 list_for_each_entry(pasync_handle, plist, link) {
1923 if (index == 0) {
1924 phdr = pasync_handle->pbuffer;
1925 hdr_len = pasync_handle->buffer_len;
1926 } else {
1927 buf_len = pasync_handle->buffer_len;
1928 if (!num_buf) {
1929 pfirst_buffer = pasync_handle->pbuffer;
1930 num_buf++;
1931 }
1932 memcpy(pfirst_buffer + offset,
1933 pasync_handle->pbuffer, buf_len);
f2ba02b8 1934 offset += buf_len;
6733b39a
JK		 1935 }
1936 index++;
1937 }
1938
1939 status = beiscsi_process_async_pdu(beiscsi_conn, phba,
7da50879 1940 phdr, hdr_len, pfirst_buffer,
f2ba02b8 1941 offset);
6733b39a 1942
8a86e833 1943 hwi_free_async_msg(phba, pasync_ctx, cri);
6733b39a
JK		 1944 return 0;
1945}
1946
1947static unsigned int
1948hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
1949 struct beiscsi_hba *phba,
1950 struct async_pdu_handle *pasync_handle)
1951{
1952 struct hwi_async_pdu_context *pasync_ctx;
1953 struct hwi_controller *phwi_ctrlr;
1954 unsigned int bytes_needed = 0, status = 0;
1955 unsigned short cri = pasync_handle->cri;
1956 struct pdu_base *ppdu;
1957
1958 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833
JK		 1959 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
1960 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
1961 BE_GET_CRI_FROM_CID(beiscsi_conn->
1962 beiscsi_conn_cid)));
6733b39a
JK		 1963
1964 list_del(&pasync_handle->link);
1965 if (pasync_handle->is_header) {
1966 pasync_ctx->async_header.busy_entries--;
1967 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
8a86e833 1968 hwi_free_async_msg(phba, pasync_ctx, cri);
6733b39a
JK		 1969 BUG();
1970 }
1971
1972 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
1973 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
1974 pasync_ctx->async_entry[cri].wait_queue.hdr_len =
1975 (unsigned short)pasync_handle->buffer_len;
1976 list_add_tail(&pasync_handle->link,
1977 &pasync_ctx->async_entry[cri].wait_queue.list);
1978
1979 ppdu = pasync_handle->pbuffer;
1980 bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
1981 data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
1982 0xFFFF0000) | ((be16_to_cpu((ppdu->
1983 dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
1984 & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
1985
1986 if (status == 0) {
1987 pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
1988 bytes_needed;
1989
1990 if (bytes_needed == 0)
1991 status = hwi_fwd_async_msg(beiscsi_conn, phba,
1992 pasync_ctx, cri);
1993 }
1994 } else {
1995 pasync_ctx->async_data.busy_entries--;
1996 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
1997 list_add_tail(&pasync_handle->link,
1998 &pasync_ctx->async_entry[cri].wait_queue.
1999 list);
2000 pasync_ctx->async_entry[cri].wait_queue.
2001 bytes_received +=
2002 (unsigned short)pasync_handle->buffer_len;
2003
2004 if (pasync_ctx->async_entry[cri].wait_queue.
2005 bytes_received >=
2006 pasync_ctx->async_entry[cri].wait_queue.
2007 bytes_needed)
2008 status = hwi_fwd_async_msg(beiscsi_conn, phba,
2009 pasync_ctx, cri);
2010 }
2011 }
2012 return status;
2013}
2014
2015static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
2016 struct beiscsi_hba *phba,
2017 struct i_t_dpdu_cqe *pdpdu_cqe)
2018{
2019 struct hwi_controller *phwi_ctrlr;
2020 struct hwi_async_pdu_context *pasync_ctx;
2021 struct async_pdu_handle *pasync_handle = NULL;
2022 unsigned int cq_index = -1;
8a86e833
JK		 2023 uint16_t cri_index = BE_GET_CRI_FROM_CID(
2024 beiscsi_conn->beiscsi_conn_cid);
6733b39a
JK		 2025
2026 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833
JK		 2027 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
2028 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
2029 cri_index));
2030
6733b39a
JK		 2031 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
2032 pdpdu_cqe, &cq_index);
2033
2034 if (pasync_handle->consumed == 0)
99bc5d55
JSJ		 2035 hwi_update_async_writables(phba, pasync_ctx,
2036 pasync_handle->is_header, cq_index);
2037
6733b39a 2038 hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
8a86e833
JK		 2039 hwi_post_async_buffers(phba, pasync_handle->is_header,
2040 BEISCSI_GET_ULP_FROM_CRI(
2041 phwi_ctrlr, cri_index));
6733b39a
JK		 2042}
2043
2e4e8f65 2044void beiscsi_process_mcc_cq(struct beiscsi_hba *phba)
756d29c8
JK		 2045{
2046 struct be_queue_info *mcc_cq;
2047 struct be_mcc_compl *mcc_compl;
2048 unsigned int num_processed = 0;
2049
2050 mcc_cq = &phba->ctrl.mcc_obj.cq;
2051 mcc_compl = queue_tail_node(mcc_cq);
2052 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
2053 while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
756d29c8
JK		 2054 if (num_processed >= 32) {
2055 hwi_ring_cq_db(phba, mcc_cq->id,
1094cf68 2056 num_processed, 0);
756d29c8
JK		 2057 num_processed = 0;
2058 }
2059 if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
53aefe25 2060 beiscsi_process_async_event(phba, mcc_compl);
756d29c8 2061 } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
2e4e8f65 2062 beiscsi_process_mcc_compl(&phba->ctrl, mcc_compl);
756d29c8
JK		 2063 }
2064
2065 mcc_compl->flags = 0;
2066 queue_tail_inc(mcc_cq);
2067 mcc_compl = queue_tail_node(mcc_cq);
2068 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
2069 num_processed++;
2070 }
2071
2072 if (num_processed > 0)
1094cf68 2073 hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1);
756d29c8 2074}
bfead3b2 2075
6763daae
JSJ		 2076/**
2077 * beiscsi_process_cq()- Process the Completion Queue
2078 * @pbe_eq: Event Q on which the Completion has come
1094cf68 2079 * @budget: Max number of events to processed
6763daae
JSJ		 2080 *
2081 * return
2082 * Number of Completion Entries processed.
2083 **/
1094cf68 2084unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq, int budget)
6733b39a 2085{
6733b39a
JK		 2086 struct be_queue_info *cq;
2087 struct sol_cqe *sol;
2088 struct dmsg_cqe *dmsg;
1094cf68 2089 unsigned int total = 0;
6733b39a 2090 unsigned int num_processed = 0;
0a513dd8 2091 unsigned short code = 0, cid = 0;
a7909b39 2092 uint16_t cri_index = 0;
6733b39a 2093 struct beiscsi_conn *beiscsi_conn;
c2462288
JK		 2094 struct beiscsi_endpoint *beiscsi_ep;
2095 struct iscsi_endpoint *ep;
bfead3b2 2096 struct beiscsi_hba *phba;
6733b39a 2097
bfead3b2 2098 cq = pbe_eq->cq;
6733b39a 2099 sol = queue_tail_node(cq);
bfead3b2 2100 phba = pbe_eq->phba;
6733b39a
JK		 2101
2102 while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
2103 CQE_VALID_MASK) {
2104 be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
2105
73133261
JSJ		 2106 code = (sol->dw[offsetof(struct amap_sol_cqe, code) /
2107 32] & CQE_CODE_MASK);
2108
2109 /* Get the CID */
2c9dfd36
JK		 2110 if (is_chip_be2_be3r(phba)) {
2111 cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol);
2112 } else {
73133261
JSJ		 2113 if ((code == DRIVERMSG_NOTIFY) ||
2114 (code == UNSOL_HDR_NOTIFY) ||
2115 (code == UNSOL_DATA_NOTIFY))
2116 cid = AMAP_GET_BITS(
2117 struct amap_i_t_dpdu_cqe_v2,
2118 cid, sol);
2119 else
2120 cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
2121 cid, sol);
2c9dfd36 2122 }
32951dd8 2123
a7909b39
JK		 2124 cri_index = BE_GET_CRI_FROM_CID(cid);
2125 ep = phba->ep_array[cri_index];
b7ab35b1
JK		 2126
2127 if (ep == NULL) {
2128 /* connection has already been freed
2129 * just move on to next one
2130 */
2131 beiscsi_log(phba, KERN_WARNING,
2132 BEISCSI_LOG_INIT,
2133 "BM_%d : proc cqe of disconn ep: cid %d\n",
2134 cid);
2135 goto proc_next_cqe;
2136 }
2137
c2462288
JK		 2138 beiscsi_ep = ep->dd_data;
2139 beiscsi_conn = beiscsi_ep->conn;
756d29c8 2140
1094cf68
JB		 2141 /* replenish cq */
2142 if (num_processed == 32) {
2143 hwi_ring_cq_db(phba, cq->id, 32, 0);
6733b39a
JK		 2144 num_processed = 0;
2145 }
1094cf68 2146 total++;
6733b39a 2147
0a513dd8 2148 switch (code) {
6733b39a
JK		 2149 case SOL_CMD_COMPLETE:
2150 hwi_complete_cmd(beiscsi_conn, phba, sol);
2151 break;
2152 case DRIVERMSG_NOTIFY:
99bc5d55
JSJ		 2153 beiscsi_log(phba, KERN_INFO,
2154 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2155 "BM_%d : Received %s[%d] on CID : %d\n",
2156 cqe_desc[code], code, cid);
99bc5d55 2157
6733b39a
JK		 2158 dmsg = (struct dmsg_cqe *)sol;
2159 hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
2160 break;
2161 case UNSOL_HDR_NOTIFY:
99bc5d55
JSJ		 2162 beiscsi_log(phba, KERN_INFO,
2163 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2164 "BM_%d : Received %s[%d] on CID : %d\n",
2165 cqe_desc[code], code, cid);
99bc5d55 2166
8f09a3b9 2167 spin_lock_bh(&phba->async_pdu_lock);
bfead3b2
JK		 2168 hwi_process_default_pdu_ring(beiscsi_conn, phba,
2169 (struct i_t_dpdu_cqe *)sol);
8f09a3b9 2170 spin_unlock_bh(&phba->async_pdu_lock);
bfead3b2 2171 break;
6733b39a 2172 case UNSOL_DATA_NOTIFY:
99bc5d55
JSJ		 2173 beiscsi_log(phba, KERN_INFO,
2174 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
6763daae
JSJ		 2175 "BM_%d : Received %s[%d] on CID : %d\n",
2176 cqe_desc[code], code, cid);
99bc5d55 2177
8f09a3b9 2178 spin_lock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2179 hwi_process_default_pdu_ring(beiscsi_conn, phba,
2180 (struct i_t_dpdu_cqe *)sol);
8f09a3b9 2181 spin_unlock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2182 break;
2183 case CXN_INVALIDATE_INDEX_NOTIFY:
2184 case CMD_INVALIDATED_NOTIFY:
2185 case CXN_INVALIDATE_NOTIFY:
99bc5d55
JSJ		 2186 beiscsi_log(phba, KERN_ERR,
2187 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2188 "BM_%d : Ignoring %s[%d] on CID : %d\n",
2189 cqe_desc[code], code, cid);
6733b39a 2190 break;
1094cf68 2191 case CXN_KILLED_HDR_DIGEST_ERR:
6733b39a 2192 case SOL_CMD_KILLED_DATA_DIGEST_ERR:
1094cf68
JB		 2193 beiscsi_log(phba, KERN_ERR,
2194 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
2195 "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
2196 cqe_desc[code], code, cid);
2197 break;
6733b39a
JK		 2198 case CMD_KILLED_INVALID_STATSN_RCVD:
2199 case CMD_KILLED_INVALID_R2T_RCVD:
2200 case CMD_CXN_KILLED_LUN_INVALID:
2201 case CMD_CXN_KILLED_ICD_INVALID:
2202 case CMD_CXN_KILLED_ITT_INVALID:
2203 case CMD_CXN_KILLED_SEQ_OUTOFORDER:
2204 case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
99bc5d55
JSJ		 2205 beiscsi_log(phba, KERN_ERR,
2206 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
6763daae
JSJ		 2207 "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
2208 cqe_desc[code], code, cid);
6733b39a
JK		 2209 break;
2210 case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
99bc5d55
JSJ		 2211 beiscsi_log(phba, KERN_ERR,
2212 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2213 "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
2214 cqe_desc[code], code, cid);
8f09a3b9 2215 spin_lock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2216 hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
2217 (struct i_t_dpdu_cqe *) sol);
8f09a3b9 2218 spin_unlock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2219 break;
2220 case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
2221 case CXN_KILLED_BURST_LEN_MISMATCH:
2222 case CXN_KILLED_AHS_RCVD:
6733b39a
JK		 2223 case CXN_KILLED_UNKNOWN_HDR:
2224 case CXN_KILLED_STALE_ITT_TTT_RCVD:
2225 case CXN_KILLED_INVALID_ITT_TTT_RCVD:
2226 case CXN_KILLED_TIMED_OUT:
2227 case CXN_KILLED_FIN_RCVD:
6763daae
JSJ		 2228 case CXN_KILLED_RST_SENT:
2229 case CXN_KILLED_RST_RCVD:
6733b39a
JK		 2230 case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
2231 case CXN_KILLED_BAD_WRB_INDEX_ERROR:
2232 case CXN_KILLED_OVER_RUN_RESIDUAL:
2233 case CXN_KILLED_UNDER_RUN_RESIDUAL:
2234 case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
99bc5d55
JSJ		 2235 beiscsi_log(phba, KERN_ERR,
2236 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2237 "BM_%d : Event %s[%d] received on CID : %d\n",
2238 cqe_desc[code], code, cid);
0a513dd8
JSJ		 2239 if (beiscsi_conn)
2240 iscsi_conn_failure(beiscsi_conn->conn,
2241 ISCSI_ERR_CONN_FAILED);
6733b39a
JK		 2242 break;
2243 default:
99bc5d55
JSJ		 2244 beiscsi_log(phba, KERN_ERR,
2245 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2246 "BM_%d : Invalid CQE Event Received Code : %d"
2247 "CID 0x%x...\n",
0a513dd8 2248 code, cid);
6733b39a
JK		 2249 break;
2250 }
2251
b7ab35b1 2252proc_next_cqe:
6733b39a
JK		 2253 AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
2254 queue_tail_inc(cq);
2255 sol = queue_tail_node(cq);
2256 num_processed++;
1094cf68
JB		 2257 if (total == budget)
2258 break;
6733b39a
JK		 2259 }
2260
1094cf68
JB		 2261 hwi_ring_cq_db(phba, cq->id, num_processed, 1);
2262 return total;
6733b39a
JK		 2263}
2264
756d29c8 2265void beiscsi_process_all_cqs(struct work_struct *work)
6733b39a
JK		 2266{
2267 unsigned long flags;
bfead3b2
JK		 2268 struct hwi_controller *phwi_ctrlr;
2269 struct hwi_context_memory *phwi_context;
72fb46a9
JSJ		 2270 struct beiscsi_hba *phba;
2271 struct be_eq_obj *pbe_eq =
2272 container_of(work, struct be_eq_obj, work_cqs);
6733b39a 2273
72fb46a9 2274 phba = pbe_eq->phba;
bfead3b2
JK		 2275 phwi_ctrlr = phba->phwi_ctrlr;
2276 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2 2277
72fb46a9 2278 if (pbe_eq->todo_mcc_cq) {
6733b39a 2279 spin_lock_irqsave(&phba->isr_lock, flags);
72fb46a9 2280 pbe_eq->todo_mcc_cq = false;
6733b39a 2281 spin_unlock_irqrestore(&phba->isr_lock, flags);
2e4e8f65 2282 beiscsi_process_mcc_cq(phba);
6733b39a
JK		 2283 }
2284
72fb46a9 2285 if (pbe_eq->todo_cq) {
6733b39a 2286 spin_lock_irqsave(&phba->isr_lock, flags);
72fb46a9 2287 pbe_eq->todo_cq = false;
6733b39a 2288 spin_unlock_irqrestore(&phba->isr_lock, flags);
1094cf68 2289 beiscsi_process_cq(pbe_eq, BE2_MAX_NUM_CQ_PROC);
6733b39a 2290 }
72fb46a9
JSJ		 2291
2292 /* rearm EQ for further interrupts */
2293 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
6733b39a
JK		 2294}
2295
511cbce2 2296static int be_iopoll(struct irq_poll *iop, int budget)
6733b39a 2297{
1094cf68 2298 unsigned int ret, num_eq_processed;
6733b39a 2299 struct beiscsi_hba *phba;
bfead3b2 2300 struct be_eq_obj *pbe_eq;
1094cf68
JB		 2301 struct be_eq_entry *eqe = NULL;
2302 struct be_queue_info *eq;
6733b39a 2303
1094cf68 2304 num_eq_processed = 0;
bfead3b2 2305 pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
1094cf68
JB		 2306 phba = pbe_eq->phba;
2307 eq = &pbe_eq->q;
2308 eqe = queue_tail_node(eq);
2309
2310 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32] &
2311 EQE_VALID_MASK) {
2312 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
2313 queue_tail_inc(eq);
2314 eqe = queue_tail_node(eq);
2315 num_eq_processed++;
2316 }
2317
2318 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
2319
2320 ret = beiscsi_process_cq(pbe_eq, budget);
73af08e1 2321 pbe_eq->cq_count += ret;
6733b39a 2322 if (ret < budget) {
511cbce2 2323 irq_poll_complete(iop);
99bc5d55
JSJ		 2324 beiscsi_log(phba, KERN_INFO,
2325 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1094cf68
JB		 2326 "BM_%d : rearm pbe_eq->q.id =%d ret %d\n",
2327 pbe_eq->q.id, ret);
bfead3b2 2328 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
6733b39a
JK		 2329 }
2330 return ret;
2331}
2332
09a1093a
JSJ		 2333static void
2334hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg,
2335 unsigned int num_sg, struct beiscsi_io_task *io_task)
2336{
2337 struct iscsi_sge *psgl;
2338 unsigned int sg_len, index;
2339 unsigned int sge_len = 0;
2340 unsigned long long addr;
2341 struct scatterlist *l_sg;
2342 unsigned int offset;
2343
2344 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb,
2345 io_task->bhs_pa.u.a32.address_lo);
2346 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb,
2347 io_task->bhs_pa.u.a32.address_hi);
2348
2349 l_sg = sg;
2350 for (index = 0; (index < num_sg) && (index < 2); index++,
2351 sg = sg_next(sg)) {
2352 if (index == 0) {
2353 sg_len = sg_dma_len(sg);
2354 addr = (u64) sg_dma_address(sg);
2355 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2356 sge0_addr_lo, pwrb,
2357 lower_32_bits(addr));
2358 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2359 sge0_addr_hi, pwrb,
2360 upper_32_bits(addr));
2361 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2362 sge0_len, pwrb,
2363 sg_len);
2364 sge_len = sg_len;
2365 } else {
2366 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset,
2367 pwrb, sge_len);
2368 sg_len = sg_dma_len(sg);
2369 addr = (u64) sg_dma_address(sg);
2370 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2371 sge1_addr_lo, pwrb,
2372 lower_32_bits(addr));
2373 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2374 sge1_addr_hi, pwrb,
2375 upper_32_bits(addr));
2376 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2377 sge1_len, pwrb,
2378 sg_len);
2379 }
2380 }
2381 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2382 memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
2383
2384 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
2385
2386 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2387 io_task->bhs_pa.u.a32.address_hi);
2388 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2389 io_task->bhs_pa.u.a32.address_lo);
2390
2391 if (num_sg == 1) {
2392 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2393 1);
2394 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2395 0);
2396 } else if (num_sg == 2) {
2397 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2398 0);
2399 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2400 1);
2401 } else {
2402 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2403 0);
2404 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2405 0);
2406 }
2407
2408 sg = l_sg;
2409 psgl++;
2410 psgl++;
2411 offset = 0;
2412 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
2413 sg_len = sg_dma_len(sg);
2414 addr = (u64) sg_dma_address(sg);
2415 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2416 lower_32_bits(addr));
2417 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2418 upper_32_bits(addr));
2419 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
2420 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
2421 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2422 offset += sg_len;
2423 }
2424 psgl--;
2425 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2426}
2427
6733b39a
JK		 2428static void
2429hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
2430 unsigned int num_sg, struct beiscsi_io_task *io_task)
2431{
2432 struct iscsi_sge *psgl;
58ff4bd0 2433 unsigned int sg_len, index;
6733b39a
JK		 2434 unsigned int sge_len = 0;
2435 unsigned long long addr;
2436 struct scatterlist *l_sg;
2437 unsigned int offset;
2438
2439 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2440 io_task->bhs_pa.u.a32.address_lo);
2441 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2442 io_task->bhs_pa.u.a32.address_hi);
2443
2444 l_sg = sg;
48bd86cf
JK		 2445 for (index = 0; (index < num_sg) && (index < 2); index++,
2446 sg = sg_next(sg)) {
6733b39a
JK		 2447 if (index == 0) {
2448 sg_len = sg_dma_len(sg);
2449 addr = (u64) sg_dma_address(sg);
2450 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
457ff3b7 2451 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2452 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
457ff3b7 2453 ((u32)(addr >> 32)));
6733b39a
JK		 2454 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2455 sg_len);
2456 sge_len = sg_len;
6733b39a 2457 } else {
6733b39a
JK		 2458 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
2459 pwrb, sge_len);
2460 sg_len = sg_dma_len(sg);
2461 addr = (u64) sg_dma_address(sg);
2462 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
457ff3b7 2463 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2464 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
457ff3b7 2465 ((u32)(addr >> 32)));
6733b39a
JK		 2466 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
2467 sg_len);
2468 }
2469 }
2470 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2471 memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
2472
2473 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
2474
2475 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2476 io_task->bhs_pa.u.a32.address_hi);
2477 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2478 io_task->bhs_pa.u.a32.address_lo);
2479
caf818f1
JK		 2480 if (num_sg == 1) {
2481 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2482 1);
2483 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2484 0);
2485 } else if (num_sg == 2) {
2486 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2487 0);
2488 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2489 1);
2490 } else {
2491 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2492 0);
2493 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2494 0);
2495 }
6733b39a
JK		 2496 sg = l_sg;
2497 psgl++;
2498 psgl++;
2499 offset = 0;
48bd86cf 2500 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
6733b39a
JK		 2501 sg_len = sg_dma_len(sg);
2502 addr = (u64) sg_dma_address(sg);
2503 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2504 (addr & 0xFFFFFFFF));
2505 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2506 (addr >> 32));
2507 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
2508 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
2509 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2510 offset += sg_len;
2511 }
2512 psgl--;
2513 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2514}
2515
d629c471
JSJ		 2516/**
2517 * hwi_write_buffer()- Populate the WRB with task info
2518 * @pwrb: ptr to the WRB entry
2519 * @task: iscsi task which is to be executed
2520 **/
e0493627 2521static int hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
6733b39a
JK		 2522{
2523 struct iscsi_sge *psgl;
6733b39a
JK		 2524 struct beiscsi_io_task *io_task = task->dd_data;
2525 struct beiscsi_conn *beiscsi_conn = io_task->conn;
2526 struct beiscsi_hba *phba = beiscsi_conn->phba;
09a1093a 2527 uint8_t dsp_value = 0;
6733b39a
JK		 2528
2529 io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
2530 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2531 io_task->bhs_pa.u.a32.address_lo);
2532 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2533 io_task->bhs_pa.u.a32.address_hi);
2534
2535 if (task->data) {
09a1093a
JSJ		 2536
2537 /* Check for the data_count */
2538 dsp_value = (task->data_count) ? 1 : 0;
2539
2c9dfd36
JK		 2540 if (is_chip_be2_be3r(phba))
2541 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp,
09a1093a
JSJ		 2542 pwrb, dsp_value);
2543 else
2c9dfd36 2544 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp,
09a1093a
JSJ		 2545 pwrb, dsp_value);
2546
2547 /* Map addr only if there is data_count */
2548 if (dsp_value) {
d629c471
JSJ		 2549 io_task->mtask_addr = pci_map_single(phba->pcidev,
2550 task->data,
2551 task->data_count,
2552 PCI_DMA_TODEVICE);
e0493627
AK		 2553 if (pci_dma_mapping_error(phba->pcidev,
2554 io_task->mtask_addr))
2555 return -ENOMEM;
d629c471 2556 io_task->mtask_data_count = task->data_count;
09a1093a 2557 } else
d629c471 2558 io_task->mtask_addr = 0;
09a1093a 2559
6733b39a 2560 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
d629c471 2561 lower_32_bits(io_task->mtask_addr));
6733b39a 2562 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
d629c471 2563 upper_32_bits(io_task->mtask_addr));
6733b39a
JK		 2564 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2565 task->data_count);
2566
2567 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
2568 } else {
2569 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
d629c471 2570 io_task->mtask_addr = 0;
6733b39a
JK		 2571 }
2572
2573 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2574
2575 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
2576
2577 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2578 io_task->bhs_pa.u.a32.address_hi);
2579 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2580 io_task->bhs_pa.u.a32.address_lo);
2581 if (task->data) {
2582 psgl++;
2583 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
2584 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
2585 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
2586 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
2587 AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
2588 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2589
2590 psgl++;
2591 if (task->data) {
2592 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
d629c471 2593 lower_32_bits(io_task->mtask_addr));
6733b39a 2594 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
d629c471 2595 upper_32_bits(io_task->mtask_addr));
6733b39a
JK		 2596 }
2597 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
2598 }
2599 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
e0493627 2600 return 0;
6733b39a
JK		 2601}
2602
843ae752
JK		 2603/**
2604 * beiscsi_find_mem_req()- Find mem needed
2605 * @phba: ptr to HBA struct
2606 **/
6733b39a
JK		 2607static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
2608{
8a86e833 2609 uint8_t mem_descr_index, ulp_num;
bfead3b2 2610 unsigned int num_cq_pages, num_async_pdu_buf_pages;
6733b39a
JK		 2611 unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
2612 unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
2613
2614 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
2615 sizeof(struct sol_cqe));
6733b39a
JK		 2616
2617 phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
2618
2619 phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
2620 BE_ISCSI_PDU_HEADER_SIZE;
2621 phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
2622 sizeof(struct hwi_context_memory);
2623
6733b39a
JK		 2624
2625 phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
2626 * (phba->params.wrbs_per_cxn)
2627 * phba->params.cxns_per_ctrl;
2628 wrb_sz_per_cxn = sizeof(struct wrb_handle) *
2629 (phba->params.wrbs_per_cxn);
2630 phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
2631 phba->params.cxns_per_ctrl);
2632
2633 phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
2634 phba->params.icds_per_ctrl;
2635 phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
2636 phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
8a86e833
JK		 2637 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
2638 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 2639
8a86e833
JK		 2640 num_async_pdu_buf_sgl_pages =
2641 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2642 phba, ulp_num) *
2643 sizeof(struct phys_addr));
2644
2645 num_async_pdu_buf_pages =
2646 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2647 phba, ulp_num) *
2648 phba->params.defpdu_hdr_sz);
2649
2650 num_async_pdu_data_pages =
2651 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2652 phba, ulp_num) *
2653 phba->params.defpdu_data_sz);
2654
2655 num_async_pdu_data_sgl_pages =
2656 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2657 phba, ulp_num) *
2658 sizeof(struct phys_addr));
2659
a129d92f
JK		 2660 mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 +
2661 (ulp_num * MEM_DESCR_OFFSET));
2662 phba->mem_req[mem_descr_index] =
2663 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2664 BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;
2665
8a86e833
JK		 2666 mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
2667 (ulp_num * MEM_DESCR_OFFSET));
2668 phba->mem_req[mem_descr_index] =
2669 num_async_pdu_buf_pages *
2670 PAGE_SIZE;
2671
2672 mem_descr_index = (HWI_MEM_ASYNC_DATA_BUF_ULP0 +
2673 (ulp_num * MEM_DESCR_OFFSET));
2674 phba->mem_req[mem_descr_index] =
2675 num_async_pdu_data_pages *
2676 PAGE_SIZE;
2677
2678 mem_descr_index = (HWI_MEM_ASYNC_HEADER_RING_ULP0 +
2679 (ulp_num * MEM_DESCR_OFFSET));
2680 phba->mem_req[mem_descr_index] =
2681 num_async_pdu_buf_sgl_pages *
2682 PAGE_SIZE;
2683
2684 mem_descr_index = (HWI_MEM_ASYNC_DATA_RING_ULP0 +
2685 (ulp_num * MEM_DESCR_OFFSET));
2686 phba->mem_req[mem_descr_index] =
2687 num_async_pdu_data_sgl_pages *
2688 PAGE_SIZE;
2689
2690 mem_descr_index = (HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
2691 (ulp_num * MEM_DESCR_OFFSET));
2692 phba->mem_req[mem_descr_index] =
2693 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2694 sizeof(struct async_pdu_handle);
2695
2696 mem_descr_index = (HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
2697 (ulp_num * MEM_DESCR_OFFSET));
2698 phba->mem_req[mem_descr_index] =
2699 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2700 sizeof(struct async_pdu_handle);
2701
2702 mem_descr_index = (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
2703 (ulp_num * MEM_DESCR_OFFSET));
2704 phba->mem_req[mem_descr_index] =
2705 sizeof(struct hwi_async_pdu_context) +
2706 (BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2707 sizeof(struct hwi_async_entry));
2708 }
2709 }
6733b39a
JK		 2710}
2711
2712static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
2713{
6733b39a 2714 dma_addr_t bus_add;
a7909b39
JK		 2715 struct hwi_controller *phwi_ctrlr;
2716 struct be_mem_descriptor *mem_descr;
6733b39a
JK		 2717 struct mem_array *mem_arr, *mem_arr_orig;
2718 unsigned int i, j, alloc_size, curr_alloc_size;
2719
3ec78271 2720 phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
6733b39a
JK		 2721 if (!phba->phwi_ctrlr)
2722 return -ENOMEM;
2723
a7909b39
JK		 2724 /* Allocate memory for wrb_context */
2725 phwi_ctrlr = phba->phwi_ctrlr;
2726 phwi_ctrlr->wrb_context = kzalloc(sizeof(struct hwi_wrb_context) *
2727 phba->params.cxns_per_ctrl,
2728 GFP_KERNEL);
2729 if (!phwi_ctrlr->wrb_context)
2730 return -ENOMEM;
2731
6733b39a
JK		 2732 phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
2733 GFP_KERNEL);
2734 if (!phba->init_mem) {
a7909b39 2735 kfree(phwi_ctrlr->wrb_context);
6733b39a
JK		 2736 kfree(phba->phwi_ctrlr);
2737 return -ENOMEM;
2738 }
2739
2740 mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
2741 GFP_KERNEL);
2742 if (!mem_arr_orig) {
2743 kfree(phba->init_mem);
a7909b39 2744 kfree(phwi_ctrlr->wrb_context);
6733b39a
JK		 2745 kfree(phba->phwi_ctrlr);
2746 return -ENOMEM;
2747 }
2748
2749 mem_descr = phba->init_mem;
2750 for (i = 0; i < SE_MEM_MAX; i++) {
8a86e833
JK		 2751 if (!phba->mem_req[i]) {
2752 mem_descr->mem_array = NULL;
2753 mem_descr++;
2754 continue;
2755 }
2756
6733b39a
JK		 2757 j = 0;
2758 mem_arr = mem_arr_orig;
2759 alloc_size = phba->mem_req[i];
2760 memset(mem_arr, 0, sizeof(struct mem_array) *
2761 BEISCSI_MAX_FRAGS_INIT);
2762 curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
2763 do {
2764 mem_arr->virtual_address = pci_alloc_consistent(
2765 phba->pcidev,
2766 curr_alloc_size,
2767 &bus_add);
2768 if (!mem_arr->virtual_address) {
2769 if (curr_alloc_size <= BE_MIN_MEM_SIZE)
2770 goto free_mem;
2771 if (curr_alloc_size -
2772 rounddown_pow_of_two(curr_alloc_size))
2773 curr_alloc_size = rounddown_pow_of_two
2774 (curr_alloc_size);
2775 else
2776 curr_alloc_size = curr_alloc_size / 2;
2777 } else {
2778 mem_arr->bus_address.u.
2779 a64.address = (__u64) bus_add;
2780 mem_arr->size = curr_alloc_size;
2781 alloc_size -= curr_alloc_size;
2782 curr_alloc_size = min(be_max_phys_size *
2783 1024, alloc_size);
2784 j++;
2785 mem_arr++;
2786 }
2787 } while (alloc_size);
2788 mem_descr->num_elements = j;
2789 mem_descr->size_in_bytes = phba->mem_req[i];
2790 mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
2791 GFP_KERNEL);
2792 if (!mem_descr->mem_array)
2793 goto free_mem;
2794
2795 memcpy(mem_descr->mem_array, mem_arr_orig,
2796 sizeof(struct mem_array) * j);
2797 mem_descr++;
2798 }
2799 kfree(mem_arr_orig);
2800 return 0;
2801free_mem:
2802 mem_descr->num_elements = j;
2803 while ((i) || (j)) {
2804 for (j = mem_descr->num_elements; j > 0; j--) {
2805 pci_free_consistent(phba->pcidev,
2806 mem_descr->mem_array[j - 1].size,
2807 mem_descr->mem_array[j - 1].
2808 virtual_address,
457ff3b7
JK		 2809 (unsigned long)mem_descr->
2810 mem_array[j - 1].
6733b39a
JK		 2811 bus_address.u.a64.address);
2812 }
2813 if (i) {
2814 i--;
2815 kfree(mem_descr->mem_array);
2816 mem_descr--;
2817 }
2818 }
2819 kfree(mem_arr_orig);
2820 kfree(phba->init_mem);
a7909b39 2821 kfree(phba->phwi_ctrlr->wrb_context);
6733b39a
JK		 2822 kfree(phba->phwi_ctrlr);
2823 return -ENOMEM;
2824}
2825
2826static int beiscsi_get_memory(struct beiscsi_hba *phba)
2827{
2828 beiscsi_find_mem_req(phba);
2829 return beiscsi_alloc_mem(phba);
2830}
2831
2832static void iscsi_init_global_templates(struct beiscsi_hba *phba)
2833{
2834 struct pdu_data_out *pdata_out;
2835 struct pdu_nop_out *pnop_out;
2836 struct be_mem_descriptor *mem_descr;
2837
2838 mem_descr = phba->init_mem;
2839 mem_descr += ISCSI_MEM_GLOBAL_HEADER;
2840 pdata_out =
2841 (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
2842 memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2843
2844 AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
2845 IIOC_SCSI_DATA);
2846
2847 pnop_out =
2848 (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
2849 virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
2850
2851 memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2852 AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
2853 AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
2854 AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
2855}
2856
3ec78271 2857static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
6733b39a
JK		 2858{
2859 struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
a7909b39 2860 struct hwi_context_memory *phwi_ctxt;
3ec78271 2861 struct wrb_handle *pwrb_handle = NULL;
6733b39a
JK		 2862 struct hwi_controller *phwi_ctrlr;
2863 struct hwi_wrb_context *pwrb_context;
3ec78271
JK		 2864 struct iscsi_wrb *pwrb = NULL;
2865 unsigned int num_cxn_wrbh = 0;
2866 unsigned int num_cxn_wrb = 0, j, idx = 0, index;
6733b39a
JK		 2867
2868 mem_descr_wrbh = phba->init_mem;
2869 mem_descr_wrbh += HWI_MEM_WRBH;
2870
2871 mem_descr_wrb = phba->init_mem;
2872 mem_descr_wrb += HWI_MEM_WRB;
6733b39a
JK		 2873 phwi_ctrlr = phba->phwi_ctrlr;
2874
a7909b39
JK		 2875 /* Allocate memory for WRBQ */
2876 phwi_ctxt = phwi_ctrlr->phwi_ctxt;
2877 phwi_ctxt->be_wrbq = kzalloc(sizeof(struct be_queue_info) *
843ae752 2878 phba->params.cxns_per_ctrl,
a7909b39
JK		 2879 GFP_KERNEL);
2880 if (!phwi_ctxt->be_wrbq) {
2881 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2882 "BM_%d : WRBQ Mem Alloc Failed\n");
2883 return -ENOMEM;
2884 }
2885
2886 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a 2887 pwrb_context = &phwi_ctrlr->wrb_context[index];
6733b39a
JK		 2888 pwrb_context->pwrb_handle_base =
2889 kzalloc(sizeof(struct wrb_handle *) *
2890 phba->params.wrbs_per_cxn, GFP_KERNEL);
3ec78271 2891 if (!pwrb_context->pwrb_handle_base) {
99bc5d55
JSJ		 2892 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2893 "BM_%d : Mem Alloc Failed. Failing to load\n");
3ec78271
JK		 2894 goto init_wrb_hndl_failed;
2895 }
6733b39a
JK		 2896 pwrb_context->pwrb_handle_basestd =
2897 kzalloc(sizeof(struct wrb_handle *) *
2898 phba->params.wrbs_per_cxn, GFP_KERNEL);
3ec78271 2899 if (!pwrb_context->pwrb_handle_basestd) {
99bc5d55
JSJ		 2900 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2901 "BM_%d : Mem Alloc Failed. Failing to load\n");
3ec78271
JK		 2902 goto init_wrb_hndl_failed;
2903 }
2904 if (!num_cxn_wrbh) {
2905 pwrb_handle =
2906 mem_descr_wrbh->mem_array[idx].virtual_address;
2907 num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
2908 ((sizeof(struct wrb_handle)) *
2909 phba->params.wrbs_per_cxn));
2910 idx++;
2911 }
2912 pwrb_context->alloc_index = 0;
2913 pwrb_context->wrb_handles_available = 0;
2914 pwrb_context->free_index = 0;
2915
6733b39a 2916 if (num_cxn_wrbh) {
6733b39a
JK		 2917 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2918 pwrb_context->pwrb_handle_base[j] = pwrb_handle;
2919 pwrb_context->pwrb_handle_basestd[j] =
2920 pwrb_handle;
2921 pwrb_context->wrb_handles_available++;
bfead3b2 2922 pwrb_handle->wrb_index = j;
6733b39a
JK		 2923 pwrb_handle++;
2924 }
6733b39a
JK		 2925 num_cxn_wrbh--;
2926 }
f64d92e6 2927 spin_lock_init(&pwrb_context->wrb_lock);
6733b39a
JK		 2928 }
2929 idx = 0;
a7909b39 2930 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a 2931 pwrb_context = &phwi_ctrlr->wrb_context[index];
3ec78271 2932 if (!num_cxn_wrb) {
6733b39a 2933 pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
7c56533c 2934 num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
3ec78271
JK		 2935 ((sizeof(struct iscsi_wrb) *
2936 phba->params.wrbs_per_cxn));
2937 idx++;
2938 }
2939
2940 if (num_cxn_wrb) {
6733b39a
JK		 2941 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2942 pwrb_handle = pwrb_context->pwrb_handle_base[j];
2943 pwrb_handle->pwrb = pwrb;
2944 pwrb++;
2945 }
2946 num_cxn_wrb--;
2947 }
2948 }
3ec78271
JK		 2949 return 0;
2950init_wrb_hndl_failed:
2951 for (j = index; j > 0; j--) {
2952 pwrb_context = &phwi_ctrlr->wrb_context[j];
2953 kfree(pwrb_context->pwrb_handle_base);
2954 kfree(pwrb_context->pwrb_handle_basestd);
2955 }
2956 return -ENOMEM;
6733b39a
JK		 2957}
2958
a7909b39 2959static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
6733b39a 2960{
8a86e833 2961 uint8_t ulp_num;
6733b39a
JK		 2962 struct hwi_controller *phwi_ctrlr;
2963 struct hba_parameters *p = &phba->params;
2964 struct hwi_async_pdu_context *pasync_ctx;
2965 struct async_pdu_handle *pasync_header_h, *pasync_data_h;
dc63aac6 2966 unsigned int index, idx, num_per_mem, num_async_data;
6733b39a
JK		 2967 struct be_mem_descriptor *mem_descr;
2968
8a86e833
JK		 2969 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
2970 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 2971
8a86e833
JK		 2972 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2973 mem_descr += (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
2974 (ulp_num * MEM_DESCR_OFFSET));
2975
2976 phwi_ctrlr = phba->phwi_ctrlr;
2977 phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num] =
2978 (struct hwi_async_pdu_context *)
2979 mem_descr->mem_array[0].virtual_address;
2980
2981 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
2982 memset(pasync_ctx, 0, sizeof(*pasync_ctx));
2983
2984 pasync_ctx->async_entry =
2985 (struct hwi_async_entry *)
2986 ((long unsigned int)pasync_ctx +
2987 sizeof(struct hwi_async_pdu_context));
2988
2989 pasync_ctx->num_entries = BEISCSI_GET_CID_COUNT(phba,
2990 ulp_num);
2991 pasync_ctx->buffer_size = p->defpdu_hdr_sz;
2992
2993 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2994 mem_descr += HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
2995 (ulp_num * MEM_DESCR_OFFSET);
2996 if (mem_descr->mem_array[0].virtual_address) {
2997 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2998 "BM_%d : hwi_init_async_pdu_ctx"
2999 " HWI_MEM_ASYNC_HEADER_BUF_ULP%d va=%p\n",
3000 ulp_num,
3001 mem_descr->mem_array[0].
3002 virtual_address);
3003 } else
3004 beiscsi_log(phba, KERN_WARNING,
3005 BEISCSI_LOG_INIT,
3006 "BM_%d : No Virtual address for ULP : %d\n",
3007 ulp_num);
3008
3009 pasync_ctx->async_header.va_base =
6733b39a 3010 mem_descr->mem_array[0].virtual_address;
6733b39a 3011
8a86e833
JK		 3012 pasync_ctx->async_header.pa_base.u.a64.address =
3013 mem_descr->mem_array[0].
3014 bus_address.u.a64.address;
6733b39a 3015
8a86e833
JK		 3016 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3017 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
3018 (ulp_num * MEM_DESCR_OFFSET);
3019 if (mem_descr->mem_array[0].virtual_address) {
3020 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3021 "BM_%d : hwi_init_async_pdu_ctx"
3022 " HWI_MEM_ASYNC_HEADER_RING_ULP%d va=%p\n",
3023 ulp_num,
3024 mem_descr->mem_array[0].
3025 virtual_address);
3026 } else
3027 beiscsi_log(phba, KERN_WARNING,
3028 BEISCSI_LOG_INIT,
3029 "BM_%d : No Virtual address for ULP : %d\n",
3030 ulp_num);
3031
3032 pasync_ctx->async_header.ring_base =
3033 mem_descr->mem_array[0].virtual_address;
6733b39a 3034
8a86e833
JK		 3035 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3036 mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
3037 (ulp_num * MEM_DESCR_OFFSET);
3038 if (mem_descr->mem_array[0].virtual_address) {
3039 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3040 "BM_%d : hwi_init_async_pdu_ctx"
3041 " HWI_MEM_ASYNC_HEADER_HANDLE_ULP%d va=%p\n",
3042 ulp_num,
3043 mem_descr->mem_array[0].
3044 virtual_address);
3045 } else
3046 beiscsi_log(phba, KERN_WARNING,
3047 BEISCSI_LOG_INIT,
3048 "BM_%d : No Virtual address for ULP : %d\n",
3049 ulp_num);
3050
3051 pasync_ctx->async_header.handle_base =
3052 mem_descr->mem_array[0].virtual_address;
3053 pasync_ctx->async_header.writables = 0;
3054 INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
3055
3056 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3057 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
3058 (ulp_num * MEM_DESCR_OFFSET);
3059 if (mem_descr->mem_array[0].virtual_address) {
3060 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3061 "BM_%d : hwi_init_async_pdu_ctx"
3062 " HWI_MEM_ASYNC_DATA_RING_ULP%d va=%p\n",
3063 ulp_num,
3064 mem_descr->mem_array[0].
3065 virtual_address);
3066 } else
3067 beiscsi_log(phba, KERN_WARNING,
3068 BEISCSI_LOG_INIT,
3069 "BM_%d : No Virtual address for ULP : %d\n",
3070 ulp_num);
3071
3072 pasync_ctx->async_data.ring_base =
3073 mem_descr->mem_array[0].virtual_address;
6733b39a 3074
8a86e833
JK		 3075 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3076 mem_descr += HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
3077 (ulp_num * MEM_DESCR_OFFSET);
3078 if (!mem_descr->mem_array[0].virtual_address)
3079 beiscsi_log(phba, KERN_WARNING,
3080 BEISCSI_LOG_INIT,
3081 "BM_%d : No Virtual address for ULP : %d\n",
3082 ulp_num);
99bc5d55 3083
8a86e833
JK		 3084 pasync_ctx->async_data.handle_base =
3085 mem_descr->mem_array[0].virtual_address;
3086 pasync_ctx->async_data.writables = 0;
3087 INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
3088
3089 pasync_header_h =
3090 (struct async_pdu_handle *)
3091 pasync_ctx->async_header.handle_base;
3092 pasync_data_h =
3093 (struct async_pdu_handle *)
3094 pasync_ctx->async_data.handle_base;
3095
3096 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3097 mem_descr += HWI_MEM_ASYNC_DATA_BUF_ULP0 +
3098 (ulp_num * MEM_DESCR_OFFSET);
3099 if (mem_descr->mem_array[0].virtual_address) {
3100 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3101 "BM_%d : hwi_init_async_pdu_ctx"
3102 " HWI_MEM_ASYNC_DATA_BUF_ULP%d va=%p\n",
3103 ulp_num,
3104 mem_descr->mem_array[0].
3105 virtual_address);
3106 } else
3107 beiscsi_log(phba, KERN_WARNING,
3108 BEISCSI_LOG_INIT,
3109 "BM_%d : No Virtual address for ULP : %d\n",
3110 ulp_num);
3111
3112 idx = 0;
dc63aac6
JK		 3113 pasync_ctx->async_data.va_base =
3114 mem_descr->mem_array[idx].virtual_address;
3115 pasync_ctx->async_data.pa_base.u.a64.address =
3116 mem_descr->mem_array[idx].
3117 bus_address.u.a64.address;
3118
3119 num_async_data = ((mem_descr->mem_array[idx].size) /
3120 phba->params.defpdu_data_sz);
8a86e833 3121 num_per_mem = 0;
6733b39a 3122
8a86e833
JK		 3123 for (index = 0; index < BEISCSI_GET_CID_COUNT
3124 (phba, ulp_num); index++) {
3125 pasync_header_h->cri = -1;
3126 pasync_header_h->index = (char)index;
3127 INIT_LIST_HEAD(&pasync_header_h->link);
3128 pasync_header_h->pbuffer =
3129 (void *)((unsigned long)
3130 (pasync_ctx->
3131 async_header.va_base) +
3132 (p->defpdu_hdr_sz * index));
3133
3134 pasync_header_h->pa.u.a64.address =
3135 pasync_ctx->async_header.pa_base.u.a64.
3136 address + (p->defpdu_hdr_sz * index);
3137
3138 list_add_tail(&pasync_header_h->link,
3139 &pasync_ctx->async_header.
3140 free_list);
3141 pasync_header_h++;
3142 pasync_ctx->async_header.free_entries++;
3143 pasync_ctx->async_header.writables++;
3144
3145 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
3146 wait_queue.list);
3147 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
3148 header_busy_list);
3149 pasync_data_h->cri = -1;
3150 pasync_data_h->index = (char)index;
3151 INIT_LIST_HEAD(&pasync_data_h->link);
3152
3153 if (!num_async_data) {
3154 num_per_mem = 0;
3155 idx++;
3156 pasync_ctx->async_data.va_base =
3157 mem_descr->mem_array[idx].
3158 virtual_address;
3159 pasync_ctx->async_data.pa_base.u.
3160 a64.address =
3161 mem_descr->mem_array[idx].
3162 bus_address.u.a64.address;
3163 num_async_data =
3164 ((mem_descr->mem_array[idx].
3165 size) /
3166 phba->params.defpdu_data_sz);
3167 }
3168 pasync_data_h->pbuffer =
3169 (void *)((unsigned long)
3170 (pasync_ctx->async_data.va_base) +
3171 (p->defpdu_data_sz * num_per_mem));
3172
3173 pasync_data_h->pa.u.a64.address =
3174 pasync_ctx->async_data.pa_base.u.a64.
3175 address + (p->defpdu_data_sz *
3176 num_per_mem);
3177 num_per_mem++;
3178 num_async_data--;
3179
3180 list_add_tail(&pasync_data_h->link,
3181 &pasync_ctx->async_data.
3182 free_list);
3183 pasync_data_h++;
3184 pasync_ctx->async_data.free_entries++;
3185 pasync_ctx->async_data.writables++;
3186
3187 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
3188 data_busy_list);
3189 }
6733b39a 3190
8a86e833
JK		 3191 pasync_ctx->async_header.host_write_ptr = 0;
3192 pasync_ctx->async_header.ep_read_ptr = -1;
3193 pasync_ctx->async_data.host_write_ptr = 0;
3194 pasync_ctx->async_data.ep_read_ptr = -1;
3195 }
6733b39a
JK		 3196 }
3197
a7909b39 3198 return 0;
6733b39a
JK		 3199}
3200
3201static int
3202be_sgl_create_contiguous(void *virtual_address,
3203 u64 physical_address, u32 length,
3204 struct be_dma_mem *sgl)
3205{
3206 WARN_ON(!virtual_address);
3207 WARN_ON(!physical_address);
dd29dae0 3208 WARN_ON(!length);
6733b39a
JK		 3209 WARN_ON(!sgl);
3210
3211 sgl->va = virtual_address;
457ff3b7 3212 sgl->dma = (unsigned long)physical_address;
6733b39a
JK		 3213 sgl->size = length;
3214
3215 return 0;
3216}
3217
3218static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
3219{
3220 memset(sgl, 0, sizeof(*sgl));
3221}
3222
3223static void
3224hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
3225 struct mem_array *pmem, struct be_dma_mem *sgl)
3226{
3227 if (sgl->va)
3228 be_sgl_destroy_contiguous(sgl);
3229
3230 be_sgl_create_contiguous(pmem->virtual_address,
3231 pmem->bus_address.u.a64.address,
3232 pmem->size, sgl);
3233}
3234
3235static void
3236hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
3237 struct mem_array *pmem, struct be_dma_mem *sgl)
3238{
3239 if (sgl->va)
3240 be_sgl_destroy_contiguous(sgl);
3241
3242 be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
3243 pmem->bus_address.u.a64.address,
3244 pmem->size, sgl);
3245}
3246
3247static int be_fill_queue(struct be_queue_info *q,
3248 u16 len, u16 entry_size, void *vaddress)
3249{
3250 struct be_dma_mem *mem = &q->dma_mem;
3251
3252 memset(q, 0, sizeof(*q));
3253 q->len = len;
3254 q->entry_size = entry_size;
3255 mem->size = len * entry_size;
3256 mem->va = vaddress;
3257 if (!mem->va)
3258 return -ENOMEM;
3259 memset(mem->va, 0, mem->size);
3260 return 0;
3261}
3262
bfead3b2 3263static int beiscsi_create_eqs(struct beiscsi_hba *phba,
6733b39a
JK		 3264 struct hwi_context_memory *phwi_context)
3265{
bfead3b2 3266 unsigned int i, num_eq_pages;
99bc5d55 3267 int ret = 0, eq_for_mcc;
6733b39a
JK		 3268 struct be_queue_info *eq;
3269 struct be_dma_mem *mem;
6733b39a 3270 void *eq_vaddress;
bfead3b2 3271 dma_addr_t paddr;
6733b39a 3272
bfead3b2
JK		 3273 num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
3274 sizeof(struct be_eq_entry));
6733b39a 3275
bfead3b2
JK		 3276 if (phba->msix_enabled)
3277 eq_for_mcc = 1;
3278 else
3279 eq_for_mcc = 0;
3280 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
3281 eq = &phwi_context->be_eq[i].q;
3282 mem = &eq->dma_mem;
3283 phwi_context->be_eq[i].phba = phba;
3284 eq_vaddress = pci_alloc_consistent(phba->pcidev,
3285 num_eq_pages * PAGE_SIZE,
3286 &paddr);
3287 if (!eq_vaddress)
3288 goto create_eq_error;
3289
3290 mem->va = eq_vaddress;
3291 ret = be_fill_queue(eq, phba->params.num_eq_entries,
3292 sizeof(struct be_eq_entry), eq_vaddress);
3293 if (ret) {
99bc5d55
JSJ		 3294 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3295 "BM_%d : be_fill_queue Failed for EQ\n");
bfead3b2
JK		 3296 goto create_eq_error;
3297 }
6733b39a 3298
bfead3b2
JK		 3299 mem->dma = paddr;
3300 ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
3301 phwi_context->cur_eqd);
3302 if (ret) {
99bc5d55
JSJ		 3303 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3304 "BM_%d : beiscsi_cmd_eq_create"
3305 "Failed for EQ\n");
bfead3b2
JK		 3306 goto create_eq_error;
3307 }
99bc5d55
JSJ		 3308
3309 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3310 "BM_%d : eqid = %d\n",
3311 phwi_context->be_eq[i].q.id);
6733b39a 3312 }
6733b39a 3313 return 0;
bfead3b2 3314create_eq_error:
107dfcba 3315 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
bfead3b2
JK		 3316 eq = &phwi_context->be_eq[i].q;
3317 mem = &eq->dma_mem;
3318 if (mem->va)
3319 pci_free_consistent(phba->pcidev, num_eq_pages
3320 * PAGE_SIZE,
3321 mem->va, mem->dma);
3322 }
3323 return ret;
6733b39a
JK		 3324}
3325
bfead3b2 3326static int beiscsi_create_cqs(struct beiscsi_hba *phba,
6733b39a
JK		 3327 struct hwi_context_memory *phwi_context)
3328{
bfead3b2 3329 unsigned int i, num_cq_pages;
99bc5d55 3330 int ret = 0;
6733b39a
JK		 3331 struct be_queue_info *cq, *eq;
3332 struct be_dma_mem *mem;
bfead3b2 3333 struct be_eq_obj *pbe_eq;
6733b39a 3334 void *cq_vaddress;
bfead3b2 3335 dma_addr_t paddr;
6733b39a 3336
bfead3b2
JK		 3337 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
3338 sizeof(struct sol_cqe));
6733b39a 3339
bfead3b2
JK		 3340 for (i = 0; i < phba->num_cpus; i++) {
3341 cq = &phwi_context->be_cq[i];
3342 eq = &phwi_context->be_eq[i].q;
3343 pbe_eq = &phwi_context->be_eq[i];
3344 pbe_eq->cq = cq;
3345 pbe_eq->phba = phba;
3346 mem = &cq->dma_mem;
3347 cq_vaddress = pci_alloc_consistent(phba->pcidev,
3348 num_cq_pages * PAGE_SIZE,
3349 &paddr);
3350 if (!cq_vaddress)
3351 goto create_cq_error;
7da50879 3352 ret = be_fill_queue(cq, phba->params.num_cq_entries,
bfead3b2
JK		 3353 sizeof(struct sol_cqe), cq_vaddress);
3354 if (ret) {
99bc5d55
JSJ		 3355 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3356 "BM_%d : be_fill_queue Failed "
3357 "for ISCSI CQ\n");
bfead3b2
JK		 3358 goto create_cq_error;
3359 }
3360
3361 mem->dma = paddr;
3362 ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
3363 false, 0);
3364 if (ret) {
99bc5d55
JSJ		 3365 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3366 "BM_%d : beiscsi_cmd_eq_create"
3367 "Failed for ISCSI CQ\n");
bfead3b2
JK		 3368 goto create_cq_error;
3369 }
99bc5d55
JSJ		 3370 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3371 "BM_%d : iscsi cq_id is %d for eq_id %d\n"
3372 "iSCSI CQ CREATED\n", cq->id, eq->id);
6733b39a 3373 }
6733b39a 3374 return 0;
bfead3b2
JK		 3375
3376create_cq_error:
3377 for (i = 0; i < phba->num_cpus; i++) {
3378 cq = &phwi_context->be_cq[i];
3379 mem = &cq->dma_mem;
3380 if (mem->va)
3381 pci_free_consistent(phba->pcidev, num_cq_pages
3382 * PAGE_SIZE,
3383 mem->va, mem->dma);
3384 }
3385 return ret;
3386
6733b39a
JK		 3387}
3388
3389static int
3390beiscsi_create_def_hdr(struct beiscsi_hba *phba,
3391 struct hwi_context_memory *phwi_context,
3392 struct hwi_controller *phwi_ctrlr,
8a86e833 3393 unsigned int def_pdu_ring_sz, uint8_t ulp_num)
6733b39a
JK		 3394{
3395 unsigned int idx;
3396 int ret;
3397 struct be_queue_info *dq, *cq;
3398 struct be_dma_mem *mem;
3399 struct be_mem_descriptor *mem_descr;
3400 void *dq_vaddress;
3401
3402 idx = 0;
8a86e833 3403 dq = &phwi_context->be_def_hdrq[ulp_num];
bfead3b2 3404 cq = &phwi_context->be_cq[0];
6733b39a
JK		 3405 mem = &dq->dma_mem;
3406 mem_descr = phba->init_mem;
8a86e833
JK		 3407 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
3408 (ulp_num * MEM_DESCR_OFFSET);
6733b39a
JK		 3409 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
3410 ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
3411 sizeof(struct phys_addr),
3412 sizeof(struct phys_addr), dq_vaddress);
3413 if (ret) {
99bc5d55 3414 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3415 "BM_%d : be_fill_queue Failed for DEF PDU HDR on ULP : %d\n",
3416 ulp_num);
3417
6733b39a
JK		 3418 return ret;
3419 }
457ff3b7
JK		 3420 mem->dma = (unsigned long)mem_descr->mem_array[idx].
3421 bus_address.u.a64.address;
6733b39a
JK		 3422 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
3423 def_pdu_ring_sz,
8a86e833
JK		 3424 phba->params.defpdu_hdr_sz,
3425 BEISCSI_DEFQ_HDR, ulp_num);
6733b39a 3426 if (ret) {
99bc5d55 3427 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3428 "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR on ULP : %d\n",
3429 ulp_num);
3430
6733b39a
JK		 3431 return ret;
3432 }
99bc5d55 3433
8a86e833
JK		 3434 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3435 "BM_%d : iscsi hdr def pdu id for ULP : %d is %d\n",
3436 ulp_num,
3437 phwi_context->be_def_hdrq[ulp_num].id);
3438 hwi_post_async_buffers(phba, BEISCSI_DEFQ_HDR, ulp_num);
6733b39a
JK		 3439 return 0;
3440}
3441
3442static int
3443beiscsi_create_def_data(struct beiscsi_hba *phba,
3444 struct hwi_context_memory *phwi_context,
3445 struct hwi_controller *phwi_ctrlr,
8a86e833 3446 unsigned int def_pdu_ring_sz, uint8_t ulp_num)
6733b39a
JK		 3447{
3448 unsigned int idx;
3449 int ret;
3450 struct be_queue_info *dataq, *cq;
3451 struct be_dma_mem *mem;
3452 struct be_mem_descriptor *mem_descr;
3453 void *dq_vaddress;
3454
3455 idx = 0;
8a86e833 3456 dataq = &phwi_context->be_def_dataq[ulp_num];
bfead3b2 3457 cq = &phwi_context->be_cq[0];
6733b39a
JK		 3458 mem = &dataq->dma_mem;
3459 mem_descr = phba->init_mem;
8a86e833
JK		 3460 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
3461 (ulp_num * MEM_DESCR_OFFSET);
6733b39a
JK		 3462 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
3463 ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
3464 sizeof(struct phys_addr),
3465 sizeof(struct phys_addr), dq_vaddress);
3466 if (ret) {
99bc5d55 3467 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3468 "BM_%d : be_fill_queue Failed for DEF PDU "
3469 "DATA on ULP : %d\n",
3470 ulp_num);
3471
6733b39a
JK		 3472 return ret;
3473 }
457ff3b7
JK		 3474 mem->dma = (unsigned long)mem_descr->mem_array[idx].
3475 bus_address.u.a64.address;
6733b39a
JK		 3476 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
3477 def_pdu_ring_sz,
8a86e833
JK		 3478 phba->params.defpdu_data_sz,
3479 BEISCSI_DEFQ_DATA, ulp_num);
6733b39a 3480 if (ret) {
99bc5d55
JSJ		 3481 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3482 "BM_%d be_cmd_create_default_pdu_queue"
8a86e833
JK		 3483 " Failed for DEF PDU DATA on ULP : %d\n",
3484 ulp_num);
6733b39a
JK		 3485 return ret;
3486 }
8a86e833 3487
99bc5d55 3488 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
8a86e833
JK		 3489 "BM_%d : iscsi def data id on ULP : %d is %d\n",
3490 ulp_num,
3491 phwi_context->be_def_dataq[ulp_num].id);
99bc5d55 3492
8a86e833 3493 hwi_post_async_buffers(phba, BEISCSI_DEFQ_DATA, ulp_num);
99bc5d55 3494 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
8a86e833
JK		 3495 "BM_%d : DEFAULT PDU DATA RING CREATED"
3496 "on ULP : %d\n", ulp_num);
99bc5d55 3497
6733b39a
JK		 3498 return 0;
3499}
3500
15a90fe0
JK		 3501
3502static int
3503beiscsi_post_template_hdr(struct beiscsi_hba *phba)
3504{
3505 struct be_mem_descriptor *mem_descr;
3506 struct mem_array *pm_arr;
3507 struct be_dma_mem sgl;
a129d92f 3508 int status, ulp_num;
15a90fe0 3509
a129d92f
JK		 3510 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3511 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3512 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3513 mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 +
3514 (ulp_num * MEM_DESCR_OFFSET);
3515 pm_arr = mem_descr->mem_array;
15a90fe0 3516
a129d92f
JK		 3517 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
3518 status = be_cmd_iscsi_post_template_hdr(
3519 &phba->ctrl, &sgl);
15a90fe0 3520
a129d92f
JK		 3521 if (status != 0) {
3522 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3523 "BM_%d : Post Template HDR Failed for"
3524 "ULP_%d\n", ulp_num);
3525 return status;
3526 }
3527
3528 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3529 "BM_%d : Template HDR Pages Posted for"
3530 "ULP_%d\n", ulp_num);
15a90fe0
JK		 3531 }
3532 }
15a90fe0
JK		 3533 return 0;
3534}
3535
6733b39a
JK		 3536static int
3537beiscsi_post_pages(struct beiscsi_hba *phba)
3538{
3539 struct be_mem_descriptor *mem_descr;
3540 struct mem_array *pm_arr;
3541 unsigned int page_offset, i;
3542 struct be_dma_mem sgl;
843ae752 3543 int status, ulp_num = 0;
6733b39a
JK		 3544
3545 mem_descr = phba->init_mem;
3546 mem_descr += HWI_MEM_SGE;
3547 pm_arr = mem_descr->mem_array;
3548
90622db3
JK		 3549 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3550 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
3551 break;
3552
6733b39a 3553 page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
843ae752 3554 phba->fw_config.iscsi_icd_start[ulp_num]) / PAGE_SIZE;
6733b39a
JK		 3555 for (i = 0; i < mem_descr->num_elements; i++) {
3556 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
3557 status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
3558 page_offset,
3559 (pm_arr->size / PAGE_SIZE));
3560 page_offset += pm_arr->size / PAGE_SIZE;
3561 if (status != 0) {
99bc5d55
JSJ		 3562 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3563 "BM_%d : post sgl failed.\n");
6733b39a
JK		 3564 return status;
3565 }
3566 pm_arr++;
3567 }
99bc5d55
JSJ		 3568 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3569 "BM_%d : POSTED PAGES\n");
6733b39a
JK		 3570 return 0;
3571}
3572
bfead3b2
JK		 3573static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
3574{
3575 struct be_dma_mem *mem = &q->dma_mem;
c8b25598 3576 if (mem->va) {
bfead3b2
JK		 3577 pci_free_consistent(phba->pcidev, mem->size,
3578 mem->va, mem->dma);
c8b25598
JK		 3579 mem->va = NULL;
3580 }
bfead3b2
JK		 3581}
3582
3583static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
3584 u16 len, u16 entry_size)
3585{
3586 struct be_dma_mem *mem = &q->dma_mem;
3587
3588 memset(q, 0, sizeof(*q));
3589 q->len = len;
3590 q->entry_size = entry_size;
3591 mem->size = len * entry_size;
7c845eb5 3592 mem->va = pci_zalloc_consistent(phba->pcidev, mem->size, &mem->dma);
bfead3b2 3593 if (!mem->va)
d3ad2bb3 3594 return -ENOMEM;
bfead3b2
JK		 3595 return 0;
3596}
3597
6733b39a
JK		 3598static int
3599beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
3600 struct hwi_context_memory *phwi_context,
3601 struct hwi_controller *phwi_ctrlr)
3602{
3603 unsigned int wrb_mem_index, offset, size, num_wrb_rings;
3604 u64 pa_addr_lo;
4eea99d5 3605 unsigned int idx, num, i, ulp_num;
6733b39a
JK		 3606 struct mem_array *pwrb_arr;
3607 void *wrb_vaddr;
3608 struct be_dma_mem sgl;
3609 struct be_mem_descriptor *mem_descr;
a7909b39 3610 struct hwi_wrb_context *pwrb_context;
6733b39a 3611 int status;
4eea99d5
JK		 3612 uint8_t ulp_count = 0, ulp_base_num = 0;
3613 uint16_t cid_count_ulp[BEISCSI_ULP_COUNT] = { 0 };
6733b39a
JK		 3614
3615 idx = 0;
3616 mem_descr = phba->init_mem;
3617 mem_descr += HWI_MEM_WRB;
3618 pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
3619 GFP_KERNEL);
3620 if (!pwrb_arr) {
99bc5d55
JSJ		 3621 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3622 "BM_%d : Memory alloc failed in create wrb ring.\n");
6733b39a
JK		 3623 return -ENOMEM;
3624 }
3625 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
3626 pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
3627 num_wrb_rings = mem_descr->mem_array[idx].size /
3628 (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
3629
3630 for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
3631 if (num_wrb_rings) {
3632 pwrb_arr[num].virtual_address = wrb_vaddr;
3633 pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
3634 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
3635 sizeof(struct iscsi_wrb);
3636 wrb_vaddr += pwrb_arr[num].size;
3637 pa_addr_lo += pwrb_arr[num].size;
3638 num_wrb_rings--;
3639 } else {
3640 idx++;
3641 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
3642 pa_addr_lo = mem_descr->mem_array[idx].\
3643 bus_address.u.a64.address;
3644 num_wrb_rings = mem_descr->mem_array[idx].size /
3645 (phba->params.wrbs_per_cxn *
3646 sizeof(struct iscsi_wrb));
3647 pwrb_arr[num].virtual_address = wrb_vaddr;
3648 pwrb_arr[num].bus_address.u.a64.address\
3649 = pa_addr_lo;
3650 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
3651 sizeof(struct iscsi_wrb);
3652 wrb_vaddr += pwrb_arr[num].size;
3653 pa_addr_lo += pwrb_arr[num].size;
3654 num_wrb_rings--;
3655 }
3656 }
4eea99d5
JK		 3657
3658 /* Get the ULP Count */
3659 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3660 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3661 ulp_count++;
3662 ulp_base_num = ulp_num;
3663 cid_count_ulp[ulp_num] =
3664 BEISCSI_GET_CID_COUNT(phba, ulp_num);
3665 }
3666
6733b39a
JK		 3667 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3668 wrb_mem_index = 0;
3669 offset = 0;
3670 size = 0;
3671
4eea99d5
JK		 3672 if (ulp_count > 1) {
3673 ulp_base_num = (ulp_base_num + 1) % BEISCSI_ULP_COUNT;
3674
3675 if (!cid_count_ulp[ulp_base_num])
3676 ulp_base_num = (ulp_base_num + 1) %
3677 BEISCSI_ULP_COUNT;
3678
3679 cid_count_ulp[ulp_base_num]--;
3680 }
3681
3682
6733b39a
JK		 3683 hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
3684 status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
4eea99d5
JK		 3685 &phwi_context->be_wrbq[i],
3686 &phwi_ctrlr->wrb_context[i],
3687 ulp_base_num);
6733b39a 3688 if (status != 0) {
99bc5d55
JSJ		 3689 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3690 "BM_%d : wrbq create failed.");
1462b8ff 3691 kfree(pwrb_arr);
6733b39a
JK		 3692 return status;
3693 }
a7909b39 3694 pwrb_context = &phwi_ctrlr->wrb_context[i];
a7909b39 3695 BE_SET_CID_TO_CRI(i, pwrb_context->cid);
6733b39a
JK		 3696 }
3697 kfree(pwrb_arr);
3698 return 0;
3699}
3700
3701static void free_wrb_handles(struct beiscsi_hba *phba)
3702{
3703 unsigned int index;
3704 struct hwi_controller *phwi_ctrlr;
3705 struct hwi_wrb_context *pwrb_context;
3706
3707 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 3708 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a
JK		 3709 pwrb_context = &phwi_ctrlr->wrb_context[index];
3710 kfree(pwrb_context->pwrb_handle_base);
3711 kfree(pwrb_context->pwrb_handle_basestd);
3712 }
3713}
3714
bfead3b2
JK		 3715static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
3716{
3717 struct be_queue_info *q;
3718 struct be_ctrl_info *ctrl = &phba->ctrl;
3719
3720 q = &phba->ctrl.mcc_obj.q;
4e2bdf7a 3721 if (q->created) {
bfead3b2 3722 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
4e2bdf7a
JSJ		 3723 be_queue_free(phba, q);
3724 }
bfead3b2
JK		 3725
3726 q = &phba->ctrl.mcc_obj.cq;
4e2bdf7a 3727 if (q->created) {
bfead3b2 3728 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
4e2bdf7a
JSJ		 3729 be_queue_free(phba, q);
3730 }
bfead3b2
JK		 3731}
3732
6733b39a
JK		 3733static void hwi_cleanup(struct beiscsi_hba *phba)
3734{
3735 struct be_queue_info *q;
3736 struct be_ctrl_info *ctrl = &phba->ctrl;
3737 struct hwi_controller *phwi_ctrlr;
3738 struct hwi_context_memory *phwi_context;
a7909b39 3739 struct hwi_async_pdu_context *pasync_ctx;
23188167 3740 int i, eq_for_mcc, ulp_num;
6733b39a
JK		 3741
3742 phwi_ctrlr = phba->phwi_ctrlr;
3743 phwi_context = phwi_ctrlr->phwi_ctxt;
15a90fe0
JK		 3744
3745 be_cmd_iscsi_remove_template_hdr(ctrl);
3746
6733b39a
JK		 3747 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3748 q = &phwi_context->be_wrbq[i];
3749 if (q->created)
3750 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
3751 }
a7909b39 3752 kfree(phwi_context->be_wrbq);
6733b39a
JK		 3753 free_wrb_handles(phba);
3754
8a86e833
JK		 3755 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3756 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 3757
8a86e833
JK		 3758 q = &phwi_context->be_def_hdrq[ulp_num];
3759 if (q->created)
3760 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3761
3762 q = &phwi_context->be_def_dataq[ulp_num];
3763 if (q->created)
3764 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3765
3766 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
3767 }
3768 }
6733b39a
JK		 3769
3770 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
3771
bfead3b2
JK		 3772 for (i = 0; i < (phba->num_cpus); i++) {
3773 q = &phwi_context->be_cq[i];
4e2bdf7a
JSJ		 3774 if (q->created) {
3775 be_queue_free(phba, q);
bfead3b2 3776 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
4e2bdf7a 3777 }
bfead3b2 3778 }
23188167
JK		 3779
3780 be_mcc_queues_destroy(phba);
bfead3b2 3781 if (phba->msix_enabled)
23188167 3782 eq_for_mcc = 1;
bfead3b2 3783 else
23188167
JK		 3784 eq_for_mcc = 0;
3785 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
bfead3b2 3786 q = &phwi_context->be_eq[i].q;
4e2bdf7a
JSJ		 3787 if (q->created) {
3788 be_queue_free(phba, q);
bfead3b2 3789 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
4e2bdf7a 3790 }
bfead3b2 3791 }
0283fbb1 3792 be_cmd_fw_uninit(ctrl);
bfead3b2 3793}
6733b39a 3794
bfead3b2
JK		 3795static int be_mcc_queues_create(struct beiscsi_hba *phba,
3796 struct hwi_context_memory *phwi_context)
3797{
3798 struct be_queue_info *q, *cq;
3799 struct be_ctrl_info *ctrl = &phba->ctrl;
3800
3801 /* Alloc MCC compl queue */
3802 cq = &phba->ctrl.mcc_obj.cq;
3803 if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
3804 sizeof(struct be_mcc_compl)))
3805 goto err;
3806 /* Ask BE to create MCC compl queue; */
3807 if (phba->msix_enabled) {
3808 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
3809 [phba->num_cpus].q, false, true, 0))
3810 goto mcc_cq_free;
3811 } else {
3812 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
3813 false, true, 0))
3814 goto mcc_cq_free;
3815 }
3816
3817 /* Alloc MCC queue */
3818 q = &phba->ctrl.mcc_obj.q;
3819 if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
3820 goto mcc_cq_destroy;
3821
3822 /* Ask BE to create MCC queue */
35e66019 3823 if (beiscsi_cmd_mccq_create(phba, q, cq))
bfead3b2
JK		 3824 goto mcc_q_free;
3825
3826 return 0;
3827
3828mcc_q_free:
3829 be_queue_free(phba, q);
3830mcc_cq_destroy:
3831 beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
3832mcc_cq_free:
3833 be_queue_free(phba, cq);
3834err:
d3ad2bb3 3835 return -ENOMEM;
bfead3b2
JK		 3836}
3837
107dfcba
JSJ		 3838/**
3839 * find_num_cpus()- Get the CPU online count
3840 * @phba: ptr to priv structure
3841 *
3842 * CPU count is used for creating EQ.
3843 **/
3844static void find_num_cpus(struct beiscsi_hba *phba)
bfead3b2
JK		 3845{
3846 int num_cpus = 0;
3847
3848 num_cpus = num_online_cpus();
bfead3b2 3849
22abeef0
JSJ		 3850 switch (phba->generation) {
3851 case BE_GEN2:
3852 case BE_GEN3:
3853 phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ?
3854 BEISCSI_MAX_NUM_CPUS : num_cpus;
3855 break;
3856 case BE_GEN4:
68c26a3a
JK		 3857 /*
3858 * If eqid_count == 1 fall back to
3859 * INTX mechanism
3860 **/
3861 if (phba->fw_config.eqid_count == 1) {
3862 enable_msix = 0;
3863 phba->num_cpus = 1;
3864 return;
3865 }
3866
3867 phba->num_cpus =
3868 (num_cpus > (phba->fw_config.eqid_count - 1)) ?
3869 (phba->fw_config.eqid_count - 1) : num_cpus;
22abeef0
JSJ		 3870 break;
3871 default:
3872 phba->num_cpus = 1;
3873 }
6733b39a
JK		 3874}
3875
3876static int hwi_init_port(struct beiscsi_hba *phba)
3877{
3878 struct hwi_controller *phwi_ctrlr;
3879 struct hwi_context_memory *phwi_context;
3880 unsigned int def_pdu_ring_sz;
3881 struct be_ctrl_info *ctrl = &phba->ctrl;
8a86e833 3882 int status, ulp_num;
6733b39a 3883
6733b39a 3884 phwi_ctrlr = phba->phwi_ctrlr;
6733b39a 3885 phwi_context = phwi_ctrlr->phwi_ctxt;
73af08e1 3886 phwi_context->max_eqd = 128;
bfead3b2 3887 phwi_context->min_eqd = 0;
73af08e1 3888 phwi_context->cur_eqd = 0;
6733b39a 3889 be_cmd_fw_initialize(&phba->ctrl);
53aefe25
JB		 3890 /* set optic state to unknown */
3891 phba->optic_state = 0xff;
bfead3b2
JK		 3892
3893 status = beiscsi_create_eqs(phba, phwi_context);
6733b39a 3894 if (status != 0) {
99bc5d55
JSJ		 3895 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3896 "BM_%d : EQ not created\n");
6733b39a
JK		 3897 goto error;
3898 }
3899
bfead3b2
JK		 3900 status = be_mcc_queues_create(phba, phwi_context);
3901 if (status != 0)
3902 goto error;
3903
3904 status = mgmt_check_supported_fw(ctrl, phba);
6733b39a 3905 if (status != 0) {
99bc5d55
JSJ		 3906 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3907 "BM_%d : Unsupported fw version\n");
6733b39a
JK		 3908 goto error;
3909 }
3910
bfead3b2 3911 status = beiscsi_create_cqs(phba, phwi_context);
6733b39a 3912 if (status != 0) {
99bc5d55
JSJ		 3913 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3914 "BM_%d : CQ not created\n");
6733b39a
JK		 3915 goto error;
3916 }
3917
8a86e833
JK		 3918 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3919 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 3920
8a86e833
JK		 3921 def_pdu_ring_sz =
3922 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
3923 sizeof(struct phys_addr);
3924
3925 status = beiscsi_create_def_hdr(phba, phwi_context,
3926 phwi_ctrlr,
3927 def_pdu_ring_sz,
3928 ulp_num);
3929 if (status != 0) {
3930 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3931 "BM_%d : Default Header not created for ULP : %d\n",
3932 ulp_num);
3933 goto error;
3934 }
3935
3936 status = beiscsi_create_def_data(phba, phwi_context,
3937 phwi_ctrlr,
3938 def_pdu_ring_sz,
3939 ulp_num);
3940 if (status != 0) {
3941 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3942 "BM_%d : Default Data not created for ULP : %d\n",
3943 ulp_num);
3944 goto error;
3945 }
3946 }
6733b39a
JK		 3947 }
3948
3949 status = beiscsi_post_pages(phba);
3950 if (status != 0) {
99bc5d55
JSJ		 3951 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3952 "BM_%d : Post SGL Pages Failed\n");
6733b39a
JK		 3953 goto error;
3954 }
3955
15a90fe0
JK		 3956 status = beiscsi_post_template_hdr(phba);
3957 if (status != 0) {
3958 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3959 "BM_%d : Template HDR Posting for CXN Failed\n");
3960 }
3961
6733b39a
JK		 3962 status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
3963 if (status != 0) {
99bc5d55
JSJ		 3964 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3965 "BM_%d : WRB Rings not created\n");
6733b39a
JK		 3966 goto error;
3967 }
3968
8a86e833
JK		 3969 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3970 uint16_t async_arr_idx = 0;
3971
3972 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3973 uint16_t cri = 0;
3974 struct hwi_async_pdu_context *pasync_ctx;
3975
3976 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(
3977 phwi_ctrlr, ulp_num);
3978 for (cri = 0; cri <
3979 phba->params.cxns_per_ctrl; cri++) {
3980 if (ulp_num == BEISCSI_GET_ULP_FROM_CRI
3981 (phwi_ctrlr, cri))
3982 pasync_ctx->cid_to_async_cri_map[
3983 phwi_ctrlr->wrb_context[cri].cid] =
3984 async_arr_idx++;
3985 }
3986 }
3987 }
3988
99bc5d55
JSJ		 3989 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3990 "BM_%d : hwi_init_port success\n");
6733b39a
JK		 3991 return 0;
3992
3993error:
99bc5d55
JSJ		 3994 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3995 "BM_%d : hwi_init_port failed");
6733b39a 3996 hwi_cleanup(phba);
a49e06d5 3997 return status;
6733b39a
JK		 3998}
3999
6733b39a
JK		 4000static int hwi_init_controller(struct beiscsi_hba *phba)
4001{
4002 struct hwi_controller *phwi_ctrlr;
4003
4004 phwi_ctrlr = phba->phwi_ctrlr;
4005 if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
4006 phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
4007 init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
99bc5d55
JSJ		 4008 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4009 "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
4010 phwi_ctrlr->phwi_ctxt);
6733b39a 4011 } else {
99bc5d55
JSJ		 4012 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4013 "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
4014 "than one element.Failing to load\n");
6733b39a
JK		 4015 return -ENOMEM;
4016 }
4017
4018 iscsi_init_global_templates(phba);
3ec78271
JK		 4019 if (beiscsi_init_wrb_handle(phba))
4020 return -ENOMEM;
4021
a7909b39
JK		 4022 if (hwi_init_async_pdu_ctx(phba)) {
4023 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4024 "BM_%d : hwi_init_async_pdu_ctx failed\n");
4025 return -ENOMEM;
4026 }
4027
6733b39a 4028 if (hwi_init_port(phba) != 0) {
99bc5d55
JSJ		 4029 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4030 "BM_%d : hwi_init_controller failed\n");
4031
6733b39a
JK		 4032 return -ENOMEM;
4033 }
4034 return 0;
4035}
4036
4037static void beiscsi_free_mem(struct beiscsi_hba *phba)
4038{
4039 struct be_mem_descriptor *mem_descr;
4040 int i, j;
4041
4042 mem_descr = phba->init_mem;
4043 i = 0;
4044 j = 0;
4045 for (i = 0; i < SE_MEM_MAX; i++) {
4046 for (j = mem_descr->num_elements; j > 0; j--) {
4047 pci_free_consistent(phba->pcidev,
4048 mem_descr->mem_array[j - 1].size,
4049 mem_descr->mem_array[j - 1].virtual_address,
457ff3b7
JK		 4050 (unsigned long)mem_descr->mem_array[j - 1].
4051 bus_address.u.a64.address);
6733b39a 4052 }
8a86e833 4053
6733b39a
JK		 4054 kfree(mem_descr->mem_array);
4055 mem_descr++;
4056 }
4057 kfree(phba->init_mem);
a7909b39 4058 kfree(phba->phwi_ctrlr->wrb_context);
6733b39a
JK		 4059 kfree(phba->phwi_ctrlr);
4060}
4061
4062static int beiscsi_init_controller(struct beiscsi_hba *phba)
4063{
4064 int ret = -ENOMEM;
4065
4066 ret = beiscsi_get_memory(phba);
4067 if (ret < 0) {
99bc5d55
JSJ		 4068 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4069 "BM_%d : beiscsi_dev_probe -"
4070 "Failed in beiscsi_alloc_memory\n");
6733b39a
JK		 4071 return ret;
4072 }
4073
4074 ret = hwi_init_controller(phba);
4075 if (ret)
4076 goto free_init;
99bc5d55
JSJ		 4077 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4078 "BM_%d : Return success from beiscsi_init_controller");
4079
6733b39a
JK		 4080 return 0;
4081
4082free_init:
4083 beiscsi_free_mem(phba);
a49e06d5 4084 return ret;
6733b39a
JK		 4085}
4086
4087static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
4088{
4089 struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
4090 struct sgl_handle *psgl_handle;
4091 struct iscsi_sge *pfrag;
90622db3
JK		 4092 unsigned int arr_index, i, idx;
4093 unsigned int ulp_icd_start, ulp_num = 0;
6733b39a
JK		 4094
4095 phba->io_sgl_hndl_avbl = 0;
4096 phba->eh_sgl_hndl_avbl = 0;
bfead3b2 4097
6733b39a
JK		 4098 mem_descr_sglh = phba->init_mem;
4099 mem_descr_sglh += HWI_MEM_SGLH;
4100 if (1 == mem_descr_sglh->num_elements) {
4101 phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
4102 phba->params.ios_per_ctrl,
4103 GFP_KERNEL);
4104 if (!phba->io_sgl_hndl_base) {
99bc5d55
JSJ		 4105 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4106 "BM_%d : Mem Alloc Failed. Failing to load\n");
6733b39a
JK		 4107 return -ENOMEM;
4108 }
4109 phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
4110 (phba->params.icds_per_ctrl -
4111 phba->params.ios_per_ctrl),
4112 GFP_KERNEL);
4113 if (!phba->eh_sgl_hndl_base) {
4114 kfree(phba->io_sgl_hndl_base);
99bc5d55
JSJ		 4115 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4116 "BM_%d : Mem Alloc Failed. Failing to load\n");
6733b39a
JK		 4117 return -ENOMEM;
4118 }
4119 } else {
99bc5d55
JSJ		 4120 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4121 "BM_%d : HWI_MEM_SGLH is more than one element."
4122 "Failing to load\n");
6733b39a
JK		 4123 return -ENOMEM;
4124 }
4125
4126 arr_index = 0;
4127 idx = 0;
4128 while (idx < mem_descr_sglh->num_elements) {
4129 psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
4130
4131 for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
4132 sizeof(struct sgl_handle)); i++) {
4133 if (arr_index < phba->params.ios_per_ctrl) {
4134 phba->io_sgl_hndl_base[arr_index] = psgl_handle;
4135 phba->io_sgl_hndl_avbl++;
4136 arr_index++;
4137 } else {
4138 phba->eh_sgl_hndl_base[arr_index -
4139 phba->params.ios_per_ctrl] =
4140 psgl_handle;
4141 arr_index++;
4142 phba->eh_sgl_hndl_avbl++;
4143 }
4144 psgl_handle++;
4145 }
4146 idx++;
4147 }
99bc5d55
JSJ		 4148 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4149 "BM_%d : phba->io_sgl_hndl_avbl=%d"
4150 "phba->eh_sgl_hndl_avbl=%d\n",
4151 phba->io_sgl_hndl_avbl,
4152 phba->eh_sgl_hndl_avbl);
4153
6733b39a
JK		 4154 mem_descr_sg = phba->init_mem;
4155 mem_descr_sg += HWI_MEM_SGE;
99bc5d55
JSJ		 4156 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4157 "\n BM_%d : mem_descr_sg->num_elements=%d\n",
4158 mem_descr_sg->num_elements);
4159
90622db3
JK		 4160 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
4161 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
4162 break;
4163
4164 ulp_icd_start = phba->fw_config.iscsi_icd_start[ulp_num];
4165
6733b39a
JK		 4166 arr_index = 0;
4167 idx = 0;
4168 while (idx < mem_descr_sg->num_elements) {
4169 pfrag = mem_descr_sg->mem_array[idx].virtual_address;
4170
4171 for (i = 0;
4172 i < (mem_descr_sg->mem_array[idx].size) /
4173 (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
4174 i++) {
4175 if (arr_index < phba->params.ios_per_ctrl)
4176 psgl_handle = phba->io_sgl_hndl_base[arr_index];
4177 else
4178 psgl_handle = phba->eh_sgl_hndl_base[arr_index -
4179 phba->params.ios_per_ctrl];
4180 psgl_handle->pfrag = pfrag;
4181 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
4182 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
4183 pfrag += phba->params.num_sge_per_io;
90622db3 4184 psgl_handle->sgl_index = ulp_icd_start + arr_index++;
6733b39a
JK		 4185 }
4186 idx++;
4187 }
4188 phba->io_sgl_free_index = 0;
4189 phba->io_sgl_alloc_index = 0;
4190 phba->eh_sgl_free_index = 0;
4191 phba->eh_sgl_alloc_index = 0;
4192 return 0;
4193}
4194
4195static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
4196{
0a3db7c0
JK		 4197 int ret;
4198 uint16_t i, ulp_num;
4199 struct ulp_cid_info *ptr_cid_info = NULL;
6733b39a 4200
0a3db7c0
JK		 4201 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4202 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4203 ptr_cid_info = kzalloc(sizeof(struct ulp_cid_info),
4204 GFP_KERNEL);
4205
4206 if (!ptr_cid_info) {
4207 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4208 "BM_%d : Failed to allocate memory"
4209 "for ULP_CID_INFO for ULP : %d\n",
4210 ulp_num);
4211 ret = -ENOMEM;
4212 goto free_memory;
4213
4214 }
4215
4216 /* Allocate memory for CID array */
4217 ptr_cid_info->cid_array = kzalloc(sizeof(void *) *
4218 BEISCSI_GET_CID_COUNT(phba,
4219 ulp_num), GFP_KERNEL);
4220 if (!ptr_cid_info->cid_array) {
4221 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4222 "BM_%d : Failed to allocate memory"
4223 "for CID_ARRAY for ULP : %d\n",
4224 ulp_num);
4225 kfree(ptr_cid_info);
4226 ptr_cid_info = NULL;
4227 ret = -ENOMEM;
4228
4229 goto free_memory;
4230 }
4231 ptr_cid_info->avlbl_cids = BEISCSI_GET_CID_COUNT(
4232 phba, ulp_num);
4233
4234 /* Save the cid_info_array ptr */
4235 phba->cid_array_info[ulp_num] = ptr_cid_info;
4236 }
6733b39a 4237 }
c2462288 4238 phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
a7909b39 4239 phba->params.cxns_per_ctrl, GFP_KERNEL);
6733b39a 4240 if (!phba->ep_array) {
99bc5d55
JSJ		 4241 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4242 "BM_%d : Failed to allocate memory in "
4243 "hba_setup_cid_tbls\n");
0a3db7c0
JK		 4244 ret = -ENOMEM;
4245
4246 goto free_memory;
6733b39a 4247 }
a7909b39
JK		 4248
4249 phba->conn_table = kzalloc(sizeof(struct beiscsi_conn *) *
4250 phba->params.cxns_per_ctrl, GFP_KERNEL);
4251 if (!phba->conn_table) {
4252 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4253 "BM_%d : Failed to allocate memory in"
4254 "hba_setup_cid_tbls\n");
4255
a7909b39 4256 kfree(phba->ep_array);
a7909b39 4257 phba->ep_array = NULL;
0a3db7c0 4258 ret = -ENOMEM;
5f2d25ef
TH		 4259
4260 goto free_memory;
6733b39a 4261 }
a7909b39 4262
0a3db7c0
JK		 4263 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
4264 ulp_num = phba->phwi_ctrlr->wrb_context[i].ulp_num;
4265
4266 ptr_cid_info = phba->cid_array_info[ulp_num];
4267 ptr_cid_info->cid_array[ptr_cid_info->cid_alloc++] =
4268 phba->phwi_ctrlr->wrb_context[i].cid;
4269
4270 }
4271
4272 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4273 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4274 ptr_cid_info = phba->cid_array_info[ulp_num];
a7909b39 4275
0a3db7c0
JK		 4276 ptr_cid_info->cid_alloc = 0;
4277 ptr_cid_info->cid_free = 0;
4278 }
4279 }
6733b39a 4280 return 0;
0a3db7c0
JK		 4281
4282free_memory:
4283 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4284 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4285 ptr_cid_info = phba->cid_array_info[ulp_num];
4286
4287 if (ptr_cid_info) {
4288 kfree(ptr_cid_info->cid_array);
4289 kfree(ptr_cid_info);
4290 phba->cid_array_info[ulp_num] = NULL;
4291 }
4292 }
4293 }
4294
4295 return ret;
6733b39a
JK		 4296}
4297
238f6b72 4298static void hwi_enable_intr(struct beiscsi_hba *phba)
6733b39a
JK		 4299{
4300 struct be_ctrl_info *ctrl = &phba->ctrl;
4301 struct hwi_controller *phwi_ctrlr;
4302 struct hwi_context_memory *phwi_context;
4303 struct be_queue_info *eq;
4304 u8 __iomem *addr;
bfead3b2 4305 u32 reg, i;
6733b39a
JK		 4306 u32 enabled;
4307
4308 phwi_ctrlr = phba->phwi_ctrlr;
4309 phwi_context = phwi_ctrlr->phwi_ctxt;
4310
6733b39a
JK		 4311 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
4312 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
4313 reg = ioread32(addr);
6733b39a
JK		 4314
4315 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4316 if (!enabled) {
4317 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
99bc5d55
JSJ		 4318 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4319 "BM_%d : reg =x%08x addr=%p\n", reg, addr);
6733b39a 4320 iowrite32(reg, addr);
665d6d94
JK		 4321 }
4322
4323 if (!phba->msix_enabled) {
4324 eq = &phwi_context->be_eq[0].q;
99bc5d55
JSJ		 4325 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4326 "BM_%d : eq->id=%d\n", eq->id);
4327
665d6d94
JK		 4328 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
4329 } else {
4330 for (i = 0; i <= phba->num_cpus; i++) {
4331 eq = &phwi_context->be_eq[i].q;
99bc5d55
JSJ		 4332 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4333 "BM_%d : eq->id=%d\n", eq->id);
bfead3b2
JK		 4334 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
4335 }
c03af1ae 4336 }
6733b39a
JK		 4337}
4338
4339static void hwi_disable_intr(struct beiscsi_hba *phba)
4340{
4341 struct be_ctrl_info *ctrl = &phba->ctrl;
4342
4343 u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
4344 u32 reg = ioread32(addr);
4345
4346 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4347 if (enabled) {
4348 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4349 iowrite32(reg, addr);
4350 } else
99bc5d55
JSJ		 4351 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
4352 "BM_%d : In hwi_disable_intr, Already Disabled\n");
6733b39a
JK		 4353}
4354
9aef4200
JSJ		 4355/**
4356 * beiscsi_get_boot_info()- Get the boot session info
4357 * @phba: The device priv structure instance
4358 *
4359 * Get the boot target info and store in driver priv structure
4360 *
4361 * return values
4362 * Success: 0
4363 * Failure: Non-Zero Value
4364 **/
c7acc5b8
JK		 4365static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
4366{
0e43895e 4367 struct be_cmd_get_session_resp *session_resp;
c7acc5b8 4368 struct be_dma_mem nonemb_cmd;
e175defe 4369 unsigned int tag;
9aef4200 4370 unsigned int s_handle;
f457a46f 4371 int ret = -ENOMEM;
c7acc5b8 4372
9aef4200
JSJ		 4373 /* Get the session handle of the boot target */
4374 ret = be_mgmt_get_boot_shandle(phba, &s_handle);
4375 if (ret) {
99bc5d55
JSJ		 4376 beiscsi_log(phba, KERN_ERR,
4377 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
4378 "BM_%d : No boot session\n");
3efde862
JSJ		 4379
4380 if (ret == -ENXIO)
4381 phba->get_boot = 0;
4382
4383
9aef4200 4384 return ret;
c7acc5b8 4385 }
3efde862 4386 phba->get_boot = 0;
7c845eb5
JP		 4387 nonemb_cmd.va = pci_zalloc_consistent(phba->ctrl.pdev,
4388 sizeof(*session_resp),
4389 &nonemb_cmd.dma);
c7acc5b8 4390 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 4391 beiscsi_log(phba, KERN_ERR,
4392 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
4393 "BM_%d : Failed to allocate memory for"
4394 "beiscsi_get_session_info\n");
4395
c7acc5b8
JK		 4396 return -ENOMEM;
4397 }
4398
9aef4200 4399 tag = mgmt_get_session_info(phba, s_handle,
0e43895e 4400 &nonemb_cmd);
c7acc5b8 4401 if (!tag) {
99bc5d55
JSJ		 4402 beiscsi_log(phba, KERN_ERR,
4403 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
4404 "BM_%d : beiscsi_get_session_info"
4405 " Failed\n");
4406
c7acc5b8 4407 goto boot_freemem;
e175defe 4408 }
c7acc5b8 4409
88840332 4410 ret = beiscsi_mccq_compl_wait(phba, tag, NULL, &nonemb_cmd);
e175defe 4411 if (ret) {
99bc5d55
JSJ		 4412 beiscsi_log(phba, KERN_ERR,
4413 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
e175defe 4414 "BM_%d : beiscsi_get_session_info Failed");
1957aa7f
JK		 4415
4416 if (ret != -EBUSY)
4417 goto boot_freemem;
4418 else
4419 return ret;
c7acc5b8 4420 }
e175defe 4421
c7acc5b8 4422 session_resp = nonemb_cmd.va ;
f457a46f 4423
c7acc5b8
JK		 4424 memcpy(&phba->boot_sess, &session_resp->session_info,
4425 sizeof(struct mgmt_session_info));
3f4134c1
JSJ		 4426
4427 beiscsi_logout_fw_sess(phba,
4428 phba->boot_sess.session_handle);
f457a46f
MC		 4429 ret = 0;
4430
c7acc5b8
JK		 4431boot_freemem:
4432 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
4433 nonemb_cmd.va, nonemb_cmd.dma);
f457a46f
MC		 4434 return ret;
4435}
4436
4437static void beiscsi_boot_release(void *data)
4438{
4439 struct beiscsi_hba *phba = data;
4440
4441 scsi_host_put(phba->shost);
4442}
4443
4444static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
4445{
4446 struct iscsi_boot_kobj *boot_kobj;
4447
a3d313ea
JK		 4448 /* it has been created previously */
4449 if (phba->boot_kset)
4450 return 0;
4451
f457a46f
MC		 4452 /* get boot info using mgmt cmd */
4453 if (beiscsi_get_boot_info(phba))
4454 /* Try to see if we can carry on without this */
4455 return 0;
4456
4457 phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
4458 if (!phba->boot_kset)
4459 return -ENOMEM;
4460
4461 /* get a ref because the show function will ref the phba */
4462 if (!scsi_host_get(phba->shost))
4463 goto free_kset;
4464 boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
4465 beiscsi_show_boot_tgt_info,
4466 beiscsi_tgt_get_attr_visibility,
4467 beiscsi_boot_release);
4468 if (!boot_kobj)
4469 goto put_shost;
4470
4471 if (!scsi_host_get(phba->shost))
4472 goto free_kset;
4473 boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
4474 beiscsi_show_boot_ini_info,
4475 beiscsi_ini_get_attr_visibility,
4476 beiscsi_boot_release);
4477 if (!boot_kobj)
4478 goto put_shost;
4479
4480 if (!scsi_host_get(phba->shost))
4481 goto free_kset;
4482 boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
4483 beiscsi_show_boot_eth_info,
4484 beiscsi_eth_get_attr_visibility,
4485 beiscsi_boot_release);
4486 if (!boot_kobj)
4487 goto put_shost;
4488 return 0;
4489
4490put_shost:
4491 scsi_host_put(phba->shost);
4492free_kset:
4493 iscsi_boot_destroy_kset(phba->boot_kset);
c7acc5b8
JK		 4494 return -ENOMEM;
4495}
4496
6733b39a
JK		 4497static int beiscsi_init_port(struct beiscsi_hba *phba)
4498{
4499 int ret;
4500
4501 ret = beiscsi_init_controller(phba);
4502 if (ret < 0) {
99bc5d55
JSJ		 4503 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4504 "BM_%d : beiscsi_dev_probe - Failed in"
4505 "beiscsi_init_controller\n");
6733b39a
JK		 4506 return ret;
4507 }
4508 ret = beiscsi_init_sgl_handle(phba);
4509 if (ret < 0) {
99bc5d55
JSJ		 4510 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4511 "BM_%d : beiscsi_dev_probe - Failed in"
4512 "beiscsi_init_sgl_handle\n");
6733b39a
JK		 4513 goto do_cleanup_ctrlr;
4514 }
4515
4516 if (hba_setup_cid_tbls(phba)) {
99bc5d55
JSJ		 4517 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4518 "BM_%d : Failed in hba_setup_cid_tbls\n");
6733b39a
JK		 4519 kfree(phba->io_sgl_hndl_base);
4520 kfree(phba->eh_sgl_hndl_base);
4521 goto do_cleanup_ctrlr;
4522 }
4523
4524 return ret;
4525
4526do_cleanup_ctrlr:
4527 hwi_cleanup(phba);
4528 return ret;
4529}
4530
4531static void hwi_purge_eq(struct beiscsi_hba *phba)
4532{
4533 struct hwi_controller *phwi_ctrlr;
4534 struct hwi_context_memory *phwi_context;
4535 struct be_queue_info *eq;
4536 struct be_eq_entry *eqe = NULL;
bfead3b2 4537 int i, eq_msix;
756d29c8 4538 unsigned int num_processed;
6733b39a
JK		 4539
4540 phwi_ctrlr = phba->phwi_ctrlr;
4541 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 4542 if (phba->msix_enabled)
4543 eq_msix = 1;
4544 else
4545 eq_msix = 0;
6733b39a 4546
bfead3b2
JK		 4547 for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
4548 eq = &phwi_context->be_eq[i].q;
6733b39a 4549 eqe = queue_tail_node(eq);
756d29c8 4550 num_processed = 0;
bfead3b2
JK		 4551 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
4552 & EQE_VALID_MASK) {
4553 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
4554 queue_tail_inc(eq);
4555 eqe = queue_tail_node(eq);
756d29c8 4556 num_processed++;
bfead3b2 4557 }
756d29c8
JK		 4558
4559 if (num_processed)
4560 hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
6733b39a
JK		 4561 }
4562}
4563
4564static void beiscsi_clean_port(struct beiscsi_hba *phba)
4565{
0a3db7c0
JK		 4566 int mgmt_status, ulp_num;
4567 struct ulp_cid_info *ptr_cid_info = NULL;
6733b39a 4568
bd41c2bd
JK		 4569 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4570 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4571 mgmt_status = mgmt_epfw_cleanup(phba, ulp_num);
4572 if (mgmt_status)
4573 beiscsi_log(phba, KERN_WARNING,
4574 BEISCSI_LOG_INIT,
4575 "BM_%d : mgmt_epfw_cleanup FAILED"
4576 " for ULP_%d\n", ulp_num);
4577 }
4578 }
756d29c8 4579
6733b39a 4580 hwi_purge_eq(phba);
756d29c8 4581 hwi_cleanup(phba);
6733b39a
JK		 4582 kfree(phba->io_sgl_hndl_base);
4583 kfree(phba->eh_sgl_hndl_base);
6733b39a 4584 kfree(phba->ep_array);
a7909b39 4585 kfree(phba->conn_table);
0a3db7c0
JK		 4586
4587 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4588 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4589 ptr_cid_info = phba->cid_array_info[ulp_num];
4590
4591 if (ptr_cid_info) {
4592 kfree(ptr_cid_info->cid_array);
4593 kfree(ptr_cid_info);
4594 phba->cid_array_info[ulp_num] = NULL;
4595 }
4596 }
4597 }
4598
6733b39a
JK		 4599}
4600
43f388b0
JK		 4601/**
4602 * beiscsi_free_mgmt_task_handles()- Free driver CXN resources
4603 * @beiscsi_conn: ptr to the conn to be cleaned up
4a4a11b9 4604 * @task: ptr to iscsi_task resource to be freed.
43f388b0
JK		 4605 *
4606 * Free driver mgmt resources binded to CXN.
4607 **/
4608void
4a4a11b9
JK		 4609beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
4610 struct iscsi_task *task)
43f388b0
JK		 4611{
4612 struct beiscsi_io_task *io_task;
4613 struct beiscsi_hba *phba = beiscsi_conn->phba;
4614 struct hwi_wrb_context *pwrb_context;
4615 struct hwi_controller *phwi_ctrlr;
a7909b39
JK		 4616 uint16_t cri_index = BE_GET_CRI_FROM_CID(
4617 beiscsi_conn->beiscsi_conn_cid);
43f388b0
JK		 4618
4619 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39
JK		 4620 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
4621
4a4a11b9 4622 io_task = task->dd_data;
43f388b0
JK		 4623
4624 if (io_task->pwrb_handle) {
4625 memset(io_task->pwrb_handle->pwrb, 0,
4626 sizeof(struct iscsi_wrb));
4627 free_wrb_handle(phba, pwrb_context,
4628 io_task->pwrb_handle);
4629 io_task->pwrb_handle = NULL;
4630 }
4631
4632 if (io_task->psgl_handle) {
43f388b0
JK		 4633 free_mgmt_sgl_handle(phba,
4634 io_task->psgl_handle);
43f388b0
JK		 4635 io_task->psgl_handle = NULL;
4636 }
4637
eb1c4692 4638 if (io_task->mtask_addr) {
43f388b0
JK		 4639 pci_unmap_single(phba->pcidev,
4640 io_task->mtask_addr,
4641 io_task->mtask_data_count,
4642 PCI_DMA_TODEVICE);
eb1c4692
JSJ		 4643 io_task->mtask_addr = 0;
4644 }
43f388b0
JK		 4645}
4646
d629c471
JSJ		 4647/**
4648 * beiscsi_cleanup_task()- Free driver resources of the task
4649 * @task: ptr to the iscsi task
4650 *
4651 **/
1282ab76
MC		 4652static void beiscsi_cleanup_task(struct iscsi_task *task)
4653{
4654 struct beiscsi_io_task *io_task = task->dd_data;
4655 struct iscsi_conn *conn = task->conn;
4656 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4657 struct beiscsi_hba *phba = beiscsi_conn->phba;
4658 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
4659 struct hwi_wrb_context *pwrb_context;
4660 struct hwi_controller *phwi_ctrlr;
a7909b39
JK		 4661 uint16_t cri_index = BE_GET_CRI_FROM_CID(
4662 beiscsi_conn->beiscsi_conn_cid);
1282ab76
MC		 4663
4664 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 4665 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
1282ab76
MC		 4666
4667 if (io_task->cmd_bhs) {
4668 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
4669 io_task->bhs_pa.u.a64.address);
4670 io_task->cmd_bhs = NULL;
4671 }
4672
4673 if (task->sc) {
4674 if (io_task->pwrb_handle) {
4675 free_wrb_handle(phba, pwrb_context,
4676 io_task->pwrb_handle);
4677 io_task->pwrb_handle = NULL;
4678 }
4679
4680 if (io_task->psgl_handle) {
1282ab76 4681 free_io_sgl_handle(phba, io_task->psgl_handle);
1282ab76
MC		 4682 io_task->psgl_handle = NULL;
4683 }
da334977
JK		 4684
4685 if (io_task->scsi_cmnd) {
4686 scsi_dma_unmap(io_task->scsi_cmnd);
4687 io_task->scsi_cmnd = NULL;
4688 }
1282ab76 4689 } else {
43f388b0 4690 if (!beiscsi_conn->login_in_progress)
4a4a11b9 4691 beiscsi_free_mgmt_task_handles(beiscsi_conn, task);
1282ab76
MC		 4692 }
4693}
4694
6733b39a
JK		 4695void
4696beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
4697 struct beiscsi_offload_params *params)
4698{
4699 struct wrb_handle *pwrb_handle;
340c99e9 4700 struct hwi_wrb_context *pwrb_context = NULL;
6733b39a 4701 struct beiscsi_hba *phba = beiscsi_conn->phba;
1282ab76
MC		 4702 struct iscsi_task *task = beiscsi_conn->task;
4703 struct iscsi_session *session = task->conn->session;
6733b39a
JK		 4704 u32 doorbell = 0;
4705
4706 /*
4707 * We can always use 0 here because it is reserved by libiscsi for
4708 * login/startup related tasks.
4709 */
1282ab76 4710 beiscsi_conn->login_in_progress = 0;
659743b0 4711 spin_lock_bh(&session->back_lock);
1282ab76 4712 beiscsi_cleanup_task(task);
659743b0 4713 spin_unlock_bh(&session->back_lock);
1282ab76 4714
340c99e9
JSJ		 4715 pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid,
4716 &pwrb_context);
6733b39a 4717
acb9693c 4718 /* Check for the adapter family */
2c9dfd36 4719 if (is_chip_be2_be3r(phba))
acb9693c 4720 beiscsi_offload_cxn_v0(params, pwrb_handle,
340c99e9
JSJ		 4721 phba->init_mem,
4722 pwrb_context);
2c9dfd36 4723 else
340c99e9
JSJ		 4724 beiscsi_offload_cxn_v2(params, pwrb_handle,
4725 pwrb_context);
6733b39a 4726
acb9693c
JSJ		 4727 be_dws_le_to_cpu(pwrb_handle->pwrb,
4728 sizeof(struct iscsi_target_context_update_wrb));
6733b39a
JK		 4729
4730 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 4731 doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
bfead3b2 4732 << DB_DEF_PDU_WRB_INDEX_SHIFT;
6733b39a 4733 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 4734 iowrite32(doorbell, phba->db_va +
4735 beiscsi_conn->doorbell_offset);
cb564c6b
JB		 4736
4737 /*
4738 * There is no completion for CONTEXT_UPDATE. The completion of next
4739 * WRB posted guarantees FW's processing and DMA'ing of it.
4740 * Use beiscsi_put_wrb_handle to put it back in the pool which makes
4741 * sure zero'ing or reuse of the WRB only after wrbs_per_cxn.
4742 */
4743 beiscsi_put_wrb_handle(pwrb_context, pwrb_handle,
4744 phba->params.wrbs_per_cxn);
4745 beiscsi_log(phba, KERN_INFO,
4746 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4747 "BM_%d : put CONTEXT_UPDATE pwrb_handle=%p free_index=0x%x wrb_handles_available=%d\n",
4748 pwrb_handle, pwrb_context->free_index,
4749 pwrb_context->wrb_handles_available);
6733b39a
JK		 4750}
4751
4752static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
4753 int *index, int *age)
4754{
bfead3b2 4755 *index = (int)itt;
6733b39a
JK		 4756 if (age)
4757 *age = conn->session->age;
4758}
4759
4760/**
4761 * beiscsi_alloc_pdu - allocates pdu and related resources
4762 * @task: libiscsi task
4763 * @opcode: opcode of pdu for task
4764 *
4765 * This is called with the session lock held. It will allocate
4766 * the wrb and sgl if needed for the command. And it will prep
4767 * the pdu's itt. beiscsi_parse_pdu will later translate
4768 * the pdu itt to the libiscsi task itt.
4769 */
4770static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
4771{
4772 struct beiscsi_io_task *io_task = task->dd_data;
4773 struct iscsi_conn *conn = task->conn;
4774 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4775 struct beiscsi_hba *phba = beiscsi_conn->phba;
4776 struct hwi_wrb_context *pwrb_context;
4777 struct hwi_controller *phwi_ctrlr;
4778 itt_t itt;
a7909b39 4779 uint16_t cri_index = 0;
2afc95bf
JK		 4780 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
4781 dma_addr_t paddr;
6733b39a 4782
2afc95bf 4783 io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
bc7accec 4784 GFP_ATOMIC, &paddr);
2afc95bf
JK		 4785 if (!io_task->cmd_bhs)
4786 return -ENOMEM;
2afc95bf 4787 io_task->bhs_pa.u.a64.address = paddr;
bfead3b2 4788 io_task->libiscsi_itt = (itt_t)task->itt;
6733b39a
JK		 4789 io_task->conn = beiscsi_conn;
4790
4791 task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
4792 task->hdr_max = sizeof(struct be_cmd_bhs);
d2cecf0d 4793 io_task->psgl_handle = NULL;
3ec78271 4794 io_task->pwrb_handle = NULL;
6733b39a
JK		 4795
4796 if (task->sc) {
6733b39a 4797 io_task->psgl_handle = alloc_io_sgl_handle(phba);
8359c79b
JSJ		 4798 if (!io_task->psgl_handle) {
4799 beiscsi_log(phba, KERN_ERR,
4800 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4801 "BM_%d : Alloc of IO_SGL_ICD Failed"
4802 "for the CID : %d\n",
4803 beiscsi_conn->beiscsi_conn_cid);
2afc95bf 4804 goto free_hndls;
8359c79b 4805 }
d2cecf0d 4806 io_task->pwrb_handle = alloc_wrb_handle(phba,
340c99e9
JSJ		 4807 beiscsi_conn->beiscsi_conn_cid,
4808 &io_task->pwrb_context);
8359c79b
JSJ		 4809 if (!io_task->pwrb_handle) {
4810 beiscsi_log(phba, KERN_ERR,
4811 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4812 "BM_%d : Alloc of WRB_HANDLE Failed"
4813 "for the CID : %d\n",
4814 beiscsi_conn->beiscsi_conn_cid);
d2cecf0d 4815 goto free_io_hndls;
8359c79b 4816 }
6733b39a
JK		 4817 } else {
4818 io_task->scsi_cmnd = NULL;
d7aea67b 4819 if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
43f388b0 4820 beiscsi_conn->task = task;
6733b39a 4821 if (!beiscsi_conn->login_in_progress) {
6733b39a
JK		 4822 io_task->psgl_handle = (struct sgl_handle *)
4823 alloc_mgmt_sgl_handle(phba);
8359c79b
JSJ		 4824 if (!io_task->psgl_handle) {
4825 beiscsi_log(phba, KERN_ERR,
4826 BEISCSI_LOG_IO |
4827 BEISCSI_LOG_CONFIG,
4828 "BM_%d : Alloc of MGMT_SGL_ICD Failed"
4829 "for the CID : %d\n",
4830 beiscsi_conn->
4831 beiscsi_conn_cid);
2afc95bf 4832 goto free_hndls;
8359c79b 4833 }
2afc95bf 4834
6733b39a
JK		 4835 beiscsi_conn->login_in_progress = 1;
4836 beiscsi_conn->plogin_sgl_handle =
4837 io_task->psgl_handle;
d2cecf0d
JK		 4838 io_task->pwrb_handle =
4839 alloc_wrb_handle(phba,
340c99e9
JSJ		 4840 beiscsi_conn->beiscsi_conn_cid,
4841 &io_task->pwrb_context);
8359c79b
JSJ		 4842 if (!io_task->pwrb_handle) {
4843 beiscsi_log(phba, KERN_ERR,
4844 BEISCSI_LOG_IO |
4845 BEISCSI_LOG_CONFIG,
4846 "BM_%d : Alloc of WRB_HANDLE Failed"
4847 "for the CID : %d\n",
4848 beiscsi_conn->
4849 beiscsi_conn_cid);
4850 goto free_mgmt_hndls;
4851 }
d2cecf0d
JK		 4852 beiscsi_conn->plogin_wrb_handle =
4853 io_task->pwrb_handle;
4854
6733b39a
JK		 4855 } else {
4856 io_task->psgl_handle =
4857 beiscsi_conn->plogin_sgl_handle;
d2cecf0d
JK		 4858 io_task->pwrb_handle =
4859 beiscsi_conn->plogin_wrb_handle;
6733b39a
JK		 4860 }
4861 } else {
6733b39a 4862 io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
8359c79b
JSJ		 4863 if (!io_task->psgl_handle) {
4864 beiscsi_log(phba, KERN_ERR,
4865 BEISCSI_LOG_IO |
4866 BEISCSI_LOG_CONFIG,
4867 "BM_%d : Alloc of MGMT_SGL_ICD Failed"
4868 "for the CID : %d\n",
4869 beiscsi_conn->
4870 beiscsi_conn_cid);
2afc95bf 4871 goto free_hndls;
8359c79b 4872 }
d2cecf0d
JK		 4873 io_task->pwrb_handle =
4874 alloc_wrb_handle(phba,
340c99e9
JSJ		 4875 beiscsi_conn->beiscsi_conn_cid,
4876 &io_task->pwrb_context);
8359c79b
JSJ		 4877 if (!io_task->pwrb_handle) {
4878 beiscsi_log(phba, KERN_ERR,
4879 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4880 "BM_%d : Alloc of WRB_HANDLE Failed"
4881 "for the CID : %d\n",
4882 beiscsi_conn->beiscsi_conn_cid);
d2cecf0d 4883 goto free_mgmt_hndls;
8359c79b 4884 }
d2cecf0d 4885
6733b39a
JK		 4886 }
4887 }
bfead3b2
JK		 4888 itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
4889 wrb_index << 16) | (unsigned int)
4890 (io_task->psgl_handle->sgl_index));
32951dd8 4891 io_task->pwrb_handle->pio_handle = task;
bfead3b2 4892
6733b39a
JK		 4893 io_task->cmd_bhs->iscsi_hdr.itt = itt;
4894 return 0;
2afc95bf 4895
d2cecf0d 4896free_io_hndls:
d2cecf0d 4897 free_io_sgl_handle(phba, io_task->psgl_handle);
d2cecf0d
JK		 4898 goto free_hndls;
4899free_mgmt_hndls:
d2cecf0d 4900 free_mgmt_sgl_handle(phba, io_task->psgl_handle);
a7909b39 4901 io_task->psgl_handle = NULL;
2afc95bf
JK		 4902free_hndls:
4903 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39
JK		 4904 cri_index = BE_GET_CRI_FROM_CID(
4905 beiscsi_conn->beiscsi_conn_cid);
4906 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
d2cecf0d
JK		 4907 if (io_task->pwrb_handle)
4908 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
2afc95bf
JK		 4909 io_task->pwrb_handle = NULL;
4910 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
4911 io_task->bhs_pa.u.a64.address);
1282ab76 4912 io_task->cmd_bhs = NULL;
2afc95bf 4913 return -ENOMEM;
6733b39a 4914}
09a1093a
JSJ		 4915int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg,
4916 unsigned int num_sg, unsigned int xferlen,
4917 unsigned int writedir)
4918{
4919
4920 struct beiscsi_io_task *io_task = task->dd_data;
4921 struct iscsi_conn *conn = task->conn;
4922 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4923 struct beiscsi_hba *phba = beiscsi_conn->phba;
4924 struct iscsi_wrb *pwrb = NULL;
4925 unsigned int doorbell = 0;
4926
4927 pwrb = io_task->pwrb_handle->pwrb;
09a1093a 4928
09a1093a
JSJ		 4929 io_task->bhs_len = sizeof(struct be_cmd_bhs);
4930
4931 if (writedir) {
4932 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
4933 INI_WR_CMD);
4934 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1);
4935 } else {
4936 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
4937 INI_RD_CMD);
4938 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0);
4939 }
4940
4941 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2,
4942 type, pwrb);
4943
4944 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb,
4945 cpu_to_be16(*(unsigned short *)
4946 &io_task->cmd_bhs->iscsi_hdr.lun));
4947 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen);
4948 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
4949 io_task->pwrb_handle->wrb_index);
4950 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
4951 be32_to_cpu(task->cmdsn));
4952 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
4953 io_task->psgl_handle->sgl_index);
4954
4955 hwi_write_sgl_v2(pwrb, sg, num_sg, io_task);
4956 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
340c99e9
JSJ		 4957 io_task->pwrb_handle->wrb_index);
4958 if (io_task->pwrb_context->plast_wrb)
4959 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb,
4960 io_task->pwrb_context->plast_wrb,
4961 io_task->pwrb_handle->wrb_index);
4962 io_task->pwrb_context->plast_wrb = pwrb;
09a1093a
JSJ		 4963
4964 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4965
4966 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
4967 doorbell |= (io_task->pwrb_handle->wrb_index &
4968 DB_DEF_PDU_WRB_INDEX_MASK) <<
4969 DB_DEF_PDU_WRB_INDEX_SHIFT;
4970 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 4971 iowrite32(doorbell, phba->db_va +
4972 beiscsi_conn->doorbell_offset);
09a1093a
JSJ		 4973 return 0;
4974}
6733b39a 4975
6733b39a
JK		 4976static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
4977 unsigned int num_sg, unsigned int xferlen,
4978 unsigned int writedir)
4979{
4980
4981 struct beiscsi_io_task *io_task = task->dd_data;
4982 struct iscsi_conn *conn = task->conn;
4983 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4984 struct beiscsi_hba *phba = beiscsi_conn->phba;
4985 struct iscsi_wrb *pwrb = NULL;
4986 unsigned int doorbell = 0;
4987
4988 pwrb = io_task->pwrb_handle->pwrb;
6733b39a
JK		 4989 io_task->bhs_len = sizeof(struct be_cmd_bhs);
4990
4991 if (writedir) {
32951dd8
JK		 4992 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4993 INI_WR_CMD);
6733b39a 4994 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
6733b39a 4995 } else {
32951dd8
JK		 4996 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4997 INI_RD_CMD);
6733b39a
JK		 4998 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
4999 }
6733b39a 5000
09a1093a
JSJ		 5001 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb,
5002 type, pwrb);
5003
6733b39a 5004 AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
dc63aac6
JK		 5005 cpu_to_be16(*(unsigned short *)
5006 &io_task->cmd_bhs->iscsi_hdr.lun));
6733b39a
JK		 5007 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
5008 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
5009 io_task->pwrb_handle->wrb_index);
5010 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
5011 be32_to_cpu(task->cmdsn));
5012 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
5013 io_task->psgl_handle->sgl_index);
5014
5015 hwi_write_sgl(pwrb, sg, num_sg, io_task);
5016
5017 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
340c99e9
JSJ		 5018 io_task->pwrb_handle->wrb_index);
5019 if (io_task->pwrb_context->plast_wrb)
5020 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb,
5021 io_task->pwrb_context->plast_wrb,
5022 io_task->pwrb_handle->wrb_index);
5023 io_task->pwrb_context->plast_wrb = pwrb;
5024
6733b39a
JK		 5025 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
5026
5027 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 5028 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 5029 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
5030 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
5031
1e4be6ff
JK		 5032 iowrite32(doorbell, phba->db_va +
5033 beiscsi_conn->doorbell_offset);
6733b39a
JK		 5034 return 0;
5035}
5036
5037static int beiscsi_mtask(struct iscsi_task *task)
5038{
dafab8e0 5039 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 5040 struct iscsi_conn *conn = task->conn;
5041 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
5042 struct beiscsi_hba *phba = beiscsi_conn->phba;
5043 struct iscsi_wrb *pwrb = NULL;
5044 unsigned int doorbell = 0;
dafab8e0 5045 unsigned int cid;
09a1093a 5046 unsigned int pwrb_typeoffset = 0;
e0493627 5047 int ret = 0;
6733b39a 5048
bfead3b2 5049 cid = beiscsi_conn->beiscsi_conn_cid;
6733b39a 5050 pwrb = io_task->pwrb_handle->pwrb;
caf818f1 5051 memset(pwrb, 0, sizeof(*pwrb));
09a1093a 5052
2c9dfd36 5053 if (is_chip_be2_be3r(phba)) {
09a1093a
JSJ		 5054 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
5055 be32_to_cpu(task->cmdsn));
5056 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
5057 io_task->pwrb_handle->wrb_index);
5058 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
5059 io_task->psgl_handle->sgl_index);
5060 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
5061 task->data_count);
5062 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
340c99e9
JSJ		 5063 io_task->pwrb_handle->wrb_index);
5064 if (io_task->pwrb_context->plast_wrb)
5065 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb,
5066 io_task->pwrb_context->plast_wrb,
5067 io_task->pwrb_handle->wrb_index);
5068 io_task->pwrb_context->plast_wrb = pwrb;
5069
09a1093a 5070 pwrb_typeoffset = BE_WRB_TYPE_OFFSET;
2c9dfd36
JK		 5071 } else {
5072 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
5073 be32_to_cpu(task->cmdsn));
5074 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
5075 io_task->pwrb_handle->wrb_index);
5076 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
5077 io_task->psgl_handle->sgl_index);
5078 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb,
5079 task->data_count);
5080 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
340c99e9
JSJ		 5081 io_task->pwrb_handle->wrb_index);
5082 if (io_task->pwrb_context->plast_wrb)
5083 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb,
5084 io_task->pwrb_context->plast_wrb,
5085 io_task->pwrb_handle->wrb_index);
5086 io_task->pwrb_context->plast_wrb = pwrb;
5087
2c9dfd36 5088 pwrb_typeoffset = SKH_WRB_TYPE_OFFSET;
09a1093a
JSJ		 5089 }
5090
dafab8e0 5091
6733b39a
JK		 5092 switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
5093 case ISCSI_OP_LOGIN:
6733b39a 5094 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
09a1093a 5095 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
e0493627 5096 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 5097 break;
5098 case ISCSI_OP_NOOP_OUT:
1390b01b 5099 if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
09a1093a 5100 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
2c9dfd36
JK		 5101 if (is_chip_be2_be3r(phba))
5102 AMAP_SET_BITS(struct amap_iscsi_wrb,
09a1093a
JSJ		 5103 dmsg, pwrb, 1);
5104 else
2c9dfd36 5105 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
09a1093a 5106 dmsg, pwrb, 1);
1390b01b 5107 } else {
09a1093a 5108 ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset);
2c9dfd36
JK		 5109 if (is_chip_be2_be3r(phba))
5110 AMAP_SET_BITS(struct amap_iscsi_wrb,
09a1093a
JSJ		 5111 dmsg, pwrb, 0);
5112 else
2c9dfd36 5113 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
09a1093a 5114 dmsg, pwrb, 0);
1390b01b 5115 }
e0493627 5116 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 5117 break;
5118 case ISCSI_OP_TEXT:
09a1093a 5119 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
e0493627 5120 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 5121 break;
5122 case ISCSI_OP_SCSI_TMFUNC:
09a1093a 5123 ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset);
e0493627 5124 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 5125 break;
5126 case ISCSI_OP_LOGOUT:
09a1093a 5127 ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset);
e0493627 5128 ret = hwi_write_buffer(pwrb, task);
6733b39a
JK		 5129 break;
5130
5131 default:
99bc5d55
JSJ		 5132 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
5133 "BM_%d : opcode =%d Not supported\n",
5134 task->hdr->opcode & ISCSI_OPCODE_MASK);
5135
6733b39a
JK		 5136 return -EINVAL;
5137 }
5138
e0493627
AK		 5139 if (ret)
5140 return ret;
5141
09a1093a 5142 /* Set the task type */
2c9dfd36
JK		 5143 io_task->wrb_type = (is_chip_be2_be3r(phba)) ?
5144 AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) :
5145 AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb);
6733b39a 5146
bfead3b2 5147 doorbell |= cid & DB_WRB_POST_CID_MASK;
32951dd8 5148 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 5149 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
5150 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 5151 iowrite32(doorbell, phba->db_va +
5152 beiscsi_conn->doorbell_offset);
6733b39a
JK		 5153 return 0;
5154}
5155
5156static int beiscsi_task_xmit(struct iscsi_task *task)
5157{
6733b39a
JK		 5158 struct beiscsi_io_task *io_task = task->dd_data;
5159 struct scsi_cmnd *sc = task->sc;
1868379b 5160 struct beiscsi_hba *phba;
6733b39a
JK		 5161 struct scatterlist *sg;
5162 int num_sg;
5163 unsigned int writedir = 0, xferlen = 0;
5164
1868379b
JB		 5165 if (!io_task->conn->login_in_progress)
5166 task->hdr->exp_statsn = 0;
09a1093a 5167
6733b39a
JK		 5168 if (!sc)
5169 return beiscsi_mtask(task);
5170
5171 io_task->scsi_cmnd = sc;
5172 num_sg = scsi_dma_map(sc);
1868379b 5173 phba = io_task->conn->phba;
6733b39a 5174 if (num_sg < 0) {
afb96058
JK		 5175 beiscsi_log(phba, KERN_ERR,
5176 BEISCSI_LOG_IO | BEISCSI_LOG_ISCSI,
5177 "BM_%d : scsi_dma_map Failed "
5178 "Driver_ITT : 0x%x ITT : 0x%x Xferlen : 0x%x\n",
5179 be32_to_cpu(io_task->cmd_bhs->iscsi_hdr.itt),
5180 io_task->libiscsi_itt, scsi_bufflen(sc));
99bc5d55 5181
6733b39a
JK		 5182 return num_sg;
5183 }
6733b39a
JK		 5184 xferlen = scsi_bufflen(sc);
5185 sg = scsi_sglist(sc);
99bc5d55 5186 if (sc->sc_data_direction == DMA_TO_DEVICE)
6733b39a 5187 writedir = 1;
99bc5d55 5188 else
6733b39a 5189 writedir = 0;
99bc5d55 5190
09a1093a 5191 return phba->iotask_fn(task, sg, num_sg, xferlen, writedir);
6733b39a
JK		 5192}
5193
ffce3e2e
JK		 5194/**
5195 * beiscsi_bsg_request - handle bsg request from ISCSI transport
5196 * @job: job to handle
5197 */
5198static int beiscsi_bsg_request(struct bsg_job *job)
5199{
5200 struct Scsi_Host *shost;
5201 struct beiscsi_hba *phba;
5202 struct iscsi_bsg_request *bsg_req = job->request;
5203 int rc = -EINVAL;
5204 unsigned int tag;
5205 struct be_dma_mem nonemb_cmd;
5206 struct be_cmd_resp_hdr *resp;
5207 struct iscsi_bsg_reply *bsg_reply = job->reply;
5208 unsigned short status, extd_status;
5209
5210 shost = iscsi_job_to_shost(job);
5211 phba = iscsi_host_priv(shost);
5212
5213 switch (bsg_req->msgcode) {
5214 case ISCSI_BSG_HST_VENDOR:
5215 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
5216 job->request_payload.payload_len,
5217 &nonemb_cmd.dma);
5218 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 5219 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
5220 "BM_%d : Failed to allocate memory for "
5221 "beiscsi_bsg_request\n");
8359c79b 5222 return -ENOMEM;
ffce3e2e
JK		 5223 }
5224 tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
5225 &nonemb_cmd);
5226 if (!tag) {
99bc5d55 5227 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
8359c79b 5228 "BM_%d : MBX Tag Allocation Failed\n");
99bc5d55 5229
ffce3e2e
JK		 5230 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
5231 nonemb_cmd.va, nonemb_cmd.dma);
5232 return -EAGAIN;
e175defe
JSJ		 5233 }
5234
5235 rc = wait_event_interruptible_timeout(
5236 phba->ctrl.mcc_wait[tag],
67296ad9 5237 phba->ctrl.mcc_tag_status[tag],
e175defe
JSJ		 5238 msecs_to_jiffies(
5239 BEISCSI_HOST_MBX_TIMEOUT));
67296ad9
JB		 5240 extd_status = (phba->ctrl.mcc_tag_status[tag] &
5241 CQE_STATUS_ADDL_MASK) >> CQE_STATUS_ADDL_SHIFT;
5242 status = phba->ctrl.mcc_tag_status[tag] & CQE_STATUS_MASK;
090e2184 5243 free_mcc_wrb(&phba->ctrl, tag);
ffce3e2e
JK		 5244 resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
5245 sg_copy_from_buffer(job->reply_payload.sg_list,
5246 job->reply_payload.sg_cnt,
5247 nonemb_cmd.va, (resp->response_length
5248 + sizeof(*resp)));
5249 bsg_reply->reply_payload_rcv_len = resp->response_length;
5250 bsg_reply->result = status;
5251 bsg_job_done(job, bsg_reply->result,
5252 bsg_reply->reply_payload_rcv_len);
5253 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
5254 nonemb_cmd.va, nonemb_cmd.dma);
5255 if (status || extd_status) {
99bc5d55 5256 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
8359c79b 5257 "BM_%d : MBX Cmd Failed"
99bc5d55
JSJ		 5258 " status = %d extd_status = %d\n",
5259 status, extd_status);
5260
ffce3e2e 5261 return -EIO;
8359c79b
JSJ		 5262 } else {
5263 rc = 0;
ffce3e2e
JK		 5264 }
5265 break;
5266
5267 default:
99bc5d55
JSJ		 5268 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
5269 "BM_%d : Unsupported bsg command: 0x%x\n",
5270 bsg_req->msgcode);
ffce3e2e
JK		 5271 break;
5272 }
5273
5274 return rc;
5275}
5276
99bc5d55
JSJ		 5277void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
5278{
5279 /* Set the logging parameter */
5280 beiscsi_log_enable_init(phba, beiscsi_log_enable);
5281}
5282
4d4d1ef8
JSJ		 5283/*
5284 * beiscsi_quiesce()- Cleanup Driver resources
5285 * @phba: Instance Priv structure
3567f36a 5286 * @unload_state:i Clean or EEH unload state
4d4d1ef8
JSJ		 5287 *
5288 * Free the OS and HW resources held by the driver
5289 **/
3567f36a
JK		 5290static void beiscsi_quiesce(struct beiscsi_hba *phba,
5291 uint32_t unload_state)
6733b39a 5292{
bfead3b2
JK		 5293 struct hwi_controller *phwi_ctrlr;
5294 struct hwi_context_memory *phwi_context;
5295 struct be_eq_obj *pbe_eq;
5296 unsigned int i, msix_vec;
6733b39a 5297
bfead3b2
JK		 5298 phwi_ctrlr = phba->phwi_ctrlr;
5299 phwi_context = phwi_ctrlr->phwi_ctxt;
6733b39a 5300 hwi_disable_intr(phba);
bfead3b2
JK		 5301 if (phba->msix_enabled) {
5302 for (i = 0; i <= phba->num_cpus; i++) {
5303 msix_vec = phba->msix_entries[i].vector;
3567f36a 5304 synchronize_irq(msix_vec);
bfead3b2 5305 free_irq(msix_vec, &phwi_context->be_eq[i]);
8fcfb210 5306 kfree(phba->msi_name[i]);
bfead3b2
JK		 5307 }
5308 } else
3567f36a
JK		 5309 if (phba->pcidev->irq) {
5310 synchronize_irq(phba->pcidev->irq);
bfead3b2 5311 free_irq(phba->pcidev->irq, phba);
3567f36a 5312 }
bfead3b2 5313 pci_disable_msix(phba->pcidev);
53281edb 5314 cancel_delayed_work_sync(&phba->beiscsi_hw_check_task);
3567f36a 5315
89f8b33c
JA		 5316 for (i = 0; i < phba->num_cpus; i++) {
5317 pbe_eq = &phwi_context->be_eq[i];
511cbce2 5318 irq_poll_disable(&pbe_eq->iopoll);
89f8b33c 5319 }
6733b39a 5320
3567f36a
JK		 5321 if (unload_state == BEISCSI_CLEAN_UNLOAD) {
5322 destroy_workqueue(phba->wq);
5323 beiscsi_clean_port(phba);
5324 beiscsi_free_mem(phba);
e9b91193 5325
3567f36a
JK		 5326 beiscsi_unmap_pci_function(phba);
5327 pci_free_consistent(phba->pcidev,
5328 phba->ctrl.mbox_mem_alloced.size,
5329 phba->ctrl.mbox_mem_alloced.va,
5330 phba->ctrl.mbox_mem_alloced.dma);
5331 } else {
5332 hwi_purge_eq(phba);
5333 hwi_cleanup(phba);
5334 }
7a158003 5335
25602c97
JK		 5336}
5337
5338static void beiscsi_remove(struct pci_dev *pcidev)
5339{
25602c97
JK		 5340 struct beiscsi_hba *phba = NULL;
5341
5342 phba = pci_get_drvdata(pcidev);
5343 if (!phba) {
5344 dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
5345 return;
5346 }
5347
0e43895e 5348 beiscsi_destroy_def_ifaces(phba);
9d045163 5349 iscsi_boot_destroy_kset(phba->boot_kset);
6733b39a 5350 iscsi_host_remove(phba->shost);
cdaa4ded 5351 beiscsi_quiesce(phba, BEISCSI_CLEAN_UNLOAD);
6733b39a
JK		 5352 pci_dev_put(phba->pcidev);
5353 iscsi_host_free(phba->shost);
3567f36a
JK		 5354 pci_disable_pcie_error_reporting(pcidev);
5355 pci_set_drvdata(pcidev, NULL);
e307f3ac 5356 pci_release_regions(pcidev);
8dce69ff 5357 pci_disable_device(pcidev);
6733b39a
JK		 5358}
5359
bfead3b2
JK		 5360static void beiscsi_msix_enable(struct beiscsi_hba *phba)
5361{
5362 int i, status;
5363
5364 for (i = 0; i <= phba->num_cpus; i++)
5365 phba->msix_entries[i].entry = i;
5366
e149fc13
AG		 5367 status = pci_enable_msix_range(phba->pcidev, phba->msix_entries,
5368 phba->num_cpus + 1, phba->num_cpus + 1);
5369 if (status > 0)
bfead3b2
JK		 5370 phba->msix_enabled = true;
5371
5372 return;
5373}
5374
73af08e1
JK		 5375static void be_eqd_update(struct beiscsi_hba *phba)
5376{
5377 struct be_set_eqd set_eqd[MAX_CPUS];
5378 struct be_aic_obj *aic;
5379 struct be_eq_obj *pbe_eq;
5380 struct hwi_controller *phwi_ctrlr;
5381 struct hwi_context_memory *phwi_context;
5382 int eqd, i, num = 0;
5383 ulong now;
5384 u32 pps, delta;
5385 unsigned int tag;
5386
5387 phwi_ctrlr = phba->phwi_ctrlr;
5388 phwi_context = phwi_ctrlr->phwi_ctxt;
5389
5390 for (i = 0; i <= phba->num_cpus; i++) {
5391 aic = &phba->aic_obj[i];
5392 pbe_eq = &phwi_context->be_eq[i];
5393 now = jiffies;
5394 if (!aic->jiffs || time_before(now, aic->jiffs) ||
5395 pbe_eq->cq_count < aic->eq_prev) {
5396 aic->jiffs = now;
5397 aic->eq_prev = pbe_eq->cq_count;
5398 continue;
5399 }
5400 delta = jiffies_to_msecs(now - aic->jiffs);
5401 pps = (((u32)(pbe_eq->cq_count - aic->eq_prev) * 1000) / delta);
5402 eqd = (pps / 1500) << 2;
5403
5404 if (eqd < 8)
5405 eqd = 0;
5406 eqd = min_t(u32, eqd, phwi_context->max_eqd);
5407 eqd = max_t(u32, eqd, phwi_context->min_eqd);
5408
5409 aic->jiffs = now;
5410 aic->eq_prev = pbe_eq->cq_count;
5411
5412 if (eqd != aic->prev_eqd) {
5413 set_eqd[num].delay_multiplier = (eqd * 65)/100;
5414 set_eqd[num].eq_id = pbe_eq->q.id;
5415 aic->prev_eqd = eqd;
5416 num++;
5417 }
5418 }
5419 if (num) {
5420 tag = be_cmd_modify_eq_delay(phba, set_eqd, num);
5421 if (tag)
88840332 5422 beiscsi_mccq_compl_wait(phba, tag, NULL, NULL);
73af08e1
JK		 5423 }
5424}
5425
a3d313ea
JK		 5426static void be_check_boot_session(struct beiscsi_hba *phba)
5427{
5428 if (beiscsi_setup_boot_info(phba))
5429 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5430 "BM_%d : Could not set up "
5431 "iSCSI boot info on async event.\n");
5432}
5433
7a158003
JSJ		 5434/*
5435 * beiscsi_hw_health_check()- Check adapter health
5436 * @work: work item to check HW health
5437 *
5438 * Check if adapter in an unrecoverable state or not.
5439 **/
5440static void
5441beiscsi_hw_health_check(struct work_struct *work)
5442{
5443 struct beiscsi_hba *phba =
5444 container_of(work, struct beiscsi_hba,
5445 beiscsi_hw_check_task.work);
5446
73af08e1
JK		 5447 be_eqd_update(phba);
5448
a3d313ea 5449 if (phba->state & BE_ADAPTER_CHECK_BOOT) {
3efde862
JSJ		 5450 if ((phba->get_boot > 0) && (!phba->boot_kset)) {
5451 phba->get_boot--;
5452 if (!(phba->get_boot % BE_GET_BOOT_TO))
5453 be_check_boot_session(phba);
5454 } else {
5455 phba->state &= ~BE_ADAPTER_CHECK_BOOT;
5456 phba->get_boot = 0;
5457 }
a3d313ea
JK		 5458 }
5459
7a158003
JSJ		 5460 beiscsi_ue_detect(phba);
5461
5462 schedule_delayed_work(&phba->beiscsi_hw_check_task,
5463 msecs_to_jiffies(1000));
5464}
5465
3567f36a
JK		 5466
5467static pci_ers_result_t beiscsi_eeh_err_detected(struct pci_dev *pdev,
5468 pci_channel_state_t state)
5469{
5470 struct beiscsi_hba *phba = NULL;
5471
5472 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5473 phba->state |= BE_ADAPTER_PCI_ERR;
5474
5475 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5476 "BM_%d : EEH error detected\n");
5477
5478 beiscsi_quiesce(phba, BEISCSI_EEH_UNLOAD);
5479
5480 if (state == pci_channel_io_perm_failure) {
5481 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5482 "BM_%d : EEH : State PERM Failure");
5483 return PCI_ERS_RESULT_DISCONNECT;
5484 }
5485
5486 pci_disable_device(pdev);
5487
5488 /* The error could cause the FW to trigger a flash debug dump.
5489 * Resetting the card while flash dump is in progress
5490 * can cause it not to recover; wait for it to finish.
5491 * Wait only for first function as it is needed only once per
5492 * adapter.
5493 **/
5494 if (pdev->devfn == 0)
5495 ssleep(30);
5496
5497 return PCI_ERS_RESULT_NEED_RESET;
5498}
5499
5500static pci_ers_result_t beiscsi_eeh_reset(struct pci_dev *pdev)
5501{
5502 struct beiscsi_hba *phba = NULL;
5503 int status = 0;
5504
5505 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5506
5507 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5508 "BM_%d : EEH Reset\n");
5509
5510 status = pci_enable_device(pdev);
5511 if (status)
5512 return PCI_ERS_RESULT_DISCONNECT;
5513
5514 pci_set_master(pdev);
5515 pci_set_power_state(pdev, PCI_D0);
5516 pci_restore_state(pdev);
5517
5518 /* Wait for the CHIP Reset to complete */
5519 status = be_chk_reset_complete(phba);
5520 if (!status) {
5521 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5522 "BM_%d : EEH Reset Completed\n");
5523 } else {
5524 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5525 "BM_%d : EEH Reset Completion Failure\n");
5526 return PCI_ERS_RESULT_DISCONNECT;
5527 }
5528
5529 pci_cleanup_aer_uncorrect_error_status(pdev);
5530 return PCI_ERS_RESULT_RECOVERED;
5531}
5532
5533static void beiscsi_eeh_resume(struct pci_dev *pdev)
5534{
5535 int ret = 0, i;
5536 struct be_eq_obj *pbe_eq;
5537 struct beiscsi_hba *phba = NULL;
5538 struct hwi_controller *phwi_ctrlr;
5539 struct hwi_context_memory *phwi_context;
5540
5541 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5542 pci_save_state(pdev);
5543
5544 if (enable_msix)
5545 find_num_cpus(phba);
5546 else
5547 phba->num_cpus = 1;
5548
5549 if (enable_msix) {
5550 beiscsi_msix_enable(phba);
5551 if (!phba->msix_enabled)
5552 phba->num_cpus = 1;
5553 }
5554
5555 ret = beiscsi_cmd_reset_function(phba);
5556 if (ret) {
5557 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5558 "BM_%d : Reset Failed\n");
5559 goto ret_err;
5560 }
5561
5562 ret = be_chk_reset_complete(phba);
5563 if (ret) {
5564 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5565 "BM_%d : Failed to get out of reset.\n");
5566 goto ret_err;
5567 }
5568
5569 beiscsi_get_params(phba);
5570 phba->shost->max_id = phba->params.cxns_per_ctrl;
5571 phba->shost->can_queue = phba->params.ios_per_ctrl;
5572 ret = hwi_init_controller(phba);
5573
5574 for (i = 0; i < MAX_MCC_CMD; i++) {
5575 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
5576 phba->ctrl.mcc_tag[i] = i + 1;
67296ad9 5577 phba->ctrl.mcc_tag_status[i + 1] = 0;
3567f36a
JK		 5578 phba->ctrl.mcc_tag_available++;
5579 }
5580
5581 phwi_ctrlr = phba->phwi_ctrlr;
5582 phwi_context = phwi_ctrlr->phwi_ctxt;
5583
89f8b33c 5584 for (i = 0; i < phba->num_cpus; i++) {
3567f36a 5585 pbe_eq = &phwi_context->be_eq[i];
511cbce2 5586 irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget,
89f8b33c 5587 be_iopoll);
3567f36a
JK		 5588 }
5589
89f8b33c
JA		 5590 i = (phba->msix_enabled) ? i : 0;
5591 /* Work item for MCC handling */
5592 pbe_eq = &phwi_context->be_eq[i];
5593 INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
5594
3567f36a
JK		 5595 ret = beiscsi_init_irqs(phba);
5596 if (ret < 0) {
5597 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5598 "BM_%d : beiscsi_eeh_resume - "
5599 "Failed to beiscsi_init_irqs\n");
5600 goto ret_err;
5601 }
5602
5603 hwi_enable_intr(phba);
5604 phba->state &= ~BE_ADAPTER_PCI_ERR;
5605
5606 return;
5607ret_err:
5608 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5609 "BM_%d : AER EEH Resume Failed\n");
5610}
5611
6f039790
GKH		 5612static int beiscsi_dev_probe(struct pci_dev *pcidev,
5613 const struct pci_device_id *id)
6733b39a
JK		 5614{
5615 struct beiscsi_hba *phba = NULL;
bfead3b2
JK		 5616 struct hwi_controller *phwi_ctrlr;
5617 struct hwi_context_memory *phwi_context;
5618 struct be_eq_obj *pbe_eq;
3567f36a 5619 int ret = 0, i;
6733b39a
JK		 5620
5621 ret = beiscsi_enable_pci(pcidev);
5622 if (ret < 0) {
99bc5d55
JSJ		 5623 dev_err(&pcidev->dev,
5624 "beiscsi_dev_probe - Failed to enable pci device\n");
6733b39a
JK		 5625 return ret;
5626 }
5627
5628 phba = beiscsi_hba_alloc(pcidev);
5629 if (!phba) {
99bc5d55
JSJ		 5630 dev_err(&pcidev->dev,
5631 "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
6733b39a
JK		 5632 goto disable_pci;
5633 }
5634
3567f36a
JK		 5635 /* Enable EEH reporting */
5636 ret = pci_enable_pcie_error_reporting(pcidev);
5637 if (ret)
5638 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5639 "BM_%d : PCIe Error Reporting "
5640 "Enabling Failed\n");
5641
5642 pci_save_state(pcidev);
5643
99bc5d55
JSJ		 5644 /* Initialize Driver configuration Paramters */
5645 beiscsi_hba_attrs_init(phba);
5646
e175defe 5647 phba->fw_timeout = false;
6c83185a 5648 phba->mac_addr_set = false;
e175defe
JSJ		 5649
5650
f98c96b0
JK		 5651 switch (pcidev->device) {
5652 case BE_DEVICE_ID1:
5653 case OC_DEVICE_ID1:
5654 case OC_DEVICE_ID2:
5655 phba->generation = BE_GEN2;
09a1093a 5656 phba->iotask_fn = beiscsi_iotask;
f98c96b0
JK		 5657 break;
5658 case BE_DEVICE_ID2:
5659 case OC_DEVICE_ID3:
5660 phba->generation = BE_GEN3;
09a1093a 5661 phba->iotask_fn = beiscsi_iotask;
f98c96b0 5662 break;
139a1b1e
JSJ		 5663 case OC_SKH_ID1:
5664 phba->generation = BE_GEN4;
09a1093a 5665 phba->iotask_fn = beiscsi_iotask_v2;
bf9131cb 5666 break;
f98c96b0
JK		 5667 default:
5668 phba->generation = 0;
5669 }
5670
6733b39a
JK		 5671 ret = be_ctrl_init(phba, pcidev);
5672 if (ret) {
99bc5d55
JSJ		 5673 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5674 "BM_%d : beiscsi_dev_probe-"
5675 "Failed in be_ctrl_init\n");
6733b39a
JK		 5676 goto hba_free;
5677 }
5678
cdaa4ded
JB		 5679 /*
5680 * FUNCTION_RESET should clean up any stale info in FW for this fn
5681 */
4d4d1ef8
JSJ		 5682 ret = beiscsi_cmd_reset_function(phba);
5683 if (ret) {
5684 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
92665a66 5685 "BM_%d : Reset Failed\n");
4d4d1ef8
JSJ		 5686 goto hba_free;
5687 }
5688 ret = be_chk_reset_complete(phba);
5689 if (ret) {
5690 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
92665a66 5691 "BM_%d : Failed to get out of reset.\n");
4d4d1ef8 5692 goto hba_free;
e9b91193
JK		 5693 }
5694
6733b39a
JK		 5695 spin_lock_init(&phba->io_sgl_lock);
5696 spin_lock_init(&phba->mgmt_sgl_lock);
5697 spin_lock_init(&phba->isr_lock);
8f09a3b9 5698 spin_lock_init(&phba->async_pdu_lock);
7da50879
JK		 5699 ret = mgmt_get_fw_config(&phba->ctrl, phba);
5700 if (ret != 0) {
99bc5d55
JSJ		 5701 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5702 "BM_%d : Error getting fw config\n");
7da50879
JK		 5703 goto free_port;
5704 }
53aefe25 5705 mgmt_get_port_name(&phba->ctrl, phba);
4570f161 5706 beiscsi_get_params(phba);
68c26a3a
JK		 5707
5708 if (enable_msix)
5709 find_num_cpus(phba);
5710 else
5711 phba->num_cpus = 1;
5712
5713 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
5714 "BM_%d : num_cpus = %d\n",
5715 phba->num_cpus);
5716
5717 if (enable_msix) {
5718 beiscsi_msix_enable(phba);
5719 if (!phba->msix_enabled)
5720 phba->num_cpus = 1;
5721 }
5722
843ae752 5723 phba->shost->max_id = phba->params.cxns_per_ctrl;
aa874f07 5724 phba->shost->can_queue = phba->params.ios_per_ctrl;
6733b39a
JK		 5725 ret = beiscsi_init_port(phba);
5726 if (ret < 0) {
99bc5d55
JSJ		 5727 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5728 "BM_%d : beiscsi_dev_probe-"
5729 "Failed in beiscsi_init_port\n");
6733b39a
JK		 5730 goto free_port;
5731 }
5732
3567f36a 5733 for (i = 0; i < MAX_MCC_CMD; i++) {
756d29c8
JK		 5734 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
5735 phba->ctrl.mcc_tag[i] = i + 1;
67296ad9 5736 phba->ctrl.mcc_tag_status[i + 1] = 0;
756d29c8 5737 phba->ctrl.mcc_tag_available++;
1957aa7f 5738 memset(&phba->ctrl.ptag_state[i].tag_mem_state, 0,
8fc01eaa 5739 sizeof(struct be_dma_mem));
756d29c8
JK		 5740 }
5741
5742 phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
5743
72fb46a9 5744 snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq",
6733b39a 5745 phba->shost->host_no);
d8537548 5746 phba->wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 1, phba->wq_name);
6733b39a 5747 if (!phba->wq) {
99bc5d55
JSJ		 5748 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5749 "BM_%d : beiscsi_dev_probe-"
5750 "Failed to allocate work queue\n");
6733b39a
JK		 5751 goto free_twq;
5752 }
5753
7a158003
JSJ		 5754 INIT_DELAYED_WORK(&phba->beiscsi_hw_check_task,
5755 beiscsi_hw_health_check);
6733b39a 5756
bfead3b2
JK		 5757 phwi_ctrlr = phba->phwi_ctrlr;
5758 phwi_context = phwi_ctrlr->phwi_ctxt;
72fb46a9 5759
89f8b33c 5760 for (i = 0; i < phba->num_cpus; i++) {
72fb46a9 5761 pbe_eq = &phwi_context->be_eq[i];
511cbce2 5762 irq_poll_init(&pbe_eq->iopoll, be_iopoll_budget,
89f8b33c 5763 be_iopoll);
6733b39a 5764 }
72fb46a9 5765
89f8b33c
JA		 5766 i = (phba->msix_enabled) ? i : 0;
5767 /* Work item for MCC handling */
5768 pbe_eq = &phwi_context->be_eq[i];
5769 INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
5770
6733b39a
JK		 5771 ret = beiscsi_init_irqs(phba);
5772 if (ret < 0) {
99bc5d55
JSJ		 5773 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5774 "BM_%d : beiscsi_dev_probe-"
5775 "Failed to beiscsi_init_irqs\n");
6733b39a
JK		 5776 goto free_blkenbld;
5777 }
238f6b72 5778 hwi_enable_intr(phba);
f457a46f 5779
0598b8af
JK		 5780 if (iscsi_host_add(phba->shost, &phba->pcidev->dev))
5781 goto free_blkenbld;
5782
f457a46f
MC		 5783 if (beiscsi_setup_boot_info(phba))
5784 /*
5785 * log error but continue, because we may not be using
5786 * iscsi boot.
5787 */
99bc5d55
JSJ		 5788 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5789 "BM_%d : Could not set up "
5790 "iSCSI boot info.\n");
f457a46f 5791
0e43895e 5792 beiscsi_create_def_ifaces(phba);
7a158003
JSJ		 5793 schedule_delayed_work(&phba->beiscsi_hw_check_task,
5794 msecs_to_jiffies(1000));
5795
99bc5d55
JSJ		 5796 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
5797 "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
6733b39a
JK		 5798 return 0;
5799
6733b39a
JK		 5800free_blkenbld:
5801 destroy_workqueue(phba->wq);
89f8b33c
JA		 5802 for (i = 0; i < phba->num_cpus; i++) {
5803 pbe_eq = &phwi_context->be_eq[i];
511cbce2 5804 irq_poll_disable(&pbe_eq->iopoll);
89f8b33c 5805 }
6733b39a
JK		 5806free_twq:
5807 beiscsi_clean_port(phba);
5808 beiscsi_free_mem(phba);
5809free_port:
5810 pci_free_consistent(phba->pcidev,
5811 phba->ctrl.mbox_mem_alloced.size,
5812 phba->ctrl.mbox_mem_alloced.va,
5813 phba->ctrl.mbox_mem_alloced.dma);
5814 beiscsi_unmap_pci_function(phba);
5815hba_free:
238f6b72
JK		 5816 if (phba->msix_enabled)
5817 pci_disable_msix(phba->pcidev);
6733b39a
JK		 5818 pci_dev_put(phba->pcidev);
5819 iscsi_host_free(phba->shost);
2e7cee02 5820 pci_set_drvdata(pcidev, NULL);
6733b39a 5821disable_pci:
e307f3ac 5822 pci_release_regions(pcidev);
6733b39a
JK		 5823 pci_disable_device(pcidev);
5824 return ret;
5825}
5826
3567f36a
JK		 5827static struct pci_error_handlers beiscsi_eeh_handlers = {
5828 .error_detected = beiscsi_eeh_err_detected,
5829 .slot_reset = beiscsi_eeh_reset,
5830 .resume = beiscsi_eeh_resume,
5831};
5832
6733b39a
JK		 5833struct iscsi_transport beiscsi_iscsi_transport = {
5834 .owner = THIS_MODULE,
5835 .name = DRV_NAME,
9db0fb3a 5836 .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
6733b39a 5837 CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
6733b39a
JK		 5838 .create_session = beiscsi_session_create,
5839 .destroy_session = beiscsi_session_destroy,
5840 .create_conn = beiscsi_conn_create,
5841 .bind_conn = beiscsi_conn_bind,
5842 .destroy_conn = iscsi_conn_teardown,
3128c6c7 5843 .attr_is_visible = be2iscsi_attr_is_visible,
0e43895e
MC		 5844 .set_iface_param = be2iscsi_iface_set_param,
5845 .get_iface_param = be2iscsi_iface_get_param,
6733b39a 5846 .set_param = beiscsi_set_param,
c7f7fd5b 5847 .get_conn_param = iscsi_conn_get_param,
6733b39a
JK		 5848 .get_session_param = iscsi_session_get_param,
5849 .get_host_param = beiscsi_get_host_param,
5850 .start_conn = beiscsi_conn_start,
fa95d206 5851 .stop_conn = iscsi_conn_stop,
6733b39a
JK		 5852 .send_pdu = iscsi_conn_send_pdu,
5853 .xmit_task = beiscsi_task_xmit,
5854 .cleanup_task = beiscsi_cleanup_task,
5855 .alloc_pdu = beiscsi_alloc_pdu,
5856 .parse_pdu_itt = beiscsi_parse_pdu,
5857 .get_stats = beiscsi_conn_get_stats,
c7f7fd5b 5858 .get_ep_param = beiscsi_ep_get_param,
6733b39a
JK		 5859 .ep_connect = beiscsi_ep_connect,
5860 .ep_poll = beiscsi_ep_poll,
5861 .ep_disconnect = beiscsi_ep_disconnect,
5862 .session_recovery_timedout = iscsi_session_recovery_timedout,
ffce3e2e 5863 .bsg_request = beiscsi_bsg_request,
6733b39a
JK		 5864};
5865
5866static struct pci_driver beiscsi_pci_driver = {
5867 .name = DRV_NAME,
5868 .probe = beiscsi_dev_probe,
5869 .remove = beiscsi_remove,
3567f36a
JK		 5870 .id_table = beiscsi_pci_id_table,
5871 .err_handler = &beiscsi_eeh_handlers
6733b39a
JK		 5872};
5873
bfead3b2 5874
6733b39a
JK		 5875static int __init beiscsi_module_init(void)
5876{
5877 int ret;
5878
5879 beiscsi_scsi_transport =
5880 iscsi_register_transport(&beiscsi_iscsi_transport);
5881 if (!beiscsi_scsi_transport) {
99bc5d55
JSJ		 5882 printk(KERN_ERR
5883 "beiscsi_module_init - Unable to register beiscsi transport.\n");
f55a24f2 5884 return -ENOMEM;
6733b39a 5885 }
99bc5d55
JSJ		 5886 printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
5887 &beiscsi_iscsi_transport);
6733b39a
JK		 5888
5889 ret = pci_register_driver(&beiscsi_pci_driver);
5890 if (ret) {
99bc5d55
JSJ		 5891 printk(KERN_ERR
5892 "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
6733b39a
JK		 5893 goto unregister_iscsi_transport;
5894 }
5895 return 0;
5896
5897unregister_iscsi_transport:
5898 iscsi_unregister_transport(&beiscsi_iscsi_transport);
5899 return ret;
5900}
5901
5902static void __exit beiscsi_module_exit(void)
5903{
5904 pci_unregister_driver(&beiscsi_pci_driver);
5905 iscsi_unregister_transport(&beiscsi_iscsi_transport);
5906}
5907
5908module_init(beiscsi_module_init);
5909module_exit(beiscsi_module_exit);
Linux 6.x block layer and io_uring tree(s)