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be2iscsi : Fix memory leak in the unload path
[linux-2.6-block.git] / drivers / scsi / be2iscsi / be_main.c
CommitLineData
6733b39a 1/**
4627de93 2 * Copyright (C) 2005 - 2015 Avago Technologies
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
4627de93 10 * Written by: Jayamohan Kallickal (jayamohan.kallickal@avagotech.com)
6733b39a
JK		 11 *
12 * Contact Information:
4627de93 13 * linux-drivers@avagotech.com
6733b39a 14 *
4627de93 15 * Avago Technologies
255fa9a3
JK		 16 * 3333 Susan Street
17 * Costa Mesa, CA 92626
6733b39a 18 */
255fa9a3 19
6733b39a
JK		 20#include <linux/reboot.h>
21#include <linux/delay.h>
5a0e3ad6 22#include <linux/slab.h>
6733b39a
JK		 23#include <linux/interrupt.h>
24#include <linux/blkdev.h>
25#include <linux/pci.h>
26#include <linux/string.h>
27#include <linux/kernel.h>
28#include <linux/semaphore.h>
c7acc5b8 29#include <linux/iscsi_boot_sysfs.h>
acf3368f 30#include <linux/module.h>
ffce3e2e 31#include <linux/bsg-lib.h>
6733b39a
JK		 32
33#include <scsi/libiscsi.h>
ffce3e2e
JK		 34#include <scsi/scsi_bsg_iscsi.h>
35#include <scsi/scsi_netlink.h>
6733b39a
JK		 36#include <scsi/scsi_transport_iscsi.h>
37#include <scsi/scsi_transport.h>
38#include <scsi/scsi_cmnd.h>
39#include <scsi/scsi_device.h>
40#include <scsi/scsi_host.h>
41#include <scsi/scsi.h>
42#include "be_main.h"
43#include "be_iscsi.h"
44#include "be_mgmt.h"
0a513dd8 45#include "be_cmds.h"
6733b39a
JK		 46
47static unsigned int be_iopoll_budget = 10;
48static unsigned int be_max_phys_size = 64;
bfead3b2 49static unsigned int enable_msix = 1;
6733b39a 50
6733b39a 51MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
76d15dbd 52MODULE_VERSION(BUILD_STR);
4627de93 53MODULE_AUTHOR("Avago Technologies");
6733b39a
JK		 54MODULE_LICENSE("GPL");
55module_param(be_iopoll_budget, int, 0);
56module_param(enable_msix, int, 0);
57module_param(be_max_phys_size, uint, S_IRUGO);
99bc5d55
JSJ		 58MODULE_PARM_DESC(be_max_phys_size,
59 "Maximum Size (In Kilobytes) of physically contiguous "
60 "memory that can be allocated. Range is 16 - 128");
61
62#define beiscsi_disp_param(_name)\
63ssize_t \
64beiscsi_##_name##_disp(struct device *dev,\
65 struct device_attribute *attrib, char *buf) \
66{ \
67 struct Scsi_Host *shost = class_to_shost(dev);\
68 struct beiscsi_hba *phba = iscsi_host_priv(shost); \
69 uint32_t param_val = 0; \
70 param_val = phba->attr_##_name;\
71 return snprintf(buf, PAGE_SIZE, "%d\n",\
72 phba->attr_##_name);\
73}
74
75#define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
76int \
77beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
78{\
79 if (val >= _minval && val <= _maxval) {\
80 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
81 "BA_%d : beiscsi_"#_name" updated "\
82 "from 0x%x ==> 0x%x\n",\
83 phba->attr_##_name, val); \
84 phba->attr_##_name = val;\
85 return 0;\
86 } \
87 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
88 "BA_%d beiscsi_"#_name" attribute "\
89 "cannot be updated to 0x%x, "\
90 "range allowed is ["#_minval" - "#_maxval"]\n", val);\
91 return -EINVAL;\
92}
93
94#define beiscsi_store_param(_name) \
95ssize_t \
96beiscsi_##_name##_store(struct device *dev,\
97 struct device_attribute *attr, const char *buf,\
98 size_t count) \
99{ \
100 struct Scsi_Host *shost = class_to_shost(dev);\
101 struct beiscsi_hba *phba = iscsi_host_priv(shost);\
102 uint32_t param_val = 0;\
103 if (!isdigit(buf[0]))\
104 return -EINVAL;\
105 if (sscanf(buf, "%i", &param_val) != 1)\
106 return -EINVAL;\
107 if (beiscsi_##_name##_change(phba, param_val) == 0) \
108 return strlen(buf);\
109 else \
110 return -EINVAL;\
111}
112
113#define beiscsi_init_param(_name, _minval, _maxval, _defval) \
114int \
115beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
116{ \
117 if (val >= _minval && val <= _maxval) {\
118 phba->attr_##_name = val;\
119 return 0;\
120 } \
121 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
122 "BA_%d beiscsi_"#_name" attribute " \
123 "cannot be updated to 0x%x, "\
124 "range allowed is ["#_minval" - "#_maxval"]\n", val);\
125 phba->attr_##_name = _defval;\
126 return -EINVAL;\
127}
128
129#define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
130static uint beiscsi_##_name = _defval;\
131module_param(beiscsi_##_name, uint, S_IRUGO);\
132MODULE_PARM_DESC(beiscsi_##_name, _descp);\
133beiscsi_disp_param(_name)\
134beiscsi_change_param(_name, _minval, _maxval, _defval)\
135beiscsi_store_param(_name)\
136beiscsi_init_param(_name, _minval, _maxval, _defval)\
137DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
138 beiscsi_##_name##_disp, beiscsi_##_name##_store)
139
140/*
141 * When new log level added update the
142 * the MAX allowed value for log_enable
143 */
144BEISCSI_RW_ATTR(log_enable, 0x00,
145 0xFF, 0x00, "Enable logging Bit Mask\n"
146 "\t\t\t\tInitialization Events : 0x01\n"
147 "\t\t\t\tMailbox Events : 0x02\n"
148 "\t\t\t\tMiscellaneous Events : 0x04\n"
149 "\t\t\t\tError Handling : 0x08\n"
150 "\t\t\t\tIO Path Events : 0x10\n"
afb96058
JK		 151 "\t\t\t\tConfiguration Path : 0x20\n"
152 "\t\t\t\tiSCSI Protocol : 0x40\n");
99bc5d55 153
5cac7596 154DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
26000db7 155DEVICE_ATTR(beiscsi_adapter_family, S_IRUGO, beiscsi_adap_family_disp, NULL);
22661e25 156DEVICE_ATTR(beiscsi_fw_ver, S_IRUGO, beiscsi_fw_ver_disp, NULL);
d3fea9af 157DEVICE_ATTR(beiscsi_phys_port, S_IRUGO, beiscsi_phys_port_disp, NULL);
6103c1f7
JK		 158DEVICE_ATTR(beiscsi_active_session_count, S_IRUGO,
159 beiscsi_active_session_disp, NULL);
160DEVICE_ATTR(beiscsi_free_session_count, S_IRUGO,
161 beiscsi_free_session_disp, NULL);
99bc5d55
JSJ		 162struct device_attribute *beiscsi_attrs[] = {
163 &dev_attr_beiscsi_log_enable,
5cac7596 164 &dev_attr_beiscsi_drvr_ver,
26000db7 165 &dev_attr_beiscsi_adapter_family,
22661e25 166 &dev_attr_beiscsi_fw_ver,
6103c1f7
JK		 167 &dev_attr_beiscsi_active_session_count,
168 &dev_attr_beiscsi_free_session_count,
d3fea9af 169 &dev_attr_beiscsi_phys_port,
99bc5d55
JSJ		 170 NULL,
171};
6733b39a 172
6763daae
JSJ		 173static char const *cqe_desc[] = {
174 "RESERVED_DESC",
175 "SOL_CMD_COMPLETE",
176 "SOL_CMD_KILLED_DATA_DIGEST_ERR",
177 "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
178 "CXN_KILLED_BURST_LEN_MISMATCH",
179 "CXN_KILLED_AHS_RCVD",
180 "CXN_KILLED_HDR_DIGEST_ERR",
181 "CXN_KILLED_UNKNOWN_HDR",
182 "CXN_KILLED_STALE_ITT_TTT_RCVD",
183 "CXN_KILLED_INVALID_ITT_TTT_RCVD",
184 "CXN_KILLED_RST_RCVD",
185 "CXN_KILLED_TIMED_OUT",
186 "CXN_KILLED_RST_SENT",
187 "CXN_KILLED_FIN_RCVD",
188 "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
189 "CXN_KILLED_BAD_WRB_INDEX_ERROR",
190 "CXN_KILLED_OVER_RUN_RESIDUAL",
191 "CXN_KILLED_UNDER_RUN_RESIDUAL",
192 "CMD_KILLED_INVALID_STATSN_RCVD",
193 "CMD_KILLED_INVALID_R2T_RCVD",
194 "CMD_CXN_KILLED_LUN_INVALID",
195 "CMD_CXN_KILLED_ICD_INVALID",
196 "CMD_CXN_KILLED_ITT_INVALID",
197 "CMD_CXN_KILLED_SEQ_OUTOFORDER",
198 "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
199 "CXN_INVALIDATE_NOTIFY",
200 "CXN_INVALIDATE_INDEX_NOTIFY",
201 "CMD_INVALIDATED_NOTIFY",
202 "UNSOL_HDR_NOTIFY",
203 "UNSOL_DATA_NOTIFY",
204 "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
205 "DRIVERMSG_NOTIFY",
206 "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
207 "SOL_CMD_KILLED_DIF_ERR",
208 "CXN_KILLED_SYN_RCVD",
209 "CXN_KILLED_IMM_DATA_RCVD"
210};
211
6733b39a
JK		 212static int beiscsi_slave_configure(struct scsi_device *sdev)
213{
214 blk_queue_max_segment_size(sdev->request_queue, 65536);
215 return 0;
216}
217
4183122d
JK		 218static int beiscsi_eh_abort(struct scsi_cmnd *sc)
219{
220 struct iscsi_cls_session *cls_session;
221 struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
222 struct beiscsi_io_task *aborted_io_task;
223 struct iscsi_conn *conn;
224 struct beiscsi_conn *beiscsi_conn;
225 struct beiscsi_hba *phba;
226 struct iscsi_session *session;
227 struct invalidate_command_table *inv_tbl;
3cbb7a74 228 struct be_dma_mem nonemb_cmd;
4183122d 229 unsigned int cid, tag, num_invalidate;
1957aa7f 230 int rc;
4183122d
JK		 231
232 cls_session = starget_to_session(scsi_target(sc->device));
233 session = cls_session->dd_data;
234
659743b0 235 spin_lock_bh(&session->frwd_lock);
4183122d
JK		 236 if (!aborted_task || !aborted_task->sc) {
237 /* we raced */
659743b0 238 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 239 return SUCCESS;
240 }
241
242 aborted_io_task = aborted_task->dd_data;
243 if (!aborted_io_task->scsi_cmnd) {
244 /* raced or invalid command */
659743b0 245 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 246 return SUCCESS;
247 }
659743b0 248 spin_unlock_bh(&session->frwd_lock);
7626c06b
JK		 249 /* Invalidate WRB Posted for this Task */
250 AMAP_SET_BITS(struct amap_iscsi_wrb, invld,
251 aborted_io_task->pwrb_handle->pwrb,
252 1);
253
4183122d
JK		 254 conn = aborted_task->conn;
255 beiscsi_conn = conn->dd_data;
256 phba = beiscsi_conn->phba;
257
258 /* invalidate iocb */
259 cid = beiscsi_conn->beiscsi_conn_cid;
260 inv_tbl = phba->inv_tbl;
261 memset(inv_tbl, 0x0, sizeof(*inv_tbl));
262 inv_tbl->cid = cid;
263 inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
264 num_invalidate = 1;
3cbb7a74
JK		 265 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
266 sizeof(struct invalidate_commands_params_in),
267 &nonemb_cmd.dma);
268 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 269 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
270 "BM_%d : Failed to allocate memory for"
271 "mgmt_invalidate_icds\n");
3cbb7a74
JK		 272 return FAILED;
273 }
274 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
275
276 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
277 cid, &nonemb_cmd);
4183122d 278 if (!tag) {
99bc5d55
JSJ		 279 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
280 "BM_%d : mgmt_invalidate_icds could not be"
281 "submitted\n");
3cbb7a74
JK		 282 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
283 nonemb_cmd.va, nonemb_cmd.dma);
284
4183122d 285 return FAILED;
4183122d 286 }
e175defe 287
1957aa7f
JK		 288 rc = beiscsi_mccq_compl(phba, tag, NULL, &nonemb_cmd);
289 if (rc != -EBUSY)
290 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
291 nonemb_cmd.va, nonemb_cmd.dma);
292
4183122d
JK		 293 return iscsi_eh_abort(sc);
294}
295
296static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
297{
298 struct iscsi_task *abrt_task;
299 struct beiscsi_io_task *abrt_io_task;
300 struct iscsi_conn *conn;
301 struct beiscsi_conn *beiscsi_conn;
302 struct beiscsi_hba *phba;
303 struct iscsi_session *session;
304 struct iscsi_cls_session *cls_session;
305 struct invalidate_command_table *inv_tbl;
3cbb7a74 306 struct be_dma_mem nonemb_cmd;
4183122d 307 unsigned int cid, tag, i, num_invalidate;
1957aa7f 308 int rc;
4183122d
JK		 309
310 /* invalidate iocbs */
311 cls_session = starget_to_session(scsi_target(sc->device));
312 session = cls_session->dd_data;
659743b0 313 spin_lock_bh(&session->frwd_lock);
db7f7709 314 if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
659743b0 315 spin_unlock_bh(&session->frwd_lock);
db7f7709
JK		 316 return FAILED;
317 }
4183122d
JK		 318 conn = session->leadconn;
319 beiscsi_conn = conn->dd_data;
320 phba = beiscsi_conn->phba;
321 cid = beiscsi_conn->beiscsi_conn_cid;
322 inv_tbl = phba->inv_tbl;
323 memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
324 num_invalidate = 0;
325 for (i = 0; i < conn->session->cmds_max; i++) {
326 abrt_task = conn->session->cmds[i];
327 abrt_io_task = abrt_task->dd_data;
328 if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
329 continue;
330
126e964a 331 if (sc->device->lun != abrt_task->sc->device->lun)
4183122d
JK		 332 continue;
333
7626c06b
JK		 334 /* Invalidate WRB Posted for this Task */
335 AMAP_SET_BITS(struct amap_iscsi_wrb, invld,
336 abrt_io_task->pwrb_handle->pwrb,
337 1);
338
4183122d
JK		 339 inv_tbl->cid = cid;
340 inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
341 num_invalidate++;
342 inv_tbl++;
343 }
659743b0 344 spin_unlock_bh(&session->frwd_lock);
4183122d
JK		 345 inv_tbl = phba->inv_tbl;
346
3cbb7a74
JK		 347 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
348 sizeof(struct invalidate_commands_params_in),
349 &nonemb_cmd.dma);
350 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 351 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
352 "BM_%d : Failed to allocate memory for"
353 "mgmt_invalidate_icds\n");
3cbb7a74
JK		 354 return FAILED;
355 }
356 nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
357 memset(nonemb_cmd.va, 0, nonemb_cmd.size);
358 tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
359 cid, &nonemb_cmd);
4183122d 360 if (!tag) {
99bc5d55
JSJ		 361 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
362 "BM_%d : mgmt_invalidate_icds could not be"
363 " submitted\n");
3cbb7a74
JK		 364 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
365 nonemb_cmd.va, nonemb_cmd.dma);
4183122d 366 return FAILED;
4183122d 367 }
e175defe 368
1957aa7f
JK		 369 rc = beiscsi_mccq_compl(phba, tag, NULL, &nonemb_cmd);
370 if (rc != -EBUSY)
371 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
372 nonemb_cmd.va, nonemb_cmd.dma);
4183122d 373 return iscsi_eh_device_reset(sc);
4183122d
JK		 374}
375
c7acc5b8
JK		 376static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
377{
378 struct beiscsi_hba *phba = data;
f457a46f
MC		 379 struct mgmt_session_info *boot_sess = &phba->boot_sess;
380 struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
c7acc5b8
JK		 381 char *str = buf;
382 int rc;
383
384 switch (type) {
385 case ISCSI_BOOT_TGT_NAME:
386 rc = sprintf(buf, "%.*s\n",
f457a46f
MC		 387 (int)strlen(boot_sess->target_name),
388 (char *)&boot_sess->target_name);
c7acc5b8
JK		 389 break;
390 case ISCSI_BOOT_TGT_IP_ADDR:
f457a46f 391 if (boot_conn->dest_ipaddr.ip_type == 0x1)
c7acc5b8 392 rc = sprintf(buf, "%pI4\n",
0e43895e 393 (char *)&boot_conn->dest_ipaddr.addr);
c7acc5b8
JK		 394 else
395 rc = sprintf(str, "%pI6\n",
0e43895e 396 (char *)&boot_conn->dest_ipaddr.addr);
c7acc5b8
JK		 397 break;
398 case ISCSI_BOOT_TGT_PORT:
f457a46f 399 rc = sprintf(str, "%d\n", boot_conn->dest_port);
c7acc5b8
JK		 400 break;
401
402 case ISCSI_BOOT_TGT_CHAP_NAME:
403 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 404 boot_conn->negotiated_login_options.auth_data.chap.
405 target_chap_name_length,
406 (char *)&boot_conn->negotiated_login_options.
407 auth_data.chap.target_chap_name);
c7acc5b8
JK		 408 break;
409 case ISCSI_BOOT_TGT_CHAP_SECRET:
410 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 411 boot_conn->negotiated_login_options.auth_data.chap.
412 target_secret_length,
413 (char *)&boot_conn->negotiated_login_options.
414 auth_data.chap.target_secret);
c7acc5b8
JK		 415 break;
416 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
417 rc = sprintf(str, "%.*s\n",
f457a46f
MC		 418 boot_conn->negotiated_login_options.auth_data.chap.
419 intr_chap_name_length,
420 (char *)&boot_conn->negotiated_login_options.
421 auth_data.chap.intr_chap_name);
c7acc5b8
JK		 422 break;
423 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
f457a46f
MC		 424 rc = sprintf(str, "%.*s\n",
425 boot_conn->negotiated_login_options.auth_data.chap.
426 intr_secret_length,
427 (char *)&boot_conn->negotiated_login_options.
428 auth_data.chap.intr_secret);
c7acc5b8
JK		 429 break;
430 case ISCSI_BOOT_TGT_FLAGS:
f457a46f 431 rc = sprintf(str, "2\n");
c7acc5b8
JK		 432 break;
433 case ISCSI_BOOT_TGT_NIC_ASSOC:
f457a46f 434 rc = sprintf(str, "0\n");
c7acc5b8
JK		 435 break;
436 default:
437 rc = -ENOSYS;
438 break;
439 }
440 return rc;
441}
442
443static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
444{
445 struct beiscsi_hba *phba = data;
446 char *str = buf;
447 int rc;
448
449 switch (type) {
450 case ISCSI_BOOT_INI_INITIATOR_NAME:
451 rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
452 break;
453 default:
454 rc = -ENOSYS;
455 break;
456 }
457 return rc;
458}
459
460static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
461{
462 struct beiscsi_hba *phba = data;
463 char *str = buf;
464 int rc;
465
466 switch (type) {
467 case ISCSI_BOOT_ETH_FLAGS:
f457a46f 468 rc = sprintf(str, "2\n");
c7acc5b8
JK		 469 break;
470 case ISCSI_BOOT_ETH_INDEX:
f457a46f 471 rc = sprintf(str, "0\n");
c7acc5b8
JK		 472 break;
473 case ISCSI_BOOT_ETH_MAC:
0e43895e
MC		 474 rc = beiscsi_get_macaddr(str, phba);
475 break;
c7acc5b8
JK		 476 default:
477 rc = -ENOSYS;
478 break;
479 }
480 return rc;
481}
482
483
587a1f16 484static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
c7acc5b8 485{
587a1f16 486 umode_t rc;
c7acc5b8
JK		 487
488 switch (type) {
489 case ISCSI_BOOT_TGT_NAME:
490 case ISCSI_BOOT_TGT_IP_ADDR:
491 case ISCSI_BOOT_TGT_PORT:
492 case ISCSI_BOOT_TGT_CHAP_NAME:
493 case ISCSI_BOOT_TGT_CHAP_SECRET:
494 case ISCSI_BOOT_TGT_REV_CHAP_NAME:
495 case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
496 case ISCSI_BOOT_TGT_NIC_ASSOC:
497 case ISCSI_BOOT_TGT_FLAGS:
498 rc = S_IRUGO;
499 break;
500 default:
501 rc = 0;
502 break;
503 }
504 return rc;
505}
506
587a1f16 507static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
c7acc5b8 508{
587a1f16 509 umode_t rc;
c7acc5b8
JK		 510
511 switch (type) {
512 case ISCSI_BOOT_INI_INITIATOR_NAME:
513 rc = S_IRUGO;
514 break;
515 default:
516 rc = 0;
517 break;
518 }
519 return rc;
520}
521
522
587a1f16 523static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
c7acc5b8 524{
587a1f16 525 umode_t rc;
c7acc5b8
JK		 526
527 switch (type) {
528 case ISCSI_BOOT_ETH_FLAGS:
529 case ISCSI_BOOT_ETH_MAC:
530 case ISCSI_BOOT_ETH_INDEX:
531 rc = S_IRUGO;
532 break;
533 default:
534 rc = 0;
535 break;
536 }
537 return rc;
538}
539
bfead3b2 540/*------------------- PCI Driver operations and data ----------------- */
9baa3c34 541static const struct pci_device_id beiscsi_pci_id_table[] = {
bfead3b2 542 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
f98c96b0 543 { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
bfead3b2
JK		 544 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
545 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
546 { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
139a1b1e 547 { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) },
bfead3b2
JK		 548 { 0 }
549};
550MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
551
99bc5d55 552
6733b39a
JK		 553static struct scsi_host_template beiscsi_sht = {
554 .module = THIS_MODULE,
4627de93 555 .name = "Avago Technologies 10Gbe open-iscsi Initiator Driver",
6733b39a
JK		 556 .proc_name = DRV_NAME,
557 .queuecommand = iscsi_queuecommand,
db5ed4df 558 .change_queue_depth = scsi_change_queue_depth,
6733b39a
JK		 559 .slave_configure = beiscsi_slave_configure,
560 .target_alloc = iscsi_target_alloc,
4183122d
JK		 561 .eh_abort_handler = beiscsi_eh_abort,
562 .eh_device_reset_handler = beiscsi_eh_device_reset,
309ce156 563 .eh_target_reset_handler = iscsi_eh_session_reset,
99bc5d55 564 .shost_attrs = beiscsi_attrs,
6733b39a
JK		 565 .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
566 .can_queue = BE2_IO_DEPTH,
567 .this_id = -1,
568 .max_sectors = BEISCSI_MAX_SECTORS,
569 .cmd_per_lun = BEISCSI_CMD_PER_LUN,
570 .use_clustering = ENABLE_CLUSTERING,
ffce3e2e 571 .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
c40ecc12 572 .track_queue_depth = 1,
6733b39a 573};
6733b39a 574
bfead3b2 575static struct scsi_transport_template *beiscsi_scsi_transport;
6733b39a
JK		 576
577static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
578{
579 struct beiscsi_hba *phba;
580 struct Scsi_Host *shost;
581
582 shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
583 if (!shost) {
99bc5d55
JSJ		 584 dev_err(&pcidev->dev,
585 "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
6733b39a
JK		 586 return NULL;
587 }
6733b39a
JK		 588 shost->max_id = BE2_MAX_SESSIONS;
589 shost->max_channel = 0;
590 shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
591 shost->max_lun = BEISCSI_NUM_MAX_LUN;
592 shost->transportt = beiscsi_scsi_transport;
6733b39a
JK		 593 phba = iscsi_host_priv(shost);
594 memset(phba, 0, sizeof(*phba));
595 phba->shost = shost;
596 phba->pcidev = pci_dev_get(pcidev);
2807afb7 597 pci_set_drvdata(pcidev, phba);
0e43895e 598 phba->interface_handle = 0xFFFFFFFF;
6733b39a 599
6733b39a 600 return phba;
6733b39a
JK		 601}
602
603static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
604{
605 if (phba->csr_va) {
606 iounmap(phba->csr_va);
607 phba->csr_va = NULL;
608 }
609 if (phba->db_va) {
610 iounmap(phba->db_va);
611 phba->db_va = NULL;
612 }
613 if (phba->pci_va) {
614 iounmap(phba->pci_va);
615 phba->pci_va = NULL;
616 }
617}
618
619static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
620 struct pci_dev *pcidev)
621{
622 u8 __iomem *addr;
f98c96b0 623 int pcicfg_reg;
6733b39a
JK		 624
625 addr = ioremap_nocache(pci_resource_start(pcidev, 2),
626 pci_resource_len(pcidev, 2));
627 if (addr == NULL)
628 return -ENOMEM;
629 phba->ctrl.csr = addr;
630 phba->csr_va = addr;
631 phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
632
633 addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
634 if (addr == NULL)
635 goto pci_map_err;
636 phba->ctrl.db = addr;
637 phba->db_va = addr;
638 phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
639
f98c96b0
JK		 640 if (phba->generation == BE_GEN2)
641 pcicfg_reg = 1;
642 else
643 pcicfg_reg = 0;
644
645 addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
646 pci_resource_len(pcidev, pcicfg_reg));
647
6733b39a
JK		 648 if (addr == NULL)
649 goto pci_map_err;
650 phba->ctrl.pcicfg = addr;
651 phba->pci_va = addr;
f98c96b0 652 phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
6733b39a
JK		 653 return 0;
654
655pci_map_err:
656 beiscsi_unmap_pci_function(phba);
657 return -ENOMEM;
658}
659
660static int beiscsi_enable_pci(struct pci_dev *pcidev)
661{
662 int ret;
663
664 ret = pci_enable_device(pcidev);
665 if (ret) {
99bc5d55
JSJ		 666 dev_err(&pcidev->dev,
667 "beiscsi_enable_pci - enable device failed\n");
6733b39a
JK		 668 return ret;
669 }
670
e307f3ac
JSJ		 671 ret = pci_request_regions(pcidev, DRV_NAME);
672 if (ret) {
673 dev_err(&pcidev->dev,
674 "beiscsi_enable_pci - request region failed\n");
675 goto pci_dev_disable;
676 }
677
bfead3b2 678 pci_set_master(pcidev);
6c57625b
JK		 679 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(64));
680 if (ret) {
681 ret = pci_set_dma_mask(pcidev, DMA_BIT_MASK(32));
682 if (ret) {
683 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
e307f3ac 684 goto pci_region_release;
6c57625b
JK		 685 } else {
686 ret = pci_set_consistent_dma_mask(pcidev,
687 DMA_BIT_MASK(32));
688 }
689 } else {
690 ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64));
6733b39a
JK		 691 if (ret) {
692 dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
e307f3ac 693 goto pci_region_release;
6733b39a
JK		 694 }
695 }
696 return 0;
e307f3ac
JSJ		 697
698pci_region_release:
699 pci_release_regions(pcidev);
700pci_dev_disable:
701 pci_disable_device(pcidev);
702
703 return ret;
6733b39a
JK		 704}
705
706static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
707{
708 struct be_ctrl_info *ctrl = &phba->ctrl;
709 struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
710 struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
711 int status = 0;
712
713 ctrl->pdev = pdev;
714 status = beiscsi_map_pci_bars(phba, pdev);
715 if (status)
716 return status;
6733b39a
JK		 717 mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
718 mbox_mem_alloc->va = pci_alloc_consistent(pdev,
719 mbox_mem_alloc->size,
720 &mbox_mem_alloc->dma);
721 if (!mbox_mem_alloc->va) {
722 beiscsi_unmap_pci_function(phba);
a49e06d5 723 return -ENOMEM;
6733b39a
JK		 724 }
725
726 mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
727 mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
728 mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
729 memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
730 spin_lock_init(&ctrl->mbox_lock);
bfead3b2
JK		 731 spin_lock_init(&phba->ctrl.mcc_lock);
732 spin_lock_init(&phba->ctrl.mcc_cq_lock);
733
6733b39a
JK		 734 return status;
735}
736
843ae752
JK		 737/**
738 * beiscsi_get_params()- Set the config paramters
739 * @phba: ptr device priv structure
740 **/
6733b39a
JK		 741static void beiscsi_get_params(struct beiscsi_hba *phba)
742{
843ae752
JK		 743 uint32_t total_cid_count = 0;
744 uint32_t total_icd_count = 0;
745 uint8_t ulp_num = 0;
746
747 total_cid_count = BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP0) +
748 BEISCSI_GET_CID_COUNT(phba, BEISCSI_ULP1);
749
cf987b79
JK		 750 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
751 uint32_t align_mask = 0;
752 uint32_t icd_post_per_page = 0;
753 uint32_t icd_count_unavailable = 0;
754 uint32_t icd_start = 0, icd_count = 0;
755 uint32_t icd_start_align = 0, icd_count_align = 0;
756
843ae752 757 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
cf987b79
JK		 758 icd_start = phba->fw_config.iscsi_icd_start[ulp_num];
759 icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
760
761 /* Get ICD count that can be posted on each page */
762 icd_post_per_page = (PAGE_SIZE / (BE2_SGE *
763 sizeof(struct iscsi_sge)));
764 align_mask = (icd_post_per_page - 1);
765
766 /* Check if icd_start is aligned ICD per page posting */
767 if (icd_start % icd_post_per_page) {
768 icd_start_align = ((icd_start +
769 icd_post_per_page) &
770 ~(align_mask));
771 phba->fw_config.
772 iscsi_icd_start[ulp_num] =
773 icd_start_align;
774 }
775
776 icd_count_align = (icd_count & ~align_mask);
777
778 /* ICD discarded in the process of alignment */
779 if (icd_start_align)
780 icd_count_unavailable = ((icd_start_align -
781 icd_start) +
782 (icd_count -
783 icd_count_align));
784
785 /* Updated ICD count available */
786 phba->fw_config.iscsi_icd_count[ulp_num] = (icd_count -
787 icd_count_unavailable);
788
789 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
790 "BM_%d : Aligned ICD values\n"
791 "\t ICD Start : %d\n"
792 "\t ICD Count : %d\n"
793 "\t ICD Discarded : %d\n",
794 phba->fw_config.
795 iscsi_icd_start[ulp_num],
796 phba->fw_config.
797 iscsi_icd_count[ulp_num],
798 icd_count_unavailable);
843ae752
JK		 799 break;
800 }
cf987b79 801 }
843ae752 802
cf987b79 803 total_icd_count = phba->fw_config.iscsi_icd_count[ulp_num];
843ae752
JK		 804 phba->params.ios_per_ctrl = (total_icd_count -
805 (total_cid_count +
806 BE2_TMFS + BE2_NOPOUT_REQ));
807 phba->params.cxns_per_ctrl = total_cid_count;
808 phba->params.asyncpdus_per_ctrl = total_cid_count;
809 phba->params.icds_per_ctrl = total_icd_count;
6733b39a
JK		 810 phba->params.num_sge_per_io = BE2_SGE;
811 phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
812 phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
813 phba->params.eq_timer = 64;
843ae752
JK		 814 phba->params.num_eq_entries = 1024;
815 phba->params.num_cq_entries = 1024;
6733b39a
JK		 816 phba->params.wrbs_per_cxn = 256;
817}
818
819static void hwi_ring_eq_db(struct beiscsi_hba *phba,
820 unsigned int id, unsigned int clr_interrupt,
821 unsigned int num_processed,
822 unsigned char rearm, unsigned char event)
823{
824 u32 val = 0;
e08b3c8b 825
6733b39a
JK		 826 if (rearm)
827 val |= 1 << DB_EQ_REARM_SHIFT;
828 if (clr_interrupt)
829 val |= 1 << DB_EQ_CLR_SHIFT;
830 if (event)
831 val |= 1 << DB_EQ_EVNT_SHIFT;
e08b3c8b 832
6733b39a 833 val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
e08b3c8b
JK		 834 /* Setting lower order EQ_ID Bits */
835 val |= (id & DB_EQ_RING_ID_LOW_MASK);
836
837 /* Setting Higher order EQ_ID Bits */
838 val |= (((id >> DB_EQ_HIGH_FEILD_SHIFT) &
839 DB_EQ_RING_ID_HIGH_MASK)
840 << DB_EQ_HIGH_SET_SHIFT);
841
6733b39a
JK		 842 iowrite32(val, phba->db_va + DB_EQ_OFFSET);
843}
844
bfead3b2
JK		 845/**
846 * be_isr_mcc - The isr routine of the driver.
847 * @irq: Not used
848 * @dev_id: Pointer to host adapter structure
849 */
850static irqreturn_t be_isr_mcc(int irq, void *dev_id)
851{
852 struct beiscsi_hba *phba;
853 struct be_eq_entry *eqe = NULL;
854 struct be_queue_info *eq;
855 struct be_queue_info *mcc;
856 unsigned int num_eq_processed;
857 struct be_eq_obj *pbe_eq;
858 unsigned long flags;
859
860 pbe_eq = dev_id;
861 eq = &pbe_eq->q;
862 phba = pbe_eq->phba;
863 mcc = &phba->ctrl.mcc_obj.cq;
864 eqe = queue_tail_node(eq);
bfead3b2
JK		 865
866 num_eq_processed = 0;
867
868 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
869 & EQE_VALID_MASK) {
870 if (((eqe->dw[offsetof(struct amap_eq_entry,
871 resource_id) / 32] &
872 EQE_RESID_MASK) >> 16) == mcc->id) {
873 spin_lock_irqsave(&phba->isr_lock, flags);
72fb46a9 874 pbe_eq->todo_mcc_cq = true;
bfead3b2
JK		 875 spin_unlock_irqrestore(&phba->isr_lock, flags);
876 }
877 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
878 queue_tail_inc(eq);
879 eqe = queue_tail_node(eq);
880 num_eq_processed++;
881 }
72fb46a9
JSJ		 882 if (pbe_eq->todo_mcc_cq)
883 queue_work(phba->wq, &pbe_eq->work_cqs);
bfead3b2
JK		 884 if (num_eq_processed)
885 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
886
887 return IRQ_HANDLED;
888}
889
890/**
891 * be_isr_msix - The isr routine of the driver.
892 * @irq: Not used
893 * @dev_id: Pointer to host adapter structure
894 */
895static irqreturn_t be_isr_msix(int irq, void *dev_id)
896{
897 struct beiscsi_hba *phba;
898 struct be_eq_entry *eqe = NULL;
899 struct be_queue_info *eq;
900 struct be_queue_info *cq;
901 unsigned int num_eq_processed;
902 struct be_eq_obj *pbe_eq;
bfead3b2
JK		 903
904 pbe_eq = dev_id;
905 eq = &pbe_eq->q;
906 cq = pbe_eq->cq;
907 eqe = queue_tail_node(eq);
bfead3b2
JK		 908
909 phba = pbe_eq->phba;
910 num_eq_processed = 0;
89f8b33c
JA		 911 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
912 & EQE_VALID_MASK) {
913 if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
914 blk_iopoll_sched(&pbe_eq->iopoll);
bfead3b2 915
89f8b33c
JA		 916 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
917 queue_tail_inc(eq);
918 eqe = queue_tail_node(eq);
919 num_eq_processed++;
bfead3b2 920 }
72fb46a9
JSJ		 921
922 if (num_eq_processed)
923 hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
924
925 return IRQ_HANDLED;
bfead3b2
JK		 926}
927
6733b39a
JK		 928/**
929 * be_isr - The isr routine of the driver.
930 * @irq: Not used
931 * @dev_id: Pointer to host adapter structure
932 */
933static irqreturn_t be_isr(int irq, void *dev_id)
934{
935 struct beiscsi_hba *phba;
936 struct hwi_controller *phwi_ctrlr;
937 struct hwi_context_memory *phwi_context;
938 struct be_eq_entry *eqe = NULL;
939 struct be_queue_info *eq;
bfead3b2 940 struct be_queue_info *mcc;
6733b39a 941 unsigned long flags, index;
bfead3b2 942 unsigned int num_mcceq_processed, num_ioeq_processed;
6733b39a 943 struct be_ctrl_info *ctrl;
bfead3b2 944 struct be_eq_obj *pbe_eq;
6733b39a
JK		 945 int isr;
946
947 phba = dev_id;
6eab04a8 948 ctrl = &phba->ctrl;
bfead3b2
JK		 949 isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
950 (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
951 if (!isr)
952 return IRQ_NONE;
6733b39a
JK		 953
954 phwi_ctrlr = phba->phwi_ctrlr;
955 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 956 pbe_eq = &phwi_context->be_eq[0];
957
958 eq = &phwi_context->be_eq[0].q;
959 mcc = &phba->ctrl.mcc_obj.cq;
6733b39a
JK		 960 index = 0;
961 eqe = queue_tail_node(eq);
6733b39a 962
bfead3b2
JK		 963 num_ioeq_processed = 0;
964 num_mcceq_processed = 0;
89f8b33c
JA		 965 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
966 & EQE_VALID_MASK) {
967 if (((eqe->dw[offsetof(struct amap_eq_entry,
968 resource_id) / 32] &
969 EQE_RESID_MASK) >> 16) == mcc->id) {
970 spin_lock_irqsave(&phba->isr_lock, flags);
971 pbe_eq->todo_mcc_cq = true;
972 spin_unlock_irqrestore(&phba->isr_lock, flags);
973 num_mcceq_processed++;
974 } else {
975 if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
976 blk_iopoll_sched(&pbe_eq->iopoll);
bfead3b2 977 num_ioeq_processed++;
6733b39a 978 }
89f8b33c
JA		 979 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
980 queue_tail_inc(eq);
981 eqe = queue_tail_node(eq);
982 }
983 if (num_ioeq_processed || num_mcceq_processed) {
984 if (pbe_eq->todo_mcc_cq)
72fb46a9 985 queue_work(phba->wq, &pbe_eq->work_cqs);
6733b39a 986
89f8b33c 987 if ((num_mcceq_processed) && (!num_ioeq_processed))
bfead3b2 988 hwi_ring_eq_db(phba, eq->id, 0,
89f8b33c
JA		 989 (num_ioeq_processed +
990 num_mcceq_processed) , 1, 1);
991 else
992 hwi_ring_eq_db(phba, eq->id, 0,
993 (num_ioeq_processed +
994 num_mcceq_processed), 0, 1);
995
996 return IRQ_HANDLED;
997 } else
998 return IRQ_NONE;
6733b39a
JK		 999}
1000
1001static int beiscsi_init_irqs(struct beiscsi_hba *phba)
1002{
1003 struct pci_dev *pcidev = phba->pcidev;
bfead3b2
JK		 1004 struct hwi_controller *phwi_ctrlr;
1005 struct hwi_context_memory *phwi_context;
4f5af07e 1006 int ret, msix_vec, i, j;
6733b39a 1007
bfead3b2
JK		 1008 phwi_ctrlr = phba->phwi_ctrlr;
1009 phwi_context = phwi_ctrlr->phwi_ctxt;
1010
1011 if (phba->msix_enabled) {
1012 for (i = 0; i < phba->num_cpus; i++) {
8fcfb210
JK		 1013 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
1014 GFP_KERNEL);
1015 if (!phba->msi_name[i]) {
1016 ret = -ENOMEM;
1017 goto free_msix_irqs;
1018 }
1019
1020 sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
1021 phba->shost->host_no, i);
bfead3b2 1022 msix_vec = phba->msix_entries[i].vector;
8fcfb210
JK		 1023 ret = request_irq(msix_vec, be_isr_msix, 0,
1024 phba->msi_name[i],
bfead3b2 1025 &phwi_context->be_eq[i]);
4f5af07e 1026 if (ret) {
99bc5d55
JSJ		 1027 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1028 "BM_%d : beiscsi_init_irqs-Failed to"
1029 "register msix for i = %d\n",
1030 i);
8fcfb210 1031 kfree(phba->msi_name[i]);
4f5af07e
JK		 1032 goto free_msix_irqs;
1033 }
bfead3b2 1034 }
8fcfb210
JK		 1035 phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
1036 if (!phba->msi_name[i]) {
1037 ret = -ENOMEM;
1038 goto free_msix_irqs;
1039 }
1040 sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
1041 phba->shost->host_no);
bfead3b2 1042 msix_vec = phba->msix_entries[i].vector;
8fcfb210 1043 ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
bfead3b2 1044 &phwi_context->be_eq[i]);
4f5af07e 1045 if (ret) {
99bc5d55
JSJ		 1046 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
1047 "BM_%d : beiscsi_init_irqs-"
1048 "Failed to register beiscsi_msix_mcc\n");
8fcfb210 1049 kfree(phba->msi_name[i]);
4f5af07e
JK		 1050 goto free_msix_irqs;
1051 }
1052
bfead3b2
JK		 1053 } else {
1054 ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
1055 "beiscsi", phba);
1056 if (ret) {
99bc5d55
JSJ		 1057 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1058 "BM_%d : beiscsi_init_irqs-"
1059 "Failed to register irq\\n");
bfead3b2
JK		 1060 return ret;
1061 }
6733b39a
JK		 1062 }
1063 return 0;
4f5af07e 1064free_msix_irqs:
8fcfb210
JK		 1065 for (j = i - 1; j >= 0; j--) {
1066 kfree(phba->msi_name[j]);
1067 msix_vec = phba->msix_entries[j].vector;
4f5af07e 1068 free_irq(msix_vec, &phwi_context->be_eq[j]);
8fcfb210 1069 }
4f5af07e 1070 return ret;
6733b39a
JK		 1071}
1072
e08b3c8b 1073void hwi_ring_cq_db(struct beiscsi_hba *phba,
6733b39a
JK		 1074 unsigned int id, unsigned int num_processed,
1075 unsigned char rearm, unsigned char event)
1076{
1077 u32 val = 0;
e08b3c8b 1078
6733b39a
JK		 1079 if (rearm)
1080 val |= 1 << DB_CQ_REARM_SHIFT;
e08b3c8b 1081
6733b39a 1082 val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
e08b3c8b
JK		 1083
1084 /* Setting lower order CQ_ID Bits */
1085 val |= (id & DB_CQ_RING_ID_LOW_MASK);
1086
1087 /* Setting Higher order CQ_ID Bits */
1088 val |= (((id >> DB_CQ_HIGH_FEILD_SHIFT) &
1089 DB_CQ_RING_ID_HIGH_MASK)
1090 << DB_CQ_HIGH_SET_SHIFT);
1091
6733b39a
JK		 1092 iowrite32(val, phba->db_va + DB_CQ_OFFSET);
1093}
1094
6733b39a
JK		 1095static unsigned int
1096beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
1097 struct beiscsi_hba *phba,
6733b39a
JK		 1098 struct pdu_base *ppdu,
1099 unsigned long pdu_len,
1100 void *pbuffer, unsigned long buf_len)
1101{
1102 struct iscsi_conn *conn = beiscsi_conn->conn;
1103 struct iscsi_session *session = conn->session;
bfead3b2
JK		 1104 struct iscsi_task *task;
1105 struct beiscsi_io_task *io_task;
1106 struct iscsi_hdr *login_hdr;
6733b39a
JK		 1107
1108 switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
1109 PDUBASE_OPCODE_MASK) {
1110 case ISCSI_OP_NOOP_IN:
1111 pbuffer = NULL;
1112 buf_len = 0;
1113 break;
1114 case ISCSI_OP_ASYNC_EVENT:
1115 break;
1116 case ISCSI_OP_REJECT:
1117 WARN_ON(!pbuffer);
1118 WARN_ON(!(buf_len == 48));
99bc5d55
JSJ		 1119 beiscsi_log(phba, KERN_ERR,
1120 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1121 "BM_%d : In ISCSI_OP_REJECT\n");
6733b39a
JK		 1122 break;
1123 case ISCSI_OP_LOGIN_RSP:
7bd6e25c 1124 case ISCSI_OP_TEXT_RSP:
bfead3b2
JK		 1125 task = conn->login_task;
1126 io_task = task->dd_data;
1127 login_hdr = (struct iscsi_hdr *)ppdu;
1128 login_hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1129 break;
1130 default:
99bc5d55
JSJ		 1131 beiscsi_log(phba, KERN_WARNING,
1132 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1133 "BM_%d : Unrecognized opcode 0x%x in async msg\n",
1134 (ppdu->
6733b39a 1135 dw[offsetof(struct amap_pdu_base, opcode) / 32]
99bc5d55 1136 & PDUBASE_OPCODE_MASK));
6733b39a
JK		 1137 return 1;
1138 }
1139
659743b0 1140 spin_lock_bh(&session->back_lock);
6733b39a 1141 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
659743b0 1142 spin_unlock_bh(&session->back_lock);
6733b39a
JK		 1143 return 0;
1144}
1145
1146static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
1147{
1148 struct sgl_handle *psgl_handle;
1149
1150 if (phba->io_sgl_hndl_avbl) {
99bc5d55
JSJ		 1151 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
1152 "BM_%d : In alloc_io_sgl_handle,"
1153 " io_sgl_alloc_index=%d\n",
1154 phba->io_sgl_alloc_index);
1155
6733b39a
JK		 1156 psgl_handle = phba->io_sgl_hndl_base[phba->
1157 io_sgl_alloc_index];
1158 phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
1159 phba->io_sgl_hndl_avbl--;
bfead3b2
JK		 1160 if (phba->io_sgl_alloc_index == (phba->params.
1161 ios_per_ctrl - 1))
6733b39a
JK		 1162 phba->io_sgl_alloc_index = 0;
1163 else
1164 phba->io_sgl_alloc_index++;
1165 } else
1166 psgl_handle = NULL;
1167 return psgl_handle;
1168}
1169
1170static void
1171free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
1172{
99bc5d55
JSJ		 1173 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
1174 "BM_%d : In free_,io_sgl_free_index=%d\n",
1175 phba->io_sgl_free_index);
1176
6733b39a
JK		 1177 if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
1178 /*
1179 * this can happen if clean_task is called on a task that
1180 * failed in xmit_task or alloc_pdu.
1181 */
99bc5d55
JSJ		 1182 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
1183 "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
1184 "value there=%p\n", phba->io_sgl_free_index,
1185 phba->io_sgl_hndl_base
1186 [phba->io_sgl_free_index]);
6733b39a
JK		 1187 return;
1188 }
1189 phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
1190 phba->io_sgl_hndl_avbl++;
1191 if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
1192 phba->io_sgl_free_index = 0;
1193 else
1194 phba->io_sgl_free_index++;
1195}
1196
1197/**
1198 * alloc_wrb_handle - To allocate a wrb handle
1199 * @phba: The hba pointer
1200 * @cid: The cid to use for allocation
6733b39a
JK		 1201 *
1202 * This happens under session_lock until submission to chip
1203 */
d5431488 1204struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
6733b39a
JK		 1205{
1206 struct hwi_wrb_context *pwrb_context;
1207 struct hwi_controller *phwi_ctrlr;
d5431488 1208 struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
a7909b39 1209 uint16_t cri_index = BE_GET_CRI_FROM_CID(cid);
6733b39a
JK		 1210
1211 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 1212 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
d5431488 1213 if (pwrb_context->wrb_handles_available >= 2) {
bfead3b2
JK		 1214 pwrb_handle = pwrb_context->pwrb_handle_base[
1215 pwrb_context->alloc_index];
1216 pwrb_context->wrb_handles_available--;
bfead3b2
JK		 1217 if (pwrb_context->alloc_index ==
1218 (phba->params.wrbs_per_cxn - 1))
1219 pwrb_context->alloc_index = 0;
1220 else
1221 pwrb_context->alloc_index++;
d5431488
JK		 1222 pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
1223 pwrb_context->alloc_index];
1224 pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
bfead3b2
JK		 1225 } else
1226 pwrb_handle = NULL;
6733b39a
JK		 1227 return pwrb_handle;
1228}
1229
1230/**
1231 * free_wrb_handle - To free the wrb handle back to pool
1232 * @phba: The hba pointer
1233 * @pwrb_context: The context to free from
1234 * @pwrb_handle: The wrb_handle to free
1235 *
1236 * This happens under session_lock until submission to chip
1237 */
1238static void
1239free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
1240 struct wrb_handle *pwrb_handle)
1241{
32951dd8 1242 pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
bfead3b2
JK		 1243 pwrb_context->wrb_handles_available++;
1244 if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
1245 pwrb_context->free_index = 0;
1246 else
1247 pwrb_context->free_index++;
1248
99bc5d55
JSJ		 1249 beiscsi_log(phba, KERN_INFO,
1250 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1251 "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
1252 "wrb_handles_available=%d\n",
1253 pwrb_handle, pwrb_context->free_index,
1254 pwrb_context->wrb_handles_available);
6733b39a
JK		 1255}
1256
1257static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
1258{
1259 struct sgl_handle *psgl_handle;
1260
1261 if (phba->eh_sgl_hndl_avbl) {
1262 psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
1263 phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
99bc5d55
JSJ		 1264 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
1265 "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
1266 phba->eh_sgl_alloc_index,
1267 phba->eh_sgl_alloc_index);
1268
6733b39a
JK		 1269 phba->eh_sgl_hndl_avbl--;
1270 if (phba->eh_sgl_alloc_index ==
1271 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
1272 1))
1273 phba->eh_sgl_alloc_index = 0;
1274 else
1275 phba->eh_sgl_alloc_index++;
1276 } else
1277 psgl_handle = NULL;
1278 return psgl_handle;
1279}
1280
1281void
1282free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
1283{
1284
99bc5d55
JSJ		 1285 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
1286 "BM_%d : In free_mgmt_sgl_handle,"
1287 "eh_sgl_free_index=%d\n",
1288 phba->eh_sgl_free_index);
1289
6733b39a
JK		 1290 if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
1291 /*
1292 * this can happen if clean_task is called on a task that
1293 * failed in xmit_task or alloc_pdu.
1294 */
99bc5d55
JSJ		 1295 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
1296 "BM_%d : Double Free in eh SGL ,"
1297 "eh_sgl_free_index=%d\n",
1298 phba->eh_sgl_free_index);
6733b39a
JK		 1299 return;
1300 }
1301 phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
1302 phba->eh_sgl_hndl_avbl++;
1303 if (phba->eh_sgl_free_index ==
1304 (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
1305 phba->eh_sgl_free_index = 0;
1306 else
1307 phba->eh_sgl_free_index++;
1308}
1309
1310static void
1311be_complete_io(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1312 struct iscsi_task *task,
1313 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1314{
1315 struct beiscsi_io_task *io_task = task->dd_data;
1316 struct be_status_bhs *sts_bhs =
1317 (struct be_status_bhs *)io_task->cmd_bhs;
1318 struct iscsi_conn *conn = beiscsi_conn->conn;
6733b39a
JK		 1319 unsigned char *sense;
1320 u32 resid = 0, exp_cmdsn, max_cmdsn;
1321 u8 rsp, status, flags;
1322
73133261
JSJ		 1323 exp_cmdsn = csol_cqe->exp_cmdsn;
1324 max_cmdsn = (csol_cqe->exp_cmdsn +
1325 csol_cqe->cmd_wnd - 1);
1326 rsp = csol_cqe->i_resp;
1327 status = csol_cqe->i_sts;
1328 flags = csol_cqe->i_flags;
1329 resid = csol_cqe->res_cnt;
1330
bd535451 1331 if (!task->sc) {
da334977 1332 if (io_task->scsi_cmnd) {
bd535451 1333 scsi_dma_unmap(io_task->scsi_cmnd);
da334977
JK		 1334 io_task->scsi_cmnd = NULL;
1335 }
6733b39a 1336
bd535451
JK		 1337 return;
1338 }
6733b39a
JK		 1339 task->sc->result = (DID_OK << 16) | status;
1340 if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
1341 task->sc->result = DID_ERROR << 16;
1342 goto unmap;
1343 }
1344
1345 /* bidi not initially supported */
1346 if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
6733b39a
JK		 1347 if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
1348 task->sc->result = DID_ERROR << 16;
1349
1350 if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
1351 scsi_set_resid(task->sc, resid);
1352 if (!status && (scsi_bufflen(task->sc) - resid <
1353 task->sc->underflow))
1354 task->sc->result = DID_ERROR << 16;
1355 }
1356 }
1357
1358 if (status == SAM_STAT_CHECK_CONDITION) {
4053a4be 1359 u16 sense_len;
bfead3b2 1360 unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
4053a4be 1361
6733b39a 1362 sense = sts_bhs->sense_info + sizeof(unsigned short);
4053a4be 1363 sense_len = be16_to_cpu(*slen);
6733b39a
JK		 1364 memcpy(task->sc->sense_buffer, sense,
1365 min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
1366 }
756d29c8 1367
73133261
JSJ		 1368 if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ)
1369 conn->rxdata_octets += resid;
6733b39a
JK		 1370unmap:
1371 scsi_dma_unmap(io_task->scsi_cmnd);
da334977 1372 io_task->scsi_cmnd = NULL;
6733b39a
JK		 1373 iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
1374}
1375
1376static void
1377be_complete_logout(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1378 struct iscsi_task *task,
1379 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1380{
1381 struct iscsi_logout_rsp *hdr;
bfead3b2 1382 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1383 struct iscsi_conn *conn = beiscsi_conn->conn;
1384
1385 hdr = (struct iscsi_logout_rsp *)task->hdr;
7bd6e25c 1386 hdr->opcode = ISCSI_OP_LOGOUT_RSP;
6733b39a
JK		 1387 hdr->t2wait = 5;
1388 hdr->t2retain = 0;
73133261
JSJ		 1389 hdr->flags = csol_cqe->i_flags;
1390 hdr->response = csol_cqe->i_resp;
702dc5e8
JK		 1391 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
1392 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1393 csol_cqe->cmd_wnd - 1);
73133261 1394
7bd6e25c
JK		 1395 hdr->dlength[0] = 0;
1396 hdr->dlength[1] = 0;
1397 hdr->dlength[2] = 0;
6733b39a 1398 hdr->hlength = 0;
bfead3b2 1399 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1400 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1401}
1402
1403static void
1404be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1405 struct iscsi_task *task,
1406 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1407{
1408 struct iscsi_tm_rsp *hdr;
1409 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1410 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1411
1412 hdr = (struct iscsi_tm_rsp *)task->hdr;
7bd6e25c 1413 hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
73133261
JSJ		 1414 hdr->flags = csol_cqe->i_flags;
1415 hdr->response = csol_cqe->i_resp;
702dc5e8
JK		 1416 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
1417 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1418 csol_cqe->cmd_wnd - 1);
73133261 1419
bfead3b2 1420 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1421 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1422}
1423
1424static void
1425hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
1426 struct beiscsi_hba *phba, struct sol_cqe *psol)
1427{
1428 struct hwi_wrb_context *pwrb_context;
bfead3b2 1429 struct wrb_handle *pwrb_handle = NULL;
6733b39a 1430 struct hwi_controller *phwi_ctrlr;
bfead3b2
JK		 1431 struct iscsi_task *task;
1432 struct beiscsi_io_task *io_task;
a7909b39 1433 uint16_t wrb_index, cid, cri_index;
6733b39a
JK		 1434
1435 phwi_ctrlr = phba->phwi_ctrlr;
2c9dfd36
JK		 1436 if (is_chip_be2_be3r(phba)) {
1437 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
73133261 1438 wrb_idx, psol);
2c9dfd36 1439 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
73133261
JSJ		 1440 cid, psol);
1441 } else {
2c9dfd36 1442 wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
73133261 1443 wrb_idx, psol);
2c9dfd36 1444 cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
73133261
JSJ		 1445 cid, psol);
1446 }
1447
a7909b39
JK		 1448 cri_index = BE_GET_CRI_FROM_CID(cid);
1449 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
73133261 1450 pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index];
32951dd8 1451 task = pwrb_handle->pio_handle;
35e66019 1452
bfead3b2 1453 io_task = task->dd_data;
4a4a11b9
JK		 1454 memset(io_task->pwrb_handle->pwrb, 0, sizeof(struct iscsi_wrb));
1455 iscsi_put_task(task);
6733b39a
JK		 1456}
1457
1458static void
1459be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
73133261
JSJ		 1460 struct iscsi_task *task,
1461 struct common_sol_cqe *csol_cqe)
6733b39a
JK		 1462{
1463 struct iscsi_nopin *hdr;
1464 struct iscsi_conn *conn = beiscsi_conn->conn;
bfead3b2 1465 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 1466
1467 hdr = (struct iscsi_nopin *)task->hdr;
73133261
JSJ		 1468 hdr->flags = csol_cqe->i_flags;
1469 hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
702dc5e8
JK		 1470 hdr->max_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn +
1471 csol_cqe->cmd_wnd - 1);
73133261 1472
6733b39a 1473 hdr->opcode = ISCSI_OP_NOOP_IN;
bfead3b2 1474 hdr->itt = io_task->libiscsi_itt;
6733b39a
JK		 1475 __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
1476}
1477
73133261
JSJ		 1478static void adapter_get_sol_cqe(struct beiscsi_hba *phba,
1479 struct sol_cqe *psol,
1480 struct common_sol_cqe *csol_cqe)
1481{
2c9dfd36
JK		 1482 if (is_chip_be2_be3r(phba)) {
1483 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe,
1484 i_exp_cmd_sn, psol);
1485 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe,
1486 i_res_cnt, psol);
1487 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
1488 i_cmd_wnd, psol);
1489 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe,
1490 wrb_index, psol);
1491 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe,
1492 cid, psol);
1493 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe,
1494 hw_sts, psol);
1495 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe,
1496 i_resp, psol);
1497 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe,
1498 i_sts, psol);
1499 csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe,
1500 i_flags, psol);
1501 } else {
73133261
JSJ		 1502 csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1503 i_exp_cmd_sn, psol);
1504 csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1505 i_res_cnt, psol);
1506 csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1507 wrb_index, psol);
1508 csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1509 cid, psol);
1510 csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1511 hw_sts, psol);
702dc5e8 1512 csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe_v2,
73133261
JSJ		 1513 i_cmd_wnd, psol);
1514 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1515 cmd_cmpl, psol))
1516 csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1517 i_sts, psol);
1518 else
1519 csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2,
1520 i_sts, psol);
1521 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1522 u, psol))
1523 csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW;
1524
1525 if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
1526 o, psol))
1527 csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW;
73133261
JSJ		 1528 }
1529}
1530
1531
6733b39a
JK		 1532static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
1533 struct beiscsi_hba *phba, struct sol_cqe *psol)
1534{
1535 struct hwi_wrb_context *pwrb_context;
1536 struct wrb_handle *pwrb_handle;
1537 struct iscsi_wrb *pwrb = NULL;
1538 struct hwi_controller *phwi_ctrlr;
1539 struct iscsi_task *task;
bfead3b2 1540 unsigned int type;
6733b39a
JK		 1541 struct iscsi_conn *conn = beiscsi_conn->conn;
1542 struct iscsi_session *session = conn->session;
73133261 1543 struct common_sol_cqe csol_cqe = {0};
a7909b39 1544 uint16_t cri_index = 0;
6733b39a
JK		 1545
1546 phwi_ctrlr = phba->phwi_ctrlr;
73133261
JSJ		 1547
1548 /* Copy the elements to a common structure */
1549 adapter_get_sol_cqe(phba, psol, &csol_cqe);
1550
a7909b39
JK		 1551 cri_index = BE_GET_CRI_FROM_CID(csol_cqe.cid);
1552 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
73133261
JSJ		 1553
1554 pwrb_handle = pwrb_context->pwrb_handle_basestd[
1555 csol_cqe.wrb_index];
1556
32951dd8
JK		 1557 task = pwrb_handle->pio_handle;
1558 pwrb = pwrb_handle->pwrb;
73133261 1559 type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type;
32951dd8 1560
659743b0 1561 spin_lock_bh(&session->back_lock);
bfead3b2 1562 switch (type) {
6733b39a
JK		 1563 case HWH_TYPE_IO:
1564 case HWH_TYPE_IO_RD:
1565 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
dafab8e0 1566 ISCSI_OP_NOOP_OUT)
73133261 1567 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
dafab8e0 1568 else
73133261 1569 be_complete_io(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1570 break;
1571
1572 case HWH_TYPE_LOGOUT:
dafab8e0 1573 if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
73133261 1574 be_complete_logout(beiscsi_conn, task, &csol_cqe);
dafab8e0 1575 else
73133261 1576 be_complete_tmf(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1577 break;
1578
1579 case HWH_TYPE_LOGIN:
99bc5d55
JSJ		 1580 beiscsi_log(phba, KERN_ERR,
1581 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1582 "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
1583 " hwi_complete_cmd- Solicited path\n");
6733b39a
JK		 1584 break;
1585
6733b39a 1586 case HWH_TYPE_NOP:
73133261 1587 be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
6733b39a
JK		 1588 break;
1589
1590 default:
99bc5d55
JSJ		 1591 beiscsi_log(phba, KERN_WARNING,
1592 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1593 "BM_%d : In hwi_complete_cmd, unknown type = %d"
1594 "wrb_index 0x%x CID 0x%x\n", type,
73133261
JSJ		 1595 csol_cqe.wrb_index,
1596 csol_cqe.cid);
6733b39a
JK		 1597 break;
1598 }
35e66019 1599
659743b0 1600 spin_unlock_bh(&session->back_lock);
6733b39a
JK		 1601}
1602
1603static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
1604 *pasync_ctx, unsigned int is_header,
1605 unsigned int host_write_ptr)
1606{
1607 if (is_header)
1608 return &pasync_ctx->async_entry[host_write_ptr].
1609 header_busy_list;
1610 else
1611 return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
1612}
1613
1614static struct async_pdu_handle *
1615hwi_get_async_handle(struct beiscsi_hba *phba,
1616 struct beiscsi_conn *beiscsi_conn,
1617 struct hwi_async_pdu_context *pasync_ctx,
1618 struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
1619{
1620 struct be_bus_address phys_addr;
1621 struct list_head *pbusy_list;
1622 struct async_pdu_handle *pasync_handle = NULL;
6733b39a 1623 unsigned char is_header = 0;
73133261
JSJ		 1624 unsigned int index, dpl;
1625
2c9dfd36
JK		 1626 if (is_chip_be2_be3r(phba)) {
1627 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
73133261 1628 dpl, pdpdu_cqe);
2c9dfd36 1629 index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
73133261
JSJ		 1630 index, pdpdu_cqe);
1631 } else {
2c9dfd36 1632 dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
73133261 1633 dpl, pdpdu_cqe);
2c9dfd36 1634 index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
73133261
JSJ		 1635 index, pdpdu_cqe);
1636 }
6733b39a
JK		 1637
1638 phys_addr.u.a32.address_lo =
73133261
JSJ		 1639 (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1640 db_addr_lo) / 32] - dpl);
6733b39a 1641 phys_addr.u.a32.address_hi =
73133261
JSJ		 1642 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1643 db_addr_hi) / 32];
6733b39a
JK		 1644
1645 phys_addr.u.a64.address =
1646 *((unsigned long long *)(&phys_addr.u.a64.address));
1647
1648 switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
1649 & PDUCQE_CODE_MASK) {
1650 case UNSOL_HDR_NOTIFY:
1651 is_header = 1;
1652
73133261
JSJ		 1653 pbusy_list = hwi_get_async_busy_list(pasync_ctx,
1654 is_header, index);
6733b39a
JK		 1655 break;
1656 case UNSOL_DATA_NOTIFY:
73133261
JSJ		 1657 pbusy_list = hwi_get_async_busy_list(pasync_ctx,
1658 is_header, index);
6733b39a
JK		 1659 break;
1660 default:
1661 pbusy_list = NULL;
99bc5d55
JSJ		 1662 beiscsi_log(phba, KERN_WARNING,
1663 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
1664 "BM_%d : Unexpected code=%d\n",
1665 pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
1666 code) / 32] & PDUCQE_CODE_MASK);
6733b39a
JK		 1667 return NULL;
1668 }
1669
6733b39a
JK		 1670 WARN_ON(list_empty(pbusy_list));
1671 list_for_each_entry(pasync_handle, pbusy_list, link) {
dc63aac6 1672 if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
6733b39a
JK		 1673 break;
1674 }
1675
1676 WARN_ON(!pasync_handle);
1677
8a86e833
JK		 1678 pasync_handle->cri = BE_GET_ASYNC_CRI_FROM_CID(
1679 beiscsi_conn->beiscsi_conn_cid);
6733b39a 1680 pasync_handle->is_header = is_header;
73133261
JSJ		 1681 pasync_handle->buffer_len = dpl;
1682 *pcq_index = index;
6733b39a 1683
6733b39a
JK		 1684 return pasync_handle;
1685}
1686
1687static unsigned int
99bc5d55
JSJ		 1688hwi_update_async_writables(struct beiscsi_hba *phba,
1689 struct hwi_async_pdu_context *pasync_ctx,
1690 unsigned int is_header, unsigned int cq_index)
6733b39a
JK		 1691{
1692 struct list_head *pbusy_list;
1693 struct async_pdu_handle *pasync_handle;
1694 unsigned int num_entries, writables = 0;
1695 unsigned int *pep_read_ptr, *pwritables;
1696
dc63aac6 1697 num_entries = pasync_ctx->num_entries;
6733b39a
JK		 1698 if (is_header) {
1699 pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
1700 pwritables = &pasync_ctx->async_header.writables;
6733b39a
JK		 1701 } else {
1702 pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
1703 pwritables = &pasync_ctx->async_data.writables;
6733b39a
JK		 1704 }
1705
1706 while ((*pep_read_ptr) != cq_index) {
1707 (*pep_read_ptr)++;
1708 *pep_read_ptr = (*pep_read_ptr) % num_entries;
1709
1710 pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
1711 *pep_read_ptr);
1712 if (writables == 0)
1713 WARN_ON(list_empty(pbusy_list));
1714
1715 if (!list_empty(pbusy_list)) {
1716 pasync_handle = list_entry(pbusy_list->next,
1717 struct async_pdu_handle,
1718 link);
1719 WARN_ON(!pasync_handle);
1720 pasync_handle->consumed = 1;
1721 }
1722
1723 writables++;
1724 }
1725
1726 if (!writables) {
99bc5d55
JSJ		 1727 beiscsi_log(phba, KERN_ERR,
1728 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
1729 "BM_%d : Duplicate notification received - index 0x%x!!\n",
1730 cq_index);
6733b39a
JK		 1731 WARN_ON(1);
1732 }
1733
1734 *pwritables = *pwritables + writables;
1735 return 0;
1736}
1737
9728d8d0 1738static void hwi_free_async_msg(struct beiscsi_hba *phba,
8a86e833
JK		 1739 struct hwi_async_pdu_context *pasync_ctx,
1740 unsigned int cri)
6733b39a 1741{
6733b39a
JK		 1742 struct async_pdu_handle *pasync_handle, *tmp_handle;
1743 struct list_head *plist;
6733b39a 1744
6733b39a 1745 plist = &pasync_ctx->async_entry[cri].wait_queue.list;
6733b39a
JK		 1746 list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
1747 list_del(&pasync_handle->link);
1748
9728d8d0 1749 if (pasync_handle->is_header) {
6733b39a
JK		 1750 list_add_tail(&pasync_handle->link,
1751 &pasync_ctx->async_header.free_list);
1752 pasync_ctx->async_header.free_entries++;
6733b39a
JK		 1753 } else {
1754 list_add_tail(&pasync_handle->link,
1755 &pasync_ctx->async_data.free_list);
1756 pasync_ctx->async_data.free_entries++;
6733b39a
JK		 1757 }
1758 }
1759
1760 INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
1761 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
1762 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
6733b39a
JK		 1763}
1764
1765static struct phys_addr *
1766hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
1767 unsigned int is_header, unsigned int host_write_ptr)
1768{
1769 struct phys_addr *pasync_sge = NULL;
1770
1771 if (is_header)
1772 pasync_sge = pasync_ctx->async_header.ring_base;
1773 else
1774 pasync_sge = pasync_ctx->async_data.ring_base;
1775
1776 return pasync_sge + host_write_ptr;
1777}
1778
1779static void hwi_post_async_buffers(struct beiscsi_hba *phba,
8a86e833 1780 unsigned int is_header, uint8_t ulp_num)
6733b39a
JK		 1781{
1782 struct hwi_controller *phwi_ctrlr;
1783 struct hwi_async_pdu_context *pasync_ctx;
1784 struct async_pdu_handle *pasync_handle;
1785 struct list_head *pfree_link, *pbusy_list;
1786 struct phys_addr *pasync_sge;
1787 unsigned int ring_id, num_entries;
8a86e833 1788 unsigned int host_write_num, doorbell_offset;
6733b39a
JK		 1789 unsigned int writables;
1790 unsigned int i = 0;
1791 u32 doorbell = 0;
1792
1793 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833 1794 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr, ulp_num);
dc63aac6 1795 num_entries = pasync_ctx->num_entries;
6733b39a
JK		 1796
1797 if (is_header) {
6733b39a
JK		 1798 writables = min(pasync_ctx->async_header.writables,
1799 pasync_ctx->async_header.free_entries);
1800 pfree_link = pasync_ctx->async_header.free_list.next;
1801 host_write_num = pasync_ctx->async_header.host_write_ptr;
8a86e833
JK		 1802 ring_id = phwi_ctrlr->default_pdu_hdr[ulp_num].id;
1803 doorbell_offset = phwi_ctrlr->default_pdu_hdr[ulp_num].
1804 doorbell_offset;
6733b39a 1805 } else {
6733b39a
JK		 1806 writables = min(pasync_ctx->async_data.writables,
1807 pasync_ctx->async_data.free_entries);
1808 pfree_link = pasync_ctx->async_data.free_list.next;
1809 host_write_num = pasync_ctx->async_data.host_write_ptr;
8a86e833
JK		 1810 ring_id = phwi_ctrlr->default_pdu_data[ulp_num].id;
1811 doorbell_offset = phwi_ctrlr->default_pdu_data[ulp_num].
1812 doorbell_offset;
6733b39a
JK		 1813 }
1814
1815 writables = (writables / 8) * 8;
1816 if (writables) {
1817 for (i = 0; i < writables; i++) {
1818 pbusy_list =
1819 hwi_get_async_busy_list(pasync_ctx, is_header,
1820 host_write_num);
1821 pasync_handle =
1822 list_entry(pfree_link, struct async_pdu_handle,
1823 link);
1824 WARN_ON(!pasync_handle);
1825 pasync_handle->consumed = 0;
1826
1827 pfree_link = pfree_link->next;
1828
1829 pasync_sge = hwi_get_ring_address(pasync_ctx,
1830 is_header, host_write_num);
1831
1832 pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
1833 pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
1834
1835 list_move(&pasync_handle->link, pbusy_list);
1836
1837 host_write_num++;
1838 host_write_num = host_write_num % num_entries;
1839 }
1840
1841 if (is_header) {
1842 pasync_ctx->async_header.host_write_ptr =
1843 host_write_num;
1844 pasync_ctx->async_header.free_entries -= writables;
1845 pasync_ctx->async_header.writables -= writables;
1846 pasync_ctx->async_header.busy_entries += writables;
1847 } else {
1848 pasync_ctx->async_data.host_write_ptr = host_write_num;
1849 pasync_ctx->async_data.free_entries -= writables;
1850 pasync_ctx->async_data.writables -= writables;
1851 pasync_ctx->async_data.busy_entries += writables;
1852 }
1853
1854 doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
1855 doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
1856 doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
1857 doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
1858 << DB_DEF_PDU_CQPROC_SHIFT;
1859
8a86e833 1860 iowrite32(doorbell, phba->db_va + doorbell_offset);
6733b39a
JK		 1861 }
1862}
1863
1864static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
1865 struct beiscsi_conn *beiscsi_conn,
1866 struct i_t_dpdu_cqe *pdpdu_cqe)
1867{
1868 struct hwi_controller *phwi_ctrlr;
1869 struct hwi_async_pdu_context *pasync_ctx;
1870 struct async_pdu_handle *pasync_handle = NULL;
1871 unsigned int cq_index = -1;
8a86e833
JK		 1872 uint16_t cri_index = BE_GET_CRI_FROM_CID(
1873 beiscsi_conn->beiscsi_conn_cid);
6733b39a
JK		 1874
1875 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833
JK		 1876 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
1877 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
1878 cri_index));
6733b39a
JK		 1879
1880 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
1881 pdpdu_cqe, &cq_index);
1882 BUG_ON(pasync_handle->is_header != 0);
1883 if (pasync_handle->consumed == 0)
99bc5d55
JSJ		 1884 hwi_update_async_writables(phba, pasync_ctx,
1885 pasync_handle->is_header, cq_index);
6733b39a 1886
8a86e833
JK		 1887 hwi_free_async_msg(phba, pasync_ctx, pasync_handle->cri);
1888 hwi_post_async_buffers(phba, pasync_handle->is_header,
1889 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
1890 cri_index));
6733b39a
JK		 1891}
1892
1893static unsigned int
1894hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
1895 struct beiscsi_hba *phba,
1896 struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
1897{
1898 struct list_head *plist;
1899 struct async_pdu_handle *pasync_handle;
1900 void *phdr = NULL;
1901 unsigned int hdr_len = 0, buf_len = 0;
1902 unsigned int status, index = 0, offset = 0;
1903 void *pfirst_buffer = NULL;
1904 unsigned int num_buf = 0;
1905
1906 plist = &pasync_ctx->async_entry[cri].wait_queue.list;
1907
1908 list_for_each_entry(pasync_handle, plist, link) {
1909 if (index == 0) {
1910 phdr = pasync_handle->pbuffer;
1911 hdr_len = pasync_handle->buffer_len;
1912 } else {
1913 buf_len = pasync_handle->buffer_len;
1914 if (!num_buf) {
1915 pfirst_buffer = pasync_handle->pbuffer;
1916 num_buf++;
1917 }
1918 memcpy(pfirst_buffer + offset,
1919 pasync_handle->pbuffer, buf_len);
f2ba02b8 1920 offset += buf_len;
6733b39a
JK		 1921 }
1922 index++;
1923 }
1924
1925 status = beiscsi_process_async_pdu(beiscsi_conn, phba,
7da50879 1926 phdr, hdr_len, pfirst_buffer,
f2ba02b8 1927 offset);
6733b39a 1928
8a86e833 1929 hwi_free_async_msg(phba, pasync_ctx, cri);
6733b39a
JK		 1930 return 0;
1931}
1932
1933static unsigned int
1934hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
1935 struct beiscsi_hba *phba,
1936 struct async_pdu_handle *pasync_handle)
1937{
1938 struct hwi_async_pdu_context *pasync_ctx;
1939 struct hwi_controller *phwi_ctrlr;
1940 unsigned int bytes_needed = 0, status = 0;
1941 unsigned short cri = pasync_handle->cri;
1942 struct pdu_base *ppdu;
1943
1944 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833
JK		 1945 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
1946 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
1947 BE_GET_CRI_FROM_CID(beiscsi_conn->
1948 beiscsi_conn_cid)));
6733b39a
JK		 1949
1950 list_del(&pasync_handle->link);
1951 if (pasync_handle->is_header) {
1952 pasync_ctx->async_header.busy_entries--;
1953 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
8a86e833 1954 hwi_free_async_msg(phba, pasync_ctx, cri);
6733b39a
JK		 1955 BUG();
1956 }
1957
1958 pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
1959 pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
1960 pasync_ctx->async_entry[cri].wait_queue.hdr_len =
1961 (unsigned short)pasync_handle->buffer_len;
1962 list_add_tail(&pasync_handle->link,
1963 &pasync_ctx->async_entry[cri].wait_queue.list);
1964
1965 ppdu = pasync_handle->pbuffer;
1966 bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
1967 data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
1968 0xFFFF0000) | ((be16_to_cpu((ppdu->
1969 dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
1970 & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
1971
1972 if (status == 0) {
1973 pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
1974 bytes_needed;
1975
1976 if (bytes_needed == 0)
1977 status = hwi_fwd_async_msg(beiscsi_conn, phba,
1978 pasync_ctx, cri);
1979 }
1980 } else {
1981 pasync_ctx->async_data.busy_entries--;
1982 if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
1983 list_add_tail(&pasync_handle->link,
1984 &pasync_ctx->async_entry[cri].wait_queue.
1985 list);
1986 pasync_ctx->async_entry[cri].wait_queue.
1987 bytes_received +=
1988 (unsigned short)pasync_handle->buffer_len;
1989
1990 if (pasync_ctx->async_entry[cri].wait_queue.
1991 bytes_received >=
1992 pasync_ctx->async_entry[cri].wait_queue.
1993 bytes_needed)
1994 status = hwi_fwd_async_msg(beiscsi_conn, phba,
1995 pasync_ctx, cri);
1996 }
1997 }
1998 return status;
1999}
2000
2001static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
2002 struct beiscsi_hba *phba,
2003 struct i_t_dpdu_cqe *pdpdu_cqe)
2004{
2005 struct hwi_controller *phwi_ctrlr;
2006 struct hwi_async_pdu_context *pasync_ctx;
2007 struct async_pdu_handle *pasync_handle = NULL;
2008 unsigned int cq_index = -1;
8a86e833
JK		 2009 uint16_t cri_index = BE_GET_CRI_FROM_CID(
2010 beiscsi_conn->beiscsi_conn_cid);
6733b39a
JK		 2011
2012 phwi_ctrlr = phba->phwi_ctrlr;
8a86e833
JK		 2013 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr,
2014 BEISCSI_GET_ULP_FROM_CRI(phwi_ctrlr,
2015 cri_index));
2016
6733b39a
JK		 2017 pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
2018 pdpdu_cqe, &cq_index);
2019
2020 if (pasync_handle->consumed == 0)
99bc5d55
JSJ		 2021 hwi_update_async_writables(phba, pasync_ctx,
2022 pasync_handle->is_header, cq_index);
2023
6733b39a 2024 hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
8a86e833
JK		 2025 hwi_post_async_buffers(phba, pasync_handle->is_header,
2026 BEISCSI_GET_ULP_FROM_CRI(
2027 phwi_ctrlr, cri_index));
6733b39a
JK		 2028}
2029
756d29c8
JK		 2030static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
2031{
2032 struct be_queue_info *mcc_cq;
2033 struct be_mcc_compl *mcc_compl;
2034 unsigned int num_processed = 0;
2035
2036 mcc_cq = &phba->ctrl.mcc_obj.cq;
2037 mcc_compl = queue_tail_node(mcc_cq);
2038 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
2039 while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
2040
2041 if (num_processed >= 32) {
2042 hwi_ring_cq_db(phba, mcc_cq->id,
2043 num_processed, 0, 0);
2044 num_processed = 0;
2045 }
2046 if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
2047 /* Interpret flags as an async trailer */
2048 if (is_link_state_evt(mcc_compl->flags))
2049 /* Interpret compl as a async link evt */
2050 beiscsi_async_link_state_process(phba,
2051 (struct be_async_event_link_state *) mcc_compl);
3efde862 2052 else {
99bc5d55
JSJ		 2053 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX,
2054 "BM_%d : Unsupported Async Event, flags"
2055 " = 0x%08x\n",
2056 mcc_compl->flags);
3efde862
JSJ		 2057 if (phba->state & BE_ADAPTER_LINK_UP) {
2058 phba->state |= BE_ADAPTER_CHECK_BOOT;
2059 phba->get_boot = BE_GET_BOOT_RETRIES;
2060 }
2061 }
756d29c8
JK		 2062 } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
2063 be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
2064 atomic_dec(&phba->ctrl.mcc_obj.q.used);
2065 }
2066
2067 mcc_compl->flags = 0;
2068 queue_tail_inc(mcc_cq);
2069 mcc_compl = queue_tail_node(mcc_cq);
2070 mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
2071 num_processed++;
2072 }
2073
2074 if (num_processed > 0)
2075 hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
2076
2077}
bfead3b2 2078
6763daae
JSJ		 2079/**
2080 * beiscsi_process_cq()- Process the Completion Queue
2081 * @pbe_eq: Event Q on which the Completion has come
2082 *
2083 * return
2084 * Number of Completion Entries processed.
2085 **/
b7ab35b1 2086unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
6733b39a 2087{
6733b39a
JK		 2088 struct be_queue_info *cq;
2089 struct sol_cqe *sol;
2090 struct dmsg_cqe *dmsg;
2091 unsigned int num_processed = 0;
2092 unsigned int tot_nump = 0;
0a513dd8 2093 unsigned short code = 0, cid = 0;
a7909b39 2094 uint16_t cri_index = 0;
6733b39a 2095 struct beiscsi_conn *beiscsi_conn;
c2462288
JK		 2096 struct beiscsi_endpoint *beiscsi_ep;
2097 struct iscsi_endpoint *ep;
bfead3b2 2098 struct beiscsi_hba *phba;
6733b39a 2099
bfead3b2 2100 cq = pbe_eq->cq;
6733b39a 2101 sol = queue_tail_node(cq);
bfead3b2 2102 phba = pbe_eq->phba;
6733b39a
JK		 2103
2104 while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
2105 CQE_VALID_MASK) {
2106 be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
2107
73133261
JSJ		 2108 code = (sol->dw[offsetof(struct amap_sol_cqe, code) /
2109 32] & CQE_CODE_MASK);
2110
2111 /* Get the CID */
2c9dfd36
JK		 2112 if (is_chip_be2_be3r(phba)) {
2113 cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol);
2114 } else {
73133261
JSJ		 2115 if ((code == DRIVERMSG_NOTIFY) ||
2116 (code == UNSOL_HDR_NOTIFY) ||
2117 (code == UNSOL_DATA_NOTIFY))
2118 cid = AMAP_GET_BITS(
2119 struct amap_i_t_dpdu_cqe_v2,
2120 cid, sol);
2121 else
2122 cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
2123 cid, sol);
2c9dfd36 2124 }
32951dd8 2125
a7909b39
JK		 2126 cri_index = BE_GET_CRI_FROM_CID(cid);
2127 ep = phba->ep_array[cri_index];
b7ab35b1
JK		 2128
2129 if (ep == NULL) {
2130 /* connection has already been freed
2131 * just move on to next one
2132 */
2133 beiscsi_log(phba, KERN_WARNING,
2134 BEISCSI_LOG_INIT,
2135 "BM_%d : proc cqe of disconn ep: cid %d\n",
2136 cid);
2137 goto proc_next_cqe;
2138 }
2139
c2462288
JK		 2140 beiscsi_ep = ep->dd_data;
2141 beiscsi_conn = beiscsi_ep->conn;
756d29c8 2142
6733b39a 2143 if (num_processed >= 32) {
bfead3b2 2144 hwi_ring_cq_db(phba, cq->id,
6733b39a
JK		 2145 num_processed, 0, 0);
2146 tot_nump += num_processed;
2147 num_processed = 0;
2148 }
2149
0a513dd8 2150 switch (code) {
6733b39a
JK		 2151 case SOL_CMD_COMPLETE:
2152 hwi_complete_cmd(beiscsi_conn, phba, sol);
2153 break;
2154 case DRIVERMSG_NOTIFY:
99bc5d55
JSJ		 2155 beiscsi_log(phba, KERN_INFO,
2156 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2157 "BM_%d : Received %s[%d] on CID : %d\n",
2158 cqe_desc[code], code, cid);
99bc5d55 2159
6733b39a
JK		 2160 dmsg = (struct dmsg_cqe *)sol;
2161 hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
2162 break;
2163 case UNSOL_HDR_NOTIFY:
99bc5d55
JSJ		 2164 beiscsi_log(phba, KERN_INFO,
2165 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2166 "BM_%d : Received %s[%d] on CID : %d\n",
2167 cqe_desc[code], code, cid);
99bc5d55 2168
8f09a3b9 2169 spin_lock_bh(&phba->async_pdu_lock);
bfead3b2
JK		 2170 hwi_process_default_pdu_ring(beiscsi_conn, phba,
2171 (struct i_t_dpdu_cqe *)sol);
8f09a3b9 2172 spin_unlock_bh(&phba->async_pdu_lock);
bfead3b2 2173 break;
6733b39a 2174 case UNSOL_DATA_NOTIFY:
99bc5d55
JSJ		 2175 beiscsi_log(phba, KERN_INFO,
2176 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
6763daae
JSJ		 2177 "BM_%d : Received %s[%d] on CID : %d\n",
2178 cqe_desc[code], code, cid);
99bc5d55 2179
8f09a3b9 2180 spin_lock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2181 hwi_process_default_pdu_ring(beiscsi_conn, phba,
2182 (struct i_t_dpdu_cqe *)sol);
8f09a3b9 2183 spin_unlock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2184 break;
2185 case CXN_INVALIDATE_INDEX_NOTIFY:
2186 case CMD_INVALIDATED_NOTIFY:
2187 case CXN_INVALIDATE_NOTIFY:
99bc5d55
JSJ		 2188 beiscsi_log(phba, KERN_ERR,
2189 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2190 "BM_%d : Ignoring %s[%d] on CID : %d\n",
2191 cqe_desc[code], code, cid);
6733b39a
JK		 2192 break;
2193 case SOL_CMD_KILLED_DATA_DIGEST_ERR:
2194 case CMD_KILLED_INVALID_STATSN_RCVD:
2195 case CMD_KILLED_INVALID_R2T_RCVD:
2196 case CMD_CXN_KILLED_LUN_INVALID:
2197 case CMD_CXN_KILLED_ICD_INVALID:
2198 case CMD_CXN_KILLED_ITT_INVALID:
2199 case CMD_CXN_KILLED_SEQ_OUTOFORDER:
2200 case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
99bc5d55
JSJ		 2201 beiscsi_log(phba, KERN_ERR,
2202 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
6763daae
JSJ		 2203 "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
2204 cqe_desc[code], code, cid);
6733b39a
JK		 2205 break;
2206 case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
99bc5d55
JSJ		 2207 beiscsi_log(phba, KERN_ERR,
2208 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2209 "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
2210 cqe_desc[code], code, cid);
8f09a3b9 2211 spin_lock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2212 hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
2213 (struct i_t_dpdu_cqe *) sol);
8f09a3b9 2214 spin_unlock_bh(&phba->async_pdu_lock);
6733b39a
JK		 2215 break;
2216 case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
2217 case CXN_KILLED_BURST_LEN_MISMATCH:
2218 case CXN_KILLED_AHS_RCVD:
2219 case CXN_KILLED_HDR_DIGEST_ERR:
2220 case CXN_KILLED_UNKNOWN_HDR:
2221 case CXN_KILLED_STALE_ITT_TTT_RCVD:
2222 case CXN_KILLED_INVALID_ITT_TTT_RCVD:
2223 case CXN_KILLED_TIMED_OUT:
2224 case CXN_KILLED_FIN_RCVD:
6763daae
JSJ		 2225 case CXN_KILLED_RST_SENT:
2226 case CXN_KILLED_RST_RCVD:
6733b39a
JK		 2227 case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
2228 case CXN_KILLED_BAD_WRB_INDEX_ERROR:
2229 case CXN_KILLED_OVER_RUN_RESIDUAL:
2230 case CXN_KILLED_UNDER_RUN_RESIDUAL:
2231 case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
99bc5d55
JSJ		 2232 beiscsi_log(phba, KERN_ERR,
2233 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2234 "BM_%d : Event %s[%d] received on CID : %d\n",
2235 cqe_desc[code], code, cid);
0a513dd8
JSJ		 2236 if (beiscsi_conn)
2237 iscsi_conn_failure(beiscsi_conn->conn,
2238 ISCSI_ERR_CONN_FAILED);
6733b39a
JK		 2239 break;
2240 default:
99bc5d55
JSJ		 2241 beiscsi_log(phba, KERN_ERR,
2242 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
6763daae
JSJ		 2243 "BM_%d : Invalid CQE Event Received Code : %d"
2244 "CID 0x%x...\n",
0a513dd8 2245 code, cid);
6733b39a
JK		 2246 break;
2247 }
2248
b7ab35b1 2249proc_next_cqe:
6733b39a
JK		 2250 AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
2251 queue_tail_inc(cq);
2252 sol = queue_tail_node(cq);
2253 num_processed++;
2254 }
2255
2256 if (num_processed > 0) {
2257 tot_nump += num_processed;
bfead3b2 2258 hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
6733b39a
JK		 2259 }
2260 return tot_nump;
2261}
2262
756d29c8 2263void beiscsi_process_all_cqs(struct work_struct *work)
6733b39a
JK		 2264{
2265 unsigned long flags;
bfead3b2
JK		 2266 struct hwi_controller *phwi_ctrlr;
2267 struct hwi_context_memory *phwi_context;
72fb46a9
JSJ		 2268 struct beiscsi_hba *phba;
2269 struct be_eq_obj *pbe_eq =
2270 container_of(work, struct be_eq_obj, work_cqs);
6733b39a 2271
72fb46a9 2272 phba = pbe_eq->phba;
bfead3b2
JK		 2273 phwi_ctrlr = phba->phwi_ctrlr;
2274 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2 2275
72fb46a9 2276 if (pbe_eq->todo_mcc_cq) {
6733b39a 2277 spin_lock_irqsave(&phba->isr_lock, flags);
72fb46a9 2278 pbe_eq->todo_mcc_cq = false;
6733b39a 2279 spin_unlock_irqrestore(&phba->isr_lock, flags);
756d29c8 2280 beiscsi_process_mcc_isr(phba);
6733b39a
JK		 2281 }
2282
72fb46a9 2283 if (pbe_eq->todo_cq) {
6733b39a 2284 spin_lock_irqsave(&phba->isr_lock, flags);
72fb46a9 2285 pbe_eq->todo_cq = false;
6733b39a 2286 spin_unlock_irqrestore(&phba->isr_lock, flags);
bfead3b2 2287 beiscsi_process_cq(pbe_eq);
6733b39a 2288 }
72fb46a9
JSJ		 2289
2290 /* rearm EQ for further interrupts */
2291 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
6733b39a
JK		 2292}
2293
2294static int be_iopoll(struct blk_iopoll *iop, int budget)
2295{
ad3f428e 2296 unsigned int ret;
6733b39a 2297 struct beiscsi_hba *phba;
bfead3b2 2298 struct be_eq_obj *pbe_eq;
6733b39a 2299
bfead3b2
JK		 2300 pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
2301 ret = beiscsi_process_cq(pbe_eq);
73af08e1 2302 pbe_eq->cq_count += ret;
6733b39a 2303 if (ret < budget) {
bfead3b2 2304 phba = pbe_eq->phba;
6733b39a 2305 blk_iopoll_complete(iop);
99bc5d55
JSJ		 2306 beiscsi_log(phba, KERN_INFO,
2307 BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
2308 "BM_%d : rearm pbe_eq->q.id =%d\n",
2309 pbe_eq->q.id);
bfead3b2 2310 hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
6733b39a
JK		 2311 }
2312 return ret;
2313}
2314
09a1093a
JSJ		 2315static void
2316hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg,
2317 unsigned int num_sg, struct beiscsi_io_task *io_task)
2318{
2319 struct iscsi_sge *psgl;
2320 unsigned int sg_len, index;
2321 unsigned int sge_len = 0;
2322 unsigned long long addr;
2323 struct scatterlist *l_sg;
2324 unsigned int offset;
2325
2326 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb,
2327 io_task->bhs_pa.u.a32.address_lo);
2328 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb,
2329 io_task->bhs_pa.u.a32.address_hi);
2330
2331 l_sg = sg;
2332 for (index = 0; (index < num_sg) && (index < 2); index++,
2333 sg = sg_next(sg)) {
2334 if (index == 0) {
2335 sg_len = sg_dma_len(sg);
2336 addr = (u64) sg_dma_address(sg);
2337 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2338 sge0_addr_lo, pwrb,
2339 lower_32_bits(addr));
2340 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2341 sge0_addr_hi, pwrb,
2342 upper_32_bits(addr));
2343 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2344 sge0_len, pwrb,
2345 sg_len);
2346 sge_len = sg_len;
2347 } else {
2348 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset,
2349 pwrb, sge_len);
2350 sg_len = sg_dma_len(sg);
2351 addr = (u64) sg_dma_address(sg);
2352 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2353 sge1_addr_lo, pwrb,
2354 lower_32_bits(addr));
2355 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2356 sge1_addr_hi, pwrb,
2357 upper_32_bits(addr));
2358 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
2359 sge1_len, pwrb,
2360 sg_len);
2361 }
2362 }
2363 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2364 memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
2365
2366 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
2367
2368 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2369 io_task->bhs_pa.u.a32.address_hi);
2370 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2371 io_task->bhs_pa.u.a32.address_lo);
2372
2373 if (num_sg == 1) {
2374 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2375 1);
2376 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2377 0);
2378 } else if (num_sg == 2) {
2379 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2380 0);
2381 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2382 1);
2383 } else {
2384 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
2385 0);
2386 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
2387 0);
2388 }
2389
2390 sg = l_sg;
2391 psgl++;
2392 psgl++;
2393 offset = 0;
2394 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
2395 sg_len = sg_dma_len(sg);
2396 addr = (u64) sg_dma_address(sg);
2397 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2398 lower_32_bits(addr));
2399 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2400 upper_32_bits(addr));
2401 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
2402 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
2403 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2404 offset += sg_len;
2405 }
2406 psgl--;
2407 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2408}
2409
6733b39a
JK		 2410static void
2411hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
2412 unsigned int num_sg, struct beiscsi_io_task *io_task)
2413{
2414 struct iscsi_sge *psgl;
58ff4bd0 2415 unsigned int sg_len, index;
6733b39a
JK		 2416 unsigned int sge_len = 0;
2417 unsigned long long addr;
2418 struct scatterlist *l_sg;
2419 unsigned int offset;
2420
2421 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2422 io_task->bhs_pa.u.a32.address_lo);
2423 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2424 io_task->bhs_pa.u.a32.address_hi);
2425
2426 l_sg = sg;
48bd86cf
JK		 2427 for (index = 0; (index < num_sg) && (index < 2); index++,
2428 sg = sg_next(sg)) {
6733b39a
JK		 2429 if (index == 0) {
2430 sg_len = sg_dma_len(sg);
2431 addr = (u64) sg_dma_address(sg);
2432 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
457ff3b7 2433 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2434 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
457ff3b7 2435 ((u32)(addr >> 32)));
6733b39a
JK		 2436 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2437 sg_len);
2438 sge_len = sg_len;
6733b39a 2439 } else {
6733b39a
JK		 2440 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
2441 pwrb, sge_len);
2442 sg_len = sg_dma_len(sg);
2443 addr = (u64) sg_dma_address(sg);
2444 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
457ff3b7 2445 ((u32)(addr & 0xFFFFFFFF)));
6733b39a 2446 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
457ff3b7 2447 ((u32)(addr >> 32)));
6733b39a
JK		 2448 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
2449 sg_len);
2450 }
2451 }
2452 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2453 memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
2454
2455 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
2456
2457 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2458 io_task->bhs_pa.u.a32.address_hi);
2459 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2460 io_task->bhs_pa.u.a32.address_lo);
2461
caf818f1
JK		 2462 if (num_sg == 1) {
2463 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2464 1);
2465 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2466 0);
2467 } else if (num_sg == 2) {
2468 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2469 0);
2470 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2471 1);
2472 } else {
2473 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
2474 0);
2475 AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
2476 0);
2477 }
6733b39a
JK		 2478 sg = l_sg;
2479 psgl++;
2480 psgl++;
2481 offset = 0;
48bd86cf 2482 for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
6733b39a
JK		 2483 sg_len = sg_dma_len(sg);
2484 addr = (u64) sg_dma_address(sg);
2485 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2486 (addr & 0xFFFFFFFF));
2487 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2488 (addr >> 32));
2489 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
2490 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
2491 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2492 offset += sg_len;
2493 }
2494 psgl--;
2495 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2496}
2497
d629c471
JSJ		 2498/**
2499 * hwi_write_buffer()- Populate the WRB with task info
2500 * @pwrb: ptr to the WRB entry
2501 * @task: iscsi task which is to be executed
2502 **/
6733b39a
JK		 2503static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
2504{
2505 struct iscsi_sge *psgl;
6733b39a
JK		 2506 struct beiscsi_io_task *io_task = task->dd_data;
2507 struct beiscsi_conn *beiscsi_conn = io_task->conn;
2508 struct beiscsi_hba *phba = beiscsi_conn->phba;
09a1093a 2509 uint8_t dsp_value = 0;
6733b39a
JK		 2510
2511 io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
2512 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
2513 io_task->bhs_pa.u.a32.address_lo);
2514 AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
2515 io_task->bhs_pa.u.a32.address_hi);
2516
2517 if (task->data) {
09a1093a
JSJ		 2518
2519 /* Check for the data_count */
2520 dsp_value = (task->data_count) ? 1 : 0;
2521
2c9dfd36
JK		 2522 if (is_chip_be2_be3r(phba))
2523 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp,
09a1093a
JSJ		 2524 pwrb, dsp_value);
2525 else
2c9dfd36 2526 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp,
09a1093a
JSJ		 2527 pwrb, dsp_value);
2528
2529 /* Map addr only if there is data_count */
2530 if (dsp_value) {
d629c471
JSJ		 2531 io_task->mtask_addr = pci_map_single(phba->pcidev,
2532 task->data,
2533 task->data_count,
2534 PCI_DMA_TODEVICE);
d629c471 2535 io_task->mtask_data_count = task->data_count;
09a1093a 2536 } else
d629c471 2537 io_task->mtask_addr = 0;
09a1093a 2538
6733b39a 2539 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
d629c471 2540 lower_32_bits(io_task->mtask_addr));
6733b39a 2541 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
d629c471 2542 upper_32_bits(io_task->mtask_addr));
6733b39a
JK		 2543 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
2544 task->data_count);
2545
2546 AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
2547 } else {
2548 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
d629c471 2549 io_task->mtask_addr = 0;
6733b39a
JK		 2550 }
2551
2552 psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
2553
2554 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
2555
2556 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
2557 io_task->bhs_pa.u.a32.address_hi);
2558 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
2559 io_task->bhs_pa.u.a32.address_lo);
2560 if (task->data) {
2561 psgl++;
2562 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
2563 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
2564 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
2565 AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
2566 AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
2567 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
2568
2569 psgl++;
2570 if (task->data) {
2571 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
d629c471 2572 lower_32_bits(io_task->mtask_addr));
6733b39a 2573 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
d629c471 2574 upper_32_bits(io_task->mtask_addr));
6733b39a
JK		 2575 }
2576 AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
2577 }
2578 AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
2579}
2580
843ae752
JK		 2581/**
2582 * beiscsi_find_mem_req()- Find mem needed
2583 * @phba: ptr to HBA struct
2584 **/
6733b39a
JK		 2585static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
2586{
8a86e833 2587 uint8_t mem_descr_index, ulp_num;
bfead3b2 2588 unsigned int num_cq_pages, num_async_pdu_buf_pages;
6733b39a
JK		 2589 unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
2590 unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
2591
2592 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
2593 sizeof(struct sol_cqe));
6733b39a
JK		 2594
2595 phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
2596
2597 phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
2598 BE_ISCSI_PDU_HEADER_SIZE;
2599 phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
2600 sizeof(struct hwi_context_memory);
2601
6733b39a
JK		 2602
2603 phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
2604 * (phba->params.wrbs_per_cxn)
2605 * phba->params.cxns_per_ctrl;
2606 wrb_sz_per_cxn = sizeof(struct wrb_handle) *
2607 (phba->params.wrbs_per_cxn);
2608 phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
2609 phba->params.cxns_per_ctrl);
2610
2611 phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
2612 phba->params.icds_per_ctrl;
2613 phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
2614 phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
8a86e833
JK		 2615 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
2616 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 2617
8a86e833
JK		 2618 num_async_pdu_buf_sgl_pages =
2619 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2620 phba, ulp_num) *
2621 sizeof(struct phys_addr));
2622
2623 num_async_pdu_buf_pages =
2624 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2625 phba, ulp_num) *
2626 phba->params.defpdu_hdr_sz);
2627
2628 num_async_pdu_data_pages =
2629 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2630 phba, ulp_num) *
2631 phba->params.defpdu_data_sz);
2632
2633 num_async_pdu_data_sgl_pages =
2634 PAGES_REQUIRED(BEISCSI_GET_CID_COUNT(
2635 phba, ulp_num) *
2636 sizeof(struct phys_addr));
2637
a129d92f
JK		 2638 mem_descr_index = (HWI_MEM_TEMPLATE_HDR_ULP0 +
2639 (ulp_num * MEM_DESCR_OFFSET));
2640 phba->mem_req[mem_descr_index] =
2641 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2642 BEISCSI_TEMPLATE_HDR_PER_CXN_SIZE;
2643
8a86e833
JK		 2644 mem_descr_index = (HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
2645 (ulp_num * MEM_DESCR_OFFSET));
2646 phba->mem_req[mem_descr_index] =
2647 num_async_pdu_buf_pages *
2648 PAGE_SIZE;
2649
2650 mem_descr_index = (HWI_MEM_ASYNC_DATA_BUF_ULP0 +
2651 (ulp_num * MEM_DESCR_OFFSET));
2652 phba->mem_req[mem_descr_index] =
2653 num_async_pdu_data_pages *
2654 PAGE_SIZE;
2655
2656 mem_descr_index = (HWI_MEM_ASYNC_HEADER_RING_ULP0 +
2657 (ulp_num * MEM_DESCR_OFFSET));
2658 phba->mem_req[mem_descr_index] =
2659 num_async_pdu_buf_sgl_pages *
2660 PAGE_SIZE;
2661
2662 mem_descr_index = (HWI_MEM_ASYNC_DATA_RING_ULP0 +
2663 (ulp_num * MEM_DESCR_OFFSET));
2664 phba->mem_req[mem_descr_index] =
2665 num_async_pdu_data_sgl_pages *
2666 PAGE_SIZE;
2667
2668 mem_descr_index = (HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
2669 (ulp_num * MEM_DESCR_OFFSET));
2670 phba->mem_req[mem_descr_index] =
2671 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2672 sizeof(struct async_pdu_handle);
2673
2674 mem_descr_index = (HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
2675 (ulp_num * MEM_DESCR_OFFSET));
2676 phba->mem_req[mem_descr_index] =
2677 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2678 sizeof(struct async_pdu_handle);
2679
2680 mem_descr_index = (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
2681 (ulp_num * MEM_DESCR_OFFSET));
2682 phba->mem_req[mem_descr_index] =
2683 sizeof(struct hwi_async_pdu_context) +
2684 (BEISCSI_GET_CID_COUNT(phba, ulp_num) *
2685 sizeof(struct hwi_async_entry));
2686 }
2687 }
6733b39a
JK		 2688}
2689
2690static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
2691{
6733b39a 2692 dma_addr_t bus_add;
a7909b39
JK		 2693 struct hwi_controller *phwi_ctrlr;
2694 struct be_mem_descriptor *mem_descr;
6733b39a
JK		 2695 struct mem_array *mem_arr, *mem_arr_orig;
2696 unsigned int i, j, alloc_size, curr_alloc_size;
2697
3ec78271 2698 phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
6733b39a
JK		 2699 if (!phba->phwi_ctrlr)
2700 return -ENOMEM;
2701
a7909b39
JK		 2702 /* Allocate memory for wrb_context */
2703 phwi_ctrlr = phba->phwi_ctrlr;
2704 phwi_ctrlr->wrb_context = kzalloc(sizeof(struct hwi_wrb_context) *
2705 phba->params.cxns_per_ctrl,
2706 GFP_KERNEL);
2707 if (!phwi_ctrlr->wrb_context)
2708 return -ENOMEM;
2709
6733b39a
JK		 2710 phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
2711 GFP_KERNEL);
2712 if (!phba->init_mem) {
a7909b39 2713 kfree(phwi_ctrlr->wrb_context);
6733b39a
JK		 2714 kfree(phba->phwi_ctrlr);
2715 return -ENOMEM;
2716 }
2717
2718 mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
2719 GFP_KERNEL);
2720 if (!mem_arr_orig) {
2721 kfree(phba->init_mem);
a7909b39 2722 kfree(phwi_ctrlr->wrb_context);
6733b39a
JK		 2723 kfree(phba->phwi_ctrlr);
2724 return -ENOMEM;
2725 }
2726
2727 mem_descr = phba->init_mem;
2728 for (i = 0; i < SE_MEM_MAX; i++) {
8a86e833
JK		 2729 if (!phba->mem_req[i]) {
2730 mem_descr->mem_array = NULL;
2731 mem_descr++;
2732 continue;
2733 }
2734
6733b39a
JK		 2735 j = 0;
2736 mem_arr = mem_arr_orig;
2737 alloc_size = phba->mem_req[i];
2738 memset(mem_arr, 0, sizeof(struct mem_array) *
2739 BEISCSI_MAX_FRAGS_INIT);
2740 curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
2741 do {
2742 mem_arr->virtual_address = pci_alloc_consistent(
2743 phba->pcidev,
2744 curr_alloc_size,
2745 &bus_add);
2746 if (!mem_arr->virtual_address) {
2747 if (curr_alloc_size <= BE_MIN_MEM_SIZE)
2748 goto free_mem;
2749 if (curr_alloc_size -
2750 rounddown_pow_of_two(curr_alloc_size))
2751 curr_alloc_size = rounddown_pow_of_two
2752 (curr_alloc_size);
2753 else
2754 curr_alloc_size = curr_alloc_size / 2;
2755 } else {
2756 mem_arr->bus_address.u.
2757 a64.address = (__u64) bus_add;
2758 mem_arr->size = curr_alloc_size;
2759 alloc_size -= curr_alloc_size;
2760 curr_alloc_size = min(be_max_phys_size *
2761 1024, alloc_size);
2762 j++;
2763 mem_arr++;
2764 }
2765 } while (alloc_size);
2766 mem_descr->num_elements = j;
2767 mem_descr->size_in_bytes = phba->mem_req[i];
2768 mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
2769 GFP_KERNEL);
2770 if (!mem_descr->mem_array)
2771 goto free_mem;
2772
2773 memcpy(mem_descr->mem_array, mem_arr_orig,
2774 sizeof(struct mem_array) * j);
2775 mem_descr++;
2776 }
2777 kfree(mem_arr_orig);
2778 return 0;
2779free_mem:
2780 mem_descr->num_elements = j;
2781 while ((i) || (j)) {
2782 for (j = mem_descr->num_elements; j > 0; j--) {
2783 pci_free_consistent(phba->pcidev,
2784 mem_descr->mem_array[j - 1].size,
2785 mem_descr->mem_array[j - 1].
2786 virtual_address,
457ff3b7
JK		 2787 (unsigned long)mem_descr->
2788 mem_array[j - 1].
6733b39a
JK		 2789 bus_address.u.a64.address);
2790 }
2791 if (i) {
2792 i--;
2793 kfree(mem_descr->mem_array);
2794 mem_descr--;
2795 }
2796 }
2797 kfree(mem_arr_orig);
2798 kfree(phba->init_mem);
a7909b39 2799 kfree(phba->phwi_ctrlr->wrb_context);
6733b39a
JK		 2800 kfree(phba->phwi_ctrlr);
2801 return -ENOMEM;
2802}
2803
2804static int beiscsi_get_memory(struct beiscsi_hba *phba)
2805{
2806 beiscsi_find_mem_req(phba);
2807 return beiscsi_alloc_mem(phba);
2808}
2809
2810static void iscsi_init_global_templates(struct beiscsi_hba *phba)
2811{
2812 struct pdu_data_out *pdata_out;
2813 struct pdu_nop_out *pnop_out;
2814 struct be_mem_descriptor *mem_descr;
2815
2816 mem_descr = phba->init_mem;
2817 mem_descr += ISCSI_MEM_GLOBAL_HEADER;
2818 pdata_out =
2819 (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
2820 memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2821
2822 AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
2823 IIOC_SCSI_DATA);
2824
2825 pnop_out =
2826 (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
2827 virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
2828
2829 memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
2830 AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
2831 AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
2832 AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
2833}
2834
3ec78271 2835static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
6733b39a
JK		 2836{
2837 struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
a7909b39 2838 struct hwi_context_memory *phwi_ctxt;
3ec78271 2839 struct wrb_handle *pwrb_handle = NULL;
6733b39a
JK		 2840 struct hwi_controller *phwi_ctrlr;
2841 struct hwi_wrb_context *pwrb_context;
3ec78271
JK		 2842 struct iscsi_wrb *pwrb = NULL;
2843 unsigned int num_cxn_wrbh = 0;
2844 unsigned int num_cxn_wrb = 0, j, idx = 0, index;
6733b39a
JK		 2845
2846 mem_descr_wrbh = phba->init_mem;
2847 mem_descr_wrbh += HWI_MEM_WRBH;
2848
2849 mem_descr_wrb = phba->init_mem;
2850 mem_descr_wrb += HWI_MEM_WRB;
6733b39a
JK		 2851 phwi_ctrlr = phba->phwi_ctrlr;
2852
a7909b39
JK		 2853 /* Allocate memory for WRBQ */
2854 phwi_ctxt = phwi_ctrlr->phwi_ctxt;
2855 phwi_ctxt->be_wrbq = kzalloc(sizeof(struct be_queue_info) *
843ae752 2856 phba->params.cxns_per_ctrl,
a7909b39
JK		 2857 GFP_KERNEL);
2858 if (!phwi_ctxt->be_wrbq) {
2859 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2860 "BM_%d : WRBQ Mem Alloc Failed\n");
2861 return -ENOMEM;
2862 }
2863
2864 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a 2865 pwrb_context = &phwi_ctrlr->wrb_context[index];
6733b39a
JK		 2866 pwrb_context->pwrb_handle_base =
2867 kzalloc(sizeof(struct wrb_handle *) *
2868 phba->params.wrbs_per_cxn, GFP_KERNEL);
3ec78271 2869 if (!pwrb_context->pwrb_handle_base) {
99bc5d55
JSJ		 2870 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2871 "BM_%d : Mem Alloc Failed. Failing to load\n");
3ec78271
JK		 2872 goto init_wrb_hndl_failed;
2873 }
6733b39a
JK		 2874 pwrb_context->pwrb_handle_basestd =
2875 kzalloc(sizeof(struct wrb_handle *) *
2876 phba->params.wrbs_per_cxn, GFP_KERNEL);
3ec78271 2877 if (!pwrb_context->pwrb_handle_basestd) {
99bc5d55
JSJ		 2878 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
2879 "BM_%d : Mem Alloc Failed. Failing to load\n");
3ec78271
JK		 2880 goto init_wrb_hndl_failed;
2881 }
2882 if (!num_cxn_wrbh) {
2883 pwrb_handle =
2884 mem_descr_wrbh->mem_array[idx].virtual_address;
2885 num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
2886 ((sizeof(struct wrb_handle)) *
2887 phba->params.wrbs_per_cxn));
2888 idx++;
2889 }
2890 pwrb_context->alloc_index = 0;
2891 pwrb_context->wrb_handles_available = 0;
2892 pwrb_context->free_index = 0;
2893
6733b39a 2894 if (num_cxn_wrbh) {
6733b39a
JK		 2895 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2896 pwrb_context->pwrb_handle_base[j] = pwrb_handle;
2897 pwrb_context->pwrb_handle_basestd[j] =
2898 pwrb_handle;
2899 pwrb_context->wrb_handles_available++;
bfead3b2 2900 pwrb_handle->wrb_index = j;
6733b39a
JK		 2901 pwrb_handle++;
2902 }
6733b39a
JK		 2903 num_cxn_wrbh--;
2904 }
2905 }
2906 idx = 0;
a7909b39 2907 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a 2908 pwrb_context = &phwi_ctrlr->wrb_context[index];
3ec78271 2909 if (!num_cxn_wrb) {
6733b39a 2910 pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
7c56533c 2911 num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
3ec78271
JK		 2912 ((sizeof(struct iscsi_wrb) *
2913 phba->params.wrbs_per_cxn));
2914 idx++;
2915 }
2916
2917 if (num_cxn_wrb) {
6733b39a
JK		 2918 for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
2919 pwrb_handle = pwrb_context->pwrb_handle_base[j];
2920 pwrb_handle->pwrb = pwrb;
2921 pwrb++;
2922 }
2923 num_cxn_wrb--;
2924 }
2925 }
3ec78271
JK		 2926 return 0;
2927init_wrb_hndl_failed:
2928 for (j = index; j > 0; j--) {
2929 pwrb_context = &phwi_ctrlr->wrb_context[j];
2930 kfree(pwrb_context->pwrb_handle_base);
2931 kfree(pwrb_context->pwrb_handle_basestd);
2932 }
2933 return -ENOMEM;
6733b39a
JK		 2934}
2935
a7909b39 2936static int hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
6733b39a 2937{
8a86e833 2938 uint8_t ulp_num;
6733b39a
JK		 2939 struct hwi_controller *phwi_ctrlr;
2940 struct hba_parameters *p = &phba->params;
2941 struct hwi_async_pdu_context *pasync_ctx;
2942 struct async_pdu_handle *pasync_header_h, *pasync_data_h;
dc63aac6 2943 unsigned int index, idx, num_per_mem, num_async_data;
6733b39a
JK		 2944 struct be_mem_descriptor *mem_descr;
2945
8a86e833
JK		 2946 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
2947 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 2948
8a86e833
JK		 2949 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2950 mem_descr += (HWI_MEM_ASYNC_PDU_CONTEXT_ULP0 +
2951 (ulp_num * MEM_DESCR_OFFSET));
2952
2953 phwi_ctrlr = phba->phwi_ctrlr;
2954 phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num] =
2955 (struct hwi_async_pdu_context *)
2956 mem_descr->mem_array[0].virtual_address;
2957
2958 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
2959 memset(pasync_ctx, 0, sizeof(*pasync_ctx));
2960
2961 pasync_ctx->async_entry =
2962 (struct hwi_async_entry *)
2963 ((long unsigned int)pasync_ctx +
2964 sizeof(struct hwi_async_pdu_context));
2965
2966 pasync_ctx->num_entries = BEISCSI_GET_CID_COUNT(phba,
2967 ulp_num);
2968 pasync_ctx->buffer_size = p->defpdu_hdr_sz;
2969
2970 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2971 mem_descr += HWI_MEM_ASYNC_HEADER_BUF_ULP0 +
2972 (ulp_num * MEM_DESCR_OFFSET);
2973 if (mem_descr->mem_array[0].virtual_address) {
2974 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2975 "BM_%d : hwi_init_async_pdu_ctx"
2976 " HWI_MEM_ASYNC_HEADER_BUF_ULP%d va=%p\n",
2977 ulp_num,
2978 mem_descr->mem_array[0].
2979 virtual_address);
2980 } else
2981 beiscsi_log(phba, KERN_WARNING,
2982 BEISCSI_LOG_INIT,
2983 "BM_%d : No Virtual address for ULP : %d\n",
2984 ulp_num);
2985
2986 pasync_ctx->async_header.va_base =
6733b39a 2987 mem_descr->mem_array[0].virtual_address;
6733b39a 2988
8a86e833
JK		 2989 pasync_ctx->async_header.pa_base.u.a64.address =
2990 mem_descr->mem_array[0].
2991 bus_address.u.a64.address;
6733b39a 2992
8a86e833
JK		 2993 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
2994 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
2995 (ulp_num * MEM_DESCR_OFFSET);
2996 if (mem_descr->mem_array[0].virtual_address) {
2997 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
2998 "BM_%d : hwi_init_async_pdu_ctx"
2999 " HWI_MEM_ASYNC_HEADER_RING_ULP%d va=%p\n",
3000 ulp_num,
3001 mem_descr->mem_array[0].
3002 virtual_address);
3003 } else
3004 beiscsi_log(phba, KERN_WARNING,
3005 BEISCSI_LOG_INIT,
3006 "BM_%d : No Virtual address for ULP : %d\n",
3007 ulp_num);
3008
3009 pasync_ctx->async_header.ring_base =
3010 mem_descr->mem_array[0].virtual_address;
6733b39a 3011
8a86e833
JK		 3012 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3013 mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE_ULP0 +
3014 (ulp_num * MEM_DESCR_OFFSET);
3015 if (mem_descr->mem_array[0].virtual_address) {
3016 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3017 "BM_%d : hwi_init_async_pdu_ctx"
3018 " HWI_MEM_ASYNC_HEADER_HANDLE_ULP%d va=%p\n",
3019 ulp_num,
3020 mem_descr->mem_array[0].
3021 virtual_address);
3022 } else
3023 beiscsi_log(phba, KERN_WARNING,
3024 BEISCSI_LOG_INIT,
3025 "BM_%d : No Virtual address for ULP : %d\n",
3026 ulp_num);
3027
3028 pasync_ctx->async_header.handle_base =
3029 mem_descr->mem_array[0].virtual_address;
3030 pasync_ctx->async_header.writables = 0;
3031 INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
3032
3033 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3034 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
3035 (ulp_num * MEM_DESCR_OFFSET);
3036 if (mem_descr->mem_array[0].virtual_address) {
3037 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3038 "BM_%d : hwi_init_async_pdu_ctx"
3039 " HWI_MEM_ASYNC_DATA_RING_ULP%d va=%p\n",
3040 ulp_num,
3041 mem_descr->mem_array[0].
3042 virtual_address);
3043 } else
3044 beiscsi_log(phba, KERN_WARNING,
3045 BEISCSI_LOG_INIT,
3046 "BM_%d : No Virtual address for ULP : %d\n",
3047 ulp_num);
3048
3049 pasync_ctx->async_data.ring_base =
3050 mem_descr->mem_array[0].virtual_address;
6733b39a 3051
8a86e833
JK		 3052 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3053 mem_descr += HWI_MEM_ASYNC_DATA_HANDLE_ULP0 +
3054 (ulp_num * MEM_DESCR_OFFSET);
3055 if (!mem_descr->mem_array[0].virtual_address)
3056 beiscsi_log(phba, KERN_WARNING,
3057 BEISCSI_LOG_INIT,
3058 "BM_%d : No Virtual address for ULP : %d\n",
3059 ulp_num);
99bc5d55 3060
8a86e833
JK		 3061 pasync_ctx->async_data.handle_base =
3062 mem_descr->mem_array[0].virtual_address;
3063 pasync_ctx->async_data.writables = 0;
3064 INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
3065
3066 pasync_header_h =
3067 (struct async_pdu_handle *)
3068 pasync_ctx->async_header.handle_base;
3069 pasync_data_h =
3070 (struct async_pdu_handle *)
3071 pasync_ctx->async_data.handle_base;
3072
3073 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3074 mem_descr += HWI_MEM_ASYNC_DATA_BUF_ULP0 +
3075 (ulp_num * MEM_DESCR_OFFSET);
3076 if (mem_descr->mem_array[0].virtual_address) {
3077 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3078 "BM_%d : hwi_init_async_pdu_ctx"
3079 " HWI_MEM_ASYNC_DATA_BUF_ULP%d va=%p\n",
3080 ulp_num,
3081 mem_descr->mem_array[0].
3082 virtual_address);
3083 } else
3084 beiscsi_log(phba, KERN_WARNING,
3085 BEISCSI_LOG_INIT,
3086 "BM_%d : No Virtual address for ULP : %d\n",
3087 ulp_num);
3088
3089 idx = 0;
dc63aac6
JK		 3090 pasync_ctx->async_data.va_base =
3091 mem_descr->mem_array[idx].virtual_address;
3092 pasync_ctx->async_data.pa_base.u.a64.address =
3093 mem_descr->mem_array[idx].
3094 bus_address.u.a64.address;
3095
3096 num_async_data = ((mem_descr->mem_array[idx].size) /
3097 phba->params.defpdu_data_sz);
8a86e833 3098 num_per_mem = 0;
6733b39a 3099
8a86e833
JK		 3100 for (index = 0; index < BEISCSI_GET_CID_COUNT
3101 (phba, ulp_num); index++) {
3102 pasync_header_h->cri = -1;
3103 pasync_header_h->index = (char)index;
3104 INIT_LIST_HEAD(&pasync_header_h->link);
3105 pasync_header_h->pbuffer =
3106 (void *)((unsigned long)
3107 (pasync_ctx->
3108 async_header.va_base) +
3109 (p->defpdu_hdr_sz * index));
3110
3111 pasync_header_h->pa.u.a64.address =
3112 pasync_ctx->async_header.pa_base.u.a64.
3113 address + (p->defpdu_hdr_sz * index);
3114
3115 list_add_tail(&pasync_header_h->link,
3116 &pasync_ctx->async_header.
3117 free_list);
3118 pasync_header_h++;
3119 pasync_ctx->async_header.free_entries++;
3120 pasync_ctx->async_header.writables++;
3121
3122 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
3123 wait_queue.list);
3124 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
3125 header_busy_list);
3126 pasync_data_h->cri = -1;
3127 pasync_data_h->index = (char)index;
3128 INIT_LIST_HEAD(&pasync_data_h->link);
3129
3130 if (!num_async_data) {
3131 num_per_mem = 0;
3132 idx++;
3133 pasync_ctx->async_data.va_base =
3134 mem_descr->mem_array[idx].
3135 virtual_address;
3136 pasync_ctx->async_data.pa_base.u.
3137 a64.address =
3138 mem_descr->mem_array[idx].
3139 bus_address.u.a64.address;
3140 num_async_data =
3141 ((mem_descr->mem_array[idx].
3142 size) /
3143 phba->params.defpdu_data_sz);
3144 }
3145 pasync_data_h->pbuffer =
3146 (void *)((unsigned long)
3147 (pasync_ctx->async_data.va_base) +
3148 (p->defpdu_data_sz * num_per_mem));
3149
3150 pasync_data_h->pa.u.a64.address =
3151 pasync_ctx->async_data.pa_base.u.a64.
3152 address + (p->defpdu_data_sz *
3153 num_per_mem);
3154 num_per_mem++;
3155 num_async_data--;
3156
3157 list_add_tail(&pasync_data_h->link,
3158 &pasync_ctx->async_data.
3159 free_list);
3160 pasync_data_h++;
3161 pasync_ctx->async_data.free_entries++;
3162 pasync_ctx->async_data.writables++;
3163
3164 INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
3165 data_busy_list);
3166 }
6733b39a 3167
8a86e833
JK		 3168 pasync_ctx->async_header.host_write_ptr = 0;
3169 pasync_ctx->async_header.ep_read_ptr = -1;
3170 pasync_ctx->async_data.host_write_ptr = 0;
3171 pasync_ctx->async_data.ep_read_ptr = -1;
3172 }
6733b39a
JK		 3173 }
3174
a7909b39 3175 return 0;
6733b39a
JK		 3176}
3177
3178static int
3179be_sgl_create_contiguous(void *virtual_address,
3180 u64 physical_address, u32 length,
3181 struct be_dma_mem *sgl)
3182{
3183 WARN_ON(!virtual_address);
3184 WARN_ON(!physical_address);
3185 WARN_ON(!length > 0);
3186 WARN_ON(!sgl);
3187
3188 sgl->va = virtual_address;
457ff3b7 3189 sgl->dma = (unsigned long)physical_address;
6733b39a
JK		 3190 sgl->size = length;
3191
3192 return 0;
3193}
3194
3195static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
3196{
3197 memset(sgl, 0, sizeof(*sgl));
3198}
3199
3200static void
3201hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
3202 struct mem_array *pmem, struct be_dma_mem *sgl)
3203{
3204 if (sgl->va)
3205 be_sgl_destroy_contiguous(sgl);
3206
3207 be_sgl_create_contiguous(pmem->virtual_address,
3208 pmem->bus_address.u.a64.address,
3209 pmem->size, sgl);
3210}
3211
3212static void
3213hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
3214 struct mem_array *pmem, struct be_dma_mem *sgl)
3215{
3216 if (sgl->va)
3217 be_sgl_destroy_contiguous(sgl);
3218
3219 be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
3220 pmem->bus_address.u.a64.address,
3221 pmem->size, sgl);
3222}
3223
3224static int be_fill_queue(struct be_queue_info *q,
3225 u16 len, u16 entry_size, void *vaddress)
3226{
3227 struct be_dma_mem *mem = &q->dma_mem;
3228
3229 memset(q, 0, sizeof(*q));
3230 q->len = len;
3231 q->entry_size = entry_size;
3232 mem->size = len * entry_size;
3233 mem->va = vaddress;
3234 if (!mem->va)
3235 return -ENOMEM;
3236 memset(mem->va, 0, mem->size);
3237 return 0;
3238}
3239
bfead3b2 3240static int beiscsi_create_eqs(struct beiscsi_hba *phba,
6733b39a
JK		 3241 struct hwi_context_memory *phwi_context)
3242{
bfead3b2 3243 unsigned int i, num_eq_pages;
99bc5d55 3244 int ret = 0, eq_for_mcc;
6733b39a
JK		 3245 struct be_queue_info *eq;
3246 struct be_dma_mem *mem;
6733b39a 3247 void *eq_vaddress;
bfead3b2 3248 dma_addr_t paddr;
6733b39a 3249
bfead3b2
JK		 3250 num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
3251 sizeof(struct be_eq_entry));
6733b39a 3252
bfead3b2
JK		 3253 if (phba->msix_enabled)
3254 eq_for_mcc = 1;
3255 else
3256 eq_for_mcc = 0;
3257 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
3258 eq = &phwi_context->be_eq[i].q;
3259 mem = &eq->dma_mem;
3260 phwi_context->be_eq[i].phba = phba;
3261 eq_vaddress = pci_alloc_consistent(phba->pcidev,
3262 num_eq_pages * PAGE_SIZE,
3263 &paddr);
3264 if (!eq_vaddress)
3265 goto create_eq_error;
3266
3267 mem->va = eq_vaddress;
3268 ret = be_fill_queue(eq, phba->params.num_eq_entries,
3269 sizeof(struct be_eq_entry), eq_vaddress);
3270 if (ret) {
99bc5d55
JSJ		 3271 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3272 "BM_%d : be_fill_queue Failed for EQ\n");
bfead3b2
JK		 3273 goto create_eq_error;
3274 }
6733b39a 3275
bfead3b2
JK		 3276 mem->dma = paddr;
3277 ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
3278 phwi_context->cur_eqd);
3279 if (ret) {
99bc5d55
JSJ		 3280 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3281 "BM_%d : beiscsi_cmd_eq_create"
3282 "Failed for EQ\n");
bfead3b2
JK		 3283 goto create_eq_error;
3284 }
99bc5d55
JSJ		 3285
3286 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3287 "BM_%d : eqid = %d\n",
3288 phwi_context->be_eq[i].q.id);
6733b39a 3289 }
6733b39a 3290 return 0;
bfead3b2 3291create_eq_error:
107dfcba 3292 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
bfead3b2
JK		 3293 eq = &phwi_context->be_eq[i].q;
3294 mem = &eq->dma_mem;
3295 if (mem->va)
3296 pci_free_consistent(phba->pcidev, num_eq_pages
3297 * PAGE_SIZE,
3298 mem->va, mem->dma);
3299 }
3300 return ret;
6733b39a
JK		 3301}
3302
bfead3b2 3303static int beiscsi_create_cqs(struct beiscsi_hba *phba,
6733b39a
JK		 3304 struct hwi_context_memory *phwi_context)
3305{
bfead3b2 3306 unsigned int i, num_cq_pages;
99bc5d55 3307 int ret = 0;
6733b39a
JK		 3308 struct be_queue_info *cq, *eq;
3309 struct be_dma_mem *mem;
bfead3b2 3310 struct be_eq_obj *pbe_eq;
6733b39a 3311 void *cq_vaddress;
bfead3b2 3312 dma_addr_t paddr;
6733b39a 3313
bfead3b2
JK		 3314 num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
3315 sizeof(struct sol_cqe));
6733b39a 3316
bfead3b2
JK		 3317 for (i = 0; i < phba->num_cpus; i++) {
3318 cq = &phwi_context->be_cq[i];
3319 eq = &phwi_context->be_eq[i].q;
3320 pbe_eq = &phwi_context->be_eq[i];
3321 pbe_eq->cq = cq;
3322 pbe_eq->phba = phba;
3323 mem = &cq->dma_mem;
3324 cq_vaddress = pci_alloc_consistent(phba->pcidev,
3325 num_cq_pages * PAGE_SIZE,
3326 &paddr);
3327 if (!cq_vaddress)
3328 goto create_cq_error;
7da50879 3329 ret = be_fill_queue(cq, phba->params.num_cq_entries,
bfead3b2
JK		 3330 sizeof(struct sol_cqe), cq_vaddress);
3331 if (ret) {
99bc5d55
JSJ		 3332 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3333 "BM_%d : be_fill_queue Failed "
3334 "for ISCSI CQ\n");
bfead3b2
JK		 3335 goto create_cq_error;
3336 }
3337
3338 mem->dma = paddr;
3339 ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
3340 false, 0);
3341 if (ret) {
99bc5d55
JSJ		 3342 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3343 "BM_%d : beiscsi_cmd_eq_create"
3344 "Failed for ISCSI CQ\n");
bfead3b2
JK		 3345 goto create_cq_error;
3346 }
99bc5d55
JSJ		 3347 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3348 "BM_%d : iscsi cq_id is %d for eq_id %d\n"
3349 "iSCSI CQ CREATED\n", cq->id, eq->id);
6733b39a 3350 }
6733b39a 3351 return 0;
bfead3b2
JK		 3352
3353create_cq_error:
3354 for (i = 0; i < phba->num_cpus; i++) {
3355 cq = &phwi_context->be_cq[i];
3356 mem = &cq->dma_mem;
3357 if (mem->va)
3358 pci_free_consistent(phba->pcidev, num_cq_pages
3359 * PAGE_SIZE,
3360 mem->va, mem->dma);
3361 }
3362 return ret;
3363
6733b39a
JK		 3364}
3365
3366static int
3367beiscsi_create_def_hdr(struct beiscsi_hba *phba,
3368 struct hwi_context_memory *phwi_context,
3369 struct hwi_controller *phwi_ctrlr,
8a86e833 3370 unsigned int def_pdu_ring_sz, uint8_t ulp_num)
6733b39a
JK		 3371{
3372 unsigned int idx;
3373 int ret;
3374 struct be_queue_info *dq, *cq;
3375 struct be_dma_mem *mem;
3376 struct be_mem_descriptor *mem_descr;
3377 void *dq_vaddress;
3378
3379 idx = 0;
8a86e833 3380 dq = &phwi_context->be_def_hdrq[ulp_num];
bfead3b2 3381 cq = &phwi_context->be_cq[0];
6733b39a
JK		 3382 mem = &dq->dma_mem;
3383 mem_descr = phba->init_mem;
8a86e833
JK		 3384 mem_descr += HWI_MEM_ASYNC_HEADER_RING_ULP0 +
3385 (ulp_num * MEM_DESCR_OFFSET);
6733b39a
JK		 3386 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
3387 ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
3388 sizeof(struct phys_addr),
3389 sizeof(struct phys_addr), dq_vaddress);
3390 if (ret) {
99bc5d55 3391 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3392 "BM_%d : be_fill_queue Failed for DEF PDU HDR on ULP : %d\n",
3393 ulp_num);
3394
6733b39a
JK		 3395 return ret;
3396 }
457ff3b7
JK		 3397 mem->dma = (unsigned long)mem_descr->mem_array[idx].
3398 bus_address.u.a64.address;
6733b39a
JK		 3399 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
3400 def_pdu_ring_sz,
8a86e833
JK		 3401 phba->params.defpdu_hdr_sz,
3402 BEISCSI_DEFQ_HDR, ulp_num);
6733b39a 3403 if (ret) {
99bc5d55 3404 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3405 "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR on ULP : %d\n",
3406 ulp_num);
3407
6733b39a
JK		 3408 return ret;
3409 }
99bc5d55 3410
8a86e833
JK		 3411 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3412 "BM_%d : iscsi hdr def pdu id for ULP : %d is %d\n",
3413 ulp_num,
3414 phwi_context->be_def_hdrq[ulp_num].id);
3415 hwi_post_async_buffers(phba, BEISCSI_DEFQ_HDR, ulp_num);
6733b39a
JK		 3416 return 0;
3417}
3418
3419static int
3420beiscsi_create_def_data(struct beiscsi_hba *phba,
3421 struct hwi_context_memory *phwi_context,
3422 struct hwi_controller *phwi_ctrlr,
8a86e833 3423 unsigned int def_pdu_ring_sz, uint8_t ulp_num)
6733b39a
JK		 3424{
3425 unsigned int idx;
3426 int ret;
3427 struct be_queue_info *dataq, *cq;
3428 struct be_dma_mem *mem;
3429 struct be_mem_descriptor *mem_descr;
3430 void *dq_vaddress;
3431
3432 idx = 0;
8a86e833 3433 dataq = &phwi_context->be_def_dataq[ulp_num];
bfead3b2 3434 cq = &phwi_context->be_cq[0];
6733b39a
JK		 3435 mem = &dataq->dma_mem;
3436 mem_descr = phba->init_mem;
8a86e833
JK		 3437 mem_descr += HWI_MEM_ASYNC_DATA_RING_ULP0 +
3438 (ulp_num * MEM_DESCR_OFFSET);
6733b39a
JK		 3439 dq_vaddress = mem_descr->mem_array[idx].virtual_address;
3440 ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
3441 sizeof(struct phys_addr),
3442 sizeof(struct phys_addr), dq_vaddress);
3443 if (ret) {
99bc5d55 3444 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
8a86e833
JK		 3445 "BM_%d : be_fill_queue Failed for DEF PDU "
3446 "DATA on ULP : %d\n",
3447 ulp_num);
3448
6733b39a
JK		 3449 return ret;
3450 }
457ff3b7
JK		 3451 mem->dma = (unsigned long)mem_descr->mem_array[idx].
3452 bus_address.u.a64.address;
6733b39a
JK		 3453 ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
3454 def_pdu_ring_sz,
8a86e833
JK		 3455 phba->params.defpdu_data_sz,
3456 BEISCSI_DEFQ_DATA, ulp_num);
6733b39a 3457 if (ret) {
99bc5d55
JSJ		 3458 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3459 "BM_%d be_cmd_create_default_pdu_queue"
8a86e833
JK		 3460 " Failed for DEF PDU DATA on ULP : %d\n",
3461 ulp_num);
6733b39a
JK		 3462 return ret;
3463 }
8a86e833 3464
99bc5d55 3465 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
8a86e833
JK		 3466 "BM_%d : iscsi def data id on ULP : %d is %d\n",
3467 ulp_num,
3468 phwi_context->be_def_dataq[ulp_num].id);
99bc5d55 3469
8a86e833 3470 hwi_post_async_buffers(phba, BEISCSI_DEFQ_DATA, ulp_num);
99bc5d55 3471 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
8a86e833
JK		 3472 "BM_%d : DEFAULT PDU DATA RING CREATED"
3473 "on ULP : %d\n", ulp_num);
99bc5d55 3474
6733b39a
JK		 3475 return 0;
3476}
3477
15a90fe0
JK		 3478
3479static int
3480beiscsi_post_template_hdr(struct beiscsi_hba *phba)
3481{
3482 struct be_mem_descriptor *mem_descr;
3483 struct mem_array *pm_arr;
3484 struct be_dma_mem sgl;
a129d92f 3485 int status, ulp_num;
15a90fe0 3486
a129d92f
JK		 3487 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3488 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3489 mem_descr = (struct be_mem_descriptor *)phba->init_mem;
3490 mem_descr += HWI_MEM_TEMPLATE_HDR_ULP0 +
3491 (ulp_num * MEM_DESCR_OFFSET);
3492 pm_arr = mem_descr->mem_array;
15a90fe0 3493
a129d92f
JK		 3494 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
3495 status = be_cmd_iscsi_post_template_hdr(
3496 &phba->ctrl, &sgl);
15a90fe0 3497
a129d92f
JK		 3498 if (status != 0) {
3499 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3500 "BM_%d : Post Template HDR Failed for"
3501 "ULP_%d\n", ulp_num);
3502 return status;
3503 }
3504
3505 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3506 "BM_%d : Template HDR Pages Posted for"
3507 "ULP_%d\n", ulp_num);
15a90fe0
JK		 3508 }
3509 }
15a90fe0
JK		 3510 return 0;
3511}
3512
6733b39a
JK		 3513static int
3514beiscsi_post_pages(struct beiscsi_hba *phba)
3515{
3516 struct be_mem_descriptor *mem_descr;
3517 struct mem_array *pm_arr;
3518 unsigned int page_offset, i;
3519 struct be_dma_mem sgl;
843ae752 3520 int status, ulp_num = 0;
6733b39a
JK		 3521
3522 mem_descr = phba->init_mem;
3523 mem_descr += HWI_MEM_SGE;
3524 pm_arr = mem_descr->mem_array;
3525
90622db3
JK		 3526 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3527 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
3528 break;
3529
6733b39a 3530 page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
843ae752 3531 phba->fw_config.iscsi_icd_start[ulp_num]) / PAGE_SIZE;
6733b39a
JK		 3532 for (i = 0; i < mem_descr->num_elements; i++) {
3533 hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
3534 status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
3535 page_offset,
3536 (pm_arr->size / PAGE_SIZE));
3537 page_offset += pm_arr->size / PAGE_SIZE;
3538 if (status != 0) {
99bc5d55
JSJ		 3539 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3540 "BM_%d : post sgl failed.\n");
6733b39a
JK		 3541 return status;
3542 }
3543 pm_arr++;
3544 }
99bc5d55
JSJ		 3545 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3546 "BM_%d : POSTED PAGES\n");
6733b39a
JK		 3547 return 0;
3548}
3549
bfead3b2
JK		 3550static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
3551{
3552 struct be_dma_mem *mem = &q->dma_mem;
c8b25598 3553 if (mem->va) {
bfead3b2
JK		 3554 pci_free_consistent(phba->pcidev, mem->size,
3555 mem->va, mem->dma);
c8b25598
JK		 3556 mem->va = NULL;
3557 }
bfead3b2
JK		 3558}
3559
3560static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
3561 u16 len, u16 entry_size)
3562{
3563 struct be_dma_mem *mem = &q->dma_mem;
3564
3565 memset(q, 0, sizeof(*q));
3566 q->len = len;
3567 q->entry_size = entry_size;
3568 mem->size = len * entry_size;
7c845eb5 3569 mem->va = pci_zalloc_consistent(phba->pcidev, mem->size, &mem->dma);
bfead3b2 3570 if (!mem->va)
d3ad2bb3 3571 return -ENOMEM;
bfead3b2
JK		 3572 return 0;
3573}
3574
6733b39a
JK		 3575static int
3576beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
3577 struct hwi_context_memory *phwi_context,
3578 struct hwi_controller *phwi_ctrlr)
3579{
3580 unsigned int wrb_mem_index, offset, size, num_wrb_rings;
3581 u64 pa_addr_lo;
4eea99d5 3582 unsigned int idx, num, i, ulp_num;
6733b39a
JK		 3583 struct mem_array *pwrb_arr;
3584 void *wrb_vaddr;
3585 struct be_dma_mem sgl;
3586 struct be_mem_descriptor *mem_descr;
a7909b39 3587 struct hwi_wrb_context *pwrb_context;
6733b39a 3588 int status;
4eea99d5
JK		 3589 uint8_t ulp_count = 0, ulp_base_num = 0;
3590 uint16_t cid_count_ulp[BEISCSI_ULP_COUNT] = { 0 };
6733b39a
JK		 3591
3592 idx = 0;
3593 mem_descr = phba->init_mem;
3594 mem_descr += HWI_MEM_WRB;
3595 pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
3596 GFP_KERNEL);
3597 if (!pwrb_arr) {
99bc5d55
JSJ		 3598 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3599 "BM_%d : Memory alloc failed in create wrb ring.\n");
6733b39a
JK		 3600 return -ENOMEM;
3601 }
3602 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
3603 pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
3604 num_wrb_rings = mem_descr->mem_array[idx].size /
3605 (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
3606
3607 for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
3608 if (num_wrb_rings) {
3609 pwrb_arr[num].virtual_address = wrb_vaddr;
3610 pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
3611 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
3612 sizeof(struct iscsi_wrb);
3613 wrb_vaddr += pwrb_arr[num].size;
3614 pa_addr_lo += pwrb_arr[num].size;
3615 num_wrb_rings--;
3616 } else {
3617 idx++;
3618 wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
3619 pa_addr_lo = mem_descr->mem_array[idx].\
3620 bus_address.u.a64.address;
3621 num_wrb_rings = mem_descr->mem_array[idx].size /
3622 (phba->params.wrbs_per_cxn *
3623 sizeof(struct iscsi_wrb));
3624 pwrb_arr[num].virtual_address = wrb_vaddr;
3625 pwrb_arr[num].bus_address.u.a64.address\
3626 = pa_addr_lo;
3627 pwrb_arr[num].size = phba->params.wrbs_per_cxn *
3628 sizeof(struct iscsi_wrb);
3629 wrb_vaddr += pwrb_arr[num].size;
3630 pa_addr_lo += pwrb_arr[num].size;
3631 num_wrb_rings--;
3632 }
3633 }
4eea99d5
JK		 3634
3635 /* Get the ULP Count */
3636 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
3637 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3638 ulp_count++;
3639 ulp_base_num = ulp_num;
3640 cid_count_ulp[ulp_num] =
3641 BEISCSI_GET_CID_COUNT(phba, ulp_num);
3642 }
3643
6733b39a
JK		 3644 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3645 wrb_mem_index = 0;
3646 offset = 0;
3647 size = 0;
3648
4eea99d5
JK		 3649 if (ulp_count > 1) {
3650 ulp_base_num = (ulp_base_num + 1) % BEISCSI_ULP_COUNT;
3651
3652 if (!cid_count_ulp[ulp_base_num])
3653 ulp_base_num = (ulp_base_num + 1) %
3654 BEISCSI_ULP_COUNT;
3655
3656 cid_count_ulp[ulp_base_num]--;
3657 }
3658
3659
6733b39a
JK		 3660 hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
3661 status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
4eea99d5
JK		 3662 &phwi_context->be_wrbq[i],
3663 &phwi_ctrlr->wrb_context[i],
3664 ulp_base_num);
6733b39a 3665 if (status != 0) {
99bc5d55
JSJ		 3666 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3667 "BM_%d : wrbq create failed.");
1462b8ff 3668 kfree(pwrb_arr);
6733b39a
JK		 3669 return status;
3670 }
a7909b39 3671 pwrb_context = &phwi_ctrlr->wrb_context[i];
a7909b39 3672 BE_SET_CID_TO_CRI(i, pwrb_context->cid);
6733b39a
JK		 3673 }
3674 kfree(pwrb_arr);
3675 return 0;
3676}
3677
3678static void free_wrb_handles(struct beiscsi_hba *phba)
3679{
3680 unsigned int index;
3681 struct hwi_controller *phwi_ctrlr;
3682 struct hwi_wrb_context *pwrb_context;
3683
3684 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 3685 for (index = 0; index < phba->params.cxns_per_ctrl; index++) {
6733b39a
JK		 3686 pwrb_context = &phwi_ctrlr->wrb_context[index];
3687 kfree(pwrb_context->pwrb_handle_base);
3688 kfree(pwrb_context->pwrb_handle_basestd);
3689 }
3690}
3691
bfead3b2
JK		 3692static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
3693{
3694 struct be_queue_info *q;
3695 struct be_ctrl_info *ctrl = &phba->ctrl;
3696
3697 q = &phba->ctrl.mcc_obj.q;
4e2bdf7a 3698 if (q->created) {
bfead3b2 3699 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
4e2bdf7a
JSJ		 3700 be_queue_free(phba, q);
3701 }
bfead3b2
JK		 3702
3703 q = &phba->ctrl.mcc_obj.cq;
4e2bdf7a 3704 if (q->created) {
bfead3b2 3705 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
4e2bdf7a
JSJ		 3706 be_queue_free(phba, q);
3707 }
bfead3b2
JK		 3708}
3709
6733b39a
JK		 3710static void hwi_cleanup(struct beiscsi_hba *phba)
3711{
3712 struct be_queue_info *q;
3713 struct be_ctrl_info *ctrl = &phba->ctrl;
3714 struct hwi_controller *phwi_ctrlr;
3715 struct hwi_context_memory *phwi_context;
a7909b39 3716 struct hwi_async_pdu_context *pasync_ctx;
23188167 3717 int i, eq_for_mcc, ulp_num;
6733b39a
JK		 3718
3719 phwi_ctrlr = phba->phwi_ctrlr;
3720 phwi_context = phwi_ctrlr->phwi_ctxt;
15a90fe0
JK		 3721
3722 be_cmd_iscsi_remove_template_hdr(ctrl);
3723
6733b39a
JK		 3724 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
3725 q = &phwi_context->be_wrbq[i];
3726 if (q->created)
3727 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
3728 }
a7909b39 3729 kfree(phwi_context->be_wrbq);
6733b39a
JK		 3730 free_wrb_handles(phba);
3731
8a86e833
JK		 3732 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3733 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 3734
8a86e833
JK		 3735 q = &phwi_context->be_def_hdrq[ulp_num];
3736 if (q->created)
3737 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3738
3739 q = &phwi_context->be_def_dataq[ulp_num];
3740 if (q->created)
3741 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
3742
3743 pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx[ulp_num];
3744 }
3745 }
6733b39a
JK		 3746
3747 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
3748
bfead3b2
JK		 3749 for (i = 0; i < (phba->num_cpus); i++) {
3750 q = &phwi_context->be_cq[i];
4e2bdf7a
JSJ		 3751 if (q->created) {
3752 be_queue_free(phba, q);
bfead3b2 3753 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
4e2bdf7a 3754 }
bfead3b2 3755 }
23188167
JK		 3756
3757 be_mcc_queues_destroy(phba);
bfead3b2 3758 if (phba->msix_enabled)
23188167 3759 eq_for_mcc = 1;
bfead3b2 3760 else
23188167
JK		 3761 eq_for_mcc = 0;
3762 for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
bfead3b2 3763 q = &phwi_context->be_eq[i].q;
4e2bdf7a
JSJ		 3764 if (q->created) {
3765 be_queue_free(phba, q);
bfead3b2 3766 beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
4e2bdf7a 3767 }
bfead3b2 3768 }
0283fbb1 3769 be_cmd_fw_uninit(ctrl);
bfead3b2 3770}
6733b39a 3771
bfead3b2
JK		 3772static int be_mcc_queues_create(struct beiscsi_hba *phba,
3773 struct hwi_context_memory *phwi_context)
3774{
3775 struct be_queue_info *q, *cq;
3776 struct be_ctrl_info *ctrl = &phba->ctrl;
3777
3778 /* Alloc MCC compl queue */
3779 cq = &phba->ctrl.mcc_obj.cq;
3780 if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
3781 sizeof(struct be_mcc_compl)))
3782 goto err;
3783 /* Ask BE to create MCC compl queue; */
3784 if (phba->msix_enabled) {
3785 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
3786 [phba->num_cpus].q, false, true, 0))
3787 goto mcc_cq_free;
3788 } else {
3789 if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
3790 false, true, 0))
3791 goto mcc_cq_free;
3792 }
3793
3794 /* Alloc MCC queue */
3795 q = &phba->ctrl.mcc_obj.q;
3796 if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
3797 goto mcc_cq_destroy;
3798
3799 /* Ask BE to create MCC queue */
35e66019 3800 if (beiscsi_cmd_mccq_create(phba, q, cq))
bfead3b2
JK		 3801 goto mcc_q_free;
3802
3803 return 0;
3804
3805mcc_q_free:
3806 be_queue_free(phba, q);
3807mcc_cq_destroy:
3808 beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
3809mcc_cq_free:
3810 be_queue_free(phba, cq);
3811err:
d3ad2bb3 3812 return -ENOMEM;
bfead3b2
JK		 3813}
3814
107dfcba
JSJ		 3815/**
3816 * find_num_cpus()- Get the CPU online count
3817 * @phba: ptr to priv structure
3818 *
3819 * CPU count is used for creating EQ.
3820 **/
3821static void find_num_cpus(struct beiscsi_hba *phba)
bfead3b2
JK		 3822{
3823 int num_cpus = 0;
3824
3825 num_cpus = num_online_cpus();
bfead3b2 3826
22abeef0
JSJ		 3827 switch (phba->generation) {
3828 case BE_GEN2:
3829 case BE_GEN3:
3830 phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ?
3831 BEISCSI_MAX_NUM_CPUS : num_cpus;
3832 break;
3833 case BE_GEN4:
68c26a3a
JK		 3834 /*
3835 * If eqid_count == 1 fall back to
3836 * INTX mechanism
3837 **/
3838 if (phba->fw_config.eqid_count == 1) {
3839 enable_msix = 0;
3840 phba->num_cpus = 1;
3841 return;
3842 }
3843
3844 phba->num_cpus =
3845 (num_cpus > (phba->fw_config.eqid_count - 1)) ?
3846 (phba->fw_config.eqid_count - 1) : num_cpus;
22abeef0
JSJ		 3847 break;
3848 default:
3849 phba->num_cpus = 1;
3850 }
6733b39a
JK		 3851}
3852
3853static int hwi_init_port(struct beiscsi_hba *phba)
3854{
3855 struct hwi_controller *phwi_ctrlr;
3856 struct hwi_context_memory *phwi_context;
3857 unsigned int def_pdu_ring_sz;
3858 struct be_ctrl_info *ctrl = &phba->ctrl;
8a86e833 3859 int status, ulp_num;
6733b39a 3860
6733b39a 3861 phwi_ctrlr = phba->phwi_ctrlr;
6733b39a 3862 phwi_context = phwi_ctrlr->phwi_ctxt;
73af08e1 3863 phwi_context->max_eqd = 128;
bfead3b2 3864 phwi_context->min_eqd = 0;
73af08e1 3865 phwi_context->cur_eqd = 0;
6733b39a 3866 be_cmd_fw_initialize(&phba->ctrl);
bfead3b2
JK		 3867
3868 status = beiscsi_create_eqs(phba, phwi_context);
6733b39a 3869 if (status != 0) {
99bc5d55
JSJ		 3870 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3871 "BM_%d : EQ not created\n");
6733b39a
JK		 3872 goto error;
3873 }
3874
bfead3b2
JK		 3875 status = be_mcc_queues_create(phba, phwi_context);
3876 if (status != 0)
3877 goto error;
3878
3879 status = mgmt_check_supported_fw(ctrl, phba);
6733b39a 3880 if (status != 0) {
99bc5d55
JSJ		 3881 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3882 "BM_%d : Unsupported fw version\n");
6733b39a
JK		 3883 goto error;
3884 }
3885
bfead3b2 3886 status = beiscsi_create_cqs(phba, phwi_context);
6733b39a 3887 if (status != 0) {
99bc5d55
JSJ		 3888 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3889 "BM_%d : CQ not created\n");
6733b39a
JK		 3890 goto error;
3891 }
3892
8a86e833
JK		 3893 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3894 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
6733b39a 3895
8a86e833
JK		 3896 def_pdu_ring_sz =
3897 BEISCSI_GET_CID_COUNT(phba, ulp_num) *
3898 sizeof(struct phys_addr);
3899
3900 status = beiscsi_create_def_hdr(phba, phwi_context,
3901 phwi_ctrlr,
3902 def_pdu_ring_sz,
3903 ulp_num);
3904 if (status != 0) {
3905 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3906 "BM_%d : Default Header not created for ULP : %d\n",
3907 ulp_num);
3908 goto error;
3909 }
3910
3911 status = beiscsi_create_def_data(phba, phwi_context,
3912 phwi_ctrlr,
3913 def_pdu_ring_sz,
3914 ulp_num);
3915 if (status != 0) {
3916 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3917 "BM_%d : Default Data not created for ULP : %d\n",
3918 ulp_num);
3919 goto error;
3920 }
3921 }
6733b39a
JK		 3922 }
3923
3924 status = beiscsi_post_pages(phba);
3925 if (status != 0) {
99bc5d55
JSJ		 3926 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3927 "BM_%d : Post SGL Pages Failed\n");
6733b39a
JK		 3928 goto error;
3929 }
3930
15a90fe0
JK		 3931 status = beiscsi_post_template_hdr(phba);
3932 if (status != 0) {
3933 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3934 "BM_%d : Template HDR Posting for CXN Failed\n");
3935 }
3936
6733b39a
JK		 3937 status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
3938 if (status != 0) {
99bc5d55
JSJ		 3939 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3940 "BM_%d : WRB Rings not created\n");
6733b39a
JK		 3941 goto error;
3942 }
3943
8a86e833
JK		 3944 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
3945 uint16_t async_arr_idx = 0;
3946
3947 if (test_bit(ulp_num, &phba->fw_config.ulp_supported)) {
3948 uint16_t cri = 0;
3949 struct hwi_async_pdu_context *pasync_ctx;
3950
3951 pasync_ctx = HWI_GET_ASYNC_PDU_CTX(
3952 phwi_ctrlr, ulp_num);
3953 for (cri = 0; cri <
3954 phba->params.cxns_per_ctrl; cri++) {
3955 if (ulp_num == BEISCSI_GET_ULP_FROM_CRI
3956 (phwi_ctrlr, cri))
3957 pasync_ctx->cid_to_async_cri_map[
3958 phwi_ctrlr->wrb_context[cri].cid] =
3959 async_arr_idx++;
3960 }
3961 }
3962 }
3963
99bc5d55
JSJ		 3964 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3965 "BM_%d : hwi_init_port success\n");
6733b39a
JK		 3966 return 0;
3967
3968error:
99bc5d55
JSJ		 3969 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3970 "BM_%d : hwi_init_port failed");
6733b39a 3971 hwi_cleanup(phba);
a49e06d5 3972 return status;
6733b39a
JK		 3973}
3974
6733b39a
JK		 3975static int hwi_init_controller(struct beiscsi_hba *phba)
3976{
3977 struct hwi_controller *phwi_ctrlr;
3978
3979 phwi_ctrlr = phba->phwi_ctrlr;
3980 if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
3981 phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
3982 init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
99bc5d55
JSJ		 3983 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
3984 "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
3985 phwi_ctrlr->phwi_ctxt);
6733b39a 3986 } else {
99bc5d55
JSJ		 3987 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3988 "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
3989 "than one element.Failing to load\n");
6733b39a
JK		 3990 return -ENOMEM;
3991 }
3992
3993 iscsi_init_global_templates(phba);
3ec78271
JK		 3994 if (beiscsi_init_wrb_handle(phba))
3995 return -ENOMEM;
3996
a7909b39
JK		 3997 if (hwi_init_async_pdu_ctx(phba)) {
3998 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
3999 "BM_%d : hwi_init_async_pdu_ctx failed\n");
4000 return -ENOMEM;
4001 }
4002
6733b39a 4003 if (hwi_init_port(phba) != 0) {
99bc5d55
JSJ		 4004 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4005 "BM_%d : hwi_init_controller failed\n");
4006
6733b39a
JK		 4007 return -ENOMEM;
4008 }
4009 return 0;
4010}
4011
4012static void beiscsi_free_mem(struct beiscsi_hba *phba)
4013{
4014 struct be_mem_descriptor *mem_descr;
4015 int i, j;
4016
4017 mem_descr = phba->init_mem;
4018 i = 0;
4019 j = 0;
4020 for (i = 0; i < SE_MEM_MAX; i++) {
4021 for (j = mem_descr->num_elements; j > 0; j--) {
4022 pci_free_consistent(phba->pcidev,
4023 mem_descr->mem_array[j - 1].size,
4024 mem_descr->mem_array[j - 1].virtual_address,
457ff3b7
JK		 4025 (unsigned long)mem_descr->mem_array[j - 1].
4026 bus_address.u.a64.address);
6733b39a 4027 }
8a86e833 4028
6733b39a
JK		 4029 kfree(mem_descr->mem_array);
4030 mem_descr++;
4031 }
4032 kfree(phba->init_mem);
a7909b39 4033 kfree(phba->phwi_ctrlr->wrb_context);
6733b39a
JK		 4034 kfree(phba->phwi_ctrlr);
4035}
4036
4037static int beiscsi_init_controller(struct beiscsi_hba *phba)
4038{
4039 int ret = -ENOMEM;
4040
4041 ret = beiscsi_get_memory(phba);
4042 if (ret < 0) {
99bc5d55
JSJ		 4043 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4044 "BM_%d : beiscsi_dev_probe -"
4045 "Failed in beiscsi_alloc_memory\n");
6733b39a
JK		 4046 return ret;
4047 }
4048
4049 ret = hwi_init_controller(phba);
4050 if (ret)
4051 goto free_init;
99bc5d55
JSJ		 4052 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4053 "BM_%d : Return success from beiscsi_init_controller");
4054
6733b39a
JK		 4055 return 0;
4056
4057free_init:
4058 beiscsi_free_mem(phba);
a49e06d5 4059 return ret;
6733b39a
JK		 4060}
4061
4062static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
4063{
4064 struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
4065 struct sgl_handle *psgl_handle;
4066 struct iscsi_sge *pfrag;
90622db3
JK		 4067 unsigned int arr_index, i, idx;
4068 unsigned int ulp_icd_start, ulp_num = 0;
6733b39a
JK		 4069
4070 phba->io_sgl_hndl_avbl = 0;
4071 phba->eh_sgl_hndl_avbl = 0;
bfead3b2 4072
6733b39a
JK		 4073 mem_descr_sglh = phba->init_mem;
4074 mem_descr_sglh += HWI_MEM_SGLH;
4075 if (1 == mem_descr_sglh->num_elements) {
4076 phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
4077 phba->params.ios_per_ctrl,
4078 GFP_KERNEL);
4079 if (!phba->io_sgl_hndl_base) {
99bc5d55
JSJ		 4080 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4081 "BM_%d : Mem Alloc Failed. Failing to load\n");
6733b39a
JK		 4082 return -ENOMEM;
4083 }
4084 phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
4085 (phba->params.icds_per_ctrl -
4086 phba->params.ios_per_ctrl),
4087 GFP_KERNEL);
4088 if (!phba->eh_sgl_hndl_base) {
4089 kfree(phba->io_sgl_hndl_base);
99bc5d55
JSJ		 4090 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4091 "BM_%d : Mem Alloc Failed. Failing to load\n");
6733b39a
JK		 4092 return -ENOMEM;
4093 }
4094 } else {
99bc5d55
JSJ		 4095 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4096 "BM_%d : HWI_MEM_SGLH is more than one element."
4097 "Failing to load\n");
6733b39a
JK		 4098 return -ENOMEM;
4099 }
4100
4101 arr_index = 0;
4102 idx = 0;
4103 while (idx < mem_descr_sglh->num_elements) {
4104 psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
4105
4106 for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
4107 sizeof(struct sgl_handle)); i++) {
4108 if (arr_index < phba->params.ios_per_ctrl) {
4109 phba->io_sgl_hndl_base[arr_index] = psgl_handle;
4110 phba->io_sgl_hndl_avbl++;
4111 arr_index++;
4112 } else {
4113 phba->eh_sgl_hndl_base[arr_index -
4114 phba->params.ios_per_ctrl] =
4115 psgl_handle;
4116 arr_index++;
4117 phba->eh_sgl_hndl_avbl++;
4118 }
4119 psgl_handle++;
4120 }
4121 idx++;
4122 }
99bc5d55
JSJ		 4123 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4124 "BM_%d : phba->io_sgl_hndl_avbl=%d"
4125 "phba->eh_sgl_hndl_avbl=%d\n",
4126 phba->io_sgl_hndl_avbl,
4127 phba->eh_sgl_hndl_avbl);
4128
6733b39a
JK		 4129 mem_descr_sg = phba->init_mem;
4130 mem_descr_sg += HWI_MEM_SGE;
99bc5d55
JSJ		 4131 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4132 "\n BM_%d : mem_descr_sg->num_elements=%d\n",
4133 mem_descr_sg->num_elements);
4134
90622db3
JK		 4135 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++)
4136 if (test_bit(ulp_num, &phba->fw_config.ulp_supported))
4137 break;
4138
4139 ulp_icd_start = phba->fw_config.iscsi_icd_start[ulp_num];
4140
6733b39a
JK		 4141 arr_index = 0;
4142 idx = 0;
4143 while (idx < mem_descr_sg->num_elements) {
4144 pfrag = mem_descr_sg->mem_array[idx].virtual_address;
4145
4146 for (i = 0;
4147 i < (mem_descr_sg->mem_array[idx].size) /
4148 (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
4149 i++) {
4150 if (arr_index < phba->params.ios_per_ctrl)
4151 psgl_handle = phba->io_sgl_hndl_base[arr_index];
4152 else
4153 psgl_handle = phba->eh_sgl_hndl_base[arr_index -
4154 phba->params.ios_per_ctrl];
4155 psgl_handle->pfrag = pfrag;
4156 AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
4157 AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
4158 pfrag += phba->params.num_sge_per_io;
90622db3 4159 psgl_handle->sgl_index = ulp_icd_start + arr_index++;
6733b39a
JK		 4160 }
4161 idx++;
4162 }
4163 phba->io_sgl_free_index = 0;
4164 phba->io_sgl_alloc_index = 0;
4165 phba->eh_sgl_free_index = 0;
4166 phba->eh_sgl_alloc_index = 0;
4167 return 0;
4168}
4169
4170static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
4171{
0a3db7c0
JK		 4172 int ret;
4173 uint16_t i, ulp_num;
4174 struct ulp_cid_info *ptr_cid_info = NULL;
6733b39a 4175
0a3db7c0
JK		 4176 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4177 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4178 ptr_cid_info = kzalloc(sizeof(struct ulp_cid_info),
4179 GFP_KERNEL);
4180
4181 if (!ptr_cid_info) {
4182 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4183 "BM_%d : Failed to allocate memory"
4184 "for ULP_CID_INFO for ULP : %d\n",
4185 ulp_num);
4186 ret = -ENOMEM;
4187 goto free_memory;
4188
4189 }
4190
4191 /* Allocate memory for CID array */
4192 ptr_cid_info->cid_array = kzalloc(sizeof(void *) *
4193 BEISCSI_GET_CID_COUNT(phba,
4194 ulp_num), GFP_KERNEL);
4195 if (!ptr_cid_info->cid_array) {
4196 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4197 "BM_%d : Failed to allocate memory"
4198 "for CID_ARRAY for ULP : %d\n",
4199 ulp_num);
4200 kfree(ptr_cid_info);
4201 ptr_cid_info = NULL;
4202 ret = -ENOMEM;
4203
4204 goto free_memory;
4205 }
4206 ptr_cid_info->avlbl_cids = BEISCSI_GET_CID_COUNT(
4207 phba, ulp_num);
4208
4209 /* Save the cid_info_array ptr */
4210 phba->cid_array_info[ulp_num] = ptr_cid_info;
4211 }
6733b39a 4212 }
c2462288 4213 phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
a7909b39 4214 phba->params.cxns_per_ctrl, GFP_KERNEL);
6733b39a 4215 if (!phba->ep_array) {
99bc5d55
JSJ		 4216 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4217 "BM_%d : Failed to allocate memory in "
4218 "hba_setup_cid_tbls\n");
0a3db7c0
JK		 4219 ret = -ENOMEM;
4220
4221 goto free_memory;
6733b39a 4222 }
a7909b39
JK		 4223
4224 phba->conn_table = kzalloc(sizeof(struct beiscsi_conn *) *
4225 phba->params.cxns_per_ctrl, GFP_KERNEL);
4226 if (!phba->conn_table) {
4227 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4228 "BM_%d : Failed to allocate memory in"
4229 "hba_setup_cid_tbls\n");
4230
a7909b39 4231 kfree(phba->ep_array);
a7909b39 4232 phba->ep_array = NULL;
0a3db7c0 4233 ret = -ENOMEM;
5f2d25ef
TH		 4234
4235 goto free_memory;
6733b39a 4236 }
a7909b39 4237
0a3db7c0
JK		 4238 for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
4239 ulp_num = phba->phwi_ctrlr->wrb_context[i].ulp_num;
4240
4241 ptr_cid_info = phba->cid_array_info[ulp_num];
4242 ptr_cid_info->cid_array[ptr_cid_info->cid_alloc++] =
4243 phba->phwi_ctrlr->wrb_context[i].cid;
4244
4245 }
4246
4247 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4248 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4249 ptr_cid_info = phba->cid_array_info[ulp_num];
a7909b39 4250
0a3db7c0
JK		 4251 ptr_cid_info->cid_alloc = 0;
4252 ptr_cid_info->cid_free = 0;
4253 }
4254 }
6733b39a 4255 return 0;
0a3db7c0
JK		 4256
4257free_memory:
4258 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4259 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4260 ptr_cid_info = phba->cid_array_info[ulp_num];
4261
4262 if (ptr_cid_info) {
4263 kfree(ptr_cid_info->cid_array);
4264 kfree(ptr_cid_info);
4265 phba->cid_array_info[ulp_num] = NULL;
4266 }
4267 }
4268 }
4269
4270 return ret;
6733b39a
JK		 4271}
4272
238f6b72 4273static void hwi_enable_intr(struct beiscsi_hba *phba)
6733b39a
JK		 4274{
4275 struct be_ctrl_info *ctrl = &phba->ctrl;
4276 struct hwi_controller *phwi_ctrlr;
4277 struct hwi_context_memory *phwi_context;
4278 struct be_queue_info *eq;
4279 u8 __iomem *addr;
bfead3b2 4280 u32 reg, i;
6733b39a
JK		 4281 u32 enabled;
4282
4283 phwi_ctrlr = phba->phwi_ctrlr;
4284 phwi_context = phwi_ctrlr->phwi_ctxt;
4285
6733b39a
JK		 4286 addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
4287 PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
4288 reg = ioread32(addr);
6733b39a
JK		 4289
4290 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4291 if (!enabled) {
4292 reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
99bc5d55
JSJ		 4293 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4294 "BM_%d : reg =x%08x addr=%p\n", reg, addr);
6733b39a 4295 iowrite32(reg, addr);
665d6d94
JK		 4296 }
4297
4298 if (!phba->msix_enabled) {
4299 eq = &phwi_context->be_eq[0].q;
99bc5d55
JSJ		 4300 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4301 "BM_%d : eq->id=%d\n", eq->id);
4302
665d6d94
JK		 4303 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
4304 } else {
4305 for (i = 0; i <= phba->num_cpus; i++) {
4306 eq = &phwi_context->be_eq[i].q;
99bc5d55
JSJ		 4307 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
4308 "BM_%d : eq->id=%d\n", eq->id);
bfead3b2
JK		 4309 hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
4310 }
c03af1ae 4311 }
6733b39a
JK		 4312}
4313
4314static void hwi_disable_intr(struct beiscsi_hba *phba)
4315{
4316 struct be_ctrl_info *ctrl = &phba->ctrl;
4317
4318 u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
4319 u32 reg = ioread32(addr);
4320
4321 u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4322 if (enabled) {
4323 reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
4324 iowrite32(reg, addr);
4325 } else
99bc5d55
JSJ		 4326 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
4327 "BM_%d : In hwi_disable_intr, Already Disabled\n");
6733b39a
JK		 4328}
4329
9aef4200
JSJ		 4330/**
4331 * beiscsi_get_boot_info()- Get the boot session info
4332 * @phba: The device priv structure instance
4333 *
4334 * Get the boot target info and store in driver priv structure
4335 *
4336 * return values
4337 * Success: 0
4338 * Failure: Non-Zero Value
4339 **/
c7acc5b8
JK		 4340static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
4341{
0e43895e 4342 struct be_cmd_get_session_resp *session_resp;
c7acc5b8 4343 struct be_dma_mem nonemb_cmd;
e175defe 4344 unsigned int tag;
9aef4200 4345 unsigned int s_handle;
f457a46f 4346 int ret = -ENOMEM;
c7acc5b8 4347
9aef4200
JSJ		 4348 /* Get the session handle of the boot target */
4349 ret = be_mgmt_get_boot_shandle(phba, &s_handle);
4350 if (ret) {
99bc5d55
JSJ		 4351 beiscsi_log(phba, KERN_ERR,
4352 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
4353 "BM_%d : No boot session\n");
3efde862
JSJ		 4354
4355 if (ret == -ENXIO)
4356 phba->get_boot = 0;
4357
4358
9aef4200 4359 return ret;
c7acc5b8 4360 }
3efde862 4361 phba->get_boot = 0;
7c845eb5
JP		 4362 nonemb_cmd.va = pci_zalloc_consistent(phba->ctrl.pdev,
4363 sizeof(*session_resp),
4364 &nonemb_cmd.dma);
c7acc5b8 4365 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 4366 beiscsi_log(phba, KERN_ERR,
4367 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
4368 "BM_%d : Failed to allocate memory for"
4369 "beiscsi_get_session_info\n");
4370
c7acc5b8
JK		 4371 return -ENOMEM;
4372 }
4373
9aef4200 4374 tag = mgmt_get_session_info(phba, s_handle,
0e43895e 4375 &nonemb_cmd);
c7acc5b8 4376 if (!tag) {
99bc5d55
JSJ		 4377 beiscsi_log(phba, KERN_ERR,
4378 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
4379 "BM_%d : beiscsi_get_session_info"
4380 " Failed\n");
4381
c7acc5b8 4382 goto boot_freemem;
e175defe 4383 }
c7acc5b8 4384
1957aa7f 4385 ret = beiscsi_mccq_compl(phba, tag, NULL, &nonemb_cmd);
e175defe 4386 if (ret) {
99bc5d55
JSJ		 4387 beiscsi_log(phba, KERN_ERR,
4388 BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
e175defe 4389 "BM_%d : beiscsi_get_session_info Failed");
1957aa7f
JK		 4390
4391 if (ret != -EBUSY)
4392 goto boot_freemem;
4393 else
4394 return ret;
c7acc5b8 4395 }
e175defe 4396
c7acc5b8 4397 session_resp = nonemb_cmd.va ;
f457a46f 4398
c7acc5b8
JK		 4399 memcpy(&phba->boot_sess, &session_resp->session_info,
4400 sizeof(struct mgmt_session_info));
f457a46f
MC		 4401 ret = 0;
4402
c7acc5b8
JK		 4403boot_freemem:
4404 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
4405 nonemb_cmd.va, nonemb_cmd.dma);
f457a46f
MC		 4406 return ret;
4407}
4408
4409static void beiscsi_boot_release(void *data)
4410{
4411 struct beiscsi_hba *phba = data;
4412
4413 scsi_host_put(phba->shost);
4414}
4415
4416static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
4417{
4418 struct iscsi_boot_kobj *boot_kobj;
4419
a3d313ea
JK		 4420 /* it has been created previously */
4421 if (phba->boot_kset)
4422 return 0;
4423
f457a46f
MC		 4424 /* get boot info using mgmt cmd */
4425 if (beiscsi_get_boot_info(phba))
4426 /* Try to see if we can carry on without this */
4427 return 0;
4428
4429 phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
4430 if (!phba->boot_kset)
4431 return -ENOMEM;
4432
4433 /* get a ref because the show function will ref the phba */
4434 if (!scsi_host_get(phba->shost))
4435 goto free_kset;
4436 boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
4437 beiscsi_show_boot_tgt_info,
4438 beiscsi_tgt_get_attr_visibility,
4439 beiscsi_boot_release);
4440 if (!boot_kobj)
4441 goto put_shost;
4442
4443 if (!scsi_host_get(phba->shost))
4444 goto free_kset;
4445 boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
4446 beiscsi_show_boot_ini_info,
4447 beiscsi_ini_get_attr_visibility,
4448 beiscsi_boot_release);
4449 if (!boot_kobj)
4450 goto put_shost;
4451
4452 if (!scsi_host_get(phba->shost))
4453 goto free_kset;
4454 boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
4455 beiscsi_show_boot_eth_info,
4456 beiscsi_eth_get_attr_visibility,
4457 beiscsi_boot_release);
4458 if (!boot_kobj)
4459 goto put_shost;
4460 return 0;
4461
4462put_shost:
4463 scsi_host_put(phba->shost);
4464free_kset:
4465 iscsi_boot_destroy_kset(phba->boot_kset);
c7acc5b8
JK		 4466 return -ENOMEM;
4467}
4468
6733b39a
JK		 4469static int beiscsi_init_port(struct beiscsi_hba *phba)
4470{
4471 int ret;
4472
4473 ret = beiscsi_init_controller(phba);
4474 if (ret < 0) {
99bc5d55
JSJ		 4475 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4476 "BM_%d : beiscsi_dev_probe - Failed in"
4477 "beiscsi_init_controller\n");
6733b39a
JK		 4478 return ret;
4479 }
4480 ret = beiscsi_init_sgl_handle(phba);
4481 if (ret < 0) {
99bc5d55
JSJ		 4482 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4483 "BM_%d : beiscsi_dev_probe - Failed in"
4484 "beiscsi_init_sgl_handle\n");
6733b39a
JK		 4485 goto do_cleanup_ctrlr;
4486 }
4487
4488 if (hba_setup_cid_tbls(phba)) {
99bc5d55
JSJ		 4489 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
4490 "BM_%d : Failed in hba_setup_cid_tbls\n");
6733b39a
JK		 4491 kfree(phba->io_sgl_hndl_base);
4492 kfree(phba->eh_sgl_hndl_base);
4493 goto do_cleanup_ctrlr;
4494 }
4495
4496 return ret;
4497
4498do_cleanup_ctrlr:
4499 hwi_cleanup(phba);
4500 return ret;
4501}
4502
4503static void hwi_purge_eq(struct beiscsi_hba *phba)
4504{
4505 struct hwi_controller *phwi_ctrlr;
4506 struct hwi_context_memory *phwi_context;
4507 struct be_queue_info *eq;
4508 struct be_eq_entry *eqe = NULL;
bfead3b2 4509 int i, eq_msix;
756d29c8 4510 unsigned int num_processed;
6733b39a
JK		 4511
4512 phwi_ctrlr = phba->phwi_ctrlr;
4513 phwi_context = phwi_ctrlr->phwi_ctxt;
bfead3b2
JK		 4514 if (phba->msix_enabled)
4515 eq_msix = 1;
4516 else
4517 eq_msix = 0;
6733b39a 4518
bfead3b2
JK		 4519 for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
4520 eq = &phwi_context->be_eq[i].q;
6733b39a 4521 eqe = queue_tail_node(eq);
756d29c8 4522 num_processed = 0;
bfead3b2
JK		 4523 while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
4524 & EQE_VALID_MASK) {
4525 AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
4526 queue_tail_inc(eq);
4527 eqe = queue_tail_node(eq);
756d29c8 4528 num_processed++;
bfead3b2 4529 }
756d29c8
JK		 4530
4531 if (num_processed)
4532 hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
6733b39a
JK		 4533 }
4534}
4535
4536static void beiscsi_clean_port(struct beiscsi_hba *phba)
4537{
0a3db7c0
JK		 4538 int mgmt_status, ulp_num;
4539 struct ulp_cid_info *ptr_cid_info = NULL;
6733b39a 4540
bd41c2bd
JK		 4541 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4542 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4543 mgmt_status = mgmt_epfw_cleanup(phba, ulp_num);
4544 if (mgmt_status)
4545 beiscsi_log(phba, KERN_WARNING,
4546 BEISCSI_LOG_INIT,
4547 "BM_%d : mgmt_epfw_cleanup FAILED"
4548 " for ULP_%d\n", ulp_num);
4549 }
4550 }
756d29c8 4551
6733b39a 4552 hwi_purge_eq(phba);
756d29c8 4553 hwi_cleanup(phba);
6733b39a
JK		 4554 kfree(phba->io_sgl_hndl_base);
4555 kfree(phba->eh_sgl_hndl_base);
6733b39a 4556 kfree(phba->ep_array);
a7909b39 4557 kfree(phba->conn_table);
0a3db7c0
JK		 4558
4559 for (ulp_num = 0; ulp_num < BEISCSI_ULP_COUNT; ulp_num++) {
4560 if (test_bit(ulp_num, (void *)&phba->fw_config.ulp_supported)) {
4561 ptr_cid_info = phba->cid_array_info[ulp_num];
4562
4563 if (ptr_cid_info) {
4564 kfree(ptr_cid_info->cid_array);
4565 kfree(ptr_cid_info);
4566 phba->cid_array_info[ulp_num] = NULL;
4567 }
4568 }
4569 }
4570
6733b39a
JK		 4571}
4572
43f388b0
JK		 4573/**
4574 * beiscsi_free_mgmt_task_handles()- Free driver CXN resources
4575 * @beiscsi_conn: ptr to the conn to be cleaned up
4a4a11b9 4576 * @task: ptr to iscsi_task resource to be freed.
43f388b0
JK		 4577 *
4578 * Free driver mgmt resources binded to CXN.
4579 **/
4580void
4a4a11b9
JK		 4581beiscsi_free_mgmt_task_handles(struct beiscsi_conn *beiscsi_conn,
4582 struct iscsi_task *task)
43f388b0
JK		 4583{
4584 struct beiscsi_io_task *io_task;
4585 struct beiscsi_hba *phba = beiscsi_conn->phba;
4586 struct hwi_wrb_context *pwrb_context;
4587 struct hwi_controller *phwi_ctrlr;
a7909b39
JK		 4588 uint16_t cri_index = BE_GET_CRI_FROM_CID(
4589 beiscsi_conn->beiscsi_conn_cid);
43f388b0
JK		 4590
4591 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39
JK		 4592 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
4593
4a4a11b9 4594 io_task = task->dd_data;
43f388b0
JK		 4595
4596 if (io_task->pwrb_handle) {
4597 memset(io_task->pwrb_handle->pwrb, 0,
4598 sizeof(struct iscsi_wrb));
4599 free_wrb_handle(phba, pwrb_context,
4600 io_task->pwrb_handle);
4601 io_task->pwrb_handle = NULL;
4602 }
4603
4604 if (io_task->psgl_handle) {
4605 spin_lock_bh(&phba->mgmt_sgl_lock);
4606 free_mgmt_sgl_handle(phba,
4607 io_task->psgl_handle);
43f388b0 4608 io_task->psgl_handle = NULL;
4a4a11b9 4609 spin_unlock_bh(&phba->mgmt_sgl_lock);
43f388b0
JK		 4610 }
4611
4612 if (io_task->mtask_addr)
4613 pci_unmap_single(phba->pcidev,
4614 io_task->mtask_addr,
4615 io_task->mtask_data_count,
4616 PCI_DMA_TODEVICE);
4617}
4618
d629c471
JSJ		 4619/**
4620 * beiscsi_cleanup_task()- Free driver resources of the task
4621 * @task: ptr to the iscsi task
4622 *
4623 **/
1282ab76
MC		 4624static void beiscsi_cleanup_task(struct iscsi_task *task)
4625{
4626 struct beiscsi_io_task *io_task = task->dd_data;
4627 struct iscsi_conn *conn = task->conn;
4628 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4629 struct beiscsi_hba *phba = beiscsi_conn->phba;
4630 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
4631 struct hwi_wrb_context *pwrb_context;
4632 struct hwi_controller *phwi_ctrlr;
a7909b39
JK		 4633 uint16_t cri_index = BE_GET_CRI_FROM_CID(
4634 beiscsi_conn->beiscsi_conn_cid);
1282ab76
MC		 4635
4636 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39 4637 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
1282ab76
MC		 4638
4639 if (io_task->cmd_bhs) {
4640 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
4641 io_task->bhs_pa.u.a64.address);
4642 io_task->cmd_bhs = NULL;
4643 }
4644
4645 if (task->sc) {
4646 if (io_task->pwrb_handle) {
4647 free_wrb_handle(phba, pwrb_context,
4648 io_task->pwrb_handle);
4649 io_task->pwrb_handle = NULL;
4650 }
4651
4652 if (io_task->psgl_handle) {
4653 spin_lock(&phba->io_sgl_lock);
4654 free_io_sgl_handle(phba, io_task->psgl_handle);
4655 spin_unlock(&phba->io_sgl_lock);
4656 io_task->psgl_handle = NULL;
4657 }
da334977
JK		 4658
4659 if (io_task->scsi_cmnd) {
4660 scsi_dma_unmap(io_task->scsi_cmnd);
4661 io_task->scsi_cmnd = NULL;
4662 }
1282ab76 4663 } else {
43f388b0 4664 if (!beiscsi_conn->login_in_progress)
4a4a11b9 4665 beiscsi_free_mgmt_task_handles(beiscsi_conn, task);
1282ab76
MC		 4666 }
4667}
4668
6733b39a
JK		 4669void
4670beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
4671 struct beiscsi_offload_params *params)
4672{
4673 struct wrb_handle *pwrb_handle;
6733b39a 4674 struct beiscsi_hba *phba = beiscsi_conn->phba;
1282ab76
MC		 4675 struct iscsi_task *task = beiscsi_conn->task;
4676 struct iscsi_session *session = task->conn->session;
6733b39a
JK		 4677 u32 doorbell = 0;
4678
4679 /*
4680 * We can always use 0 here because it is reserved by libiscsi for
4681 * login/startup related tasks.
4682 */
1282ab76 4683 beiscsi_conn->login_in_progress = 0;
659743b0 4684 spin_lock_bh(&session->back_lock);
1282ab76 4685 beiscsi_cleanup_task(task);
659743b0 4686 spin_unlock_bh(&session->back_lock);
1282ab76 4687
a7909b39 4688 pwrb_handle = alloc_wrb_handle(phba, beiscsi_conn->beiscsi_conn_cid);
6733b39a 4689
acb9693c 4690 /* Check for the adapter family */
2c9dfd36 4691 if (is_chip_be2_be3r(phba))
acb9693c
JSJ		 4692 beiscsi_offload_cxn_v0(params, pwrb_handle,
4693 phba->init_mem);
2c9dfd36
JK		 4694 else
4695 beiscsi_offload_cxn_v2(params, pwrb_handle);
6733b39a 4696
acb9693c
JSJ		 4697 be_dws_le_to_cpu(pwrb_handle->pwrb,
4698 sizeof(struct iscsi_target_context_update_wrb));
6733b39a
JK		 4699
4700 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 4701 doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
bfead3b2 4702 << DB_DEF_PDU_WRB_INDEX_SHIFT;
6733b39a 4703 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 4704 iowrite32(doorbell, phba->db_va +
4705 beiscsi_conn->doorbell_offset);
6733b39a
JK		 4706}
4707
4708static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
4709 int *index, int *age)
4710{
bfead3b2 4711 *index = (int)itt;
6733b39a
JK		 4712 if (age)
4713 *age = conn->session->age;
4714}
4715
4716/**
4717 * beiscsi_alloc_pdu - allocates pdu and related resources
4718 * @task: libiscsi task
4719 * @opcode: opcode of pdu for task
4720 *
4721 * This is called with the session lock held. It will allocate
4722 * the wrb and sgl if needed for the command. And it will prep
4723 * the pdu's itt. beiscsi_parse_pdu will later translate
4724 * the pdu itt to the libiscsi task itt.
4725 */
4726static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
4727{
4728 struct beiscsi_io_task *io_task = task->dd_data;
4729 struct iscsi_conn *conn = task->conn;
4730 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4731 struct beiscsi_hba *phba = beiscsi_conn->phba;
4732 struct hwi_wrb_context *pwrb_context;
4733 struct hwi_controller *phwi_ctrlr;
4734 itt_t itt;
a7909b39 4735 uint16_t cri_index = 0;
2afc95bf
JK		 4736 struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
4737 dma_addr_t paddr;
6733b39a 4738
2afc95bf 4739 io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
bc7accec 4740 GFP_ATOMIC, &paddr);
2afc95bf
JK		 4741 if (!io_task->cmd_bhs)
4742 return -ENOMEM;
2afc95bf 4743 io_task->bhs_pa.u.a64.address = paddr;
bfead3b2 4744 io_task->libiscsi_itt = (itt_t)task->itt;
6733b39a
JK		 4745 io_task->conn = beiscsi_conn;
4746
4747 task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
4748 task->hdr_max = sizeof(struct be_cmd_bhs);
d2cecf0d 4749 io_task->psgl_handle = NULL;
3ec78271 4750 io_task->pwrb_handle = NULL;
6733b39a
JK		 4751
4752 if (task->sc) {
4753 spin_lock(&phba->io_sgl_lock);
4754 io_task->psgl_handle = alloc_io_sgl_handle(phba);
4755 spin_unlock(&phba->io_sgl_lock);
8359c79b
JSJ		 4756 if (!io_task->psgl_handle) {
4757 beiscsi_log(phba, KERN_ERR,
4758 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4759 "BM_%d : Alloc of IO_SGL_ICD Failed"
4760 "for the CID : %d\n",
4761 beiscsi_conn->beiscsi_conn_cid);
2afc95bf 4762 goto free_hndls;
8359c79b 4763 }
d2cecf0d 4764 io_task->pwrb_handle = alloc_wrb_handle(phba,
a7909b39 4765 beiscsi_conn->beiscsi_conn_cid);
8359c79b
JSJ		 4766 if (!io_task->pwrb_handle) {
4767 beiscsi_log(phba, KERN_ERR,
4768 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4769 "BM_%d : Alloc of WRB_HANDLE Failed"
4770 "for the CID : %d\n",
4771 beiscsi_conn->beiscsi_conn_cid);
d2cecf0d 4772 goto free_io_hndls;
8359c79b 4773 }
6733b39a
JK		 4774 } else {
4775 io_task->scsi_cmnd = NULL;
d7aea67b 4776 if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
43f388b0 4777 beiscsi_conn->task = task;
6733b39a
JK		 4778 if (!beiscsi_conn->login_in_progress) {
4779 spin_lock(&phba->mgmt_sgl_lock);
4780 io_task->psgl_handle = (struct sgl_handle *)
4781 alloc_mgmt_sgl_handle(phba);
4782 spin_unlock(&phba->mgmt_sgl_lock);
8359c79b
JSJ		 4783 if (!io_task->psgl_handle) {
4784 beiscsi_log(phba, KERN_ERR,
4785 BEISCSI_LOG_IO |
4786 BEISCSI_LOG_CONFIG,
4787 "BM_%d : Alloc of MGMT_SGL_ICD Failed"
4788 "for the CID : %d\n",
4789 beiscsi_conn->
4790 beiscsi_conn_cid);
2afc95bf 4791 goto free_hndls;
8359c79b 4792 }
2afc95bf 4793
6733b39a
JK		 4794 beiscsi_conn->login_in_progress = 1;
4795 beiscsi_conn->plogin_sgl_handle =
4796 io_task->psgl_handle;
d2cecf0d
JK		 4797 io_task->pwrb_handle =
4798 alloc_wrb_handle(phba,
a7909b39 4799 beiscsi_conn->beiscsi_conn_cid);
8359c79b
JSJ		 4800 if (!io_task->pwrb_handle) {
4801 beiscsi_log(phba, KERN_ERR,
4802 BEISCSI_LOG_IO |
4803 BEISCSI_LOG_CONFIG,
4804 "BM_%d : Alloc of WRB_HANDLE Failed"
4805 "for the CID : %d\n",
4806 beiscsi_conn->
4807 beiscsi_conn_cid);
4808 goto free_mgmt_hndls;
4809 }
d2cecf0d
JK		 4810 beiscsi_conn->plogin_wrb_handle =
4811 io_task->pwrb_handle;
4812
6733b39a
JK		 4813 } else {
4814 io_task->psgl_handle =
4815 beiscsi_conn->plogin_sgl_handle;
d2cecf0d
JK		 4816 io_task->pwrb_handle =
4817 beiscsi_conn->plogin_wrb_handle;
6733b39a
JK		 4818 }
4819 } else {
4820 spin_lock(&phba->mgmt_sgl_lock);
4821 io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
4822 spin_unlock(&phba->mgmt_sgl_lock);
8359c79b
JSJ		 4823 if (!io_task->psgl_handle) {
4824 beiscsi_log(phba, KERN_ERR,
4825 BEISCSI_LOG_IO |
4826 BEISCSI_LOG_CONFIG,
4827 "BM_%d : Alloc of MGMT_SGL_ICD Failed"
4828 "for the CID : %d\n",
4829 beiscsi_conn->
4830 beiscsi_conn_cid);
2afc95bf 4831 goto free_hndls;
8359c79b 4832 }
d2cecf0d
JK		 4833 io_task->pwrb_handle =
4834 alloc_wrb_handle(phba,
a7909b39 4835 beiscsi_conn->beiscsi_conn_cid);
8359c79b
JSJ		 4836 if (!io_task->pwrb_handle) {
4837 beiscsi_log(phba, KERN_ERR,
4838 BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
4839 "BM_%d : Alloc of WRB_HANDLE Failed"
4840 "for the CID : %d\n",
4841 beiscsi_conn->beiscsi_conn_cid);
d2cecf0d 4842 goto free_mgmt_hndls;
8359c79b 4843 }
d2cecf0d 4844
6733b39a
JK		 4845 }
4846 }
bfead3b2
JK		 4847 itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
4848 wrb_index << 16) | (unsigned int)
4849 (io_task->psgl_handle->sgl_index));
32951dd8 4850 io_task->pwrb_handle->pio_handle = task;
bfead3b2 4851
6733b39a
JK		 4852 io_task->cmd_bhs->iscsi_hdr.itt = itt;
4853 return 0;
2afc95bf 4854
d2cecf0d
JK		 4855free_io_hndls:
4856 spin_lock(&phba->io_sgl_lock);
4857 free_io_sgl_handle(phba, io_task->psgl_handle);
4858 spin_unlock(&phba->io_sgl_lock);
4859 goto free_hndls;
4860free_mgmt_hndls:
4861 spin_lock(&phba->mgmt_sgl_lock);
4862 free_mgmt_sgl_handle(phba, io_task->psgl_handle);
a7909b39 4863 io_task->psgl_handle = NULL;
d2cecf0d 4864 spin_unlock(&phba->mgmt_sgl_lock);
2afc95bf
JK		 4865free_hndls:
4866 phwi_ctrlr = phba->phwi_ctrlr;
a7909b39
JK		 4867 cri_index = BE_GET_CRI_FROM_CID(
4868 beiscsi_conn->beiscsi_conn_cid);
4869 pwrb_context = &phwi_ctrlr->wrb_context[cri_index];
d2cecf0d
JK		 4870 if (io_task->pwrb_handle)
4871 free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
2afc95bf
JK		 4872 io_task->pwrb_handle = NULL;
4873 pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
4874 io_task->bhs_pa.u.a64.address);
1282ab76 4875 io_task->cmd_bhs = NULL;
2afc95bf 4876 return -ENOMEM;
6733b39a 4877}
09a1093a
JSJ		 4878int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg,
4879 unsigned int num_sg, unsigned int xferlen,
4880 unsigned int writedir)
4881{
4882
4883 struct beiscsi_io_task *io_task = task->dd_data;
4884 struct iscsi_conn *conn = task->conn;
4885 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4886 struct beiscsi_hba *phba = beiscsi_conn->phba;
4887 struct iscsi_wrb *pwrb = NULL;
4888 unsigned int doorbell = 0;
4889
4890 pwrb = io_task->pwrb_handle->pwrb;
09a1093a
JSJ		 4891
4892 io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
4893 io_task->bhs_len = sizeof(struct be_cmd_bhs);
4894
4895 if (writedir) {
4896 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
4897 INI_WR_CMD);
4898 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1);
4899 } else {
4900 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
4901 INI_RD_CMD);
4902 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0);
4903 }
4904
4905 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2,
4906 type, pwrb);
4907
4908 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb,
4909 cpu_to_be16(*(unsigned short *)
4910 &io_task->cmd_bhs->iscsi_hdr.lun));
4911 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen);
4912 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
4913 io_task->pwrb_handle->wrb_index);
4914 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
4915 be32_to_cpu(task->cmdsn));
4916 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
4917 io_task->psgl_handle->sgl_index);
4918
4919 hwi_write_sgl_v2(pwrb, sg, num_sg, io_task);
4920 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
4921 io_task->pwrb_handle->nxt_wrb_index);
4922
4923 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4924
4925 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
4926 doorbell |= (io_task->pwrb_handle->wrb_index &
4927 DB_DEF_PDU_WRB_INDEX_MASK) <<
4928 DB_DEF_PDU_WRB_INDEX_SHIFT;
4929 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 4930 iowrite32(doorbell, phba->db_va +
4931 beiscsi_conn->doorbell_offset);
09a1093a
JSJ		 4932 return 0;
4933}
6733b39a 4934
6733b39a
JK		 4935static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
4936 unsigned int num_sg, unsigned int xferlen,
4937 unsigned int writedir)
4938{
4939
4940 struct beiscsi_io_task *io_task = task->dd_data;
4941 struct iscsi_conn *conn = task->conn;
4942 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4943 struct beiscsi_hba *phba = beiscsi_conn->phba;
4944 struct iscsi_wrb *pwrb = NULL;
4945 unsigned int doorbell = 0;
4946
4947 pwrb = io_task->pwrb_handle->pwrb;
6733b39a
JK		 4948 io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
4949 io_task->bhs_len = sizeof(struct be_cmd_bhs);
4950
4951 if (writedir) {
32951dd8
JK		 4952 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4953 INI_WR_CMD);
6733b39a 4954 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
6733b39a 4955 } else {
32951dd8
JK		 4956 AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
4957 INI_RD_CMD);
6733b39a
JK		 4958 AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
4959 }
6733b39a 4960
09a1093a
JSJ		 4961 io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb,
4962 type, pwrb);
4963
6733b39a 4964 AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
dc63aac6
JK		 4965 cpu_to_be16(*(unsigned short *)
4966 &io_task->cmd_bhs->iscsi_hdr.lun));
6733b39a
JK		 4967 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
4968 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
4969 io_task->pwrb_handle->wrb_index);
4970 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
4971 be32_to_cpu(task->cmdsn));
4972 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
4973 io_task->psgl_handle->sgl_index);
4974
4975 hwi_write_sgl(pwrb, sg, num_sg, io_task);
4976
4977 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
4978 io_task->pwrb_handle->nxt_wrb_index);
4979 be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
4980
4981 doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
32951dd8 4982 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 4983 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
4984 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
4985
1e4be6ff
JK		 4986 iowrite32(doorbell, phba->db_va +
4987 beiscsi_conn->doorbell_offset);
6733b39a
JK		 4988 return 0;
4989}
4990
4991static int beiscsi_mtask(struct iscsi_task *task)
4992{
dafab8e0 4993 struct beiscsi_io_task *io_task = task->dd_data;
6733b39a
JK		 4994 struct iscsi_conn *conn = task->conn;
4995 struct beiscsi_conn *beiscsi_conn = conn->dd_data;
4996 struct beiscsi_hba *phba = beiscsi_conn->phba;
4997 struct iscsi_wrb *pwrb = NULL;
4998 unsigned int doorbell = 0;
dafab8e0 4999 unsigned int cid;
09a1093a 5000 unsigned int pwrb_typeoffset = 0;
6733b39a 5001
bfead3b2 5002 cid = beiscsi_conn->beiscsi_conn_cid;
6733b39a 5003 pwrb = io_task->pwrb_handle->pwrb;
caf818f1 5004 memset(pwrb, 0, sizeof(*pwrb));
09a1093a 5005
2c9dfd36 5006 if (is_chip_be2_be3r(phba)) {
09a1093a
JSJ		 5007 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
5008 be32_to_cpu(task->cmdsn));
5009 AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
5010 io_task->pwrb_handle->wrb_index);
5011 AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
5012 io_task->psgl_handle->sgl_index);
5013 AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
5014 task->data_count);
5015 AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
5016 io_task->pwrb_handle->nxt_wrb_index);
5017 pwrb_typeoffset = BE_WRB_TYPE_OFFSET;
2c9dfd36
JK		 5018 } else {
5019 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
5020 be32_to_cpu(task->cmdsn));
5021 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
5022 io_task->pwrb_handle->wrb_index);
5023 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
5024 io_task->psgl_handle->sgl_index);
5025 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb,
5026 task->data_count);
5027 AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
5028 io_task->pwrb_handle->nxt_wrb_index);
5029 pwrb_typeoffset = SKH_WRB_TYPE_OFFSET;
09a1093a
JSJ		 5030 }
5031
dafab8e0 5032
6733b39a
JK		 5033 switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
5034 case ISCSI_OP_LOGIN:
6733b39a 5035 AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
09a1093a 5036 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
6733b39a
JK		 5037 hwi_write_buffer(pwrb, task);
5038 break;
5039 case ISCSI_OP_NOOP_OUT:
1390b01b 5040 if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
09a1093a 5041 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
2c9dfd36
JK		 5042 if (is_chip_be2_be3r(phba))
5043 AMAP_SET_BITS(struct amap_iscsi_wrb,
09a1093a
JSJ		 5044 dmsg, pwrb, 1);
5045 else
2c9dfd36 5046 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
09a1093a 5047 dmsg, pwrb, 1);
1390b01b 5048 } else {
09a1093a 5049 ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset);
2c9dfd36
JK		 5050 if (is_chip_be2_be3r(phba))
5051 AMAP_SET_BITS(struct amap_iscsi_wrb,
09a1093a
JSJ		 5052 dmsg, pwrb, 0);
5053 else
2c9dfd36 5054 AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
09a1093a 5055 dmsg, pwrb, 0);
1390b01b 5056 }
6733b39a
JK		 5057 hwi_write_buffer(pwrb, task);
5058 break;
5059 case ISCSI_OP_TEXT:
09a1093a 5060 ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
6733b39a
JK		 5061 hwi_write_buffer(pwrb, task);
5062 break;
5063 case ISCSI_OP_SCSI_TMFUNC:
09a1093a 5064 ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset);
6733b39a
JK		 5065 hwi_write_buffer(pwrb, task);
5066 break;
5067 case ISCSI_OP_LOGOUT:
09a1093a 5068 ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset);
6733b39a
JK		 5069 hwi_write_buffer(pwrb, task);
5070 break;
5071
5072 default:
99bc5d55
JSJ		 5073 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
5074 "BM_%d : opcode =%d Not supported\n",
5075 task->hdr->opcode & ISCSI_OPCODE_MASK);
5076
6733b39a
JK		 5077 return -EINVAL;
5078 }
5079
09a1093a 5080 /* Set the task type */
2c9dfd36
JK		 5081 io_task->wrb_type = (is_chip_be2_be3r(phba)) ?
5082 AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb) :
5083 AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb);
6733b39a 5084
bfead3b2 5085 doorbell |= cid & DB_WRB_POST_CID_MASK;
32951dd8 5086 doorbell |= (io_task->pwrb_handle->wrb_index &
6733b39a
JK		 5087 DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
5088 doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
1e4be6ff
JK		 5089 iowrite32(doorbell, phba->db_va +
5090 beiscsi_conn->doorbell_offset);
6733b39a
JK		 5091 return 0;
5092}
5093
5094static int beiscsi_task_xmit(struct iscsi_task *task)
5095{
6733b39a
JK		 5096 struct beiscsi_io_task *io_task = task->dd_data;
5097 struct scsi_cmnd *sc = task->sc;
09a1093a 5098 struct beiscsi_hba *phba = NULL;
6733b39a
JK		 5099 struct scatterlist *sg;
5100 int num_sg;
5101 unsigned int writedir = 0, xferlen = 0;
5102
09a1093a
JSJ		 5103 phba = ((struct beiscsi_conn *)task->conn->dd_data)->phba;
5104
6733b39a
JK		 5105 if (!sc)
5106 return beiscsi_mtask(task);
5107
5108 io_task->scsi_cmnd = sc;
5109 num_sg = scsi_dma_map(sc);
5110 if (num_sg < 0) {
99bc5d55
JSJ		 5111 struct iscsi_conn *conn = task->conn;
5112 struct beiscsi_hba *phba = NULL;
5113
5114 phba = ((struct beiscsi_conn *)conn->dd_data)->phba;
afb96058
JK		 5115 beiscsi_log(phba, KERN_ERR,
5116 BEISCSI_LOG_IO | BEISCSI_LOG_ISCSI,
5117 "BM_%d : scsi_dma_map Failed "
5118 "Driver_ITT : 0x%x ITT : 0x%x Xferlen : 0x%x\n",
5119 be32_to_cpu(io_task->cmd_bhs->iscsi_hdr.itt),
5120 io_task->libiscsi_itt, scsi_bufflen(sc));
99bc5d55 5121
6733b39a
JK		 5122 return num_sg;
5123 }
6733b39a
JK		 5124 xferlen = scsi_bufflen(sc);
5125 sg = scsi_sglist(sc);
99bc5d55 5126 if (sc->sc_data_direction == DMA_TO_DEVICE)
6733b39a 5127 writedir = 1;
99bc5d55 5128 else
6733b39a 5129 writedir = 0;
99bc5d55 5130
09a1093a 5131 return phba->iotask_fn(task, sg, num_sg, xferlen, writedir);
6733b39a
JK		 5132}
5133
ffce3e2e
JK		 5134/**
5135 * beiscsi_bsg_request - handle bsg request from ISCSI transport
5136 * @job: job to handle
5137 */
5138static int beiscsi_bsg_request(struct bsg_job *job)
5139{
5140 struct Scsi_Host *shost;
5141 struct beiscsi_hba *phba;
5142 struct iscsi_bsg_request *bsg_req = job->request;
5143 int rc = -EINVAL;
5144 unsigned int tag;
5145 struct be_dma_mem nonemb_cmd;
5146 struct be_cmd_resp_hdr *resp;
5147 struct iscsi_bsg_reply *bsg_reply = job->reply;
5148 unsigned short status, extd_status;
5149
5150 shost = iscsi_job_to_shost(job);
5151 phba = iscsi_host_priv(shost);
5152
5153 switch (bsg_req->msgcode) {
5154 case ISCSI_BSG_HST_VENDOR:
5155 nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
5156 job->request_payload.payload_len,
5157 &nonemb_cmd.dma);
5158 if (nonemb_cmd.va == NULL) {
99bc5d55
JSJ		 5159 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
5160 "BM_%d : Failed to allocate memory for "
5161 "beiscsi_bsg_request\n");
8359c79b 5162 return -ENOMEM;
ffce3e2e
JK		 5163 }
5164 tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
5165 &nonemb_cmd);
5166 if (!tag) {
99bc5d55 5167 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
8359c79b 5168 "BM_%d : MBX Tag Allocation Failed\n");
99bc5d55 5169
ffce3e2e
JK		 5170 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
5171 nonemb_cmd.va, nonemb_cmd.dma);
5172 return -EAGAIN;
e175defe
JSJ		 5173 }
5174
5175 rc = wait_event_interruptible_timeout(
5176 phba->ctrl.mcc_wait[tag],
5177 phba->ctrl.mcc_numtag[tag],
5178 msecs_to_jiffies(
5179 BEISCSI_HOST_MBX_TIMEOUT));
ffce3e2e
JK		 5180 extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
5181 status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
5182 free_mcc_tag(&phba->ctrl, tag);
5183 resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
5184 sg_copy_from_buffer(job->reply_payload.sg_list,
5185 job->reply_payload.sg_cnt,
5186 nonemb_cmd.va, (resp->response_length
5187 + sizeof(*resp)));
5188 bsg_reply->reply_payload_rcv_len = resp->response_length;
5189 bsg_reply->result = status;
5190 bsg_job_done(job, bsg_reply->result,
5191 bsg_reply->reply_payload_rcv_len);
5192 pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
5193 nonemb_cmd.va, nonemb_cmd.dma);
5194 if (status || extd_status) {
99bc5d55 5195 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
8359c79b 5196 "BM_%d : MBX Cmd Failed"
99bc5d55
JSJ		 5197 " status = %d extd_status = %d\n",
5198 status, extd_status);
5199
ffce3e2e 5200 return -EIO;
8359c79b
JSJ		 5201 } else {
5202 rc = 0;
ffce3e2e
JK		 5203 }
5204 break;
5205
5206 default:
99bc5d55
JSJ		 5207 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
5208 "BM_%d : Unsupported bsg command: 0x%x\n",
5209 bsg_req->msgcode);
ffce3e2e
JK		 5210 break;
5211 }
5212
5213 return rc;
5214}
5215
99bc5d55
JSJ		 5216void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
5217{
5218 /* Set the logging parameter */
5219 beiscsi_log_enable_init(phba, beiscsi_log_enable);
5220}
5221
4d4d1ef8
JSJ		 5222/*
5223 * beiscsi_quiesce()- Cleanup Driver resources
5224 * @phba: Instance Priv structure
3567f36a 5225 * @unload_state:i Clean or EEH unload state
4d4d1ef8
JSJ		 5226 *
5227 * Free the OS and HW resources held by the driver
5228 **/
3567f36a
JK		 5229static void beiscsi_quiesce(struct beiscsi_hba *phba,
5230 uint32_t unload_state)
6733b39a 5231{
bfead3b2
JK		 5232 struct hwi_controller *phwi_ctrlr;
5233 struct hwi_context_memory *phwi_context;
5234 struct be_eq_obj *pbe_eq;
5235 unsigned int i, msix_vec;
6733b39a 5236
bfead3b2
JK		 5237 phwi_ctrlr = phba->phwi_ctrlr;
5238 phwi_context = phwi_ctrlr->phwi_ctxt;
6733b39a 5239 hwi_disable_intr(phba);
bfead3b2
JK		 5240 if (phba->msix_enabled) {
5241 for (i = 0; i <= phba->num_cpus; i++) {
5242 msix_vec = phba->msix_entries[i].vector;
3567f36a 5243 synchronize_irq(msix_vec);
bfead3b2 5244 free_irq(msix_vec, &phwi_context->be_eq[i]);
8fcfb210 5245 kfree(phba->msi_name[i]);
bfead3b2
JK		 5246 }
5247 } else
3567f36a
JK		 5248 if (phba->pcidev->irq) {
5249 synchronize_irq(phba->pcidev->irq);
bfead3b2 5250 free_irq(phba->pcidev->irq, phba);
3567f36a 5251 }
bfead3b2 5252 pci_disable_msix(phba->pcidev);
53281edb 5253 cancel_delayed_work_sync(&phba->beiscsi_hw_check_task);
3567f36a 5254
89f8b33c
JA		 5255 for (i = 0; i < phba->num_cpus; i++) {
5256 pbe_eq = &phwi_context->be_eq[i];
5257 blk_iopoll_disable(&pbe_eq->iopoll);
5258 }
6733b39a 5259
3567f36a
JK		 5260 if (unload_state == BEISCSI_CLEAN_UNLOAD) {
5261 destroy_workqueue(phba->wq);
5262 beiscsi_clean_port(phba);
5263 beiscsi_free_mem(phba);
e9b91193 5264
3567f36a
JK		 5265 beiscsi_unmap_pci_function(phba);
5266 pci_free_consistent(phba->pcidev,
5267 phba->ctrl.mbox_mem_alloced.size,
5268 phba->ctrl.mbox_mem_alloced.va,
5269 phba->ctrl.mbox_mem_alloced.dma);
5270 } else {
5271 hwi_purge_eq(phba);
5272 hwi_cleanup(phba);
5273 }
7a158003 5274
25602c97
JK		 5275}
5276
5277static void beiscsi_remove(struct pci_dev *pcidev)
5278{
5279
5280 struct beiscsi_hba *phba = NULL;
5281
5282 phba = pci_get_drvdata(pcidev);
5283 if (!phba) {
5284 dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
5285 return;
5286 }
5287
0e43895e 5288 beiscsi_destroy_def_ifaces(phba);
3567f36a 5289 beiscsi_quiesce(phba, BEISCSI_CLEAN_UNLOAD);
9d045163 5290 iscsi_boot_destroy_kset(phba->boot_kset);
6733b39a
JK		 5291 iscsi_host_remove(phba->shost);
5292 pci_dev_put(phba->pcidev);
5293 iscsi_host_free(phba->shost);
3567f36a
JK		 5294 pci_disable_pcie_error_reporting(pcidev);
5295 pci_set_drvdata(pcidev, NULL);
e307f3ac 5296 pci_release_regions(pcidev);
8dce69ff 5297 pci_disable_device(pcidev);
6733b39a
JK		 5298}
5299
25602c97
JK		 5300static void beiscsi_shutdown(struct pci_dev *pcidev)
5301{
5302
5303 struct beiscsi_hba *phba = NULL;
5304
5305 phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
5306 if (!phba) {
5307 dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
5308 return;
5309 }
5310
9343be74
JK		 5311 phba->state = BE_ADAPTER_STATE_SHUTDOWN;
5312 iscsi_host_for_each_session(phba->shost, be2iscsi_fail_session);
3567f36a 5313 beiscsi_quiesce(phba, BEISCSI_CLEAN_UNLOAD);
8dce69ff 5314 pci_disable_device(pcidev);
25602c97
JK		 5315}
5316
bfead3b2
JK		 5317static void beiscsi_msix_enable(struct beiscsi_hba *phba)
5318{
5319 int i, status;
5320
5321 for (i = 0; i <= phba->num_cpus; i++)
5322 phba->msix_entries[i].entry = i;
5323
e149fc13
AG		 5324 status = pci_enable_msix_range(phba->pcidev, phba->msix_entries,
5325 phba->num_cpus + 1, phba->num_cpus + 1);
5326 if (status > 0)
bfead3b2
JK		 5327 phba->msix_enabled = true;
5328
5329 return;
5330}
5331
73af08e1
JK		 5332static void be_eqd_update(struct beiscsi_hba *phba)
5333{
5334 struct be_set_eqd set_eqd[MAX_CPUS];
5335 struct be_aic_obj *aic;
5336 struct be_eq_obj *pbe_eq;
5337 struct hwi_controller *phwi_ctrlr;
5338 struct hwi_context_memory *phwi_context;
5339 int eqd, i, num = 0;
5340 ulong now;
5341 u32 pps, delta;
5342 unsigned int tag;
5343
5344 phwi_ctrlr = phba->phwi_ctrlr;
5345 phwi_context = phwi_ctrlr->phwi_ctxt;
5346
5347 for (i = 0; i <= phba->num_cpus; i++) {
5348 aic = &phba->aic_obj[i];
5349 pbe_eq = &phwi_context->be_eq[i];
5350 now = jiffies;
5351 if (!aic->jiffs || time_before(now, aic->jiffs) ||
5352 pbe_eq->cq_count < aic->eq_prev) {
5353 aic->jiffs = now;
5354 aic->eq_prev = pbe_eq->cq_count;
5355 continue;
5356 }
5357 delta = jiffies_to_msecs(now - aic->jiffs);
5358 pps = (((u32)(pbe_eq->cq_count - aic->eq_prev) * 1000) / delta);
5359 eqd = (pps / 1500) << 2;
5360
5361 if (eqd < 8)
5362 eqd = 0;
5363 eqd = min_t(u32, eqd, phwi_context->max_eqd);
5364 eqd = max_t(u32, eqd, phwi_context->min_eqd);
5365
5366 aic->jiffs = now;
5367 aic->eq_prev = pbe_eq->cq_count;
5368
5369 if (eqd != aic->prev_eqd) {
5370 set_eqd[num].delay_multiplier = (eqd * 65)/100;
5371 set_eqd[num].eq_id = pbe_eq->q.id;
5372 aic->prev_eqd = eqd;
5373 num++;
5374 }
5375 }
5376 if (num) {
5377 tag = be_cmd_modify_eq_delay(phba, set_eqd, num);
5378 if (tag)
5379 beiscsi_mccq_compl(phba, tag, NULL, NULL);
5380 }
5381}
5382
a3d313ea
JK		 5383static void be_check_boot_session(struct beiscsi_hba *phba)
5384{
5385 if (beiscsi_setup_boot_info(phba))
5386 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5387 "BM_%d : Could not set up "
5388 "iSCSI boot info on async event.\n");
5389}
5390
7a158003
JSJ		 5391/*
5392 * beiscsi_hw_health_check()- Check adapter health
5393 * @work: work item to check HW health
5394 *
5395 * Check if adapter in an unrecoverable state or not.
5396 **/
5397static void
5398beiscsi_hw_health_check(struct work_struct *work)
5399{
5400 struct beiscsi_hba *phba =
5401 container_of(work, struct beiscsi_hba,
5402 beiscsi_hw_check_task.work);
5403
73af08e1
JK		 5404 be_eqd_update(phba);
5405
a3d313ea 5406 if (phba->state & BE_ADAPTER_CHECK_BOOT) {
3efde862
JSJ		 5407 if ((phba->get_boot > 0) && (!phba->boot_kset)) {
5408 phba->get_boot--;
5409 if (!(phba->get_boot % BE_GET_BOOT_TO))
5410 be_check_boot_session(phba);
5411 } else {
5412 phba->state &= ~BE_ADAPTER_CHECK_BOOT;
5413 phba->get_boot = 0;
5414 }
a3d313ea
JK		 5415 }
5416
7a158003
JSJ		 5417 beiscsi_ue_detect(phba);
5418
5419 schedule_delayed_work(&phba->beiscsi_hw_check_task,
5420 msecs_to_jiffies(1000));
5421}
5422
3567f36a
JK		 5423
5424static pci_ers_result_t beiscsi_eeh_err_detected(struct pci_dev *pdev,
5425 pci_channel_state_t state)
5426{
5427 struct beiscsi_hba *phba = NULL;
5428
5429 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5430 phba->state |= BE_ADAPTER_PCI_ERR;
5431
5432 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5433 "BM_%d : EEH error detected\n");
5434
5435 beiscsi_quiesce(phba, BEISCSI_EEH_UNLOAD);
5436
5437 if (state == pci_channel_io_perm_failure) {
5438 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5439 "BM_%d : EEH : State PERM Failure");
5440 return PCI_ERS_RESULT_DISCONNECT;
5441 }
5442
5443 pci_disable_device(pdev);
5444
5445 /* The error could cause the FW to trigger a flash debug dump.
5446 * Resetting the card while flash dump is in progress
5447 * can cause it not to recover; wait for it to finish.
5448 * Wait only for first function as it is needed only once per
5449 * adapter.
5450 **/
5451 if (pdev->devfn == 0)
5452 ssleep(30);
5453
5454 return PCI_ERS_RESULT_NEED_RESET;
5455}
5456
5457static pci_ers_result_t beiscsi_eeh_reset(struct pci_dev *pdev)
5458{
5459 struct beiscsi_hba *phba = NULL;
5460 int status = 0;
5461
5462 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5463
5464 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5465 "BM_%d : EEH Reset\n");
5466
5467 status = pci_enable_device(pdev);
5468 if (status)
5469 return PCI_ERS_RESULT_DISCONNECT;
5470
5471 pci_set_master(pdev);
5472 pci_set_power_state(pdev, PCI_D0);
5473 pci_restore_state(pdev);
5474
5475 /* Wait for the CHIP Reset to complete */
5476 status = be_chk_reset_complete(phba);
5477 if (!status) {
5478 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5479 "BM_%d : EEH Reset Completed\n");
5480 } else {
5481 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5482 "BM_%d : EEH Reset Completion Failure\n");
5483 return PCI_ERS_RESULT_DISCONNECT;
5484 }
5485
5486 pci_cleanup_aer_uncorrect_error_status(pdev);
5487 return PCI_ERS_RESULT_RECOVERED;
5488}
5489
5490static void beiscsi_eeh_resume(struct pci_dev *pdev)
5491{
5492 int ret = 0, i;
5493 struct be_eq_obj *pbe_eq;
5494 struct beiscsi_hba *phba = NULL;
5495 struct hwi_controller *phwi_ctrlr;
5496 struct hwi_context_memory *phwi_context;
5497
5498 phba = (struct beiscsi_hba *)pci_get_drvdata(pdev);
5499 pci_save_state(pdev);
5500
5501 if (enable_msix)
5502 find_num_cpus(phba);
5503 else
5504 phba->num_cpus = 1;
5505
5506 if (enable_msix) {
5507 beiscsi_msix_enable(phba);
5508 if (!phba->msix_enabled)
5509 phba->num_cpus = 1;
5510 }
5511
5512 ret = beiscsi_cmd_reset_function(phba);
5513 if (ret) {
5514 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5515 "BM_%d : Reset Failed\n");
5516 goto ret_err;
5517 }
5518
5519 ret = be_chk_reset_complete(phba);
5520 if (ret) {
5521 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5522 "BM_%d : Failed to get out of reset.\n");
5523 goto ret_err;
5524 }
5525
5526 beiscsi_get_params(phba);
5527 phba->shost->max_id = phba->params.cxns_per_ctrl;
5528 phba->shost->can_queue = phba->params.ios_per_ctrl;
5529 ret = hwi_init_controller(phba);
5530
5531 for (i = 0; i < MAX_MCC_CMD; i++) {
5532 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
5533 phba->ctrl.mcc_tag[i] = i + 1;
5534 phba->ctrl.mcc_numtag[i + 1] = 0;
5535 phba->ctrl.mcc_tag_available++;
5536 }
5537
5538 phwi_ctrlr = phba->phwi_ctrlr;
5539 phwi_context = phwi_ctrlr->phwi_ctxt;
5540
89f8b33c 5541 for (i = 0; i < phba->num_cpus; i++) {
3567f36a 5542 pbe_eq = &phwi_context->be_eq[i];
89f8b33c
JA		 5543 blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
5544 be_iopoll);
5545 blk_iopoll_enable(&pbe_eq->iopoll);
3567f36a
JK		 5546 }
5547
89f8b33c
JA		 5548 i = (phba->msix_enabled) ? i : 0;
5549 /* Work item for MCC handling */
5550 pbe_eq = &phwi_context->be_eq[i];
5551 INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
5552
3567f36a
JK		 5553 ret = beiscsi_init_irqs(phba);
5554 if (ret < 0) {
5555 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5556 "BM_%d : beiscsi_eeh_resume - "
5557 "Failed to beiscsi_init_irqs\n");
5558 goto ret_err;
5559 }
5560
5561 hwi_enable_intr(phba);
5562 phba->state &= ~BE_ADAPTER_PCI_ERR;
5563
5564 return;
5565ret_err:
5566 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5567 "BM_%d : AER EEH Resume Failed\n");
5568}
5569
6f039790
GKH		 5570static int beiscsi_dev_probe(struct pci_dev *pcidev,
5571 const struct pci_device_id *id)
6733b39a
JK		 5572{
5573 struct beiscsi_hba *phba = NULL;
bfead3b2
JK		 5574 struct hwi_controller *phwi_ctrlr;
5575 struct hwi_context_memory *phwi_context;
5576 struct be_eq_obj *pbe_eq;
3567f36a 5577 int ret = 0, i;
6733b39a
JK		 5578
5579 ret = beiscsi_enable_pci(pcidev);
5580 if (ret < 0) {
99bc5d55
JSJ		 5581 dev_err(&pcidev->dev,
5582 "beiscsi_dev_probe - Failed to enable pci device\n");
6733b39a
JK		 5583 return ret;
5584 }
5585
5586 phba = beiscsi_hba_alloc(pcidev);
5587 if (!phba) {
99bc5d55
JSJ		 5588 dev_err(&pcidev->dev,
5589 "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
6733b39a
JK		 5590 goto disable_pci;
5591 }
5592
3567f36a
JK		 5593 /* Enable EEH reporting */
5594 ret = pci_enable_pcie_error_reporting(pcidev);
5595 if (ret)
5596 beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
5597 "BM_%d : PCIe Error Reporting "
5598 "Enabling Failed\n");
5599
5600 pci_save_state(pcidev);
5601
99bc5d55
JSJ		 5602 /* Initialize Driver configuration Paramters */
5603 beiscsi_hba_attrs_init(phba);
5604
e175defe 5605 phba->fw_timeout = false;
6c83185a 5606 phba->mac_addr_set = false;
e175defe
JSJ		 5607
5608
f98c96b0
JK		 5609 switch (pcidev->device) {
5610 case BE_DEVICE_ID1:
5611 case OC_DEVICE_ID1:
5612 case OC_DEVICE_ID2:
5613 phba->generation = BE_GEN2;
09a1093a 5614 phba->iotask_fn = beiscsi_iotask;
f98c96b0
JK		 5615 break;
5616 case BE_DEVICE_ID2:
5617 case OC_DEVICE_ID3:
5618 phba->generation = BE_GEN3;
09a1093a 5619 phba->iotask_fn = beiscsi_iotask;
f98c96b0 5620 break;
139a1b1e
JSJ		 5621 case OC_SKH_ID1:
5622 phba->generation = BE_GEN4;
09a1093a 5623 phba->iotask_fn = beiscsi_iotask_v2;
bf9131cb 5624 break;
f98c96b0
JK		 5625 default:
5626 phba->generation = 0;
5627 }
5628
6733b39a
JK		 5629 ret = be_ctrl_init(phba, pcidev);
5630 if (ret) {
99bc5d55
JSJ		 5631 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5632 "BM_%d : beiscsi_dev_probe-"
5633 "Failed in be_ctrl_init\n");
6733b39a
JK		 5634 goto hba_free;
5635 }
5636
4d4d1ef8
JSJ		 5637 ret = beiscsi_cmd_reset_function(phba);
5638 if (ret) {
5639 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
92665a66 5640 "BM_%d : Reset Failed\n");
4d4d1ef8
JSJ		 5641 goto hba_free;
5642 }
5643 ret = be_chk_reset_complete(phba);
5644 if (ret) {
5645 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
92665a66 5646 "BM_%d : Failed to get out of reset.\n");
4d4d1ef8 5647 goto hba_free;
e9b91193
JK		 5648 }
5649
6733b39a
JK		 5650 spin_lock_init(&phba->io_sgl_lock);
5651 spin_lock_init(&phba->mgmt_sgl_lock);
5652 spin_lock_init(&phba->isr_lock);
8f09a3b9 5653 spin_lock_init(&phba->async_pdu_lock);
7da50879
JK		 5654 ret = mgmt_get_fw_config(&phba->ctrl, phba);
5655 if (ret != 0) {
99bc5d55
JSJ		 5656 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5657 "BM_%d : Error getting fw config\n");
7da50879
JK		 5658 goto free_port;
5659 }
68c26a3a
JK		 5660
5661 if (enable_msix)
5662 find_num_cpus(phba);
5663 else
5664 phba->num_cpus = 1;
5665
5666 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
5667 "BM_%d : num_cpus = %d\n",
5668 phba->num_cpus);
5669
5670 if (enable_msix) {
5671 beiscsi_msix_enable(phba);
5672 if (!phba->msix_enabled)
5673 phba->num_cpus = 1;
5674 }
5675
843ae752 5676 phba->shost->max_id = phba->params.cxns_per_ctrl;
6733b39a 5677 beiscsi_get_params(phba);
aa874f07 5678 phba->shost->can_queue = phba->params.ios_per_ctrl;
6733b39a
JK		 5679 ret = beiscsi_init_port(phba);
5680 if (ret < 0) {
99bc5d55
JSJ		 5681 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5682 "BM_%d : beiscsi_dev_probe-"
5683 "Failed in beiscsi_init_port\n");
6733b39a
JK		 5684 goto free_port;
5685 }
5686
3567f36a 5687 for (i = 0; i < MAX_MCC_CMD; i++) {
756d29c8
JK		 5688 init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
5689 phba->ctrl.mcc_tag[i] = i + 1;
5690 phba->ctrl.mcc_numtag[i + 1] = 0;
5691 phba->ctrl.mcc_tag_available++;
1957aa7f 5692 memset(&phba->ctrl.ptag_state[i].tag_mem_state, 0,
8fc01eaa 5693 sizeof(struct be_dma_mem));
756d29c8
JK		 5694 }
5695
5696 phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
5697
72fb46a9 5698 snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq",
6733b39a 5699 phba->shost->host_no);
d8537548 5700 phba->wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 1, phba->wq_name);
6733b39a 5701 if (!phba->wq) {
99bc5d55
JSJ		 5702 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5703 "BM_%d : beiscsi_dev_probe-"
5704 "Failed to allocate work queue\n");
6733b39a
JK		 5705 goto free_twq;
5706 }
5707
7a158003
JSJ		 5708 INIT_DELAYED_WORK(&phba->beiscsi_hw_check_task,
5709 beiscsi_hw_health_check);
6733b39a 5710
bfead3b2
JK		 5711 phwi_ctrlr = phba->phwi_ctrlr;
5712 phwi_context = phwi_ctrlr->phwi_ctxt;
72fb46a9 5713
89f8b33c 5714 for (i = 0; i < phba->num_cpus; i++) {
72fb46a9 5715 pbe_eq = &phwi_context->be_eq[i];
89f8b33c
JA		 5716 blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
5717 be_iopoll);
5718 blk_iopoll_enable(&pbe_eq->iopoll);
6733b39a 5719 }
72fb46a9 5720
89f8b33c
JA		 5721 i = (phba->msix_enabled) ? i : 0;
5722 /* Work item for MCC handling */
5723 pbe_eq = &phwi_context->be_eq[i];
5724 INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
5725
6733b39a
JK		 5726 ret = beiscsi_init_irqs(phba);
5727 if (ret < 0) {
99bc5d55
JSJ		 5728 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5729 "BM_%d : beiscsi_dev_probe-"
5730 "Failed to beiscsi_init_irqs\n");
6733b39a
JK		 5731 goto free_blkenbld;
5732 }
238f6b72 5733 hwi_enable_intr(phba);
f457a46f 5734
0598b8af
JK		 5735 if (iscsi_host_add(phba->shost, &phba->pcidev->dev))
5736 goto free_blkenbld;
5737
f457a46f
MC		 5738 if (beiscsi_setup_boot_info(phba))
5739 /*
5740 * log error but continue, because we may not be using
5741 * iscsi boot.
5742 */
99bc5d55
JSJ		 5743 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
5744 "BM_%d : Could not set up "
5745 "iSCSI boot info.\n");
f457a46f 5746
0e43895e 5747 beiscsi_create_def_ifaces(phba);
7a158003
JSJ		 5748 schedule_delayed_work(&phba->beiscsi_hw_check_task,
5749 msecs_to_jiffies(1000));
5750
99bc5d55
JSJ		 5751 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
5752 "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
6733b39a
JK		 5753 return 0;
5754
6733b39a
JK		 5755free_blkenbld:
5756 destroy_workqueue(phba->wq);
89f8b33c
JA		 5757 for (i = 0; i < phba->num_cpus; i++) {
5758 pbe_eq = &phwi_context->be_eq[i];
5759 blk_iopoll_disable(&pbe_eq->iopoll);
5760 }
6733b39a
JK		 5761free_twq:
5762 beiscsi_clean_port(phba);
5763 beiscsi_free_mem(phba);
5764free_port:
5765 pci_free_consistent(phba->pcidev,
5766 phba->ctrl.mbox_mem_alloced.size,
5767 phba->ctrl.mbox_mem_alloced.va,
5768 phba->ctrl.mbox_mem_alloced.dma);
5769 beiscsi_unmap_pci_function(phba);
5770hba_free:
238f6b72
JK		 5771 if (phba->msix_enabled)
5772 pci_disable_msix(phba->pcidev);
6733b39a
JK		 5773 pci_dev_put(phba->pcidev);
5774 iscsi_host_free(phba->shost);
2e7cee02 5775 pci_set_drvdata(pcidev, NULL);
6733b39a 5776disable_pci:
e307f3ac 5777 pci_release_regions(pcidev);
6733b39a
JK		 5778 pci_disable_device(pcidev);
5779 return ret;
5780}
5781
3567f36a
JK		 5782static struct pci_error_handlers beiscsi_eeh_handlers = {
5783 .error_detected = beiscsi_eeh_err_detected,
5784 .slot_reset = beiscsi_eeh_reset,
5785 .resume = beiscsi_eeh_resume,
5786};
5787
6733b39a
JK		 5788struct iscsi_transport beiscsi_iscsi_transport = {
5789 .owner = THIS_MODULE,
5790 .name = DRV_NAME,
9db0fb3a 5791 .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
6733b39a 5792 CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
6733b39a
JK		 5793 .create_session = beiscsi_session_create,
5794 .destroy_session = beiscsi_session_destroy,
5795 .create_conn = beiscsi_conn_create,
5796 .bind_conn = beiscsi_conn_bind,
5797 .destroy_conn = iscsi_conn_teardown,
3128c6c7 5798 .attr_is_visible = be2iscsi_attr_is_visible,
0e43895e
MC		 5799 .set_iface_param = be2iscsi_iface_set_param,
5800 .get_iface_param = be2iscsi_iface_get_param,
6733b39a 5801 .set_param = beiscsi_set_param,
c7f7fd5b 5802 .get_conn_param = iscsi_conn_get_param,
6733b39a
JK		 5803 .get_session_param = iscsi_session_get_param,
5804 .get_host_param = beiscsi_get_host_param,
5805 .start_conn = beiscsi_conn_start,
fa95d206 5806 .stop_conn = iscsi_conn_stop,
6733b39a
JK		 5807 .send_pdu = iscsi_conn_send_pdu,
5808 .xmit_task = beiscsi_task_xmit,
5809 .cleanup_task = beiscsi_cleanup_task,
5810 .alloc_pdu = beiscsi_alloc_pdu,
5811 .parse_pdu_itt = beiscsi_parse_pdu,
5812 .get_stats = beiscsi_conn_get_stats,
c7f7fd5b 5813 .get_ep_param = beiscsi_ep_get_param,
6733b39a
JK		 5814 .ep_connect = beiscsi_ep_connect,
5815 .ep_poll = beiscsi_ep_poll,
5816 .ep_disconnect = beiscsi_ep_disconnect,
5817 .session_recovery_timedout = iscsi_session_recovery_timedout,
ffce3e2e 5818 .bsg_request = beiscsi_bsg_request,
6733b39a
JK		 5819};
5820
5821static struct pci_driver beiscsi_pci_driver = {
5822 .name = DRV_NAME,
5823 .probe = beiscsi_dev_probe,
5824 .remove = beiscsi_remove,
25602c97 5825 .shutdown = beiscsi_shutdown,
3567f36a
JK		 5826 .id_table = beiscsi_pci_id_table,
5827 .err_handler = &beiscsi_eeh_handlers
6733b39a
JK		 5828};
5829
bfead3b2 5830
6733b39a
JK		 5831static int __init beiscsi_module_init(void)
5832{
5833 int ret;
5834
5835 beiscsi_scsi_transport =
5836 iscsi_register_transport(&beiscsi_iscsi_transport);
5837 if (!beiscsi_scsi_transport) {
99bc5d55
JSJ		 5838 printk(KERN_ERR
5839 "beiscsi_module_init - Unable to register beiscsi transport.\n");
f55a24f2 5840 return -ENOMEM;
6733b39a 5841 }
99bc5d55
JSJ		 5842 printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
5843 &beiscsi_iscsi_transport);
6733b39a
JK		 5844
5845 ret = pci_register_driver(&beiscsi_pci_driver);
5846 if (ret) {
99bc5d55
JSJ		 5847 printk(KERN_ERR
5848 "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
6733b39a
JK		 5849 goto unregister_iscsi_transport;
5850 }
5851 return 0;
5852
5853unregister_iscsi_transport:
5854 iscsi_unregister_transport(&beiscsi_iscsi_transport);
5855 return ret;
5856}
5857
5858static void __exit beiscsi_module_exit(void)
5859{
5860 pci_unregister_driver(&beiscsi_pci_driver);
5861 iscsi_unregister_transport(&beiscsi_iscsi_transport);
5862}
5863
5864module_init(beiscsi_module_init);
5865module_exit(beiscsi_module_exit);
Linux 6.x block layer and io_uring tree(s)