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Merge branches 'acpi-video', 'device-properties', 'pm-sleep' and 'pm-cpuidle'
[linux-2.6-block.git] / drivers / scsi / be2iscsi / be_cmds.c
CommitLineData
6733b39a 1/**
4627de93 2 * Copyright (C) 2005 - 2015 Avago Technologies
6733b39a
JK		 3 * All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License version 2
7 * as published by the Free Software Foundation. The full GNU General
8 * Public License is included in this distribution in the file called COPYING.
9 *
10 * Contact Information:
4627de93 11 * linux-drivers@avagotech.com
6733b39a 12 *
4627de93 13 * Avago Technologies
255fa9a3
JK		 14 * 3333 Susan Street
15 * Costa Mesa, CA 92626
6733b39a
JK		 16 */
17
2177199d
JSJ		 18#include <scsi/iscsi_proto.h>
19
4eea99d5 20#include "be_main.h"
6733b39a
JK		 21#include "be.h"
22#include "be_mgmt.h"
6733b39a 23
e9b91193
JK		 24int beiscsi_pci_soft_reset(struct beiscsi_hba *phba)
25{
26 u32 sreset;
27 u8 *pci_reset_offset = 0;
28 u8 *pci_online0_offset = 0;
29 u8 *pci_online1_offset = 0;
30 u32 pconline0 = 0;
31 u32 pconline1 = 0;
32 u32 i;
33
34 pci_reset_offset = (u8 *)phba->pci_va + BE2_SOFT_RESET;
35 pci_online0_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE0;
36 pci_online1_offset = (u8 *)phba->pci_va + BE2_PCI_ONLINE1;
37 sreset = readl((void *)pci_reset_offset);
38 sreset |= BE2_SET_RESET;
39 writel(sreset, (void *)pci_reset_offset);
40
41 i = 0;
42 while (sreset & BE2_SET_RESET) {
43 if (i > 64)
44 break;
45 msleep(100);
46 sreset = readl((void *)pci_reset_offset);
47 i++;
48 }
49
50 if (sreset & BE2_SET_RESET) {
99bc5d55
JSJ		 51 printk(KERN_ERR DRV_NAME
52 " Soft Reset did not deassert\n");
e9b91193
JK		 53 return -EIO;
54 }
55 pconline1 = BE2_MPU_IRAM_ONLINE;
56 writel(pconline0, (void *)pci_online0_offset);
57 writel(pconline1, (void *)pci_online1_offset);
58
1d8bc70a 59 sreset |= BE2_SET_RESET;
e9b91193
JK		 60 writel(sreset, (void *)pci_reset_offset);
61
62 i = 0;
63 while (sreset & BE2_SET_RESET) {
64 if (i > 64)
65 break;
66 msleep(1);
67 sreset = readl((void *)pci_reset_offset);
68 i++;
69 }
70 if (sreset & BE2_SET_RESET) {
99bc5d55
JSJ		 71 printk(KERN_ERR DRV_NAME
72 " MPU Online Soft Reset did not deassert\n");
e9b91193
JK		 73 return -EIO;
74 }
75 return 0;
76}
77
78int be_chk_reset_complete(struct beiscsi_hba *phba)
79{
80 unsigned int num_loop;
81 u8 *mpu_sem = 0;
82 u32 status;
83
84 num_loop = 1000;
85 mpu_sem = (u8 *)phba->csr_va + MPU_EP_SEMAPHORE;
86 msleep(5000);
87
88 while (num_loop) {
89 status = readl((void *)mpu_sem);
90
91 if ((status & 0x80000000) || (status & 0x0000FFFF) == 0xC000)
92 break;
93 msleep(60);
94 num_loop--;
95 }
96
97 if ((status & 0x80000000) || (!num_loop)) {
99bc5d55
JSJ		 98 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
99 "BC_%d : Failed in be_chk_reset_complete"
100 "status = 0x%x\n", status);
e9b91193
JK		 101 return -EIO;
102 }
103
104 return 0;
105}
106
756d29c8 107void be_mcc_notify(struct beiscsi_hba *phba)
bfead3b2
JK		 108{
109 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
110 u32 val = 0;
111
112 val |= mccq->id & DB_MCCQ_RING_ID_MASK;
113 val |= 1 << DB_MCCQ_NUM_POSTED_SHIFT;
114 iowrite32(val, phba->db_va + DB_MCCQ_OFFSET);
115}
116
756d29c8
JK		 117unsigned int alloc_mcc_tag(struct beiscsi_hba *phba)
118{
119 unsigned int tag = 0;
756d29c8 120
756d29c8
JK		 121 if (phba->ctrl.mcc_tag_available) {
122 tag = phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index];
123 phba->ctrl.mcc_tag[phba->ctrl.mcc_alloc_index] = 0;
124 phba->ctrl.mcc_numtag[tag] = 0;
756d29c8
JK		 125 }
126 if (tag) {
127 phba->ctrl.mcc_tag_available--;
128 if (phba->ctrl.mcc_alloc_index == (MAX_MCC_CMD - 1))
129 phba->ctrl.mcc_alloc_index = 0;
130 else
131 phba->ctrl.mcc_alloc_index++;
132 }
133 return tag;
134}
135
e175defe
JSJ		 136/*
137 * beiscsi_mccq_compl()- Wait for completion of MBX
138 * @phba: Driver private structure
139 * @tag: Tag for the MBX Command
140 * @wrb: the WRB used for the MBX Command
1957aa7f 141 * @mbx_cmd_mem: ptr to memory allocated for MBX Cmd
e175defe
JSJ		 142 *
143 * Waits for MBX completion with the passed TAG.
144 *
145 * return
146 * Success: 0
147 * Failure: Non-Zero
148 **/
149int beiscsi_mccq_compl(struct beiscsi_hba *phba,
150 uint32_t tag, struct be_mcc_wrb **wrb,
1957aa7f 151 struct be_dma_mem *mbx_cmd_mem)
e175defe
JSJ		 152{
153 int rc = 0;
154 uint32_t mcc_tag_response;
155 uint16_t status = 0, addl_status = 0, wrb_num = 0;
156 struct be_mcc_wrb *temp_wrb;
1957aa7f
JK		 157 struct be_cmd_req_hdr *mbx_hdr;
158 struct be_cmd_resp_hdr *mbx_resp_hdr;
e175defe
JSJ		 159 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
160
1f536d49
JK		 161 if (beiscsi_error(phba)) {
162 free_mcc_tag(&phba->ctrl, tag);
1957aa7f 163 return -EPERM;
1f536d49 164 }
7a158003 165
1957aa7f
JK		 166 /* Set MBX Tag state to Active */
167 spin_lock(&phba->ctrl.mbox_lock);
168 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_RUNNING;
169 spin_unlock(&phba->ctrl.mbox_lock);
170
e175defe
JSJ		 171 /* wait for the mccq completion */
172 rc = wait_event_interruptible_timeout(
173 phba->ctrl.mcc_wait[tag],
174 phba->ctrl.mcc_numtag[tag],
175 msecs_to_jiffies(
176 BEISCSI_HOST_MBX_TIMEOUT));
177
178 if (rc <= 0) {
1957aa7f
JK		 179 struct be_dma_mem *tag_mem;
180 /* Set MBX Tag state to timeout */
181 spin_lock(&phba->ctrl.mbox_lock);
182 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_TIMEOUT;
183 spin_unlock(&phba->ctrl.mbox_lock);
184
185 /* Store resource addr to be freed later */
186 tag_mem = &phba->ctrl.ptag_state[tag].tag_mem_state;
187 if (mbx_cmd_mem) {
188 tag_mem->size = mbx_cmd_mem->size;
189 tag_mem->va = mbx_cmd_mem->va;
190 tag_mem->dma = mbx_cmd_mem->dma;
191 } else
192 tag_mem->size = 0;
193
e175defe
JSJ		 194 beiscsi_log(phba, KERN_ERR,
195 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
196 BEISCSI_LOG_CONFIG,
197 "BC_%d : MBX Cmd Completion timed out\n");
1957aa7f
JK		 198 return -EBUSY;
199 } else {
e175defe 200 rc = 0;
1957aa7f
JK		 201 /* Set MBX Tag state to completed */
202 spin_lock(&phba->ctrl.mbox_lock);
203 phba->ctrl.ptag_state[tag].tag_state = MCC_TAG_STATE_COMPLETED;
204 spin_unlock(&phba->ctrl.mbox_lock);
205 }
e175defe
JSJ		 206
207 mcc_tag_response = phba->ctrl.mcc_numtag[tag];
208 status = (mcc_tag_response & CQE_STATUS_MASK);
209 addl_status = ((mcc_tag_response & CQE_STATUS_ADDL_MASK) >>
210 CQE_STATUS_ADDL_SHIFT);
211
1957aa7f
JK		 212 if (mbx_cmd_mem) {
213 mbx_hdr = (struct be_cmd_req_hdr *)mbx_cmd_mem->va;
e175defe
JSJ		 214 } else {
215 wrb_num = (mcc_tag_response & CQE_STATUS_WRB_MASK) >>
216 CQE_STATUS_WRB_SHIFT;
217 temp_wrb = (struct be_mcc_wrb *)queue_get_wrb(mccq, wrb_num);
1957aa7f 218 mbx_hdr = embedded_payload(temp_wrb);
e175defe
JSJ		 219
220 if (wrb)
221 *wrb = temp_wrb;
222 }
223
224 if (status || addl_status) {
1957aa7f 225 beiscsi_log(phba, KERN_WARNING,
e175defe
JSJ		 226 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
227 BEISCSI_LOG_CONFIG,
228 "BC_%d : MBX Cmd Failed for "
229 "Subsys : %d Opcode : %d with "
230 "Status : %d and Extd_Status : %d\n",
1957aa7f
JK		 231 mbx_hdr->subsystem,
232 mbx_hdr->opcode,
e175defe 233 status, addl_status);
a8081e34
JK		 234
235 if (status == MCC_STATUS_INSUFFICIENT_BUFFER) {
1957aa7f 236 mbx_resp_hdr = (struct be_cmd_resp_hdr *) mbx_hdr;
1f536d49
JK		 237 beiscsi_log(phba, KERN_WARNING,
238 BEISCSI_LOG_INIT | BEISCSI_LOG_EH |
239 BEISCSI_LOG_CONFIG,
d939be3a 240 "BC_%d : Insufficient Buffer Error "
1f536d49 241 "Resp_Len : %d Actual_Resp_Len : %d\n",
1957aa7f
JK		 242 mbx_resp_hdr->response_length,
243 mbx_resp_hdr->actual_resp_len);
1f536d49
JK		 244
245 rc = -EAGAIN;
246 goto release_mcc_tag;
a8081e34 247 }
1f536d49 248 rc = -EIO;
e175defe
JSJ		 249 }
250
251release_mcc_tag:
252 /* Release the MCC entry */
253 free_mcc_tag(&phba->ctrl, tag);
254
255 return rc;
256}
257
756d29c8
JK		 258void free_mcc_tag(struct be_ctrl_info *ctrl, unsigned int tag)
259{
260 spin_lock(&ctrl->mbox_lock);
261 tag = tag & 0x000000FF;
262 ctrl->mcc_tag[ctrl->mcc_free_index] = tag;
263 if (ctrl->mcc_free_index == (MAX_MCC_CMD - 1))
264 ctrl->mcc_free_index = 0;
265 else
266 ctrl->mcc_free_index++;
267 ctrl->mcc_tag_available++;
268 spin_unlock(&ctrl->mbox_lock);
269}
270
271bool is_link_state_evt(u32 trailer)
272{
273 return (((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
274 ASYNC_TRAILER_EVENT_CODE_MASK) ==
275 ASYNC_EVENT_CODE_LINK_STATE);
276}
277
a3d313ea
JK		 278static bool is_iscsi_evt(u32 trailer)
279{
280 return ((trailer >> ASYNC_TRAILER_EVENT_CODE_SHIFT) &
281 ASYNC_TRAILER_EVENT_CODE_MASK) ==
282 ASYNC_EVENT_CODE_ISCSI;
283}
284
285static int iscsi_evt_type(u32 trailer)
286{
287 return (trailer >> ASYNC_TRAILER_EVENT_TYPE_SHIFT) &
288 ASYNC_TRAILER_EVENT_TYPE_MASK;
289}
290
6733b39a
JK		 291static inline bool be_mcc_compl_is_new(struct be_mcc_compl *compl)
292{
293 if (compl->flags != 0) {
294 compl->flags = le32_to_cpu(compl->flags);
295 WARN_ON((compl->flags & CQE_FLAGS_VALID_MASK) == 0);
296 return true;
297 } else
298 return false;
299}
300
301static inline void be_mcc_compl_use(struct be_mcc_compl *compl)
302{
303 compl->flags = 0;
304}
305
e175defe
JSJ		 306/*
307 * be_mcc_compl_process()- Check the MBX comapletion status
308 * @ctrl: Function specific MBX data structure
309 * @compl: Completion status of MBX Command
310 *
311 * Check for the MBX completion status when BMBX method used
312 *
313 * return
314 * Success: Zero
315 * Failure: Non-Zero
316 **/
6733b39a
JK		 317static int be_mcc_compl_process(struct be_ctrl_info *ctrl,
318 struct be_mcc_compl *compl)
319{
320 u16 compl_status, extd_status;
e175defe 321 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
99bc5d55 322 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
e175defe 323 struct be_cmd_req_hdr *hdr = embedded_payload(wrb);
a8081e34 324 struct be_cmd_resp_hdr *resp_hdr;
6733b39a
JK		 325
326 be_dws_le_to_cpu(compl, 4);
327
328 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
329 CQE_STATUS_COMPL_MASK;
330 if (compl_status != MCC_STATUS_SUCCESS) {
331 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
332 CQE_STATUS_EXTD_MASK;
99bc5d55
JSJ		 333
334 beiscsi_log(phba, KERN_ERR,
335 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
e175defe
JSJ		 336 "BC_%d : error in cmd completion: "
337 "Subsystem : %d Opcode : %d "
338 "status(compl/extd)=%d/%d\n",
339 hdr->subsystem, hdr->opcode,
99bc5d55
JSJ		 340 compl_status, extd_status);
341
a8081e34
JK		 342 if (compl_status == MCC_STATUS_INSUFFICIENT_BUFFER) {
343 resp_hdr = (struct be_cmd_resp_hdr *) hdr;
344 if (resp_hdr->response_length)
345 return 0;
346 }
d3ad2bb3 347 return -EBUSY;
6733b39a
JK		 348 }
349 return 0;
350}
351
756d29c8
JK		 352int be_mcc_compl_process_isr(struct be_ctrl_info *ctrl,
353 struct be_mcc_compl *compl)
6733b39a 354{
1957aa7f 355 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
756d29c8
JK		 356 u16 compl_status, extd_status;
357 unsigned short tag;
358
359 be_dws_le_to_cpu(compl, 4);
360
361 compl_status = (compl->status >> CQE_STATUS_COMPL_SHIFT) &
362 CQE_STATUS_COMPL_MASK;
363 /* The ctrl.mcc_numtag[tag] is filled with
364 * [31] = valid, [30:24] = Rsvd, [23:16] = wrb, [15:8] = extd_status,
365 * [7:0] = compl_status
366 */
367 tag = (compl->tag0 & 0x000000FF);
368 extd_status = (compl->status >> CQE_STATUS_EXTD_SHIFT) &
369 CQE_STATUS_EXTD_MASK;
370
371 ctrl->mcc_numtag[tag] = 0x80000000;
372 ctrl->mcc_numtag[tag] |= (compl->tag0 & 0x00FF0000);
373 ctrl->mcc_numtag[tag] |= (extd_status & 0x000000FF) << 8;
374 ctrl->mcc_numtag[tag] |= (compl_status & 0x000000FF);
1957aa7f
JK		 375
376 if (ctrl->ptag_state[tag].tag_state == MCC_TAG_STATE_RUNNING) {
377 wake_up_interruptible(&ctrl->mcc_wait[tag]);
378 } else if (ctrl->ptag_state[tag].tag_state == MCC_TAG_STATE_TIMEOUT) {
379 struct be_dma_mem *tag_mem;
380 tag_mem = &ctrl->ptag_state[tag].tag_mem_state;
381
382 beiscsi_log(phba, KERN_WARNING,
383 BEISCSI_LOG_MBOX | BEISCSI_LOG_INIT |
384 BEISCSI_LOG_CONFIG,
385 "BC_%d : MBX Completion for timeout Command "
386 "from FW\n");
387 /* Check if memory needs to be freed */
388 if (tag_mem->size)
389 pci_free_consistent(ctrl->pdev, tag_mem->size,
390 tag_mem->va, tag_mem->dma);
391
392 /* Change tag state */
393 spin_lock(&phba->ctrl.mbox_lock);
394 ctrl->ptag_state[tag].tag_state = MCC_TAG_STATE_COMPLETED;
395 spin_unlock(&phba->ctrl.mbox_lock);
396
397 /* Free MCC Tag */
398 free_mcc_tag(ctrl, tag);
399 }
400
756d29c8 401 return 0;
bfead3b2
JK		 402}
403
404static struct be_mcc_compl *be_mcc_compl_get(struct beiscsi_hba *phba)
405{
406 struct be_queue_info *mcc_cq = &phba->ctrl.mcc_obj.cq;
407 struct be_mcc_compl *compl = queue_tail_node(mcc_cq);
408
409 if (be_mcc_compl_is_new(compl)) {
410 queue_tail_inc(mcc_cq);
411 return compl;
412 }
413 return NULL;
414}
415
9343be74
JK		 416/**
417 * be2iscsi_fail_session(): Closing session with appropriate error
418 * @cls_session: ptr to session
419 *
420 * Depending on adapter state appropriate error flag is passed.
421 **/
422void be2iscsi_fail_session(struct iscsi_cls_session *cls_session)
bfead3b2 423{
9343be74
JK		 424 struct Scsi_Host *shost = iscsi_session_to_shost(cls_session);
425 struct beiscsi_hba *phba = iscsi_host_priv(shost);
426 uint32_t iscsi_err_flag;
427
428 if (phba->state & BE_ADAPTER_STATE_SHUTDOWN)
429 iscsi_err_flag = ISCSI_ERR_INVALID_HOST;
430 else
431 iscsi_err_flag = ISCSI_ERR_CONN_FAILED;
432
bfead3b2
JK		 433 iscsi_session_failure(cls_session->dd_data, ISCSI_ERR_CONN_FAILED);
434}
435
756d29c8 436void beiscsi_async_link_state_process(struct beiscsi_hba *phba,
bfead3b2
JK		 437 struct be_async_event_link_state *evt)
438{
6ea9b3b0
JK		 439 if ((evt->port_link_status == ASYNC_EVENT_LINK_DOWN) ||
440 ((evt->port_link_status & ASYNC_EVENT_LOGICAL) &&
441 (evt->port_fault != BEISCSI_PHY_LINK_FAULT_NONE))) {
442 phba->state = BE_ADAPTER_LINK_DOWN;
443
99bc5d55
JSJ		 444 beiscsi_log(phba, KERN_ERR,
445 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT,
6ea9b3b0 446 "BC_%d : Link Down on Port %d\n",
99bc5d55
JSJ		 447 evt->physical_port);
448
da7408c8
JK		 449 iscsi_host_for_each_session(phba->shost,
450 be2iscsi_fail_session);
6ea9b3b0
JK		 451 } else if ((evt->port_link_status & ASYNC_EVENT_LINK_UP) ||
452 ((evt->port_link_status & ASYNC_EVENT_LOGICAL) &&
453 (evt->port_fault == BEISCSI_PHY_LINK_FAULT_NONE))) {
a3d313ea 454 phba->state = BE_ADAPTER_LINK_UP | BE_ADAPTER_CHECK_BOOT;
6ea9b3b0 455
99bc5d55
JSJ		 456 beiscsi_log(phba, KERN_ERR,
457 BEISCSI_LOG_CONFIG | BEISCSI_LOG_INIT,
6ea9b3b0 458 "BC_%d : Link UP on Port %d\n",
99bc5d55 459 evt->physical_port);
bfead3b2 460 }
6733b39a
JK		 461}
462
35e66019 463int beiscsi_process_mcc(struct beiscsi_hba *phba)
bfead3b2
JK		 464{
465 struct be_mcc_compl *compl;
466 int num = 0, status = 0;
467 struct be_ctrl_info *ctrl = &phba->ctrl;
468
469 spin_lock_bh(&phba->ctrl.mcc_cq_lock);
470 while ((compl = be_mcc_compl_get(phba))) {
471 if (compl->flags & CQE_FLAGS_ASYNC_MASK) {
472 /* Interpret flags as an async trailer */
78b9fb6d
JK		 473 if (is_link_state_evt(compl->flags))
474 /* Interpret compl as a async link evt */
475 beiscsi_async_link_state_process(phba,
476 (struct be_async_event_link_state *) compl);
a3d313ea
JK		 477 else if (is_iscsi_evt(compl->flags)) {
478 switch (iscsi_evt_type(compl->flags)) {
479 case ASYNC_EVENT_NEW_ISCSI_TGT_DISC:
480 case ASYNC_EVENT_NEW_ISCSI_CONN:
481 case ASYNC_EVENT_NEW_TCP_CONN:
482 phba->state |= BE_ADAPTER_CHECK_BOOT;
483 beiscsi_log(phba, KERN_ERR,
484 BEISCSI_LOG_CONFIG |
485 BEISCSI_LOG_MBOX,
486 "BC_%d : Async iscsi Event,"
487 " flags handled = 0x%08x\n",
488 compl->flags);
489 break;
490 default:
491 beiscsi_log(phba, KERN_ERR,
492 BEISCSI_LOG_CONFIG |
493 BEISCSI_LOG_MBOX,
494 "BC_%d : Unsupported Async"
495 " Event, flags = 0x%08x\n",
496 compl->flags);
497 }
498 } else
99bc5d55
JSJ		 499 beiscsi_log(phba, KERN_ERR,
500 BEISCSI_LOG_CONFIG |
501 BEISCSI_LOG_MBOX,
502 "BC_%d : Unsupported Async Event, flags"
503 " = 0x%08x\n", compl->flags);
bfead3b2 504
bfead3b2
JK		 505 } else if (compl->flags & CQE_FLAGS_COMPLETED_MASK) {
506 status = be_mcc_compl_process(ctrl, compl);
507 atomic_dec(&phba->ctrl.mcc_obj.q.used);
508 }
509 be_mcc_compl_use(compl);
510 num++;
511 }
512
513 if (num)
e08b3c8b 514 hwi_ring_cq_db(phba, phba->ctrl.mcc_obj.cq.id, num, 1, 0);
bfead3b2
JK		 515
516 spin_unlock_bh(&phba->ctrl.mcc_cq_lock);
517 return status;
518}
519
e175defe
JSJ		 520/*
521 * be_mcc_wait_compl()- Wait for MBX completion
522 * @phba: driver private structure
523 *
524 * Wait till no more pending mcc requests are present
525 *
526 * return
527 * Success: 0
528 * Failure: Non-Zero
529 *
530 **/
bfead3b2
JK		 531static int be_mcc_wait_compl(struct beiscsi_hba *phba)
532{
bfead3b2
JK		 533 int i, status;
534 for (i = 0; i < mcc_timeout; i++) {
7a158003 535 if (beiscsi_error(phba))
e175defe
JSJ		 536 return -EIO;
537
35e66019 538 status = beiscsi_process_mcc(phba);
bfead3b2
JK		 539 if (status)
540 return status;
541
542 if (atomic_read(&phba->ctrl.mcc_obj.q.used) == 0)
543 break;
544 udelay(100);
545 }
546 if (i == mcc_timeout) {
99bc5d55
JSJ		 547 beiscsi_log(phba, KERN_ERR,
548 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
e175defe
JSJ		 549 "BC_%d : FW Timed Out\n");
550 phba->fw_timeout = true;
7a158003 551 beiscsi_ue_detect(phba);
d3ad2bb3 552 return -EBUSY;
bfead3b2
JK		 553 }
554 return 0;
555}
556
e175defe
JSJ		 557/*
558 * be_mcc_notify_wait()- Notify and wait for Compl
559 * @phba: driver private structure
560 *
561 * Notify MCC requests and wait for completion
562 *
563 * return
564 * Success: 0
565 * Failure: Non-Zero
566 **/
bfead3b2
JK		 567int be_mcc_notify_wait(struct beiscsi_hba *phba)
568{
569 be_mcc_notify(phba);
570 return be_mcc_wait_compl(phba);
6733b39a
JK		 571}
572
e175defe
JSJ		 573/*
574 * be_mbox_db_ready_wait()- Check ready status
575 * @ctrl: Function specific MBX data structure
576 *
577 * Check for the ready status of FW to send BMBX
578 * commands to adapter.
579 *
580 * return
581 * Success: 0
582 * Failure: Non-Zero
583 **/
6733b39a
JK		 584static int be_mbox_db_ready_wait(struct be_ctrl_info *ctrl)
585{
92665a66 586#define BEISCSI_MBX_RDY_BIT_TIMEOUT 4000 /* 4sec */
6733b39a 587 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
e175defe 588 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
92665a66
JK		 589 unsigned long timeout;
590 bool read_flag = false;
591 int ret = 0, i;
6733b39a 592 u32 ready;
92665a66 593 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(rdybit_check_q);
6733b39a 594
92665a66
JK		 595 if (beiscsi_error(phba))
596 return -EIO;
7a158003 597
92665a66 598 timeout = jiffies + (HZ * 110);
e175defe 599
92665a66
JK		 600 do {
601 for (i = 0; i < BEISCSI_MBX_RDY_BIT_TIMEOUT; i++) {
602 ready = ioread32(db) & MPU_MAILBOX_DB_RDY_MASK;
603 if (ready) {
604 read_flag = true;
605 break;
606 }
607 mdelay(1);
608 }
6733b39a 609
92665a66
JK		 610 if (!read_flag) {
611 wait_event_timeout(rdybit_check_q,
612 (read_flag != true),
613 HZ * 5);
614 }
615 } while ((time_before(jiffies, timeout)) && !read_flag);
616
617 if (!read_flag) {
618 beiscsi_log(phba, KERN_ERR,
619 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
620 "BC_%d : FW Timed Out\n");
e175defe 621 phba->fw_timeout = true;
7a158003 622 beiscsi_ue_detect(phba);
92665a66
JK		 623 ret = -EBUSY;
624 }
6733b39a 625
92665a66 626 return ret;
6733b39a
JK		 627}
628
e175defe
JSJ		 629/*
630 * be_mbox_notify: Notify adapter of new BMBX command
631 * @ctrl: Function specific MBX data structure
632 *
633 * Ring doorbell to inform adapter of a BMBX command
634 * to process
635 *
636 * return
637 * Success: 0
638 * Failure: Non-Zero
639 **/
6733b39a
JK		 640int be_mbox_notify(struct be_ctrl_info *ctrl)
641{
642 int status;
643 u32 val = 0;
644 void __iomem *db = ctrl->db + MPU_MAILBOX_DB_OFFSET;
645 struct be_dma_mem *mbox_mem = &ctrl->mbox_mem;
646 struct be_mcc_mailbox *mbox = mbox_mem->va;
647 struct be_mcc_compl *compl = &mbox->compl;
99bc5d55 648 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a 649
1e234bbb
JK		 650 status = be_mbox_db_ready_wait(ctrl);
651 if (status)
652 return status;
653
6733b39a
JK		 654 val &= ~MPU_MAILBOX_DB_RDY_MASK;
655 val |= MPU_MAILBOX_DB_HI_MASK;
656 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
657 iowrite32(val, db);
658
659 status = be_mbox_db_ready_wait(ctrl);
e175defe 660 if (status)
6733b39a 661 return status;
e175defe 662
6733b39a
JK		 663 val = 0;
664 val &= ~MPU_MAILBOX_DB_RDY_MASK;
665 val &= ~MPU_MAILBOX_DB_HI_MASK;
666 val |= (u32) (mbox_mem->dma >> 4) << 2;
667 iowrite32(val, db);
668
669 status = be_mbox_db_ready_wait(ctrl);
e175defe 670 if (status)
6733b39a 671 return status;
e175defe 672
6733b39a
JK		 673 if (be_mcc_compl_is_new(compl)) {
674 status = be_mcc_compl_process(ctrl, &mbox->compl);
675 be_mcc_compl_use(compl);
676 if (status) {
99bc5d55
JSJ		 677 beiscsi_log(phba, KERN_ERR,
678 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
679 "BC_%d : After be_mcc_compl_process\n");
680
6733b39a
JK		 681 return status;
682 }
683 } else {
99bc5d55
JSJ		 684 beiscsi_log(phba, KERN_ERR,
685 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
686 "BC_%d : Invalid Mailbox Completion\n");
687
d3ad2bb3 688 return -EBUSY;
6733b39a
JK		 689 }
690 return 0;
691}
692
bfead3b2
JK		 693/*
694 * Insert the mailbox address into the doorbell in two steps
695 * Polls on the mbox doorbell till a command completion (or a timeout) occurs
696 */
697static int be_mbox_notify_wait(struct beiscsi_hba *phba)
698{
699 int status;
700 u32 val = 0;
701 void __iomem *db = phba->ctrl.db + MPU_MAILBOX_DB_OFFSET;
702 struct be_dma_mem *mbox_mem = &phba->ctrl.mbox_mem;
703 struct be_mcc_mailbox *mbox = mbox_mem->va;
704 struct be_mcc_compl *compl = &mbox->compl;
705 struct be_ctrl_info *ctrl = &phba->ctrl;
706
1e234bbb
JK		 707 status = be_mbox_db_ready_wait(ctrl);
708 if (status)
709 return status;
710
bfead3b2
JK		 711 val |= MPU_MAILBOX_DB_HI_MASK;
712 /* at bits 2 - 31 place mbox dma addr msb bits 34 - 63 */
713 val |= (upper_32_bits(mbox_mem->dma) >> 2) << 2;
714 iowrite32(val, db);
715
716 /* wait for ready to be set */
717 status = be_mbox_db_ready_wait(ctrl);
718 if (status != 0)
719 return status;
720
721 val = 0;
722 /* at bits 2 - 31 place mbox dma addr lsb bits 4 - 33 */
723 val |= (u32)(mbox_mem->dma >> 4) << 2;
724 iowrite32(val, db);
725
726 status = be_mbox_db_ready_wait(ctrl);
727 if (status != 0)
728 return status;
729
730 /* A cq entry has been made now */
731 if (be_mcc_compl_is_new(compl)) {
732 status = be_mcc_compl_process(ctrl, &mbox->compl);
733 be_mcc_compl_use(compl);
734 if (status)
735 return status;
736 } else {
99bc5d55
JSJ		 737 beiscsi_log(phba, KERN_ERR,
738 BEISCSI_LOG_CONFIG | BEISCSI_LOG_MBOX,
739 "BC_%d : invalid mailbox completion\n");
740
d3ad2bb3 741 return -EBUSY;
bfead3b2
JK		 742 }
743 return 0;
744}
745
6733b39a
JK		 746void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
747 bool embedded, u8 sge_cnt)
748{
749 if (embedded)
750 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
751 else
752 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
753 MCC_WRB_SGE_CNT_SHIFT;
754 wrb->payload_length = payload_len;
755 be_dws_cpu_to_le(wrb, 8);
756}
757
758void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
759 u8 subsystem, u8 opcode, int cmd_len)
760{
761 req_hdr->opcode = opcode;
762 req_hdr->subsystem = subsystem;
763 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
e175defe 764 req_hdr->timeout = BEISCSI_FW_MBX_TIMEOUT;
6733b39a
JK		 765}
766
767static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
768 struct be_dma_mem *mem)
769{
770 int i, buf_pages;
771 u64 dma = (u64) mem->dma;
772
773 buf_pages = min(PAGES_4K_SPANNED(mem->va, mem->size), max_pages);
774 for (i = 0; i < buf_pages; i++) {
775 pages[i].lo = cpu_to_le32(dma & 0xFFFFFFFF);
776 pages[i].hi = cpu_to_le32(upper_32_bits(dma));
777 dma += PAGE_SIZE_4K;
778 }
779}
780
781static u32 eq_delay_to_mult(u32 usec_delay)
782{
783#define MAX_INTR_RATE 651042
784 const u32 round = 10;
785 u32 multiplier;
786
787 if (usec_delay == 0)
788 multiplier = 0;
789 else {
790 u32 interrupt_rate = 1000000 / usec_delay;
791 if (interrupt_rate == 0)
792 multiplier = 1023;
793 else {
794 multiplier = (MAX_INTR_RATE - interrupt_rate) * round;
795 multiplier /= interrupt_rate;
796 multiplier = (multiplier + round / 2) / round;
797 multiplier = min(multiplier, (u32) 1023);
798 }
799 }
800 return multiplier;
801}
802
803struct be_mcc_wrb *wrb_from_mbox(struct be_dma_mem *mbox_mem)
804{
805 return &((struct be_mcc_mailbox *)(mbox_mem->va))->wrb;
806}
807
bfead3b2
JK		 808struct be_mcc_wrb *wrb_from_mccq(struct beiscsi_hba *phba)
809{
810 struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
811 struct be_mcc_wrb *wrb;
812
e074d20f 813 WARN_ON(atomic_read(&mccq->used) >= mccq->len);
bfead3b2 814 wrb = queue_head_node(mccq);
756d29c8
JK		 815 memset(wrb, 0, sizeof(*wrb));
816 wrb->tag0 = (mccq->head & 0x000000FF) << 16;
bfead3b2
JK		 817 queue_head_inc(mccq);
818 atomic_inc(&mccq->used);
bfead3b2
JK		 819 return wrb;
820}
821
822
6733b39a
JK		 823int beiscsi_cmd_eq_create(struct be_ctrl_info *ctrl,
824 struct be_queue_info *eq, int eq_delay)
825{
826 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
827 struct be_cmd_req_eq_create *req = embedded_payload(wrb);
828 struct be_cmd_resp_eq_create *resp = embedded_payload(wrb);
829 struct be_dma_mem *q_mem = &eq->dma_mem;
830 int status;
831
832 spin_lock(&ctrl->mbox_lock);
833 memset(wrb, 0, sizeof(*wrb));
834
835 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
836
837 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
838 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
839
840 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
841
842 AMAP_SET_BITS(struct amap_eq_context, func, req->context,
843 PCI_FUNC(ctrl->pdev->devfn));
844 AMAP_SET_BITS(struct amap_eq_context, valid, req->context, 1);
845 AMAP_SET_BITS(struct amap_eq_context, size, req->context, 0);
846 AMAP_SET_BITS(struct amap_eq_context, count, req->context,
847 __ilog2_u32(eq->len / 256));
848 AMAP_SET_BITS(struct amap_eq_context, delaymult, req->context,
849 eq_delay_to_mult(eq_delay));
850 be_dws_cpu_to_le(req->context, sizeof(req->context));
851
852 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
853
854 status = be_mbox_notify(ctrl);
855 if (!status) {
856 eq->id = le16_to_cpu(resp->eq_id);
857 eq->created = true;
858 }
859 spin_unlock(&ctrl->mbox_lock);
860 return status;
861}
862
0283fbb1
JK		 863/**
864 * be_cmd_fw_initialize()- Initialize FW
865 * @ctrl: Pointer to function control structure
866 *
867 * Send FW initialize pattern for the function.
868 *
869 * return
870 * Success: 0
871 * Failure: Non-Zero value
872 **/
6733b39a
JK		 873int be_cmd_fw_initialize(struct be_ctrl_info *ctrl)
874{
875 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
99bc5d55 876 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 877 int status;
878 u8 *endian_check;
879
880 spin_lock(&ctrl->mbox_lock);
881 memset(wrb, 0, sizeof(*wrb));
882
883 endian_check = (u8 *) wrb;
884 *endian_check++ = 0xFF;
885 *endian_check++ = 0x12;
886 *endian_check++ = 0x34;
887 *endian_check++ = 0xFF;
888 *endian_check++ = 0xFF;
889 *endian_check++ = 0x56;
890 *endian_check++ = 0x78;
891 *endian_check++ = 0xFF;
892 be_dws_cpu_to_le(wrb, sizeof(*wrb));
893
894 status = be_mbox_notify(ctrl);
895 if (status)
99bc5d55
JSJ		 896 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
897 "BC_%d : be_cmd_fw_initialize Failed\n");
6733b39a
JK		 898
899 spin_unlock(&ctrl->mbox_lock);
900 return status;
901}
902
0283fbb1
JK		 903/**
904 * be_cmd_fw_uninit()- Uinitialize FW
905 * @ctrl: Pointer to function control structure
906 *
907 * Send FW uninitialize pattern for the function
908 *
909 * return
910 * Success: 0
911 * Failure: Non-Zero value
912 **/
913int be_cmd_fw_uninit(struct be_ctrl_info *ctrl)
914{
915 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
916 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
917 int status;
918 u8 *endian_check;
919
920 spin_lock(&ctrl->mbox_lock);
921 memset(wrb, 0, sizeof(*wrb));
922
923 endian_check = (u8 *) wrb;
924 *endian_check++ = 0xFF;
925 *endian_check++ = 0xAA;
926 *endian_check++ = 0xBB;
927 *endian_check++ = 0xFF;
928 *endian_check++ = 0xFF;
929 *endian_check++ = 0xCC;
930 *endian_check++ = 0xDD;
931 *endian_check = 0xFF;
932
933 be_dws_cpu_to_le(wrb, sizeof(*wrb));
934
935 status = be_mbox_notify(ctrl);
936 if (status)
937 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
938 "BC_%d : be_cmd_fw_uninit Failed\n");
939
940 spin_unlock(&ctrl->mbox_lock);
941 return status;
942}
943
6733b39a
JK		 944int beiscsi_cmd_cq_create(struct be_ctrl_info *ctrl,
945 struct be_queue_info *cq, struct be_queue_info *eq,
946 bool sol_evts, bool no_delay, int coalesce_wm)
947{
948 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
949 struct be_cmd_req_cq_create *req = embedded_payload(wrb);
950 struct be_cmd_resp_cq_create *resp = embedded_payload(wrb);
99bc5d55 951 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 952 struct be_dma_mem *q_mem = &cq->dma_mem;
953 void *ctxt = &req->context;
954 int status;
955
956 spin_lock(&ctrl->mbox_lock);
957 memset(wrb, 0, sizeof(*wrb));
958
959 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
960
961 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
962 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
6733b39a
JK		 963
964 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
2c9dfd36 965 if (is_chip_be2_be3r(phba)) {
eaae5267
JSJ		 966 AMAP_SET_BITS(struct amap_cq_context, coalescwm,
967 ctxt, coalesce_wm);
968 AMAP_SET_BITS(struct amap_cq_context, nodelay, ctxt, no_delay);
969 AMAP_SET_BITS(struct amap_cq_context, count, ctxt,
970 __ilog2_u32(cq->len / 256));
971 AMAP_SET_BITS(struct amap_cq_context, valid, ctxt, 1);
972 AMAP_SET_BITS(struct amap_cq_context, solevent, ctxt, sol_evts);
973 AMAP_SET_BITS(struct amap_cq_context, eventable, ctxt, 1);
974 AMAP_SET_BITS(struct amap_cq_context, eqid, ctxt, eq->id);
975 AMAP_SET_BITS(struct amap_cq_context, armed, ctxt, 1);
976 AMAP_SET_BITS(struct amap_cq_context, func, ctxt,
977 PCI_FUNC(ctrl->pdev->devfn));
2c9dfd36
JK		 978 } else {
979 req->hdr.version = MBX_CMD_VER2;
980 req->page_size = 1;
981 AMAP_SET_BITS(struct amap_cq_context_v2, coalescwm,
982 ctxt, coalesce_wm);
983 AMAP_SET_BITS(struct amap_cq_context_v2, nodelay,
984 ctxt, no_delay);
985 AMAP_SET_BITS(struct amap_cq_context_v2, count, ctxt,
986 __ilog2_u32(cq->len / 256));
987 AMAP_SET_BITS(struct amap_cq_context_v2, valid, ctxt, 1);
988 AMAP_SET_BITS(struct amap_cq_context_v2, eventable, ctxt, 1);
989 AMAP_SET_BITS(struct amap_cq_context_v2, eqid, ctxt, eq->id);
990 AMAP_SET_BITS(struct amap_cq_context_v2, armed, ctxt, 1);
eaae5267 991 }
6733b39a 992
6733b39a
JK		 993 be_dws_cpu_to_le(ctxt, sizeof(req->context));
994
995 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
996
997 status = be_mbox_notify(ctrl);
998 if (!status) {
999 cq->id = le16_to_cpu(resp->cq_id);
1000 cq->created = true;
1001 } else
99bc5d55
JSJ		 1002 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1003 "BC_%d : In be_cmd_cq_create, status=ox%08x\n",
1004 status);
1005
6733b39a
JK		 1006 spin_unlock(&ctrl->mbox_lock);
1007
1008 return status;
1009}
1010
1011static u32 be_encoded_q_len(int q_len)
1012{
1013 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
1014 if (len_encoded == 16)
1015 len_encoded = 0;
1016 return len_encoded;
1017}
bfead3b2 1018
35e66019 1019int beiscsi_cmd_mccq_create(struct beiscsi_hba *phba,
bfead3b2
JK		 1020 struct be_queue_info *mccq,
1021 struct be_queue_info *cq)
1022{
1023 struct be_mcc_wrb *wrb;
1024 struct be_cmd_req_mcc_create *req;
1025 struct be_dma_mem *q_mem = &mccq->dma_mem;
1026 struct be_ctrl_info *ctrl;
1027 void *ctxt;
1028 int status;
1029
1030 spin_lock(&phba->ctrl.mbox_lock);
1031 ctrl = &phba->ctrl;
1032 wrb = wrb_from_mbox(&ctrl->mbox_mem);
37609766 1033 memset(wrb, 0, sizeof(*wrb));
bfead3b2
JK		 1034 req = embedded_payload(wrb);
1035 ctxt = &req->context;
1036
1037 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1038
1039 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1040 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
1041
1042 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1043
1044 AMAP_SET_BITS(struct amap_mcc_context, fid, ctxt,
1045 PCI_FUNC(phba->pcidev->devfn));
1046 AMAP_SET_BITS(struct amap_mcc_context, valid, ctxt, 1);
1047 AMAP_SET_BITS(struct amap_mcc_context, ring_size, ctxt,
1048 be_encoded_q_len(mccq->len));
1049 AMAP_SET_BITS(struct amap_mcc_context, cq_id, ctxt, cq->id);
1050
1051 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1052
1053 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1054
1055 status = be_mbox_notify_wait(phba);
1056 if (!status) {
1057 struct be_cmd_resp_mcc_create *resp = embedded_payload(wrb);
1058 mccq->id = le16_to_cpu(resp->id);
1059 mccq->created = true;
1060 }
1061 spin_unlock(&phba->ctrl.mbox_lock);
1062
1063 return status;
1064}
1065
6733b39a
JK		 1066int beiscsi_cmd_q_destroy(struct be_ctrl_info *ctrl, struct be_queue_info *q,
1067 int queue_type)
1068{
1069 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1070 struct be_cmd_req_q_destroy *req = embedded_payload(wrb);
99bc5d55 1071 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 1072 u8 subsys = 0, opcode = 0;
1073 int status;
1074
99bc5d55
JSJ		 1075 beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
1076 "BC_%d : In beiscsi_cmd_q_destroy "
1077 "queue_type : %d\n", queue_type);
1078
6733b39a
JK		 1079 spin_lock(&ctrl->mbox_lock);
1080 memset(wrb, 0, sizeof(*wrb));
1081 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1082
1083 switch (queue_type) {
1084 case QTYPE_EQ:
1085 subsys = CMD_SUBSYSTEM_COMMON;
1086 opcode = OPCODE_COMMON_EQ_DESTROY;
1087 break;
1088 case QTYPE_CQ:
1089 subsys = CMD_SUBSYSTEM_COMMON;
1090 opcode = OPCODE_COMMON_CQ_DESTROY;
1091 break;
bfead3b2
JK		 1092 case QTYPE_MCCQ:
1093 subsys = CMD_SUBSYSTEM_COMMON;
1094 opcode = OPCODE_COMMON_MCC_DESTROY;
1095 break;
6733b39a
JK		 1096 case QTYPE_WRBQ:
1097 subsys = CMD_SUBSYSTEM_ISCSI;
1098 opcode = OPCODE_COMMON_ISCSI_WRBQ_DESTROY;
1099 break;
1100 case QTYPE_DPDUQ:
1101 subsys = CMD_SUBSYSTEM_ISCSI;
1102 opcode = OPCODE_COMMON_ISCSI_DEFQ_DESTROY;
1103 break;
1104 case QTYPE_SGL:
1105 subsys = CMD_SUBSYSTEM_ISCSI;
1106 opcode = OPCODE_COMMON_ISCSI_CFG_REMOVE_SGL_PAGES;
1107 break;
1108 default:
1109 spin_unlock(&ctrl->mbox_lock);
1110 BUG();
d3ad2bb3 1111 return -ENXIO;
6733b39a
JK		 1112 }
1113 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
1114 if (queue_type != QTYPE_SGL)
1115 req->id = cpu_to_le16(q->id);
1116
1117 status = be_mbox_notify(ctrl);
1118
1119 spin_unlock(&ctrl->mbox_lock);
1120 return status;
1121}
1122
8a86e833
JK		 1123/**
1124 * be_cmd_create_default_pdu_queue()- Create DEFQ for the adapter
1125 * @ctrl: ptr to ctrl_info
1126 * @cq: Completion Queue
1127 * @dq: Default Queue
1128 * @lenght: ring size
1129 * @entry_size: size of each entry in DEFQ
1130 * @is_header: Header or Data DEFQ
1131 * @ulp_num: Bind to which ULP
1132 *
1133 * Create HDR/Data DEFQ for the passed ULP. Unsol PDU are posted
1134 * on this queue by the FW
1135 *
1136 * return
1137 * Success: 0
1138 * Failure: Non-Zero Value
1139 *
1140 **/
6733b39a
JK		 1141int be_cmd_create_default_pdu_queue(struct be_ctrl_info *ctrl,
1142 struct be_queue_info *cq,
1143 struct be_queue_info *dq, int length,
8a86e833
JK		 1144 int entry_size, uint8_t is_header,
1145 uint8_t ulp_num)
6733b39a
JK		 1146{
1147 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1148 struct be_defq_create_req *req = embedded_payload(wrb);
1149 struct be_dma_mem *q_mem = &dq->dma_mem;
ef9e1b9b 1150 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 1151 void *ctxt = &req->context;
1152 int status;
1153
1154 spin_lock(&ctrl->mbox_lock);
1155 memset(wrb, 0, sizeof(*wrb));
1156
1157 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1158
1159 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1160 OPCODE_COMMON_ISCSI_DEFQ_CREATE, sizeof(*req));
1161
1162 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
8a86e833
JK		 1163 if (phba->fw_config.dual_ulp_aware) {
1164 req->ulp_num = ulp_num;
1165 req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT);
1166 req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT);
1167 }
ef9e1b9b
JK		 1168
1169 if (is_chip_be2_be3r(phba)) {
1170 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1171 rx_pdid, ctxt, 0);
1172 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1173 rx_pdid_valid, ctxt, 1);
1174 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1175 pci_func_id, ctxt, PCI_FUNC(ctrl->pdev->devfn));
1176 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1177 ring_size, ctxt,
1178 be_encoded_q_len(length /
1179 sizeof(struct phys_addr)));
1180 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1181 default_buffer_size, ctxt, entry_size);
1182 AMAP_SET_BITS(struct amap_be_default_pdu_context,
1183 cq_id_recv, ctxt, cq->id);
1184 } else {
1185 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1186 rx_pdid, ctxt, 0);
1187 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1188 rx_pdid_valid, ctxt, 1);
1189 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1190 ring_size, ctxt,
1191 be_encoded_q_len(length /
1192 sizeof(struct phys_addr)));
1193 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1194 default_buffer_size, ctxt, entry_size);
1195 AMAP_SET_BITS(struct amap_default_pdu_context_ext,
1196 cq_id_recv, ctxt, cq->id);
1197 }
6733b39a
JK		 1198
1199 be_dws_cpu_to_le(ctxt, sizeof(req->context));
1200
1201 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1202
1203 status = be_mbox_notify(ctrl);
1204 if (!status) {
8a86e833 1205 struct be_ring *defq_ring;
6733b39a
JK		 1206 struct be_defq_create_resp *resp = embedded_payload(wrb);
1207
1208 dq->id = le16_to_cpu(resp->id);
1209 dq->created = true;
8a86e833
JK		 1210 if (is_header)
1211 defq_ring = &phba->phwi_ctrlr->default_pdu_hdr[ulp_num];
1212 else
1213 defq_ring = &phba->phwi_ctrlr->
1214 default_pdu_data[ulp_num];
1215
1216 defq_ring->id = dq->id;
1217
1218 if (!phba->fw_config.dual_ulp_aware) {
1219 defq_ring->ulp_num = BEISCSI_ULP0;
1220 defq_ring->doorbell_offset = DB_RXULP0_OFFSET;
1221 } else {
1222 defq_ring->ulp_num = resp->ulp_num;
1223 defq_ring->doorbell_offset = resp->doorbell_offset;
1224 }
6733b39a
JK		 1225 }
1226 spin_unlock(&ctrl->mbox_lock);
1227
1228 return status;
1229}
1230
4eea99d5
JK		 1231/**
1232 * be_cmd_wrbq_create()- Create WRBQ
1233 * @ctrl: ptr to ctrl_info
1234 * @q_mem: memory details for the queue
1235 * @wrbq: queue info
1236 * @pwrb_context: ptr to wrb_context
1237 * @ulp_num: ULP on which the WRBQ is to be created
1238 *
1239 * Create WRBQ on the passed ULP_NUM.
1240 *
1241 **/
1242int be_cmd_wrbq_create(struct be_ctrl_info *ctrl,
1243 struct be_dma_mem *q_mem,
1244 struct be_queue_info *wrbq,
1245 struct hwi_wrb_context *pwrb_context,
1246 uint8_t ulp_num)
6733b39a
JK		 1247{
1248 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1249 struct be_wrbq_create_req *req = embedded_payload(wrb);
1250 struct be_wrbq_create_resp *resp = embedded_payload(wrb);
4eea99d5 1251 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 1252 int status;
1253
1254 spin_lock(&ctrl->mbox_lock);
1255 memset(wrb, 0, sizeof(*wrb));
1256
1257 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1258
1259 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1260 OPCODE_COMMON_ISCSI_WRBQ_CREATE, sizeof(*req));
1261 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
4eea99d5
JK		 1262
1263 if (phba->fw_config.dual_ulp_aware) {
1264 req->ulp_num = ulp_num;
1265 req->dua_feature |= (1 << BEISCSI_DUAL_ULP_AWARE_BIT);
1266 req->dua_feature |= (1 << BEISCSI_BIND_Q_TO_ULP_BIT);
1267 }
1268
6733b39a
JK		 1269 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1270
1271 status = be_mbox_notify(ctrl);
bfead3b2 1272 if (!status) {
6733b39a 1273 wrbq->id = le16_to_cpu(resp->cid);
bfead3b2 1274 wrbq->created = true;
4eea99d5
JK		 1275
1276 pwrb_context->cid = wrbq->id;
1277 if (!phba->fw_config.dual_ulp_aware) {
1278 pwrb_context->doorbell_offset = DB_TXULP0_OFFSET;
1279 pwrb_context->ulp_num = BEISCSI_ULP0;
1280 } else {
1281 pwrb_context->ulp_num = resp->ulp_num;
1282 pwrb_context->doorbell_offset = resp->doorbell_offset;
1283 }
bfead3b2 1284 }
6733b39a
JK		 1285 spin_unlock(&ctrl->mbox_lock);
1286 return status;
1287}
1288
15a90fe0
JK		 1289int be_cmd_iscsi_post_template_hdr(struct be_ctrl_info *ctrl,
1290 struct be_dma_mem *q_mem)
1291{
1292 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1293 struct be_post_template_pages_req *req = embedded_payload(wrb);
1294 int status;
1295
1296 spin_lock(&ctrl->mbox_lock);
1297
1298 memset(wrb, 0, sizeof(*wrb));
1299 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1300 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1301 OPCODE_COMMON_ADD_TEMPLATE_HEADER_BUFFERS,
1302 sizeof(*req));
1303
1304 req->num_pages = PAGES_4K_SPANNED(q_mem->va, q_mem->size);
1305 req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI;
1306 be_cmd_page_addrs_prepare(req->pages, ARRAY_SIZE(req->pages), q_mem);
1307
1308 status = be_mbox_notify(ctrl);
1309 spin_unlock(&ctrl->mbox_lock);
1310 return status;
1311}
1312
1313int be_cmd_iscsi_remove_template_hdr(struct be_ctrl_info *ctrl)
1314{
1315 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1316 struct be_remove_template_pages_req *req = embedded_payload(wrb);
1317 int status;
1318
1319 spin_lock(&ctrl->mbox_lock);
1320
1321 memset(wrb, 0, sizeof(*wrb));
1322 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1323 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1324 OPCODE_COMMON_REMOVE_TEMPLATE_HEADER_BUFFERS,
1325 sizeof(*req));
1326
1327 req->type = BEISCSI_TEMPLATE_HDR_TYPE_ISCSI;
1328
1329 status = be_mbox_notify(ctrl);
1330 spin_unlock(&ctrl->mbox_lock);
1331 return status;
1332}
1333
6733b39a
JK		 1334int be_cmd_iscsi_post_sgl_pages(struct be_ctrl_info *ctrl,
1335 struct be_dma_mem *q_mem,
1336 u32 page_offset, u32 num_pages)
1337{
1338 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1339 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
99bc5d55 1340 struct beiscsi_hba *phba = pci_get_drvdata(ctrl->pdev);
6733b39a
JK		 1341 int status;
1342 unsigned int curr_pages;
1343 u32 internal_page_offset = 0;
1344 u32 temp_num_pages = num_pages;
1345
1346 if (num_pages == 0xff)
1347 num_pages = 1;
1348
1349 spin_lock(&ctrl->mbox_lock);
1350 do {
1351 memset(wrb, 0, sizeof(*wrb));
1352 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1353 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1354 OPCODE_COMMON_ISCSI_CFG_POST_SGL_PAGES,
1355 sizeof(*req));
1356 curr_pages = BE_NUMBER_OF_FIELD(struct be_post_sgl_pages_req,
1357 pages);
1358 req->num_pages = min(num_pages, curr_pages);
1359 req->page_offset = page_offset;
1360 be_cmd_page_addrs_prepare(req->pages, req->num_pages, q_mem);
1361 q_mem->dma = q_mem->dma + (req->num_pages * PAGE_SIZE);
1362 internal_page_offset += req->num_pages;
1363 page_offset += req->num_pages;
1364 num_pages -= req->num_pages;
1365
1366 if (temp_num_pages == 0xff)
1367 req->num_pages = temp_num_pages;
1368
1369 status = be_mbox_notify(ctrl);
1370 if (status) {
99bc5d55
JSJ		 1371 beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
1372 "BC_%d : FW CMD to map iscsi frags failed.\n");
1373
6733b39a
JK		 1374 goto error;
1375 }
1376 } while (num_pages > 0);
1377error:
1378 spin_unlock(&ctrl->mbox_lock);
1379 if (status != 0)
1380 beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
1381 return status;
1382}
e5285860
JK		 1383
1384int beiscsi_cmd_reset_function(struct beiscsi_hba *phba)
1385{
1386 struct be_ctrl_info *ctrl = &phba->ctrl;
1387 struct be_mcc_wrb *wrb = wrb_from_mbox(&ctrl->mbox_mem);
1388 struct be_post_sgl_pages_req *req = embedded_payload(wrb);
1389 int status;
1390
1391 spin_lock(&ctrl->mbox_lock);
1392
1393 req = embedded_payload(wrb);
1394 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0);
1395 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1396 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1397 status = be_mbox_notify_wait(phba);
1398
1399 spin_unlock(&ctrl->mbox_lock);
1400 return status;
1401}
6f72238e
JSJ		 1402
1403/**
1404 * be_cmd_set_vlan()- Configure VLAN paramters on the adapter
1405 * @phba: device priv structure instance
1406 * @vlan_tag: TAG to be set
1407 *
1408 * Set the VLAN_TAG for the adapter or Disable VLAN on adapter
1409 *
1410 * returns
1411 * TAG for the MBX Cmd
1412 * **/
1413int be_cmd_set_vlan(struct beiscsi_hba *phba,
1414 uint16_t vlan_tag)
1415{
1416 unsigned int tag = 0;
1417 struct be_mcc_wrb *wrb;
1418 struct be_cmd_set_vlan_req *req;
1419 struct be_ctrl_info *ctrl = &phba->ctrl;
1420
1421 spin_lock(&ctrl->mbox_lock);
1422 tag = alloc_mcc_tag(phba);
1423 if (!tag) {
1424 spin_unlock(&ctrl->mbox_lock);
1425 return tag;
1426 }
1427
1428 wrb = wrb_from_mccq(phba);
1429 req = embedded_payload(wrb);
1430 wrb->tag0 |= tag;
1431 be_wrb_hdr_prepare(wrb, sizeof(*wrb), true, 0);
1432 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ISCSI,
1433 OPCODE_COMMON_ISCSI_NTWK_SET_VLAN,
1434 sizeof(*req));
1435
1436 req->interface_hndl = phba->interface_handle;
1437 req->vlan_priority = vlan_tag;
1438
1439 be_mcc_notify(phba);
1440 spin_unlock(&ctrl->mbox_lock);
1441
1442 return tag;
1443}
Linux 6.x block layer and io_uring tree(s)