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[PATCH] libata-hp: update unload-unplug
[linux-block.git] / drivers / scsi / ata_piix.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
94
95#define DRV_NAME "ata_piix"
af64371a 96#define DRV_VERSION "1.10"
1da177e4
LT		 97
98enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 102 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 103
219e6214 104 PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */
d4358048 105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108 PIIX_FLAG_COMBINED = (1 << 29), /* combined mode possible */
109 /* ICH6/7 use different scheme for map value */
110 PIIX_FLAG_COMBINED_ICH6 = PIIX_FLAG_COMBINED | (1 << 30),
1da177e4
LT		 111
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
6a690df5
HR		 115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
1d076e5b
TH		 121 /* controller IDs */
122 piix4_pata = 0,
123 ich5_pata = 1,
124 ich5_sata = 2,
125 esb_sata = 3,
126 ich6_sata = 4,
127 ich6_sata_ahci = 5,
128 ich6m_sata_ahci = 6,
7b6dbd68 129
d33f58b8
TH		 130 /* constants for mapping table */
131 P0 = 0, /* port 0 */
132 P1 = 1, /* port 1 */
133 P2 = 2, /* port 2 */
134 P3 = 3, /* port 3 */
135 IDE = -1, /* IDE */
136 NA = -2, /* not avaliable */
137 RV = -3, /* reserved */
138
7b6dbd68 139 PIIX_AHCI_DEVICE = 6,
1da177e4
LT		 140};
141
d33f58b8
TH		 142struct piix_map_db {
143 const u32 mask;
144 const int map[][4];
145};
146
1da177e4
LT		 147static int piix_init_one (struct pci_dev *pdev,
148 const struct pci_device_id *ent);
149
573db6b8 150static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes);
ccbe6d5e 151static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes);
1da177e4
LT		 152static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
153static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
154
155static unsigned int in_module_init = 1;
156
3b7d697d 157static const struct pci_device_id piix_pci_tbl[] = {
1da177e4
LT		 158#ifdef ATA_ENABLE_PATA
159 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
160 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
161 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
b74ba22f 162 { 0x8086, 0x27df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
1da177e4
LT		 163#endif
164
165 /* NOTE: The following PCI ids must be kept in sync with the
166 * list in drivers/pci/quirks.c.
167 */
168
1d076e5b 169 /* 82801EB (ICH5) */
1da177e4 170 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 171 /* 82801EB (ICH5) */
1da177e4 172 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b
TH		 173 /* 6300ESB (ICH5 variant with broken PCS present bits) */
174 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
175 /* 6300ESB pretending RAID */
176 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
177 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 178 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 179 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 180 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 181 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
182 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
183 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 184 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 185 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
186 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
187 /* Enterprise Southbridge 2 (where's the datasheet?) */
1c24a412 188 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 189 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
012b265f 190 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 191 /* SATA Controller 2 IDE (ICH8, ditto) */
012b265f 192 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 193 /* Mobile SATA Controller IDE (ICH8M, ditto) */
194 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
1da177e4
LT		 195
196 { } /* terminate list */
197};
198
199static struct pci_driver piix_pci_driver = {
200 .name = DRV_NAME,
201 .id_table = piix_pci_tbl,
202 .probe = piix_init_one,
203 .remove = ata_pci_remove_one,
9b847548
JA		 204 .suspend = ata_pci_device_suspend,
205 .resume = ata_pci_device_resume,
1da177e4
LT		 206};
207
193515d5 208static struct scsi_host_template piix_sht = {
1da177e4
LT		 209 .module = THIS_MODULE,
210 .name = DRV_NAME,
211 .ioctl = ata_scsi_ioctl,
212 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 213 .can_queue = ATA_DEF_QUEUE,
214 .this_id = ATA_SHT_THIS_ID,
215 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 216 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
217 .emulated = ATA_SHT_EMULATED,
218 .use_clustering = ATA_SHT_USE_CLUSTERING,
219 .proc_name = DRV_NAME,
220 .dma_boundary = ATA_DMA_BOUNDARY,
221 .slave_configure = ata_scsi_slave_config,
ccf68c34 222 .slave_destroy = ata_scsi_slave_destroy,
1da177e4 223 .bios_param = ata_std_bios_param,
9b847548
JA		 224 .resume = ata_scsi_device_resume,
225 .suspend = ata_scsi_device_suspend,
1da177e4
LT		 226};
227
057ace5e 228static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 229 .port_disable = ata_port_disable,
230 .set_piomode = piix_set_piomode,
231 .set_dmamode = piix_set_dmamode,
89bad589 232 .mode_filter = ata_pci_default_filter,
1da177e4
LT		 233
234 .tf_load = ata_tf_load,
235 .tf_read = ata_tf_read,
236 .check_status = ata_check_status,
237 .exec_command = ata_exec_command,
238 .dev_select = ata_std_dev_select,
239
573db6b8 240 .probe_reset = piix_pata_probe_reset,
1da177e4
LT		 241
242 .bmdma_setup = ata_bmdma_setup,
243 .bmdma_start = ata_bmdma_start,
244 .bmdma_stop = ata_bmdma_stop,
245 .bmdma_status = ata_bmdma_status,
246 .qc_prep = ata_qc_prep,
247 .qc_issue = ata_qc_issue_prot,
89bad589 248 .data_xfer = ata_pio_data_xfer,
1da177e4 249
3f037db0
TH		 250 .freeze = ata_bmdma_freeze,
251 .thaw = ata_bmdma_thaw,
252 .error_handler = ata_bmdma_error_handler,
253 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 254
255 .irq_handler = ata_interrupt,
256 .irq_clear = ata_bmdma_irq_clear,
257
258 .port_start = ata_port_start,
259 .port_stop = ata_port_stop,
aa8f0dc6 260 .host_stop = ata_host_stop,
1da177e4
LT		 261};
262
057ace5e 263static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 264 .port_disable = ata_port_disable,
265
266 .tf_load = ata_tf_load,
267 .tf_read = ata_tf_read,
268 .check_status = ata_check_status,
269 .exec_command = ata_exec_command,
270 .dev_select = ata_std_dev_select,
271
ccbe6d5e 272 .probe_reset = piix_sata_probe_reset,
1da177e4
LT		 273
274 .bmdma_setup = ata_bmdma_setup,
275 .bmdma_start = ata_bmdma_start,
276 .bmdma_stop = ata_bmdma_stop,
277 .bmdma_status = ata_bmdma_status,
278 .qc_prep = ata_qc_prep,
279 .qc_issue = ata_qc_issue_prot,
89bad589 280 .data_xfer = ata_pio_data_xfer,
1da177e4 281
3f037db0
TH		 282 .freeze = ata_bmdma_freeze,
283 .thaw = ata_bmdma_thaw,
284 .error_handler = ata_bmdma_error_handler,
285 .post_internal_cmd = ata_bmdma_post_internal_cmd,
1da177e4
LT		 286
287 .irq_handler = ata_interrupt,
288 .irq_clear = ata_bmdma_irq_clear,
289
290 .port_start = ata_port_start,
291 .port_stop = ata_port_stop,
aa8f0dc6 292 .host_stop = ata_host_stop,
1da177e4
LT		 293};
294
d33f58b8
TH		 295static struct piix_map_db ich5_map_db = {
296 .mask = 0x7,
297 .map = {
298 /* PM PS SM SS MAP */
299 { P0, NA, P1, NA }, /* 000b */
300 { P1, NA, P0, NA }, /* 001b */
301 { RV, RV, RV, RV },
302 { RV, RV, RV, RV },
303 { P0, P1, IDE, IDE }, /* 100b */
304 { P1, P0, IDE, IDE }, /* 101b */
305 { IDE, IDE, P0, P1 }, /* 110b */
306 { IDE, IDE, P1, P0 }, /* 111b */
307 },
308};
309
310static struct piix_map_db ich6_map_db = {
311 .mask = 0x3,
312 .map = {
313 /* PM PS SM SS MAP */
79ea24e7 314 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 315 { IDE, IDE, P1, P3 }, /* 01b */
316 { P0, P2, IDE, IDE }, /* 10b */
317 { RV, RV, RV, RV },
318 },
319};
320
321static struct piix_map_db ich6m_map_db = {
322 .mask = 0x3,
323 .map = {
324 /* PM PS SM SS MAP */
79ea24e7 325 { P0, P2, RV, RV }, /* 00b */
d33f58b8
TH		 326 { RV, RV, RV, RV },
327 { P0, P2, IDE, IDE }, /* 10b */
328 { RV, RV, RV, RV },
329 },
330};
331
1da177e4 332static struct ata_port_info piix_port_info[] = {
1d076e5b
TH		 333 /* piix4_pata */
334 {
335 .sht = &piix_sht,
336 .host_flags = ATA_FLAG_SLAVE_POSS,
337 .pio_mask = 0x1f, /* pio0-4 */
338#if 0
339 .mwdma_mask = 0x06, /* mwdma1-2 */
340#else
341 .mwdma_mask = 0x00, /* mwdma broken */
342#endif
343 .udma_mask = ATA_UDMA_MASK_40C,
344 .port_ops = &piix_pata_ops,
345 },
346
1da177e4
LT		 347 /* ich5_pata */
348 {
349 .sht = &piix_sht,
573db6b8 350 .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
1da177e4
LT		 351 .pio_mask = 0x1f, /* pio0-4 */
352#if 0
353 .mwdma_mask = 0x06, /* mwdma1-2 */
354#else
355 .mwdma_mask = 0x00, /* mwdma broken */
356#endif
357 .udma_mask = 0x3f, /* udma0-5 */
358 .port_ops = &piix_pata_ops,
359 },
360
361 /* ich5_sata */
362 {
363 .sht = &piix_sht,
ccbe6d5e
TH		 364 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
365 PIIX_FLAG_CHECKINTR,
1da177e4
LT		 366 .pio_mask = 0x1f, /* pio0-4 */
367 .mwdma_mask = 0x07, /* mwdma0-2 */
368 .udma_mask = 0x7f, /* udma0-6 */
369 .port_ops = &piix_sata_ops,
d33f58b8 370 .private_data = &ich5_map_db,
1da177e4
LT		 371 },
372
1d076e5b 373 /* i6300esb_sata */
1da177e4
LT		 374 {
375 .sht = &piix_sht,
1d076e5b 376 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
219e6214 377 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS,
1da177e4 378 .pio_mask = 0x1f, /* pio0-4 */
1d076e5b
TH		 379 .mwdma_mask = 0x07, /* mwdma0-2 */
380 .udma_mask = 0x7f, /* udma0-6 */
381 .port_ops = &piix_sata_ops,
d33f58b8 382 .private_data = &ich5_map_db,
1da177e4
LT		 383 },
384
385 /* ich6_sata */
386 {
387 .sht = &piix_sht,
ccbe6d5e 388 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
d33f58b8 389 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR,
1da177e4
LT		 390 .pio_mask = 0x1f, /* pio0-4 */
391 .mwdma_mask = 0x07, /* mwdma0-2 */
392 .udma_mask = 0x7f, /* udma0-6 */
393 .port_ops = &piix_sata_ops,
d33f58b8 394 .private_data = &ich6_map_db,
1da177e4
LT		 395 },
396
1c24a412 397 /* ich6_sata_ahci */
c368ca4e
JG		 398 {
399 .sht = &piix_sht,
ccbe6d5e 400 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
d33f58b8
TH		 401 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
402 PIIX_FLAG_AHCI,
c368ca4e
JG		 403 .pio_mask = 0x1f, /* pio0-4 */
404 .mwdma_mask = 0x07, /* mwdma0-2 */
405 .udma_mask = 0x7f, /* udma0-6 */
406 .port_ops = &piix_sata_ops,
d33f58b8 407 .private_data = &ich6_map_db,
c368ca4e 408 },
1d076e5b
TH		 409
410 /* ich6m_sata_ahci */
411 {
412 .sht = &piix_sht,
413 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
d33f58b8
TH		 414 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
415 PIIX_FLAG_AHCI,
1d076e5b
TH		 416 .pio_mask = 0x1f, /* pio0-4 */
417 .mwdma_mask = 0x07, /* mwdma0-2 */
418 .udma_mask = 0x7f, /* udma0-6 */
419 .port_ops = &piix_sata_ops,
d33f58b8 420 .private_data = &ich6m_map_db,
1d076e5b 421 },
1da177e4
LT		 422};
423
424static struct pci_bits piix_enable_bits[] = {
425 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
426 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
427};
428
429MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
430MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
431MODULE_LICENSE("GPL");
432MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
433MODULE_VERSION(DRV_VERSION);
434
435/**
436 * piix_pata_cbl_detect - Probe host controller cable detect info
437 * @ap: Port for which cable detect info is desired
438 *
439 * Read 80c cable indicator from ATA PCI device's PCI config
440 * register. This register is normally set by firmware (BIOS).
441 *
442 * LOCKING:
443 * None (inherited from caller).
444 */
445static void piix_pata_cbl_detect(struct ata_port *ap)
446{
447 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
448 u8 tmp, mask;
449
450 /* no 80c support in host controller? */
451 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
452 goto cbl40;
453
454 /* check BIOS cable detect results */
455 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
456 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
457 if ((tmp & mask) == 0)
458 goto cbl40;
459
460 ap->cbl = ATA_CBL_PATA80;
461 return;
462
463cbl40:
464 ap->cbl = ATA_CBL_PATA40;
465 ap->udma_mask &= ATA_UDMA_MASK_40C;
466}
467
468/**
573db6b8
TH		 469 * piix_pata_probeinit - probeinit for PATA host controller
470 * @ap: Target port
1da177e4 471 *
573db6b8 472 * Probeinit including cable detection.
1da177e4
LT		 473 *
474 * LOCKING:
475 * None (inherited from caller).
476 */
573db6b8
TH		 477static void piix_pata_probeinit(struct ata_port *ap)
478{
479 piix_pata_cbl_detect(ap);
480 ata_std_probeinit(ap);
481}
1da177e4 482
573db6b8
TH		 483/**
484 * piix_pata_probe_reset - Perform reset on PATA port and classify
485 * @ap: Port to reset
486 * @classes: Resulting classes of attached devices
487 *
488 * Reset PATA phy and classify attached devices.
489 *
490 * LOCKING:
491 * None (inherited from caller).
492 */
493static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes)
1da177e4
LT		 494{
495 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
496
497 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
f15a1daf 498 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
573db6b8 499 return 0;
1da177e4
LT		 500 }
501
573db6b8
TH		 502 return ata_drive_probe_reset(ap, piix_pata_probeinit,
503 ata_std_softreset, NULL,
504 ata_std_postreset, classes);
1da177e4
LT		 505}
506
507/**
508 * piix_sata_probe - Probe PCI device for present SATA devices
509 * @ap: Port associated with the PCI device we wish to probe
510 *
d133ecab
TH		 511 * Reads and configures SATA PCI device's PCI config register
512 * Port Configuration and Status (PCS) to determine port and
513 * device availability.
1da177e4
LT		 514 *
515 * LOCKING:
516 * None (inherited from caller).
517 *
518 * RETURNS:
d133ecab 519 * Mask of avaliable devices on the port.
1da177e4 520 */
d133ecab 521static unsigned int piix_sata_probe (struct ata_port *ap)
1da177e4
LT		 522{
523 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
d133ecab
TH		 524 const unsigned int *map = ap->host_set->private_data;
525 int base = 2 * ap->hard_port_no;
526 unsigned int present_mask = 0;
527 int port, i;
1da177e4
LT		 528 u8 pcs;
529
1da177e4 530 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
d133ecab
TH		 531 DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base);
532
533 /* enable all ports on this ap and wait for them to settle */
534 for (i = 0; i < 2; i++) {
535 port = map[base + i];
536 if (port >= 0)
537 pcs |= 1 << port;
538 }
1da177e4 539
d133ecab
TH		 540 pci_write_config_byte(pdev, ICH5_PCS, pcs);
541 msleep(100);
1da177e4 542
d133ecab
TH		 543 /* let's see which devices are present */
544 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
545
546 for (i = 0; i < 2; i++) {
547 port = map[base + i];
548 if (port < 0)
549 continue;
219e6214 550 if (ap->flags & PIIX_FLAG_IGNORE_PCS || pcs & 1 << (4 + port))
d133ecab
TH		 551 present_mask |= 1 << i;
552 else
553 pcs &= ~(1 << port);
1da177e4
LT		 554 }
555
d133ecab
TH		 556 /* disable offline ports on non-AHCI controllers */
557 if (!(ap->flags & PIIX_FLAG_AHCI))
558 pci_write_config_byte(pdev, ICH5_PCS, pcs);
559
560 DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n",
561 ap->id, pcs, present_mask);
562
563 return present_mask;
1da177e4
LT		 564}
565
566/**
ccbe6d5e
TH		 567 * piix_sata_probe_reset - Perform reset on SATA port and classify
568 * @ap: Port to reset
569 * @classes: Resulting classes of attached devices
1da177e4 570 *
ccbe6d5e 571 * Reset SATA phy and classify attached devices.
1da177e4
LT		 572 *
573 * LOCKING:
574 * None (inherited from caller).
575 */
ccbe6d5e 576static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes)
1da177e4
LT		 577{
578 if (!piix_sata_probe(ap)) {
f15a1daf 579 ata_port_printk(ap, KERN_INFO, "SATA port has no device.\n");
ccbe6d5e 580 return 0;
1da177e4
LT		 581 }
582
ccbe6d5e
TH		 583 return ata_drive_probe_reset(ap, ata_std_probeinit,
584 ata_std_softreset, NULL,
585 ata_std_postreset, classes);
1da177e4
LT		 586}
587
588/**
589 * piix_set_piomode - Initialize host controller PATA PIO timings
590 * @ap: Port whose timings we are configuring
591 * @adev: um
1da177e4
LT		 592 *
593 * Set PIO mode for device, in host controller PCI config space.
594 *
595 * LOCKING:
596 * None (inherited from caller).
597 */
598
599static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
600{
601 unsigned int pio = adev->pio_mode - XFER_PIO_0;
602 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
603 unsigned int is_slave = (adev->devno != 0);
604 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
605 unsigned int slave_port = 0x44;
606 u16 master_data;
607 u8 slave_data;
608
609 static const /* ISP RTC */
610 u8 timings[][2] = { { 0, 0 },
611 { 0, 0 },
612 { 1, 0 },
613 { 2, 1 },
614 { 2, 3 }, };
615
616 pci_read_config_word(dev, master_port, &master_data);
617 if (is_slave) {
618 master_data |= 0x4000;
619 /* enable PPE, IE and TIME */
620 master_data |= 0x0070;
621 pci_read_config_byte(dev, slave_port, &slave_data);
622 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
623 slave_data |=
624 (timings[pio][0] << 2) |
625 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
626 } else {
627 master_data &= 0xccf8;
628 /* enable PPE, IE and TIME */
629 master_data |= 0x0007;
630 master_data |=
631 (timings[pio][0] << 12) |
632 (timings[pio][1] << 8);
633 }
634 pci_write_config_word(dev, master_port, master_data);
635 if (is_slave)
636 pci_write_config_byte(dev, slave_port, slave_data);
637}
638
639/**
640 * piix_set_dmamode - Initialize host controller PATA PIO timings
641 * @ap: Port whose timings we are configuring
642 * @adev: um
643 * @udma: udma mode, 0 - 6
644 *
645 * Set UDMA mode for device, in host controller PCI config space.
646 *
647 * LOCKING:
648 * None (inherited from caller).
649 */
650
651static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
652{
653 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
654 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
655 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
656 u8 speed = udma;
657 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
658 int a_speed = 3 << (drive_dn * 4);
659 int u_flag = 1 << drive_dn;
660 int v_flag = 0x01 << drive_dn;
661 int w_flag = 0x10 << drive_dn;
662 int u_speed = 0;
663 int sitre;
664 u16 reg4042, reg4a;
665 u8 reg48, reg54, reg55;
666
667 pci_read_config_word(dev, maslave, &reg4042);
668 DPRINTK("reg4042 = 0x%04x\n", reg4042);
669 sitre = (reg4042 & 0x4000) ? 1 : 0;
670 pci_read_config_byte(dev, 0x48, &reg48);
671 pci_read_config_word(dev, 0x4a, &reg4a);
672 pci_read_config_byte(dev, 0x54, &reg54);
673 pci_read_config_byte(dev, 0x55, &reg55);
674
675 switch(speed) {
676 case XFER_UDMA_4:
677 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
678 case XFER_UDMA_6:
679 case XFER_UDMA_5:
680 case XFER_UDMA_3:
681 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
682 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
683 case XFER_MW_DMA_2:
684 case XFER_MW_DMA_1: break;
685 default:
686 BUG();
687 return;
688 }
689
690 if (speed >= XFER_UDMA_0) {
691 if (!(reg48 & u_flag))
692 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
693 if (speed == XFER_UDMA_5) {
694 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
695 } else {
696 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
697 }
698 if ((reg4a & a_speed) != u_speed)
699 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
700 if (speed > XFER_UDMA_2) {
701 if (!(reg54 & v_flag))
702 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
703 } else
704 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
705 } else {
706 if (reg48 & u_flag)
707 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
708 if (reg4a & a_speed)
709 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
710 if (reg54 & v_flag)
711 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
712 if (reg55 & w_flag)
713 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
714 }
715}
716
1da177e4
LT		 717#define AHCI_PCI_BAR 5
718#define AHCI_GLOBAL_CTL 0x04
719#define AHCI_ENABLE (1 << 31)
720static int piix_disable_ahci(struct pci_dev *pdev)
721{
ea6ba10b 722 void __iomem *mmio;
1da177e4
LT		 723 u32 tmp;
724 int rc = 0;
725
726 /* BUG: pci_enable_device has not yet been called. This
727 * works because this device is usually set up by BIOS.
728 */
729
374b1873
JG		 730 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
731 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 732 return 0;
7b6dbd68 733
374b1873 734 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 735 if (!mmio)
736 return -ENOMEM;
7b6dbd68 737
1da177e4
LT		 738 tmp = readl(mmio + AHCI_GLOBAL_CTL);
739 if (tmp & AHCI_ENABLE) {
740 tmp &= ~AHCI_ENABLE;
741 writel(tmp, mmio + AHCI_GLOBAL_CTL);
742
743 tmp = readl(mmio + AHCI_GLOBAL_CTL);
744 if (tmp & AHCI_ENABLE)
745 rc = -EIO;
746 }
7b6dbd68 747
374b1873 748 pci_iounmap(pdev, mmio);
1da177e4
LT		 749 return rc;
750}
751
c621b140
AC		 752/**
753 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 754 * @ata_dev: the PCI device to check
2e9edbf8 755 *
c621b140
AC		 756 * Check for the present of 450NX errata #19 and errata #25. If
757 * they are found return an error code so we can turn off DMA
758 */
759
760static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
761{
762 struct pci_dev *pdev = NULL;
763 u16 cfg;
764 u8 rev;
765 int no_piix_dma = 0;
2e9edbf8 766
c621b140
AC		 767 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
768 {
769 /* Look for 450NX PXB. Check for problem configurations
770 A PCI quirk checks bit 6 already */
771 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
772 pci_read_config_word(pdev, 0x41, &cfg);
773 /* Only on the original revision: IDE DMA can hang */
31a34fe7 774 if (rev == 0x00)
c621b140
AC		 775 no_piix_dma = 1;
776 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
31a34fe7 777 else if (cfg & (1<<14) && rev < 5)
c621b140
AC		 778 no_piix_dma = 2;
779 }
31a34fe7 780 if (no_piix_dma)
c621b140 781 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
31a34fe7 782 if (no_piix_dma == 2)
c621b140
AC		 783 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
784 return no_piix_dma;
2e9edbf8 785}
c621b140 786
d33f58b8
TH		 787static void __devinit piix_init_sata_map(struct pci_dev *pdev,
788 struct ata_port_info *pinfo)
789{
790 struct piix_map_db *map_db = pinfo[0].private_data;
791 const unsigned int *map;
792 int i, invalid_map = 0;
793 u8 map_value;
794
795 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
796
797 map = map_db->map[map_value & map_db->mask];
798
799 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
800 for (i = 0; i < 4; i++) {
801 switch (map[i]) {
802 case RV:
803 invalid_map = 1;
804 printk(" XX");
805 break;
806
807 case NA:
808 printk(" --");
809 break;
810
811 case IDE:
812 WARN_ON((i & 1) || map[i + 1] != IDE);
813 pinfo[i / 2] = piix_port_info[ich5_pata];
814 i++;
815 printk(" IDE IDE");
816 break;
817
818 default:
819 printk(" P%d", map[i]);
820 if (i & 1)
821 pinfo[i / 2].host_flags |= ATA_FLAG_SLAVE_POSS;
822 break;
823 }
824 }
825 printk(" ]\n");
826
827 if (invalid_map)
828 dev_printk(KERN_ERR, &pdev->dev,
829 "invalid MAP value %u\n", map_value);
830
831 pinfo[0].private_data = (void *)map;
832 pinfo[1].private_data = (void *)map;
833}
834
1da177e4
LT		 835/**
836 * piix_init_one - Register PIIX ATA PCI device with kernel services
837 * @pdev: PCI device to register
838 * @ent: Entry in piix_pci_tbl matching with @pdev
839 *
840 * Called from kernel PCI layer. We probe for combined mode (sigh),
841 * and then hand over control to libata, for it to do the rest.
842 *
843 * LOCKING:
844 * Inherited from PCI layer (may sleep).
845 *
846 * RETURNS:
847 * Zero on success, or -ERRNO value.
848 */
849
850static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
851{
852 static int printed_version;
d33f58b8
TH		 853 struct ata_port_info port_info[2];
854 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
ff0fc146 855 unsigned long host_flags;
1da177e4
LT		 856
857 if (!printed_version++)
6248e647
JG		 858 dev_printk(KERN_DEBUG, &pdev->dev,
859 "version " DRV_VERSION "\n");
1da177e4
LT		 860
861 /* no hotplugging support (FIXME) */
862 if (!in_module_init)
863 return -ENODEV;
864
d33f58b8
TH		 865 port_info[0] = piix_port_info[ent->driver_data];
866 port_info[1] = piix_port_info[ent->driver_data];
1da177e4 867
d33f58b8 868 host_flags = port_info[0].host_flags;
ff0fc146
TH		 869
870 if (host_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 871 u8 tmp;
872 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
873 if (tmp == PIIX_AHCI_DEVICE) {
874 int rc = piix_disable_ahci(pdev);
875 if (rc)
876 return rc;
877 }
1da177e4
LT		 878 }
879
d33f58b8
TH		 880 /* Initialize SATA map */
881 if (host_flags & ATA_FLAG_SATA)
882 piix_init_sata_map(pdev, port_info);
1da177e4
LT		 883
884 /* On ICH5, some BIOSen disable the interrupt using the
885 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
886 * On ICH6, this bit has the same effect, but only when
887 * MSI is disabled (and it is disabled, as we don't use
888 * message-signalled interrupts currently).
889 */
ff0fc146 890 if (host_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 891 pci_intx(pdev, 1);
1da177e4 892
c621b140
AC		 893 if (piix_check_450nx_errata(pdev)) {
894 /* This writes into the master table but it does not
895 really matter for this errata as we will apply it to
896 all the PIIX devices on the board */
d33f58b8
TH		 897 port_info[0].mwdma_mask = 0;
898 port_info[0].udma_mask = 0;
899 port_info[1].mwdma_mask = 0;
900 port_info[1].udma_mask = 0;
c621b140 901 }
d33f58b8 902 return ata_pci_init_one(pdev, ppinfo, 2);
1da177e4
LT		 903}
904
1da177e4
LT		 905static int __init piix_init(void)
906{
907 int rc;
908
909 DPRINTK("pci_module_init\n");
910 rc = pci_module_init(&piix_pci_driver);
911 if (rc)
912 return rc;
913
914 in_module_init = 0;
915
916 DPRINTK("done\n");
917 return 0;
918}
919
1da177e4
LT		 920static void __exit piix_exit(void)
921{
922 pci_unregister_driver(&piix_pci_driver);
923}
924
925module_init(piix_init);
926module_exit(piix_exit);
927
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