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[PATCH] libata-eh: implement BMDMA EH
[linux-block.git] / drivers / scsi / ata_piix.c
CommitLineData
1da177e4 1/*
af36d7f0
JG		 2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
d96212ed
AC		 40 * Documentation
41 * Publically available from Intel web site. Errata documentation
42 * is also publically available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below.going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The orginal Triton
47 * series chipsets do _not_ support independant device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independant timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 *
76 * Should have been BIOS fixed:
77 * 450NX: errata #19 - DMA hangs on old 450NX
78 * 450NX: errata #20 - DMA hangs on old 450NX
79 * 450NX: errata #25 - Corruption with DMA on old 450NX
80 * ICH3 errata #15 - IDE deadlock under high load
81 * (BIOS must set dev 31 fn 0 bit 23)
82 * ICH3 errata #18 - Don't use native mode
1da177e4
LT		 83 */
84
85#include <linux/kernel.h>
86#include <linux/module.h>
87#include <linux/pci.h>
88#include <linux/init.h>
89#include <linux/blkdev.h>
90#include <linux/delay.h>
6248e647 91#include <linux/device.h>
1da177e4
LT		 92#include <scsi/scsi_host.h>
93#include <linux/libata.h>
94
95#define DRV_NAME "ata_piix"
af64371a 96#define DRV_VERSION "1.10"
1da177e4
LT		 97
98enum {
99 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
100 ICH5_PMR = 0x90, /* port mapping register */
101 ICH5_PCS = 0x92, /* port control and status */
7b6dbd68 102 PIIX_SCC = 0x0A, /* sub-class code register */
1da177e4 103
219e6214 104 PIIX_FLAG_IGNORE_PCS = (1 << 25), /* ignore PCS present bits */
d4358048 105 PIIX_FLAG_SCR = (1 << 26), /* SCR available */
ff0fc146
TH		 106 PIIX_FLAG_AHCI = (1 << 27), /* AHCI possible */
107 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
108 PIIX_FLAG_COMBINED = (1 << 29), /* combined mode possible */
109 /* ICH6/7 use different scheme for map value */
110 PIIX_FLAG_COMBINED_ICH6 = PIIX_FLAG_COMBINED | (1 << 30),
1da177e4
LT		 111
112 /* combined mode. if set, PATA is channel 0.
113 * if clear, PATA is channel 1.
114 */
6a690df5
HR		 115 PIIX_PORT_ENABLED = (1 << 0),
116 PIIX_PORT_PRESENT = (1 << 4),
1da177e4
LT		 117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
1d076e5b
TH		 121 /* controller IDs */
122 piix4_pata = 0,
123 ich5_pata = 1,
124 ich5_sata = 2,
125 esb_sata = 3,
126 ich6_sata = 4,
127 ich6_sata_ahci = 5,
128 ich6m_sata_ahci = 6,
7b6dbd68 129
d33f58b8
TH		 130 /* constants for mapping table */
131 P0 = 0, /* port 0 */
132 P1 = 1, /* port 1 */
133 P2 = 2, /* port 2 */
134 P3 = 3, /* port 3 */
135 IDE = -1, /* IDE */
136 NA = -2, /* not avaliable */
137 RV = -3, /* reserved */
138
7b6dbd68 139 PIIX_AHCI_DEVICE = 6,
1da177e4
LT		 140};
141
d33f58b8
TH		 142struct piix_map_db {
143 const u32 mask;
144 const int map[][4];
145};
146
1da177e4
LT		 147static int piix_init_one (struct pci_dev *pdev,
148 const struct pci_device_id *ent);
149
573db6b8 150static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes);
ccbe6d5e 151static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes);
1da177e4
LT		 152static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
153static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
154
155static unsigned int in_module_init = 1;
156
3b7d697d 157static const struct pci_device_id piix_pci_tbl[] = {
1da177e4
LT		 158#ifdef ATA_ENABLE_PATA
159 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
160 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
161 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
162#endif
163
164 /* NOTE: The following PCI ids must be kept in sync with the
165 * list in drivers/pci/quirks.c.
166 */
167
1d076e5b 168 /* 82801EB (ICH5) */
1da177e4 169 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b 170 /* 82801EB (ICH5) */
1da177e4 171 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
1d076e5b
TH		 172 /* 6300ESB (ICH5 variant with broken PCS present bits) */
173 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
174 /* 6300ESB pretending RAID */
175 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb_sata },
176 /* 82801FB/FW (ICH6/ICH6W) */
1da177e4 177 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
1d076e5b 178 /* 82801FR/FRW (ICH6R/ICH6RW) */
1c24a412 179 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 180 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented) */
181 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
182 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
1c24a412 183 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 184 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
185 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
186 /* Enterprise Southbridge 2 (where's the datasheet?) */
1c24a412 187 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 188 /* SATA Controller 1 IDE (ICH8, no datasheet yet) */
012b265f 189 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b 190 /* SATA Controller 2 IDE (ICH8, ditto) */
012b265f 191 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_ahci },
1d076e5b
TH		 192 /* Mobile SATA Controller IDE (ICH8M, ditto) */
193 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata_ahci },
1da177e4
LT		 194
195 { } /* terminate list */
196};
197
198static struct pci_driver piix_pci_driver = {
199 .name = DRV_NAME,
200 .id_table = piix_pci_tbl,
201 .probe = piix_init_one,
202 .remove = ata_pci_remove_one,
9b847548
JA		 203 .suspend = ata_pci_device_suspend,
204 .resume = ata_pci_device_resume,
1da177e4
LT		 205};
206
193515d5 207static struct scsi_host_template piix_sht = {
1da177e4
LT		 208 .module = THIS_MODULE,
209 .name = DRV_NAME,
210 .ioctl = ata_scsi_ioctl,
211 .queuecommand = ata_scsi_queuecmd,
1da177e4
LT		 212 .can_queue = ATA_DEF_QUEUE,
213 .this_id = ATA_SHT_THIS_ID,
214 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4
LT		 215 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
216 .emulated = ATA_SHT_EMULATED,
217 .use_clustering = ATA_SHT_USE_CLUSTERING,
218 .proc_name = DRV_NAME,
219 .dma_boundary = ATA_DMA_BOUNDARY,
220 .slave_configure = ata_scsi_slave_config,
221 .bios_param = ata_std_bios_param,
9b847548
JA		 222 .resume = ata_scsi_device_resume,
223 .suspend = ata_scsi_device_suspend,
1da177e4
LT		 224};
225
057ace5e 226static const struct ata_port_operations piix_pata_ops = {
1da177e4
LT		 227 .port_disable = ata_port_disable,
228 .set_piomode = piix_set_piomode,
229 .set_dmamode = piix_set_dmamode,
230
231 .tf_load = ata_tf_load,
232 .tf_read = ata_tf_read,
233 .check_status = ata_check_status,
234 .exec_command = ata_exec_command,
235 .dev_select = ata_std_dev_select,
236
573db6b8 237 .probe_reset = piix_pata_probe_reset,
1da177e4
LT		 238
239 .bmdma_setup = ata_bmdma_setup,
240 .bmdma_start = ata_bmdma_start,
241 .bmdma_stop = ata_bmdma_stop,
242 .bmdma_status = ata_bmdma_status,
243 .qc_prep = ata_qc_prep,
244 .qc_issue = ata_qc_issue_prot,
245
246 .eng_timeout = ata_eng_timeout,
247
248 .irq_handler = ata_interrupt,
249 .irq_clear = ata_bmdma_irq_clear,
250
251 .port_start = ata_port_start,
252 .port_stop = ata_port_stop,
aa8f0dc6 253 .host_stop = ata_host_stop,
1da177e4
LT		 254};
255
057ace5e 256static const struct ata_port_operations piix_sata_ops = {
1da177e4
LT		 257 .port_disable = ata_port_disable,
258
259 .tf_load = ata_tf_load,
260 .tf_read = ata_tf_read,
261 .check_status = ata_check_status,
262 .exec_command = ata_exec_command,
263 .dev_select = ata_std_dev_select,
264
ccbe6d5e 265 .probe_reset = piix_sata_probe_reset,
1da177e4
LT		 266
267 .bmdma_setup = ata_bmdma_setup,
268 .bmdma_start = ata_bmdma_start,
269 .bmdma_stop = ata_bmdma_stop,
270 .bmdma_status = ata_bmdma_status,
271 .qc_prep = ata_qc_prep,
272 .qc_issue = ata_qc_issue_prot,
273
274 .eng_timeout = ata_eng_timeout,
275
276 .irq_handler = ata_interrupt,
277 .irq_clear = ata_bmdma_irq_clear,
278
279 .port_start = ata_port_start,
280 .port_stop = ata_port_stop,
aa8f0dc6 281 .host_stop = ata_host_stop,
1da177e4
LT		 282};
283
d33f58b8
TH		 284static struct piix_map_db ich5_map_db = {
285 .mask = 0x7,
286 .map = {
287 /* PM PS SM SS MAP */
288 { P0, NA, P1, NA }, /* 000b */
289 { P1, NA, P0, NA }, /* 001b */
290 { RV, RV, RV, RV },
291 { RV, RV, RV, RV },
292 { P0, P1, IDE, IDE }, /* 100b */
293 { P1, P0, IDE, IDE }, /* 101b */
294 { IDE, IDE, P0, P1 }, /* 110b */
295 { IDE, IDE, P1, P0 }, /* 111b */
296 },
297};
298
299static struct piix_map_db ich6_map_db = {
300 .mask = 0x3,
301 .map = {
302 /* PM PS SM SS MAP */
79ea24e7 303 { P0, P2, P1, P3 }, /* 00b */
d33f58b8
TH		 304 { IDE, IDE, P1, P3 }, /* 01b */
305 { P0, P2, IDE, IDE }, /* 10b */
306 { RV, RV, RV, RV },
307 },
308};
309
310static struct piix_map_db ich6m_map_db = {
311 .mask = 0x3,
312 .map = {
313 /* PM PS SM SS MAP */
79ea24e7 314 { P0, P2, RV, RV }, /* 00b */
d33f58b8
TH		 315 { RV, RV, RV, RV },
316 { P0, P2, IDE, IDE }, /* 10b */
317 { RV, RV, RV, RV },
318 },
319};
320
1da177e4 321static struct ata_port_info piix_port_info[] = {
1d076e5b
TH		 322 /* piix4_pata */
323 {
324 .sht = &piix_sht,
325 .host_flags = ATA_FLAG_SLAVE_POSS,
326 .pio_mask = 0x1f, /* pio0-4 */
327#if 0
328 .mwdma_mask = 0x06, /* mwdma1-2 */
329#else
330 .mwdma_mask = 0x00, /* mwdma broken */
331#endif
332 .udma_mask = ATA_UDMA_MASK_40C,
333 .port_ops = &piix_pata_ops,
334 },
335
1da177e4
LT		 336 /* ich5_pata */
337 {
338 .sht = &piix_sht,
573db6b8 339 .host_flags = ATA_FLAG_SLAVE_POSS | PIIX_FLAG_CHECKINTR,
1da177e4
LT		 340 .pio_mask = 0x1f, /* pio0-4 */
341#if 0
342 .mwdma_mask = 0x06, /* mwdma1-2 */
343#else
344 .mwdma_mask = 0x00, /* mwdma broken */
345#endif
346 .udma_mask = 0x3f, /* udma0-5 */
347 .port_ops = &piix_pata_ops,
348 },
349
350 /* ich5_sata */
351 {
352 .sht = &piix_sht,
ccbe6d5e
TH		 353 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
354 PIIX_FLAG_CHECKINTR,
1da177e4
LT		 355 .pio_mask = 0x1f, /* pio0-4 */
356 .mwdma_mask = 0x07, /* mwdma0-2 */
357 .udma_mask = 0x7f, /* udma0-6 */
358 .port_ops = &piix_sata_ops,
d33f58b8 359 .private_data = &ich5_map_db,
1da177e4
LT		 360 },
361
1d076e5b 362 /* i6300esb_sata */
1da177e4
LT		 363 {
364 .sht = &piix_sht,
1d076e5b 365 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED |
219e6214 366 PIIX_FLAG_CHECKINTR | PIIX_FLAG_IGNORE_PCS,
1da177e4 367 .pio_mask = 0x1f, /* pio0-4 */
1d076e5b
TH		 368 .mwdma_mask = 0x07, /* mwdma0-2 */
369 .udma_mask = 0x7f, /* udma0-6 */
370 .port_ops = &piix_sata_ops,
d33f58b8 371 .private_data = &ich5_map_db,
1da177e4
LT		 372 },
373
374 /* ich6_sata */
375 {
376 .sht = &piix_sht,
ccbe6d5e 377 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
d33f58b8 378 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR,
1da177e4
LT		 379 .pio_mask = 0x1f, /* pio0-4 */
380 .mwdma_mask = 0x07, /* mwdma0-2 */
381 .udma_mask = 0x7f, /* udma0-6 */
382 .port_ops = &piix_sata_ops,
d33f58b8 383 .private_data = &ich6_map_db,
1da177e4
LT		 384 },
385
1c24a412 386 /* ich6_sata_ahci */
c368ca4e
JG		 387 {
388 .sht = &piix_sht,
ccbe6d5e 389 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
d33f58b8
TH		 390 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
391 PIIX_FLAG_AHCI,
c368ca4e
JG		 392 .pio_mask = 0x1f, /* pio0-4 */
393 .mwdma_mask = 0x07, /* mwdma0-2 */
394 .udma_mask = 0x7f, /* udma0-6 */
395 .port_ops = &piix_sata_ops,
d33f58b8 396 .private_data = &ich6_map_db,
c368ca4e 397 },
1d076e5b
TH		 398
399 /* ich6m_sata_ahci */
400 {
401 .sht = &piix_sht,
402 .host_flags = ATA_FLAG_SATA | PIIX_FLAG_COMBINED_ICH6 |
d33f58b8
TH		 403 PIIX_FLAG_CHECKINTR | PIIX_FLAG_SCR |
404 PIIX_FLAG_AHCI,
1d076e5b
TH		 405 .pio_mask = 0x1f, /* pio0-4 */
406 .mwdma_mask = 0x07, /* mwdma0-2 */
407 .udma_mask = 0x7f, /* udma0-6 */
408 .port_ops = &piix_sata_ops,
d33f58b8 409 .private_data = &ich6m_map_db,
1d076e5b 410 },
1da177e4
LT		 411};
412
413static struct pci_bits piix_enable_bits[] = {
414 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
415 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
416};
417
418MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
419MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
420MODULE_LICENSE("GPL");
421MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
422MODULE_VERSION(DRV_VERSION);
423
424/**
425 * piix_pata_cbl_detect - Probe host controller cable detect info
426 * @ap: Port for which cable detect info is desired
427 *
428 * Read 80c cable indicator from ATA PCI device's PCI config
429 * register. This register is normally set by firmware (BIOS).
430 *
431 * LOCKING:
432 * None (inherited from caller).
433 */
434static void piix_pata_cbl_detect(struct ata_port *ap)
435{
436 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
437 u8 tmp, mask;
438
439 /* no 80c support in host controller? */
440 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
441 goto cbl40;
442
443 /* check BIOS cable detect results */
444 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
445 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
446 if ((tmp & mask) == 0)
447 goto cbl40;
448
449 ap->cbl = ATA_CBL_PATA80;
450 return;
451
452cbl40:
453 ap->cbl = ATA_CBL_PATA40;
454 ap->udma_mask &= ATA_UDMA_MASK_40C;
455}
456
457/**
573db6b8
TH		 458 * piix_pata_probeinit - probeinit for PATA host controller
459 * @ap: Target port
1da177e4 460 *
573db6b8 461 * Probeinit including cable detection.
1da177e4
LT		 462 *
463 * LOCKING:
464 * None (inherited from caller).
465 */
573db6b8
TH		 466static void piix_pata_probeinit(struct ata_port *ap)
467{
468 piix_pata_cbl_detect(ap);
469 ata_std_probeinit(ap);
470}
1da177e4 471
573db6b8
TH		 472/**
473 * piix_pata_probe_reset - Perform reset on PATA port and classify
474 * @ap: Port to reset
475 * @classes: Resulting classes of attached devices
476 *
477 * Reset PATA phy and classify attached devices.
478 *
479 * LOCKING:
480 * None (inherited from caller).
481 */
482static int piix_pata_probe_reset(struct ata_port *ap, unsigned int *classes)
1da177e4
LT		 483{
484 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
485
486 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
f15a1daf 487 ata_port_printk(ap, KERN_INFO, "port disabled. ignoring.\n");
573db6b8 488 return 0;
1da177e4
LT		 489 }
490
573db6b8
TH		 491 return ata_drive_probe_reset(ap, piix_pata_probeinit,
492 ata_std_softreset, NULL,
493 ata_std_postreset, classes);
1da177e4
LT		 494}
495
496/**
497 * piix_sata_probe - Probe PCI device for present SATA devices
498 * @ap: Port associated with the PCI device we wish to probe
499 *
d133ecab
TH		 500 * Reads and configures SATA PCI device's PCI config register
501 * Port Configuration and Status (PCS) to determine port and
502 * device availability.
1da177e4
LT		 503 *
504 * LOCKING:
505 * None (inherited from caller).
506 *
507 * RETURNS:
d133ecab 508 * Mask of avaliable devices on the port.
1da177e4 509 */
d133ecab 510static unsigned int piix_sata_probe (struct ata_port *ap)
1da177e4
LT		 511{
512 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
d133ecab
TH		 513 const unsigned int *map = ap->host_set->private_data;
514 int base = 2 * ap->hard_port_no;
515 unsigned int present_mask = 0;
516 int port, i;
1da177e4
LT		 517 u8 pcs;
518
1da177e4 519 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
d133ecab
TH		 520 DPRINTK("ata%u: ENTER, pcs=0x%x base=%d\n", ap->id, pcs, base);
521
522 /* enable all ports on this ap and wait for them to settle */
523 for (i = 0; i < 2; i++) {
524 port = map[base + i];
525 if (port >= 0)
526 pcs |= 1 << port;
527 }
1da177e4 528
d133ecab
TH		 529 pci_write_config_byte(pdev, ICH5_PCS, pcs);
530 msleep(100);
1da177e4 531
d133ecab
TH		 532 /* let's see which devices are present */
533 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
534
535 for (i = 0; i < 2; i++) {
536 port = map[base + i];
537 if (port < 0)
538 continue;
219e6214 539 if (ap->flags & PIIX_FLAG_IGNORE_PCS || pcs & 1 << (4 + port))
d133ecab
TH		 540 present_mask |= 1 << i;
541 else
542 pcs &= ~(1 << port);
1da177e4
LT		 543 }
544
d133ecab
TH		 545 /* disable offline ports on non-AHCI controllers */
546 if (!(ap->flags & PIIX_FLAG_AHCI))
547 pci_write_config_byte(pdev, ICH5_PCS, pcs);
548
549 DPRINTK("ata%u: LEAVE, pcs=0x%x present_mask=0x%x\n",
550 ap->id, pcs, present_mask);
551
552 return present_mask;
1da177e4
LT		 553}
554
555/**
ccbe6d5e
TH		 556 * piix_sata_probe_reset - Perform reset on SATA port and classify
557 * @ap: Port to reset
558 * @classes: Resulting classes of attached devices
1da177e4 559 *
ccbe6d5e 560 * Reset SATA phy and classify attached devices.
1da177e4
LT		 561 *
562 * LOCKING:
563 * None (inherited from caller).
564 */
ccbe6d5e 565static int piix_sata_probe_reset(struct ata_port *ap, unsigned int *classes)
1da177e4
LT		 566{
567 if (!piix_sata_probe(ap)) {
f15a1daf 568 ata_port_printk(ap, KERN_INFO, "SATA port has no device.\n");
ccbe6d5e 569 return 0;
1da177e4
LT		 570 }
571
ccbe6d5e
TH		 572 return ata_drive_probe_reset(ap, ata_std_probeinit,
573 ata_std_softreset, NULL,
574 ata_std_postreset, classes);
1da177e4
LT		 575}
576
577/**
578 * piix_set_piomode - Initialize host controller PATA PIO timings
579 * @ap: Port whose timings we are configuring
580 * @adev: um
1da177e4
LT		 581 *
582 * Set PIO mode for device, in host controller PCI config space.
583 *
584 * LOCKING:
585 * None (inherited from caller).
586 */
587
588static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
589{
590 unsigned int pio = adev->pio_mode - XFER_PIO_0;
591 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
592 unsigned int is_slave = (adev->devno != 0);
593 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
594 unsigned int slave_port = 0x44;
595 u16 master_data;
596 u8 slave_data;
597
598 static const /* ISP RTC */
599 u8 timings[][2] = { { 0, 0 },
600 { 0, 0 },
601 { 1, 0 },
602 { 2, 1 },
603 { 2, 3 }, };
604
605 pci_read_config_word(dev, master_port, &master_data);
606 if (is_slave) {
607 master_data |= 0x4000;
608 /* enable PPE, IE and TIME */
609 master_data |= 0x0070;
610 pci_read_config_byte(dev, slave_port, &slave_data);
611 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
612 slave_data |=
613 (timings[pio][0] << 2) |
614 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
615 } else {
616 master_data &= 0xccf8;
617 /* enable PPE, IE and TIME */
618 master_data |= 0x0007;
619 master_data |=
620 (timings[pio][0] << 12) |
621 (timings[pio][1] << 8);
622 }
623 pci_write_config_word(dev, master_port, master_data);
624 if (is_slave)
625 pci_write_config_byte(dev, slave_port, slave_data);
626}
627
628/**
629 * piix_set_dmamode - Initialize host controller PATA PIO timings
630 * @ap: Port whose timings we are configuring
631 * @adev: um
632 * @udma: udma mode, 0 - 6
633 *
634 * Set UDMA mode for device, in host controller PCI config space.
635 *
636 * LOCKING:
637 * None (inherited from caller).
638 */
639
640static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
641{
642 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
643 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
644 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
645 u8 speed = udma;
646 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
647 int a_speed = 3 << (drive_dn * 4);
648 int u_flag = 1 << drive_dn;
649 int v_flag = 0x01 << drive_dn;
650 int w_flag = 0x10 << drive_dn;
651 int u_speed = 0;
652 int sitre;
653 u16 reg4042, reg4a;
654 u8 reg48, reg54, reg55;
655
656 pci_read_config_word(dev, maslave, &reg4042);
657 DPRINTK("reg4042 = 0x%04x\n", reg4042);
658 sitre = (reg4042 & 0x4000) ? 1 : 0;
659 pci_read_config_byte(dev, 0x48, &reg48);
660 pci_read_config_word(dev, 0x4a, &reg4a);
661 pci_read_config_byte(dev, 0x54, &reg54);
662 pci_read_config_byte(dev, 0x55, &reg55);
663
664 switch(speed) {
665 case XFER_UDMA_4:
666 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
667 case XFER_UDMA_6:
668 case XFER_UDMA_5:
669 case XFER_UDMA_3:
670 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
671 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
672 case XFER_MW_DMA_2:
673 case XFER_MW_DMA_1: break;
674 default:
675 BUG();
676 return;
677 }
678
679 if (speed >= XFER_UDMA_0) {
680 if (!(reg48 & u_flag))
681 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
682 if (speed == XFER_UDMA_5) {
683 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
684 } else {
685 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
686 }
687 if ((reg4a & a_speed) != u_speed)
688 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
689 if (speed > XFER_UDMA_2) {
690 if (!(reg54 & v_flag))
691 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
692 } else
693 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
694 } else {
695 if (reg48 & u_flag)
696 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
697 if (reg4a & a_speed)
698 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
699 if (reg54 & v_flag)
700 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
701 if (reg55 & w_flag)
702 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
703 }
704}
705
1da177e4
LT		 706#define AHCI_PCI_BAR 5
707#define AHCI_GLOBAL_CTL 0x04
708#define AHCI_ENABLE (1 << 31)
709static int piix_disable_ahci(struct pci_dev *pdev)
710{
ea6ba10b 711 void __iomem *mmio;
1da177e4
LT		 712 u32 tmp;
713 int rc = 0;
714
715 /* BUG: pci_enable_device has not yet been called. This
716 * works because this device is usually set up by BIOS.
717 */
718
374b1873
JG		 719 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
720 !pci_resource_len(pdev, AHCI_PCI_BAR))
1da177e4 721 return 0;
7b6dbd68 722
374b1873 723 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1da177e4
LT		 724 if (!mmio)
725 return -ENOMEM;
7b6dbd68 726
1da177e4
LT		 727 tmp = readl(mmio + AHCI_GLOBAL_CTL);
728 if (tmp & AHCI_ENABLE) {
729 tmp &= ~AHCI_ENABLE;
730 writel(tmp, mmio + AHCI_GLOBAL_CTL);
731
732 tmp = readl(mmio + AHCI_GLOBAL_CTL);
733 if (tmp & AHCI_ENABLE)
734 rc = -EIO;
735 }
7b6dbd68 736
374b1873 737 pci_iounmap(pdev, mmio);
1da177e4
LT		 738 return rc;
739}
740
c621b140
AC		 741/**
742 * piix_check_450nx_errata - Check for problem 450NX setup
c893a3ae 743 * @ata_dev: the PCI device to check
2e9edbf8 744 *
c621b140
AC		 745 * Check for the present of 450NX errata #19 and errata #25. If
746 * they are found return an error code so we can turn off DMA
747 */
748
749static int __devinit piix_check_450nx_errata(struct pci_dev *ata_dev)
750{
751 struct pci_dev *pdev = NULL;
752 u16 cfg;
753 u8 rev;
754 int no_piix_dma = 0;
2e9edbf8 755
c621b140
AC		 756 while((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL)
757 {
758 /* Look for 450NX PXB. Check for problem configurations
759 A PCI quirk checks bit 6 already */
760 pci_read_config_byte(pdev, PCI_REVISION_ID, &rev);
761 pci_read_config_word(pdev, 0x41, &cfg);
762 /* Only on the original revision: IDE DMA can hang */
763 if(rev == 0x00)
764 no_piix_dma = 1;
765 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
766 else if(cfg & (1<<14) && rev < 5)
767 no_piix_dma = 2;
768 }
769 if(no_piix_dma)
770 dev_printk(KERN_WARNING, &ata_dev->dev, "450NX errata present, disabling IDE DMA.\n");
771 if(no_piix_dma == 2)
772 dev_printk(KERN_WARNING, &ata_dev->dev, "A BIOS update may resolve this.\n");
773 return no_piix_dma;
2e9edbf8 774}
c621b140 775
d33f58b8
TH		 776static void __devinit piix_init_sata_map(struct pci_dev *pdev,
777 struct ata_port_info *pinfo)
778{
779 struct piix_map_db *map_db = pinfo[0].private_data;
780 const unsigned int *map;
781 int i, invalid_map = 0;
782 u8 map_value;
783
784 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
785
786 map = map_db->map[map_value & map_db->mask];
787
788 dev_printk(KERN_INFO, &pdev->dev, "MAP [");
789 for (i = 0; i < 4; i++) {
790 switch (map[i]) {
791 case RV:
792 invalid_map = 1;
793 printk(" XX");
794 break;
795
796 case NA:
797 printk(" --");
798 break;
799
800 case IDE:
801 WARN_ON((i & 1) || map[i + 1] != IDE);
802 pinfo[i / 2] = piix_port_info[ich5_pata];
803 i++;
804 printk(" IDE IDE");
805 break;
806
807 default:
808 printk(" P%d", map[i]);
809 if (i & 1)
810 pinfo[i / 2].host_flags |= ATA_FLAG_SLAVE_POSS;
811 break;
812 }
813 }
814 printk(" ]\n");
815
816 if (invalid_map)
817 dev_printk(KERN_ERR, &pdev->dev,
818 "invalid MAP value %u\n", map_value);
819
820 pinfo[0].private_data = (void *)map;
821 pinfo[1].private_data = (void *)map;
822}
823
1da177e4
LT		 824/**
825 * piix_init_one - Register PIIX ATA PCI device with kernel services
826 * @pdev: PCI device to register
827 * @ent: Entry in piix_pci_tbl matching with @pdev
828 *
829 * Called from kernel PCI layer. We probe for combined mode (sigh),
830 * and then hand over control to libata, for it to do the rest.
831 *
832 * LOCKING:
833 * Inherited from PCI layer (may sleep).
834 *
835 * RETURNS:
836 * Zero on success, or -ERRNO value.
837 */
838
839static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
840{
841 static int printed_version;
d33f58b8
TH		 842 struct ata_port_info port_info[2];
843 struct ata_port_info *ppinfo[2] = { &port_info[0], &port_info[1] };
ff0fc146 844 unsigned long host_flags;
1da177e4
LT		 845
846 if (!printed_version++)
6248e647
JG		 847 dev_printk(KERN_DEBUG, &pdev->dev,
848 "version " DRV_VERSION "\n");
1da177e4
LT		 849
850 /* no hotplugging support (FIXME) */
851 if (!in_module_init)
852 return -ENODEV;
853
d33f58b8
TH		 854 port_info[0] = piix_port_info[ent->driver_data];
855 port_info[1] = piix_port_info[ent->driver_data];
1da177e4 856
d33f58b8 857 host_flags = port_info[0].host_flags;
ff0fc146
TH		 858
859 if (host_flags & PIIX_FLAG_AHCI) {
8a60a071
JG		 860 u8 tmp;
861 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
862 if (tmp == PIIX_AHCI_DEVICE) {
863 int rc = piix_disable_ahci(pdev);
864 if (rc)
865 return rc;
866 }
1da177e4
LT		 867 }
868
d33f58b8
TH		 869 /* Initialize SATA map */
870 if (host_flags & ATA_FLAG_SATA)
871 piix_init_sata_map(pdev, port_info);
1da177e4
LT		 872
873 /* On ICH5, some BIOSen disable the interrupt using the
874 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
875 * On ICH6, this bit has the same effect, but only when
876 * MSI is disabled (and it is disabled, as we don't use
877 * message-signalled interrupts currently).
878 */
ff0fc146 879 if (host_flags & PIIX_FLAG_CHECKINTR)
a04ce0ff 880 pci_intx(pdev, 1);
1da177e4 881
c621b140
AC		 882 if (piix_check_450nx_errata(pdev)) {
883 /* This writes into the master table but it does not
884 really matter for this errata as we will apply it to
885 all the PIIX devices on the board */
d33f58b8
TH		 886 port_info[0].mwdma_mask = 0;
887 port_info[0].udma_mask = 0;
888 port_info[1].mwdma_mask = 0;
889 port_info[1].udma_mask = 0;
c621b140 890 }
d33f58b8 891 return ata_pci_init_one(pdev, ppinfo, 2);
1da177e4
LT		 892}
893
1da177e4
LT		 894static int __init piix_init(void)
895{
896 int rc;
897
898 DPRINTK("pci_module_init\n");
899 rc = pci_module_init(&piix_pci_driver);
900 if (rc)
901 return rc;
902
903 in_module_init = 0;
904
905 DPRINTK("done\n");
906 return 0;
907}
908
1da177e4
LT		 909static void __exit piix_exit(void)
910{
911 pci_unregister_driver(&piix_pci_driver);
912}
913
914module_init(piix_init);
915module_exit(piix_exit);
916
Linux 6.x block layer and io_uring tree(s)