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[linux-block.git] / drivers / scsi / arcmsr / arcmsr_hba.c
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1c57e86d
EC		 1/*
2*******************************************************************************
3** O.S : Linux
4** FILE NAME : arcmsr_hba.c
aaa64f69
CH		 5** BY : Nick Cheng, C.L. Huang
6** Description: SCSI RAID Device Driver for Areca RAID Controller
1c57e86d 7*******************************************************************************
aaa64f69 8** Copyright (C) 2002 - 2014, Areca Technology Corporation All rights reserved
1c57e86d
EC		 9**
10** Web site: www.areca.com.tw
1a4f550a 11** E-mail: support@areca.com.tw
1c57e86d
EC		 12**
13** This program is free software; you can redistribute it and/or modify
14** it under the terms of the GNU General Public License version 2 as
15** published by the Free Software Foundation.
16** This program is distributed in the hope that it will be useful,
17** but WITHOUT ANY WARRANTY; without even the implied warranty of
18** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19** GNU General Public License for more details.
20*******************************************************************************
21** Redistribution and use in source and binary forms, with or without
22** modification, are permitted provided that the following conditions
23** are met:
24** 1. Redistributions of source code must retain the above copyright
25** notice, this list of conditions and the following disclaimer.
26** 2. Redistributions in binary form must reproduce the above copyright
27** notice, this list of conditions and the following disclaimer in the
28** documentation and/or other materials provided with the distribution.
29** 3. The name of the author may not be used to endorse or promote products
30** derived from this software without specific prior written permission.
31**
32** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
33** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
34** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
35** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
36** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
37** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
39** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
41** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42*******************************************************************************
43** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
dade67f4 44** Firmware Specification, see Documentation/scsi/arcmsr_spec.rst
1c57e86d
EC		 45*******************************************************************************
46*/
47#include <linux/module.h>
48#include <linux/reboot.h>
49#include <linux/spinlock.h>
50#include <linux/pci_ids.h>
51#include <linux/interrupt.h>
52#include <linux/moduleparam.h>
53#include <linux/errno.h>
54#include <linux/types.h>
55#include <linux/delay.h>
56#include <linux/dma-mapping.h>
57#include <linux/timer.h>
a7c8962b 58#include <linux/slab.h>
1c57e86d 59#include <linux/pci.h>
a1f6e021 60#include <linux/aer.h>
2e9feb43 61#include <linux/circ_buf.h>
1c57e86d
EC		 62#include <asm/dma.h>
63#include <asm/io.h>
7c0f6ba6 64#include <linux/uaccess.h>
1c57e86d
EC		 65#include <scsi/scsi_host.h>
66#include <scsi/scsi.h>
67#include <scsi/scsi_cmnd.h>
68#include <scsi/scsi_tcq.h>
69#include <scsi/scsi_device.h>
70#include <scsi/scsi_transport.h>
71#include <scsi/scsicam.h>
72#include "arcmsr.h"
aaa64f69
CH		 73MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>");
74MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver");
1c57e86d
EC		 75MODULE_LICENSE("Dual BSD/GPL");
76MODULE_VERSION(ARCMSR_DRIVER_VERSION);
8b7eb86f 77
07640404
CH		 78static int msix_enable = 1;
79module_param(msix_enable, int, S_IRUGO);
80MODULE_PARM_DESC(msix_enable, "Enable MSI-X interrupt(0 ~ 1), msix_enable=1(enable), =0(disable)");
81
a18686eb
CH		 82static int msi_enable = 1;
83module_param(msi_enable, int, S_IRUGO);
84MODULE_PARM_DESC(msi_enable, "Enable MSI interrupt(0 ~ 1), msi_enable=1(enable), =0(disable)");
85
dd6206e1
CH		 86static int host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD;
87module_param(host_can_queue, int, S_IRUGO);
88MODULE_PARM_DESC(host_can_queue, " adapter queue depth(32 ~ 1024), default is 128");
89
abf33d83
CH		 90static int cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN;
91module_param(cmd_per_lun, int, S_IRUGO);
92MODULE_PARM_DESC(cmd_per_lun, " device queue depth(1 ~ 128), default is 32");
93
7ec7261f
CH		 94static int dma_mask_64 = 0;
95module_param(dma_mask_64, int, S_IRUGO);
96MODULE_PARM_DESC(dma_mask_64, " set DMA mask to 64 bits(0 ~ 1), dma_mask_64=1(64 bits), =0(32 bits)");
97
b416c099
CH		 98static int set_date_time = 0;
99module_param(set_date_time, int, S_IRUGO);
100MODULE_PARM_DESC(set_date_time, " send date, time to iop(0 ~ 1), set_date_time=1(enable), default(=0) is disable");
101
8b7eb86f
TH		 102#define ARCMSR_SLEEPTIME 10
103#define ARCMSR_RETRYCOUNT 12
104
c10b1d54 105static wait_queue_head_t wait_q;
1a4f550a
NC		 106static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
107 struct scsi_cmnd *cmd);
108static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
1c57e86d
EC		 109static int arcmsr_abort(struct scsi_cmnd *);
110static int arcmsr_bus_reset(struct scsi_cmnd *);
111static int arcmsr_bios_param(struct scsi_device *sdev,
1a4f550a 112 struct block_device *bdev, sector_t capacity, int *info);
f281233d 113static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1c57e86d
EC		 114static int arcmsr_probe(struct pci_dev *pdev,
115 const struct pci_device_id *id);
61cda87f
CH		 116static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state);
117static int arcmsr_resume(struct pci_dev *pdev);
1c57e86d
EC		 118static void arcmsr_remove(struct pci_dev *pdev);
119static void arcmsr_shutdown(struct pci_dev *pdev);
120static void arcmsr_iop_init(struct AdapterControlBlock *acb);
121static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
1a4f550a 122static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
61cda87f
CH		 123static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
124 u32 intmask_org);
1c57e86d 125static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
626fa32c
CH		 126static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb);
127static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb);
e99e88a9 128static void arcmsr_request_device_map(struct timer_list *t);
36b83ded 129static void arcmsr_message_isr_bh_fn(struct work_struct *work);
ae52e7f0 130static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
36b83ded 131static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
626fa32c 132static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB);
5b37479a 133static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb);
23509024
CH		 134static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb);
135static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb);
cdd3cb15 136static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
1c57e86d
EC		 137static const char *arcmsr_info(struct Scsi_Host *);
138static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
b4eb6ae9 139static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *);
7e315ffd 140static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb);
b416c099 141static void arcmsr_set_iop_datetime(struct timer_list *);
db5ed4df 142static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth)
1c57e86d
EC		 143{
144 if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
145 queue_depth = ARCMSR_MAX_CMD_PERLUN;
db5ed4df 146 return scsi_change_queue_depth(sdev, queue_depth);
1c57e86d
EC		 147}
148
149static struct scsi_host_template arcmsr_scsi_host_template = {
150 .module = THIS_MODULE,
aaa64f69 151 .name = "Areca SAS/SATA RAID driver",
1c57e86d
EC		 152 .info = arcmsr_info,
153 .queuecommand = arcmsr_queue_command,
a3de4b58 154 .eh_abort_handler = arcmsr_abort,
1c57e86d
EC		 155 .eh_bus_reset_handler = arcmsr_bus_reset,
156 .bios_param = arcmsr_bios_param,
157 .change_queue_depth = arcmsr_adjust_disk_queue_depth,
dd6206e1 158 .can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD,
a3de4b58
CH		 159 .this_id = ARCMSR_SCSI_INITIATOR_ID,
160 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
161 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
abf33d83 162 .cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN,
1c57e86d 163 .shost_attrs = arcmsr_host_attrs,
54b2b50c 164 .no_write_same = 1,
1c57e86d 165};
8b7c9942 166
1c57e86d 167static struct pci_device_id arcmsr_device_id_table[] = {
8b7c9942
CH		 168 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110),
169 .driver_data = ACB_ADAPTER_TYPE_A},
170 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120),
171 .driver_data = ACB_ADAPTER_TYPE_A},
172 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130),
173 .driver_data = ACB_ADAPTER_TYPE_A},
174 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160),
175 .driver_data = ACB_ADAPTER_TYPE_A},
176 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170),
177 .driver_data = ACB_ADAPTER_TYPE_A},
178 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200),
179 .driver_data = ACB_ADAPTER_TYPE_B},
180 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201),
181 .driver_data = ACB_ADAPTER_TYPE_B},
182 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202),
183 .driver_data = ACB_ADAPTER_TYPE_B},
7e315ffd
CH		 184 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1203),
185 .driver_data = ACB_ADAPTER_TYPE_B},
8b7c9942
CH		 186 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210),
187 .driver_data = ACB_ADAPTER_TYPE_A},
5b37479a
CH		 188 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214),
189 .driver_data = ACB_ADAPTER_TYPE_D},
8b7c9942
CH		 190 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220),
191 .driver_data = ACB_ADAPTER_TYPE_A},
192 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230),
193 .driver_data = ACB_ADAPTER_TYPE_A},
194 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260),
195 .driver_data = ACB_ADAPTER_TYPE_A},
196 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270),
197 .driver_data = ACB_ADAPTER_TYPE_A},
198 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280),
199 .driver_data = ACB_ADAPTER_TYPE_A},
200 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380),
201 .driver_data = ACB_ADAPTER_TYPE_A},
202 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381),
203 .driver_data = ACB_ADAPTER_TYPE_A},
204 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680),
205 .driver_data = ACB_ADAPTER_TYPE_A},
206 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681),
207 .driver_data = ACB_ADAPTER_TYPE_A},
208 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880),
209 .driver_data = ACB_ADAPTER_TYPE_C},
23509024
CH		 210 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1884),
211 .driver_data = ACB_ADAPTER_TYPE_E},
1c57e86d
EC		 212 {0, 0}, /* Terminating entry */
213};
214MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
8b7c9942 215
1c57e86d
EC		 216static struct pci_driver arcmsr_pci_driver = {
217 .name = "arcmsr",
a3de4b58 218 .id_table = arcmsr_device_id_table,
1c57e86d
EC		 219 .probe = arcmsr_probe,
220 .remove = arcmsr_remove,
61cda87f
CH		 221 .suspend = arcmsr_suspend,
222 .resume = arcmsr_resume,
a1f6e021 223 .shutdown = arcmsr_shutdown,
1c57e86d 224};
cdd3cb15
NC		 225/*
226****************************************************************************
227****************************************************************************
228*/
1c57e86d 229
609d0858 230static void arcmsr_free_io_queue(struct AdapterControlBlock *acb)
ae52e7f0
NC		 231{
232 switch (acb->adapter_type) {
5b37479a 233 case ACB_ADAPTER_TYPE_B:
23509024
CH		 234 case ACB_ADAPTER_TYPE_D:
235 case ACB_ADAPTER_TYPE_E: {
381d66da 236 dma_free_coherent(&acb->pdev->dev, acb->ioqueue_size,
6e38adfc
CH		 237 acb->dma_coherent2, acb->dma_coherent_handle2);
238 break;
ae52e7f0
NC		 239 }
240 }
241}
242
243static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
244{
245 struct pci_dev *pdev = acb->pdev;
cdd3cb15 246 switch (acb->adapter_type){
ae52e7f0 247 case ACB_ADAPTER_TYPE_A:{
cdd3cb15 248 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
ae52e7f0
NC		 249 if (!acb->pmuA) {
250 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
251 return false;
252 }
253 break;
254 }
255 case ACB_ADAPTER_TYPE_B:{
256 void __iomem *mem_base0, *mem_base1;
257 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
258 if (!mem_base0) {
259 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
260 return false;
261 }
262 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
263 if (!mem_base1) {
264 iounmap(mem_base0);
265 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
266 return false;
267 }
268 acb->mem_base0 = mem_base0;
269 acb->mem_base1 = mem_base1;
cdd3cb15
NC		 270 break;
271 }
272 case ACB_ADAPTER_TYPE_C:{
4bdc0d67 273 acb->pmuC = ioremap(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
cdd3cb15
NC		 274 if (!acb->pmuC) {
275 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
276 return false;
277 }
278 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
279 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
280 return true;
281 }
282 break;
ae52e7f0 283 }
5b37479a
CH		 284 case ACB_ADAPTER_TYPE_D: {
285 void __iomem *mem_base0;
18bc435e 286 unsigned long addr, range;
5b37479a
CH		 287
288 addr = (unsigned long)pci_resource_start(pdev, 0);
289 range = pci_resource_len(pdev, 0);
92b19ff5 290 mem_base0 = ioremap(addr, range);
5b37479a
CH		 291 if (!mem_base0) {
292 pr_notice("arcmsr%d: memory mapping region fail\n",
293 acb->host->host_no);
294 return false;
295 }
296 acb->mem_base0 = mem_base0;
297 break;
298 }
23509024
CH		 299 case ACB_ADAPTER_TYPE_E: {
300 acb->pmuE = ioremap(pci_resource_start(pdev, 1),
301 pci_resource_len(pdev, 1));
302 if (!acb->pmuE) {
303 pr_notice("arcmsr%d: memory mapping region fail \n",
304 acb->host->host_no);
305 return false;
306 }
307 writel(0, &acb->pmuE->host_int_status); /*clear interrupt*/
308 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell); /* synchronize doorbell to 0 */
309 acb->in_doorbell = 0;
310 acb->out_doorbell = 0;
311 break;
312 }
ae52e7f0
NC		 313 }
314 return true;
315}
316
317static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
318{
319 switch (acb->adapter_type) {
cdd3cb15
NC		 320 case ACB_ADAPTER_TYPE_A:{
321 iounmap(acb->pmuA);
322 }
323 break;
324 case ACB_ADAPTER_TYPE_B:{
325 iounmap(acb->mem_base0);
326 iounmap(acb->mem_base1);
327 }
328
329 break;
330 case ACB_ADAPTER_TYPE_C:{
331 iounmap(acb->pmuC);
332 }
5b37479a
CH		 333 break;
334 case ACB_ADAPTER_TYPE_D:
335 iounmap(acb->mem_base0);
336 break;
23509024
CH		 337 case ACB_ADAPTER_TYPE_E:
338 iounmap(acb->pmuE);
339 break;
ae52e7f0
NC		 340 }
341}
342
7d12e780 343static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
1c57e86d
EC		 344{
345 irqreturn_t handle_state;
1a4f550a 346 struct AdapterControlBlock *acb = dev_id;
1c57e86d 347
1c57e86d 348 handle_state = arcmsr_interrupt(acb);
1c57e86d
EC		 349 return handle_state;
350}
351
352static int arcmsr_bios_param(struct scsi_device *sdev,
353 struct block_device *bdev, sector_t capacity, int *geom)
354{
a10183d7
CH		 355 int heads, sectors, cylinders, total_capacity;
356
357 if (scsi_partsize(bdev, capacity, geom))
358 return 0;
1c57e86d 359
1c57e86d
EC		 360 total_capacity = capacity;
361 heads = 64;
362 sectors = 32;
363 cylinders = total_capacity / (heads * sectors);
364 if (cylinders > 1024) {
365 heads = 255;
366 sectors = 63;
367 cylinders = total_capacity / (heads * sectors);
368 }
369 geom[0] = heads;
370 geom[1] = sectors;
371 geom[2] = cylinders;
372 return 0;
373}
374
626fa32c 375static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb)
ae52e7f0
NC		 376{
377 struct MessageUnit_A __iomem *reg = acb->pmuA;
8b7eb86f
TH		 378 int i;
379
380 for (i = 0; i < 2000; i++) {
381 if (readl(&reg->outbound_intstatus) &
382 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
383 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
384 &reg->outbound_intstatus);
385 return true;
386 }
387 msleep(10);
388 } /* max 20 seconds */
ae52e7f0 389
cdd3cb15 390 return false;
ae52e7f0
NC		 391}
392
626fa32c 393static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb)
1a4f550a 394{
ae52e7f0 395 struct MessageUnit_B *reg = acb->pmuB;
8b7eb86f
TH		 396 int i;
397
398 for (i = 0; i < 2000; i++) {
399 if (readl(reg->iop2drv_doorbell)
400 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
401 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
402 reg->iop2drv_doorbell);
403 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
404 reg->drv2iop_doorbell);
405 return true;
406 }
407 msleep(10);
408 } /* max 20 seconds */
ae52e7f0 409
cdd3cb15 410 return false;
ae52e7f0
NC		 411}
412
626fa32c 413static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB)
cdd3cb15 414{
c10b1d54 415 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
8b7eb86f
TH		 416 int i;
417
418 for (i = 0; i < 2000; i++) {
419 if (readl(&phbcmu->outbound_doorbell)
420 & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
421 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
422 &phbcmu->outbound_doorbell_clear); /*clear interrupt*/
423 return true;
424 }
425 msleep(10);
426 } /* max 20 seconds */
427
cdd3cb15
NC		 428 return false;
429}
8b7eb86f 430
5b37479a
CH		 431static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB)
432{
433 struct MessageUnit_D *reg = pACB->pmuD;
434 int i;
435
436 for (i = 0; i < 2000; i++) {
437 if (readl(reg->outbound_doorbell)
438 & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
439 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
440 reg->outbound_doorbell);
441 return true;
442 }
443 msleep(10);
444 } /* max 20 seconds */
445 return false;
446}
447
23509024
CH		 448static bool arcmsr_hbaE_wait_msgint_ready(struct AdapterControlBlock *pACB)
449{
450 int i;
451 uint32_t read_doorbell;
452 struct MessageUnit_E __iomem *phbcmu = pACB->pmuE;
453
454 for (i = 0; i < 2000; i++) {
455 read_doorbell = readl(&phbcmu->iobound_doorbell);
456 if ((read_doorbell ^ pACB->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
457 writel(0, &phbcmu->host_int_status); /*clear interrupt*/
458 pACB->in_doorbell = read_doorbell;
459 return true;
460 }
461 msleep(10);
462 } /* max 20 seconds */
463 return false;
464}
465
626fa32c 466static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb)
ae52e7f0
NC		 467{
468 struct MessageUnit_A __iomem *reg = acb->pmuA;
469 int retry_count = 30;
ae52e7f0
NC		 470 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
471 do {
626fa32c 472 if (arcmsr_hbaA_wait_msgint_ready(acb))
ae52e7f0
NC		 473 break;
474 else {
475 retry_count--;
476 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
477 timeout, retry count down = %d \n", acb->host->host_no, retry_count);
478 }
479 } while (retry_count != 0);
480}
481
626fa32c 482static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb)
ae52e7f0
NC		 483{
484 struct MessageUnit_B *reg = acb->pmuB;
485 int retry_count = 30;
ae52e7f0
NC		 486 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
487 do {
626fa32c 488 if (arcmsr_hbaB_wait_msgint_ready(acb))
ae52e7f0
NC		 489 break;
490 else {
491 retry_count--;
492 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
493 timeout,retry count down = %d \n", acb->host->host_no, retry_count);
494 }
495 } while (retry_count != 0);
496}
497
626fa32c 498static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB)
cdd3cb15 499{
c10b1d54 500 struct MessageUnit_C __iomem *reg = pACB->pmuC;
cdd3cb15
NC		 501 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
502 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
503 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
504 do {
626fa32c 505 if (arcmsr_hbaC_wait_msgint_ready(pACB)) {
cdd3cb15
NC		 506 break;
507 } else {
508 retry_count--;
509 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
510 timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
511 }
512 } while (retry_count != 0);
513 return;
514}
5b37479a
CH		 515
516static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB)
517{
518 int retry_count = 15;
519 struct MessageUnit_D *reg = pACB->pmuD;
520
521 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0);
522 do {
523 if (arcmsr_hbaD_wait_msgint_ready(pACB))
524 break;
525
526 retry_count--;
527 pr_notice("arcmsr%d: wait 'flush adapter "
528 "cache' timeout, retry count down = %d\n",
529 pACB->host->host_no, retry_count);
530 } while (retry_count != 0);
531}
532
23509024
CH		 533static void arcmsr_hbaE_flush_cache(struct AdapterControlBlock *pACB)
534{
535 int retry_count = 30;
536 struct MessageUnit_E __iomem *reg = pACB->pmuE;
537
538 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
539 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
540 writel(pACB->out_doorbell, &reg->iobound_doorbell);
541 do {
542 if (arcmsr_hbaE_wait_msgint_ready(pACB))
543 break;
544 retry_count--;
545 pr_notice("arcmsr%d: wait 'flush adapter "
546 "cache' timeout, retry count down = %d\n",
547 pACB->host->host_no, retry_count);
548 } while (retry_count != 0);
549}
550
ae52e7f0
NC		 551static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
552{
1a4f550a 553 switch (acb->adapter_type) {
1c57e86d 554
1a4f550a 555 case ACB_ADAPTER_TYPE_A: {
626fa32c 556 arcmsr_hbaA_flush_cache(acb);
ae52e7f0
NC		 557 }
558 break;
1a4f550a 559
ae52e7f0 560 case ACB_ADAPTER_TYPE_B: {
626fa32c 561 arcmsr_hbaB_flush_cache(acb);
1a4f550a 562 }
cdd3cb15
NC		 563 break;
564 case ACB_ADAPTER_TYPE_C: {
626fa32c 565 arcmsr_hbaC_flush_cache(acb);
cdd3cb15 566 }
5b37479a
CH		 567 break;
568 case ACB_ADAPTER_TYPE_D:
569 arcmsr_hbaD_flush_cache(acb);
570 break;
23509024
CH		 571 case ACB_ADAPTER_TYPE_E:
572 arcmsr_hbaE_flush_cache(acb);
573 break;
ae52e7f0
NC		 574 }
575}
1a4f550a 576
222f1189
CH		 577static void arcmsr_hbaB_assign_regAddr(struct AdapterControlBlock *acb)
578{
579 struct MessageUnit_B *reg = acb->pmuB;
580
581 if (acb->pdev->device == PCI_DEVICE_ID_ARECA_1203) {
582 reg->drv2iop_doorbell = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_1203);
583 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK_1203);
584 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_1203);
585 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK_1203);
586 } else {
587 reg->drv2iop_doorbell= MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL);
588 reg->drv2iop_doorbell_mask = MEM_BASE0(ARCMSR_DRV2IOP_DOORBELL_MASK);
589 reg->iop2drv_doorbell = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL);
590 reg->iop2drv_doorbell_mask = MEM_BASE0(ARCMSR_IOP2DRV_DOORBELL_MASK);
591 }
592 reg->message_wbuffer = MEM_BASE1(ARCMSR_MESSAGE_WBUFFER);
593 reg->message_rbuffer = MEM_BASE1(ARCMSR_MESSAGE_RBUFFER);
594 reg->message_rwbuffer = MEM_BASE1(ARCMSR_MESSAGE_RWBUFFER);
595}
596
597static void arcmsr_hbaD_assign_regAddr(struct AdapterControlBlock *acb)
598{
599 struct MessageUnit_D *reg = acb->pmuD;
600
601 reg->chip_id = MEM_BASE0(ARCMSR_ARC1214_CHIP_ID);
602 reg->cpu_mem_config = MEM_BASE0(ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION);
603 reg->i2o_host_interrupt_mask = MEM_BASE0(ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK);
604 reg->sample_at_reset = MEM_BASE0(ARCMSR_ARC1214_SAMPLE_RESET);
605 reg->reset_request = MEM_BASE0(ARCMSR_ARC1214_RESET_REQUEST);
606 reg->host_int_status = MEM_BASE0(ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS);
607 reg->pcief0_int_enable = MEM_BASE0(ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE);
608 reg->inbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE0);
609 reg->inbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_INBOUND_MESSAGE1);
610 reg->outbound_msgaddr0 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE0);
611 reg->outbound_msgaddr1 = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_MESSAGE1);
612 reg->inbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_INBOUND_DOORBELL);
613 reg->outbound_doorbell = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL);
614 reg->outbound_doorbell_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE);
615 reg->inboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW);
616 reg->inboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH);
617 reg->inboundlist_write_pointer = MEM_BASE0(ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER);
618 reg->outboundlist_base_low = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW);
619 reg->outboundlist_base_high = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH);
620 reg->outboundlist_copy_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER);
621 reg->outboundlist_read_pointer = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER);
622 reg->outboundlist_interrupt_cause = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE);
623 reg->outboundlist_interrupt_enable = MEM_BASE0(ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE);
624 reg->message_wbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_WBUFFER);
625 reg->message_rbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RBUFFER);
626 reg->msgcode_rwbuffer = MEM_BASE0(ARCMSR_ARC1214_MESSAGE_RWBUFFER);
627}
628
02040670
CH		 629static bool arcmsr_alloc_io_queue(struct AdapterControlBlock *acb)
630{
631 bool rtn = true;
632 void *dma_coherent;
633 dma_addr_t dma_coherent_handle;
634 struct pci_dev *pdev = acb->pdev;
635
636 switch (acb->adapter_type) {
637 case ACB_ADAPTER_TYPE_B: {
381d66da 638 acb->ioqueue_size = roundup(sizeof(struct MessageUnit_B), 32);
3e3153b0 639 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
02040670
CH		 640 &dma_coherent_handle, GFP_KERNEL);
641 if (!dma_coherent) {
642 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
643 return false;
644 }
645 acb->dma_coherent_handle2 = dma_coherent_handle;
646 acb->dma_coherent2 = dma_coherent;
222f1189
CH		 647 acb->pmuB = (struct MessageUnit_B *)dma_coherent;
648 arcmsr_hbaB_assign_regAddr(acb);
02040670
CH		 649 }
650 break;
651 case ACB_ADAPTER_TYPE_D: {
381d66da 652 acb->ioqueue_size = roundup(sizeof(struct MessageUnit_D), 32);
3e3153b0 653 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
02040670
CH		 654 &dma_coherent_handle, GFP_KERNEL);
655 if (!dma_coherent) {
656 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
657 return false;
658 }
659 acb->dma_coherent_handle2 = dma_coherent_handle;
660 acb->dma_coherent2 = dma_coherent;
222f1189
CH		 661 acb->pmuD = (struct MessageUnit_D *)dma_coherent;
662 arcmsr_hbaD_assign_regAddr(acb);
02040670
CH		 663 }
664 break;
23509024
CH		 665 case ACB_ADAPTER_TYPE_E: {
666 uint32_t completeQ_size;
667 completeQ_size = sizeof(struct deliver_completeQ) * ARCMSR_MAX_HBE_DONEQUEUE + 128;
381d66da 668 acb->ioqueue_size = roundup(completeQ_size, 32);
3e3153b0 669 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->ioqueue_size,
23509024
CH		 670 &dma_coherent_handle, GFP_KERNEL);
671 if (!dma_coherent){
672 pr_notice("arcmsr%d: DMA allocation failed\n", acb->host->host_no);
673 return false;
674 }
675 acb->dma_coherent_handle2 = dma_coherent_handle;
676 acb->dma_coherent2 = dma_coherent;
677 acb->pCompletionQ = dma_coherent;
381d66da 678 acb->completionQ_entry = acb->ioqueue_size / sizeof(struct deliver_completeQ);
23509024
CH		 679 acb->doneq_index = 0;
680 }
681 break;
02040670
CH		 682 default:
683 break;
684 }
685 return rtn;
686}
687
ae52e7f0
NC		 688static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
689{
cdd3cb15
NC		 690 struct pci_dev *pdev = acb->pdev;
691 void *dma_coherent;
692 dma_addr_t dma_coherent_handle;
693 struct CommandControlBlock *ccb_tmp;
694 int i = 0, j = 0;
7860a486 695 unsigned long cdb_phyaddr, next_ccb_phy;
87f76152 696 unsigned long roundup_ccbsize;
cdd3cb15
NC		 697 unsigned long max_xfer_len;
698 unsigned long max_sg_entrys;
7860a486 699 uint32_t firm_config_version, curr_phy_upper32;
87f76152 700
cdd3cb15
NC		 701 for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
702 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
703 acb->devstate[i][j] = ARECA_RAID_GONE;
704
705 max_xfer_len = ARCMSR_MAX_XFER_LEN;
706 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
707 firm_config_version = acb->firm_cfg_version;
708 if((firm_config_version & 0xFF) >= 3){
709 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
87f76152 710 max_sg_entrys = (max_xfer_len/4096);
cdd3cb15
NC		 711 }
712 acb->host->max_sectors = max_xfer_len/512;
713 acb->host->sg_tablesize = max_sg_entrys;
714 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
d076e4aa 715 acb->uncache_size = roundup_ccbsize * acb->maxFreeCCB;
222f1189 716 acb->uncache_size += acb->ioqueue_size;
cdd3cb15
NC		 717 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
718 if(!dma_coherent){
87f76152 719 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
cdd3cb15
NC		 720 return -ENOMEM;
721 }
722 acb->dma_coherent = dma_coherent;
723 acb->dma_coherent_handle = dma_coherent_handle;
724 memset(dma_coherent, 0, acb->uncache_size);
23509024 725 acb->ccbsize = roundup_ccbsize;
cdd3cb15 726 ccb_tmp = dma_coherent;
7860a486 727 curr_phy_upper32 = upper_32_bits(dma_coherent_handle);
cdd3cb15 728 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
d076e4aa 729 for(i = 0; i < acb->maxFreeCCB; i++){
7860a486 730 cdb_phyaddr = (unsigned long)dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
5b37479a
CH		 731 switch (acb->adapter_type) {
732 case ACB_ADAPTER_TYPE_A:
733 case ACB_ADAPTER_TYPE_B:
734 ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5;
735 break;
736 case ACB_ADAPTER_TYPE_C:
737 case ACB_ADAPTER_TYPE_D:
23509024 738 case ACB_ADAPTER_TYPE_E:
5b37479a
CH		 739 ccb_tmp->cdb_phyaddr = cdb_phyaddr;
740 break;
741 }
cdd3cb15
NC		 742 acb->pccb_pool[i] = ccb_tmp;
743 ccb_tmp->acb = acb;
23509024 744 ccb_tmp->smid = (u32)i << 16;
cdd3cb15 745 INIT_LIST_HEAD(&ccb_tmp->list);
7860a486
CH		 746 next_ccb_phy = dma_coherent_handle + roundup_ccbsize;
747 if (upper_32_bits(next_ccb_phy) != curr_phy_upper32) {
748 acb->maxFreeCCB = i;
749 acb->host->can_queue = i;
750 break;
751 }
752 else
753 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
cdd3cb15 754 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
7860a486 755 dma_coherent_handle = next_ccb_phy;
1a4f550a 756 }
222f1189
CH		 757 acb->dma_coherent_handle2 = dma_coherent_handle;
758 acb->dma_coherent2 = ccb_tmp;
759 switch (acb->adapter_type) {
760 case ACB_ADAPTER_TYPE_B:
761 acb->pmuB = (struct MessageUnit_B *)acb->dma_coherent2;
762 arcmsr_hbaB_assign_regAddr(acb);
763 break;
764 case ACB_ADAPTER_TYPE_D:
765 acb->pmuD = (struct MessageUnit_D *)acb->dma_coherent2;
766 arcmsr_hbaD_assign_regAddr(acb);
767 break;
768 case ACB_ADAPTER_TYPE_E:
769 acb->pCompletionQ = acb->dma_coherent2;
770 acb->completionQ_entry = acb->ioqueue_size / sizeof(struct deliver_completeQ);
771 acb->doneq_index = 0;
772 break;
773 }
1c57e86d
EC		 774 return 0;
775}
36b83ded 776
cdd3cb15
NC		 777static void arcmsr_message_isr_bh_fn(struct work_struct *work)
778{
12aad947
CH		 779 struct AdapterControlBlock *acb = container_of(work,
780 struct AdapterControlBlock, arcmsr_do_message_isr_bh);
781 char *acb_dev_map = (char *)acb->device_map;
782 uint32_t __iomem *signature = NULL;
783 char __iomem *devicemap = NULL;
784 int target, lun;
785 struct scsi_device *psdev;
786 char diff, temp;
787
5dd8b3e7 788 acb->acb_flags &= ~ACB_F_MSG_GET_CONFIG;
36b83ded 789 switch (acb->adapter_type) {
12aad947
CH		 790 case ACB_ADAPTER_TYPE_A: {
791 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 792
12aad947
CH		 793 signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
794 devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
cdd3cb15 795 break;
12aad947
CH		 796 }
797 case ACB_ADAPTER_TYPE_B: {
798 struct MessageUnit_B *reg = acb->pmuB;
799
800 signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
801 devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
802 break;
803 }
804 case ACB_ADAPTER_TYPE_C: {
805 struct MessageUnit_C __iomem *reg = acb->pmuC;
806
807 signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
808 devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
809 break;
810 }
5b37479a
CH		 811 case ACB_ADAPTER_TYPE_D: {
812 struct MessageUnit_D *reg = acb->pmuD;
813
814 signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
815 devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
816 break;
817 }
23509024
CH		 818 case ACB_ADAPTER_TYPE_E: {
819 struct MessageUnit_E __iomem *reg = acb->pmuE;
820
821 signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
822 devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
823 break;
824 }
12aad947
CH		 825 }
826 atomic_inc(&acb->rq_map_token);
827 if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG)
828 return;
829 for (target = 0; target < ARCMSR_MAX_TARGETID - 1;
830 target++) {
831 temp = readb(devicemap);
832 diff = (*acb_dev_map) ^ temp;
833 if (diff != 0) {
834 *acb_dev_map = temp;
835 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN;
836 lun++) {
837 if ((diff & 0x01) == 1 &&
838 (temp & 0x01) == 1) {
839 scsi_add_device(acb->host,
840 0, target, lun);
841 } else if ((diff & 0x01) == 1
842 && (temp & 0x01) == 0) {
843 psdev = scsi_device_lookup(acb->host,
844 0, target, lun);
845 if (psdev != NULL) {
846 scsi_remove_device(psdev);
847 scsi_device_put(psdev);
36b83ded 848 }
36b83ded 849 }
12aad947
CH		 850 temp >>= 1;
851 diff >>= 1;
36b83ded
NC		 852 }
853 }
12aad947
CH		 854 devicemap++;
855 acb_dev_map++;
36b83ded
NC		 856 }
857}
1c57e86d 858
1d1166ea
CH		 859static int
860arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb)
861{
68130c99
CH		 862 unsigned long flags;
863 int nvec, i;
864
07640404
CH		 865 if (msix_enable == 0)
866 goto msi_int0;
68130c99
CH		 867 nvec = pci_alloc_irq_vectors(pdev, 1, ARCMST_NUM_MSIX_VECTORS,
868 PCI_IRQ_MSIX);
869 if (nvec > 0) {
870 pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no);
871 flags = 0;
872 } else {
07640404 873msi_int0:
a18686eb
CH		 874 if (msi_enable == 1) {
875 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
876 if (nvec == 1) {
877 dev_info(&pdev->dev, "msi enabled\n");
878 goto msi_int1;
879 }
880 }
881 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_LEGACY);
68130c99
CH		 882 if (nvec < 1)
883 return FAILED;
a18686eb 884msi_int1:
68130c99
CH		 885 flags = IRQF_SHARED;
886 }
887
888 acb->vector_count = nvec;
889 for (i = 0; i < nvec; i++) {
890 if (request_irq(pci_irq_vector(pdev, i), arcmsr_do_interrupt,
891 flags, "arcmsr", acb)) {
1d1166ea 892 pr_warn("arcmsr%d: request_irq =%d failed!\n",
68130c99
CH		 893 acb->host->host_no, pci_irq_vector(pdev, i));
894 goto out_free_irq;
1d1166ea 895 }
1d1166ea 896 }
68130c99 897
1d1166ea 898 return SUCCESS;
68130c99
CH		 899out_free_irq:
900 while (--i >= 0)
901 free_irq(pci_irq_vector(pdev, i), acb);
902 pci_free_irq_vectors(pdev);
903 return FAILED;
1d1166ea
CH		 904}
905
ea331f30
CH		 906static void arcmsr_init_get_devmap_timer(struct AdapterControlBlock *pacb)
907{
908 INIT_WORK(&pacb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
909 atomic_set(&pacb->rq_map_token, 16);
910 atomic_set(&pacb->ante_token_value, 16);
911 pacb->fw_flag = FW_NORMAL;
912 timer_setup(&pacb->eternal_timer, arcmsr_request_device_map, 0);
913 pacb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
914 add_timer(&pacb->eternal_timer);
915}
916
b416c099
CH		 917static void arcmsr_init_set_datetime_timer(struct AdapterControlBlock *pacb)
918{
919 timer_setup(&pacb->refresh_timer, arcmsr_set_iop_datetime, 0);
920 pacb->refresh_timer.expires = jiffies + msecs_to_jiffies(60 * 1000);
921 add_timer(&pacb->refresh_timer);
922}
923
1d120c61
CH		 924static int arcmsr_set_dma_mask(struct AdapterControlBlock *acb)
925{
926 struct pci_dev *pcidev = acb->pdev;
927
928 if (IS_DMA64) {
929 if (((acb->adapter_type == ACB_ADAPTER_TYPE_A) && !dma_mask_64) ||
930 dma_set_mask(&pcidev->dev, DMA_BIT_MASK(64)))
931 goto dma32;
932 if (dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(64)) ||
933 dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(64))) {
934 printk("arcmsr: set DMA 64 mask failed\n");
935 return -ENXIO;
936 }
937 } else {
938dma32:
939 if (dma_set_mask(&pcidev->dev, DMA_BIT_MASK(32)) ||
940 dma_set_coherent_mask(&pcidev->dev, DMA_BIT_MASK(32)) ||
941 dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32))) {
942 printk("arcmsr: set DMA 32-bit mask failed\n");
943 return -ENXIO;
944 }
945 }
946 return 0;
947}
948
ae52e7f0 949static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1c57e86d
EC		 950{
951 struct Scsi_Host *host;
952 struct AdapterControlBlock *acb;
cdd3cb15 953 uint8_t bus,dev_fun;
1c57e86d 954 int error;
1c57e86d 955 error = pci_enable_device(pdev);
cdd3cb15 956 if(error){
ae52e7f0
NC		 957 return -ENODEV;
958 }
959 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
cdd3cb15
NC		 960 if(!host){
961 goto pci_disable_dev;
1c57e86d 962 }
ae52e7f0 963 init_waitqueue_head(&wait_q);
1c57e86d
EC		 964 bus = pdev->bus->number;
965 dev_fun = pdev->devfn;
ae52e7f0 966 acb = (struct AdapterControlBlock *) host->hostdata;
cdd3cb15 967 memset(acb,0,sizeof(struct AdapterControlBlock));
1c57e86d 968 acb->pdev = pdev;
1d120c61
CH		 969 acb->adapter_type = id->driver_data;
970 if (arcmsr_set_dma_mask(acb))
971 goto scsi_host_release;
ae52e7f0 972 acb->host = host;
1c57e86d 973 host->max_lun = ARCMSR_MAX_TARGETLUN;
cdd3cb15
NC		 974 host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
975 host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
dd6206e1
CH		 976 if ((host_can_queue < ARCMSR_MIN_OUTSTANDING_CMD) || (host_can_queue > ARCMSR_MAX_OUTSTANDING_CMD))
977 host_can_queue = ARCMSR_DEFAULT_OUTSTANDING_CMD;
978 host->can_queue = host_can_queue; /* max simultaneous cmds */
abf33d83
CH		 979 if ((cmd_per_lun < ARCMSR_MIN_CMD_PERLUN) || (cmd_per_lun > ARCMSR_MAX_CMD_PERLUN))
980 cmd_per_lun = ARCMSR_DEFAULT_CMD_PERLUN;
981 host->cmd_per_lun = cmd_per_lun;
1c57e86d
EC		 982 host->this_id = ARCMSR_SCSI_INITIATOR_ID;
983 host->unique_id = (bus << 8) | dev_fun;
ae52e7f0
NC		 984 pci_set_drvdata(pdev, host);
985 pci_set_master(pdev);
1c57e86d 986 error = pci_request_regions(pdev, "arcmsr");
cdd3cb15 987 if(error){
ae52e7f0 988 goto scsi_host_release;
1c57e86d 989 }
ae52e7f0
NC		 990 spin_lock_init(&acb->eh_lock);
991 spin_lock_init(&acb->ccblist_lock);
5b37479a
CH		 992 spin_lock_init(&acb->postq_lock);
993 spin_lock_init(&acb->doneq_lock);
bb263c4e
CH		 994 spin_lock_init(&acb->rqbuffer_lock);
995 spin_lock_init(&acb->wqbuffer_lock);
1c57e86d 996 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
cdd3cb15
NC		 997 ACB_F_MESSAGE_RQBUFFER_CLEARED |
998 ACB_F_MESSAGE_WQBUFFER_READED);
1c57e86d
EC		 999 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
1000 INIT_LIST_HEAD(&acb->ccb_free_list);
ae52e7f0 1001 error = arcmsr_remap_pciregion(acb);
cdd3cb15 1002 if(!error){
ae52e7f0
NC		 1003 goto pci_release_regs;
1004 }
02040670
CH		 1005 error = arcmsr_alloc_io_queue(acb);
1006 if (!error)
1007 goto unmap_pci_region;
ae52e7f0 1008 error = arcmsr_get_firmware_spec(acb);
cdd3cb15 1009 if(!error){
02040670 1010 goto free_hbb_mu;
ae52e7f0 1011 }
222f1189 1012 arcmsr_free_io_queue(acb);
1c57e86d 1013 error = arcmsr_alloc_ccb_pool(acb);
cdd3cb15 1014 if(error){
222f1189 1015 goto unmap_pci_region;
ae52e7f0 1016 }
1c57e86d 1017 error = scsi_add_host(host, &pdev->dev);
cdd3cb15 1018 if(error){
b4eb6ae9 1019 goto free_ccb_pool;
ae52e7f0 1020 }
1d1166ea 1021 if (arcmsr_request_irq(pdev, acb) == FAILED)
ae52e7f0 1022 goto scsi_host_remove;
1d1166ea 1023 arcmsr_iop_init(acb);
ea331f30 1024 arcmsr_init_get_devmap_timer(acb);
b416c099
CH		 1025 if (set_date_time)
1026 arcmsr_init_set_datetime_timer(acb);
cdd3cb15 1027 if(arcmsr_alloc_sysfs_attr(acb))
ae52e7f0 1028 goto out_free_sysfs;
b4eb6ae9 1029 scsi_scan_host(host);
1c57e86d 1030 return 0;
cdd3cb15 1031out_free_sysfs:
b416c099
CH		 1032 if (set_date_time)
1033 del_timer_sync(&acb->refresh_timer);
b4eb6ae9
CH		 1034 del_timer_sync(&acb->eternal_timer);
1035 flush_work(&acb->arcmsr_do_message_isr_bh);
ae52e7f0
NC		 1036 arcmsr_stop_adapter_bgrb(acb);
1037 arcmsr_flush_adapter_cache(acb);
b4eb6ae9
CH		 1038 arcmsr_free_irq(pdev, acb);
1039scsi_host_remove:
1040 scsi_remove_host(host);
1041free_ccb_pool:
1c57e86d 1042 arcmsr_free_ccb_pool(acb);
222f1189 1043 goto unmap_pci_region;
ae52e7f0 1044free_hbb_mu:
609d0858 1045 arcmsr_free_io_queue(acb);
ae52e7f0
NC		 1046unmap_pci_region:
1047 arcmsr_unmap_pciregion(acb);
1048pci_release_regs:
1c57e86d 1049 pci_release_regions(pdev);
ae52e7f0 1050scsi_host_release:
1c57e86d 1051 scsi_host_put(host);
ae52e7f0 1052pci_disable_dev:
1c57e86d 1053 pci_disable_device(pdev);
ae52e7f0 1054 return -ENODEV;
1a4f550a
NC		 1055}
1056
1d1166ea
CH		 1057static void arcmsr_free_irq(struct pci_dev *pdev,
1058 struct AdapterControlBlock *acb)
1059{
1060 int i;
1061
68130c99
CH		 1062 for (i = 0; i < acb->vector_count; i++)
1063 free_irq(pci_irq_vector(pdev, i), acb);
1064 pci_free_irq_vectors(pdev);
1d1166ea
CH		 1065}
1066
61cda87f
CH		 1067static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state)
1068{
61cda87f
CH		 1069 struct Scsi_Host *host = pci_get_drvdata(pdev);
1070 struct AdapterControlBlock *acb =
1071 (struct AdapterControlBlock *)host->hostdata;
1072
18bc435e 1073 arcmsr_disable_outbound_ints(acb);
61cda87f
CH		 1074 arcmsr_free_irq(pdev, acb);
1075 del_timer_sync(&acb->eternal_timer);
b416c099
CH		 1076 if (set_date_time)
1077 del_timer_sync(&acb->refresh_timer);
61cda87f
CH		 1078 flush_work(&acb->arcmsr_do_message_isr_bh);
1079 arcmsr_stop_adapter_bgrb(acb);
1080 arcmsr_flush_adapter_cache(acb);
1081 pci_set_drvdata(pdev, host);
1082 pci_save_state(pdev);
1083 pci_disable_device(pdev);
1084 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1085 return 0;
1086}
1087
1088static int arcmsr_resume(struct pci_dev *pdev)
1089{
61cda87f
CH		 1090 struct Scsi_Host *host = pci_get_drvdata(pdev);
1091 struct AdapterControlBlock *acb =
1092 (struct AdapterControlBlock *)host->hostdata;
1093
1094 pci_set_power_state(pdev, PCI_D0);
1095 pci_enable_wake(pdev, PCI_D0, 0);
1096 pci_restore_state(pdev);
1097 if (pci_enable_device(pdev)) {
1098 pr_warn("%s: pci_enable_device error\n", __func__);
1099 return -ENODEV;
1100 }
1d120c61
CH		 1101 if (arcmsr_set_dma_mask(acb))
1102 goto controller_unregister;
61cda87f
CH		 1103 pci_set_master(pdev);
1104 if (arcmsr_request_irq(pdev, acb) == FAILED)
1105 goto controller_stop;
afdda878
CH		 1106 switch (acb->adapter_type) {
1107 case ACB_ADAPTER_TYPE_B: {
1108 struct MessageUnit_B *reg = acb->pmuB;
317d0e02
CH		 1109 uint32_t i;
1110 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
1111 reg->post_qbuffer[i] = 0;
1112 reg->done_qbuffer[i] = 0;
1113 }
afdda878
CH		 1114 reg->postq_index = 0;
1115 reg->doneq_index = 0;
1116 break;
1117 }
1118 case ACB_ADAPTER_TYPE_E:
97fe2225
CH		 1119 writel(0, &acb->pmuE->host_int_status);
1120 writel(ARCMSR_HBEMU_DOORBELL_SYNC, &acb->pmuE->iobound_doorbell);
1121 acb->in_doorbell = 0;
1122 acb->out_doorbell = 0;
1123 acb->doneq_index = 0;
afdda878 1124 break;
97fe2225 1125 }
61cda87f 1126 arcmsr_iop_init(acb);
ea331f30 1127 arcmsr_init_get_devmap_timer(acb);
b416c099
CH		 1128 if (set_date_time)
1129 arcmsr_init_set_datetime_timer(acb);
61cda87f
CH		 1130 return 0;
1131controller_stop:
1132 arcmsr_stop_adapter_bgrb(acb);
1133 arcmsr_flush_adapter_cache(acb);
1134controller_unregister:
1135 scsi_remove_host(host);
1136 arcmsr_free_ccb_pool(acb);
1137 arcmsr_unmap_pciregion(acb);
1138 pci_release_regions(pdev);
1139 scsi_host_put(host);
1140 pci_disable_device(pdev);
1141 return -ENODEV;
1142}
1143
626fa32c 1144static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb)
1c57e86d 1145{
80da1adb 1146 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 1147 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
626fa32c 1148 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1a4f550a 1149 printk(KERN_NOTICE
626fa32c 1150 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
1a4f550a 1151 , acb->host->host_no);
cdd3cb15 1152 return false;
36b83ded 1153 }
cdd3cb15 1154 return true;
1a4f550a
NC		 1155}
1156
626fa32c 1157static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb)
1a4f550a 1158{
80da1adb 1159 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1160
ae52e7f0 1161 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
626fa32c 1162 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1c57e86d 1163 printk(KERN_NOTICE
626fa32c 1164 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
1c57e86d 1165 , acb->host->host_no);
cdd3cb15 1166 return false;
36b83ded 1167 }
cdd3cb15
NC		 1168 return true;
1169}
626fa32c 1170static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB)
cdd3cb15 1171{
c10b1d54 1172 struct MessageUnit_C __iomem *reg = pACB->pmuC;
cdd3cb15
NC		 1173 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
1174 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
626fa32c 1175 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
cdd3cb15 1176 printk(KERN_NOTICE
626fa32c 1177 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
cdd3cb15
NC		 1178 , pACB->host->host_no);
1179 return false;
1180 }
1181 return true;
1c57e86d 1182}
5b37479a
CH		 1183
1184static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB)
1185{
1186 struct MessageUnit_D *reg = pACB->pmuD;
1187
1188 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0);
1189 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
1190 pr_notice("arcmsr%d: wait 'abort all outstanding "
1191 "command' timeout\n", pACB->host->host_no);
1192 return false;
1193 }
1194 return true;
1195}
1196
23509024
CH		 1197static uint8_t arcmsr_hbaE_abort_allcmd(struct AdapterControlBlock *pACB)
1198{
1199 struct MessageUnit_E __iomem *reg = pACB->pmuE;
1200
1201 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
1202 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
1203 writel(pACB->out_doorbell, &reg->iobound_doorbell);
1204 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
1205 pr_notice("arcmsr%d: wait 'abort all outstanding "
1206 "command' timeout\n", pACB->host->host_no);
1207 return false;
1208 }
1209 return true;
1210}
1211
36b83ded 1212static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
1a4f550a 1213{
36b83ded 1214 uint8_t rtnval = 0;
1a4f550a
NC		 1215 switch (acb->adapter_type) {
1216 case ACB_ADAPTER_TYPE_A: {
626fa32c 1217 rtnval = arcmsr_hbaA_abort_allcmd(acb);
1a4f550a
NC		 1218 }
1219 break;
1220
1221 case ACB_ADAPTER_TYPE_B: {
626fa32c 1222 rtnval = arcmsr_hbaB_abort_allcmd(acb);
1a4f550a 1223 }
cdd3cb15
NC		 1224 break;
1225
1226 case ACB_ADAPTER_TYPE_C: {
626fa32c 1227 rtnval = arcmsr_hbaC_abort_allcmd(acb);
cdd3cb15 1228 }
5b37479a
CH		 1229 break;
1230
1231 case ACB_ADAPTER_TYPE_D:
1232 rtnval = arcmsr_hbaD_abort_allcmd(acb);
1233 break;
23509024
CH		 1234 case ACB_ADAPTER_TYPE_E:
1235 rtnval = arcmsr_hbaE_abort_allcmd(acb);
1236 break;
1a4f550a 1237 }
36b83ded 1238 return rtnval;
1a4f550a
NC		 1239}
1240
1c57e86d
EC		 1241static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
1242{
1c57e86d
EC		 1243 struct scsi_cmnd *pcmd = ccb->pcmd;
1244
deff2627 1245 scsi_dma_unmap(pcmd);
cdd3cb15 1246}
1c57e86d 1247
ae52e7f0 1248static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
1c57e86d
EC		 1249{
1250 struct AdapterControlBlock *acb = ccb->acb;
1251 struct scsi_cmnd *pcmd = ccb->pcmd;
ae52e7f0 1252 unsigned long flags;
ae52e7f0 1253 atomic_dec(&acb->ccboutstandingcount);
1c57e86d 1254 arcmsr_pci_unmap_dma(ccb);
1c57e86d 1255 ccb->startdone = ARCMSR_CCB_DONE;
ae52e7f0 1256 spin_lock_irqsave(&acb->ccblist_lock, flags);
1c57e86d 1257 list_add_tail(&ccb->list, &acb->ccb_free_list);
ae52e7f0 1258 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 1259 pcmd->scsi_done(pcmd);
1260}
1261
1a4f550a
NC		 1262static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
1263{
1264
1265 struct scsi_cmnd *pcmd = ccb->pcmd;
1266 struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
fa576b43 1267 pcmd->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
1a4f550a
NC		 1268 if (sensebuffer) {
1269 int sense_data_length =
b80ca4f7
FT		 1270 sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
1271 ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
1272 memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
1a4f550a
NC		 1273 memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
1274 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
1275 sensebuffer->Valid = 1;
fa576b43 1276 pcmd->result |= (DRIVER_SENSE << 24);
1a4f550a
NC		 1277 }
1278}
1279
1280static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
1281{
1282 u32 orig_mask = 0;
cdd3cb15 1283 switch (acb->adapter_type) {
1a4f550a 1284 case ACB_ADAPTER_TYPE_A : {
80da1adb 1285 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 1286 orig_mask = readl(&reg->outbound_intmask);
1a4f550a
NC		 1287 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
1288 &reg->outbound_intmask);
1289 }
1290 break;
1a4f550a 1291 case ACB_ADAPTER_TYPE_B : {
80da1adb 1292 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0
NC		 1293 orig_mask = readl(reg->iop2drv_doorbell_mask);
1294 writel(0, reg->iop2drv_doorbell_mask);
1a4f550a
NC		 1295 }
1296 break;
cdd3cb15 1297 case ACB_ADAPTER_TYPE_C:{
c10b1d54 1298 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15
NC		 1299 /* disable all outbound interrupt */
1300 orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
1301 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
1302 }
1303 break;
5b37479a
CH		 1304 case ACB_ADAPTER_TYPE_D: {
1305 struct MessageUnit_D *reg = acb->pmuD;
1306 /* disable all outbound interrupt */
1307 writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable);
1308 }
1309 break;
23509024
CH		 1310 case ACB_ADAPTER_TYPE_E: {
1311 struct MessageUnit_E __iomem *reg = acb->pmuE;
1312 orig_mask = readl(&reg->host_int_mask);
1313 writel(orig_mask | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR, &reg->host_int_mask);
1314 readl(&reg->host_int_mask); /* Dummy readl to force pci flush */
1315 }
1316 break;
1a4f550a
NC		 1317 }
1318 return orig_mask;
1319}
1320
cdd3cb15
NC		 1321static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
1322 struct CommandControlBlock *ccb, bool error)
1a4f550a 1323{
1a4f550a
NC		 1324 uint8_t id, lun;
1325 id = ccb->pcmd->device->id;
1326 lun = ccb->pcmd->device->lun;
cdd3cb15 1327 if (!error) {
1a4f550a
NC		 1328 if (acb->devstate[id][lun] == ARECA_RAID_GONE)
1329 acb->devstate[id][lun] = ARECA_RAID_GOOD;
7968f194
JL		 1330 ccb->pcmd->result = DID_OK << 16;
1331 arcmsr_ccb_complete(ccb);
cdd3cb15 1332 }else{
1a4f550a
NC		 1333 switch (ccb->arcmsr_cdb.DeviceStatus) {
1334 case ARCMSR_DEV_SELECT_TIMEOUT: {
1335 acb->devstate[id][lun] = ARECA_RAID_GONE;
1336 ccb->pcmd->result = DID_NO_CONNECT << 16;
ae52e7f0 1337 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 1338 }
1339 break;
1340
1341 case ARCMSR_DEV_ABORTED:
1342
1343 case ARCMSR_DEV_INIT_FAIL: {
1344 acb->devstate[id][lun] = ARECA_RAID_GONE;
1345 ccb->pcmd->result = DID_BAD_TARGET << 16;
ae52e7f0 1346 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 1347 }
1348 break;
1349
1350 case ARCMSR_DEV_CHECK_CONDITION: {
1351 acb->devstate[id][lun] = ARECA_RAID_GOOD;
1352 arcmsr_report_sense_info(ccb);
ae52e7f0 1353 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 1354 }
1355 break;
1356
1357 default:
cdd3cb15
NC		 1358 printk(KERN_NOTICE
1359 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
1360 but got unknown DeviceStatus = 0x%x \n"
1361 , acb->host->host_no
1362 , id
1363 , lun
1364 , ccb->arcmsr_cdb.DeviceStatus);
1365 acb->devstate[id][lun] = ARECA_RAID_GONE;
1366 ccb->pcmd->result = DID_NO_CONNECT << 16;
1367 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 1368 break;
1369 }
1370 }
1371}
1372
cdd3cb15 1373static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
1a4f550a 1374{
cdd3cb15
NC		 1375 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
1376 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
1377 struct scsi_cmnd *abortcmd = pCCB->pcmd;
1a4f550a
NC		 1378 if (abortcmd) {
1379 abortcmd->result |= DID_ABORT << 16;
cdd3cb15
NC		 1380 arcmsr_ccb_complete(pCCB);
1381 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
1382 acb->host->host_no, pCCB);
1a4f550a 1383 }
cdd3cb15 1384 return;
1a4f550a
NC		 1385 }
1386 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
1387 done acb = '0x%p'"
1388 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
1389 " ccboutstandingcount = %d \n"
1390 , acb->host->host_no
1391 , acb
cdd3cb15
NC		 1392 , pCCB
1393 , pCCB->acb
1394 , pCCB->startdone
1a4f550a 1395 , atomic_read(&acb->ccboutstandingcount));
9b44ffab 1396 return;
97b99127 1397 }
cdd3cb15 1398 arcmsr_report_ccb_state(acb, pCCB, error);
1a4f550a
NC		 1399}
1400
1401static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
1402{
1403 int i = 0;
9e386a55 1404 uint32_t flag_ccb;
cdd3cb15
NC		 1405 struct ARCMSR_CDB *pARCMSR_CDB;
1406 bool error;
1407 struct CommandControlBlock *pCCB;
18bc435e 1408 unsigned long ccb_cdb_phy;
9e386a55 1409
1a4f550a
NC		 1410 switch (acb->adapter_type) {
1411
1412 case ACB_ADAPTER_TYPE_A: {
80da1adb 1413 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 1414 uint32_t outbound_intstatus;
80da1adb 1415 outbound_intstatus = readl(&reg->outbound_intstatus) &
1a4f550a
NC		 1416 acb->outbound_int_enable;
1417 /*clear and abort all outbound posted Q*/
1418 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
cdd3cb15 1419 while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
e4587f45 1420 && (i++ < acb->maxOutstanding)) {
9e386a55
CH		 1421 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
1422 if (acb->cdb_phyadd_hipart)
1423 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
1424 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
cdd3cb15
NC		 1425 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1426 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1427 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 1428 }
1429 }
1430 break;
1431
1432 case ACB_ADAPTER_TYPE_B: {
80da1adb 1433 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1434 /*clear all outbound posted Q*/
97b99127 1435 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */
1a4f550a 1436 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
c10b1d54
CH		 1437 flag_ccb = reg->done_qbuffer[i];
1438 if (flag_ccb != 0) {
1439 reg->done_qbuffer[i] = 0;
e66764f2
CH		 1440 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
1441 if (acb->cdb_phyadd_hipart)
1442 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
1443 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
cdd3cb15
NC		 1444 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1445 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1446 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a 1447 }
cdd3cb15 1448 reg->post_qbuffer[i] = 0;
1a4f550a
NC		 1449 }
1450 reg->doneq_index = 0;
1451 reg->postq_index = 0;
1452 }
1453 break;
cdd3cb15 1454 case ACB_ADAPTER_TYPE_C: {
c10b1d54 1455 struct MessageUnit_C __iomem *reg = acb->pmuC;
e4587f45 1456 while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < acb->maxOutstanding)) {
cdd3cb15
NC		 1457 /*need to do*/
1458 flag_ccb = readl(&reg->outbound_queueport_low);
1459 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
c71ec551
CH		 1460 if (acb->cdb_phyadd_hipart)
1461 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
1462 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
cdd3cb15
NC		 1463 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1464 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
1465 arcmsr_drain_donequeue(acb, pCCB, error);
1466 }
5b37479a
CH		 1467 }
1468 break;
1469 case ACB_ADAPTER_TYPE_D: {
1470 struct MessageUnit_D *pmu = acb->pmuD;
3b8155d5
CH		 1471 uint32_t outbound_write_pointer;
1472 uint32_t doneq_index, index_stripped, addressLow, residual, toggle;
1473 unsigned long flags;
5b37479a 1474
5b37479a
CH		 1475 residual = atomic_read(&acb->ccboutstandingcount);
1476 for (i = 0; i < residual; i++) {
3b8155d5
CH		 1477 spin_lock_irqsave(&acb->doneq_lock, flags);
1478 outbound_write_pointer =
1479 pmu->done_qbuffer[0].addressLow + 1;
1480 doneq_index = pmu->doneq_index;
1481 if ((doneq_index & 0xFFF) !=
5b37479a 1482 (outbound_write_pointer & 0xFFF)) {
3b8155d5
CH		 1483 toggle = doneq_index & 0x4000;
1484 index_stripped = (doneq_index & 0xFFF) + 1;
1485 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
1486 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
1487 ((toggle ^ 0x4000) + 1);
5b37479a 1488 doneq_index = pmu->doneq_index;
3b8155d5 1489 spin_unlock_irqrestore(&acb->doneq_lock, flags);
5b37479a
CH		 1490 addressLow = pmu->done_qbuffer[doneq_index &
1491 0xFFF].addressLow;
1492 ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
a36ade41
CH		 1493 if (acb->cdb_phyadd_hipart)
1494 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
5b37479a
CH		 1495 pARCMSR_CDB = (struct ARCMSR_CDB *)
1496 (acb->vir2phy_offset + ccb_cdb_phy);
1497 pCCB = container_of(pARCMSR_CDB,
1498 struct CommandControlBlock, arcmsr_cdb);
1499 error = (addressLow &
1500 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ?
1501 true : false;
1502 arcmsr_drain_donequeue(acb, pCCB, error);
1503 writel(doneq_index,
1504 pmu->outboundlist_read_pointer);
3b8155d5
CH		 1505 } else {
1506 spin_unlock_irqrestore(&acb->doneq_lock, flags);
1507 mdelay(10);
5b37479a 1508 }
5b37479a
CH		 1509 }
1510 pmu->postq_index = 0;
1511 pmu->doneq_index = 0x40FF;
1512 }
1513 break;
23509024
CH		 1514 case ACB_ADAPTER_TYPE_E:
1515 arcmsr_hbaE_postqueue_isr(acb);
1516 break;
1a4f550a
NC		 1517 }
1518}
1d1166ea 1519
c4c1adb3
CH		 1520static void arcmsr_remove_scsi_devices(struct AdapterControlBlock *acb)
1521{
1522 char *acb_dev_map = (char *)acb->device_map;
1523 int target, lun, i;
1524 struct scsi_device *psdev;
1525 struct CommandControlBlock *ccb;
1526 char temp;
1527
1528 for (i = 0; i < acb->maxFreeCCB; i++) {
1529 ccb = acb->pccb_pool[i];
1530 if (ccb->startdone == ARCMSR_CCB_START) {
1531 ccb->pcmd->result = DID_NO_CONNECT << 16;
1532 arcmsr_pci_unmap_dma(ccb);
1533 ccb->pcmd->scsi_done(ccb->pcmd);
1534 }
1535 }
1536 for (target = 0; target < ARCMSR_MAX_TARGETID; target++) {
1537 temp = *acb_dev_map;
1538 if (temp) {
1539 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
1540 if (temp & 1) {
1541 psdev = scsi_device_lookup(acb->host,
1542 0, target, lun);
1543 if (psdev != NULL) {
1544 scsi_remove_device(psdev);
1545 scsi_device_put(psdev);
1546 }
1547 }
1548 temp >>= 1;
1549 }
1550 *acb_dev_map = 0;
1551 }
1552 acb_dev_map++;
1553 }
1554}
1555
1556static void arcmsr_free_pcidev(struct AdapterControlBlock *acb)
1557{
1558 struct pci_dev *pdev;
1559 struct Scsi_Host *host;
1560
1561 host = acb->host;
1562 arcmsr_free_sysfs_attr(acb);
1563 scsi_remove_host(host);
1564 flush_work(&acb->arcmsr_do_message_isr_bh);
1565 del_timer_sync(&acb->eternal_timer);
1566 if (set_date_time)
1567 del_timer_sync(&acb->refresh_timer);
1568 pdev = acb->pdev;
1569 arcmsr_free_irq(pdev, acb);
1570 arcmsr_free_ccb_pool(acb);
c4c1adb3
CH		 1571 arcmsr_unmap_pciregion(acb);
1572 pci_release_regions(pdev);
1573 scsi_host_put(host);
1574 pci_disable_device(pdev);
1575}
1576
1c57e86d
EC		 1577static void arcmsr_remove(struct pci_dev *pdev)
1578{
1579 struct Scsi_Host *host = pci_get_drvdata(pdev);
1580 struct AdapterControlBlock *acb =
1581 (struct AdapterControlBlock *) host->hostdata;
1c57e86d 1582 int poll_count = 0;
c4c1adb3
CH		 1583 uint16_t dev_id;
1584
1585 pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
1586 if (dev_id == 0xffff) {
1587 acb->acb_flags &= ~ACB_F_IOP_INITED;
1588 acb->acb_flags |= ACB_F_ADAPTER_REMOVED;
1589 arcmsr_remove_scsi_devices(acb);
1590 arcmsr_free_pcidev(acb);
1591 return;
1592 }
1c57e86d
EC		 1593 arcmsr_free_sysfs_attr(acb);
1594 scsi_remove_host(host);
43829731 1595 flush_work(&acb->arcmsr_do_message_isr_bh);
36b83ded 1596 del_timer_sync(&acb->eternal_timer);
b416c099
CH		 1597 if (set_date_time)
1598 del_timer_sync(&acb->refresh_timer);
36b83ded 1599 arcmsr_disable_outbound_ints(acb);
1c57e86d 1600 arcmsr_stop_adapter_bgrb(acb);
cdd3cb15 1601 arcmsr_flush_adapter_cache(acb);
1c57e86d
EC		 1602 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
1603 acb->acb_flags &= ~ACB_F_IOP_INITED;
1604
e4587f45 1605 for (poll_count = 0; poll_count < acb->maxOutstanding; poll_count++){
1c57e86d
EC		 1606 if (!atomic_read(&acb->ccboutstandingcount))
1607 break;
1a4f550a 1608 arcmsr_interrupt(acb);/* FIXME: need spinlock */
1c57e86d
EC		 1609 msleep(25);
1610 }
1611
1612 if (atomic_read(&acb->ccboutstandingcount)) {
1613 int i;
1614
1615 arcmsr_abort_allcmd(acb);
1a4f550a 1616 arcmsr_done4abort_postqueue(acb);
d076e4aa 1617 for (i = 0; i < acb->maxFreeCCB; i++) {
1c57e86d
EC		 1618 struct CommandControlBlock *ccb = acb->pccb_pool[i];
1619 if (ccb->startdone == ARCMSR_CCB_START) {
1620 ccb->startdone = ARCMSR_CCB_ABORTED;
1621 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 1622 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 1623 }
1624 }
1625 }
1d1166ea 1626 arcmsr_free_irq(pdev, acb);
1c57e86d 1627 arcmsr_free_ccb_pool(acb);
cdd3cb15 1628 arcmsr_unmap_pciregion(acb);
1c57e86d 1629 pci_release_regions(pdev);
cdd3cb15 1630 scsi_host_put(host);
1c57e86d 1631 pci_disable_device(pdev);
1c57e86d
EC		 1632}
1633
1634static void arcmsr_shutdown(struct pci_dev *pdev)
1635{
1636 struct Scsi_Host *host = pci_get_drvdata(pdev);
1637 struct AdapterControlBlock *acb =
1638 (struct AdapterControlBlock *)host->hostdata;
c4c1adb3
CH		 1639 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
1640 return;
36b83ded 1641 del_timer_sync(&acb->eternal_timer);
b416c099
CH		 1642 if (set_date_time)
1643 del_timer_sync(&acb->refresh_timer);
36b83ded 1644 arcmsr_disable_outbound_ints(acb);
1d1166ea 1645 arcmsr_free_irq(pdev, acb);
43829731 1646 flush_work(&acb->arcmsr_do_message_isr_bh);
1c57e86d
EC		 1647 arcmsr_stop_adapter_bgrb(acb);
1648 arcmsr_flush_adapter_cache(acb);
1649}
1650
1651static int arcmsr_module_init(void)
1652{
1653 int error = 0;
1c57e86d
EC		 1654 error = pci_register_driver(&arcmsr_pci_driver);
1655 return error;
1656}
1657
1658static void arcmsr_module_exit(void)
1659{
1660 pci_unregister_driver(&arcmsr_pci_driver);
1661}
1662module_init(arcmsr_module_init);
1663module_exit(arcmsr_module_exit);
1664
36b83ded 1665static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
1a4f550a 1666 u32 intmask_org)
1c57e86d 1667{
1c57e86d 1668 u32 mask;
1a4f550a 1669 switch (acb->adapter_type) {
1c57e86d 1670
cdd3cb15 1671 case ACB_ADAPTER_TYPE_A: {
80da1adb 1672 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 1673 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
36b83ded
NC		 1674 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
1675 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
1a4f550a
NC		 1676 writel(mask, &reg->outbound_intmask);
1677 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
1678 }
1679 break;
1c57e86d 1680
cdd3cb15 1681 case ACB_ADAPTER_TYPE_B: {
80da1adb 1682 struct MessageUnit_B *reg = acb->pmuB;
36b83ded
NC		 1683 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
1684 ARCMSR_IOP2DRV_DATA_READ_OK |
1685 ARCMSR_IOP2DRV_CDB_DONE |
1686 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
ae52e7f0 1687 writel(mask, reg->iop2drv_doorbell_mask);
1a4f550a
NC		 1688 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
1689 }
cdd3cb15
NC		 1690 break;
1691 case ACB_ADAPTER_TYPE_C: {
c10b1d54 1692 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15
NC		 1693 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
1694 writel(intmask_org & mask, &reg->host_int_mask);
1695 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
1696 }
5b37479a
CH		 1697 break;
1698 case ACB_ADAPTER_TYPE_D: {
1699 struct MessageUnit_D *reg = acb->pmuD;
1700
1701 mask = ARCMSR_ARC1214_ALL_INT_ENABLE;
1702 writel(intmask_org | mask, reg->pcief0_int_enable);
1703 break;
1704 }
23509024
CH		 1705 case ACB_ADAPTER_TYPE_E: {
1706 struct MessageUnit_E __iomem *reg = acb->pmuE;
1707
1708 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR);
1709 writel(intmask_org & mask, &reg->host_int_mask);
1710 break;
1711 }
1c57e86d
EC		 1712 }
1713}
1714
76d78300 1715static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
1a4f550a 1716 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
1c57e86d 1717{
1a4f550a
NC		 1718 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1719 int8_t *psge = (int8_t *)&arcmsr_cdb->u;
80da1adb 1720 __le32 address_lo, address_hi;
1a4f550a 1721 int arccdbsize = 0x30;
ae52e7f0 1722 __le32 length = 0;
cdd3cb15 1723 int i;
ae52e7f0 1724 struct scatterlist *sg;
1a4f550a 1725 int nseg;
1c57e86d 1726 ccb->pcmd = pcmd;
1a4f550a 1727 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1c57e86d
EC		 1728 arcmsr_cdb->TargetID = pcmd->device->id;
1729 arcmsr_cdb->LUN = pcmd->device->lun;
1730 arcmsr_cdb->Function = 1;
626fa32c 1731 arcmsr_cdb->msgContext = 0;
1c57e86d 1732 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
deff2627
FT		 1733
1734 nseg = scsi_dma_map(pcmd);
cdd3cb15 1735 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
76d78300 1736 return FAILED;
cdd3cb15
NC		 1737 scsi_for_each_sg(pcmd, sg, nseg, i) {
1738 /* Get the physical address of the current data pointer */
1739 length = cpu_to_le32(sg_dma_len(sg));
1740 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
1741 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
1742 if (address_hi == 0) {
1743 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1744
1745 pdma_sg->address = address_lo;
1746 pdma_sg->length = length;
1747 psge += sizeof (struct SG32ENTRY);
1748 arccdbsize += sizeof (struct SG32ENTRY);
1749 } else {
1750 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1c57e86d 1751
cdd3cb15
NC		 1752 pdma_sg->addresshigh = address_hi;
1753 pdma_sg->address = address_lo;
1754 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
1755 psge += sizeof (struct SG64ENTRY);
1756 arccdbsize += sizeof (struct SG64ENTRY);
1c57e86d 1757 }
cdd3cb15
NC		 1758 }
1759 arcmsr_cdb->sgcount = (uint8_t)nseg;
1760 arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
ae52e7f0 1761 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
cdd3cb15
NC		 1762 if ( arccdbsize > 256)
1763 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
c32e061f 1764 if (pcmd->sc_data_direction == DMA_TO_DEVICE)
1c57e86d 1765 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
cdd3cb15 1766 ccb->arc_cdb_size = arccdbsize;
76d78300 1767 return SUCCESS;
1c57e86d
EC		 1768}
1769
1770static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
1771{
626fa32c 1772 uint32_t cdb_phyaddr = ccb->cdb_phyaddr;
1c57e86d 1773 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1c57e86d
EC		 1774 atomic_inc(&acb->ccboutstandingcount);
1775 ccb->startdone = ARCMSR_CCB_START;
1a4f550a
NC		 1776 switch (acb->adapter_type) {
1777 case ACB_ADAPTER_TYPE_A: {
80da1adb 1778 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1779
1780 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
626fa32c 1781 writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
1c57e86d 1782 &reg->inbound_queueport);
626fa32c
CH		 1783 else
1784 writel(cdb_phyaddr, &reg->inbound_queueport);
1a4f550a 1785 break;
626fa32c 1786 }
1c57e86d 1787
1a4f550a 1788 case ACB_ADAPTER_TYPE_B: {
80da1adb 1789 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1790 uint32_t ending_index, index = reg->postq_index;
1c57e86d 1791
1a4f550a 1792 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
c10b1d54 1793 reg->post_qbuffer[ending_index] = 0;
1a4f550a 1794 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
c10b1d54
CH		 1795 reg->post_qbuffer[index] =
1796 cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE;
cdd3cb15 1797 } else {
c10b1d54 1798 reg->post_qbuffer[index] = cdb_phyaddr;
1a4f550a
NC		 1799 }
1800 index++;
1801 index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
1802 reg->postq_index = index;
ae52e7f0 1803 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
1c57e86d 1804 }
1a4f550a 1805 break;
cdd3cb15 1806 case ACB_ADAPTER_TYPE_C: {
c10b1d54 1807 struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
cdd3cb15
NC		 1808 uint32_t ccb_post_stamp, arc_cdb_size;
1809
1810 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
626fa32c 1811 ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1);
c71ec551
CH		 1812 writel(upper_32_bits(ccb->cdb_phyaddr), &phbcmu->inbound_queueport_high);
1813 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
cdd3cb15 1814 }
5b37479a
CH		 1815 break;
1816 case ACB_ADAPTER_TYPE_D: {
1817 struct MessageUnit_D *pmu = acb->pmuD;
1818 u16 index_stripped;
3b8155d5 1819 u16 postq_index, toggle;
5b37479a
CH		 1820 unsigned long flags;
1821 struct InBound_SRB *pinbound_srb;
1822
1823 spin_lock_irqsave(&acb->postq_lock, flags);
1824 postq_index = pmu->postq_index;
1825 pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]);
a36ade41
CH		 1826 pinbound_srb->addressHigh = upper_32_bits(ccb->cdb_phyaddr);
1827 pinbound_srb->addressLow = cdb_phyaddr;
5b37479a
CH		 1828 pinbound_srb->length = ccb->arc_cdb_size >> 2;
1829 arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr);
3b8155d5
CH		 1830 toggle = postq_index & 0x4000;
1831 index_stripped = postq_index + 1;
1832 index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1);
1833 pmu->postq_index = index_stripped ? (index_stripped | toggle) :
1834 (toggle ^ 0x4000);
5b37479a
CH		 1835 writel(postq_index, pmu->inboundlist_write_pointer);
1836 spin_unlock_irqrestore(&acb->postq_lock, flags);
1837 break;
1838 }
23509024
CH		 1839 case ACB_ADAPTER_TYPE_E: {
1840 struct MessageUnit_E __iomem *pmu = acb->pmuE;
1841 u32 ccb_post_stamp, arc_cdb_size;
1842
1843 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
1844 ccb_post_stamp = (ccb->smid | ((arc_cdb_size - 1) >> 6));
1845 writel(0, &pmu->inbound_queueport_high);
1846 writel(ccb_post_stamp, &pmu->inbound_queueport_low);
1847 break;
1848 }
1c57e86d
EC		 1849 }
1850}
1851
626fa32c 1852static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb)
1c57e86d 1853{
80da1adb 1854 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d
EC		 1855 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1856 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
626fa32c 1857 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1a4f550a 1858 printk(KERN_NOTICE
948dff7a 1859 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
1a4f550a
NC		 1860 , acb->host->host_no);
1861 }
1862}
1863
626fa32c 1864static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb)
1a4f550a 1865{
80da1adb 1866 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1867 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
ae52e7f0 1868 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
1a4f550a 1869
626fa32c 1870 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1c57e86d 1871 printk(KERN_NOTICE
948dff7a 1872 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
1c57e86d 1873 , acb->host->host_no);
1a4f550a
NC		 1874 }
1875}
1876
626fa32c 1877static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB)
cdd3cb15 1878{
c10b1d54 1879 struct MessageUnit_C __iomem *reg = pACB->pmuC;
cdd3cb15
NC		 1880 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1881 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
1882 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
626fa32c 1883 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
cdd3cb15 1884 printk(KERN_NOTICE
948dff7a 1885 "arcmsr%d: wait 'stop adapter background rebuild' timeout\n"
cdd3cb15
NC		 1886 , pACB->host->host_no);
1887 }
1888 return;
1889}
5b37479a
CH		 1890
1891static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB)
1892{
1893 struct MessageUnit_D *reg = pACB->pmuD;
1894
1895 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1896 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0);
1897 if (!arcmsr_hbaD_wait_msgint_ready(pACB))
948dff7a 1898 pr_notice("arcmsr%d: wait 'stop adapter background rebuild' "
5b37479a
CH		 1899 "timeout\n", pACB->host->host_no);
1900}
1901
23509024
CH		 1902static void arcmsr_hbaE_stop_bgrb(struct AdapterControlBlock *pACB)
1903{
1904 struct MessageUnit_E __iomem *reg = pACB->pmuE;
1905
1906 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1907 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
1908 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
1909 writel(pACB->out_doorbell, &reg->iobound_doorbell);
1910 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
948dff7a 1911 pr_notice("arcmsr%d: wait 'stop adapter background rebuild' "
23509024
CH		 1912 "timeout\n", pACB->host->host_no);
1913 }
1914}
1915
1a4f550a
NC		 1916static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1917{
1918 switch (acb->adapter_type) {
1919 case ACB_ADAPTER_TYPE_A: {
626fa32c 1920 arcmsr_hbaA_stop_bgrb(acb);
1a4f550a
NC		 1921 }
1922 break;
1923
1924 case ACB_ADAPTER_TYPE_B: {
626fa32c 1925 arcmsr_hbaB_stop_bgrb(acb);
1a4f550a
NC		 1926 }
1927 break;
cdd3cb15 1928 case ACB_ADAPTER_TYPE_C: {
626fa32c 1929 arcmsr_hbaC_stop_bgrb(acb);
cdd3cb15 1930 }
5b37479a
CH		 1931 break;
1932 case ACB_ADAPTER_TYPE_D:
1933 arcmsr_hbaD_stop_bgrb(acb);
1934 break;
23509024
CH		 1935 case ACB_ADAPTER_TYPE_E:
1936 arcmsr_hbaE_stop_bgrb(acb);
1937 break;
1a4f550a 1938 }
1c57e86d
EC		 1939}
1940
1941static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
1942{
cdd3cb15 1943 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
1c57e86d
EC		 1944}
1945
c10b1d54 1946static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1c57e86d 1947{
1a4f550a
NC		 1948 switch (acb->adapter_type) {
1949 case ACB_ADAPTER_TYPE_A: {
80da1adb 1950 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1951 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
1952 }
1953 break;
1c57e86d 1954
1a4f550a 1955 case ACB_ADAPTER_TYPE_B: {
80da1adb 1956 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1957 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1c57e86d 1958 }
1a4f550a 1959 break;
cdd3cb15
NC		 1960 case ACB_ADAPTER_TYPE_C: {
1961 struct MessageUnit_C __iomem *reg = acb->pmuC;
5b37479a 1962
cdd3cb15
NC		 1963 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
1964 }
5b37479a
CH		 1965 break;
1966 case ACB_ADAPTER_TYPE_D: {
1967 struct MessageUnit_D *reg = acb->pmuD;
1968 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
1969 reg->inbound_doorbell);
1970 }
1971 break;
23509024
CH		 1972 case ACB_ADAPTER_TYPE_E: {
1973 struct MessageUnit_E __iomem *reg = acb->pmuE;
1974 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
1975 writel(acb->out_doorbell, &reg->iobound_doorbell);
1976 }
1977 break;
1c57e86d 1978 }
1a4f550a
NC		 1979}
1980
1981static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1982{
1983 switch (acb->adapter_type) {
1984 case ACB_ADAPTER_TYPE_A: {
80da1adb 1985 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 1986 /*
1a4f550a
NC		 1987 ** push inbound doorbell tell iop, driver data write ok
1988 ** and wait reply on next hwinterrupt for next Qbuffer post
1c57e86d 1989 */
1a4f550a
NC		 1990 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
1991 }
1992 break;
1993
1994 case ACB_ADAPTER_TYPE_B: {
80da1adb 1995 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a
NC		 1996 /*
1997 ** push inbound doorbell tell iop, driver data write ok
1998 ** and wait reply on next hwinterrupt for next Qbuffer post
1999 */
ae52e7f0 2000 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
1a4f550a
NC		 2001 }
2002 break;
cdd3cb15
NC		 2003 case ACB_ADAPTER_TYPE_C: {
2004 struct MessageUnit_C __iomem *reg = acb->pmuC;
2005 /*
2006 ** push inbound doorbell tell iop, driver data write ok
2007 ** and wait reply on next hwinterrupt for next Qbuffer post
2008 */
2009 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
2010 }
2011 break;
5b37479a
CH		 2012 case ACB_ADAPTER_TYPE_D: {
2013 struct MessageUnit_D *reg = acb->pmuD;
2014 writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY,
2015 reg->inbound_doorbell);
2016 }
2017 break;
23509024
CH		 2018 case ACB_ADAPTER_TYPE_E: {
2019 struct MessageUnit_E __iomem *reg = acb->pmuE;
2020 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK;
2021 writel(acb->out_doorbell, &reg->iobound_doorbell);
2022 }
2023 break;
1a4f550a
NC		 2024 }
2025}
2026
80da1adb 2027struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
1a4f550a 2028{
0c7eb2eb 2029 struct QBUFFER __iomem *qbuffer = NULL;
1a4f550a
NC		 2030 switch (acb->adapter_type) {
2031
2032 case ACB_ADAPTER_TYPE_A: {
80da1adb
AV		 2033 struct MessageUnit_A __iomem *reg = acb->pmuA;
2034 qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
1a4f550a
NC		 2035 }
2036 break;
2037
2038 case ACB_ADAPTER_TYPE_B: {
80da1adb 2039 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2040 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
1a4f550a
NC		 2041 }
2042 break;
cdd3cb15 2043 case ACB_ADAPTER_TYPE_C: {
c10b1d54 2044 struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
cdd3cb15
NC		 2045 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
2046 }
5b37479a
CH		 2047 break;
2048 case ACB_ADAPTER_TYPE_D: {
2049 struct MessageUnit_D *reg = acb->pmuD;
2050 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
2051 }
2052 break;
23509024
CH		 2053 case ACB_ADAPTER_TYPE_E: {
2054 struct MessageUnit_E __iomem *reg = acb->pmuE;
2055 qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
2056 }
2057 break;
1a4f550a
NC		 2058 }
2059 return qbuffer;
2060}
2061
80da1adb 2062static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
1a4f550a 2063{
0c7eb2eb 2064 struct QBUFFER __iomem *pqbuffer = NULL;
1a4f550a
NC		 2065 switch (acb->adapter_type) {
2066
2067 case ACB_ADAPTER_TYPE_A: {
80da1adb
AV		 2068 struct MessageUnit_A __iomem *reg = acb->pmuA;
2069 pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
1a4f550a
NC		 2070 }
2071 break;
2072
2073 case ACB_ADAPTER_TYPE_B: {
80da1adb 2074 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2075 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
1a4f550a
NC		 2076 }
2077 break;
cdd3cb15 2078 case ACB_ADAPTER_TYPE_C: {
c10b1d54 2079 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15 2080 pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
5b37479a
CH		 2081 }
2082 break;
2083 case ACB_ADAPTER_TYPE_D: {
2084 struct MessageUnit_D *reg = acb->pmuD;
2085 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
2086 }
2087 break;
23509024
CH		 2088 case ACB_ADAPTER_TYPE_E: {
2089 struct MessageUnit_E __iomem *reg = acb->pmuE;
2090 pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
2091 }
2092 break;
1a4f550a
NC		 2093 }
2094 return pqbuffer;
2095}
2096
bb263c4e
CH		 2097static uint32_t
2098arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb,
2099 struct QBUFFER __iomem *prbuffer)
1a4f550a 2100{
bb263c4e
CH		 2101 uint8_t *pQbuffer;
2102 uint8_t *buf1 = NULL;
2103 uint32_t __iomem *iop_data;
2104 uint32_t iop_len, data_len, *buf2 = NULL;
2105
2106 iop_data = (uint32_t __iomem *)prbuffer->data;
2107 iop_len = readl(&prbuffer->data_len);
2108 if (iop_len > 0) {
2109 buf1 = kmalloc(128, GFP_ATOMIC);
2110 buf2 = (uint32_t *)buf1;
2111 if (buf1 == NULL)
2112 return 0;
2113 data_len = iop_len;
2114 while (data_len >= 4) {
2115 *buf2++ = readl(iop_data);
1a4f550a 2116 iop_data++;
bb263c4e 2117 data_len -= 4;
1a4f550a 2118 }
bb263c4e
CH		 2119 if (data_len)
2120 *buf2 = readl(iop_data);
2121 buf2 = (uint32_t *)buf1;
2122 }
2123 while (iop_len > 0) {
2e9feb43 2124 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
bb263c4e 2125 *pQbuffer = *buf1;
2e9feb43 2126 acb->rqbuf_putIndex++;
bb263c4e 2127 /* if last, index number set it to 0 */
2e9feb43 2128 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
bb263c4e
CH		 2129 buf1++;
2130 iop_len--;
2131 }
2e9feb43 2132 kfree(buf2);
bb263c4e
CH		 2133 /* let IOP know data has been read */
2134 arcmsr_iop_message_read(acb);
2135 return 1;
2136}
2137
2138uint32_t
2139arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
2140 struct QBUFFER __iomem *prbuffer) {
2141
2142 uint8_t *pQbuffer;
2143 uint8_t __iomem *iop_data;
2144 uint32_t iop_len;
2145
52b4dab3 2146 if (acb->adapter_type > ACB_ADAPTER_TYPE_B)
bb263c4e
CH		 2147 return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer);
2148 iop_data = (uint8_t __iomem *)prbuffer->data;
2149 iop_len = readl(&prbuffer->data_len);
2150 while (iop_len > 0) {
2e9feb43 2151 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
bb263c4e 2152 *pQbuffer = readb(iop_data);
2e9feb43
CH		 2153 acb->rqbuf_putIndex++;
2154 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
bb263c4e
CH		 2155 iop_data++;
2156 iop_len--;
1a4f550a 2157 }
bb263c4e
CH		 2158 arcmsr_iop_message_read(acb);
2159 return 1;
2160}
1a4f550a 2161
bb263c4e
CH		 2162static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
2163{
2164 unsigned long flags;
2165 struct QBUFFER __iomem *prbuffer;
2166 int32_t buf_empty_len;
2167
2168 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2169 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2e9feb43 2170 buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) &
bb263c4e
CH		 2171 (ARCMSR_MAX_QBUFFER - 1);
2172 if (buf_empty_len >= readl(&prbuffer->data_len)) {
2173 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2174 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2175 } else
1a4f550a 2176 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
bb263c4e
CH		 2177 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2178}
2179
2180static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb)
2181{
2182 uint8_t *pQbuffer;
2183 struct QBUFFER __iomem *pwbuffer;
2184 uint8_t *buf1 = NULL;
2185 uint32_t __iomem *iop_data;
2186 uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data;
2187
2188 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
2189 buf1 = kmalloc(128, GFP_ATOMIC);
2190 buf2 = (uint32_t *)buf1;
2191 if (buf1 == NULL)
2192 return;
2193
2194 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
2195 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
2196 iop_data = (uint32_t __iomem *)pwbuffer->data;
2e9feb43 2197 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
bb263c4e 2198 && (allxfer_len < 124)) {
2e9feb43 2199 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
bb263c4e 2200 *buf1 = *pQbuffer;
2e9feb43
CH		 2201 acb->wqbuf_getIndex++;
2202 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
bb263c4e
CH		 2203 buf1++;
2204 allxfer_len++;
2205 }
2206 data_len = allxfer_len;
2207 buf1 = (uint8_t *)buf2;
2208 while (data_len >= 4) {
2209 data = *buf2++;
2210 writel(data, iop_data);
2211 iop_data++;
2212 data_len -= 4;
2213 }
2214 if (data_len) {
2215 data = *buf2;
2216 writel(data, iop_data);
2217 }
2218 writel(allxfer_len, &pwbuffer->data_len);
2219 kfree(buf1);
2220 arcmsr_iop_message_wrote(acb);
1a4f550a
NC		 2221 }
2222}
2223
bb263c4e
CH		 2224void
2225arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb)
1a4f550a 2226{
bb263c4e
CH		 2227 uint8_t *pQbuffer;
2228 struct QBUFFER __iomem *pwbuffer;
2229 uint8_t __iomem *iop_data;
2230 int32_t allxfer_len = 0;
1a4f550a 2231
52b4dab3 2232 if (acb->adapter_type > ACB_ADAPTER_TYPE_B) {
bb263c4e
CH		 2233 arcmsr_write_ioctldata2iop_in_DWORD(acb);
2234 return;
2235 }
2236 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
1a4f550a
NC		 2237 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
2238 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
2239 iop_data = (uint8_t __iomem *)pwbuffer->data;
2e9feb43 2240 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
bb263c4e 2241 && (allxfer_len < 124)) {
2e9feb43 2242 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
bb263c4e 2243 writeb(*pQbuffer, iop_data);
2e9feb43
CH		 2244 acb->wqbuf_getIndex++;
2245 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
1a4f550a
NC		 2246 iop_data++;
2247 allxfer_len++;
2248 }
bb263c4e 2249 writel(allxfer_len, &pwbuffer->data_len);
1a4f550a
NC		 2250 arcmsr_iop_message_wrote(acb);
2251 }
bb263c4e 2252}
1a4f550a 2253
bb263c4e
CH		 2254static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
2255{
2256 unsigned long flags;
2257
2258 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2259 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
2e9feb43 2260 if (acb->wqbuf_getIndex != acb->wqbuf_putIndex)
bb263c4e 2261 arcmsr_write_ioctldata2iop(acb);
2e9feb43 2262 if (acb->wqbuf_getIndex == acb->wqbuf_putIndex)
1a4f550a 2263 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
bb263c4e 2264 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
1a4f550a
NC		 2265}
2266
626fa32c 2267static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 2268{
2269 uint32_t outbound_doorbell;
80da1adb 2270 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 2271 outbound_doorbell = readl(&reg->outbound_doorbell);
6b393722
CH		 2272 do {
2273 writel(outbound_doorbell, &reg->outbound_doorbell);
2274 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK)
2275 arcmsr_iop2drv_data_wrote_handle(acb);
2276 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)
2277 arcmsr_iop2drv_data_read_handle(acb);
2278 outbound_doorbell = readl(&reg->outbound_doorbell);
2279 } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK
2280 | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK));
1a4f550a 2281}
626fa32c 2282static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB)
cdd3cb15
NC		 2283{
2284 uint32_t outbound_doorbell;
c10b1d54 2285 struct MessageUnit_C __iomem *reg = pACB->pmuC;
cdd3cb15
NC		 2286 /*
2287 *******************************************************************
2288 ** Maybe here we need to check wrqbuffer_lock is lock or not
2289 ** DOORBELL: din! don!
2290 ** check if there are any mail need to pack from firmware
2291 *******************************************************************
2292 */
2293 outbound_doorbell = readl(&reg->outbound_doorbell);
6b393722
CH		 2294 do {
2295 writel(outbound_doorbell, &reg->outbound_doorbell_clear);
2296 readl(&reg->outbound_doorbell_clear);
2297 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK)
2298 arcmsr_iop2drv_data_wrote_handle(pACB);
2299 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK)
2300 arcmsr_iop2drv_data_read_handle(pACB);
2301 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)
626fa32c 2302 arcmsr_hbaC_message_isr(pACB);
6b393722
CH		 2303 outbound_doorbell = readl(&reg->outbound_doorbell);
2304 } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK
2305 | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK
2306 | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE));
cdd3cb15 2307}
5b37479a
CH		 2308
2309static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB)
2310{
2311 uint32_t outbound_doorbell;
2312 struct MessageUnit_D *pmu = pACB->pmuD;
2313
2314 outbound_doorbell = readl(pmu->outbound_doorbell);
2315 do {
2316 writel(outbound_doorbell, pmu->outbound_doorbell);
2317 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)
2318 arcmsr_hbaD_message_isr(pACB);
2319 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK)
2320 arcmsr_iop2drv_data_wrote_handle(pACB);
2321 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK)
2322 arcmsr_iop2drv_data_read_handle(pACB);
2323 outbound_doorbell = readl(pmu->outbound_doorbell);
2324 } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK
2325 | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK
2326 | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE));
2327}
2328
23509024
CH		 2329static void arcmsr_hbaE_doorbell_isr(struct AdapterControlBlock *pACB)
2330{
2331 uint32_t outbound_doorbell, in_doorbell, tmp;
2332 struct MessageUnit_E __iomem *reg = pACB->pmuE;
2333
2334 in_doorbell = readl(&reg->iobound_doorbell);
2335 outbound_doorbell = in_doorbell ^ pACB->in_doorbell;
2336 do {
2337 writel(0, &reg->host_int_status); /* clear interrupt */
2338 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
2339 arcmsr_iop2drv_data_wrote_handle(pACB);
2340 }
2341 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) {
2342 arcmsr_iop2drv_data_read_handle(pACB);
2343 }
2344 if (outbound_doorbell & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) {
2345 arcmsr_hbaE_message_isr(pACB);
2346 }
2347 tmp = in_doorbell;
2348 in_doorbell = readl(&reg->iobound_doorbell);
2349 outbound_doorbell = tmp ^ in_doorbell;
2350 } while (outbound_doorbell & (ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK
2351 | ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK
2352 | ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE));
2353 pACB->in_doorbell = in_doorbell;
2354}
2355
626fa32c 2356static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 2357{
2358 uint32_t flag_ccb;
80da1adb 2359 struct MessageUnit_A __iomem *reg = acb->pmuA;
cdd3cb15
NC		 2360 struct ARCMSR_CDB *pARCMSR_CDB;
2361 struct CommandControlBlock *pCCB;
2362 bool error;
9e386a55
CH		 2363 unsigned long cdb_phy_addr;
2364
1a4f550a 2365 while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
9e386a55
CH		 2366 cdb_phy_addr = (flag_ccb << 5) & 0xffffffff;
2367 if (acb->cdb_phyadd_hipart)
2368 cdb_phy_addr = cdb_phy_addr | acb->cdb_phyadd_hipart;
2369 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + cdb_phy_addr);
cdd3cb15
NC		 2370 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
2371 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2372 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 2373 }
2374}
626fa32c 2375static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 2376{
2377 uint32_t index;
2378 uint32_t flag_ccb;
80da1adb 2379 struct MessageUnit_B *reg = acb->pmuB;
cdd3cb15
NC		 2380 struct ARCMSR_CDB *pARCMSR_CDB;
2381 struct CommandControlBlock *pCCB;
2382 bool error;
e66764f2
CH		 2383 unsigned long cdb_phy_addr;
2384
1a4f550a 2385 index = reg->doneq_index;
c10b1d54 2386 while ((flag_ccb = reg->done_qbuffer[index]) != 0) {
e66764f2
CH		 2387 cdb_phy_addr = (flag_ccb << 5) & 0xffffffff;
2388 if (acb->cdb_phyadd_hipart)
2389 cdb_phy_addr = cdb_phy_addr | acb->cdb_phyadd_hipart;
2390 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + cdb_phy_addr);
cdd3cb15
NC		 2391 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
2392 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2393 arcmsr_drain_donequeue(acb, pCCB, error);
e66764f2 2394 reg->done_qbuffer[index] = 0;
1a4f550a
NC		 2395 index++;
2396 index %= ARCMSR_MAX_HBB_POSTQUEUE;
2397 reg->doneq_index = index;
2398 }
2399}
cdd3cb15 2400
626fa32c 2401static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb)
cdd3cb15 2402{
c10b1d54 2403 struct MessageUnit_C __iomem *phbcmu;
cdd3cb15
NC		 2404 struct ARCMSR_CDB *arcmsr_cdb;
2405 struct CommandControlBlock *ccb;
c71ec551
CH		 2406 uint32_t flag_ccb, throttling = 0;
2407 unsigned long ccb_cdb_phy;
cdd3cb15
NC		 2408 int error;
2409
c10b1d54 2410 phbcmu = acb->pmuC;
cdd3cb15
NC		 2411 /* areca cdb command done */
2412 /* Use correct offset and size for syncing */
2413
6b393722
CH		 2414 while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) !=
2415 0xFFFFFFFF) {
2416 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
c71ec551
CH		 2417 if (acb->cdb_phyadd_hipart)
2418 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
6b393722
CH		 2419 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
2420 + ccb_cdb_phy);
2421 ccb = container_of(arcmsr_cdb, struct CommandControlBlock,
2422 arcmsr_cdb);
2423 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
2424 ? true : false;
2425 /* check if command done with no error */
2426 arcmsr_drain_donequeue(acb, ccb, error);
2427 throttling++;
2428 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
2429 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING,
2430 &phbcmu->inbound_doorbell);
2431 throttling = 0;
2432 }
cdd3cb15
NC		 2433 }
2434}
5b37479a
CH		 2435
2436static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb)
2437{
3b8155d5 2438 u32 outbound_write_pointer, doneq_index, index_stripped, toggle;
a36ade41 2439 uint32_t addressLow;
5b37479a
CH		 2440 int error;
2441 struct MessageUnit_D *pmu;
2442 struct ARCMSR_CDB *arcmsr_cdb;
2443 struct CommandControlBlock *ccb;
18bc435e 2444 unsigned long flags, ccb_cdb_phy;
5b37479a
CH		 2445
2446 spin_lock_irqsave(&acb->doneq_lock, flags);
2447 pmu = acb->pmuD;
2448 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
2449 doneq_index = pmu->doneq_index;
2450 if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) {
2451 do {
3b8155d5
CH		 2452 toggle = doneq_index & 0x4000;
2453 index_stripped = (doneq_index & 0xFFF) + 1;
2454 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
2455 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
2456 ((toggle ^ 0x4000) + 1);
5b37479a
CH		 2457 doneq_index = pmu->doneq_index;
2458 addressLow = pmu->done_qbuffer[doneq_index &
2459 0xFFF].addressLow;
2460 ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
a36ade41
CH		 2461 if (acb->cdb_phyadd_hipart)
2462 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
5b37479a
CH		 2463 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
2464 + ccb_cdb_phy);
2465 ccb = container_of(arcmsr_cdb,
2466 struct CommandControlBlock, arcmsr_cdb);
2467 error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
2468 ? true : false;
2469 arcmsr_drain_donequeue(acb, ccb, error);
2470 writel(doneq_index, pmu->outboundlist_read_pointer);
2471 } while ((doneq_index & 0xFFF) !=
2472 (outbound_write_pointer & 0xFFF));
2473 }
2474 writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR,
2475 pmu->outboundlist_interrupt_cause);
2476 readl(pmu->outboundlist_interrupt_cause);
2477 spin_unlock_irqrestore(&acb->doneq_lock, flags);
2478}
2479
23509024
CH		 2480static void arcmsr_hbaE_postqueue_isr(struct AdapterControlBlock *acb)
2481{
2482 uint32_t doneq_index;
2483 uint16_t cmdSMID;
2484 int error;
2485 struct MessageUnit_E __iomem *pmu;
2486 struct CommandControlBlock *ccb;
2487 unsigned long flags;
2488
2489 spin_lock_irqsave(&acb->doneq_lock, flags);
2490 doneq_index = acb->doneq_index;
2491 pmu = acb->pmuE;
2492 while ((readl(&pmu->reply_post_producer_index) & 0xFFFF) != doneq_index) {
2493 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
2494 ccb = acb->pccb_pool[cmdSMID];
2495 error = (acb->pCompletionQ[doneq_index].cmdFlag
2496 & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
2497 arcmsr_drain_donequeue(acb, ccb, error);
2498 doneq_index++;
2499 if (doneq_index >= acb->completionQ_entry)
2500 doneq_index = 0;
2501 }
2502 acb->doneq_index = doneq_index;
2503 writel(doneq_index, &pmu->reply_post_consumer_index);
2504 spin_unlock_irqrestore(&acb->doneq_lock, flags);
2505}
2506
36b83ded
NC		 2507/*
2508**********************************************************************************
2509** Handle a message interrupt
2510**
cdd3cb15 2511** The only message interrupt we expect is in response to a query for the current adapter config.
36b83ded
NC		 2512** We want this in order to compare the drivemap so that we can detect newly-attached drives.
2513**********************************************************************************
2514*/
626fa32c 2515static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb)
36b83ded 2516{
c10b1d54 2517 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded
NC		 2518 /*clear interrupt and message state*/
2519 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
5dd8b3e7
CH		 2520 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2521 schedule_work(&acb->arcmsr_do_message_isr_bh);
36b83ded 2522}
626fa32c 2523static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb)
36b83ded
NC		 2524{
2525 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2526
36b83ded 2527 /*clear interrupt and message state*/
ae52e7f0 2528 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
5dd8b3e7
CH		 2529 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2530 schedule_work(&acb->arcmsr_do_message_isr_bh);
36b83ded 2531}
cdd3cb15
NC		 2532/*
2533**********************************************************************************
2534** Handle a message interrupt
2535**
2536** The only message interrupt we expect is in response to a query for the
2537** current adapter config.
2538** We want this in order to compare the drivemap so that we can detect newly-attached drives.
2539**********************************************************************************
2540*/
626fa32c 2541static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb)
cdd3cb15 2542{
c10b1d54 2543 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15
NC		 2544 /*clear interrupt and message state*/
2545 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
5dd8b3e7
CH		 2546 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2547 schedule_work(&acb->arcmsr_do_message_isr_bh);
cdd3cb15
NC		 2548}
2549
5b37479a
CH		 2550static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb)
2551{
2552 struct MessageUnit_D *reg = acb->pmuD;
2553
2554 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell);
2555 readl(reg->outbound_doorbell);
5dd8b3e7
CH		 2556 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2557 schedule_work(&acb->arcmsr_do_message_isr_bh);
5b37479a
CH		 2558}
2559
23509024
CH		 2560static void arcmsr_hbaE_message_isr(struct AdapterControlBlock *acb)
2561{
2562 struct MessageUnit_E __iomem *reg = acb->pmuE;
2563
2564 writel(0, &reg->host_int_status);
5dd8b3e7
CH		 2565 if (acb->acb_flags & ACB_F_MSG_GET_CONFIG)
2566 schedule_work(&acb->arcmsr_do_message_isr_bh);
23509024
CH		 2567}
2568
626fa32c 2569static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 2570{
2571 uint32_t outbound_intstatus;
80da1adb 2572 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 2573 outbound_intstatus = readl(&reg->outbound_intstatus) &
cdd3cb15 2574 acb->outbound_int_enable;
6b393722
CH		 2575 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT))
2576 return IRQ_NONE;
2577 do {
2578 writel(outbound_intstatus, &reg->outbound_intstatus);
2579 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT)
626fa32c 2580 arcmsr_hbaA_doorbell_isr(acb);
6b393722 2581 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT)
626fa32c 2582 arcmsr_hbaA_postqueue_isr(acb);
6b393722 2583 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT)
626fa32c 2584 arcmsr_hbaA_message_isr(acb);
6b393722
CH		 2585 outbound_intstatus = readl(&reg->outbound_intstatus) &
2586 acb->outbound_int_enable;
2587 } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT
2588 | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT
2589 | ARCMSR_MU_OUTBOUND_MESSAGE0_INT));
2590 return IRQ_HANDLED;
1a4f550a
NC		 2591}
2592
626fa32c 2593static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 2594{
2595 uint32_t outbound_doorbell;
80da1adb 2596 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2597 outbound_doorbell = readl(reg->iop2drv_doorbell) &
cdd3cb15 2598 acb->outbound_int_enable;
1a4f550a 2599 if (!outbound_doorbell)
6b393722
CH		 2600 return IRQ_NONE;
2601 do {
2602 writel(~outbound_doorbell, reg->iop2drv_doorbell);
2603 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
2604 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK)
2605 arcmsr_iop2drv_data_wrote_handle(acb);
2606 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK)
2607 arcmsr_iop2drv_data_read_handle(acb);
2608 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE)
626fa32c 2609 arcmsr_hbaB_postqueue_isr(acb);
6b393722 2610 if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)
626fa32c 2611 arcmsr_hbaB_message_isr(acb);
6b393722
CH		 2612 outbound_doorbell = readl(reg->iop2drv_doorbell) &
2613 acb->outbound_int_enable;
2614 } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK
2615 | ARCMSR_IOP2DRV_DATA_READ_OK
2616 | ARCMSR_IOP2DRV_CDB_DONE
2617 | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE));
2618 return IRQ_HANDLED;
1a4f550a
NC		 2619}
2620
626fa32c 2621static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB)
cdd3cb15
NC		 2622{
2623 uint32_t host_interrupt_status;
c10b1d54 2624 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
cdd3cb15
NC		 2625 /*
2626 *********************************************
2627 ** check outbound intstatus
2628 *********************************************
2629 */
6b393722
CH		 2630 host_interrupt_status = readl(&phbcmu->host_int_status) &
2631 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2632 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2633 if (!host_interrupt_status)
2634 return IRQ_NONE;
2635 do {
2636 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)
626fa32c 2637 arcmsr_hbaC_doorbell_isr(pACB);
6b393722
CH		 2638 /* MU post queue interrupts*/
2639 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)
626fa32c 2640 arcmsr_hbaC_postqueue_isr(pACB);
6b393722
CH		 2641 host_interrupt_status = readl(&phbcmu->host_int_status);
2642 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2643 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2644 return IRQ_HANDLED;
cdd3cb15 2645}
5b37479a
CH		 2646
2647static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB)
2648{
2649 u32 host_interrupt_status;
2650 struct MessageUnit_D *pmu = pACB->pmuD;
2651
2652 host_interrupt_status = readl(pmu->host_int_status) &
2653 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
2654 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR);
2655 if (!host_interrupt_status)
2656 return IRQ_NONE;
2657 do {
2658 /* MU post queue interrupts*/
2659 if (host_interrupt_status &
2660 ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR)
2661 arcmsr_hbaD_postqueue_isr(pACB);
2662 if (host_interrupt_status &
2663 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)
2664 arcmsr_hbaD_doorbell_isr(pACB);
2665 host_interrupt_status = readl(pmu->host_int_status);
2666 } while (host_interrupt_status &
2667 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
2668 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR));
2669 return IRQ_HANDLED;
2670}
2671
23509024
CH		 2672static irqreturn_t arcmsr_hbaE_handle_isr(struct AdapterControlBlock *pACB)
2673{
2674 uint32_t host_interrupt_status;
2675 struct MessageUnit_E __iomem *pmu = pACB->pmuE;
2676
2677 host_interrupt_status = readl(&pmu->host_int_status) &
2678 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2679 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR);
2680 if (!host_interrupt_status)
2681 return IRQ_NONE;
2682 do {
2683 /* MU ioctl transfer doorbell interrupts*/
2684 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) {
2685 arcmsr_hbaE_doorbell_isr(pACB);
2686 }
2687 /* MU post queue interrupts*/
2688 if (host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) {
2689 arcmsr_hbaE_postqueue_isr(pACB);
2690 }
2691 host_interrupt_status = readl(&pmu->host_int_status);
2692 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR |
2693 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR));
2694 return IRQ_HANDLED;
2695}
2696
1a4f550a
NC		 2697static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
2698{
2699 switch (acb->adapter_type) {
6b393722 2700 case ACB_ADAPTER_TYPE_A:
626fa32c 2701 return arcmsr_hbaA_handle_isr(acb);
1a4f550a 2702 break;
6b393722 2703 case ACB_ADAPTER_TYPE_B:
626fa32c 2704 return arcmsr_hbaB_handle_isr(acb);
1a4f550a 2705 break;
6b393722 2706 case ACB_ADAPTER_TYPE_C:
626fa32c 2707 return arcmsr_hbaC_handle_isr(acb);
5b37479a
CH		 2708 case ACB_ADAPTER_TYPE_D:
2709 return arcmsr_hbaD_handle_isr(acb);
23509024
CH		 2710 case ACB_ADAPTER_TYPE_E:
2711 return arcmsr_hbaE_handle_isr(acb);
6b393722
CH		 2712 default:
2713 return IRQ_NONE;
1c57e86d 2714 }
1c57e86d
EC		 2715}
2716
2717static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2718{
2719 if (acb) {
2720 /* stop adapter background rebuild */
2721 if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
1a4f550a 2722 uint32_t intmask_org;
1c57e86d 2723 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1a4f550a 2724 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d
EC		 2725 arcmsr_stop_adapter_bgrb(acb);
2726 arcmsr_flush_adapter_cache(acb);
1a4f550a
NC		 2727 arcmsr_enable_outbound_ints(acb, intmask_org);
2728 }
2729 }
2730}
2731
bb263c4e
CH		 2732
2733void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb)
1a4f550a 2734{
bb263c4e
CH		 2735 uint32_t i;
2736
2737 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2738 for (i = 0; i < 15; i++) {
2739 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2740 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2e9feb43
CH		 2741 acb->rqbuf_getIndex = 0;
2742 acb->rqbuf_putIndex = 0;
bb263c4e
CH		 2743 arcmsr_iop_message_read(acb);
2744 mdelay(30);
2e9feb43
CH		 2745 } else if (acb->rqbuf_getIndex !=
2746 acb->rqbuf_putIndex) {
2747 acb->rqbuf_getIndex = 0;
2748 acb->rqbuf_putIndex = 0;
bb263c4e
CH		 2749 mdelay(30);
2750 } else
2751 break;
1c57e86d
EC		 2752 }
2753 }
2754}
2755
36b83ded 2756static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
bb263c4e 2757 struct scsi_cmnd *cmd)
1c57e86d 2758{
1c57e86d 2759 char *buffer;
bb263c4e
CH		 2760 unsigned short use_sg;
2761 int retvalue = 0, transfer_len = 0;
2762 unsigned long flags;
2763 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2764 uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 |
2765 (uint32_t)cmd->cmnd[6] << 16 |
2766 (uint32_t)cmd->cmnd[7] << 8 |
2767 (uint32_t)cmd->cmnd[8];
deff2627 2768 struct scatterlist *sg;
bb263c4e
CH		 2769
2770 use_sg = scsi_sg_count(cmd);
deff2627 2771 sg = scsi_sglist(cmd);
77dfce07 2772 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
bb263c4e 2773 if (use_sg > 1) {
deff2627
FT		 2774 retvalue = ARCMSR_MESSAGE_FAIL;
2775 goto message_out;
1c57e86d 2776 }
deff2627 2777 transfer_len += sg->length;
1c57e86d
EC		 2778 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2779 retvalue = ARCMSR_MESSAGE_FAIL;
bb263c4e 2780 pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__);
1c57e86d
EC		 2781 goto message_out;
2782 }
bb263c4e
CH		 2783 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer;
2784 switch (controlcode) {
1c57e86d 2785 case ARCMSR_MESSAGE_READ_RQBUFFER: {
69e562c2 2786 unsigned char *ver_addr;
2e9feb43 2787 uint8_t *ptmpQbuffer;
bb263c4e 2788 uint32_t allxfer_len = 0;
2e9feb43 2789 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
69e562c2 2790 if (!ver_addr) {
1a4f550a 2791 retvalue = ARCMSR_MESSAGE_FAIL;
bb263c4e 2792 pr_info("%s: memory not enough!\n", __func__);
1a4f550a
NC		 2793 goto message_out;
2794 }
69e562c2 2795 ptmpQbuffer = ver_addr;
bb263c4e 2796 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2e9feb43
CH		 2797 if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) {
2798 unsigned int tail = acb->rqbuf_getIndex;
2799 unsigned int head = acb->rqbuf_putIndex;
2800 unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER);
2801
2802 allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER);
2803 if (allxfer_len > ARCMSR_API_DATA_BUFLEN)
2804 allxfer_len = ARCMSR_API_DATA_BUFLEN;
2805
2806 if (allxfer_len <= cnt_to_end)
2807 memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len);
2808 else {
2809 memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end);
2810 memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end);
bb263c4e 2811 }
2e9feb43 2812 acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER;
1a4f550a 2813 }
bb263c4e
CH		 2814 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr,
2815 allxfer_len);
1a4f550a 2816 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
80da1adb 2817 struct QBUFFER __iomem *prbuffer;
1a4f550a
NC		 2818 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2819 prbuffer = arcmsr_get_iop_rqbuffer(acb);
bb263c4e
CH		 2820 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2821 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
ae52e7f0 2822 }
bb263c4e 2823 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
69e562c2 2824 kfree(ver_addr);
bb263c4e
CH		 2825 pcmdmessagefld->cmdmessage.Length = allxfer_len;
2826 if (acb->fw_flag == FW_DEADLOCK)
2827 pcmdmessagefld->cmdmessage.ReturnCode =
2828 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2829 else
2830 pcmdmessagefld->cmdmessage.ReturnCode =
2831 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 2832 break;
bb263c4e 2833 }
1a4f550a 2834 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
69e562c2 2835 unsigned char *ver_addr;
7bc2b55a
DC		 2836 uint32_t user_len;
2837 int32_t cnt2end;
1a4f550a 2838 uint8_t *pQbuffer, *ptmpuserbuffer;
4bd173c3
BP		 2839
2840 user_len = pcmdmessagefld->cmdmessage.Length;
2841 if (user_len > ARCMSR_API_DATA_BUFLEN) {
1a4f550a
NC		 2842 retvalue = ARCMSR_MESSAGE_FAIL;
2843 goto message_out;
2844 }
4bd173c3
BP		 2845
2846 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
2847 if (!ver_addr) {
7bc2b55a 2848 retvalue = ARCMSR_MESSAGE_FAIL;
7bc2b55a
DC		 2849 goto message_out;
2850 }
4bd173c3
BP		 2851 ptmpuserbuffer = ver_addr;
2852
bb263c4e
CH		 2853 memcpy(ptmpuserbuffer,
2854 pcmdmessagefld->messagedatabuffer, user_len);
2855 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2e9feb43 2856 if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) {
1a4f550a
NC		 2857 struct SENSE_DATA *sensebuffer =
2858 (struct SENSE_DATA *)cmd->sense_buffer;
bb263c4e 2859 arcmsr_write_ioctldata2iop(acb);
1a4f550a 2860 /* has error report sensedata */
bb263c4e 2861 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
1a4f550a
NC		 2862 sensebuffer->SenseKey = ILLEGAL_REQUEST;
2863 sensebuffer->AdditionalSenseLength = 0x0A;
2864 sensebuffer->AdditionalSenseCode = 0x20;
2865 sensebuffer->Valid = 1;
2866 retvalue = ARCMSR_MESSAGE_FAIL;
2867 } else {
2e9feb43
CH		 2868 pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex];
2869 cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex;
2870 if (user_len > cnt2end) {
2871 memcpy(pQbuffer, ptmpuserbuffer, cnt2end);
2872 ptmpuserbuffer += cnt2end;
2873 user_len -= cnt2end;
2874 acb->wqbuf_putIndex = 0;
2875 pQbuffer = acb->wqbuffer;
2876 }
2877 memcpy(pQbuffer, ptmpuserbuffer, user_len);
2878 acb->wqbuf_putIndex += user_len;
2879 acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
2880 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2881 acb->acb_flags &=
1a4f550a 2882 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2e9feb43 2883 arcmsr_write_ioctldata2iop(acb);
1a4f550a 2884 }
1c57e86d 2885 }
bb263c4e
CH		 2886 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2887 kfree(ver_addr);
2888 if (acb->fw_flag == FW_DEADLOCK)
2889 pcmdmessagefld->cmdmessage.ReturnCode =
2890 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2891 else
2892 pcmdmessagefld->cmdmessage.ReturnCode =
2893 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 2894 break;
bb263c4e 2895 }
1c57e86d 2896 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
1a4f550a 2897 uint8_t *pQbuffer = acb->rqbuffer;
bb263c4e
CH		 2898
2899 arcmsr_clear_iop2drv_rqueue_buffer(acb);
2900 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
1a4f550a 2901 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2e9feb43
CH		 2902 acb->rqbuf_getIndex = 0;
2903 acb->rqbuf_putIndex = 0;
1a4f550a 2904 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
bb263c4e
CH		 2905 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2906 if (acb->fw_flag == FW_DEADLOCK)
ae52e7f0 2907 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 2908 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2909 else
ae52e7f0 2910 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e 2911 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 2912 break;
bb263c4e 2913 }
1c57e86d 2914 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
1a4f550a 2915 uint8_t *pQbuffer = acb->wqbuffer;
bb263c4e
CH		 2916 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2917 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2918 ACB_F_MESSAGE_WQBUFFER_READED);
2e9feb43
CH		 2919 acb->wqbuf_getIndex = 0;
2920 acb->wqbuf_putIndex = 0;
1a4f550a 2921 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
bb263c4e
CH		 2922 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2923 if (acb->fw_flag == FW_DEADLOCK)
2924 pcmdmessagefld->cmdmessage.ReturnCode =
2925 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2926 else
2927 pcmdmessagefld->cmdmessage.ReturnCode =
2928 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 2929 break;
bb263c4e 2930 }
1c57e86d 2931 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
1a4f550a 2932 uint8_t *pQbuffer;
bb263c4e
CH		 2933 arcmsr_clear_iop2drv_rqueue_buffer(acb);
2934 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2935 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2e9feb43
CH		 2936 acb->rqbuf_getIndex = 0;
2937 acb->rqbuf_putIndex = 0;
1a4f550a
NC		 2938 pQbuffer = acb->rqbuffer;
2939 memset(pQbuffer, 0, sizeof(struct QBUFFER));
bb263c4e
CH		 2940 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2941 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2942 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2943 ACB_F_MESSAGE_WQBUFFER_READED);
2e9feb43
CH		 2944 acb->wqbuf_getIndex = 0;
2945 acb->wqbuf_putIndex = 0;
1a4f550a
NC		 2946 pQbuffer = acb->wqbuffer;
2947 memset(pQbuffer, 0, sizeof(struct QBUFFER));
bb263c4e
CH		 2948 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2949 if (acb->fw_flag == FW_DEADLOCK)
ae52e7f0 2950 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 2951 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2952 else
ae52e7f0 2953 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e 2954 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 2955 break;
bb263c4e 2956 }
1c57e86d 2957 case ARCMSR_MESSAGE_RETURN_CODE_3F: {
bb263c4e 2958 if (acb->fw_flag == FW_DEADLOCK)
36b83ded 2959 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 2960 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2961 else
ae52e7f0 2962 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e 2963 ARCMSR_MESSAGE_RETURNCODE_3F;
1c57e86d 2964 break;
bb263c4e 2965 }
1c57e86d 2966 case ARCMSR_MESSAGE_SAY_HELLO: {
1a4f550a 2967 int8_t *hello_string = "Hello! I am ARCMSR";
bb263c4e 2968 if (acb->fw_flag == FW_DEADLOCK)
36b83ded 2969 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 2970 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2971 else
ae52e7f0 2972 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 2973 ARCMSR_MESSAGE_RETURNCODE_OK;
2974 memcpy(pcmdmessagefld->messagedatabuffer,
2975 hello_string, (int16_t)strlen(hello_string));
1c57e86d 2976 break;
bb263c4e
CH		 2977 }
2978 case ARCMSR_MESSAGE_SAY_GOODBYE: {
2979 if (acb->fw_flag == FW_DEADLOCK)
36b83ded 2980 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 2981 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2982 else
2983 pcmdmessagefld->cmdmessage.ReturnCode =
2984 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d
EC		 2985 arcmsr_iop_parking(acb);
2986 break;
bb263c4e
CH		 2987 }
2988 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2989 if (acb->fw_flag == FW_DEADLOCK)
36b83ded 2990 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 2991 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2992 else
2993 pcmdmessagefld->cmdmessage.ReturnCode =
2994 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d
EC		 2995 arcmsr_flush_adapter_cache(acb);
2996 break;
bb263c4e 2997 }
1c57e86d
EC		 2998 default:
2999 retvalue = ARCMSR_MESSAGE_FAIL;
bb263c4e
CH		 3000 pr_info("%s: unknown controlcode!\n", __func__);
3001 }
3002message_out:
3003 if (use_sg) {
3004 struct scatterlist *sg = scsi_sglist(cmd);
3005 kunmap_atomic(buffer - sg->offset);
1c57e86d 3006 }
1c57e86d
EC		 3007 return retvalue;
3008}
3009
3010static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
3011{
3012 struct list_head *head = &acb->ccb_free_list;
3013 struct CommandControlBlock *ccb = NULL;
ae52e7f0
NC		 3014 unsigned long flags;
3015 spin_lock_irqsave(&acb->ccblist_lock, flags);
1c57e86d
EC		 3016 if (!list_empty(head)) {
3017 ccb = list_entry(head->next, struct CommandControlBlock, list);
ae52e7f0 3018 list_del_init(&ccb->list);
cdd3cb15 3019 }else{
ae52e7f0 3020 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
c10b1d54 3021 return NULL;
1c57e86d 3022 }
ae52e7f0 3023 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 3024 return ccb;
3025}
3026
3027static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
3028 struct scsi_cmnd *cmd)
3029{
3030 switch (cmd->cmnd[0]) {
3031 case INQUIRY: {
3032 unsigned char inqdata[36];
3033 char *buffer;
deff2627 3034 struct scatterlist *sg;
1c57e86d
EC		 3035
3036 if (cmd->device->lun) {
3037 cmd->result = (DID_TIME_OUT << 16);
3038 cmd->scsi_done(cmd);
3039 return;
3040 }
3041 inqdata[0] = TYPE_PROCESSOR;
3042 /* Periph Qualifier & Periph Dev Type */
3043 inqdata[1] = 0;
3044 /* rem media bit & Dev Type Modifier */
3045 inqdata[2] = 0;
a1f6e021 3046 /* ISO, ECMA, & ANSI versions */
1c57e86d
EC		 3047 inqdata[4] = 31;
3048 /* length of additional data */
3049 strncpy(&inqdata[8], "Areca ", 8);
3050 /* Vendor Identification */
3051 strncpy(&inqdata[16], "RAID controller ", 16);
3052 /* Product Identification */
3053 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
1c57e86d 3054
deff2627 3055 sg = scsi_sglist(cmd);
77dfce07 3056 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
deff2627 3057
1c57e86d 3058 memcpy(buffer, inqdata, sizeof(inqdata));
deff2627 3059 sg = scsi_sglist(cmd);
77dfce07 3060 kunmap_atomic(buffer - sg->offset);
1c57e86d 3061
1c57e86d
EC		 3062 cmd->scsi_done(cmd);
3063 }
3064 break;
3065 case WRITE_BUFFER:
3066 case READ_BUFFER: {
3067 if (arcmsr_iop_message_xfer(acb, cmd))
3068 cmd->result = (DID_ERROR << 16);
3069 cmd->scsi_done(cmd);
3070 }
3071 break;
3072 default:
3073 cmd->scsi_done(cmd);
3074 }
3075}
3076
f281233d 3077static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
1c57e86d
EC		 3078 void (* done)(struct scsi_cmnd *))
3079{
3080 struct Scsi_Host *host = cmd->device->host;
1a4f550a 3081 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
1c57e86d
EC		 3082 struct CommandControlBlock *ccb;
3083 int target = cmd->device->id;
c4c1adb3
CH		 3084
3085 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED) {
3086 cmd->result = (DID_NO_CONNECT << 16);
3087 cmd->scsi_done(cmd);
3088 return 0;
3089 }
1c57e86d
EC		 3090 cmd->scsi_done = done;
3091 cmd->host_scribble = NULL;
3092 cmd->result = 0;
a1f6e021 3093 if (target == 16) {
1c57e86d
EC		 3094 /* virtual device for iop message transfer */
3095 arcmsr_handle_virtual_command(acb, cmd);
3096 return 0;
3097 }
1c57e86d
EC		 3098 ccb = arcmsr_get_freeccb(acb);
3099 if (!ccb)
3100 return SCSI_MLQUEUE_HOST_BUSY;
cdd3cb15 3101 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
76d78300
NC		 3102 cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
3103 cmd->scsi_done(cmd);
3104 return 0;
3105 }
1c57e86d
EC		 3106 arcmsr_post_ccb(acb, ccb);
3107 return 0;
3108}
3109
f281233d
JG		 3110static DEF_SCSI_QCMD(arcmsr_queue_command)
3111
1e9c8108 3112static void arcmsr_get_adapter_config(struct AdapterControlBlock *pACB, uint32_t *rwbuffer)
1c57e86d 3113{
1c57e86d 3114 int count;
1e9c8108
CH		 3115 uint32_t *acb_firm_model = (uint32_t *)pACB->firm_model;
3116 uint32_t *acb_firm_version = (uint32_t *)pACB->firm_version;
3117 uint32_t *acb_device_map = (uint32_t *)pACB->device_map;
3118 uint32_t *firm_model = &rwbuffer[15];
3119 uint32_t *firm_version = &rwbuffer[17];
3120 uint32_t *device_map = &rwbuffer[21];
3121
3122 count = 2;
3123 while (count) {
3124 *acb_firm_model = readl(firm_model);
1c57e86d 3125 acb_firm_model++;
1e9c8108 3126 firm_model++;
1c57e86d
EC		 3127 count--;
3128 }
1e9c8108
CH		 3129 count = 4;
3130 while (count) {
3131 *acb_firm_version = readl(firm_version);
1c57e86d 3132 acb_firm_version++;
1e9c8108 3133 firm_version++;
1c57e86d
EC		 3134 count--;
3135 }
1e9c8108
CH		 3136 count = 4;
3137 while (count) {
3138 *acb_device_map = readl(device_map);
cdd3cb15 3139 acb_device_map++;
1e9c8108 3140 device_map++;
cdd3cb15
NC		 3141 count--;
3142 }
1e9c8108
CH		 3143 pACB->signature = readl(&rwbuffer[0]);
3144 pACB->firm_request_len = readl(&rwbuffer[1]);
3145 pACB->firm_numbers_queue = readl(&rwbuffer[2]);
3146 pACB->firm_sdram_size = readl(&rwbuffer[3]);
3147 pACB->firm_hd_channels = readl(&rwbuffer[4]);
3148 pACB->firm_cfg_version = readl(&rwbuffer[25]);
a2c89bbc 3149 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
1e9c8108
CH		 3150 pACB->host->host_no,
3151 pACB->firm_model,
3152 pACB->firm_version);
3153}
3154
3155static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb)
3156{
3157 struct MessageUnit_A __iomem *reg = acb->pmuA;
3158
3159 arcmsr_wait_firmware_ready(acb);
3160 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3161 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
3162 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
3163 miscellaneous data' timeout \n", acb->host->host_no);
3164 return false;
3165 }
3166 arcmsr_get_adapter_config(acb, reg->message_rwbuffer);
ae52e7f0 3167 return true;
1c57e86d 3168}
626fa32c 3169static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb)
1a4f550a 3170{
02040670 3171 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 3172
7e315ffd
CH		 3173 arcmsr_wait_firmware_ready(acb);
3174 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
3175 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
3176 printk(KERN_ERR "arcmsr%d: can't set driver mode.\n", acb->host->host_no);
02040670 3177 return false;
7e315ffd 3178 }
ae52e7f0 3179 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
626fa32c 3180 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1a4f550a
NC		 3181 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
3182 miscellaneous data' timeout \n", acb->host->host_no);
02040670 3183 return false;
1a4f550a 3184 }
1e9c8108 3185 arcmsr_get_adapter_config(acb, reg->message_rwbuffer);
ae52e7f0 3186 return true;
1a4f550a 3187}
cdd3cb15 3188
626fa32c 3189static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB)
cdd3cb15 3190{
df9f0ee9 3191 uint32_t intmask_org;
c10b1d54 3192 struct MessageUnit_C __iomem *reg = pACB->pmuC;
1e9c8108 3193
cdd3cb15
NC		 3194 /* disable all outbound interrupt */
3195 intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
3196 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
3197 /* wait firmware ready */
df9f0ee9 3198 arcmsr_wait_firmware_ready(pACB);
cdd3cb15
NC		 3199 /* post "get config" instruction */
3200 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3201 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
3202 /* wait message ready */
df9f0ee9 3203 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
cdd3cb15
NC		 3204 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
3205 miscellaneous data' timeout \n", pACB->host->host_no);
3206 return false;
3207 }
1e9c8108 3208 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer);
cdd3cb15
NC		 3209 return true;
3210}
5b37479a
CH		 3211
3212static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb)
3213{
02040670 3214 struct MessageUnit_D *reg = acb->pmuD;
5b37479a 3215
5b37479a
CH		 3216 if (readl(acb->pmuD->outbound_doorbell) &
3217 ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
3218 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
3219 acb->pmuD->outbound_doorbell);/*clear interrupt*/
3220 }
b6b3084a 3221 arcmsr_wait_firmware_ready(acb);
5b37479a
CH		 3222 /* post "get config" instruction */
3223 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
3224 /* wait message ready */
3225 if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
3226 pr_notice("arcmsr%d: wait get adapter firmware "
3227 "miscellaneous data timeout\n", acb->host->host_no);
5b37479a
CH		 3228 return false;
3229 }
1e9c8108 3230 arcmsr_get_adapter_config(acb, reg->msgcode_rwbuffer);
5b37479a
CH		 3231 return true;
3232}
3233
23509024
CH		 3234static bool arcmsr_hbaE_get_config(struct AdapterControlBlock *pACB)
3235{
23509024 3236 struct MessageUnit_E __iomem *reg = pACB->pmuE;
22c4ae5b 3237 uint32_t intmask_org;
23509024
CH		 3238
3239 /* disable all outbound interrupt */
3240 intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
3241 writel(intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE, &reg->host_int_mask);
3242 /* wait firmware ready */
22c4ae5b 3243 arcmsr_wait_firmware_ready(pACB);
23509024
CH		 3244 mdelay(20);
3245 /* post "get config" instruction */
3246 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3247
3248 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3249 writel(pACB->out_doorbell, &reg->iobound_doorbell);
3250 /* wait message ready */
22c4ae5b 3251 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
23509024
CH		 3252 pr_notice("arcmsr%d: wait get adapter firmware "
3253 "miscellaneous data timeout\n", pACB->host->host_no);
3254 return false;
3255 }
1e9c8108 3256 arcmsr_get_adapter_config(pACB, reg->msgcode_rwbuffer);
23509024
CH		 3257 return true;
3258}
3259
ae52e7f0 3260static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
1a4f550a 3261{
3df824af
CH		 3262 bool rtn = false;
3263
3264 switch (acb->adapter_type) {
3265 case ACB_ADAPTER_TYPE_A:
626fa32c 3266 rtn = arcmsr_hbaA_get_config(acb);
3df824af
CH		 3267 break;
3268 case ACB_ADAPTER_TYPE_B:
626fa32c 3269 rtn = arcmsr_hbaB_get_config(acb);
3df824af
CH		 3270 break;
3271 case ACB_ADAPTER_TYPE_C:
626fa32c 3272 rtn = arcmsr_hbaC_get_config(acb);
3df824af 3273 break;
5b37479a
CH		 3274 case ACB_ADAPTER_TYPE_D:
3275 rtn = arcmsr_hbaD_get_config(acb);
3276 break;
23509024
CH		 3277 case ACB_ADAPTER_TYPE_E:
3278 rtn = arcmsr_hbaE_get_config(acb);
3279 break;
3df824af
CH		 3280 default:
3281 break;
3282 }
dd6206e1
CH		 3283 acb->maxOutstanding = acb->firm_numbers_queue - 1;
3284 if (acb->host->can_queue >= acb->firm_numbers_queue)
3285 acb->host->can_queue = acb->maxOutstanding;
cdd3cb15 3286 else
dd6206e1 3287 acb->maxOutstanding = acb->host->can_queue;
d076e4aa
CH		 3288 acb->maxFreeCCB = acb->host->can_queue;
3289 if (acb->maxFreeCCB < ARCMSR_MAX_FREECCB_NUM)
3290 acb->maxFreeCCB += 64;
3df824af 3291 return rtn;
1a4f550a
NC		 3292}
3293
626fa32c 3294static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb,
1c57e86d
EC		 3295 struct CommandControlBlock *poll_ccb)
3296{
80da1adb 3297 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 3298 struct CommandControlBlock *ccb;
ae52e7f0 3299 struct ARCMSR_CDB *arcmsr_cdb;
1c57e86d 3300 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
ae52e7f0 3301 int rtn;
cdd3cb15 3302 bool error;
9e386a55
CH		 3303 unsigned long ccb_cdb_phy;
3304
3305polling_hba_ccb_retry:
1c57e86d 3306 poll_count++;
1a4f550a 3307 outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
1c57e86d
EC		 3308 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
3309 while (1) {
3310 if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
cdd3cb15 3311 if (poll_ccb_done){
ae52e7f0 3312 rtn = SUCCESS;
1c57e86d 3313 break;
cdd3cb15
NC		 3314 }else {
3315 msleep(25);
3316 if (poll_count > 100){
ae52e7f0 3317 rtn = FAILED;
1c57e86d 3318 break;
ae52e7f0 3319 }
1a4f550a 3320 goto polling_hba_ccb_retry;
1c57e86d
EC		 3321 }
3322 }
9e386a55
CH		 3323 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
3324 if (acb->cdb_phyadd_hipart)
3325 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
3326 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
ae52e7f0 3327 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
cab5aece 3328 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
1a4f550a
NC		 3329 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
3330 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
3331 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
1c57e86d
EC		 3332 " poll command abort successfully \n"
3333 , acb->host->host_no
3334 , ccb->pcmd->device->id
9cb78c16 3335 , (u32)ccb->pcmd->device->lun
1c57e86d
EC		 3336 , ccb);
3337 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 3338 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 3339 continue;
3340 }
1a4f550a
NC		 3341 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3342 " command done ccb = '0x%p'"
a1f6e021 3343 "ccboutstandingcount = %d \n"
1c57e86d
EC		 3344 , acb->host->host_no
3345 , ccb
3346 , atomic_read(&acb->ccboutstandingcount));
3347 continue;
cdd3cb15
NC		 3348 }
3349 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
3350 arcmsr_report_ccb_state(acb, ccb, error);
1a4f550a 3351 }
ae52e7f0
NC		 3352 return rtn;
3353}
1a4f550a 3354
626fa32c 3355static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb,
1a4f550a
NC		 3356 struct CommandControlBlock *poll_ccb)
3357{
cdd3cb15 3358 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 3359 struct ARCMSR_CDB *arcmsr_cdb;
cdd3cb15
NC		 3360 struct CommandControlBlock *ccb;
3361 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
ae52e7f0 3362 int index, rtn;
cdd3cb15 3363 bool error;
e66764f2 3364 unsigned long ccb_cdb_phy;
97b99127 3365
e66764f2 3366polling_hbb_ccb_retry:
cdd3cb15
NC		 3367 poll_count++;
3368 /* clear doorbell interrupt */
ae52e7f0 3369 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
cdd3cb15
NC		 3370 while(1){
3371 index = reg->doneq_index;
c10b1d54
CH		 3372 flag_ccb = reg->done_qbuffer[index];
3373 if (flag_ccb == 0) {
cdd3cb15 3374 if (poll_ccb_done){
ae52e7f0 3375 rtn = SUCCESS;
cdd3cb15
NC		 3376 break;
3377 }else {
3378 msleep(25);
3379 if (poll_count > 100){
ae52e7f0 3380 rtn = FAILED;
cdd3cb15 3381 break;
1c57e86d 3382 }
cdd3cb15 3383 goto polling_hbb_ccb_retry;
1a4f550a 3384 }
cdd3cb15 3385 }
c10b1d54 3386 reg->done_qbuffer[index] = 0;
cdd3cb15
NC		 3387 index++;
3388 /*if last index number set it to 0 */
3389 index %= ARCMSR_MAX_HBB_POSTQUEUE;
3390 reg->doneq_index = index;
3391 /* check if command done with no error*/
e66764f2
CH		 3392 ccb_cdb_phy = (flag_ccb << 5) & 0xffffffff;
3393 if (acb->cdb_phyadd_hipart)
3394 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
3395 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
ae52e7f0 3396 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
cab5aece 3397 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
cdd3cb15
NC		 3398 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
3399 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
ae52e7f0
NC		 3400 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3401 " poll command abort successfully \n"
cdd3cb15
NC		 3402 ,acb->host->host_no
3403 ,ccb->pcmd->device->id
9cb78c16 3404 ,(u32)ccb->pcmd->device->lun
cdd3cb15
NC		 3405 ,ccb);
3406 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 3407 arcmsr_ccb_complete(ccb);
cdd3cb15
NC		 3408 continue;
3409 }
3410 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3411 " command done ccb = '0x%p'"
3412 "ccboutstandingcount = %d \n"
3413 , acb->host->host_no
3414 , ccb
3415 , atomic_read(&acb->ccboutstandingcount));
3416 continue;
3417 }
3418 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
3419 arcmsr_report_ccb_state(acb, ccb, error);
3420 }
3421 return rtn;
3422}
3423
626fa32c
CH		 3424static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb,
3425 struct CommandControlBlock *poll_ccb)
cdd3cb15 3426{
c10b1d54 3427 struct MessageUnit_C __iomem *reg = acb->pmuC;
c71ec551 3428 uint32_t flag_ccb;
cdd3cb15
NC		 3429 struct ARCMSR_CDB *arcmsr_cdb;
3430 bool error;
3431 struct CommandControlBlock *pCCB;
3432 uint32_t poll_ccb_done = 0, poll_count = 0;
3433 int rtn;
c71ec551
CH		 3434 unsigned long ccb_cdb_phy;
3435
cdd3cb15
NC		 3436polling_hbc_ccb_retry:
3437 poll_count++;
3438 while (1) {
3439 if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
3440 if (poll_ccb_done) {
3441 rtn = SUCCESS;
3442 break;
3443 } else {
3444 msleep(25);
3445 if (poll_count > 100) {
3446 rtn = FAILED;
3447 break;
1c57e86d 3448 }
cdd3cb15
NC		 3449 goto polling_hbc_ccb_retry;
3450 }
3451 }
3452 flag_ccb = readl(&reg->outbound_queueport_low);
3453 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
c71ec551
CH		 3454 if (acb->cdb_phyadd_hipart)
3455 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
3456 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
cdd3cb15 3457 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
cab5aece 3458 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
cdd3cb15
NC		 3459 /* check ifcommand done with no error*/
3460 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
3461 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3462 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3463 " poll command abort successfully \n"
1c57e86d 3464 , acb->host->host_no
cdd3cb15 3465 , pCCB->pcmd->device->id
9cb78c16 3466 , (u32)pCCB->pcmd->device->lun
cdd3cb15 3467 , pCCB);
9b44ffab
CIK		 3468 pCCB->pcmd->result = DID_ABORT << 16;
3469 arcmsr_ccb_complete(pCCB);
1a4f550a 3470 continue;
cdd3cb15
NC		 3471 }
3472 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3473 " command done ccb = '0x%p'"
3474 "ccboutstandingcount = %d \n"
3475 , acb->host->host_no
3476 , pCCB
3477 , atomic_read(&acb->ccboutstandingcount));
3478 continue;
ae52e7f0 3479 }
cdd3cb15
NC		 3480 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
3481 arcmsr_report_ccb_state(acb, pCCB, error);
3482 }
ae52e7f0 3483 return rtn;
1a4f550a 3484}
5b37479a
CH		 3485
3486static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb,
3487 struct CommandControlBlock *poll_ccb)
3488{
3489 bool error;
a36ade41 3490 uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb;
3b8155d5 3491 int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle;
18bc435e 3492 unsigned long flags, ccb_cdb_phy;
5b37479a
CH		 3493 struct ARCMSR_CDB *arcmsr_cdb;
3494 struct CommandControlBlock *pCCB;
3495 struct MessageUnit_D *pmu = acb->pmuD;
3496
3497polling_hbaD_ccb_retry:
3498 poll_count++;
3499 while (1) {
3b8155d5 3500 spin_lock_irqsave(&acb->doneq_lock, flags);
5b37479a
CH		 3501 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
3502 doneq_index = pmu->doneq_index;
3503 if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) {
3b8155d5 3504 spin_unlock_irqrestore(&acb->doneq_lock, flags);
5b37479a
CH		 3505 if (poll_ccb_done) {
3506 rtn = SUCCESS;
3507 break;
3508 } else {
3509 msleep(25);
3510 if (poll_count > 40) {
3511 rtn = FAILED;
3512 break;
3513 }
3514 goto polling_hbaD_ccb_retry;
3515 }
3516 }
3b8155d5
CH		 3517 toggle = doneq_index & 0x4000;
3518 index_stripped = (doneq_index & 0xFFF) + 1;
3519 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
3520 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
3521 ((toggle ^ 0x4000) + 1);
5b37479a 3522 doneq_index = pmu->doneq_index;
3b8155d5 3523 spin_unlock_irqrestore(&acb->doneq_lock, flags);
5b37479a
CH		 3524 flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow;
3525 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
a36ade41
CH		 3526 if (acb->cdb_phyadd_hipart)
3527 ccb_cdb_phy = ccb_cdb_phy | acb->cdb_phyadd_hipart;
5b37479a
CH		 3528 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset +
3529 ccb_cdb_phy);
3530 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock,
3531 arcmsr_cdb);
3532 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3533 if ((pCCB->acb != acb) ||
3534 (pCCB->startdone != ARCMSR_CCB_START)) {
3535 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3536 pr_notice("arcmsr%d: scsi id = %d "
3537 "lun = %d ccb = '0x%p' poll command "
3538 "abort successfully\n"
3539 , acb->host->host_no
3540 , pCCB->pcmd->device->id
3541 , (u32)pCCB->pcmd->device->lun
3542 , pCCB);
3543 pCCB->pcmd->result = DID_ABORT << 16;
3544 arcmsr_ccb_complete(pCCB);
3545 continue;
3546 }
3547 pr_notice("arcmsr%d: polling an illegal "
3548 "ccb command done ccb = '0x%p' "
3549 "ccboutstandingcount = %d\n"
3550 , acb->host->host_no
3551 , pCCB
3552 , atomic_read(&acb->ccboutstandingcount));
3553 continue;
3554 }
3555 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
3556 ? true : false;
3557 arcmsr_report_ccb_state(acb, pCCB, error);
3558 }
3559 return rtn;
3560}
3561
23509024
CH		 3562static int arcmsr_hbaE_polling_ccbdone(struct AdapterControlBlock *acb,
3563 struct CommandControlBlock *poll_ccb)
3564{
3565 bool error;
3566 uint32_t poll_ccb_done = 0, poll_count = 0, doneq_index;
3567 uint16_t cmdSMID;
3568 unsigned long flags;
3569 int rtn;
3570 struct CommandControlBlock *pCCB;
3571 struct MessageUnit_E __iomem *reg = acb->pmuE;
3572
3573 polling_hbaC_ccb_retry:
3574 poll_count++;
3575 while (1) {
3576 spin_lock_irqsave(&acb->doneq_lock, flags);
3577 doneq_index = acb->doneq_index;
3578 if ((readl(&reg->reply_post_producer_index) & 0xFFFF) ==
3579 doneq_index) {
3580 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3581 if (poll_ccb_done) {
3582 rtn = SUCCESS;
3583 break;
3584 } else {
3585 msleep(25);
3586 if (poll_count > 40) {
3587 rtn = FAILED;
3588 break;
3589 }
3590 goto polling_hbaC_ccb_retry;
3591 }
3592 }
3593 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID;
3594 doneq_index++;
3595 if (doneq_index >= acb->completionQ_entry)
3596 doneq_index = 0;
3597 acb->doneq_index = doneq_index;
3598 spin_unlock_irqrestore(&acb->doneq_lock, flags);
3599 pCCB = acb->pccb_pool[cmdSMID];
3600 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3601 /* check if command done with no error*/
3602 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
3603 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3604 pr_notice("arcmsr%d: scsi id = %d "
3605 "lun = %d ccb = '0x%p' poll command "
3606 "abort successfully\n"
3607 , acb->host->host_no
3608 , pCCB->pcmd->device->id
3609 , (u32)pCCB->pcmd->device->lun
3610 , pCCB);
3611 pCCB->pcmd->result = DID_ABORT << 16;
3612 arcmsr_ccb_complete(pCCB);
3613 continue;
3614 }
3615 pr_notice("arcmsr%d: polling an illegal "
3616 "ccb command done ccb = '0x%p' "
3617 "ccboutstandingcount = %d\n"
3618 , acb->host->host_no
3619 , pCCB
3620 , atomic_read(&acb->ccboutstandingcount));
3621 continue;
3622 }
3623 error = (acb->pCompletionQ[doneq_index].cmdFlag &
3624 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
3625 arcmsr_report_ccb_state(acb, pCCB, error);
3626 }
3627 writel(doneq_index, &reg->reply_post_consumer_index);
3628 return rtn;
3629}
3630
ae52e7f0 3631static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
1a4f550a
NC		 3632 struct CommandControlBlock *poll_ccb)
3633{
ae52e7f0 3634 int rtn = 0;
1a4f550a
NC		 3635 switch (acb->adapter_type) {
3636
3637 case ACB_ADAPTER_TYPE_A: {
626fa32c 3638 rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb);
1a4f550a
NC		 3639 }
3640 break;
3641
3642 case ACB_ADAPTER_TYPE_B: {
626fa32c 3643 rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb);
1c57e86d 3644 }
cdd3cb15
NC		 3645 break;
3646 case ACB_ADAPTER_TYPE_C: {
626fa32c 3647 rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb);
cdd3cb15 3648 }
5b37479a
CH		 3649 break;
3650 case ACB_ADAPTER_TYPE_D:
3651 rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb);
3652 break;
23509024
CH		 3653 case ACB_ADAPTER_TYPE_E:
3654 rtn = arcmsr_hbaE_polling_ccbdone(acb, poll_ccb);
3655 break;
1c57e86d 3656 }
ae52e7f0 3657 return rtn;
1c57e86d 3658}
1a4f550a 3659
b416c099
CH		 3660static void arcmsr_set_iop_datetime(struct timer_list *t)
3661{
3662 struct AdapterControlBlock *pacb = from_timer(pacb, t, refresh_timer);
45596c78
AB		 3663 unsigned int next_time;
3664 struct tm tm;
3665
b416c099
CH		 3666 union {
3667 struct {
3668 uint16_t signature;
3669 uint8_t year;
3670 uint8_t month;
3671 uint8_t date;
3672 uint8_t hour;
3673 uint8_t minute;
3674 uint8_t second;
3675 } a;
3676 struct {
3677 uint32_t msg_time[2];
3678 } b;
3679 } datetime;
3680
45596c78 3681 time64_to_tm(ktime_get_real_seconds(), -sys_tz.tz_minuteswest * 60, &tm);
b416c099
CH		 3682
3683 datetime.a.signature = 0x55AA;
45596c78
AB		 3684 datetime.a.year = tm.tm_year - 100; /* base 2000 instead of 1900 */
3685 datetime.a.month = tm.tm_mon;
3686 datetime.a.date = tm.tm_mday;
3687 datetime.a.hour = tm.tm_hour;
3688 datetime.a.minute = tm.tm_min;
3689 datetime.a.second = tm.tm_sec;
b416c099
CH		 3690
3691 switch (pacb->adapter_type) {
3692 case ACB_ADAPTER_TYPE_A: {
3693 struct MessageUnit_A __iomem *reg = pacb->pmuA;
3694 writel(datetime.b.msg_time[0], &reg->message_rwbuffer[0]);
3695 writel(datetime.b.msg_time[1], &reg->message_rwbuffer[1]);
3696 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, &reg->inbound_msgaddr0);
3697 break;
3698 }
3699 case ACB_ADAPTER_TYPE_B: {
3700 uint32_t __iomem *rwbuffer;
3701 struct MessageUnit_B *reg = pacb->pmuB;
3702 rwbuffer = reg->message_rwbuffer;
3703 writel(datetime.b.msg_time[0], rwbuffer++);
3704 writel(datetime.b.msg_time[1], rwbuffer++);
3705 writel(ARCMSR_MESSAGE_SYNC_TIMER, reg->drv2iop_doorbell);
3706 break;
3707 }
3708 case ACB_ADAPTER_TYPE_C: {
3709 struct MessageUnit_C __iomem *reg = pacb->pmuC;
3710 writel(datetime.b.msg_time[0], &reg->msgcode_rwbuffer[0]);
3711 writel(datetime.b.msg_time[1], &reg->msgcode_rwbuffer[1]);
3712 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, &reg->inbound_msgaddr0);
3713 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
3714 break;
3715 }
3716 case ACB_ADAPTER_TYPE_D: {
3717 uint32_t __iomem *rwbuffer;
3718 struct MessageUnit_D *reg = pacb->pmuD;
3719 rwbuffer = reg->msgcode_rwbuffer;
3720 writel(datetime.b.msg_time[0], rwbuffer++);
3721 writel(datetime.b.msg_time[1], rwbuffer++);
3722 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, reg->inbound_msgaddr0);
3723 break;
3724 }
3725 case ACB_ADAPTER_TYPE_E: {
3726 struct MessageUnit_E __iomem *reg = pacb->pmuE;
3727 writel(datetime.b.msg_time[0], &reg->msgcode_rwbuffer[0]);
3728 writel(datetime.b.msg_time[1], &reg->msgcode_rwbuffer[1]);
3729 writel(ARCMSR_INBOUND_MESG0_SYNC_TIMER, &reg->inbound_msgaddr0);
3730 pacb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3731 writel(pacb->out_doorbell, &reg->iobound_doorbell);
3732 break;
3733 }
3734 }
3735 if (sys_tz.tz_minuteswest)
3736 next_time = ARCMSR_HOURS;
3737 else
3738 next_time = ARCMSR_MINUTES;
3739 mod_timer(&pacb->refresh_timer, jiffies + msecs_to_jiffies(next_time));
3740}
3741
1a4f550a 3742static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
a1f6e021 3743{
ae52e7f0 3744 uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
6e38adfc 3745 dma_addr_t dma_coherent_handle;
e2c70425 3746
1a4f550a
NC		 3747 /*
3748 ********************************************************************
3749 ** here we need to tell iop 331 our freeccb.HighPart
3750 ** if freeccb.HighPart is not zero
3751 ********************************************************************
3752 */
6e38adfc
CH		 3753 switch (acb->adapter_type) {
3754 case ACB_ADAPTER_TYPE_B:
5b37479a 3755 case ACB_ADAPTER_TYPE_D:
6e38adfc
CH		 3756 dma_coherent_handle = acb->dma_coherent_handle2;
3757 break;
23509024
CH		 3758 case ACB_ADAPTER_TYPE_E:
3759 dma_coherent_handle = acb->dma_coherent_handle +
3760 offsetof(struct CommandControlBlock, arcmsr_cdb);
3761 break;
6e38adfc
CH		 3762 default:
3763 dma_coherent_handle = acb->dma_coherent_handle;
3764 break;
3765 }
3766 cdb_phyaddr = lower_32_bits(dma_coherent_handle);
3767 cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle);
cdd3cb15 3768 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
7860a486 3769 acb->cdb_phyadd_hipart = ((uint64_t)cdb_phyaddr_hi32) << 32;
1a4f550a
NC		 3770 /*
3771 ***********************************************************************
3772 ** if adapter type B, set window of "post command Q"
3773 ***********************************************************************
3774 */
3775 switch (acb->adapter_type) {
3776
3777 case ACB_ADAPTER_TYPE_A: {
ae52e7f0 3778 if (cdb_phyaddr_hi32 != 0) {
80da1adb 3779 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 3780 writel(ARCMSR_SIGNATURE_SET_CONFIG, \
3781 &reg->message_rwbuffer[0]);
ae52e7f0 3782 writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
1a4f550a
NC		 3783 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
3784 &reg->inbound_msgaddr0);
626fa32c 3785 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1a4f550a
NC		 3786 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
3787 part physical address timeout\n",
3788 acb->host->host_no);
3789 return 1;
a1f6e021 3790 }
1a4f550a
NC		 3791 }
3792 }
3793 break;
a1f6e021 3794
1a4f550a 3795 case ACB_ADAPTER_TYPE_B: {
80da1adb 3796 uint32_t __iomem *rwbuffer;
a1f6e021 3797
80da1adb 3798 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a
NC		 3799 reg->postq_index = 0;
3800 reg->doneq_index = 0;
ae52e7f0 3801 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
626fa32c 3802 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
47268a4f 3803 printk(KERN_NOTICE "arcmsr%d: cannot set driver mode\n", \
1a4f550a
NC		 3804 acb->host->host_no);
3805 return 1;
3806 }
ae52e7f0 3807 rwbuffer = reg->message_rwbuffer;
1a4f550a
NC		 3808 /* driver "set config" signature */
3809 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
3810 /* normal should be zero */
ae52e7f0 3811 writel(cdb_phyaddr_hi32, rwbuffer++);
1a4f550a 3812 /* postQ size (256 + 8)*4 */
6e38adfc 3813 writel(cdb_phyaddr, rwbuffer++);
1a4f550a 3814 /* doneQ size (256 + 8)*4 */
6e38adfc 3815 writel(cdb_phyaddr + 1056, rwbuffer++);
1a4f550a
NC		 3816 /* ccb maxQ size must be --> [(256 + 8)*4]*/
3817 writel(1056, rwbuffer);
3818
ae52e7f0 3819 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
626fa32c 3820 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1a4f550a
NC		 3821 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
3822 timeout \n",acb->host->host_no);
3823 return 1;
3824 }
a5849726 3825 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
626fa32c 3826 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
a5849726
CH		 3827 pr_err("arcmsr%d: can't set driver mode.\n",
3828 acb->host->host_no);
3829 return 1;
3830 }
1a4f550a
NC		 3831 }
3832 break;
cdd3cb15 3833 case ACB_ADAPTER_TYPE_C: {
c10b1d54 3834 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15 3835
8b7eb86f
TH		 3836 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n",
3837 acb->adapter_index, cdb_phyaddr_hi32);
cdd3cb15
NC		 3838 writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
3839 writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
3840 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
3841 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
626fa32c 3842 if (!arcmsr_hbaC_wait_msgint_ready(acb)) {
cdd3cb15
NC		 3843 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
3844 timeout \n", acb->host->host_no);
3845 return 1;
3846 }
3847 }
5b37479a
CH		 3848 break;
3849 case ACB_ADAPTER_TYPE_D: {
3850 uint32_t __iomem *rwbuffer;
3851 struct MessageUnit_D *reg = acb->pmuD;
3852 reg->postq_index = 0;
3853 reg->doneq_index = 0;
3854 rwbuffer = reg->msgcode_rwbuffer;
3855 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
3856 writel(cdb_phyaddr_hi32, rwbuffer++);
3857 writel(cdb_phyaddr, rwbuffer++);
3858 writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE *
3859 sizeof(struct InBound_SRB)), rwbuffer++);
3860 writel(0x100, rwbuffer);
3861 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0);
3862 if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
3863 pr_notice("arcmsr%d: 'set command Q window' timeout\n",
3864 acb->host->host_no);
3865 return 1;
3866 }
3867 }
3868 break;
23509024
CH		 3869 case ACB_ADAPTER_TYPE_E: {
3870 struct MessageUnit_E __iomem *reg = acb->pmuE;
3871 writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
3872 writel(ARCMSR_SIGNATURE_1884, &reg->msgcode_rwbuffer[1]);
3873 writel(cdb_phyaddr, &reg->msgcode_rwbuffer[2]);
3874 writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[3]);
3875 writel(acb->ccbsize, &reg->msgcode_rwbuffer[4]);
3876 dma_coherent_handle = acb->dma_coherent_handle2;
3877 cdb_phyaddr = (uint32_t)(dma_coherent_handle & 0xffffffff);
3878 cdb_phyaddr_hi32 = (uint32_t)((dma_coherent_handle >> 16) >> 16);
3879 writel(cdb_phyaddr, &reg->msgcode_rwbuffer[5]);
3880 writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[6]);
381d66da 3881 writel(acb->ioqueue_size, &reg->msgcode_rwbuffer[7]);
23509024
CH		 3882 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
3883 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3884 writel(acb->out_doorbell, &reg->iobound_doorbell);
3885 if (!arcmsr_hbaE_wait_msgint_ready(acb)) {
3886 pr_notice("arcmsr%d: 'set command Q window' timeout \n",
3887 acb->host->host_no);
3888 return 1;
3889 }
3890 }
3891 break;
1a4f550a
NC		 3892 }
3893 return 0;
3894}
a1f6e021 3895
1a4f550a
NC		 3896static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
3897{
3898 uint32_t firmware_state = 0;
1a4f550a
NC		 3899 switch (acb->adapter_type) {
3900
3901 case ACB_ADAPTER_TYPE_A: {
80da1adb 3902 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 3903 do {
c2c62ebc
CH		 3904 if (!(acb->acb_flags & ACB_F_IOP_INITED))
3905 msleep(20);
1a4f550a
NC		 3906 firmware_state = readl(&reg->outbound_msgaddr1);
3907 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
3908 }
3909 break;
3910
3911 case ACB_ADAPTER_TYPE_B: {
80da1adb 3912 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 3913 do {
c2c62ebc
CH		 3914 if (!(acb->acb_flags & ACB_F_IOP_INITED))
3915 msleep(20);
ae52e7f0 3916 firmware_state = readl(reg->iop2drv_doorbell);
1a4f550a 3917 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
ae52e7f0 3918 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
1a4f550a
NC		 3919 }
3920 break;
cdd3cb15 3921 case ACB_ADAPTER_TYPE_C: {
c10b1d54 3922 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15 3923 do {
c2c62ebc
CH		 3924 if (!(acb->acb_flags & ACB_F_IOP_INITED))
3925 msleep(20);
cdd3cb15
NC		 3926 firmware_state = readl(&reg->outbound_msgaddr1);
3927 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
3928 }
5b37479a
CH		 3929 break;
3930 case ACB_ADAPTER_TYPE_D: {
3931 struct MessageUnit_D *reg = acb->pmuD;
3932 do {
c2c62ebc
CH		 3933 if (!(acb->acb_flags & ACB_F_IOP_INITED))
3934 msleep(20);
5b37479a
CH		 3935 firmware_state = readl(reg->outbound_msgaddr1);
3936 } while ((firmware_state &
3937 ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0);
3938 }
3939 break;
23509024
CH		 3940 case ACB_ADAPTER_TYPE_E: {
3941 struct MessageUnit_E __iomem *reg = acb->pmuE;
3942 do {
c2c62ebc
CH		 3943 if (!(acb->acb_flags & ACB_F_IOP_INITED))
3944 msleep(20);
23509024
CH		 3945 firmware_state = readl(&reg->outbound_msgaddr1);
3946 } while ((firmware_state & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0);
3947 }
3948 break;
a1f6e021 3949 }
1a4f550a
NC		 3950}
3951
6ae9abe0 3952static void arcmsr_request_device_map(struct timer_list *t)
23509024 3953{
6ae9abe0 3954 struct AdapterControlBlock *acb = from_timer(acb, t, eternal_timer);
23509024 3955 if (unlikely(atomic_read(&acb->rq_map_token) == 0) ||
6ae9abe0
CH		 3956 (acb->acb_flags & ACB_F_BUS_RESET) ||
3957 (acb->acb_flags & ACB_F_ABORT)) {
23509024
CH		 3958 mod_timer(&acb->eternal_timer,
3959 jiffies + msecs_to_jiffies(6 * HZ));
3960 } else {
3961 acb->fw_flag = FW_NORMAL;
3962 if (atomic_read(&acb->ante_token_value) ==
3963 atomic_read(&acb->rq_map_token)) {
3964 atomic_set(&acb->rq_map_token, 16);
3965 }
3966 atomic_set(&acb->ante_token_value,
3967 atomic_read(&acb->rq_map_token));
3968 if (atomic_dec_and_test(&acb->rq_map_token)) {
3969 mod_timer(&acb->eternal_timer, jiffies +
3970 msecs_to_jiffies(6 * HZ));
3971 return;
3972 }
6ae9abe0 3973 switch (acb->adapter_type) {
36b83ded 3974 case ACB_ADAPTER_TYPE_A: {
6ae9abe0
CH		 3975 struct MessageUnit_A __iomem *reg = acb->pmuA;
3976 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3977 break;
3978 }
36b83ded 3979 case ACB_ADAPTER_TYPE_B: {
6ae9abe0
CH		 3980 struct MessageUnit_B *reg = acb->pmuB;
3981 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
3982 break;
3983 }
cdd3cb15 3984 case ACB_ADAPTER_TYPE_C: {
6ae9abe0
CH		 3985 struct MessageUnit_C __iomem *reg = acb->pmuC;
3986 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3987 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
3988 break;
3989 }
3990 case ACB_ADAPTER_TYPE_D: {
3991 struct MessageUnit_D *reg = acb->pmuD;
3992 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
3993 break;
3994 }
3995 case ACB_ADAPTER_TYPE_E: {
3996 struct MessageUnit_E __iomem *reg = acb->pmuE;
3997 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3998 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
3999 writel(acb->out_doorbell, &reg->iobound_doorbell);
4000 break;
4001 }
4002 default:
4003 return;
cdd3cb15 4004 }
6ae9abe0
CH		 4005 acb->acb_flags |= ACB_F_MSG_GET_CONFIG;
4006 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
36b83ded
NC		 4007 }
4008}
4009
626fa32c 4010static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb)
1a4f550a 4011{
80da1adb 4012 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 4013 acb->acb_flags |= ACB_F_MSG_START_BGRB;
4014 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
626fa32c 4015 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1a4f550a 4016 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
948dff7a 4017 rebuild' timeout \n", acb->host->host_no);
a1f6e021 4018 }
a1f6e021 4019}
4020
626fa32c 4021static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb)
1a4f550a 4022{
80da1adb 4023 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 4024 acb->acb_flags |= ACB_F_MSG_START_BGRB;
ae52e7f0 4025 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
626fa32c 4026 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1a4f550a 4027 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
948dff7a 4028 rebuild' timeout \n",acb->host->host_no);
1a4f550a
NC		 4029 }
4030}
1c57e86d 4031
626fa32c 4032static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB)
cdd3cb15 4033{
c10b1d54 4034 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
cdd3cb15
NC		 4035 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
4036 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
4037 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
626fa32c 4038 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
cdd3cb15 4039 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
948dff7a 4040 rebuild' timeout \n", pACB->host->host_no);
cdd3cb15
NC		 4041 }
4042 return;
4043}
5b37479a
CH		 4044
4045static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB)
4046{
4047 struct MessageUnit_D *pmu = pACB->pmuD;
4048
4049 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
4050 writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0);
4051 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
4052 pr_notice("arcmsr%d: wait 'start adapter "
948dff7a 4053 "background rebuild' timeout\n", pACB->host->host_no);
5b37479a
CH		 4054 }
4055}
4056
23509024
CH		 4057static void arcmsr_hbaE_start_bgrb(struct AdapterControlBlock *pACB)
4058{
4059 struct MessageUnit_E __iomem *pmu = pACB->pmuE;
4060
4061 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
4062 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &pmu->inbound_msgaddr0);
4063 pACB->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE;
4064 writel(pACB->out_doorbell, &pmu->iobound_doorbell);
4065 if (!arcmsr_hbaE_wait_msgint_ready(pACB)) {
4066 pr_notice("arcmsr%d: wait 'start adapter "
948dff7a 4067 "background rebuild' timeout \n", pACB->host->host_no);
23509024
CH		 4068 }
4069}
4070
1a4f550a 4071static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
1c57e86d 4072{
1a4f550a
NC		 4073 switch (acb->adapter_type) {
4074 case ACB_ADAPTER_TYPE_A:
626fa32c 4075 arcmsr_hbaA_start_bgrb(acb);
1a4f550a
NC		 4076 break;
4077 case ACB_ADAPTER_TYPE_B:
626fa32c 4078 arcmsr_hbaB_start_bgrb(acb);
1a4f550a 4079 break;
cdd3cb15 4080 case ACB_ADAPTER_TYPE_C:
626fa32c 4081 arcmsr_hbaC_start_bgrb(acb);
5b37479a
CH		 4082 break;
4083 case ACB_ADAPTER_TYPE_D:
4084 arcmsr_hbaD_start_bgrb(acb);
4085 break;
23509024
CH		 4086 case ACB_ADAPTER_TYPE_E:
4087 arcmsr_hbaE_start_bgrb(acb);
4088 break;
1a4f550a
NC		 4089 }
4090}
1c57e86d 4091
1a4f550a
NC		 4092static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
4093{
4094 switch (acb->adapter_type) {
4095 case ACB_ADAPTER_TYPE_A: {
80da1adb 4096 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 4097 uint32_t outbound_doorbell;
4098 /* empty doorbell Qbuffer if door bell ringed */
4099 outbound_doorbell = readl(&reg->outbound_doorbell);
4100 /*clear doorbell interrupt */
4101 writel(outbound_doorbell, &reg->outbound_doorbell);
4102 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
4103 }
4104 break;
1c57e86d 4105
1a4f550a 4106 case ACB_ADAPTER_TYPE_B: {
80da1adb 4107 struct MessageUnit_B *reg = acb->pmuB;
2124c5b2
CH		 4108 uint32_t outbound_doorbell, i;
4109 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
ae52e7f0 4110 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1a4f550a 4111 /* let IOP know data has been read */
2124c5b2
CH		 4112 for(i=0; i < 200; i++) {
4113 msleep(20);
4114 outbound_doorbell = readl(reg->iop2drv_doorbell);
4115 if( outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
4116 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
4117 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
4118 } else
4119 break;
4120 }
1a4f550a
NC		 4121 }
4122 break;
cdd3cb15 4123 case ACB_ADAPTER_TYPE_C: {
c10b1d54 4124 struct MessageUnit_C __iomem *reg = acb->pmuC;
5eb6bfa0 4125 uint32_t outbound_doorbell, i;
cdd3cb15
NC		 4126 /* empty doorbell Qbuffer if door bell ringed */
4127 outbound_doorbell = readl(&reg->outbound_doorbell);
4128 writel(outbound_doorbell, &reg->outbound_doorbell_clear);
4129 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
5eb6bfa0
CH		 4130 for (i = 0; i < 200; i++) {
4131 msleep(20);
4132 outbound_doorbell = readl(&reg->outbound_doorbell);
4133 if (outbound_doorbell &
4134 ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
4135 writel(outbound_doorbell,
4136 &reg->outbound_doorbell_clear);
4137 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK,
4138 &reg->inbound_doorbell);
4139 } else
4140 break;
4141 }
cdd3cb15 4142 }
5b37479a
CH		 4143 break;
4144 case ACB_ADAPTER_TYPE_D: {
4145 struct MessageUnit_D *reg = acb->pmuD;
4146 uint32_t outbound_doorbell, i;
4147 /* empty doorbell Qbuffer if door bell ringed */
4148 outbound_doorbell = readl(reg->outbound_doorbell);
4149 writel(outbound_doorbell, reg->outbound_doorbell);
4150 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
4151 reg->inbound_doorbell);
4152 for (i = 0; i < 200; i++) {
4153 msleep(20);
4154 outbound_doorbell = readl(reg->outbound_doorbell);
4155 if (outbound_doorbell &
4156 ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) {
4157 writel(outbound_doorbell,
4158 reg->outbound_doorbell);
4159 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
4160 reg->inbound_doorbell);
4161 } else
4162 break;
4163 }
4164 }
4165 break;
23509024
CH		 4166 case ACB_ADAPTER_TYPE_E: {
4167 struct MessageUnit_E __iomem *reg = acb->pmuE;
4168 uint32_t i, tmp;
4169
4170 acb->in_doorbell = readl(&reg->iobound_doorbell);
4171 writel(0, &reg->host_int_status); /*clear interrupt*/
4172 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4173 writel(acb->out_doorbell, &reg->iobound_doorbell);
4174 for(i=0; i < 200; i++) {
4175 msleep(20);
4176 tmp = acb->in_doorbell;
4177 acb->in_doorbell = readl(&reg->iobound_doorbell);
4178 if((tmp ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) {
4179 writel(0, &reg->host_int_status); /*clear interrupt*/
4180 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK;
4181 writel(acb->out_doorbell, &reg->iobound_doorbell);
4182 } else
4183 break;
4184 }
4185 }
4186 break;
1c57e86d 4187 }
1a4f550a 4188}
1c57e86d 4189
76d78300
NC		 4190static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
4191{
4192 switch (acb->adapter_type) {
4193 case ACB_ADAPTER_TYPE_A:
4194 return;
4195 case ACB_ADAPTER_TYPE_B:
4196 {
4197 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 4198 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
626fa32c 4199 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
76d78300
NC		 4200 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
4201 return;
4202 }
4203 }
4204 break;
cdd3cb15
NC		 4205 case ACB_ADAPTER_TYPE_C:
4206 return;
76d78300
NC		 4207 }
4208 return;
4209}
4210
36b83ded
NC		 4211static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
4212{
4213 uint8_t value[64];
cdd3cb15
NC		 4214 int i, count = 0;
4215 struct MessageUnit_A __iomem *pmuA = acb->pmuA;
4216 struct MessageUnit_C __iomem *pmuC = acb->pmuC;
5b37479a 4217 struct MessageUnit_D *pmuD = acb->pmuD;
6ad819b0 4218
36b83ded 4219 /* backup pci config data */
cdd3cb15 4220 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
36b83ded
NC		 4221 for (i = 0; i < 64; i++) {
4222 pci_read_config_byte(acb->pdev, i, &value[i]);
4223 }
4224 /* hardware reset signal */
ca2ade24 4225 if (acb->dev_id == 0x1680) {
cdd3cb15 4226 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
ca2ade24 4227 } else if (acb->dev_id == 0x1880) {
cdd3cb15
NC		 4228 do {
4229 count++;
4230 writel(0xF, &pmuC->write_sequence);
4231 writel(0x4, &pmuC->write_sequence);
4232 writel(0xB, &pmuC->write_sequence);
4233 writel(0x2, &pmuC->write_sequence);
4234 writel(0x7, &pmuC->write_sequence);
4235 writel(0xD, &pmuC->write_sequence);
6ad819b0 4236 } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
cdd3cb15 4237 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
23509024
CH		 4238 } else if (acb->dev_id == 0x1884) {
4239 struct MessageUnit_E __iomem *pmuE = acb->pmuE;
4240 do {
4241 count++;
4242 writel(0x4, &pmuE->write_sequence_3xxx);
4243 writel(0xB, &pmuE->write_sequence_3xxx);
4244 writel(0x2, &pmuE->write_sequence_3xxx);
4245 writel(0x7, &pmuE->write_sequence_3xxx);
4246 writel(0xD, &pmuE->write_sequence_3xxx);
4247 mdelay(10);
4248 } while (((readl(&pmuE->host_diagnostic_3xxx) &
4249 ARCMSR_ARC1884_DiagWrite_ENABLE) == 0) && (count < 5));
4250 writel(ARCMSR_ARC188X_RESET_ADAPTER, &pmuE->host_diagnostic_3xxx);
ca2ade24 4251 } else if (acb->dev_id == 0x1214) {
5b37479a 4252 writel(0x20, pmuD->reset_request);
ae52e7f0 4253 } else {
cdd3cb15 4254 pci_write_config_byte(acb->pdev, 0x84, 0x20);
ae52e7f0 4255 }
cdd3cb15 4256 msleep(2000);
36b83ded
NC		 4257 /* write back pci config data */
4258 for (i = 0; i < 64; i++) {
4259 pci_write_config_byte(acb->pdev, i, value[i]);
4260 }
4261 msleep(1000);
4262 return;
4263}
72a7f313
CH		 4264
4265static bool arcmsr_reset_in_progress(struct AdapterControlBlock *acb)
4266{
4267 bool rtn = true;
4268
4269 switch(acb->adapter_type) {
4270 case ACB_ADAPTER_TYPE_A:{
4271 struct MessageUnit_A __iomem *reg = acb->pmuA;
4272 rtn = ((readl(&reg->outbound_msgaddr1) &
4273 ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) ? true : false;
4274 }
4275 break;
4276 case ACB_ADAPTER_TYPE_B:{
4277 struct MessageUnit_B *reg = acb->pmuB;
4278 rtn = ((readl(reg->iop2drv_doorbell) &
4279 ARCMSR_MESSAGE_FIRMWARE_OK) == 0) ? true : false;
4280 }
4281 break;
4282 case ACB_ADAPTER_TYPE_C:{
4283 struct MessageUnit_C __iomem *reg = acb->pmuC;
4284 rtn = (readl(&reg->host_diagnostic) & 0x04) ? true : false;
4285 }
4286 break;
4287 case ACB_ADAPTER_TYPE_D:{
4288 struct MessageUnit_D *reg = acb->pmuD;
4289 rtn = ((readl(reg->sample_at_reset) & 0x80) == 0) ?
4290 true : false;
4291 }
4292 break;
23509024
CH		 4293 case ACB_ADAPTER_TYPE_E:{
4294 struct MessageUnit_E __iomem *reg = acb->pmuE;
4295 rtn = (readl(&reg->host_diagnostic_3xxx) &
4296 ARCMSR_ARC188X_RESET_ADAPTER) ? true : false;
4297 }
4298 break;
72a7f313
CH		 4299 }
4300 return rtn;
4301}
4302
1a4f550a
NC		 4303static void arcmsr_iop_init(struct AdapterControlBlock *acb)
4304{
4305 uint32_t intmask_org;
cdd3cb15
NC		 4306 /* disable all outbound interrupt */
4307 intmask_org = arcmsr_disable_outbound_ints(acb);
76d78300
NC		 4308 arcmsr_wait_firmware_ready(acb);
4309 arcmsr_iop_confirm(acb);
1a4f550a
NC		 4310 /*start background rebuild*/
4311 arcmsr_start_adapter_bgrb(acb);
4312 /* empty doorbell Qbuffer if door bell ringed */
4313 arcmsr_clear_doorbell_queue_buffer(acb);
76d78300 4314 arcmsr_enable_eoi_mode(acb);
1a4f550a
NC		 4315 /* enable outbound Post Queue,outbound doorbell Interrupt */
4316 arcmsr_enable_outbound_ints(acb, intmask_org);
1c57e86d
EC		 4317 acb->acb_flags |= ACB_F_IOP_INITED;
4318}
4319
36b83ded 4320static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
1c57e86d 4321{
1c57e86d
EC		 4322 struct CommandControlBlock *ccb;
4323 uint32_t intmask_org;
36b83ded 4324 uint8_t rtnval = 0x00;
1c57e86d 4325 int i = 0;
97b99127
N		 4326 unsigned long flags;
4327
1c57e86d 4328 if (atomic_read(&acb->ccboutstandingcount) != 0) {
36b83ded
NC		 4329 /* disable all outbound interrupt */
4330 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d 4331 /* talk to iop 331 outstanding command aborted */
36b83ded 4332 rtnval = arcmsr_abort_allcmd(acb);
1c57e86d 4333 /* clear all outbound posted Q */
1a4f550a 4334 arcmsr_done4abort_postqueue(acb);
d076e4aa 4335 for (i = 0; i < acb->maxFreeCCB; i++) {
1c57e86d 4336 ccb = acb->pccb_pool[i];
a1f6e021 4337 if (ccb->startdone == ARCMSR_CCB_START) {
97b99127
N		 4338 scsi_dma_unmap(ccb->pcmd);
4339 ccb->startdone = ARCMSR_CCB_DONE;
4340 ccb->ccb_flags = 0;
4341 spin_lock_irqsave(&acb->ccblist_lock, flags);
4342 list_add_tail(&ccb->list, &acb->ccb_free_list);
4343 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 4344 }
4345 }
36b83ded 4346 atomic_set(&acb->ccboutstandingcount, 0);
1c57e86d
EC		 4347 /* enable all outbound interrupt */
4348 arcmsr_enable_outbound_ints(acb, intmask_org);
36b83ded 4349 return rtnval;
1c57e86d 4350 }
36b83ded 4351 return rtnval;
1c57e86d
EC		 4352}
4353
4354static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
4355{
97b99127 4356 struct AdapterControlBlock *acb;
ae52e7f0
NC		 4357 int retry_count = 0;
4358 int rtn = FAILED;
ae52e7f0 4359 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
c4c1adb3
CH		 4360 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
4361 return SUCCESS;
72a7f313
CH		 4362 pr_notice("arcmsr: executing bus reset eh.....num_resets = %d,"
4363 " num_aborts = %d \n", acb->num_resets, acb->num_aborts);
36b83ded 4364 acb->num_resets++;
36b83ded 4365
72a7f313
CH		 4366 if (acb->acb_flags & ACB_F_BUS_RESET) {
4367 long timeout;
852c3f32 4368 pr_notice("arcmsr: there is a bus reset eh proceeding...\n");
72a7f313
CH		 4369 timeout = wait_event_timeout(wait_q, (acb->acb_flags
4370 & ACB_F_BUS_RESET) == 0, 220 * HZ);
4371 if (timeout)
4372 return SUCCESS;
4373 }
4374 acb->acb_flags |= ACB_F_BUS_RESET;
4375 if (!arcmsr_iop_reset(acb)) {
4376 arcmsr_hardware_reset(acb);
4377 acb->acb_flags &= ~ACB_F_IOP_INITED;
4378wait_reset_done:
4379 ssleep(ARCMSR_SLEEPTIME);
4380 if (arcmsr_reset_in_progress(acb)) {
4381 if (retry_count > ARCMSR_RETRYCOUNT) {
4382 acb->fw_flag = FW_DEADLOCK;
4383 pr_notice("arcmsr%d: waiting for hw bus reset"
4384 " return, RETRY TERMINATED!!\n",
4385 acb->host->host_no);
4386 return FAILED;
cdd3cb15 4387 }
72a7f313
CH		 4388 retry_count++;
4389 goto wait_reset_done;
5b37479a 4390 }
72a7f313
CH		 4391 arcmsr_iop_init(acb);
4392 atomic_set(&acb->rq_map_token, 16);
4393 atomic_set(&acb->ante_token_value, 16);
4394 acb->fw_flag = FW_NORMAL;
4395 mod_timer(&acb->eternal_timer, jiffies +
4396 msecs_to_jiffies(6 * HZ));
4397 acb->acb_flags &= ~ACB_F_BUS_RESET;
4398 rtn = SUCCESS;
4399 pr_notice("arcmsr: scsi bus reset eh returns with success\n");
4400 } else {
4401 acb->acb_flags &= ~ACB_F_BUS_RESET;
4402 atomic_set(&acb->rq_map_token, 16);
4403 atomic_set(&acb->ante_token_value, 16);
4404 acb->fw_flag = FW_NORMAL;
4405 mod_timer(&acb->eternal_timer, jiffies +
4406 msecs_to_jiffies(6 * HZ));
4407 rtn = SUCCESS;
ae52e7f0
NC		 4408 }
4409 return rtn;
1c57e86d
EC		 4410}
4411
ae52e7f0 4412static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
1c57e86d
EC		 4413 struct CommandControlBlock *ccb)
4414{
ae52e7f0 4415 int rtn;
ae52e7f0 4416 rtn = arcmsr_polling_ccbdone(acb, ccb);
ae52e7f0 4417 return rtn;
1c57e86d
EC		 4418}
4419
4420static int arcmsr_abort(struct scsi_cmnd *cmd)
4421{
4422 struct AdapterControlBlock *acb =
4423 (struct AdapterControlBlock *)cmd->device->host->hostdata;
4424 int i = 0;
ae52e7f0 4425 int rtn = FAILED;
cab5aece
CH		 4426 uint32_t intmask_org;
4427
c4c1adb3
CH		 4428 if (acb->acb_flags & ACB_F_ADAPTER_REMOVED)
4429 return SUCCESS;
1c57e86d 4430 printk(KERN_NOTICE
cab5aece 4431 "arcmsr%d: abort device command of scsi id = %d lun = %d\n",
9cb78c16 4432 acb->host->host_no, cmd->device->id, (u32)cmd->device->lun);
ae52e7f0 4433 acb->acb_flags |= ACB_F_ABORT;
1c57e86d 4434 acb->num_aborts++;
1c57e86d
EC		 4435 /*
4436 ************************************************
4437 ** the all interrupt service routine is locked
4438 ** we need to handle it as soon as possible and exit
4439 ************************************************
4440 */
cab5aece
CH		 4441 if (!atomic_read(&acb->ccboutstandingcount)) {
4442 acb->acb_flags &= ~ACB_F_ABORT;
ae52e7f0 4443 return rtn;
cab5aece 4444 }
1c57e86d 4445
cab5aece 4446 intmask_org = arcmsr_disable_outbound_ints(acb);
d076e4aa 4447 for (i = 0; i < acb->maxFreeCCB; i++) {
1c57e86d
EC		 4448 struct CommandControlBlock *ccb = acb->pccb_pool[i];
4449 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
ae52e7f0
NC		 4450 ccb->startdone = ARCMSR_CCB_ABORTED;
4451 rtn = arcmsr_abort_one_cmd(acb, ccb);
1c57e86d
EC		 4452 break;
4453 }
4454 }
ae52e7f0 4455 acb->acb_flags &= ~ACB_F_ABORT;
cab5aece 4456 arcmsr_enable_outbound_ints(acb, intmask_org);
ae52e7f0 4457 return rtn;
1c57e86d
EC		 4458}
4459
4460static const char *arcmsr_info(struct Scsi_Host *host)
4461{
4462 struct AdapterControlBlock *acb =
4463 (struct AdapterControlBlock *) host->hostdata;
4464 static char buf[256];
4465 char *type;
4466 int raid6 = 1;
1c57e86d
EC		 4467 switch (acb->pdev->device) {
4468 case PCI_DEVICE_ID_ARECA_1110:
1a4f550a
NC		 4469 case PCI_DEVICE_ID_ARECA_1200:
4470 case PCI_DEVICE_ID_ARECA_1202:
1c57e86d
EC		 4471 case PCI_DEVICE_ID_ARECA_1210:
4472 raid6 = 0;
df561f66 4473 fallthrough;
1c57e86d
EC		 4474 case PCI_DEVICE_ID_ARECA_1120:
4475 case PCI_DEVICE_ID_ARECA_1130:
4476 case PCI_DEVICE_ID_ARECA_1160:
4477 case PCI_DEVICE_ID_ARECA_1170:
1a4f550a 4478 case PCI_DEVICE_ID_ARECA_1201:
7e315ffd 4479 case PCI_DEVICE_ID_ARECA_1203:
1c57e86d
EC		 4480 case PCI_DEVICE_ID_ARECA_1220:
4481 case PCI_DEVICE_ID_ARECA_1230:
4482 case PCI_DEVICE_ID_ARECA_1260:
4483 case PCI_DEVICE_ID_ARECA_1270:
4484 case PCI_DEVICE_ID_ARECA_1280:
4485 type = "SATA";
4486 break;
5b37479a 4487 case PCI_DEVICE_ID_ARECA_1214:
1c57e86d
EC		 4488 case PCI_DEVICE_ID_ARECA_1380:
4489 case PCI_DEVICE_ID_ARECA_1381:
4490 case PCI_DEVICE_ID_ARECA_1680:
4491 case PCI_DEVICE_ID_ARECA_1681:
cdd3cb15 4492 case PCI_DEVICE_ID_ARECA_1880:
23509024 4493 case PCI_DEVICE_ID_ARECA_1884:
aaa64f69 4494 type = "SAS/SATA";
1c57e86d
EC		 4495 break;
4496 default:
aaa64f69
CH		 4497 type = "unknown";
4498 raid6 = 0;
1c57e86d
EC		 4499 break;
4500 }
aaa64f69
CH		 4501 sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n",
4502 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
1c57e86d
EC		 4503 return buf;
4504}
Linux 6.x block layer and io_uring tree(s)