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qla2xxx: Restrict max_lun to 16-bit for older HBAs
[linux-2.6-block.git] / drivers / scsi / arcmsr / arcmsr_hba.c
CommitLineData
1c57e86d
EC		 1/*
2*******************************************************************************
3** O.S : Linux
4** FILE NAME : arcmsr_hba.c
97b99127 5** BY : Nick Cheng
1c57e86d
EC		 6** Description: SCSI RAID Device Driver for
7** ARECA RAID Host adapter
8*******************************************************************************
9** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved
10**
11** Web site: www.areca.com.tw
1a4f550a 12** E-mail: support@areca.com.tw
1c57e86d
EC		 13**
14** This program is free software; you can redistribute it and/or modify
15** it under the terms of the GNU General Public License version 2 as
16** published by the Free Software Foundation.
17** This program is distributed in the hope that it will be useful,
18** but WITHOUT ANY WARRANTY; without even the implied warranty of
19** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20** GNU General Public License for more details.
21*******************************************************************************
22** Redistribution and use in source and binary forms, with or without
23** modification, are permitted provided that the following conditions
24** are met:
25** 1. Redistributions of source code must retain the above copyright
26** notice, this list of conditions and the following disclaimer.
27** 2. Redistributions in binary form must reproduce the above copyright
28** notice, this list of conditions and the following disclaimer in the
29** documentation and/or other materials provided with the distribution.
30** 3. The name of the author may not be used to endorse or promote products
31** derived from this software without specific prior written permission.
32**
33** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
34** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
35** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
36** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
37** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
38** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
39** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
40** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
41** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
42** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
43*******************************************************************************
44** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
45** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
46*******************************************************************************
47*/
48#include <linux/module.h>
49#include <linux/reboot.h>
50#include <linux/spinlock.h>
51#include <linux/pci_ids.h>
52#include <linux/interrupt.h>
53#include <linux/moduleparam.h>
54#include <linux/errno.h>
55#include <linux/types.h>
56#include <linux/delay.h>
57#include <linux/dma-mapping.h>
58#include <linux/timer.h>
a7c8962b 59#include <linux/slab.h>
1c57e86d 60#include <linux/pci.h>
a1f6e021 61#include <linux/aer.h>
1c57e86d
EC		 62#include <asm/dma.h>
63#include <asm/io.h>
1c57e86d
EC		 64#include <asm/uaccess.h>
65#include <scsi/scsi_host.h>
66#include <scsi/scsi.h>
67#include <scsi/scsi_cmnd.h>
68#include <scsi/scsi_tcq.h>
69#include <scsi/scsi_device.h>
70#include <scsi/scsi_transport.h>
71#include <scsi/scsicam.h>
72#include "arcmsr.h"
ae52e7f0 73MODULE_AUTHOR("Nick Cheng <support@areca.com.tw>");
cdd3cb15 74MODULE_DESCRIPTION("ARECA (ARC11xx/12xx/16xx/1880) SATA/SAS RAID Host Bus Adapter");
1c57e86d
EC		 75MODULE_LICENSE("Dual BSD/GPL");
76MODULE_VERSION(ARCMSR_DRIVER_VERSION);
8b7eb86f
TH		 77
78#define ARCMSR_SLEEPTIME 10
79#define ARCMSR_RETRYCOUNT 12
80
ae52e7f0 81wait_queue_head_t wait_q;
1a4f550a
NC		 82static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
83 struct scsi_cmnd *cmd);
84static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
1c57e86d
EC		 85static int arcmsr_abort(struct scsi_cmnd *);
86static int arcmsr_bus_reset(struct scsi_cmnd *);
87static int arcmsr_bios_param(struct scsi_device *sdev,
1a4f550a 88 struct block_device *bdev, sector_t capacity, int *info);
f281233d 89static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1c57e86d
EC		 90static int arcmsr_probe(struct pci_dev *pdev,
91 const struct pci_device_id *id);
92static void arcmsr_remove(struct pci_dev *pdev);
93static void arcmsr_shutdown(struct pci_dev *pdev);
94static void arcmsr_iop_init(struct AdapterControlBlock *acb);
95static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
1a4f550a 96static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
1c57e86d 97static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
1a4f550a
NC		 98static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb);
99static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb);
36b83ded
NC		 100static void arcmsr_request_device_map(unsigned long pacb);
101static void arcmsr_request_hba_device_map(struct AdapterControlBlock *acb);
102static void arcmsr_request_hbb_device_map(struct AdapterControlBlock *acb);
cdd3cb15 103static void arcmsr_request_hbc_device_map(struct AdapterControlBlock *acb);
36b83ded 104static void arcmsr_message_isr_bh_fn(struct work_struct *work);
ae52e7f0 105static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
36b83ded 106static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
cdd3cb15
NC		 107static void arcmsr_hbc_message_isr(struct AdapterControlBlock *pACB);
108static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
1c57e86d
EC		 109static const char *arcmsr_info(struct Scsi_Host *);
110static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
1a4f550a 111static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev,
e881a172 112 int queue_depth, int reason)
1c57e86d 113{
e881a172
MC		 114 if (reason != SCSI_QDEPTH_DEFAULT)
115 return -EOPNOTSUPP;
116
1c57e86d
EC		 117 if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
118 queue_depth = ARCMSR_MAX_CMD_PERLUN;
119 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, queue_depth);
120 return queue_depth;
121}
122
123static struct scsi_host_template arcmsr_scsi_host_template = {
124 .module = THIS_MODULE,
cdd3cb15
NC		 125 .name = "ARCMSR ARECA SATA/SAS RAID Controller"
126 ARCMSR_DRIVER_VERSION,
1c57e86d
EC		 127 .info = arcmsr_info,
128 .queuecommand = arcmsr_queue_command,
cdd3cb15 129 .eh_abort_handler = arcmsr_abort,
1c57e86d
EC		 130 .eh_bus_reset_handler = arcmsr_bus_reset,
131 .bios_param = arcmsr_bios_param,
132 .change_queue_depth = arcmsr_adjust_disk_queue_depth,
ae52e7f0 133 .can_queue = ARCMSR_MAX_FREECCB_NUM,
cdd3cb15
NC		 134 .this_id = ARCMSR_SCSI_INITIATOR_ID,
135 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
136 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
1c57e86d
EC		 137 .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
138 .use_clustering = ENABLE_CLUSTERING,
139 .shost_attrs = arcmsr_host_attrs,
54b2b50c 140 .no_write_same = 1,
1c57e86d 141};
1c57e86d
EC		 142static struct pci_device_id arcmsr_device_id_table[] = {
143 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110)},
144 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120)},
145 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130)},
146 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160)},
147 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170)},
1a4f550a
NC		 148 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200)},
149 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201)},
150 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202)},
1c57e86d
EC		 151 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210)},
152 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220)},
153 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230)},
154 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260)},
155 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270)},
156 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280)},
157 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380)},
158 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381)},
159 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680)},
160 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681)},
ae52e7f0 161 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880)},
1c57e86d
EC		 162 {0, 0}, /* Terminating entry */
163};
164MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
165static struct pci_driver arcmsr_pci_driver = {
166 .name = "arcmsr",
cdd3cb15 167 .id_table = arcmsr_device_id_table,
1c57e86d
EC		 168 .probe = arcmsr_probe,
169 .remove = arcmsr_remove,
a1f6e021 170 .shutdown = arcmsr_shutdown,
1c57e86d 171};
cdd3cb15
NC		 172/*
173****************************************************************************
174****************************************************************************
175*/
1c57e86d 176
cdd3cb15 177static void arcmsr_free_hbb_mu(struct AdapterControlBlock *acb)
ae52e7f0
NC		 178{
179 switch (acb->adapter_type) {
180 case ACB_ADAPTER_TYPE_A:
cdd3cb15 181 case ACB_ADAPTER_TYPE_C:
ae52e7f0
NC		 182 break;
183 case ACB_ADAPTER_TYPE_B:{
cdd3cb15
NC		 184 dma_free_coherent(&acb->pdev->dev,
185 sizeof(struct MessageUnit_B),
186 acb->pmuB, acb->dma_coherent_handle_hbb_mu);
ae52e7f0
NC		 187 }
188 }
189}
190
191static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
192{
193 struct pci_dev *pdev = acb->pdev;
cdd3cb15 194 switch (acb->adapter_type){
ae52e7f0 195 case ACB_ADAPTER_TYPE_A:{
cdd3cb15 196 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
ae52e7f0
NC		 197 if (!acb->pmuA) {
198 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
199 return false;
200 }
201 break;
202 }
203 case ACB_ADAPTER_TYPE_B:{
204 void __iomem *mem_base0, *mem_base1;
205 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
206 if (!mem_base0) {
207 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
208 return false;
209 }
210 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
211 if (!mem_base1) {
212 iounmap(mem_base0);
213 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
214 return false;
215 }
216 acb->mem_base0 = mem_base0;
217 acb->mem_base1 = mem_base1;
cdd3cb15
NC		 218 break;
219 }
220 case ACB_ADAPTER_TYPE_C:{
221 acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
222 if (!acb->pmuC) {
223 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
224 return false;
225 }
226 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
227 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
228 return true;
229 }
230 break;
ae52e7f0
NC		 231 }
232 }
233 return true;
234}
235
236static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
237{
238 switch (acb->adapter_type) {
cdd3cb15
NC		 239 case ACB_ADAPTER_TYPE_A:{
240 iounmap(acb->pmuA);
241 }
242 break;
243 case ACB_ADAPTER_TYPE_B:{
244 iounmap(acb->mem_base0);
245 iounmap(acb->mem_base1);
246 }
247
248 break;
249 case ACB_ADAPTER_TYPE_C:{
250 iounmap(acb->pmuC);
251 }
ae52e7f0
NC		 252 }
253}
254
7d12e780 255static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
1c57e86d
EC		 256{
257 irqreturn_t handle_state;
1a4f550a 258 struct AdapterControlBlock *acb = dev_id;
1c57e86d 259
1c57e86d 260 handle_state = arcmsr_interrupt(acb);
1c57e86d
EC		 261 return handle_state;
262}
263
264static int arcmsr_bios_param(struct scsi_device *sdev,
265 struct block_device *bdev, sector_t capacity, int *geom)
266{
267 int ret, heads, sectors, cylinders, total_capacity;
268 unsigned char *buffer;/* return copy of block device's partition table */
269
270 buffer = scsi_bios_ptable(bdev);
271 if (buffer) {
272 ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
273 kfree(buffer);
274 if (ret != -1)
275 return ret;
276 }
277 total_capacity = capacity;
278 heads = 64;
279 sectors = 32;
280 cylinders = total_capacity / (heads * sectors);
281 if (cylinders > 1024) {
282 heads = 255;
283 sectors = 63;
284 cylinders = total_capacity / (heads * sectors);
285 }
286 geom[0] = heads;
287 geom[1] = sectors;
288 geom[2] = cylinders;
289 return 0;
290}
291
1a4f550a 292static void arcmsr_define_adapter_type(struct AdapterControlBlock *acb)
1c57e86d
EC		 293{
294 struct pci_dev *pdev = acb->pdev;
1a4f550a
NC		 295 u16 dev_id;
296 pci_read_config_word(pdev, PCI_DEVICE_ID, &dev_id);
ae52e7f0 297 acb->dev_id = dev_id;
1a4f550a 298 switch (dev_id) {
cdd3cb15
NC		 299 case 0x1880: {
300 acb->adapter_type = ACB_ADAPTER_TYPE_C;
301 }
302 break;
303 case 0x1201: {
1a4f550a
NC		 304 acb->adapter_type = ACB_ADAPTER_TYPE_B;
305 }
306 break;
307
cdd3cb15 308 default: acb->adapter_type = ACB_ADAPTER_TYPE_A;
1a4f550a 309 }
8b7eb86f 310}
1a4f550a 311
ae52e7f0
NC		 312static uint8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
313{
314 struct MessageUnit_A __iomem *reg = acb->pmuA;
8b7eb86f
TH		 315 int i;
316
317 for (i = 0; i < 2000; i++) {
318 if (readl(&reg->outbound_intstatus) &
319 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
320 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
321 &reg->outbound_intstatus);
322 return true;
323 }
324 msleep(10);
325 } /* max 20 seconds */
ae52e7f0 326
cdd3cb15 327 return false;
ae52e7f0
NC		 328}
329
330static uint8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
1a4f550a 331{
ae52e7f0 332 struct MessageUnit_B *reg = acb->pmuB;
8b7eb86f
TH		 333 int i;
334
335 for (i = 0; i < 2000; i++) {
336 if (readl(reg->iop2drv_doorbell)
337 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
338 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
339 reg->iop2drv_doorbell);
340 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
341 reg->drv2iop_doorbell);
342 return true;
343 }
344 msleep(10);
345 } /* max 20 seconds */
ae52e7f0 346
cdd3cb15 347 return false;
ae52e7f0
NC		 348}
349
cdd3cb15
NC		 350static uint8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *pACB)
351{
352 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
8b7eb86f
TH		 353 int i;
354
355 for (i = 0; i < 2000; i++) {
356 if (readl(&phbcmu->outbound_doorbell)
357 & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
358 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
359 &phbcmu->outbound_doorbell_clear); /*clear interrupt*/
360 return true;
361 }
362 msleep(10);
363 } /* max 20 seconds */
364
cdd3cb15
NC		 365 return false;
366}
8b7eb86f 367
ae52e7f0
NC		 368static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
369{
370 struct MessageUnit_A __iomem *reg = acb->pmuA;
371 int retry_count = 30;
ae52e7f0
NC		 372 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
373 do {
cdd3cb15 374 if (arcmsr_hba_wait_msgint_ready(acb))
ae52e7f0
NC		 375 break;
376 else {
377 retry_count--;
378 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
379 timeout, retry count down = %d \n", acb->host->host_no, retry_count);
380 }
381 } while (retry_count != 0);
382}
383
384static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
385{
386 struct MessageUnit_B *reg = acb->pmuB;
387 int retry_count = 30;
ae52e7f0
NC		 388 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
389 do {
cdd3cb15 390 if (arcmsr_hbb_wait_msgint_ready(acb))
ae52e7f0
NC		 391 break;
392 else {
393 retry_count--;
394 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
395 timeout,retry count down = %d \n", acb->host->host_no, retry_count);
396 }
397 } while (retry_count != 0);
398}
399
cdd3cb15
NC		 400static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *pACB)
401{
402 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
403 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
404 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
405 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
406 do {
407 if (arcmsr_hbc_wait_msgint_ready(pACB)) {
408 break;
409 } else {
410 retry_count--;
411 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
412 timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
413 }
414 } while (retry_count != 0);
415 return;
416}
ae52e7f0
NC		 417static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
418{
1a4f550a 419 switch (acb->adapter_type) {
1c57e86d 420
1a4f550a 421 case ACB_ADAPTER_TYPE_A: {
ae52e7f0
NC		 422 arcmsr_flush_hba_cache(acb);
423 }
424 break;
1a4f550a 425
ae52e7f0
NC		 426 case ACB_ADAPTER_TYPE_B: {
427 arcmsr_flush_hbb_cache(acb);
1a4f550a 428 }
cdd3cb15
NC		 429 break;
430 case ACB_ADAPTER_TYPE_C: {
431 arcmsr_flush_hbc_cache(acb);
432 }
ae52e7f0
NC		 433 }
434}
1a4f550a 435
ae52e7f0
NC		 436static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
437{
cdd3cb15
NC		 438 struct pci_dev *pdev = acb->pdev;
439 void *dma_coherent;
440 dma_addr_t dma_coherent_handle;
441 struct CommandControlBlock *ccb_tmp;
442 int i = 0, j = 0;
443 dma_addr_t cdb_phyaddr;
87f76152 444 unsigned long roundup_ccbsize;
cdd3cb15
NC		 445 unsigned long max_xfer_len;
446 unsigned long max_sg_entrys;
447 uint32_t firm_config_version;
87f76152 448
cdd3cb15
NC		 449 for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
450 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
451 acb->devstate[i][j] = ARECA_RAID_GONE;
452
453 max_xfer_len = ARCMSR_MAX_XFER_LEN;
454 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
455 firm_config_version = acb->firm_cfg_version;
456 if((firm_config_version & 0xFF) >= 3){
457 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
87f76152 458 max_sg_entrys = (max_xfer_len/4096);
cdd3cb15
NC		 459 }
460 acb->host->max_sectors = max_xfer_len/512;
461 acb->host->sg_tablesize = max_sg_entrys;
462 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
87f76152 463 acb->uncache_size = roundup_ccbsize * ARCMSR_MAX_FREECCB_NUM;
cdd3cb15
NC		 464 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
465 if(!dma_coherent){
87f76152 466 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
cdd3cb15
NC		 467 return -ENOMEM;
468 }
469 acb->dma_coherent = dma_coherent;
470 acb->dma_coherent_handle = dma_coherent_handle;
471 memset(dma_coherent, 0, acb->uncache_size);
cdd3cb15
NC		 472 ccb_tmp = dma_coherent;
473 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
474 for(i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++){
475 cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
476 ccb_tmp->cdb_phyaddr_pattern = ((acb->adapter_type == ACB_ADAPTER_TYPE_C) ? cdb_phyaddr : (cdb_phyaddr >> 5));
477 acb->pccb_pool[i] = ccb_tmp;
478 ccb_tmp->acb = acb;
479 INIT_LIST_HEAD(&ccb_tmp->list);
480 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
481 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
482 dma_coherent_handle = dma_coherent_handle + roundup_ccbsize;
1a4f550a 483 }
1c57e86d
EC		 484 return 0;
485}
36b83ded 486
cdd3cb15
NC		 487static void arcmsr_message_isr_bh_fn(struct work_struct *work)
488{
489 struct AdapterControlBlock *acb = container_of(work,struct AdapterControlBlock, arcmsr_do_message_isr_bh);
36b83ded
NC		 490 switch (acb->adapter_type) {
491 case ACB_ADAPTER_TYPE_A: {
492
493 struct MessageUnit_A __iomem *reg = acb->pmuA;
494 char *acb_dev_map = (char *)acb->device_map;
cdd3cb15
NC		 495 uint32_t __iomem *signature = (uint32_t __iomem*) (&reg->message_rwbuffer[0]);
496 char __iomem *devicemap = (char __iomem*) (&reg->message_rwbuffer[21]);
36b83ded
NC		 497 int target, lun;
498 struct scsi_device *psdev;
499 char diff;
500
501 atomic_inc(&acb->rq_map_token);
502 if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
cdd3cb15 503 for(target = 0; target < ARCMSR_MAX_TARGETID -1; target++) {
36b83ded
NC		 504 diff = (*acb_dev_map)^readb(devicemap);
505 if (diff != 0) {
506 char temp;
507 *acb_dev_map = readb(devicemap);
cdd3cb15
NC		 508 temp =*acb_dev_map;
509 for(lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
510 if((temp & 0x01)==1 && (diff & 0x01) == 1) {
36b83ded 511 scsi_add_device(acb->host, 0, target, lun);
cdd3cb15 512 }else if((temp & 0x01) == 0 && (diff & 0x01) == 1) {
36b83ded 513 psdev = scsi_device_lookup(acb->host, 0, target, lun);
cdd3cb15 514 if (psdev != NULL ) {
36b83ded
NC		 515 scsi_remove_device(psdev);
516 scsi_device_put(psdev);
517 }
518 }
519 temp >>= 1;
520 diff >>= 1;
521 }
522 }
523 devicemap++;
524 acb_dev_map++;
525 }
526 }
527 break;
528 }
529
530 case ACB_ADAPTER_TYPE_B: {
531 struct MessageUnit_B *reg = acb->pmuB;
532 char *acb_dev_map = (char *)acb->device_map;
cdd3cb15
NC		 533 uint32_t __iomem *signature = (uint32_t __iomem*)(&reg->message_rwbuffer[0]);
534 char __iomem *devicemap = (char __iomem*)(&reg->message_rwbuffer[21]);
535 int target, lun;
536 struct scsi_device *psdev;
537 char diff;
538
539 atomic_inc(&acb->rq_map_token);
540 if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
541 for(target = 0; target < ARCMSR_MAX_TARGETID -1; target++) {
542 diff = (*acb_dev_map)^readb(devicemap);
543 if (diff != 0) {
544 char temp;
545 *acb_dev_map = readb(devicemap);
546 temp =*acb_dev_map;
547 for(lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
548 if((temp & 0x01)==1 && (diff & 0x01) == 1) {
549 scsi_add_device(acb->host, 0, target, lun);
550 }else if((temp & 0x01) == 0 && (diff & 0x01) == 1) {
551 psdev = scsi_device_lookup(acb->host, 0, target, lun);
552 if (psdev != NULL ) {
553 scsi_remove_device(psdev);
554 scsi_device_put(psdev);
555 }
556 }
557 temp >>= 1;
558 diff >>= 1;
559 }
560 }
561 devicemap++;
562 acb_dev_map++;
563 }
564 }
565 }
566 break;
567 case ACB_ADAPTER_TYPE_C: {
568 struct MessageUnit_C *reg = acb->pmuC;
569 char *acb_dev_map = (char *)acb->device_map;
570 uint32_t __iomem *signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
571 char __iomem *devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
36b83ded
NC		 572 int target, lun;
573 struct scsi_device *psdev;
574 char diff;
575
576 atomic_inc(&acb->rq_map_token);
577 if (readl(signature) == ARCMSR_SIGNATURE_GET_CONFIG) {
578 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) {
579 diff = (*acb_dev_map)^readb(devicemap);
580 if (diff != 0) {
581 char temp;
582 *acb_dev_map = readb(devicemap);
583 temp = *acb_dev_map;
584 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN; lun++) {
585 if ((temp & 0x01) == 1 && (diff & 0x01) == 1) {
586 scsi_add_device(acb->host, 0, target, lun);
587 } else if ((temp & 0x01) == 0 && (diff & 0x01) == 1) {
588 psdev = scsi_device_lookup(acb->host, 0, target, lun);
589 if (psdev != NULL) {
590 scsi_remove_device(psdev);
591 scsi_device_put(psdev);
592 }
593 }
594 temp >>= 1;
595 diff >>= 1;
596 }
597 }
598 devicemap++;
599 acb_dev_map++;
600 }
601 }
602 }
603 }
604}
1c57e86d 605
ae52e7f0 606static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1c57e86d
EC		 607{
608 struct Scsi_Host *host;
609 struct AdapterControlBlock *acb;
cdd3cb15 610 uint8_t bus,dev_fun;
1c57e86d 611 int error;
1c57e86d 612 error = pci_enable_device(pdev);
cdd3cb15 613 if(error){
ae52e7f0
NC		 614 return -ENODEV;
615 }
616 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
cdd3cb15
NC		 617 if(!host){
618 goto pci_disable_dev;
1c57e86d 619 }
6a35528a 620 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
cdd3cb15 621 if(error){
284901a9 622 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cdd3cb15 623 if(error){
1c57e86d
EC		 624 printk(KERN_WARNING
625 "scsi%d: No suitable DMA mask available\n",
626 host->host_no);
ae52e7f0 627 goto scsi_host_release;
1c57e86d
EC		 628 }
629 }
ae52e7f0 630 init_waitqueue_head(&wait_q);
1c57e86d
EC		 631 bus = pdev->bus->number;
632 dev_fun = pdev->devfn;
ae52e7f0 633 acb = (struct AdapterControlBlock *) host->hostdata;
cdd3cb15 634 memset(acb,0,sizeof(struct AdapterControlBlock));
1c57e86d 635 acb->pdev = pdev;
ae52e7f0 636 acb->host = host;
1c57e86d 637 host->max_lun = ARCMSR_MAX_TARGETLUN;
cdd3cb15
NC		 638 host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
639 host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
640 host->can_queue = ARCMSR_MAX_FREECCB_NUM; /* max simultaneous cmds */
641 host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
1c57e86d
EC		 642 host->this_id = ARCMSR_SCSI_INITIATOR_ID;
643 host->unique_id = (bus << 8) | dev_fun;
ae52e7f0
NC		 644 pci_set_drvdata(pdev, host);
645 pci_set_master(pdev);
1c57e86d 646 error = pci_request_regions(pdev, "arcmsr");
cdd3cb15 647 if(error){
ae52e7f0 648 goto scsi_host_release;
1c57e86d 649 }
ae52e7f0
NC		 650 spin_lock_init(&acb->eh_lock);
651 spin_lock_init(&acb->ccblist_lock);
1c57e86d 652 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
cdd3cb15
NC		 653 ACB_F_MESSAGE_RQBUFFER_CLEARED |
654 ACB_F_MESSAGE_WQBUFFER_READED);
1c57e86d
EC		 655 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
656 INIT_LIST_HEAD(&acb->ccb_free_list);
ae52e7f0
NC		 657 arcmsr_define_adapter_type(acb);
658 error = arcmsr_remap_pciregion(acb);
cdd3cb15 659 if(!error){
ae52e7f0
NC		 660 goto pci_release_regs;
661 }
662 error = arcmsr_get_firmware_spec(acb);
cdd3cb15 663 if(!error){
ae52e7f0
NC		 664 goto unmap_pci_region;
665 }
1c57e86d 666 error = arcmsr_alloc_ccb_pool(acb);
cdd3cb15 667 if(error){
ae52e7f0
NC		 668 goto free_hbb_mu;
669 }
36b83ded 670 arcmsr_iop_init(acb);
1c57e86d 671 error = scsi_add_host(host, &pdev->dev);
cdd3cb15 672 if(error){
ae52e7f0
NC		 673 goto RAID_controller_stop;
674 }
675 error = request_irq(pdev->irq, arcmsr_do_interrupt, IRQF_SHARED, "arcmsr", acb);
cdd3cb15 676 if(error){
ae52e7f0
NC		 677 goto scsi_host_remove;
678 }
679 host->irq = pdev->irq;
cdd3cb15 680 scsi_scan_host(host);
ae52e7f0 681 INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
36b83ded 682 atomic_set(&acb->rq_map_token, 16);
ae52e7f0
NC		 683 atomic_set(&acb->ante_token_value, 16);
684 acb->fw_flag = FW_NORMAL;
36b83ded 685 init_timer(&acb->eternal_timer);
ae52e7f0 686 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
36b83ded
NC		 687 acb->eternal_timer.data = (unsigned long) acb;
688 acb->eternal_timer.function = &arcmsr_request_device_map;
689 add_timer(&acb->eternal_timer);
cdd3cb15 690 if(arcmsr_alloc_sysfs_attr(acb))
ae52e7f0 691 goto out_free_sysfs;
1c57e86d 692 return 0;
cdd3cb15 693out_free_sysfs:
ae52e7f0
NC		 694scsi_host_remove:
695 scsi_remove_host(host);
696RAID_controller_stop:
697 arcmsr_stop_adapter_bgrb(acb);
698 arcmsr_flush_adapter_cache(acb);
1c57e86d 699 arcmsr_free_ccb_pool(acb);
ae52e7f0 700free_hbb_mu:
cdd3cb15 701 arcmsr_free_hbb_mu(acb);
ae52e7f0
NC		 702unmap_pci_region:
703 arcmsr_unmap_pciregion(acb);
704pci_release_regs:
1c57e86d 705 pci_release_regions(pdev);
ae52e7f0 706scsi_host_release:
1c57e86d 707 scsi_host_put(host);
ae52e7f0 708pci_disable_dev:
1c57e86d 709 pci_disable_device(pdev);
ae52e7f0 710 return -ENODEV;
1a4f550a
NC		 711}
712
36b83ded 713static uint8_t arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
1c57e86d 714{
80da1adb 715 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 716 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
cdd3cb15 717 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 718 printk(KERN_NOTICE
719 "arcmsr%d: wait 'abort all outstanding command' timeout \n"
720 , acb->host->host_no);
cdd3cb15 721 return false;
36b83ded 722 }
cdd3cb15 723 return true;
1a4f550a
NC		 724}
725
36b83ded 726static uint8_t arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
1a4f550a 727{
80da1adb 728 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 729
ae52e7f0 730 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
cdd3cb15 731 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1c57e86d
EC		 732 printk(KERN_NOTICE
733 "arcmsr%d: wait 'abort all outstanding command' timeout \n"
734 , acb->host->host_no);
cdd3cb15 735 return false;
36b83ded 736 }
cdd3cb15
NC		 737 return true;
738}
739static uint8_t arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *pACB)
740{
741 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
742 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
743 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
744 if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
745 printk(KERN_NOTICE
746 "arcmsr%d: wait 'abort all outstanding command' timeout \n"
747 , pACB->host->host_no);
748 return false;
749 }
750 return true;
1c57e86d 751}
36b83ded 752static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
1a4f550a 753{
36b83ded 754 uint8_t rtnval = 0;
1a4f550a
NC		 755 switch (acb->adapter_type) {
756 case ACB_ADAPTER_TYPE_A: {
36b83ded 757 rtnval = arcmsr_abort_hba_allcmd(acb);
1a4f550a
NC		 758 }
759 break;
760
761 case ACB_ADAPTER_TYPE_B: {
36b83ded 762 rtnval = arcmsr_abort_hbb_allcmd(acb);
1a4f550a 763 }
cdd3cb15
NC		 764 break;
765
766 case ACB_ADAPTER_TYPE_C: {
767 rtnval = arcmsr_abort_hbc_allcmd(acb);
768 }
1a4f550a 769 }
36b83ded 770 return rtnval;
1a4f550a
NC		 771}
772
ae52e7f0
NC		 773static bool arcmsr_hbb_enable_driver_mode(struct AdapterControlBlock *pacb)
774{
775 struct MessageUnit_B *reg = pacb->pmuB;
ae52e7f0 776 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
cdd3cb15 777 if (!arcmsr_hbb_wait_msgint_ready(pacb)) {
ae52e7f0
NC		 778 printk(KERN_ERR "arcmsr%d: can't set driver mode. \n", pacb->host->host_no);
779 return false;
cdd3cb15
NC		 780 }
781 return true;
ae52e7f0
NC		 782}
783
1c57e86d
EC		 784static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
785{
1c57e86d
EC		 786 struct scsi_cmnd *pcmd = ccb->pcmd;
787
deff2627 788 scsi_dma_unmap(pcmd);
cdd3cb15 789}
1c57e86d 790
ae52e7f0 791static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
1c57e86d
EC		 792{
793 struct AdapterControlBlock *acb = ccb->acb;
794 struct scsi_cmnd *pcmd = ccb->pcmd;
ae52e7f0 795 unsigned long flags;
ae52e7f0 796 atomic_dec(&acb->ccboutstandingcount);
1c57e86d 797 arcmsr_pci_unmap_dma(ccb);
1c57e86d 798 ccb->startdone = ARCMSR_CCB_DONE;
ae52e7f0 799 spin_lock_irqsave(&acb->ccblist_lock, flags);
1c57e86d 800 list_add_tail(&ccb->list, &acb->ccb_free_list);
ae52e7f0 801 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 802 pcmd->scsi_done(pcmd);
803}
804
1a4f550a
NC		 805static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
806{
807
808 struct scsi_cmnd *pcmd = ccb->pcmd;
809 struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
1a4f550a
NC		 810 pcmd->result = DID_OK << 16;
811 if (sensebuffer) {
812 int sense_data_length =
b80ca4f7
FT		 813 sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
814 ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
815 memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
1a4f550a
NC		 816 memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
817 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
818 sensebuffer->Valid = 1;
819 }
820}
821
822static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
823{
824 u32 orig_mask = 0;
cdd3cb15 825 switch (acb->adapter_type) {
1a4f550a 826 case ACB_ADAPTER_TYPE_A : {
80da1adb 827 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 828 orig_mask = readl(&reg->outbound_intmask);
1a4f550a
NC		 829 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
830 &reg->outbound_intmask);
831 }
832 break;
1a4f550a 833 case ACB_ADAPTER_TYPE_B : {
80da1adb 834 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0
NC		 835 orig_mask = readl(reg->iop2drv_doorbell_mask);
836 writel(0, reg->iop2drv_doorbell_mask);
1a4f550a
NC		 837 }
838 break;
cdd3cb15
NC		 839 case ACB_ADAPTER_TYPE_C:{
840 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
841 /* disable all outbound interrupt */
842 orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
843 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
844 }
845 break;
1a4f550a
NC		 846 }
847 return orig_mask;
848}
849
cdd3cb15
NC		 850static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
851 struct CommandControlBlock *ccb, bool error)
1a4f550a 852{
1a4f550a
NC		 853 uint8_t id, lun;
854 id = ccb->pcmd->device->id;
855 lun = ccb->pcmd->device->lun;
cdd3cb15 856 if (!error) {
1a4f550a
NC		 857 if (acb->devstate[id][lun] == ARECA_RAID_GONE)
858 acb->devstate[id][lun] = ARECA_RAID_GOOD;
7968f194
JL		 859 ccb->pcmd->result = DID_OK << 16;
860 arcmsr_ccb_complete(ccb);
cdd3cb15 861 }else{
1a4f550a
NC		 862 switch (ccb->arcmsr_cdb.DeviceStatus) {
863 case ARCMSR_DEV_SELECT_TIMEOUT: {
864 acb->devstate[id][lun] = ARECA_RAID_GONE;
865 ccb->pcmd->result = DID_NO_CONNECT << 16;
ae52e7f0 866 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 867 }
868 break;
869
870 case ARCMSR_DEV_ABORTED:
871
872 case ARCMSR_DEV_INIT_FAIL: {
873 acb->devstate[id][lun] = ARECA_RAID_GONE;
874 ccb->pcmd->result = DID_BAD_TARGET << 16;
ae52e7f0 875 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 876 }
877 break;
878
879 case ARCMSR_DEV_CHECK_CONDITION: {
880 acb->devstate[id][lun] = ARECA_RAID_GOOD;
881 arcmsr_report_sense_info(ccb);
ae52e7f0 882 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 883 }
884 break;
885
886 default:
cdd3cb15
NC		 887 printk(KERN_NOTICE
888 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
889 but got unknown DeviceStatus = 0x%x \n"
890 , acb->host->host_no
891 , id
892 , lun
893 , ccb->arcmsr_cdb.DeviceStatus);
894 acb->devstate[id][lun] = ARECA_RAID_GONE;
895 ccb->pcmd->result = DID_NO_CONNECT << 16;
896 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 897 break;
898 }
899 }
900}
901
cdd3cb15 902static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
1a4f550a 903{
ae52e7f0 904 int id, lun;
cdd3cb15
NC		 905 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
906 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
907 struct scsi_cmnd *abortcmd = pCCB->pcmd;
1a4f550a 908 if (abortcmd) {
ae52e7f0 909 id = abortcmd->device->id;
cdd3cb15 910 lun = abortcmd->device->lun;
1a4f550a 911 abortcmd->result |= DID_ABORT << 16;
cdd3cb15
NC		 912 arcmsr_ccb_complete(pCCB);
913 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
914 acb->host->host_no, pCCB);
1a4f550a 915 }
cdd3cb15 916 return;
1a4f550a
NC		 917 }
918 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
919 done acb = '0x%p'"
920 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
921 " ccboutstandingcount = %d \n"
922 , acb->host->host_no
923 , acb
cdd3cb15
NC		 924 , pCCB
925 , pCCB->acb
926 , pCCB->startdone
1a4f550a 927 , atomic_read(&acb->ccboutstandingcount));
cdd3cb15 928 return;
97b99127 929 }
cdd3cb15 930 arcmsr_report_ccb_state(acb, pCCB, error);
1a4f550a
NC		 931}
932
933static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
934{
935 int i = 0;
936 uint32_t flag_ccb;
cdd3cb15
NC		 937 struct ARCMSR_CDB *pARCMSR_CDB;
938 bool error;
939 struct CommandControlBlock *pCCB;
1a4f550a
NC		 940 switch (acb->adapter_type) {
941
942 case ACB_ADAPTER_TYPE_A: {
80da1adb 943 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 944 uint32_t outbound_intstatus;
80da1adb 945 outbound_intstatus = readl(&reg->outbound_intstatus) &
1a4f550a
NC		 946 acb->outbound_int_enable;
947 /*clear and abort all outbound posted Q*/
948 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
cdd3cb15 949 while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
1a4f550a 950 && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
cdd3cb15
NC		 951 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
952 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
953 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
954 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 955 }
956 }
957 break;
958
959 case ACB_ADAPTER_TYPE_B: {
80da1adb 960 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 961 /*clear all outbound posted Q*/
97b99127 962 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */
1a4f550a
NC		 963 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
964 if ((flag_ccb = readl(&reg->done_qbuffer[i])) != 0) {
965 writel(0, &reg->done_qbuffer[i]);
cdd3cb15
NC		 966 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
967 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
968 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
969 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a 970 }
cdd3cb15 971 reg->post_qbuffer[i] = 0;
1a4f550a
NC		 972 }
973 reg->doneq_index = 0;
974 reg->postq_index = 0;
975 }
976 break;
cdd3cb15
NC		 977 case ACB_ADAPTER_TYPE_C: {
978 struct MessageUnit_C *reg = acb->pmuC;
979 struct ARCMSR_CDB *pARCMSR_CDB;
980 uint32_t flag_ccb, ccb_cdb_phy;
981 bool error;
982 struct CommandControlBlock *pCCB;
983 while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
984 /*need to do*/
985 flag_ccb = readl(&reg->outbound_queueport_low);
986 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
987 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);/*frame must be 32 bytes aligned*/
988 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
989 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
990 arcmsr_drain_donequeue(acb, pCCB, error);
991 }
992 }
1a4f550a
NC		 993 }
994}
1c57e86d
EC		 995static void arcmsr_remove(struct pci_dev *pdev)
996{
997 struct Scsi_Host *host = pci_get_drvdata(pdev);
998 struct AdapterControlBlock *acb =
999 (struct AdapterControlBlock *) host->hostdata;
1c57e86d 1000 int poll_count = 0;
1c57e86d
EC		 1001 arcmsr_free_sysfs_attr(acb);
1002 scsi_remove_host(host);
43829731 1003 flush_work(&acb->arcmsr_do_message_isr_bh);
36b83ded
NC		 1004 del_timer_sync(&acb->eternal_timer);
1005 arcmsr_disable_outbound_ints(acb);
1c57e86d 1006 arcmsr_stop_adapter_bgrb(acb);
cdd3cb15 1007 arcmsr_flush_adapter_cache(acb);
1c57e86d
EC		 1008 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
1009 acb->acb_flags &= ~ACB_F_IOP_INITED;
1010
cdd3cb15 1011 for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++){
1c57e86d
EC		 1012 if (!atomic_read(&acb->ccboutstandingcount))
1013 break;
1a4f550a 1014 arcmsr_interrupt(acb);/* FIXME: need spinlock */
1c57e86d
EC		 1015 msleep(25);
1016 }
1017
1018 if (atomic_read(&acb->ccboutstandingcount)) {
1019 int i;
1020
1021 arcmsr_abort_allcmd(acb);
1a4f550a 1022 arcmsr_done4abort_postqueue(acb);
1c57e86d
EC		 1023 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
1024 struct CommandControlBlock *ccb = acb->pccb_pool[i];
1025 if (ccb->startdone == ARCMSR_CCB_START) {
1026 ccb->startdone = ARCMSR_CCB_ABORTED;
1027 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 1028 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 1029 }
1030 }
1031 }
1c57e86d 1032 free_irq(pdev->irq, acb);
1c57e86d 1033 arcmsr_free_ccb_pool(acb);
cdd3cb15
NC		 1034 arcmsr_free_hbb_mu(acb);
1035 arcmsr_unmap_pciregion(acb);
1c57e86d 1036 pci_release_regions(pdev);
cdd3cb15 1037 scsi_host_put(host);
1c57e86d 1038 pci_disable_device(pdev);
1c57e86d
EC		 1039}
1040
1041static void arcmsr_shutdown(struct pci_dev *pdev)
1042{
1043 struct Scsi_Host *host = pci_get_drvdata(pdev);
1044 struct AdapterControlBlock *acb =
1045 (struct AdapterControlBlock *)host->hostdata;
36b83ded
NC		 1046 del_timer_sync(&acb->eternal_timer);
1047 arcmsr_disable_outbound_ints(acb);
43829731 1048 flush_work(&acb->arcmsr_do_message_isr_bh);
1c57e86d
EC		 1049 arcmsr_stop_adapter_bgrb(acb);
1050 arcmsr_flush_adapter_cache(acb);
1051}
1052
1053static int arcmsr_module_init(void)
1054{
1055 int error = 0;
1c57e86d
EC		 1056 error = pci_register_driver(&arcmsr_pci_driver);
1057 return error;
1058}
1059
1060static void arcmsr_module_exit(void)
1061{
1062 pci_unregister_driver(&arcmsr_pci_driver);
1063}
1064module_init(arcmsr_module_init);
1065module_exit(arcmsr_module_exit);
1066
36b83ded 1067static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
1a4f550a 1068 u32 intmask_org)
1c57e86d 1069{
1c57e86d 1070 u32 mask;
1a4f550a 1071 switch (acb->adapter_type) {
1c57e86d 1072
cdd3cb15 1073 case ACB_ADAPTER_TYPE_A: {
80da1adb 1074 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 1075 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
36b83ded
NC		 1076 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
1077 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
1a4f550a
NC		 1078 writel(mask, &reg->outbound_intmask);
1079 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
1080 }
1081 break;
1c57e86d 1082
cdd3cb15 1083 case ACB_ADAPTER_TYPE_B: {
80da1adb 1084 struct MessageUnit_B *reg = acb->pmuB;
36b83ded
NC		 1085 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
1086 ARCMSR_IOP2DRV_DATA_READ_OK |
1087 ARCMSR_IOP2DRV_CDB_DONE |
1088 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
ae52e7f0 1089 writel(mask, reg->iop2drv_doorbell_mask);
1a4f550a
NC		 1090 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
1091 }
cdd3cb15
NC		 1092 break;
1093 case ACB_ADAPTER_TYPE_C: {
1094 struct MessageUnit_C *reg = acb->pmuC;
1095 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
1096 writel(intmask_org & mask, &reg->host_int_mask);
1097 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
1098 }
1c57e86d
EC		 1099 }
1100}
1101
76d78300 1102static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
1a4f550a 1103 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
1c57e86d 1104{
1a4f550a
NC		 1105 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1106 int8_t *psge = (int8_t *)&arcmsr_cdb->u;
80da1adb 1107 __le32 address_lo, address_hi;
1a4f550a 1108 int arccdbsize = 0x30;
ae52e7f0 1109 __le32 length = 0;
cdd3cb15 1110 int i;
ae52e7f0 1111 struct scatterlist *sg;
1a4f550a 1112 int nseg;
1c57e86d 1113 ccb->pcmd = pcmd;
1a4f550a 1114 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1c57e86d
EC		 1115 arcmsr_cdb->TargetID = pcmd->device->id;
1116 arcmsr_cdb->LUN = pcmd->device->lun;
1117 arcmsr_cdb->Function = 1;
ae52e7f0 1118 arcmsr_cdb->Context = 0;
1c57e86d 1119 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
deff2627
FT		 1120
1121 nseg = scsi_dma_map(pcmd);
cdd3cb15 1122 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
76d78300 1123 return FAILED;
cdd3cb15
NC		 1124 scsi_for_each_sg(pcmd, sg, nseg, i) {
1125 /* Get the physical address of the current data pointer */
1126 length = cpu_to_le32(sg_dma_len(sg));
1127 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
1128 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
1129 if (address_hi == 0) {
1130 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1131
1132 pdma_sg->address = address_lo;
1133 pdma_sg->length = length;
1134 psge += sizeof (struct SG32ENTRY);
1135 arccdbsize += sizeof (struct SG32ENTRY);
1136 } else {
1137 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1c57e86d 1138
cdd3cb15
NC		 1139 pdma_sg->addresshigh = address_hi;
1140 pdma_sg->address = address_lo;
1141 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
1142 psge += sizeof (struct SG64ENTRY);
1143 arccdbsize += sizeof (struct SG64ENTRY);
1c57e86d 1144 }
cdd3cb15
NC		 1145 }
1146 arcmsr_cdb->sgcount = (uint8_t)nseg;
1147 arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
ae52e7f0 1148 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
cdd3cb15
NC		 1149 if ( arccdbsize > 256)
1150 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
c32e061f 1151 if (pcmd->sc_data_direction == DMA_TO_DEVICE)
1c57e86d 1152 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
cdd3cb15 1153 ccb->arc_cdb_size = arccdbsize;
76d78300 1154 return SUCCESS;
1c57e86d
EC		 1155}
1156
1157static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
1158{
cdd3cb15 1159 uint32_t cdb_phyaddr_pattern = ccb->cdb_phyaddr_pattern;
1c57e86d 1160 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1c57e86d
EC		 1161 atomic_inc(&acb->ccboutstandingcount);
1162 ccb->startdone = ARCMSR_CCB_START;
1a4f550a
NC		 1163 switch (acb->adapter_type) {
1164 case ACB_ADAPTER_TYPE_A: {
80da1adb 1165 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1166
1167 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
cdd3cb15 1168 writel(cdb_phyaddr_pattern | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
1c57e86d 1169 &reg->inbound_queueport);
1a4f550a 1170 else {
cdd3cb15 1171 writel(cdb_phyaddr_pattern, &reg->inbound_queueport);
1a4f550a
NC		 1172 }
1173 }
1174 break;
1c57e86d 1175
1a4f550a 1176 case ACB_ADAPTER_TYPE_B: {
80da1adb 1177 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1178 uint32_t ending_index, index = reg->postq_index;
1c57e86d 1179
1a4f550a
NC		 1180 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
1181 writel(0, &reg->post_qbuffer[ending_index]);
1182 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
cdd3cb15 1183 writel(cdb_phyaddr_pattern | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,\
1a4f550a 1184 &reg->post_qbuffer[index]);
cdd3cb15
NC		 1185 } else {
1186 writel(cdb_phyaddr_pattern, &reg->post_qbuffer[index]);
1a4f550a
NC		 1187 }
1188 index++;
1189 index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
1190 reg->postq_index = index;
ae52e7f0 1191 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
1c57e86d 1192 }
1a4f550a 1193 break;
cdd3cb15
NC		 1194 case ACB_ADAPTER_TYPE_C: {
1195 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)acb->pmuC;
1196 uint32_t ccb_post_stamp, arc_cdb_size;
1197
1198 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
1199 ccb_post_stamp = (cdb_phyaddr_pattern | ((arc_cdb_size - 1) >> 6) | 1);
1200 if (acb->cdb_phyaddr_hi32) {
1201 writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high);
1202 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1203 } else {
1204 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1205 }
1206 }
1c57e86d
EC		 1207 }
1208}
1209
1a4f550a 1210static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1c57e86d 1211{
80da1adb 1212 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d
EC		 1213 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1214 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
cdd3cb15 1215 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 1216 printk(KERN_NOTICE
1217 "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1218 , acb->host->host_no);
1219 }
1220}
1221
1222static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1223{
80da1adb 1224 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1225 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
ae52e7f0 1226 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
1a4f550a 1227
cdd3cb15 1228 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1c57e86d
EC		 1229 printk(KERN_NOTICE
1230 "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1231 , acb->host->host_no);
1a4f550a
NC		 1232 }
1233}
1234
cdd3cb15
NC		 1235static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *pACB)
1236{
1237 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
1238 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1239 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
1240 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
1241 if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
1242 printk(KERN_NOTICE
1243 "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1244 , pACB->host->host_no);
1245 }
1246 return;
1247}
1a4f550a
NC		 1248static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1249{
1250 switch (acb->adapter_type) {
1251 case ACB_ADAPTER_TYPE_A: {
1252 arcmsr_stop_hba_bgrb(acb);
1253 }
1254 break;
1255
1256 case ACB_ADAPTER_TYPE_B: {
1257 arcmsr_stop_hbb_bgrb(acb);
1258 }
1259 break;
cdd3cb15
NC		 1260 case ACB_ADAPTER_TYPE_C: {
1261 arcmsr_stop_hbc_bgrb(acb);
1262 }
1a4f550a 1263 }
1c57e86d
EC		 1264}
1265
1266static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
1267{
cdd3cb15 1268 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
1c57e86d
EC		 1269}
1270
1a4f550a 1271void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1c57e86d 1272{
1a4f550a
NC		 1273 switch (acb->adapter_type) {
1274 case ACB_ADAPTER_TYPE_A: {
80da1adb 1275 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1276 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
1277 }
1278 break;
1c57e86d 1279
1a4f550a 1280 case ACB_ADAPTER_TYPE_B: {
80da1adb 1281 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1282 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1c57e86d 1283 }
1a4f550a 1284 break;
cdd3cb15
NC		 1285 case ACB_ADAPTER_TYPE_C: {
1286 struct MessageUnit_C __iomem *reg = acb->pmuC;
1287 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
1288 }
1c57e86d 1289 }
1a4f550a
NC		 1290}
1291
1292static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1293{
1294 switch (acb->adapter_type) {
1295 case ACB_ADAPTER_TYPE_A: {
80da1adb 1296 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 1297 /*
1a4f550a
NC		 1298 ** push inbound doorbell tell iop, driver data write ok
1299 ** and wait reply on next hwinterrupt for next Qbuffer post
1c57e86d 1300 */
1a4f550a
NC		 1301 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
1302 }
1303 break;
1304
1305 case ACB_ADAPTER_TYPE_B: {
80da1adb 1306 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a
NC		 1307 /*
1308 ** push inbound doorbell tell iop, driver data write ok
1309 ** and wait reply on next hwinterrupt for next Qbuffer post
1310 */
ae52e7f0 1311 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
1a4f550a
NC		 1312 }
1313 break;
cdd3cb15
NC		 1314 case ACB_ADAPTER_TYPE_C: {
1315 struct MessageUnit_C __iomem *reg = acb->pmuC;
1316 /*
1317 ** push inbound doorbell tell iop, driver data write ok
1318 ** and wait reply on next hwinterrupt for next Qbuffer post
1319 */
1320 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
1321 }
1322 break;
1a4f550a
NC		 1323 }
1324}
1325
80da1adb 1326struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
1a4f550a 1327{
0c7eb2eb 1328 struct QBUFFER __iomem *qbuffer = NULL;
1a4f550a
NC		 1329 switch (acb->adapter_type) {
1330
1331 case ACB_ADAPTER_TYPE_A: {
80da1adb
AV		 1332 struct MessageUnit_A __iomem *reg = acb->pmuA;
1333 qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
1a4f550a
NC		 1334 }
1335 break;
1336
1337 case ACB_ADAPTER_TYPE_B: {
80da1adb 1338 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1339 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
1a4f550a
NC		 1340 }
1341 break;
cdd3cb15
NC		 1342 case ACB_ADAPTER_TYPE_C: {
1343 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)acb->pmuC;
1344 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
1345 }
1a4f550a
NC		 1346 }
1347 return qbuffer;
1348}
1349
80da1adb 1350static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
1a4f550a 1351{
0c7eb2eb 1352 struct QBUFFER __iomem *pqbuffer = NULL;
1a4f550a
NC		 1353 switch (acb->adapter_type) {
1354
1355 case ACB_ADAPTER_TYPE_A: {
80da1adb
AV		 1356 struct MessageUnit_A __iomem *reg = acb->pmuA;
1357 pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
1a4f550a
NC		 1358 }
1359 break;
1360
1361 case ACB_ADAPTER_TYPE_B: {
80da1adb 1362 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1363 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
1a4f550a
NC		 1364 }
1365 break;
cdd3cb15
NC		 1366 case ACB_ADAPTER_TYPE_C: {
1367 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
1368 pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
1369 }
1370
1a4f550a
NC		 1371 }
1372 return pqbuffer;
1373}
1374
1375static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1376{
80da1adb 1377 struct QBUFFER __iomem *prbuffer;
1a4f550a 1378 struct QBUFFER *pQbuffer;
80da1adb 1379 uint8_t __iomem *iop_data;
1a4f550a 1380 int32_t my_empty_len, iop_len, rqbuf_firstindex, rqbuf_lastindex;
1a4f550a
NC		 1381 rqbuf_lastindex = acb->rqbuf_lastindex;
1382 rqbuf_firstindex = acb->rqbuf_firstindex;
1383 prbuffer = arcmsr_get_iop_rqbuffer(acb);
80da1adb 1384 iop_data = (uint8_t __iomem *)prbuffer->data;
1a4f550a 1385 iop_len = prbuffer->data_len;
cdd3cb15 1386 my_empty_len = (rqbuf_firstindex - rqbuf_lastindex - 1) & (ARCMSR_MAX_QBUFFER - 1);
1a4f550a
NC		 1387
1388 if (my_empty_len >= iop_len)
1389 {
1390 while (iop_len > 0) {
1391 pQbuffer = (struct QBUFFER *)&acb->rqbuffer[rqbuf_lastindex];
cdd3cb15 1392 memcpy(pQbuffer, iop_data, 1);
1a4f550a
NC		 1393 rqbuf_lastindex++;
1394 rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1395 iop_data++;
1396 iop_len--;
1397 }
1398 acb->rqbuf_lastindex = rqbuf_lastindex;
1399 arcmsr_iop_message_read(acb);
1400 }
1401
1402 else {
1403 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1404 }
1405}
1406
1407static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1408{
1409 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
1410 if (acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1411 uint8_t *pQbuffer;
80da1adb
AV		 1412 struct QBUFFER __iomem *pwbuffer;
1413 uint8_t __iomem *iop_data;
1a4f550a
NC		 1414 int32_t allxfer_len = 0;
1415
1416 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
1417 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1418 iop_data = (uint8_t __iomem *)pwbuffer->data;
1419
1420 while ((acb->wqbuf_firstindex != acb->wqbuf_lastindex) && \
1421 (allxfer_len < 124)) {
1422 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1423 memcpy(iop_data, pQbuffer, 1);
1424 acb->wqbuf_firstindex++;
1425 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1426 iop_data++;
1427 allxfer_len++;
1428 }
1429 pwbuffer->data_len = allxfer_len;
1430
1431 arcmsr_iop_message_wrote(acb);
1432 }
1433
1434 if (acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1435 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1436 }
1437}
1438
1439static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1440{
1441 uint32_t outbound_doorbell;
80da1adb 1442 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1443 outbound_doorbell = readl(&reg->outbound_doorbell);
1444 writel(outbound_doorbell, &reg->outbound_doorbell);
1445 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1446 arcmsr_iop2drv_data_wrote_handle(acb);
1447 }
1448
cdd3cb15 1449 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1a4f550a
NC		 1450 arcmsr_iop2drv_data_read_handle(acb);
1451 }
1452}
cdd3cb15
NC		 1453static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *pACB)
1454{
1455 uint32_t outbound_doorbell;
1456 struct MessageUnit_C *reg = (struct MessageUnit_C *)pACB->pmuC;
1457 /*
1458 *******************************************************************
1459 ** Maybe here we need to check wrqbuffer_lock is lock or not
1460 ** DOORBELL: din! don!
1461 ** check if there are any mail need to pack from firmware
1462 *******************************************************************
1463 */
1464 outbound_doorbell = readl(&reg->outbound_doorbell);
1465 writel(outbound_doorbell, &reg->outbound_doorbell_clear);/*clear interrupt*/
1466 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1467 arcmsr_iop2drv_data_wrote_handle(pACB);
1468 }
1469 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1470 arcmsr_iop2drv_data_read_handle(pACB);
1471 }
1472 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1473 arcmsr_hbc_message_isr(pACB); /* messenger of "driver to iop commands" */
1474 }
1475 return;
1476}
1a4f550a
NC		 1477static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
1478{
1479 uint32_t flag_ccb;
80da1adb 1480 struct MessageUnit_A __iomem *reg = acb->pmuA;
cdd3cb15
NC		 1481 struct ARCMSR_CDB *pARCMSR_CDB;
1482 struct CommandControlBlock *pCCB;
1483 bool error;
1a4f550a 1484 while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
cdd3cb15
NC		 1485 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
1486 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1487 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1488 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 1489 }
1490}
1a4f550a
NC		 1491static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
1492{
1493 uint32_t index;
1494 uint32_t flag_ccb;
80da1adb 1495 struct MessageUnit_B *reg = acb->pmuB;
cdd3cb15
NC		 1496 struct ARCMSR_CDB *pARCMSR_CDB;
1497 struct CommandControlBlock *pCCB;
1498 bool error;
1a4f550a 1499 index = reg->doneq_index;
1a4f550a
NC		 1500 while ((flag_ccb = readl(&reg->done_qbuffer[index])) != 0) {
1501 writel(0, &reg->done_qbuffer[index]);
cdd3cb15
NC		 1502 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
1503 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1504 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1505 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 1506 index++;
1507 index %= ARCMSR_MAX_HBB_POSTQUEUE;
1508 reg->doneq_index = index;
1509 }
1510}
cdd3cb15
NC		 1511
1512static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
1513{
1514 struct MessageUnit_C *phbcmu;
1515 struct ARCMSR_CDB *arcmsr_cdb;
1516 struct CommandControlBlock *ccb;
1517 uint32_t flag_ccb, ccb_cdb_phy, throttling = 0;
1518 int error;
1519
1520 phbcmu = (struct MessageUnit_C *)acb->pmuC;
1521 /* areca cdb command done */
1522 /* Use correct offset and size for syncing */
1523
1524 while (readl(&phbcmu->host_int_status) &
1525 ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR){
1526 /* check if command done with no error*/
1527 flag_ccb = readl(&phbcmu->outbound_queueport_low);
1528 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);/*frame must be 32 bytes aligned*/
1529 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);
1530 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
1531 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
1532 /* check if command done with no error */
1533 arcmsr_drain_donequeue(acb, ccb, error);
1534 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1535 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING, &phbcmu->inbound_doorbell);
1536 break;
1537 }
1538 throttling++;
1539 }
1540}
36b83ded
NC		 1541/*
1542**********************************************************************************
1543** Handle a message interrupt
1544**
cdd3cb15 1545** The only message interrupt we expect is in response to a query for the current adapter config.
36b83ded
NC		 1546** We want this in order to compare the drivemap so that we can detect newly-attached drives.
1547**********************************************************************************
1548*/
1549static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb)
1550{
1551 struct MessageUnit_A *reg = acb->pmuA;
36b83ded
NC		 1552 /*clear interrupt and message state*/
1553 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
1554 schedule_work(&acb->arcmsr_do_message_isr_bh);
1555}
1556static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb)
1557{
1558 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1559
36b83ded 1560 /*clear interrupt and message state*/
ae52e7f0 1561 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
36b83ded
NC		 1562 schedule_work(&acb->arcmsr_do_message_isr_bh);
1563}
cdd3cb15
NC		 1564/*
1565**********************************************************************************
1566** Handle a message interrupt
1567**
1568** The only message interrupt we expect is in response to a query for the
1569** current adapter config.
1570** We want this in order to compare the drivemap so that we can detect newly-attached drives.
1571**********************************************************************************
1572*/
1573static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb)
1574{
1575 struct MessageUnit_C *reg = acb->pmuC;
1576 /*clear interrupt and message state*/
1577 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
1578 schedule_work(&acb->arcmsr_do_message_isr_bh);
1579}
1580
1a4f550a
NC		 1581static int arcmsr_handle_hba_isr(struct AdapterControlBlock *acb)
1582{
1583 uint32_t outbound_intstatus;
80da1adb 1584 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 1585 outbound_intstatus = readl(&reg->outbound_intstatus) &
cdd3cb15 1586 acb->outbound_int_enable;
1a4f550a
NC		 1587 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT)) {
1588 return 1;
1589 }
1590 writel(outbound_intstatus, &reg->outbound_intstatus);
1591 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
1592 arcmsr_hba_doorbell_isr(acb);
1593 }
1594 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
1595 arcmsr_hba_postqueue_isr(acb);
1596 }
cdd3cb15 1597 if(outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
36b83ded
NC		 1598 /* messenger of "driver to iop commands" */
1599 arcmsr_hba_message_isr(acb);
1600 }
1a4f550a
NC		 1601 return 0;
1602}
1603
1604static int arcmsr_handle_hbb_isr(struct AdapterControlBlock *acb)
1605{
1606 uint32_t outbound_doorbell;
80da1adb 1607 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1608 outbound_doorbell = readl(reg->iop2drv_doorbell) &
cdd3cb15 1609 acb->outbound_int_enable;
1a4f550a
NC		 1610 if (!outbound_doorbell)
1611 return 1;
1612
ae52e7f0 1613 writel(~outbound_doorbell, reg->iop2drv_doorbell);
36b83ded
NC		 1614 /*in case the last action of doorbell interrupt clearance is cached,
1615 this action can push HW to write down the clear bit*/
ae52e7f0
NC		 1616 readl(reg->iop2drv_doorbell);
1617 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
cdd3cb15 1618 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
1a4f550a
NC		 1619 arcmsr_iop2drv_data_wrote_handle(acb);
1620 }
1621 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
1622 arcmsr_iop2drv_data_read_handle(acb);
1623 }
1624 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
1625 arcmsr_hbb_postqueue_isr(acb);
1626 }
cdd3cb15 1627 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
36b83ded
NC		 1628 /* messenger of "driver to iop commands" */
1629 arcmsr_hbb_message_isr(acb);
1630 }
1a4f550a
NC		 1631 return 0;
1632}
1633
cdd3cb15
NC		 1634static int arcmsr_handle_hbc_isr(struct AdapterControlBlock *pACB)
1635{
1636 uint32_t host_interrupt_status;
1637 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
1638 /*
1639 *********************************************
1640 ** check outbound intstatus
1641 *********************************************
1642 */
1643 host_interrupt_status = readl(&phbcmu->host_int_status);
1644 if (!host_interrupt_status) {
1645 /*it must be share irq*/
1646 return 1;
1647 }
1648 /* MU ioctl transfer doorbell interrupts*/
1649 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
1650 arcmsr_hbc_doorbell_isr(pACB); /* messenger of "ioctl message read write" */
1651 }
1652 /* MU post queue interrupts*/
1653 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
1654 arcmsr_hbc_postqueue_isr(pACB); /* messenger of "scsi commands" */
1655 }
1656 return 0;
1657}
1a4f550a
NC		 1658static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
1659{
1660 switch (acb->adapter_type) {
1661 case ACB_ADAPTER_TYPE_A: {
1662 if (arcmsr_handle_hba_isr(acb)) {
1663 return IRQ_NONE;
1664 }
1665 }
1666 break;
1667
1668 case ACB_ADAPTER_TYPE_B: {
1669 if (arcmsr_handle_hbb_isr(acb)) {
1670 return IRQ_NONE;
1671 }
1672 }
1673 break;
cdd3cb15
NC		 1674 case ACB_ADAPTER_TYPE_C: {
1675 if (arcmsr_handle_hbc_isr(acb)) {
1676 return IRQ_NONE;
1677 }
1678 }
1c57e86d 1679 }
1c57e86d
EC		 1680 return IRQ_HANDLED;
1681}
1682
1683static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
1684{
1685 if (acb) {
1686 /* stop adapter background rebuild */
1687 if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
1a4f550a 1688 uint32_t intmask_org;
1c57e86d 1689 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1a4f550a 1690 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d
EC		 1691 arcmsr_stop_adapter_bgrb(acb);
1692 arcmsr_flush_adapter_cache(acb);
1a4f550a
NC		 1693 arcmsr_enable_outbound_ints(acb, intmask_org);
1694 }
1695 }
1696}
1697
1698void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb)
1699{
1700 int32_t wqbuf_firstindex, wqbuf_lastindex;
1701 uint8_t *pQbuffer;
80da1adb
AV		 1702 struct QBUFFER __iomem *pwbuffer;
1703 uint8_t __iomem *iop_data;
1a4f550a 1704 int32_t allxfer_len = 0;
1a4f550a
NC		 1705 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1706 iop_data = (uint8_t __iomem *)pwbuffer->data;
1707 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
1708 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
1709 wqbuf_firstindex = acb->wqbuf_firstindex;
1710 wqbuf_lastindex = acb->wqbuf_lastindex;
1711 while ((wqbuf_firstindex != wqbuf_lastindex) && (allxfer_len < 124)) {
1712 pQbuffer = &acb->wqbuffer[wqbuf_firstindex];
1713 memcpy(iop_data, pQbuffer, 1);
1714 wqbuf_firstindex++;
1715 wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1716 iop_data++;
1717 allxfer_len++;
1c57e86d 1718 }
1a4f550a
NC		 1719 acb->wqbuf_firstindex = wqbuf_firstindex;
1720 pwbuffer->data_len = allxfer_len;
1721 arcmsr_iop_message_wrote(acb);
1c57e86d
EC		 1722 }
1723}
1724
36b83ded 1725static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
1a4f550a 1726 struct scsi_cmnd *cmd)
1c57e86d 1727{
1c57e86d
EC		 1728 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
1729 int retvalue = 0, transfer_len = 0;
1730 char *buffer;
deff2627 1731 struct scatterlist *sg;
1c57e86d
EC		 1732 uint32_t controlcode = (uint32_t ) cmd->cmnd[5] << 24 |
1733 (uint32_t ) cmd->cmnd[6] << 16 |
1734 (uint32_t ) cmd->cmnd[7] << 8 |
1735 (uint32_t ) cmd->cmnd[8];
1a4f550a 1736 /* 4 bytes: Areca io control code */
deff2627 1737 sg = scsi_sglist(cmd);
77dfce07 1738 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
deff2627
FT		 1739 if (scsi_sg_count(cmd) > 1) {
1740 retvalue = ARCMSR_MESSAGE_FAIL;
1741 goto message_out;
1c57e86d 1742 }
deff2627
FT		 1743 transfer_len += sg->length;
1744
1c57e86d
EC		 1745 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
1746 retvalue = ARCMSR_MESSAGE_FAIL;
1747 goto message_out;
1748 }
1749 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
1750 switch(controlcode) {
1a4f550a 1751
1c57e86d 1752 case ARCMSR_MESSAGE_READ_RQBUFFER: {
69e562c2 1753 unsigned char *ver_addr;
1a4f550a
NC		 1754 uint8_t *pQbuffer, *ptmpQbuffer;
1755 int32_t allxfer_len = 0;
1756
69e562c2
DD		 1757 ver_addr = kmalloc(1032, GFP_ATOMIC);
1758 if (!ver_addr) {
1a4f550a
NC		 1759 retvalue = ARCMSR_MESSAGE_FAIL;
1760 goto message_out;
1761 }
cdd3cb15 1762
69e562c2 1763 ptmpQbuffer = ver_addr;
1a4f550a
NC		 1764 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
1765 && (allxfer_len < 1031)) {
1766 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
1767 memcpy(ptmpQbuffer, pQbuffer, 1);
1768 acb->rqbuf_firstindex++;
1769 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1770 ptmpQbuffer++;
1771 allxfer_len++;
1772 }
1773 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1c57e86d 1774
80da1adb
AV		 1775 struct QBUFFER __iomem *prbuffer;
1776 uint8_t __iomem *iop_data;
1a4f550a
NC		 1777 int32_t iop_len;
1778
1779 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1780 prbuffer = arcmsr_get_iop_rqbuffer(acb);
80da1adb 1781 iop_data = prbuffer->data;
1a4f550a
NC		 1782 iop_len = readl(&prbuffer->data_len);
1783 while (iop_len > 0) {
1784 acb->rqbuffer[acb->rqbuf_lastindex] = readb(iop_data);
1785 acb->rqbuf_lastindex++;
1786 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1787 iop_data++;
1788 iop_len--;
1c57e86d 1789 }
1a4f550a
NC		 1790 arcmsr_iop_message_read(acb);
1791 }
69e562c2 1792 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr, allxfer_len);
1a4f550a 1793 pcmdmessagefld->cmdmessage.Length = allxfer_len;
cdd3cb15 1794 if(acb->fw_flag == FW_DEADLOCK) {
ae52e7f0 1795 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15
NC		 1796 }else{
1797 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
ae52e7f0 1798 }
69e562c2 1799 kfree(ver_addr);
1c57e86d
EC		 1800 }
1801 break;
1c57e86d 1802
1a4f550a 1803 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
69e562c2 1804 unsigned char *ver_addr;
1a4f550a
NC		 1805 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
1806 uint8_t *pQbuffer, *ptmpuserbuffer;
1807
69e562c2
DD		 1808 ver_addr = kmalloc(1032, GFP_ATOMIC);
1809 if (!ver_addr) {
1a4f550a
NC		 1810 retvalue = ARCMSR_MESSAGE_FAIL;
1811 goto message_out;
1812 }
cdd3cb15
NC		 1813 if(acb->fw_flag == FW_DEADLOCK) {
1814 pcmdmessagefld->cmdmessage.ReturnCode =
36b83ded 1815 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15
NC		 1816 }else{
1817 pcmdmessagefld->cmdmessage.ReturnCode =
ae52e7f0 1818 ARCMSR_MESSAGE_RETURNCODE_OK;
36b83ded 1819 }
69e562c2 1820 ptmpuserbuffer = ver_addr;
1a4f550a
NC		 1821 user_len = pcmdmessagefld->cmdmessage.Length;
1822 memcpy(ptmpuserbuffer, pcmdmessagefld->messagedatabuffer, user_len);
1823 wqbuf_lastindex = acb->wqbuf_lastindex;
1824 wqbuf_firstindex = acb->wqbuf_firstindex;
1825 if (wqbuf_lastindex != wqbuf_firstindex) {
1826 struct SENSE_DATA *sensebuffer =
1827 (struct SENSE_DATA *)cmd->sense_buffer;
1828 arcmsr_post_ioctldata2iop(acb);
1829 /* has error report sensedata */
1830 sensebuffer->ErrorCode = 0x70;
1831 sensebuffer->SenseKey = ILLEGAL_REQUEST;
1832 sensebuffer->AdditionalSenseLength = 0x0A;
1833 sensebuffer->AdditionalSenseCode = 0x20;
1834 sensebuffer->Valid = 1;
1835 retvalue = ARCMSR_MESSAGE_FAIL;
1836 } else {
1837 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
1838 &(ARCMSR_MAX_QBUFFER - 1);
1839 if (my_empty_len >= user_len) {
1840 while (user_len > 0) {
1841 pQbuffer =
1842 &acb->wqbuffer[acb->wqbuf_lastindex];
1843 memcpy(pQbuffer, ptmpuserbuffer, 1);
1844 acb->wqbuf_lastindex++;
1845 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1846 ptmpuserbuffer++;
1847 user_len--;
1848 }
1849 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
1850 acb->acb_flags &=
1851 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
1852 arcmsr_post_ioctldata2iop(acb);
1853 }
1854 } else {
1855 /* has error report sensedata */
1c57e86d
EC		 1856 struct SENSE_DATA *sensebuffer =
1857 (struct SENSE_DATA *)cmd->sense_buffer;
1c57e86d
EC		 1858 sensebuffer->ErrorCode = 0x70;
1859 sensebuffer->SenseKey = ILLEGAL_REQUEST;
1860 sensebuffer->AdditionalSenseLength = 0x0A;
1861 sensebuffer->AdditionalSenseCode = 0x20;
1862 sensebuffer->Valid = 1;
1863 retvalue = ARCMSR_MESSAGE_FAIL;
1a4f550a 1864 }
1c57e86d 1865 }
69e562c2 1866 kfree(ver_addr);
1c57e86d
EC		 1867 }
1868 break;
1a4f550a 1869
1c57e86d 1870 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
1a4f550a 1871 uint8_t *pQbuffer = acb->rqbuffer;
1a4f550a
NC		 1872 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1873 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1874 arcmsr_iop_message_read(acb);
1875 }
1876 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
1877 acb->rqbuf_firstindex = 0;
1878 acb->rqbuf_lastindex = 0;
1879 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
cdd3cb15 1880 if(acb->fw_flag == FW_DEADLOCK) {
ae52e7f0
NC		 1881 pcmdmessagefld->cmdmessage.ReturnCode =
1882 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1883 }else{
ae52e7f0
NC		 1884 pcmdmessagefld->cmdmessage.ReturnCode =
1885 ARCMSR_MESSAGE_RETURNCODE_OK;
1886 }
1c57e86d
EC		 1887 }
1888 break;
1a4f550a 1889
1c57e86d 1890 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
1a4f550a 1891 uint8_t *pQbuffer = acb->wqbuffer;
cdd3cb15 1892 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1893 pcmdmessagefld->cmdmessage.ReturnCode =
1894 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1895 }else{
ae52e7f0
NC		 1896 pcmdmessagefld->cmdmessage.ReturnCode =
1897 ARCMSR_MESSAGE_RETURNCODE_OK;
36b83ded 1898 }
1c57e86d 1899
1a4f550a
NC		 1900 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1901 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1902 arcmsr_iop_message_read(acb);
1903 }
1904 acb->acb_flags |=
1905 (ACB_F_MESSAGE_WQBUFFER_CLEARED |
1906 ACB_F_MESSAGE_WQBUFFER_READED);
1907 acb->wqbuf_firstindex = 0;
1908 acb->wqbuf_lastindex = 0;
1909 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
1c57e86d
EC		 1910 }
1911 break;
1a4f550a 1912
1c57e86d 1913 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
1a4f550a 1914 uint8_t *pQbuffer;
1c57e86d 1915
1a4f550a
NC		 1916 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
1917 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
1918 arcmsr_iop_message_read(acb);
1919 }
1920 acb->acb_flags |=
1921 (ACB_F_MESSAGE_WQBUFFER_CLEARED
1922 | ACB_F_MESSAGE_RQBUFFER_CLEARED
1923 | ACB_F_MESSAGE_WQBUFFER_READED);
1924 acb->rqbuf_firstindex = 0;
1925 acb->rqbuf_lastindex = 0;
1926 acb->wqbuf_firstindex = 0;
1927 acb->wqbuf_lastindex = 0;
1928 pQbuffer = acb->rqbuffer;
1929 memset(pQbuffer, 0, sizeof(struct QBUFFER));
1930 pQbuffer = acb->wqbuffer;
1931 memset(pQbuffer, 0, sizeof(struct QBUFFER));
cdd3cb15 1932 if(acb->fw_flag == FW_DEADLOCK) {
ae52e7f0
NC		 1933 pcmdmessagefld->cmdmessage.ReturnCode =
1934 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1935 }else{
ae52e7f0
NC		 1936 pcmdmessagefld->cmdmessage.ReturnCode =
1937 ARCMSR_MESSAGE_RETURNCODE_OK;
1938 }
1c57e86d
EC		 1939 }
1940 break;
1a4f550a 1941
1c57e86d 1942 case ARCMSR_MESSAGE_RETURN_CODE_3F: {
cdd3cb15 1943 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1944 pcmdmessagefld->cmdmessage.ReturnCode =
1945 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1946 }else{
ae52e7f0
NC		 1947 pcmdmessagefld->cmdmessage.ReturnCode =
1948 ARCMSR_MESSAGE_RETURNCODE_3F;
1c57e86d
EC		 1949 }
1950 break;
ae52e7f0 1951 }
1c57e86d 1952 case ARCMSR_MESSAGE_SAY_HELLO: {
1a4f550a 1953 int8_t *hello_string = "Hello! I am ARCMSR";
cdd3cb15 1954 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1955 pcmdmessagefld->cmdmessage.ReturnCode =
1956 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
cdd3cb15 1957 }else{
ae52e7f0
NC		 1958 pcmdmessagefld->cmdmessage.ReturnCode =
1959 ARCMSR_MESSAGE_RETURNCODE_OK;
36b83ded 1960 }
1a4f550a
NC		 1961 memcpy(pcmdmessagefld->messagedatabuffer, hello_string
1962 , (int16_t)strlen(hello_string));
1c57e86d
EC		 1963 }
1964 break;
1a4f550a 1965
1c57e86d 1966 case ARCMSR_MESSAGE_SAY_GOODBYE:
cdd3cb15 1967 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1968 pcmdmessagefld->cmdmessage.ReturnCode =
1969 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
36b83ded 1970 }
1c57e86d
EC		 1971 arcmsr_iop_parking(acb);
1972 break;
1a4f550a 1973
1c57e86d 1974 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
cdd3cb15 1975 if(acb->fw_flag == FW_DEADLOCK) {
36b83ded
NC		 1976 pcmdmessagefld->cmdmessage.ReturnCode =
1977 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
36b83ded 1978 }
1c57e86d
EC		 1979 arcmsr_flush_adapter_cache(acb);
1980 break;
1a4f550a 1981
1c57e86d
EC		 1982 default:
1983 retvalue = ARCMSR_MESSAGE_FAIL;
1984 }
1a4f550a 1985 message_out:
deff2627 1986 sg = scsi_sglist(cmd);
77dfce07 1987 kunmap_atomic(buffer - sg->offset);
1c57e86d
EC		 1988 return retvalue;
1989}
1990
1991static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
1992{
1993 struct list_head *head = &acb->ccb_free_list;
1994 struct CommandControlBlock *ccb = NULL;
ae52e7f0
NC		 1995 unsigned long flags;
1996 spin_lock_irqsave(&acb->ccblist_lock, flags);
1c57e86d
EC		 1997 if (!list_empty(head)) {
1998 ccb = list_entry(head->next, struct CommandControlBlock, list);
ae52e7f0 1999 list_del_init(&ccb->list);
cdd3cb15 2000 }else{
ae52e7f0
NC		 2001 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
2002 return 0;
1c57e86d 2003 }
ae52e7f0 2004 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 2005 return ccb;
2006}
2007
2008static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2009 struct scsi_cmnd *cmd)
2010{
2011 switch (cmd->cmnd[0]) {
2012 case INQUIRY: {
2013 unsigned char inqdata[36];
2014 char *buffer;
deff2627 2015 struct scatterlist *sg;
1c57e86d
EC		 2016
2017 if (cmd->device->lun) {
2018 cmd->result = (DID_TIME_OUT << 16);
2019 cmd->scsi_done(cmd);
2020 return;
2021 }
2022 inqdata[0] = TYPE_PROCESSOR;
2023 /* Periph Qualifier & Periph Dev Type */
2024 inqdata[1] = 0;
2025 /* rem media bit & Dev Type Modifier */
2026 inqdata[2] = 0;
a1f6e021 2027 /* ISO, ECMA, & ANSI versions */
1c57e86d
EC		 2028 inqdata[4] = 31;
2029 /* length of additional data */
2030 strncpy(&inqdata[8], "Areca ", 8);
2031 /* Vendor Identification */
2032 strncpy(&inqdata[16], "RAID controller ", 16);
2033 /* Product Identification */
2034 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
1c57e86d 2035
deff2627 2036 sg = scsi_sglist(cmd);
77dfce07 2037 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
deff2627 2038
1c57e86d 2039 memcpy(buffer, inqdata, sizeof(inqdata));
deff2627 2040 sg = scsi_sglist(cmd);
77dfce07 2041 kunmap_atomic(buffer - sg->offset);
1c57e86d 2042
1c57e86d
EC		 2043 cmd->scsi_done(cmd);
2044 }
2045 break;
2046 case WRITE_BUFFER:
2047 case READ_BUFFER: {
2048 if (arcmsr_iop_message_xfer(acb, cmd))
2049 cmd->result = (DID_ERROR << 16);
2050 cmd->scsi_done(cmd);
2051 }
2052 break;
2053 default:
2054 cmd->scsi_done(cmd);
2055 }
2056}
2057
f281233d 2058static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
1c57e86d
EC		 2059 void (* done)(struct scsi_cmnd *))
2060{
2061 struct Scsi_Host *host = cmd->device->host;
1a4f550a 2062 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
1c57e86d
EC		 2063 struct CommandControlBlock *ccb;
2064 int target = cmd->device->id;
2065 int lun = cmd->device->lun;
36b83ded 2066 uint8_t scsicmd = cmd->cmnd[0];
1c57e86d
EC		 2067 cmd->scsi_done = done;
2068 cmd->host_scribble = NULL;
2069 cmd->result = 0;
cdd3cb15
NC		 2070 if ((scsicmd == SYNCHRONIZE_CACHE) ||(scsicmd == SEND_DIAGNOSTIC)){
2071 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
2072 cmd->result = (DID_NO_CONNECT << 16);
36b83ded
NC		 2073 }
2074 cmd->scsi_done(cmd);
2075 return 0;
2076 }
a1f6e021 2077 if (target == 16) {
1c57e86d
EC		 2078 /* virtual device for iop message transfer */
2079 arcmsr_handle_virtual_command(acb, cmd);
2080 return 0;
2081 }
1c57e86d
EC		 2082 if (atomic_read(&acb->ccboutstandingcount) >=
2083 ARCMSR_MAX_OUTSTANDING_CMD)
2084 return SCSI_MLQUEUE_HOST_BUSY;
1c57e86d
EC		 2085 ccb = arcmsr_get_freeccb(acb);
2086 if (!ccb)
2087 return SCSI_MLQUEUE_HOST_BUSY;
cdd3cb15 2088 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
76d78300
NC		 2089 cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
2090 cmd->scsi_done(cmd);
2091 return 0;
2092 }
1c57e86d
EC		 2093 arcmsr_post_ccb(acb, ccb);
2094 return 0;
2095}
2096
f281233d
JG		 2097static DEF_SCSI_QCMD(arcmsr_queue_command)
2098
ae52e7f0 2099static bool arcmsr_get_hba_config(struct AdapterControlBlock *acb)
1c57e86d 2100{
80da1adb 2101 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d
EC		 2102 char *acb_firm_model = acb->firm_model;
2103 char *acb_firm_version = acb->firm_version;
36b83ded 2104 char *acb_device_map = acb->device_map;
80da1adb
AV		 2105 char __iomem *iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]);
2106 char __iomem *iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]);
cdd3cb15 2107 char __iomem *iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]);
1c57e86d 2108 int count;
1c57e86d 2109 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
cdd3cb15 2110 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 2111 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2112 miscellaneous data' timeout \n", acb->host->host_no);
ae52e7f0 2113 return false;
1a4f550a 2114 }
1c57e86d 2115 count = 8;
cdd3cb15 2116 while (count){
1c57e86d
EC		 2117 *acb_firm_model = readb(iop_firm_model);
2118 acb_firm_model++;
2119 iop_firm_model++;
2120 count--;
2121 }
1a4f550a 2122
1c57e86d 2123 count = 16;
cdd3cb15 2124 while (count){
1c57e86d
EC		 2125 *acb_firm_version = readb(iop_firm_version);
2126 acb_firm_version++;
2127 iop_firm_version++;
2128 count--;
2129 }
1a4f550a 2130
cdd3cb15
NC		 2131 count=16;
2132 while(count){
2133 *acb_device_map = readb(iop_device_map);
2134 acb_device_map++;
2135 iop_device_map++;
2136 count--;
2137 }
2138 printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
ae52e7f0
NC		 2139 acb->host->host_no,
2140 acb->firm_version,
2141 acb->firm_model);
cdd3cb15 2142 acb->signature = readl(&reg->message_rwbuffer[0]);
1c57e86d
EC		 2143 acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
2144 acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
2145 acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
2146 acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
ae52e7f0
NC		 2147 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2148 return true;
1c57e86d 2149}
ae52e7f0 2150static bool arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
1a4f550a 2151{
80da1adb 2152 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0
NC		 2153 struct pci_dev *pdev = acb->pdev;
2154 void *dma_coherent;
2155 dma_addr_t dma_coherent_handle;
1a4f550a
NC		 2156 char *acb_firm_model = acb->firm_model;
2157 char *acb_firm_version = acb->firm_version;
36b83ded 2158 char *acb_device_map = acb->device_map;
ae52e7f0 2159 char __iomem *iop_firm_model;
1a4f550a 2160 /*firm_model,15,60-67*/
ae52e7f0 2161 char __iomem *iop_firm_version;
1a4f550a 2162 /*firm_version,17,68-83*/
ae52e7f0 2163 char __iomem *iop_device_map;
36b83ded 2164 /*firm_version,21,84-99*/
1a4f550a 2165 int count;
ae52e7f0 2166 dma_coherent = dma_alloc_coherent(&pdev->dev, sizeof(struct MessageUnit_B), &dma_coherent_handle, GFP_KERNEL);
cdd3cb15 2167 if (!dma_coherent){
ae52e7f0
NC		 2168 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error for hbb mu\n", acb->host->host_no);
2169 return false;
2170 }
2171 acb->dma_coherent_handle_hbb_mu = dma_coherent_handle;
2172 reg = (struct MessageUnit_B *)dma_coherent;
2173 acb->pmuB = reg;
cdd3cb15 2174 reg->drv2iop_doorbell= (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL);
ae52e7f0
NC		 2175 reg->drv2iop_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL_MASK);
2176 reg->iop2drv_doorbell = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL);
2177 reg->iop2drv_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL_MASK);
2178 reg->message_wbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_WBUFFER);
2179 reg->message_rbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RBUFFER);
2180 reg->message_rwbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RWBUFFER);
2181 iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]); /*firm_model,15,60-67*/
2182 iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]); /*firm_version,17,68-83*/
2183 iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]); /*firm_version,21,84-99*/
2184
2185 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
cdd3cb15 2186 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2187 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2188 miscellaneous data' timeout \n", acb->host->host_no);
ae52e7f0 2189 return false;
1a4f550a 2190 }
1a4f550a 2191 count = 8;
cdd3cb15 2192 while (count){
1a4f550a
NC		 2193 *acb_firm_model = readb(iop_firm_model);
2194 acb_firm_model++;
2195 iop_firm_model++;
2196 count--;
2197 }
1a4f550a 2198 count = 16;
cdd3cb15 2199 while (count){
1a4f550a
NC		 2200 *acb_firm_version = readb(iop_firm_version);
2201 acb_firm_version++;
2202 iop_firm_version++;
2203 count--;
2204 }
2205
cdd3cb15
NC		 2206 count = 16;
2207 while(count){
2208 *acb_device_map = readb(iop_device_map);
2209 acb_device_map++;
2210 iop_device_map++;
2211 count--;
2212 }
2213
ae52e7f0 2214 printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
cdd3cb15 2215 acb->host->host_no,
ae52e7f0
NC		 2216 acb->firm_version,
2217 acb->firm_model);
1a4f550a 2218
ae52e7f0 2219 acb->signature = readl(&reg->message_rwbuffer[1]);
cdd3cb15 2220 /*firm_signature,1,00-03*/
ae52e7f0 2221 acb->firm_request_len = readl(&reg->message_rwbuffer[2]);
1a4f550a 2222 /*firm_request_len,1,04-07*/
ae52e7f0 2223 acb->firm_numbers_queue = readl(&reg->message_rwbuffer[3]);
1a4f550a 2224 /*firm_numbers_queue,2,08-11*/
ae52e7f0 2225 acb->firm_sdram_size = readl(&reg->message_rwbuffer[4]);
1a4f550a 2226 /*firm_sdram_size,3,12-15*/
ae52e7f0 2227 acb->firm_hd_channels = readl(&reg->message_rwbuffer[5]);
1a4f550a 2228 /*firm_ide_channels,4,16-19*/
ae52e7f0
NC		 2229 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2230 /*firm_ide_channels,4,16-19*/
2231 return true;
1a4f550a 2232}
cdd3cb15
NC		 2233
2234static bool arcmsr_get_hbc_config(struct AdapterControlBlock *pACB)
2235{
2236 uint32_t intmask_org, Index, firmware_state = 0;
2237 struct MessageUnit_C *reg = pACB->pmuC;
2238 char *acb_firm_model = pACB->firm_model;
2239 char *acb_firm_version = pACB->firm_version;
2240 char *iop_firm_model = (char *)(&reg->msgcode_rwbuffer[15]); /*firm_model,15,60-67*/
2241 char *iop_firm_version = (char *)(&reg->msgcode_rwbuffer[17]); /*firm_version,17,68-83*/
2242 int count;
2243 /* disable all outbound interrupt */
2244 intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
2245 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
2246 /* wait firmware ready */
2247 do {
2248 firmware_state = readl(&reg->outbound_msgaddr1);
2249 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
2250 /* post "get config" instruction */
2251 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
2252 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2253 /* wait message ready */
2254 for (Index = 0; Index < 2000; Index++) {
2255 if (readl(&reg->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
2256 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);/*clear interrupt*/
2257 break;
2258 }
2259 udelay(10);
2260 } /*max 1 seconds*/
2261 if (Index >= 2000) {
2262 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2263 miscellaneous data' timeout \n", pACB->host->host_no);
2264 return false;
2265 }
2266 count = 8;
2267 while (count) {
2268 *acb_firm_model = readb(iop_firm_model);
2269 acb_firm_model++;
2270 iop_firm_model++;
2271 count--;
2272 }
2273 count = 16;
2274 while (count) {
2275 *acb_firm_version = readb(iop_firm_version);
2276 acb_firm_version++;
2277 iop_firm_version++;
2278 count--;
2279 }
2280 printk(KERN_NOTICE "Areca RAID Controller%d: F/W %s & Model %s\n",
2281 pACB->host->host_no,
2282 pACB->firm_version,
2283 pACB->firm_model);
2284 pACB->firm_request_len = readl(&reg->msgcode_rwbuffer[1]); /*firm_request_len,1,04-07*/
2285 pACB->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[2]); /*firm_numbers_queue,2,08-11*/
2286 pACB->firm_sdram_size = readl(&reg->msgcode_rwbuffer[3]); /*firm_sdram_size,3,12-15*/
2287 pACB->firm_hd_channels = readl(&reg->msgcode_rwbuffer[4]); /*firm_ide_channels,4,16-19*/
2288 pACB->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2289 /*all interrupt service will be enable at arcmsr_iop_init*/
2290 return true;
2291}
ae52e7f0 2292static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
1a4f550a 2293{
ae52e7f0
NC		 2294 if (acb->adapter_type == ACB_ADAPTER_TYPE_A)
2295 return arcmsr_get_hba_config(acb);
cdd3cb15 2296 else if (acb->adapter_type == ACB_ADAPTER_TYPE_B)
ae52e7f0 2297 return arcmsr_get_hbb_config(acb);
cdd3cb15
NC		 2298 else
2299 return arcmsr_get_hbc_config(acb);
1a4f550a
NC		 2300}
2301
ae52e7f0 2302static int arcmsr_polling_hba_ccbdone(struct AdapterControlBlock *acb,
1c57e86d
EC		 2303 struct CommandControlBlock *poll_ccb)
2304{
80da1adb 2305 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 2306 struct CommandControlBlock *ccb;
ae52e7f0 2307 struct ARCMSR_CDB *arcmsr_cdb;
1c57e86d 2308 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
ae52e7f0 2309 int rtn;
cdd3cb15 2310 bool error;
1a4f550a 2311 polling_hba_ccb_retry:
1c57e86d 2312 poll_count++;
1a4f550a 2313 outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
1c57e86d
EC		 2314 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
2315 while (1) {
2316 if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
cdd3cb15 2317 if (poll_ccb_done){
ae52e7f0 2318 rtn = SUCCESS;
1c57e86d 2319 break;
cdd3cb15
NC		 2320 }else {
2321 msleep(25);
2322 if (poll_count > 100){
ae52e7f0 2323 rtn = FAILED;
1c57e86d 2324 break;
ae52e7f0 2325 }
1a4f550a 2326 goto polling_hba_ccb_retry;
1c57e86d
EC		 2327 }
2328 }
ae52e7f0
NC		 2329 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
2330 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
1a4f550a
NC		 2331 poll_ccb_done = (ccb == poll_ccb) ? 1:0;
2332 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
2333 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
2334 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
1c57e86d
EC		 2335 " poll command abort successfully \n"
2336 , acb->host->host_no
2337 , ccb->pcmd->device->id
2338 , ccb->pcmd->device->lun
2339 , ccb);
2340 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 2341 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 2342 continue;
2343 }
1a4f550a
NC		 2344 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2345 " command done ccb = '0x%p'"
a1f6e021 2346 "ccboutstandingcount = %d \n"
1c57e86d
EC		 2347 , acb->host->host_no
2348 , ccb
2349 , atomic_read(&acb->ccboutstandingcount));
2350 continue;
cdd3cb15
NC		 2351 }
2352 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2353 arcmsr_report_ccb_state(acb, ccb, error);
1a4f550a 2354 }
ae52e7f0
NC		 2355 return rtn;
2356}
1a4f550a 2357
ae52e7f0 2358static int arcmsr_polling_hbb_ccbdone(struct AdapterControlBlock *acb,
1a4f550a
NC		 2359 struct CommandControlBlock *poll_ccb)
2360{
cdd3cb15 2361 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2362 struct ARCMSR_CDB *arcmsr_cdb;
cdd3cb15
NC		 2363 struct CommandControlBlock *ccb;
2364 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
ae52e7f0 2365 int index, rtn;
cdd3cb15 2366 bool error;
1a4f550a 2367 polling_hbb_ccb_retry:
97b99127 2368
cdd3cb15
NC		 2369 poll_count++;
2370 /* clear doorbell interrupt */
ae52e7f0 2371 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
cdd3cb15
NC		 2372 while(1){
2373 index = reg->doneq_index;
2374 if ((flag_ccb = readl(&reg->done_qbuffer[index])) == 0) {
2375 if (poll_ccb_done){
ae52e7f0 2376 rtn = SUCCESS;
cdd3cb15
NC		 2377 break;
2378 }else {
2379 msleep(25);
2380 if (poll_count > 100){
ae52e7f0 2381 rtn = FAILED;
cdd3cb15 2382 break;
1c57e86d 2383 }
cdd3cb15 2384 goto polling_hbb_ccb_retry;
1a4f550a 2385 }
cdd3cb15
NC		 2386 }
2387 writel(0, &reg->done_qbuffer[index]);
2388 index++;
2389 /*if last index number set it to 0 */
2390 index %= ARCMSR_MAX_HBB_POSTQUEUE;
2391 reg->doneq_index = index;
2392 /* check if command done with no error*/
ae52e7f0
NC		 2393 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
2394 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
cdd3cb15
NC		 2395 poll_ccb_done = (ccb == poll_ccb) ? 1:0;
2396 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
2397 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
ae52e7f0
NC		 2398 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
2399 " poll command abort successfully \n"
cdd3cb15
NC		 2400 ,acb->host->host_no
2401 ,ccb->pcmd->device->id
2402 ,ccb->pcmd->device->lun
2403 ,ccb);
2404 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 2405 arcmsr_ccb_complete(ccb);
cdd3cb15
NC		 2406 continue;
2407 }
2408 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2409 " command done ccb = '0x%p'"
2410 "ccboutstandingcount = %d \n"
2411 , acb->host->host_no
2412 , ccb
2413 , atomic_read(&acb->ccboutstandingcount));
2414 continue;
2415 }
2416 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2417 arcmsr_report_ccb_state(acb, ccb, error);
2418 }
2419 return rtn;
2420}
2421
2422static int arcmsr_polling_hbc_ccbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_ccb)
2423{
2424 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2425 uint32_t flag_ccb, ccb_cdb_phy;
2426 struct ARCMSR_CDB *arcmsr_cdb;
2427 bool error;
2428 struct CommandControlBlock *pCCB;
2429 uint32_t poll_ccb_done = 0, poll_count = 0;
2430 int rtn;
2431polling_hbc_ccb_retry:
2432 poll_count++;
2433 while (1) {
2434 if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
2435 if (poll_ccb_done) {
2436 rtn = SUCCESS;
2437 break;
2438 } else {
2439 msleep(25);
2440 if (poll_count > 100) {
2441 rtn = FAILED;
2442 break;
1c57e86d 2443 }
cdd3cb15
NC		 2444 goto polling_hbc_ccb_retry;
2445 }
2446 }
2447 flag_ccb = readl(&reg->outbound_queueport_low);
2448 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
2449 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);/*frame must be 32 bytes aligned*/
2450 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
2451 poll_ccb_done = (pCCB == poll_ccb) ? 1 : 0;
2452 /* check ifcommand done with no error*/
2453 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
2454 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
2455 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
2456 " poll command abort successfully \n"
1c57e86d 2457 , acb->host->host_no
cdd3cb15
NC		 2458 , pCCB->pcmd->device->id
2459 , pCCB->pcmd->device->lun
2460 , pCCB);
2461 pCCB->pcmd->result = DID_ABORT << 16;
2462 arcmsr_ccb_complete(pCCB);
1a4f550a 2463 continue;
cdd3cb15
NC		 2464 }
2465 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2466 " command done ccb = '0x%p'"
2467 "ccboutstandingcount = %d \n"
2468 , acb->host->host_no
2469 , pCCB
2470 , atomic_read(&acb->ccboutstandingcount));
2471 continue;
ae52e7f0 2472 }
cdd3cb15
NC		 2473 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
2474 arcmsr_report_ccb_state(acb, pCCB, error);
2475 }
ae52e7f0 2476 return rtn;
1a4f550a 2477}
ae52e7f0 2478static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
1a4f550a
NC		 2479 struct CommandControlBlock *poll_ccb)
2480{
ae52e7f0 2481 int rtn = 0;
1a4f550a
NC		 2482 switch (acb->adapter_type) {
2483
2484 case ACB_ADAPTER_TYPE_A: {
ae52e7f0 2485 rtn = arcmsr_polling_hba_ccbdone(acb, poll_ccb);
1a4f550a
NC		 2486 }
2487 break;
2488
2489 case ACB_ADAPTER_TYPE_B: {
ae52e7f0 2490 rtn = arcmsr_polling_hbb_ccbdone(acb, poll_ccb);
1c57e86d 2491 }
cdd3cb15
NC		 2492 break;
2493 case ACB_ADAPTER_TYPE_C: {
2494 rtn = arcmsr_polling_hbc_ccbdone(acb, poll_ccb);
2495 }
1c57e86d 2496 }
ae52e7f0 2497 return rtn;
1c57e86d 2498}
1a4f550a
NC		 2499
2500static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
a1f6e021 2501{
ae52e7f0 2502 uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
e2c70425 2503
1a4f550a
NC		 2504 /*
2505 ********************************************************************
2506 ** here we need to tell iop 331 our freeccb.HighPart
2507 ** if freeccb.HighPart is not zero
2508 ********************************************************************
2509 */
e2c70425
DC		 2510 cdb_phyaddr = lower_32_bits(acb->dma_coherent_handle);
2511 cdb_phyaddr_hi32 = upper_32_bits(acb->dma_coherent_handle);
cdd3cb15 2512 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
1a4f550a
NC		 2513 /*
2514 ***********************************************************************
2515 ** if adapter type B, set window of "post command Q"
2516 ***********************************************************************
2517 */
2518 switch (acb->adapter_type) {
2519
2520 case ACB_ADAPTER_TYPE_A: {
ae52e7f0 2521 if (cdb_phyaddr_hi32 != 0) {
80da1adb 2522 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2523 uint32_t intmask_org;
2524 intmask_org = arcmsr_disable_outbound_ints(acb);
2525 writel(ARCMSR_SIGNATURE_SET_CONFIG, \
2526 &reg->message_rwbuffer[0]);
ae52e7f0 2527 writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
1a4f550a
NC		 2528 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
2529 &reg->inbound_msgaddr0);
cdd3cb15 2530 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 2531 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
2532 part physical address timeout\n",
2533 acb->host->host_no);
2534 return 1;
a1f6e021 2535 }
1a4f550a
NC		 2536 arcmsr_enable_outbound_ints(acb, intmask_org);
2537 }
2538 }
2539 break;
a1f6e021 2540
1a4f550a
NC		 2541 case ACB_ADAPTER_TYPE_B: {
2542 unsigned long post_queue_phyaddr;
80da1adb 2543 uint32_t __iomem *rwbuffer;
a1f6e021 2544
80da1adb 2545 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a
NC		 2546 uint32_t intmask_org;
2547 intmask_org = arcmsr_disable_outbound_ints(acb);
2548 reg->postq_index = 0;
2549 reg->doneq_index = 0;
ae52e7f0 2550 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
cdd3cb15 2551 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2552 printk(KERN_NOTICE "arcmsr%d:can not set diver mode\n", \
2553 acb->host->host_no);
2554 return 1;
2555 }
ae52e7f0
NC		 2556 post_queue_phyaddr = acb->dma_coherent_handle_hbb_mu;
2557 rwbuffer = reg->message_rwbuffer;
1a4f550a
NC		 2558 /* driver "set config" signature */
2559 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
2560 /* normal should be zero */
ae52e7f0 2561 writel(cdb_phyaddr_hi32, rwbuffer++);
1a4f550a
NC		 2562 /* postQ size (256 + 8)*4 */
2563 writel(post_queue_phyaddr, rwbuffer++);
2564 /* doneQ size (256 + 8)*4 */
2565 writel(post_queue_phyaddr + 1056, rwbuffer++);
2566 /* ccb maxQ size must be --> [(256 + 8)*4]*/
2567 writel(1056, rwbuffer);
2568
ae52e7f0 2569 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
cdd3cb15 2570 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2571 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
2572 timeout \n",acb->host->host_no);
2573 return 1;
2574 }
ae52e7f0 2575 arcmsr_hbb_enable_driver_mode(acb);
1a4f550a
NC		 2576 arcmsr_enable_outbound_ints(acb, intmask_org);
2577 }
2578 break;
cdd3cb15
NC		 2579 case ACB_ADAPTER_TYPE_C: {
2580 if (cdb_phyaddr_hi32 != 0) {
2581 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2582
8b7eb86f
TH		 2583 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n",
2584 acb->adapter_index, cdb_phyaddr_hi32);
cdd3cb15
NC		 2585 writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
2586 writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
2587 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
2588 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2589 if (!arcmsr_hbc_wait_msgint_ready(acb)) {
2590 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
2591 timeout \n", acb->host->host_no);
2592 return 1;
2593 }
2594 }
2595 }
1a4f550a
NC		 2596 }
2597 return 0;
2598}
a1f6e021 2599
1a4f550a
NC		 2600static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
2601{
2602 uint32_t firmware_state = 0;
1a4f550a
NC		 2603 switch (acb->adapter_type) {
2604
2605 case ACB_ADAPTER_TYPE_A: {
80da1adb 2606 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2607 do {
2608 firmware_state = readl(&reg->outbound_msgaddr1);
2609 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
2610 }
2611 break;
2612
2613 case ACB_ADAPTER_TYPE_B: {
80da1adb 2614 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2615 do {
ae52e7f0 2616 firmware_state = readl(reg->iop2drv_doorbell);
1a4f550a 2617 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
ae52e7f0 2618 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
1a4f550a
NC		 2619 }
2620 break;
cdd3cb15
NC		 2621 case ACB_ADAPTER_TYPE_C: {
2622 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2623 do {
2624 firmware_state = readl(&reg->outbound_msgaddr1);
2625 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
2626 }
a1f6e021 2627 }
1a4f550a
NC		 2628}
2629
36b83ded
NC		 2630static void arcmsr_request_hba_device_map(struct AdapterControlBlock *acb)
2631{
2632 struct MessageUnit_A __iomem *reg = acb->pmuA;
cdd3cb15 2633 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
97b99127 2634 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 2635 return;
36b83ded 2636 } else {
ae52e7f0 2637 acb->fw_flag = FW_NORMAL;
cdd3cb15 2638 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)){
36b83ded
NC		 2639 atomic_set(&acb->rq_map_token, 16);
2640 }
ae52e7f0 2641 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
97b99127
N		 2642 if (atomic_dec_and_test(&acb->rq_map_token)) {
2643 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 2644 return;
97b99127 2645 }
36b83ded 2646 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
cdd3cb15 2647 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
36b83ded 2648 }
36b83ded
NC		 2649 return;
2650}
2651
2652static void arcmsr_request_hbb_device_map(struct AdapterControlBlock *acb)
2653{
2654 struct MessageUnit_B __iomem *reg = acb->pmuB;
cdd3cb15 2655 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
97b99127 2656 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
cdd3cb15
NC		 2657 return;
2658 } else {
2659 acb->fw_flag = FW_NORMAL;
2660 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
97b99127 2661 atomic_set(&acb->rq_map_token, 16);
cdd3cb15
NC		 2662 }
2663 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
97b99127
N		 2664 if (atomic_dec_and_test(&acb->rq_map_token)) {
2665 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
cdd3cb15 2666 return;
97b99127 2667 }
cdd3cb15
NC		 2668 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
2669 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
2670 }
2671 return;
2672}
36b83ded 2673
cdd3cb15
NC		 2674static void arcmsr_request_hbc_device_map(struct AdapterControlBlock *acb)
2675{
2676 struct MessageUnit_C __iomem *reg = acb->pmuC;
ae52e7f0 2677 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0) || ((acb->acb_flags & ACB_F_ABORT) != 0)) {
97b99127 2678 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 2679 return;
36b83ded 2680 } else {
ae52e7f0
NC		 2681 acb->fw_flag = FW_NORMAL;
2682 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
36b83ded
NC		 2683 atomic_set(&acb->rq_map_token, 16);
2684 }
ae52e7f0 2685 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
97b99127
N		 2686 if (atomic_dec_and_test(&acb->rq_map_token)) {
2687 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 2688 return;
97b99127 2689 }
cdd3cb15
NC		 2690 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
2691 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2692 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
36b83ded 2693 }
36b83ded
NC		 2694 return;
2695}
2696
2697static void arcmsr_request_device_map(unsigned long pacb)
2698{
2699 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)pacb;
36b83ded
NC		 2700 switch (acb->adapter_type) {
2701 case ACB_ADAPTER_TYPE_A: {
2702 arcmsr_request_hba_device_map(acb);
2703 }
2704 break;
2705 case ACB_ADAPTER_TYPE_B: {
2706 arcmsr_request_hbb_device_map(acb);
2707 }
2708 break;
cdd3cb15
NC		 2709 case ACB_ADAPTER_TYPE_C: {
2710 arcmsr_request_hbc_device_map(acb);
2711 }
36b83ded
NC		 2712 }
2713}
2714
1a4f550a
NC		 2715static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
2716{
80da1adb 2717 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2718 acb->acb_flags |= ACB_F_MSG_START_BGRB;
2719 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
cdd3cb15 2720 if (!arcmsr_hba_wait_msgint_ready(acb)) {
1a4f550a
NC		 2721 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
2722 rebulid' timeout \n", acb->host->host_no);
a1f6e021 2723 }
a1f6e021 2724}
2725
1a4f550a
NC		 2726static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
2727{
80da1adb 2728 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2729 acb->acb_flags |= ACB_F_MSG_START_BGRB;
ae52e7f0 2730 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
cdd3cb15 2731 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
1a4f550a
NC		 2732 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
2733 rebulid' timeout \n",acb->host->host_no);
2734 }
2735}
1c57e86d 2736
cdd3cb15
NC		 2737static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *pACB)
2738{
2739 struct MessageUnit_C *phbcmu = (struct MessageUnit_C *)pACB->pmuC;
2740 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
2741 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
2742 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
2743 if (!arcmsr_hbc_wait_msgint_ready(pACB)) {
2744 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
2745 rebulid' timeout \n", pACB->host->host_no);
2746 }
2747 return;
2748}
1a4f550a 2749static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
1c57e86d 2750{
1a4f550a
NC		 2751 switch (acb->adapter_type) {
2752 case ACB_ADAPTER_TYPE_A:
2753 arcmsr_start_hba_bgrb(acb);
2754 break;
2755 case ACB_ADAPTER_TYPE_B:
2756 arcmsr_start_hbb_bgrb(acb);
2757 break;
cdd3cb15
NC		 2758 case ACB_ADAPTER_TYPE_C:
2759 arcmsr_start_hbc_bgrb(acb);
1a4f550a
NC		 2760 }
2761}
1c57e86d 2762
1a4f550a
NC		 2763static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
2764{
2765 switch (acb->adapter_type) {
2766 case ACB_ADAPTER_TYPE_A: {
80da1adb 2767 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 2768 uint32_t outbound_doorbell;
2769 /* empty doorbell Qbuffer if door bell ringed */
2770 outbound_doorbell = readl(&reg->outbound_doorbell);
2771 /*clear doorbell interrupt */
2772 writel(outbound_doorbell, &reg->outbound_doorbell);
2773 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
2774 }
2775 break;
1c57e86d 2776
1a4f550a 2777 case ACB_ADAPTER_TYPE_B: {
80da1adb 2778 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2779 /*clear interrupt and message state*/
ae52e7f0
NC		 2780 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
2781 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1a4f550a
NC		 2782 /* let IOP know data has been read */
2783 }
2784 break;
cdd3cb15
NC		 2785 case ACB_ADAPTER_TYPE_C: {
2786 struct MessageUnit_C *reg = (struct MessageUnit_C *)acb->pmuC;
2787 uint32_t outbound_doorbell;
2788 /* empty doorbell Qbuffer if door bell ringed */
2789 outbound_doorbell = readl(&reg->outbound_doorbell);
2790 writel(outbound_doorbell, &reg->outbound_doorbell_clear);
2791 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
2792 }
1c57e86d 2793 }
1a4f550a 2794}
1c57e86d 2795
76d78300
NC		 2796static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
2797{
2798 switch (acb->adapter_type) {
2799 case ACB_ADAPTER_TYPE_A:
2800 return;
2801 case ACB_ADAPTER_TYPE_B:
2802 {
2803 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2804 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
cdd3cb15 2805 if (!arcmsr_hbb_wait_msgint_ready(acb)) {
76d78300
NC		 2806 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
2807 return;
2808 }
2809 }
2810 break;
cdd3cb15
NC		 2811 case ACB_ADAPTER_TYPE_C:
2812 return;
76d78300
NC		 2813 }
2814 return;
2815}
2816
36b83ded
NC		 2817static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
2818{
2819 uint8_t value[64];
cdd3cb15
NC		 2820 int i, count = 0;
2821 struct MessageUnit_A __iomem *pmuA = acb->pmuA;
2822 struct MessageUnit_C __iomem *pmuC = acb->pmuC;
6ad819b0 2823
36b83ded 2824 /* backup pci config data */
cdd3cb15 2825 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
36b83ded
NC		 2826 for (i = 0; i < 64; i++) {
2827 pci_read_config_byte(acb->pdev, i, &value[i]);
2828 }
2829 /* hardware reset signal */
ae52e7f0 2830 if ((acb->dev_id == 0x1680)) {
cdd3cb15
NC		 2831 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
2832 } else if ((acb->dev_id == 0x1880)) {
2833 do {
2834 count++;
2835 writel(0xF, &pmuC->write_sequence);
2836 writel(0x4, &pmuC->write_sequence);
2837 writel(0xB, &pmuC->write_sequence);
2838 writel(0x2, &pmuC->write_sequence);
2839 writel(0x7, &pmuC->write_sequence);
2840 writel(0xD, &pmuC->write_sequence);
6ad819b0 2841 } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
cdd3cb15 2842 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
ae52e7f0 2843 } else {
cdd3cb15 2844 pci_write_config_byte(acb->pdev, 0x84, 0x20);
ae52e7f0 2845 }
cdd3cb15 2846 msleep(2000);
36b83ded
NC		 2847 /* write back pci config data */
2848 for (i = 0; i < 64; i++) {
2849 pci_write_config_byte(acb->pdev, i, value[i]);
2850 }
2851 msleep(1000);
2852 return;
2853}
1a4f550a
NC		 2854static void arcmsr_iop_init(struct AdapterControlBlock *acb)
2855{
2856 uint32_t intmask_org;
cdd3cb15
NC		 2857 /* disable all outbound interrupt */
2858 intmask_org = arcmsr_disable_outbound_ints(acb);
76d78300
NC		 2859 arcmsr_wait_firmware_ready(acb);
2860 arcmsr_iop_confirm(acb);
1a4f550a
NC		 2861 /*start background rebuild*/
2862 arcmsr_start_adapter_bgrb(acb);
2863 /* empty doorbell Qbuffer if door bell ringed */
2864 arcmsr_clear_doorbell_queue_buffer(acb);
76d78300 2865 arcmsr_enable_eoi_mode(acb);
1a4f550a
NC		 2866 /* enable outbound Post Queue,outbound doorbell Interrupt */
2867 arcmsr_enable_outbound_ints(acb, intmask_org);
1c57e86d
EC		 2868 acb->acb_flags |= ACB_F_IOP_INITED;
2869}
2870
36b83ded 2871static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
1c57e86d 2872{
1c57e86d
EC		 2873 struct CommandControlBlock *ccb;
2874 uint32_t intmask_org;
36b83ded 2875 uint8_t rtnval = 0x00;
1c57e86d 2876 int i = 0;
97b99127
N		 2877 unsigned long flags;
2878
1c57e86d 2879 if (atomic_read(&acb->ccboutstandingcount) != 0) {
36b83ded
NC		 2880 /* disable all outbound interrupt */
2881 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d 2882 /* talk to iop 331 outstanding command aborted */
36b83ded 2883 rtnval = arcmsr_abort_allcmd(acb);
1c57e86d 2884 /* clear all outbound posted Q */
1a4f550a 2885 arcmsr_done4abort_postqueue(acb);
1c57e86d
EC		 2886 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
2887 ccb = acb->pccb_pool[i];
a1f6e021 2888 if (ccb->startdone == ARCMSR_CCB_START) {
97b99127
N		 2889 scsi_dma_unmap(ccb->pcmd);
2890 ccb->startdone = ARCMSR_CCB_DONE;
2891 ccb->ccb_flags = 0;
2892 spin_lock_irqsave(&acb->ccblist_lock, flags);
2893 list_add_tail(&ccb->list, &acb->ccb_free_list);
2894 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 2895 }
2896 }
36b83ded 2897 atomic_set(&acb->ccboutstandingcount, 0);
1c57e86d
EC		 2898 /* enable all outbound interrupt */
2899 arcmsr_enable_outbound_ints(acb, intmask_org);
36b83ded 2900 return rtnval;
1c57e86d 2901 }
36b83ded 2902 return rtnval;
1c57e86d
EC		 2903}
2904
2905static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
2906{
97b99127 2907 struct AdapterControlBlock *acb;
ae52e7f0
NC		 2908 uint32_t intmask_org, outbound_doorbell;
2909 int retry_count = 0;
2910 int rtn = FAILED;
ae52e7f0 2911 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
cdd3cb15 2912 printk(KERN_ERR "arcmsr: executing bus reset eh.....num_resets = %d, num_aborts = %d \n", acb->num_resets, acb->num_aborts);
36b83ded 2913 acb->num_resets++;
36b83ded 2914
cdd3cb15
NC		 2915 switch(acb->adapter_type){
2916 case ACB_ADAPTER_TYPE_A:{
2917 if (acb->acb_flags & ACB_F_BUS_RESET){
ae52e7f0 2918 long timeout;
cdd3cb15
NC		 2919 printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
2920 timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
ae52e7f0
NC		 2921 if (timeout) {
2922 return SUCCESS;
2923 }
2924 }
2925 acb->acb_flags |= ACB_F_BUS_RESET;
cdd3cb15 2926 if (!arcmsr_iop_reset(acb)) {
ae52e7f0
NC		 2927 struct MessageUnit_A __iomem *reg;
2928 reg = acb->pmuA;
cdd3cb15
NC		 2929 arcmsr_hardware_reset(acb);
2930 acb->acb_flags &= ~ACB_F_IOP_INITED;
36b83ded 2931sleep_again:
8b7eb86f 2932 ssleep(ARCMSR_SLEEPTIME);
ae52e7f0 2933 if ((readl(&reg->outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) {
8b7eb86f
TH		 2934 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d\n", acb->host->host_no, retry_count);
2935 if (retry_count > ARCMSR_RETRYCOUNT) {
ae52e7f0 2936 acb->fw_flag = FW_DEADLOCK;
8b7eb86f 2937 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!!\n", acb->host->host_no);
ae52e7f0 2938 return FAILED;
cdd3cb15
NC		 2939 }
2940 retry_count++;
2941 goto sleep_again;
2942 }
2943 acb->acb_flags |= ACB_F_IOP_INITED;
2944 /* disable all outbound interrupt */
2945 intmask_org = arcmsr_disable_outbound_ints(acb);
ae52e7f0 2946 arcmsr_get_firmware_spec(acb);
cdd3cb15
NC		 2947 arcmsr_start_adapter_bgrb(acb);
2948 /* clear Qbuffer if door bell ringed */
2949 outbound_doorbell = readl(&reg->outbound_doorbell);
2950 writel(outbound_doorbell, &reg->outbound_doorbell); /*clear interrupt */
2951 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
2952 /* enable outbound Post Queue,outbound doorbell Interrupt */
2953 arcmsr_enable_outbound_ints(acb, intmask_org);
2954 atomic_set(&acb->rq_map_token, 16);
ae52e7f0
NC		 2955 atomic_set(&acb->ante_token_value, 16);
2956 acb->fw_flag = FW_NORMAL;
97b99127 2957 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0
NC		 2958 acb->acb_flags &= ~ACB_F_BUS_RESET;
2959 rtn = SUCCESS;
cdd3cb15 2960 printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
ae52e7f0
NC		 2961 } else {
2962 acb->acb_flags &= ~ACB_F_BUS_RESET;
97b99127
N		 2963 atomic_set(&acb->rq_map_token, 16);
2964 atomic_set(&acb->ante_token_value, 16);
2965 acb->fw_flag = FW_NORMAL;
2966 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
ae52e7f0 2967 rtn = SUCCESS;
cdd3cb15 2968 }
ae52e7f0 2969 break;
36b83ded 2970 }
ae52e7f0
NC		 2971 case ACB_ADAPTER_TYPE_B:{
2972 acb->acb_flags |= ACB_F_BUS_RESET;
cdd3cb15 2973 if (!arcmsr_iop_reset(acb)) {
ae52e7f0
NC		 2974 acb->acb_flags &= ~ACB_F_BUS_RESET;
2975 rtn = FAILED;
cdd3cb15
NC		 2976 } else {
2977 acb->acb_flags &= ~ACB_F_BUS_RESET;
97b99127
N		 2978 atomic_set(&acb->rq_map_token, 16);
2979 atomic_set(&acb->ante_token_value, 16);
2980 acb->fw_flag = FW_NORMAL;
2981 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 2982 rtn = SUCCESS;
cdd3cb15
NC		 2983 }
2984 break;
2985 }
2986 case ACB_ADAPTER_TYPE_C:{
2987 if (acb->acb_flags & ACB_F_BUS_RESET) {
2988 long timeout;
2989 printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
2990 timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
2991 if (timeout) {
2992 return SUCCESS;
2993 }
2994 }
2995 acb->acb_flags |= ACB_F_BUS_RESET;
2996 if (!arcmsr_iop_reset(acb)) {
2997 struct MessageUnit_C __iomem *reg;
2998 reg = acb->pmuC;
2999 arcmsr_hardware_reset(acb);
3000 acb->acb_flags &= ~ACB_F_IOP_INITED;
3001sleep:
8b7eb86f 3002 ssleep(ARCMSR_SLEEPTIME);
cdd3cb15 3003 if ((readl(&reg->host_diagnostic) & 0x04) != 0) {
8b7eb86f
TH		 3004 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d\n", acb->host->host_no, retry_count);
3005 if (retry_count > ARCMSR_RETRYCOUNT) {
cdd3cb15 3006 acb->fw_flag = FW_DEADLOCK;
8b7eb86f 3007 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!!\n", acb->host->host_no);
cdd3cb15
NC		 3008 return FAILED;
3009 }
3010 retry_count++;
3011 goto sleep;
3012 }
3013 acb->acb_flags |= ACB_F_IOP_INITED;
3014 /* disable all outbound interrupt */
3015 intmask_org = arcmsr_disable_outbound_ints(acb);
3016 arcmsr_get_firmware_spec(acb);
3017 arcmsr_start_adapter_bgrb(acb);
3018 /* clear Qbuffer if door bell ringed */
3019 outbound_doorbell = readl(&reg->outbound_doorbell);
3020 writel(outbound_doorbell, &reg->outbound_doorbell_clear); /*clear interrupt */
3021 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
3022 /* enable outbound Post Queue,outbound doorbell Interrupt */
3023 arcmsr_enable_outbound_ints(acb, intmask_org);
3024 atomic_set(&acb->rq_map_token, 16);
3025 atomic_set(&acb->ante_token_value, 16);
3026 acb->fw_flag = FW_NORMAL;
97b99127 3027 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
cdd3cb15
NC		 3028 acb->acb_flags &= ~ACB_F_BUS_RESET;
3029 rtn = SUCCESS;
3030 printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
3031 } else {
3032 acb->acb_flags &= ~ACB_F_BUS_RESET;
97b99127
N		 3033 atomic_set(&acb->rq_map_token, 16);
3034 atomic_set(&acb->ante_token_value, 16);
3035 acb->fw_flag = FW_NORMAL;
3036 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
cdd3cb15
NC		 3037 rtn = SUCCESS;
3038 }
3039 break;
ae52e7f0
NC		 3040 }
3041 }
3042 return rtn;
1c57e86d
EC		 3043}
3044
ae52e7f0 3045static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
1c57e86d
EC		 3046 struct CommandControlBlock *ccb)
3047{
ae52e7f0 3048 int rtn;
ae52e7f0 3049 rtn = arcmsr_polling_ccbdone(acb, ccb);
ae52e7f0 3050 return rtn;
1c57e86d
EC		 3051}
3052
3053static int arcmsr_abort(struct scsi_cmnd *cmd)
3054{
3055 struct AdapterControlBlock *acb =
3056 (struct AdapterControlBlock *)cmd->device->host->hostdata;
3057 int i = 0;
ae52e7f0 3058 int rtn = FAILED;
1c57e86d 3059 printk(KERN_NOTICE
a1f6e021 3060 "arcmsr%d: abort device command of scsi id = %d lun = %d \n",
1c57e86d 3061 acb->host->host_no, cmd->device->id, cmd->device->lun);
ae52e7f0 3062 acb->acb_flags |= ACB_F_ABORT;
1c57e86d 3063 acb->num_aborts++;
1c57e86d
EC		 3064 /*
3065 ************************************************
3066 ** the all interrupt service routine is locked
3067 ** we need to handle it as soon as possible and exit
3068 ************************************************
3069 */
3070 if (!atomic_read(&acb->ccboutstandingcount))
ae52e7f0 3071 return rtn;
1c57e86d
EC		 3072
3073 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
3074 struct CommandControlBlock *ccb = acb->pccb_pool[i];
3075 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
ae52e7f0
NC		 3076 ccb->startdone = ARCMSR_CCB_ABORTED;
3077 rtn = arcmsr_abort_one_cmd(acb, ccb);
1c57e86d
EC		 3078 break;
3079 }
3080 }
ae52e7f0
NC		 3081 acb->acb_flags &= ~ACB_F_ABORT;
3082 return rtn;
1c57e86d
EC		 3083}
3084
3085static const char *arcmsr_info(struct Scsi_Host *host)
3086{
3087 struct AdapterControlBlock *acb =
3088 (struct AdapterControlBlock *) host->hostdata;
3089 static char buf[256];
3090 char *type;
3091 int raid6 = 1;
1c57e86d
EC		 3092 switch (acb->pdev->device) {
3093 case PCI_DEVICE_ID_ARECA_1110:
1a4f550a
NC		 3094 case PCI_DEVICE_ID_ARECA_1200:
3095 case PCI_DEVICE_ID_ARECA_1202:
1c57e86d
EC		 3096 case PCI_DEVICE_ID_ARECA_1210:
3097 raid6 = 0;
3098 /*FALLTHRU*/
3099 case PCI_DEVICE_ID_ARECA_1120:
3100 case PCI_DEVICE_ID_ARECA_1130:
3101 case PCI_DEVICE_ID_ARECA_1160:
3102 case PCI_DEVICE_ID_ARECA_1170:
1a4f550a 3103 case PCI_DEVICE_ID_ARECA_1201:
1c57e86d
EC		 3104 case PCI_DEVICE_ID_ARECA_1220:
3105 case PCI_DEVICE_ID_ARECA_1230:
3106 case PCI_DEVICE_ID_ARECA_1260:
3107 case PCI_DEVICE_ID_ARECA_1270:
3108 case PCI_DEVICE_ID_ARECA_1280:
3109 type = "SATA";
3110 break;
3111 case PCI_DEVICE_ID_ARECA_1380:
3112 case PCI_DEVICE_ID_ARECA_1381:
3113 case PCI_DEVICE_ID_ARECA_1680:
3114 case PCI_DEVICE_ID_ARECA_1681:
cdd3cb15 3115 case PCI_DEVICE_ID_ARECA_1880:
1c57e86d
EC		 3116 type = "SAS";
3117 break;
3118 default:
3119 type = "X-TYPE";
3120 break;
3121 }
a1f6e021 3122 sprintf(buf, "Areca %s Host Adapter RAID Controller%s\n %s",
1c57e86d
EC		 3123 type, raid6 ? "( RAID6 capable)" : "",
3124 ARCMSR_DRIVER_VERSION);
3125 return buf;
3126}
Linux 6.x block layer and io_uring tree(s)