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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/mason/linux...
[linux-2.6-block.git] / drivers / scsi / arcmsr / arcmsr_hba.c
CommitLineData
1c57e86d
EC		 1/*
2*******************************************************************************
3** O.S : Linux
4** FILE NAME : arcmsr_hba.c
aaa64f69
CH		 5** BY : Nick Cheng, C.L. Huang
6** Description: SCSI RAID Device Driver for Areca RAID Controller
1c57e86d 7*******************************************************************************
aaa64f69 8** Copyright (C) 2002 - 2014, Areca Technology Corporation All rights reserved
1c57e86d
EC		 9**
10** Web site: www.areca.com.tw
1a4f550a 11** E-mail: support@areca.com.tw
1c57e86d
EC		 12**
13** This program is free software; you can redistribute it and/or modify
14** it under the terms of the GNU General Public License version 2 as
15** published by the Free Software Foundation.
16** This program is distributed in the hope that it will be useful,
17** but WITHOUT ANY WARRANTY; without even the implied warranty of
18** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19** GNU General Public License for more details.
20*******************************************************************************
21** Redistribution and use in source and binary forms, with or without
22** modification, are permitted provided that the following conditions
23** are met:
24** 1. Redistributions of source code must retain the above copyright
25** notice, this list of conditions and the following disclaimer.
26** 2. Redistributions in binary form must reproduce the above copyright
27** notice, this list of conditions and the following disclaimer in the
28** documentation and/or other materials provided with the distribution.
29** 3. The name of the author may not be used to endorse or promote products
30** derived from this software without specific prior written permission.
31**
32** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
33** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
34** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
35** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
36** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT
37** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
38** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
39** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
40** (INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
41** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
42*******************************************************************************
43** For history of changes, see Documentation/scsi/ChangeLog.arcmsr
44** Firmware Specification, see Documentation/scsi/arcmsr_spec.txt
45*******************************************************************************
46*/
47#include <linux/module.h>
48#include <linux/reboot.h>
49#include <linux/spinlock.h>
50#include <linux/pci_ids.h>
51#include <linux/interrupt.h>
52#include <linux/moduleparam.h>
53#include <linux/errno.h>
54#include <linux/types.h>
55#include <linux/delay.h>
56#include <linux/dma-mapping.h>
57#include <linux/timer.h>
a7c8962b 58#include <linux/slab.h>
1c57e86d 59#include <linux/pci.h>
a1f6e021 60#include <linux/aer.h>
2e9feb43 61#include <linux/circ_buf.h>
1c57e86d
EC		 62#include <asm/dma.h>
63#include <asm/io.h>
1c57e86d
EC		 64#include <asm/uaccess.h>
65#include <scsi/scsi_host.h>
66#include <scsi/scsi.h>
67#include <scsi/scsi_cmnd.h>
68#include <scsi/scsi_tcq.h>
69#include <scsi/scsi_device.h>
70#include <scsi/scsi_transport.h>
71#include <scsi/scsicam.h>
72#include "arcmsr.h"
aaa64f69
CH		 73MODULE_AUTHOR("Nick Cheng, C.L. Huang <support@areca.com.tw>");
74MODULE_DESCRIPTION("Areca ARC11xx/12xx/16xx/188x SAS/SATA RAID Controller Driver");
1c57e86d
EC		 75MODULE_LICENSE("Dual BSD/GPL");
76MODULE_VERSION(ARCMSR_DRIVER_VERSION);
8b7eb86f
TH		 77
78#define ARCMSR_SLEEPTIME 10
79#define ARCMSR_RETRYCOUNT 12
80
c10b1d54 81static wait_queue_head_t wait_q;
1a4f550a
NC		 82static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
83 struct scsi_cmnd *cmd);
84static int arcmsr_iop_confirm(struct AdapterControlBlock *acb);
1c57e86d
EC		 85static int arcmsr_abort(struct scsi_cmnd *);
86static int arcmsr_bus_reset(struct scsi_cmnd *);
87static int arcmsr_bios_param(struct scsi_device *sdev,
1a4f550a 88 struct block_device *bdev, sector_t capacity, int *info);
f281233d 89static int arcmsr_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
1c57e86d
EC		 90static int arcmsr_probe(struct pci_dev *pdev,
91 const struct pci_device_id *id);
61cda87f
CH		 92static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state);
93static int arcmsr_resume(struct pci_dev *pdev);
1c57e86d
EC		 94static void arcmsr_remove(struct pci_dev *pdev);
95static void arcmsr_shutdown(struct pci_dev *pdev);
96static void arcmsr_iop_init(struct AdapterControlBlock *acb);
97static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb);
1a4f550a 98static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb);
61cda87f
CH		 99static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
100 u32 intmask_org);
1c57e86d 101static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
626fa32c
CH		 102static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb);
103static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb);
36b83ded 104static void arcmsr_request_device_map(unsigned long pacb);
626fa32c
CH		 105static void arcmsr_hbaA_request_device_map(struct AdapterControlBlock *acb);
106static void arcmsr_hbaB_request_device_map(struct AdapterControlBlock *acb);
107static void arcmsr_hbaC_request_device_map(struct AdapterControlBlock *acb);
36b83ded 108static void arcmsr_message_isr_bh_fn(struct work_struct *work);
ae52e7f0 109static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb);
36b83ded 110static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
626fa32c 111static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *pACB);
5b37479a 112static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb);
cdd3cb15 113static void arcmsr_hardware_reset(struct AdapterControlBlock *acb);
1c57e86d
EC		 114static const char *arcmsr_info(struct Scsi_Host *);
115static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb);
b4eb6ae9 116static void arcmsr_free_irq(struct pci_dev *, struct AdapterControlBlock *);
db5ed4df 117static int arcmsr_adjust_disk_queue_depth(struct scsi_device *sdev, int queue_depth)
1c57e86d
EC		 118{
119 if (queue_depth > ARCMSR_MAX_CMD_PERLUN)
120 queue_depth = ARCMSR_MAX_CMD_PERLUN;
db5ed4df 121 return scsi_change_queue_depth(sdev, queue_depth);
1c57e86d
EC		 122}
123
124static struct scsi_host_template arcmsr_scsi_host_template = {
125 .module = THIS_MODULE,
aaa64f69 126 .name = "Areca SAS/SATA RAID driver",
1c57e86d
EC		 127 .info = arcmsr_info,
128 .queuecommand = arcmsr_queue_command,
cdd3cb15 129 .eh_abort_handler = arcmsr_abort,
1c57e86d
EC		 130 .eh_bus_reset_handler = arcmsr_bus_reset,
131 .bios_param = arcmsr_bios_param,
132 .change_queue_depth = arcmsr_adjust_disk_queue_depth,
3df824af 133 .can_queue = ARCMSR_MAX_OUTSTANDING_CMD,
cdd3cb15
NC		 134 .this_id = ARCMSR_SCSI_INITIATOR_ID,
135 .sg_tablesize = ARCMSR_DEFAULT_SG_ENTRIES,
136 .max_sectors = ARCMSR_MAX_XFER_SECTORS_C,
1c57e86d
EC		 137 .cmd_per_lun = ARCMSR_MAX_CMD_PERLUN,
138 .use_clustering = ENABLE_CLUSTERING,
139 .shost_attrs = arcmsr_host_attrs,
54b2b50c 140 .no_write_same = 1,
1c57e86d 141};
8b7c9942 142
1c57e86d 143static struct pci_device_id arcmsr_device_id_table[] = {
8b7c9942
CH		 144 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1110),
145 .driver_data = ACB_ADAPTER_TYPE_A},
146 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1120),
147 .driver_data = ACB_ADAPTER_TYPE_A},
148 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1130),
149 .driver_data = ACB_ADAPTER_TYPE_A},
150 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1160),
151 .driver_data = ACB_ADAPTER_TYPE_A},
152 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1170),
153 .driver_data = ACB_ADAPTER_TYPE_A},
154 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1200),
155 .driver_data = ACB_ADAPTER_TYPE_B},
156 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1201),
157 .driver_data = ACB_ADAPTER_TYPE_B},
158 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1202),
159 .driver_data = ACB_ADAPTER_TYPE_B},
160 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1210),
161 .driver_data = ACB_ADAPTER_TYPE_A},
5b37479a
CH		 162 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1214),
163 .driver_data = ACB_ADAPTER_TYPE_D},
8b7c9942
CH		 164 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1220),
165 .driver_data = ACB_ADAPTER_TYPE_A},
166 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1230),
167 .driver_data = ACB_ADAPTER_TYPE_A},
168 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1260),
169 .driver_data = ACB_ADAPTER_TYPE_A},
170 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1270),
171 .driver_data = ACB_ADAPTER_TYPE_A},
172 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1280),
173 .driver_data = ACB_ADAPTER_TYPE_A},
174 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1380),
175 .driver_data = ACB_ADAPTER_TYPE_A},
176 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1381),
177 .driver_data = ACB_ADAPTER_TYPE_A},
178 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1680),
179 .driver_data = ACB_ADAPTER_TYPE_A},
180 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1681),
181 .driver_data = ACB_ADAPTER_TYPE_A},
182 {PCI_DEVICE(PCI_VENDOR_ID_ARECA, PCI_DEVICE_ID_ARECA_1880),
183 .driver_data = ACB_ADAPTER_TYPE_C},
1c57e86d
EC		 184 {0, 0}, /* Terminating entry */
185};
186MODULE_DEVICE_TABLE(pci, arcmsr_device_id_table);
8b7c9942 187
1c57e86d
EC		 188static struct pci_driver arcmsr_pci_driver = {
189 .name = "arcmsr",
cdd3cb15 190 .id_table = arcmsr_device_id_table,
1c57e86d
EC		 191 .probe = arcmsr_probe,
192 .remove = arcmsr_remove,
61cda87f
CH		 193 .suspend = arcmsr_suspend,
194 .resume = arcmsr_resume,
a1f6e021 195 .shutdown = arcmsr_shutdown,
1c57e86d 196};
cdd3cb15
NC		 197/*
198****************************************************************************
199****************************************************************************
200*/
1c57e86d 201
626fa32c 202static void arcmsr_free_mu(struct AdapterControlBlock *acb)
ae52e7f0
NC		 203{
204 switch (acb->adapter_type) {
5b37479a
CH		 205 case ACB_ADAPTER_TYPE_B:
206 case ACB_ADAPTER_TYPE_D: {
6e38adfc
CH		 207 dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize,
208 acb->dma_coherent2, acb->dma_coherent_handle2);
209 break;
ae52e7f0
NC		 210 }
211 }
212}
213
214static bool arcmsr_remap_pciregion(struct AdapterControlBlock *acb)
215{
216 struct pci_dev *pdev = acb->pdev;
cdd3cb15 217 switch (acb->adapter_type){
ae52e7f0 218 case ACB_ADAPTER_TYPE_A:{
cdd3cb15 219 acb->pmuA = ioremap(pci_resource_start(pdev,0), pci_resource_len(pdev,0));
ae52e7f0
NC		 220 if (!acb->pmuA) {
221 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
222 return false;
223 }
224 break;
225 }
226 case ACB_ADAPTER_TYPE_B:{
227 void __iomem *mem_base0, *mem_base1;
228 mem_base0 = ioremap(pci_resource_start(pdev, 0), pci_resource_len(pdev, 0));
229 if (!mem_base0) {
230 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
231 return false;
232 }
233 mem_base1 = ioremap(pci_resource_start(pdev, 2), pci_resource_len(pdev, 2));
234 if (!mem_base1) {
235 iounmap(mem_base0);
236 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
237 return false;
238 }
239 acb->mem_base0 = mem_base0;
240 acb->mem_base1 = mem_base1;
cdd3cb15
NC		 241 break;
242 }
243 case ACB_ADAPTER_TYPE_C:{
244 acb->pmuC = ioremap_nocache(pci_resource_start(pdev, 1), pci_resource_len(pdev, 1));
245 if (!acb->pmuC) {
246 printk(KERN_NOTICE "arcmsr%d: memory mapping region fail \n", acb->host->host_no);
247 return false;
248 }
249 if (readl(&acb->pmuC->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
250 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &acb->pmuC->outbound_doorbell_clear);/*clear interrupt*/
251 return true;
252 }
253 break;
ae52e7f0 254 }
5b37479a
CH		 255 case ACB_ADAPTER_TYPE_D: {
256 void __iomem *mem_base0;
257 unsigned long addr, range, flags;
258
259 addr = (unsigned long)pci_resource_start(pdev, 0);
260 range = pci_resource_len(pdev, 0);
261 flags = pci_resource_flags(pdev, 0);
262 if (flags & IORESOURCE_CACHEABLE)
263 mem_base0 = ioremap(addr, range);
264 else
265 mem_base0 = ioremap_nocache(addr, range);
266 if (!mem_base0) {
267 pr_notice("arcmsr%d: memory mapping region fail\n",
268 acb->host->host_no);
269 return false;
270 }
271 acb->mem_base0 = mem_base0;
272 break;
273 }
ae52e7f0
NC		 274 }
275 return true;
276}
277
278static void arcmsr_unmap_pciregion(struct AdapterControlBlock *acb)
279{
280 switch (acb->adapter_type) {
cdd3cb15
NC		 281 case ACB_ADAPTER_TYPE_A:{
282 iounmap(acb->pmuA);
283 }
284 break;
285 case ACB_ADAPTER_TYPE_B:{
286 iounmap(acb->mem_base0);
287 iounmap(acb->mem_base1);
288 }
289
290 break;
291 case ACB_ADAPTER_TYPE_C:{
292 iounmap(acb->pmuC);
293 }
5b37479a
CH		 294 break;
295 case ACB_ADAPTER_TYPE_D:
296 iounmap(acb->mem_base0);
297 break;
ae52e7f0
NC		 298 }
299}
300
7d12e780 301static irqreturn_t arcmsr_do_interrupt(int irq, void *dev_id)
1c57e86d
EC		 302{
303 irqreturn_t handle_state;
1a4f550a 304 struct AdapterControlBlock *acb = dev_id;
1c57e86d 305
1c57e86d 306 handle_state = arcmsr_interrupt(acb);
1c57e86d
EC		 307 return handle_state;
308}
309
310static int arcmsr_bios_param(struct scsi_device *sdev,
311 struct block_device *bdev, sector_t capacity, int *geom)
312{
313 int ret, heads, sectors, cylinders, total_capacity;
314 unsigned char *buffer;/* return copy of block device's partition table */
315
316 buffer = scsi_bios_ptable(bdev);
317 if (buffer) {
318 ret = scsi_partsize(buffer, capacity, &geom[2], &geom[0], &geom[1]);
319 kfree(buffer);
320 if (ret != -1)
321 return ret;
322 }
323 total_capacity = capacity;
324 heads = 64;
325 sectors = 32;
326 cylinders = total_capacity / (heads * sectors);
327 if (cylinders > 1024) {
328 heads = 255;
329 sectors = 63;
330 cylinders = total_capacity / (heads * sectors);
331 }
332 geom[0] = heads;
333 geom[1] = sectors;
334 geom[2] = cylinders;
335 return 0;
336}
337
626fa32c 338static uint8_t arcmsr_hbaA_wait_msgint_ready(struct AdapterControlBlock *acb)
ae52e7f0
NC		 339{
340 struct MessageUnit_A __iomem *reg = acb->pmuA;
8b7eb86f
TH		 341 int i;
342
343 for (i = 0; i < 2000; i++) {
344 if (readl(&reg->outbound_intstatus) &
345 ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
346 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT,
347 &reg->outbound_intstatus);
348 return true;
349 }
350 msleep(10);
351 } /* max 20 seconds */
ae52e7f0 352
cdd3cb15 353 return false;
ae52e7f0
NC		 354}
355
626fa32c 356static uint8_t arcmsr_hbaB_wait_msgint_ready(struct AdapterControlBlock *acb)
1a4f550a 357{
ae52e7f0 358 struct MessageUnit_B *reg = acb->pmuB;
8b7eb86f
TH		 359 int i;
360
361 for (i = 0; i < 2000; i++) {
362 if (readl(reg->iop2drv_doorbell)
363 & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
364 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN,
365 reg->iop2drv_doorbell);
366 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT,
367 reg->drv2iop_doorbell);
368 return true;
369 }
370 msleep(10);
371 } /* max 20 seconds */
ae52e7f0 372
cdd3cb15 373 return false;
ae52e7f0
NC		 374}
375
626fa32c 376static uint8_t arcmsr_hbaC_wait_msgint_ready(struct AdapterControlBlock *pACB)
cdd3cb15 377{
c10b1d54 378 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
8b7eb86f
TH		 379 int i;
380
381 for (i = 0; i < 2000; i++) {
382 if (readl(&phbcmu->outbound_doorbell)
383 & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
384 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR,
385 &phbcmu->outbound_doorbell_clear); /*clear interrupt*/
386 return true;
387 }
388 msleep(10);
389 } /* max 20 seconds */
390
cdd3cb15
NC		 391 return false;
392}
8b7eb86f 393
5b37479a
CH		 394static bool arcmsr_hbaD_wait_msgint_ready(struct AdapterControlBlock *pACB)
395{
396 struct MessageUnit_D *reg = pACB->pmuD;
397 int i;
398
399 for (i = 0; i < 2000; i++) {
400 if (readl(reg->outbound_doorbell)
401 & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
402 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
403 reg->outbound_doorbell);
404 return true;
405 }
406 msleep(10);
407 } /* max 20 seconds */
408 return false;
409}
410
626fa32c 411static void arcmsr_hbaA_flush_cache(struct AdapterControlBlock *acb)
ae52e7f0
NC		 412{
413 struct MessageUnit_A __iomem *reg = acb->pmuA;
414 int retry_count = 30;
ae52e7f0
NC		 415 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
416 do {
626fa32c 417 if (arcmsr_hbaA_wait_msgint_ready(acb))
ae52e7f0
NC		 418 break;
419 else {
420 retry_count--;
421 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
422 timeout, retry count down = %d \n", acb->host->host_no, retry_count);
423 }
424 } while (retry_count != 0);
425}
426
626fa32c 427static void arcmsr_hbaB_flush_cache(struct AdapterControlBlock *acb)
ae52e7f0
NC		 428{
429 struct MessageUnit_B *reg = acb->pmuB;
430 int retry_count = 30;
ae52e7f0
NC		 431 writel(ARCMSR_MESSAGE_FLUSH_CACHE, reg->drv2iop_doorbell);
432 do {
626fa32c 433 if (arcmsr_hbaB_wait_msgint_ready(acb))
ae52e7f0
NC		 434 break;
435 else {
436 retry_count--;
437 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
438 timeout,retry count down = %d \n", acb->host->host_no, retry_count);
439 }
440 } while (retry_count != 0);
441}
442
626fa32c 443static void arcmsr_hbaC_flush_cache(struct AdapterControlBlock *pACB)
cdd3cb15 444{
c10b1d54 445 struct MessageUnit_C __iomem *reg = pACB->pmuC;
cdd3cb15
NC		 446 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
447 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, &reg->inbound_msgaddr0);
448 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
449 do {
626fa32c 450 if (arcmsr_hbaC_wait_msgint_ready(pACB)) {
cdd3cb15
NC		 451 break;
452 } else {
453 retry_count--;
454 printk(KERN_NOTICE "arcmsr%d: wait 'flush adapter cache' \
455 timeout,retry count down = %d \n", pACB->host->host_no, retry_count);
456 }
457 } while (retry_count != 0);
458 return;
459}
5b37479a
CH		 460
461static void arcmsr_hbaD_flush_cache(struct AdapterControlBlock *pACB)
462{
463 int retry_count = 15;
464 struct MessageUnit_D *reg = pACB->pmuD;
465
466 writel(ARCMSR_INBOUND_MESG0_FLUSH_CACHE, reg->inbound_msgaddr0);
467 do {
468 if (arcmsr_hbaD_wait_msgint_ready(pACB))
469 break;
470
471 retry_count--;
472 pr_notice("arcmsr%d: wait 'flush adapter "
473 "cache' timeout, retry count down = %d\n",
474 pACB->host->host_no, retry_count);
475 } while (retry_count != 0);
476}
477
ae52e7f0
NC		 478static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
479{
1a4f550a 480 switch (acb->adapter_type) {
1c57e86d 481
1a4f550a 482 case ACB_ADAPTER_TYPE_A: {
626fa32c 483 arcmsr_hbaA_flush_cache(acb);
ae52e7f0
NC		 484 }
485 break;
1a4f550a 486
ae52e7f0 487 case ACB_ADAPTER_TYPE_B: {
626fa32c 488 arcmsr_hbaB_flush_cache(acb);
1a4f550a 489 }
cdd3cb15
NC		 490 break;
491 case ACB_ADAPTER_TYPE_C: {
626fa32c 492 arcmsr_hbaC_flush_cache(acb);
cdd3cb15 493 }
5b37479a
CH		 494 break;
495 case ACB_ADAPTER_TYPE_D:
496 arcmsr_hbaD_flush_cache(acb);
497 break;
ae52e7f0
NC		 498 }
499}
1a4f550a 500
ae52e7f0
NC		 501static int arcmsr_alloc_ccb_pool(struct AdapterControlBlock *acb)
502{
cdd3cb15
NC		 503 struct pci_dev *pdev = acb->pdev;
504 void *dma_coherent;
505 dma_addr_t dma_coherent_handle;
506 struct CommandControlBlock *ccb_tmp;
507 int i = 0, j = 0;
508 dma_addr_t cdb_phyaddr;
87f76152 509 unsigned long roundup_ccbsize;
cdd3cb15
NC		 510 unsigned long max_xfer_len;
511 unsigned long max_sg_entrys;
512 uint32_t firm_config_version;
87f76152 513
cdd3cb15
NC		 514 for (i = 0; i < ARCMSR_MAX_TARGETID; i++)
515 for (j = 0; j < ARCMSR_MAX_TARGETLUN; j++)
516 acb->devstate[i][j] = ARECA_RAID_GONE;
517
518 max_xfer_len = ARCMSR_MAX_XFER_LEN;
519 max_sg_entrys = ARCMSR_DEFAULT_SG_ENTRIES;
520 firm_config_version = acb->firm_cfg_version;
521 if((firm_config_version & 0xFF) >= 3){
522 max_xfer_len = (ARCMSR_CDB_SG_PAGE_LENGTH << ((firm_config_version >> 8) & 0xFF)) * 1024;/* max 4M byte */
87f76152 523 max_sg_entrys = (max_xfer_len/4096);
cdd3cb15
NC		 524 }
525 acb->host->max_sectors = max_xfer_len/512;
526 acb->host->sg_tablesize = max_sg_entrys;
527 roundup_ccbsize = roundup(sizeof(struct CommandControlBlock) + (max_sg_entrys - 1) * sizeof(struct SG64ENTRY), 32);
87f76152 528 acb->uncache_size = roundup_ccbsize * ARCMSR_MAX_FREECCB_NUM;
cdd3cb15
NC		 529 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->uncache_size, &dma_coherent_handle, GFP_KERNEL);
530 if(!dma_coherent){
87f76152 531 printk(KERN_NOTICE "arcmsr%d: dma_alloc_coherent got error\n", acb->host->host_no);
cdd3cb15
NC		 532 return -ENOMEM;
533 }
534 acb->dma_coherent = dma_coherent;
535 acb->dma_coherent_handle = dma_coherent_handle;
536 memset(dma_coherent, 0, acb->uncache_size);
cdd3cb15
NC		 537 ccb_tmp = dma_coherent;
538 acb->vir2phy_offset = (unsigned long)dma_coherent - (unsigned long)dma_coherent_handle;
539 for(i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++){
540 cdb_phyaddr = dma_coherent_handle + offsetof(struct CommandControlBlock, arcmsr_cdb);
5b37479a
CH		 541 switch (acb->adapter_type) {
542 case ACB_ADAPTER_TYPE_A:
543 case ACB_ADAPTER_TYPE_B:
544 ccb_tmp->cdb_phyaddr = cdb_phyaddr >> 5;
545 break;
546 case ACB_ADAPTER_TYPE_C:
547 case ACB_ADAPTER_TYPE_D:
548 ccb_tmp->cdb_phyaddr = cdb_phyaddr;
549 break;
550 }
cdd3cb15
NC		 551 acb->pccb_pool[i] = ccb_tmp;
552 ccb_tmp->acb = acb;
553 INIT_LIST_HEAD(&ccb_tmp->list);
554 list_add_tail(&ccb_tmp->list, &acb->ccb_free_list);
555 ccb_tmp = (struct CommandControlBlock *)((unsigned long)ccb_tmp + roundup_ccbsize);
556 dma_coherent_handle = dma_coherent_handle + roundup_ccbsize;
1a4f550a 557 }
1c57e86d
EC		 558 return 0;
559}
36b83ded 560
cdd3cb15
NC		 561static void arcmsr_message_isr_bh_fn(struct work_struct *work)
562{
12aad947
CH		 563 struct AdapterControlBlock *acb = container_of(work,
564 struct AdapterControlBlock, arcmsr_do_message_isr_bh);
565 char *acb_dev_map = (char *)acb->device_map;
566 uint32_t __iomem *signature = NULL;
567 char __iomem *devicemap = NULL;
568 int target, lun;
569 struct scsi_device *psdev;
570 char diff, temp;
571
36b83ded 572 switch (acb->adapter_type) {
12aad947
CH		 573 case ACB_ADAPTER_TYPE_A: {
574 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 575
12aad947
CH		 576 signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
577 devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
cdd3cb15 578 break;
12aad947
CH		 579 }
580 case ACB_ADAPTER_TYPE_B: {
581 struct MessageUnit_B *reg = acb->pmuB;
582
583 signature = (uint32_t __iomem *)(&reg->message_rwbuffer[0]);
584 devicemap = (char __iomem *)(&reg->message_rwbuffer[21]);
585 break;
586 }
587 case ACB_ADAPTER_TYPE_C: {
588 struct MessageUnit_C __iomem *reg = acb->pmuC;
589
590 signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
591 devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
592 break;
593 }
5b37479a
CH		 594 case ACB_ADAPTER_TYPE_D: {
595 struct MessageUnit_D *reg = acb->pmuD;
596
597 signature = (uint32_t __iomem *)(&reg->msgcode_rwbuffer[0]);
598 devicemap = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
599 break;
600 }
12aad947
CH		 601 }
602 atomic_inc(&acb->rq_map_token);
603 if (readl(signature) != ARCMSR_SIGNATURE_GET_CONFIG)
604 return;
605 for (target = 0; target < ARCMSR_MAX_TARGETID - 1;
606 target++) {
607 temp = readb(devicemap);
608 diff = (*acb_dev_map) ^ temp;
609 if (diff != 0) {
610 *acb_dev_map = temp;
611 for (lun = 0; lun < ARCMSR_MAX_TARGETLUN;
612 lun++) {
613 if ((diff & 0x01) == 1 &&
614 (temp & 0x01) == 1) {
615 scsi_add_device(acb->host,
616 0, target, lun);
617 } else if ((diff & 0x01) == 1
618 && (temp & 0x01) == 0) {
619 psdev = scsi_device_lookup(acb->host,
620 0, target, lun);
621 if (psdev != NULL) {
622 scsi_remove_device(psdev);
623 scsi_device_put(psdev);
36b83ded 624 }
36b83ded 625 }
12aad947
CH		 626 temp >>= 1;
627 diff >>= 1;
36b83ded
NC		 628 }
629 }
12aad947
CH		 630 devicemap++;
631 acb_dev_map++;
36b83ded
NC		 632 }
633}
1c57e86d 634
1d1166ea
CH		 635static int
636arcmsr_request_irq(struct pci_dev *pdev, struct AdapterControlBlock *acb)
637{
638 int i, j, r;
639 struct msix_entry entries[ARCMST_NUM_MSIX_VECTORS];
640
641 for (i = 0; i < ARCMST_NUM_MSIX_VECTORS; i++)
642 entries[i].entry = i;
643 r = pci_enable_msix_range(pdev, entries, 1, ARCMST_NUM_MSIX_VECTORS);
644 if (r < 0)
645 goto msi_int;
646 acb->msix_vector_count = r;
647 for (i = 0; i < r; i++) {
648 if (request_irq(entries[i].vector,
649 arcmsr_do_interrupt, 0, "arcmsr", acb)) {
650 pr_warn("arcmsr%d: request_irq =%d failed!\n",
651 acb->host->host_no, entries[i].vector);
652 for (j = 0 ; j < i ; j++)
653 free_irq(entries[j].vector, acb);
654 pci_disable_msix(pdev);
655 goto msi_int;
656 }
657 acb->entries[i] = entries[i];
658 }
659 acb->acb_flags |= ACB_F_MSIX_ENABLED;
660 pr_info("arcmsr%d: msi-x enabled\n", acb->host->host_no);
661 return SUCCESS;
662msi_int:
663 if (pci_enable_msi_exact(pdev, 1) < 0)
664 goto legacy_int;
665 if (request_irq(pdev->irq, arcmsr_do_interrupt,
666 IRQF_SHARED, "arcmsr", acb)) {
667 pr_warn("arcmsr%d: request_irq =%d failed!\n",
668 acb->host->host_no, pdev->irq);
669 pci_disable_msi(pdev);
670 goto legacy_int;
671 }
672 acb->acb_flags |= ACB_F_MSI_ENABLED;
673 pr_info("arcmsr%d: msi enabled\n", acb->host->host_no);
674 return SUCCESS;
675legacy_int:
676 if (request_irq(pdev->irq, arcmsr_do_interrupt,
677 IRQF_SHARED, "arcmsr", acb)) {
678 pr_warn("arcmsr%d: request_irq = %d failed!\n",
679 acb->host->host_no, pdev->irq);
680 return FAILED;
681 }
682 return SUCCESS;
683}
684
ae52e7f0 685static int arcmsr_probe(struct pci_dev *pdev, const struct pci_device_id *id)
1c57e86d
EC		 686{
687 struct Scsi_Host *host;
688 struct AdapterControlBlock *acb;
cdd3cb15 689 uint8_t bus,dev_fun;
1c57e86d 690 int error;
1c57e86d 691 error = pci_enable_device(pdev);
cdd3cb15 692 if(error){
ae52e7f0
NC		 693 return -ENODEV;
694 }
695 host = scsi_host_alloc(&arcmsr_scsi_host_template, sizeof(struct AdapterControlBlock));
cdd3cb15
NC		 696 if(!host){
697 goto pci_disable_dev;
1c57e86d 698 }
6a35528a 699 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
cdd3cb15 700 if(error){
284901a9 701 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
cdd3cb15 702 if(error){
1c57e86d
EC		 703 printk(KERN_WARNING
704 "scsi%d: No suitable DMA mask available\n",
705 host->host_no);
ae52e7f0 706 goto scsi_host_release;
1c57e86d
EC		 707 }
708 }
ae52e7f0 709 init_waitqueue_head(&wait_q);
1c57e86d
EC		 710 bus = pdev->bus->number;
711 dev_fun = pdev->devfn;
ae52e7f0 712 acb = (struct AdapterControlBlock *) host->hostdata;
cdd3cb15 713 memset(acb,0,sizeof(struct AdapterControlBlock));
1c57e86d 714 acb->pdev = pdev;
ae52e7f0 715 acb->host = host;
1c57e86d 716 host->max_lun = ARCMSR_MAX_TARGETLUN;
cdd3cb15
NC		 717 host->max_id = ARCMSR_MAX_TARGETID; /*16:8*/
718 host->max_cmd_len = 16; /*this is issue of 64bit LBA ,over 2T byte*/
3df824af 719 host->can_queue = ARCMSR_MAX_OUTSTANDING_CMD;
cdd3cb15 720 host->cmd_per_lun = ARCMSR_MAX_CMD_PERLUN;
1c57e86d
EC		 721 host->this_id = ARCMSR_SCSI_INITIATOR_ID;
722 host->unique_id = (bus << 8) | dev_fun;
ae52e7f0
NC		 723 pci_set_drvdata(pdev, host);
724 pci_set_master(pdev);
1c57e86d 725 error = pci_request_regions(pdev, "arcmsr");
cdd3cb15 726 if(error){
ae52e7f0 727 goto scsi_host_release;
1c57e86d 728 }
ae52e7f0
NC		 729 spin_lock_init(&acb->eh_lock);
730 spin_lock_init(&acb->ccblist_lock);
5b37479a
CH		 731 spin_lock_init(&acb->postq_lock);
732 spin_lock_init(&acb->doneq_lock);
bb263c4e
CH		 733 spin_lock_init(&acb->rqbuffer_lock);
734 spin_lock_init(&acb->wqbuffer_lock);
1c57e86d 735 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
cdd3cb15
NC		 736 ACB_F_MESSAGE_RQBUFFER_CLEARED |
737 ACB_F_MESSAGE_WQBUFFER_READED);
1c57e86d
EC		 738 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
739 INIT_LIST_HEAD(&acb->ccb_free_list);
8b7c9942 740 acb->adapter_type = id->driver_data;
ae52e7f0 741 error = arcmsr_remap_pciregion(acb);
cdd3cb15 742 if(!error){
ae52e7f0
NC		 743 goto pci_release_regs;
744 }
745 error = arcmsr_get_firmware_spec(acb);
cdd3cb15 746 if(!error){
ae52e7f0
NC		 747 goto unmap_pci_region;
748 }
1c57e86d 749 error = arcmsr_alloc_ccb_pool(acb);
cdd3cb15 750 if(error){
ae52e7f0
NC		 751 goto free_hbb_mu;
752 }
1c57e86d 753 error = scsi_add_host(host, &pdev->dev);
cdd3cb15 754 if(error){
b4eb6ae9 755 goto free_ccb_pool;
ae52e7f0 756 }
1d1166ea 757 if (arcmsr_request_irq(pdev, acb) == FAILED)
ae52e7f0 758 goto scsi_host_remove;
1d1166ea 759 arcmsr_iop_init(acb);
ae52e7f0 760 INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
36b83ded 761 atomic_set(&acb->rq_map_token, 16);
ae52e7f0
NC		 762 atomic_set(&acb->ante_token_value, 16);
763 acb->fw_flag = FW_NORMAL;
36b83ded 764 init_timer(&acb->eternal_timer);
ae52e7f0 765 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
36b83ded
NC		 766 acb->eternal_timer.data = (unsigned long) acb;
767 acb->eternal_timer.function = &arcmsr_request_device_map;
768 add_timer(&acb->eternal_timer);
cdd3cb15 769 if(arcmsr_alloc_sysfs_attr(acb))
ae52e7f0 770 goto out_free_sysfs;
b4eb6ae9 771 scsi_scan_host(host);
1c57e86d 772 return 0;
cdd3cb15 773out_free_sysfs:
b4eb6ae9
CH		 774 del_timer_sync(&acb->eternal_timer);
775 flush_work(&acb->arcmsr_do_message_isr_bh);
ae52e7f0
NC		 776 arcmsr_stop_adapter_bgrb(acb);
777 arcmsr_flush_adapter_cache(acb);
b4eb6ae9
CH		 778 arcmsr_free_irq(pdev, acb);
779scsi_host_remove:
780 scsi_remove_host(host);
781free_ccb_pool:
1c57e86d 782 arcmsr_free_ccb_pool(acb);
ae52e7f0 783free_hbb_mu:
626fa32c 784 arcmsr_free_mu(acb);
ae52e7f0
NC		 785unmap_pci_region:
786 arcmsr_unmap_pciregion(acb);
787pci_release_regs:
1c57e86d 788 pci_release_regions(pdev);
ae52e7f0 789scsi_host_release:
1c57e86d 790 scsi_host_put(host);
ae52e7f0 791pci_disable_dev:
1c57e86d 792 pci_disable_device(pdev);
ae52e7f0 793 return -ENODEV;
1a4f550a
NC		 794}
795
1d1166ea
CH		 796static void arcmsr_free_irq(struct pci_dev *pdev,
797 struct AdapterControlBlock *acb)
798{
799 int i;
800
801 if (acb->acb_flags & ACB_F_MSI_ENABLED) {
802 free_irq(pdev->irq, acb);
803 pci_disable_msi(pdev);
804 } else if (acb->acb_flags & ACB_F_MSIX_ENABLED) {
805 for (i = 0; i < acb->msix_vector_count; i++)
806 free_irq(acb->entries[i].vector, acb);
807 pci_disable_msix(pdev);
808 } else
809 free_irq(pdev->irq, acb);
810}
811
61cda87f
CH		 812static int arcmsr_suspend(struct pci_dev *pdev, pm_message_t state)
813{
814 uint32_t intmask_org;
815 struct Scsi_Host *host = pci_get_drvdata(pdev);
816 struct AdapterControlBlock *acb =
817 (struct AdapterControlBlock *)host->hostdata;
818
819 intmask_org = arcmsr_disable_outbound_ints(acb);
820 arcmsr_free_irq(pdev, acb);
821 del_timer_sync(&acb->eternal_timer);
822 flush_work(&acb->arcmsr_do_message_isr_bh);
823 arcmsr_stop_adapter_bgrb(acb);
824 arcmsr_flush_adapter_cache(acb);
825 pci_set_drvdata(pdev, host);
826 pci_save_state(pdev);
827 pci_disable_device(pdev);
828 pci_set_power_state(pdev, pci_choose_state(pdev, state));
829 return 0;
830}
831
832static int arcmsr_resume(struct pci_dev *pdev)
833{
834 int error;
835 struct Scsi_Host *host = pci_get_drvdata(pdev);
836 struct AdapterControlBlock *acb =
837 (struct AdapterControlBlock *)host->hostdata;
838
839 pci_set_power_state(pdev, PCI_D0);
840 pci_enable_wake(pdev, PCI_D0, 0);
841 pci_restore_state(pdev);
842 if (pci_enable_device(pdev)) {
843 pr_warn("%s: pci_enable_device error\n", __func__);
844 return -ENODEV;
845 }
846 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
847 if (error) {
848 error = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
849 if (error) {
850 pr_warn("scsi%d: No suitable DMA mask available\n",
851 host->host_no);
852 goto controller_unregister;
853 }
854 }
855 pci_set_master(pdev);
856 if (arcmsr_request_irq(pdev, acb) == FAILED)
857 goto controller_stop;
858 arcmsr_iop_init(acb);
859 INIT_WORK(&acb->arcmsr_do_message_isr_bh, arcmsr_message_isr_bh_fn);
860 atomic_set(&acb->rq_map_token, 16);
861 atomic_set(&acb->ante_token_value, 16);
862 acb->fw_flag = FW_NORMAL;
863 init_timer(&acb->eternal_timer);
864 acb->eternal_timer.expires = jiffies + msecs_to_jiffies(6 * HZ);
865 acb->eternal_timer.data = (unsigned long) acb;
866 acb->eternal_timer.function = &arcmsr_request_device_map;
867 add_timer(&acb->eternal_timer);
868 return 0;
869controller_stop:
870 arcmsr_stop_adapter_bgrb(acb);
871 arcmsr_flush_adapter_cache(acb);
872controller_unregister:
873 scsi_remove_host(host);
874 arcmsr_free_ccb_pool(acb);
875 arcmsr_unmap_pciregion(acb);
876 pci_release_regions(pdev);
877 scsi_host_put(host);
878 pci_disable_device(pdev);
879 return -ENODEV;
880}
881
626fa32c 882static uint8_t arcmsr_hbaA_abort_allcmd(struct AdapterControlBlock *acb)
1c57e86d 883{
80da1adb 884 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 885 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
626fa32c 886 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1a4f550a 887 printk(KERN_NOTICE
626fa32c 888 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
1a4f550a 889 , acb->host->host_no);
cdd3cb15 890 return false;
36b83ded 891 }
cdd3cb15 892 return true;
1a4f550a
NC		 893}
894
626fa32c 895static uint8_t arcmsr_hbaB_abort_allcmd(struct AdapterControlBlock *acb)
1a4f550a 896{
80da1adb 897 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 898
ae52e7f0 899 writel(ARCMSR_MESSAGE_ABORT_CMD, reg->drv2iop_doorbell);
626fa32c 900 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1c57e86d 901 printk(KERN_NOTICE
626fa32c 902 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
1c57e86d 903 , acb->host->host_no);
cdd3cb15 904 return false;
36b83ded 905 }
cdd3cb15
NC		 906 return true;
907}
626fa32c 908static uint8_t arcmsr_hbaC_abort_allcmd(struct AdapterControlBlock *pACB)
cdd3cb15 909{
c10b1d54 910 struct MessageUnit_C __iomem *reg = pACB->pmuC;
cdd3cb15
NC		 911 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, &reg->inbound_msgaddr0);
912 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
626fa32c 913 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
cdd3cb15 914 printk(KERN_NOTICE
626fa32c 915 "arcmsr%d: wait 'abort all outstanding command' timeout\n"
cdd3cb15
NC		 916 , pACB->host->host_no);
917 return false;
918 }
919 return true;
1c57e86d 920}
5b37479a
CH		 921
922static uint8_t arcmsr_hbaD_abort_allcmd(struct AdapterControlBlock *pACB)
923{
924 struct MessageUnit_D *reg = pACB->pmuD;
925
926 writel(ARCMSR_INBOUND_MESG0_ABORT_CMD, reg->inbound_msgaddr0);
927 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
928 pr_notice("arcmsr%d: wait 'abort all outstanding "
929 "command' timeout\n", pACB->host->host_no);
930 return false;
931 }
932 return true;
933}
934
36b83ded 935static uint8_t arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
1a4f550a 936{
36b83ded 937 uint8_t rtnval = 0;
1a4f550a
NC		 938 switch (acb->adapter_type) {
939 case ACB_ADAPTER_TYPE_A: {
626fa32c 940 rtnval = arcmsr_hbaA_abort_allcmd(acb);
1a4f550a
NC		 941 }
942 break;
943
944 case ACB_ADAPTER_TYPE_B: {
626fa32c 945 rtnval = arcmsr_hbaB_abort_allcmd(acb);
1a4f550a 946 }
cdd3cb15
NC		 947 break;
948
949 case ACB_ADAPTER_TYPE_C: {
626fa32c 950 rtnval = arcmsr_hbaC_abort_allcmd(acb);
cdd3cb15 951 }
5b37479a
CH		 952 break;
953
954 case ACB_ADAPTER_TYPE_D:
955 rtnval = arcmsr_hbaD_abort_allcmd(acb);
956 break;
1a4f550a 957 }
36b83ded 958 return rtnval;
1a4f550a
NC		 959}
960
1c57e86d
EC		 961static void arcmsr_pci_unmap_dma(struct CommandControlBlock *ccb)
962{
1c57e86d
EC		 963 struct scsi_cmnd *pcmd = ccb->pcmd;
964
deff2627 965 scsi_dma_unmap(pcmd);
cdd3cb15 966}
1c57e86d 967
ae52e7f0 968static void arcmsr_ccb_complete(struct CommandControlBlock *ccb)
1c57e86d
EC		 969{
970 struct AdapterControlBlock *acb = ccb->acb;
971 struct scsi_cmnd *pcmd = ccb->pcmd;
ae52e7f0 972 unsigned long flags;
ae52e7f0 973 atomic_dec(&acb->ccboutstandingcount);
1c57e86d 974 arcmsr_pci_unmap_dma(ccb);
1c57e86d 975 ccb->startdone = ARCMSR_CCB_DONE;
ae52e7f0 976 spin_lock_irqsave(&acb->ccblist_lock, flags);
1c57e86d 977 list_add_tail(&ccb->list, &acb->ccb_free_list);
ae52e7f0 978 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 979 pcmd->scsi_done(pcmd);
980}
981
1a4f550a
NC		 982static void arcmsr_report_sense_info(struct CommandControlBlock *ccb)
983{
984
985 struct scsi_cmnd *pcmd = ccb->pcmd;
986 struct SENSE_DATA *sensebuffer = (struct SENSE_DATA *)pcmd->sense_buffer;
1a4f550a
NC		 987 pcmd->result = DID_OK << 16;
988 if (sensebuffer) {
989 int sense_data_length =
b80ca4f7
FT		 990 sizeof(struct SENSE_DATA) < SCSI_SENSE_BUFFERSIZE
991 ? sizeof(struct SENSE_DATA) : SCSI_SENSE_BUFFERSIZE;
992 memset(sensebuffer, 0, SCSI_SENSE_BUFFERSIZE);
1a4f550a
NC		 993 memcpy(sensebuffer, ccb->arcmsr_cdb.SenseData, sense_data_length);
994 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
995 sensebuffer->Valid = 1;
996 }
997}
998
999static u32 arcmsr_disable_outbound_ints(struct AdapterControlBlock *acb)
1000{
1001 u32 orig_mask = 0;
cdd3cb15 1002 switch (acb->adapter_type) {
1a4f550a 1003 case ACB_ADAPTER_TYPE_A : {
80da1adb 1004 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 1005 orig_mask = readl(&reg->outbound_intmask);
1a4f550a
NC		 1006 writel(orig_mask|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE, \
1007 &reg->outbound_intmask);
1008 }
1009 break;
1a4f550a 1010 case ACB_ADAPTER_TYPE_B : {
80da1adb 1011 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0
NC		 1012 orig_mask = readl(reg->iop2drv_doorbell_mask);
1013 writel(0, reg->iop2drv_doorbell_mask);
1a4f550a
NC		 1014 }
1015 break;
cdd3cb15 1016 case ACB_ADAPTER_TYPE_C:{
c10b1d54 1017 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15
NC		 1018 /* disable all outbound interrupt */
1019 orig_mask = readl(&reg->host_int_mask); /* disable outbound message0 int */
1020 writel(orig_mask|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
1021 }
1022 break;
5b37479a
CH		 1023 case ACB_ADAPTER_TYPE_D: {
1024 struct MessageUnit_D *reg = acb->pmuD;
1025 /* disable all outbound interrupt */
1026 writel(ARCMSR_ARC1214_ALL_INT_DISABLE, reg->pcief0_int_enable);
1027 }
1028 break;
1a4f550a
NC		 1029 }
1030 return orig_mask;
1031}
1032
cdd3cb15
NC		 1033static void arcmsr_report_ccb_state(struct AdapterControlBlock *acb,
1034 struct CommandControlBlock *ccb, bool error)
1a4f550a 1035{
1a4f550a
NC		 1036 uint8_t id, lun;
1037 id = ccb->pcmd->device->id;
1038 lun = ccb->pcmd->device->lun;
cdd3cb15 1039 if (!error) {
1a4f550a
NC		 1040 if (acb->devstate[id][lun] == ARECA_RAID_GONE)
1041 acb->devstate[id][lun] = ARECA_RAID_GOOD;
7968f194
JL		 1042 ccb->pcmd->result = DID_OK << 16;
1043 arcmsr_ccb_complete(ccb);
cdd3cb15 1044 }else{
1a4f550a
NC		 1045 switch (ccb->arcmsr_cdb.DeviceStatus) {
1046 case ARCMSR_DEV_SELECT_TIMEOUT: {
1047 acb->devstate[id][lun] = ARECA_RAID_GONE;
1048 ccb->pcmd->result = DID_NO_CONNECT << 16;
ae52e7f0 1049 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 1050 }
1051 break;
1052
1053 case ARCMSR_DEV_ABORTED:
1054
1055 case ARCMSR_DEV_INIT_FAIL: {
1056 acb->devstate[id][lun] = ARECA_RAID_GONE;
1057 ccb->pcmd->result = DID_BAD_TARGET << 16;
ae52e7f0 1058 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 1059 }
1060 break;
1061
1062 case ARCMSR_DEV_CHECK_CONDITION: {
1063 acb->devstate[id][lun] = ARECA_RAID_GOOD;
1064 arcmsr_report_sense_info(ccb);
ae52e7f0 1065 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 1066 }
1067 break;
1068
1069 default:
cdd3cb15
NC		 1070 printk(KERN_NOTICE
1071 "arcmsr%d: scsi id = %d lun = %d isr get command error done, \
1072 but got unknown DeviceStatus = 0x%x \n"
1073 , acb->host->host_no
1074 , id
1075 , lun
1076 , ccb->arcmsr_cdb.DeviceStatus);
1077 acb->devstate[id][lun] = ARECA_RAID_GONE;
1078 ccb->pcmd->result = DID_NO_CONNECT << 16;
1079 arcmsr_ccb_complete(ccb);
1a4f550a
NC		 1080 break;
1081 }
1082 }
1083}
1084
cdd3cb15 1085static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, struct CommandControlBlock *pCCB, bool error)
1a4f550a 1086{
ae52e7f0 1087 int id, lun;
cdd3cb15
NC		 1088 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
1089 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
1090 struct scsi_cmnd *abortcmd = pCCB->pcmd;
1a4f550a 1091 if (abortcmd) {
ae52e7f0 1092 id = abortcmd->device->id;
cdd3cb15 1093 lun = abortcmd->device->lun;
1a4f550a 1094 abortcmd->result |= DID_ABORT << 16;
cdd3cb15
NC		 1095 arcmsr_ccb_complete(pCCB);
1096 printk(KERN_NOTICE "arcmsr%d: pCCB ='0x%p' isr got aborted command \n",
1097 acb->host->host_no, pCCB);
1a4f550a 1098 }
cdd3cb15 1099 return;
1a4f550a
NC		 1100 }
1101 printk(KERN_NOTICE "arcmsr%d: isr get an illegal ccb command \
1102 done acb = '0x%p'"
1103 "ccb = '0x%p' ccbacb = '0x%p' startdone = 0x%x"
1104 " ccboutstandingcount = %d \n"
1105 , acb->host->host_no
1106 , acb
cdd3cb15
NC		 1107 , pCCB
1108 , pCCB->acb
1109 , pCCB->startdone
1a4f550a 1110 , atomic_read(&acb->ccboutstandingcount));
cdd3cb15 1111 return;
97b99127 1112 }
cdd3cb15 1113 arcmsr_report_ccb_state(acb, pCCB, error);
1a4f550a
NC		 1114}
1115
1116static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
1117{
1118 int i = 0;
3b8155d5 1119 uint32_t flag_ccb, ccb_cdb_phy;
cdd3cb15
NC		 1120 struct ARCMSR_CDB *pARCMSR_CDB;
1121 bool error;
1122 struct CommandControlBlock *pCCB;
1a4f550a
NC		 1123 switch (acb->adapter_type) {
1124
1125 case ACB_ADAPTER_TYPE_A: {
80da1adb 1126 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 1127 uint32_t outbound_intstatus;
80da1adb 1128 outbound_intstatus = readl(&reg->outbound_intstatus) &
1a4f550a
NC		 1129 acb->outbound_int_enable;
1130 /*clear and abort all outbound posted Q*/
1131 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
cdd3cb15 1132 while(((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF)
1a4f550a 1133 && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
cdd3cb15
NC		 1134 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
1135 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1136 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1137 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 1138 }
1139 }
1140 break;
1141
1142 case ACB_ADAPTER_TYPE_B: {
80da1adb 1143 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1144 /*clear all outbound posted Q*/
97b99127 1145 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell); /* clear doorbell interrupt */
1a4f550a 1146 for (i = 0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
c10b1d54
CH		 1147 flag_ccb = reg->done_qbuffer[i];
1148 if (flag_ccb != 0) {
1149 reg->done_qbuffer[i] = 0;
cdd3cb15
NC		 1150 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
1151 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1152 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1153 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a 1154 }
cdd3cb15 1155 reg->post_qbuffer[i] = 0;
1a4f550a
NC		 1156 }
1157 reg->doneq_index = 0;
1158 reg->postq_index = 0;
1159 }
1160 break;
cdd3cb15 1161 case ACB_ADAPTER_TYPE_C: {
c10b1d54 1162 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15
NC		 1163 while ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
1164 /*need to do*/
1165 flag_ccb = readl(&reg->outbound_queueport_low);
1166 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
1167 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+ccb_cdb_phy);/*frame must be 32 bytes aligned*/
1168 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1169 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
1170 arcmsr_drain_donequeue(acb, pCCB, error);
1171 }
5b37479a
CH		 1172 }
1173 break;
1174 case ACB_ADAPTER_TYPE_D: {
1175 struct MessageUnit_D *pmu = acb->pmuD;
3b8155d5
CH		 1176 uint32_t outbound_write_pointer;
1177 uint32_t doneq_index, index_stripped, addressLow, residual, toggle;
1178 unsigned long flags;
5b37479a 1179
5b37479a
CH		 1180 residual = atomic_read(&acb->ccboutstandingcount);
1181 for (i = 0; i < residual; i++) {
3b8155d5
CH		 1182 spin_lock_irqsave(&acb->doneq_lock, flags);
1183 outbound_write_pointer =
1184 pmu->done_qbuffer[0].addressLow + 1;
1185 doneq_index = pmu->doneq_index;
1186 if ((doneq_index & 0xFFF) !=
5b37479a 1187 (outbound_write_pointer & 0xFFF)) {
3b8155d5
CH		 1188 toggle = doneq_index & 0x4000;
1189 index_stripped = (doneq_index & 0xFFF) + 1;
1190 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
1191 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
1192 ((toggle ^ 0x4000) + 1);
5b37479a 1193 doneq_index = pmu->doneq_index;
3b8155d5 1194 spin_unlock_irqrestore(&acb->doneq_lock, flags);
5b37479a
CH		 1195 addressLow = pmu->done_qbuffer[doneq_index &
1196 0xFFF].addressLow;
1197 ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
1198 pARCMSR_CDB = (struct ARCMSR_CDB *)
1199 (acb->vir2phy_offset + ccb_cdb_phy);
1200 pCCB = container_of(pARCMSR_CDB,
1201 struct CommandControlBlock, arcmsr_cdb);
1202 error = (addressLow &
1203 ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ?
1204 true : false;
1205 arcmsr_drain_donequeue(acb, pCCB, error);
1206 writel(doneq_index,
1207 pmu->outboundlist_read_pointer);
3b8155d5
CH		 1208 } else {
1209 spin_unlock_irqrestore(&acb->doneq_lock, flags);
1210 mdelay(10);
5b37479a 1211 }
5b37479a
CH		 1212 }
1213 pmu->postq_index = 0;
1214 pmu->doneq_index = 0x40FF;
1215 }
1216 break;
1a4f550a
NC		 1217 }
1218}
1d1166ea 1219
1c57e86d
EC		 1220static void arcmsr_remove(struct pci_dev *pdev)
1221{
1222 struct Scsi_Host *host = pci_get_drvdata(pdev);
1223 struct AdapterControlBlock *acb =
1224 (struct AdapterControlBlock *) host->hostdata;
1c57e86d 1225 int poll_count = 0;
1c57e86d
EC		 1226 arcmsr_free_sysfs_attr(acb);
1227 scsi_remove_host(host);
43829731 1228 flush_work(&acb->arcmsr_do_message_isr_bh);
36b83ded
NC		 1229 del_timer_sync(&acb->eternal_timer);
1230 arcmsr_disable_outbound_ints(acb);
1c57e86d 1231 arcmsr_stop_adapter_bgrb(acb);
cdd3cb15 1232 arcmsr_flush_adapter_cache(acb);
1c57e86d
EC		 1233 acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
1234 acb->acb_flags &= ~ACB_F_IOP_INITED;
1235
cdd3cb15 1236 for (poll_count = 0; poll_count < ARCMSR_MAX_OUTSTANDING_CMD; poll_count++){
1c57e86d
EC		 1237 if (!atomic_read(&acb->ccboutstandingcount))
1238 break;
1a4f550a 1239 arcmsr_interrupt(acb);/* FIXME: need spinlock */
1c57e86d
EC		 1240 msleep(25);
1241 }
1242
1243 if (atomic_read(&acb->ccboutstandingcount)) {
1244 int i;
1245
1246 arcmsr_abort_allcmd(acb);
1a4f550a 1247 arcmsr_done4abort_postqueue(acb);
1c57e86d
EC		 1248 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
1249 struct CommandControlBlock *ccb = acb->pccb_pool[i];
1250 if (ccb->startdone == ARCMSR_CCB_START) {
1251 ccb->startdone = ARCMSR_CCB_ABORTED;
1252 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 1253 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 1254 }
1255 }
1256 }
1d1166ea 1257 arcmsr_free_irq(pdev, acb);
1c57e86d 1258 arcmsr_free_ccb_pool(acb);
626fa32c 1259 arcmsr_free_mu(acb);
cdd3cb15 1260 arcmsr_unmap_pciregion(acb);
1c57e86d 1261 pci_release_regions(pdev);
cdd3cb15 1262 scsi_host_put(host);
1c57e86d 1263 pci_disable_device(pdev);
1c57e86d
EC		 1264}
1265
1266static void arcmsr_shutdown(struct pci_dev *pdev)
1267{
1268 struct Scsi_Host *host = pci_get_drvdata(pdev);
1269 struct AdapterControlBlock *acb =
1270 (struct AdapterControlBlock *)host->hostdata;
36b83ded
NC		 1271 del_timer_sync(&acb->eternal_timer);
1272 arcmsr_disable_outbound_ints(acb);
1d1166ea 1273 arcmsr_free_irq(pdev, acb);
43829731 1274 flush_work(&acb->arcmsr_do_message_isr_bh);
1c57e86d
EC		 1275 arcmsr_stop_adapter_bgrb(acb);
1276 arcmsr_flush_adapter_cache(acb);
1277}
1278
1279static int arcmsr_module_init(void)
1280{
1281 int error = 0;
1c57e86d
EC		 1282 error = pci_register_driver(&arcmsr_pci_driver);
1283 return error;
1284}
1285
1286static void arcmsr_module_exit(void)
1287{
1288 pci_unregister_driver(&arcmsr_pci_driver);
1289}
1290module_init(arcmsr_module_init);
1291module_exit(arcmsr_module_exit);
1292
36b83ded 1293static void arcmsr_enable_outbound_ints(struct AdapterControlBlock *acb,
1a4f550a 1294 u32 intmask_org)
1c57e86d 1295{
1c57e86d 1296 u32 mask;
1a4f550a 1297 switch (acb->adapter_type) {
1c57e86d 1298
cdd3cb15 1299 case ACB_ADAPTER_TYPE_A: {
80da1adb 1300 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 1301 mask = intmask_org & ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE |
36b83ded
NC		 1302 ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|
1303 ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
1a4f550a
NC		 1304 writel(mask, &reg->outbound_intmask);
1305 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
1306 }
1307 break;
1c57e86d 1308
cdd3cb15 1309 case ACB_ADAPTER_TYPE_B: {
80da1adb 1310 struct MessageUnit_B *reg = acb->pmuB;
36b83ded
NC		 1311 mask = intmask_org | (ARCMSR_IOP2DRV_DATA_WRITE_OK |
1312 ARCMSR_IOP2DRV_DATA_READ_OK |
1313 ARCMSR_IOP2DRV_CDB_DONE |
1314 ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
ae52e7f0 1315 writel(mask, reg->iop2drv_doorbell_mask);
1a4f550a
NC		 1316 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
1317 }
cdd3cb15
NC		 1318 break;
1319 case ACB_ADAPTER_TYPE_C: {
c10b1d54 1320 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15
NC		 1321 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK|ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
1322 writel(intmask_org & mask, &reg->host_int_mask);
1323 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
1324 }
5b37479a
CH		 1325 break;
1326 case ACB_ADAPTER_TYPE_D: {
1327 struct MessageUnit_D *reg = acb->pmuD;
1328
1329 mask = ARCMSR_ARC1214_ALL_INT_ENABLE;
1330 writel(intmask_org | mask, reg->pcief0_int_enable);
1331 break;
1332 }
1c57e86d
EC		 1333 }
1334}
1335
76d78300 1336static int arcmsr_build_ccb(struct AdapterControlBlock *acb,
1a4f550a 1337 struct CommandControlBlock *ccb, struct scsi_cmnd *pcmd)
1c57e86d 1338{
1a4f550a
NC		 1339 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1340 int8_t *psge = (int8_t *)&arcmsr_cdb->u;
80da1adb 1341 __le32 address_lo, address_hi;
1a4f550a 1342 int arccdbsize = 0x30;
ae52e7f0 1343 __le32 length = 0;
cdd3cb15 1344 int i;
ae52e7f0 1345 struct scatterlist *sg;
1a4f550a 1346 int nseg;
1c57e86d 1347 ccb->pcmd = pcmd;
1a4f550a 1348 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
1c57e86d
EC		 1349 arcmsr_cdb->TargetID = pcmd->device->id;
1350 arcmsr_cdb->LUN = pcmd->device->lun;
1351 arcmsr_cdb->Function = 1;
626fa32c 1352 arcmsr_cdb->msgContext = 0;
1c57e86d 1353 memcpy(arcmsr_cdb->Cdb, pcmd->cmnd, pcmd->cmd_len);
deff2627
FT		 1354
1355 nseg = scsi_dma_map(pcmd);
cdd3cb15 1356 if (unlikely(nseg > acb->host->sg_tablesize || nseg < 0))
76d78300 1357 return FAILED;
cdd3cb15
NC		 1358 scsi_for_each_sg(pcmd, sg, nseg, i) {
1359 /* Get the physical address of the current data pointer */
1360 length = cpu_to_le32(sg_dma_len(sg));
1361 address_lo = cpu_to_le32(dma_addr_lo32(sg_dma_address(sg)));
1362 address_hi = cpu_to_le32(dma_addr_hi32(sg_dma_address(sg)));
1363 if (address_hi == 0) {
1364 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1365
1366 pdma_sg->address = address_lo;
1367 pdma_sg->length = length;
1368 psge += sizeof (struct SG32ENTRY);
1369 arccdbsize += sizeof (struct SG32ENTRY);
1370 } else {
1371 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1c57e86d 1372
cdd3cb15
NC		 1373 pdma_sg->addresshigh = address_hi;
1374 pdma_sg->address = address_lo;
1375 pdma_sg->length = length|cpu_to_le32(IS_SG64_ADDR);
1376 psge += sizeof (struct SG64ENTRY);
1377 arccdbsize += sizeof (struct SG64ENTRY);
1c57e86d 1378 }
cdd3cb15
NC		 1379 }
1380 arcmsr_cdb->sgcount = (uint8_t)nseg;
1381 arcmsr_cdb->DataLength = scsi_bufflen(pcmd);
ae52e7f0 1382 arcmsr_cdb->msgPages = arccdbsize/0x100 + (arccdbsize % 0x100 ? 1 : 0);
cdd3cb15
NC		 1383 if ( arccdbsize > 256)
1384 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
c32e061f 1385 if (pcmd->sc_data_direction == DMA_TO_DEVICE)
1c57e86d 1386 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
cdd3cb15 1387 ccb->arc_cdb_size = arccdbsize;
76d78300 1388 return SUCCESS;
1c57e86d
EC		 1389}
1390
1391static void arcmsr_post_ccb(struct AdapterControlBlock *acb, struct CommandControlBlock *ccb)
1392{
626fa32c 1393 uint32_t cdb_phyaddr = ccb->cdb_phyaddr;
1c57e86d 1394 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&ccb->arcmsr_cdb;
1c57e86d
EC		 1395 atomic_inc(&acb->ccboutstandingcount);
1396 ccb->startdone = ARCMSR_CCB_START;
1a4f550a
NC		 1397 switch (acb->adapter_type) {
1398 case ACB_ADAPTER_TYPE_A: {
80da1adb 1399 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1400
1401 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE)
626fa32c 1402 writel(cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE,
1c57e86d 1403 &reg->inbound_queueport);
626fa32c
CH		 1404 else
1405 writel(cdb_phyaddr, &reg->inbound_queueport);
1a4f550a 1406 break;
626fa32c 1407 }
1c57e86d 1408
1a4f550a 1409 case ACB_ADAPTER_TYPE_B: {
80da1adb 1410 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1411 uint32_t ending_index, index = reg->postq_index;
1c57e86d 1412
1a4f550a 1413 ending_index = ((index + 1) % ARCMSR_MAX_HBB_POSTQUEUE);
c10b1d54 1414 reg->post_qbuffer[ending_index] = 0;
1a4f550a 1415 if (arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
c10b1d54
CH		 1416 reg->post_qbuffer[index] =
1417 cdb_phyaddr | ARCMSR_CCBPOST_FLAG_SGL_BSIZE;
cdd3cb15 1418 } else {
c10b1d54 1419 reg->post_qbuffer[index] = cdb_phyaddr;
1a4f550a
NC		 1420 }
1421 index++;
1422 index %= ARCMSR_MAX_HBB_POSTQUEUE;/*if last index number set it to 0 */
1423 reg->postq_index = index;
ae52e7f0 1424 writel(ARCMSR_DRV2IOP_CDB_POSTED, reg->drv2iop_doorbell);
1c57e86d 1425 }
1a4f550a 1426 break;
cdd3cb15 1427 case ACB_ADAPTER_TYPE_C: {
c10b1d54 1428 struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
cdd3cb15
NC		 1429 uint32_t ccb_post_stamp, arc_cdb_size;
1430
1431 arc_cdb_size = (ccb->arc_cdb_size > 0x300) ? 0x300 : ccb->arc_cdb_size;
626fa32c 1432 ccb_post_stamp = (cdb_phyaddr | ((arc_cdb_size - 1) >> 6) | 1);
cdd3cb15
NC		 1433 if (acb->cdb_phyaddr_hi32) {
1434 writel(acb->cdb_phyaddr_hi32, &phbcmu->inbound_queueport_high);
1435 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1436 } else {
1437 writel(ccb_post_stamp, &phbcmu->inbound_queueport_low);
1438 }
1439 }
5b37479a
CH		 1440 break;
1441 case ACB_ADAPTER_TYPE_D: {
1442 struct MessageUnit_D *pmu = acb->pmuD;
1443 u16 index_stripped;
3b8155d5 1444 u16 postq_index, toggle;
5b37479a
CH		 1445 unsigned long flags;
1446 struct InBound_SRB *pinbound_srb;
1447
1448 spin_lock_irqsave(&acb->postq_lock, flags);
1449 postq_index = pmu->postq_index;
1450 pinbound_srb = (struct InBound_SRB *)&(pmu->post_qbuffer[postq_index & 0xFF]);
1451 pinbound_srb->addressHigh = dma_addr_hi32(cdb_phyaddr);
1452 pinbound_srb->addressLow = dma_addr_lo32(cdb_phyaddr);
1453 pinbound_srb->length = ccb->arc_cdb_size >> 2;
1454 arcmsr_cdb->msgContext = dma_addr_lo32(cdb_phyaddr);
3b8155d5
CH		 1455 toggle = postq_index & 0x4000;
1456 index_stripped = postq_index + 1;
1457 index_stripped &= (ARCMSR_MAX_ARC1214_POSTQUEUE - 1);
1458 pmu->postq_index = index_stripped ? (index_stripped | toggle) :
1459 (toggle ^ 0x4000);
5b37479a
CH		 1460 writel(postq_index, pmu->inboundlist_write_pointer);
1461 spin_unlock_irqrestore(&acb->postq_lock, flags);
1462 break;
1463 }
1c57e86d
EC		 1464 }
1465}
1466
626fa32c 1467static void arcmsr_hbaA_stop_bgrb(struct AdapterControlBlock *acb)
1c57e86d 1468{
80da1adb 1469 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d
EC		 1470 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1471 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
626fa32c 1472 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1a4f550a 1473 printk(KERN_NOTICE
626fa32c 1474 "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
1a4f550a
NC		 1475 , acb->host->host_no);
1476 }
1477}
1478
626fa32c 1479static void arcmsr_hbaB_stop_bgrb(struct AdapterControlBlock *acb)
1a4f550a 1480{
80da1adb 1481 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 1482 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
ae52e7f0 1483 writel(ARCMSR_MESSAGE_STOP_BGRB, reg->drv2iop_doorbell);
1a4f550a 1484
626fa32c 1485 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1c57e86d 1486 printk(KERN_NOTICE
626fa32c 1487 "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
1c57e86d 1488 , acb->host->host_no);
1a4f550a
NC		 1489 }
1490}
1491
626fa32c 1492static void arcmsr_hbaC_stop_bgrb(struct AdapterControlBlock *pACB)
cdd3cb15 1493{
c10b1d54 1494 struct MessageUnit_C __iomem *reg = pACB->pmuC;
cdd3cb15
NC		 1495 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1496 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, &reg->inbound_msgaddr0);
1497 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
626fa32c 1498 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
cdd3cb15 1499 printk(KERN_NOTICE
626fa32c 1500 "arcmsr%d: wait 'stop adapter background rebulid' timeout\n"
cdd3cb15
NC		 1501 , pACB->host->host_no);
1502 }
1503 return;
1504}
5b37479a
CH		 1505
1506static void arcmsr_hbaD_stop_bgrb(struct AdapterControlBlock *pACB)
1507{
1508 struct MessageUnit_D *reg = pACB->pmuD;
1509
1510 pACB->acb_flags &= ~ACB_F_MSG_START_BGRB;
1511 writel(ARCMSR_INBOUND_MESG0_STOP_BGRB, reg->inbound_msgaddr0);
1512 if (!arcmsr_hbaD_wait_msgint_ready(pACB))
1513 pr_notice("arcmsr%d: wait 'stop adapter background rebulid' "
1514 "timeout\n", pACB->host->host_no);
1515}
1516
1a4f550a
NC		 1517static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1518{
1519 switch (acb->adapter_type) {
1520 case ACB_ADAPTER_TYPE_A: {
626fa32c 1521 arcmsr_hbaA_stop_bgrb(acb);
1a4f550a
NC		 1522 }
1523 break;
1524
1525 case ACB_ADAPTER_TYPE_B: {
626fa32c 1526 arcmsr_hbaB_stop_bgrb(acb);
1a4f550a
NC		 1527 }
1528 break;
cdd3cb15 1529 case ACB_ADAPTER_TYPE_C: {
626fa32c 1530 arcmsr_hbaC_stop_bgrb(acb);
cdd3cb15 1531 }
5b37479a
CH		 1532 break;
1533 case ACB_ADAPTER_TYPE_D:
1534 arcmsr_hbaD_stop_bgrb(acb);
1535 break;
1a4f550a 1536 }
1c57e86d
EC		 1537}
1538
1539static void arcmsr_free_ccb_pool(struct AdapterControlBlock *acb)
1540{
cdd3cb15 1541 dma_free_coherent(&acb->pdev->dev, acb->uncache_size, acb->dma_coherent, acb->dma_coherent_handle);
1c57e86d
EC		 1542}
1543
c10b1d54 1544static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1c57e86d 1545{
1a4f550a
NC		 1546 switch (acb->adapter_type) {
1547 case ACB_ADAPTER_TYPE_A: {
80da1adb 1548 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 1549 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
1550 }
1551 break;
1c57e86d 1552
1a4f550a 1553 case ACB_ADAPTER_TYPE_B: {
80da1adb 1554 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1555 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1c57e86d 1556 }
1a4f550a 1557 break;
cdd3cb15
NC		 1558 case ACB_ADAPTER_TYPE_C: {
1559 struct MessageUnit_C __iomem *reg = acb->pmuC;
5b37479a 1560
cdd3cb15
NC		 1561 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
1562 }
5b37479a
CH		 1563 break;
1564 case ACB_ADAPTER_TYPE_D: {
1565 struct MessageUnit_D *reg = acb->pmuD;
1566 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
1567 reg->inbound_doorbell);
1568 }
1569 break;
1c57e86d 1570 }
1a4f550a
NC		 1571}
1572
1573static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1574{
1575 switch (acb->adapter_type) {
1576 case ACB_ADAPTER_TYPE_A: {
80da1adb 1577 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 1578 /*
1a4f550a
NC		 1579 ** push inbound doorbell tell iop, driver data write ok
1580 ** and wait reply on next hwinterrupt for next Qbuffer post
1c57e86d 1581 */
1a4f550a
NC		 1582 writel(ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK, &reg->inbound_doorbell);
1583 }
1584 break;
1585
1586 case ACB_ADAPTER_TYPE_B: {
80da1adb 1587 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a
NC		 1588 /*
1589 ** push inbound doorbell tell iop, driver data write ok
1590 ** and wait reply on next hwinterrupt for next Qbuffer post
1591 */
ae52e7f0 1592 writel(ARCMSR_DRV2IOP_DATA_WRITE_OK, reg->drv2iop_doorbell);
1a4f550a
NC		 1593 }
1594 break;
cdd3cb15
NC		 1595 case ACB_ADAPTER_TYPE_C: {
1596 struct MessageUnit_C __iomem *reg = acb->pmuC;
1597 /*
1598 ** push inbound doorbell tell iop, driver data write ok
1599 ** and wait reply on next hwinterrupt for next Qbuffer post
1600 */
1601 writel(ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK, &reg->inbound_doorbell);
1602 }
1603 break;
5b37479a
CH		 1604 case ACB_ADAPTER_TYPE_D: {
1605 struct MessageUnit_D *reg = acb->pmuD;
1606 writel(ARCMSR_ARC1214_DRV2IOP_DATA_IN_READY,
1607 reg->inbound_doorbell);
1608 }
1609 break;
1a4f550a
NC		 1610 }
1611}
1612
80da1adb 1613struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *acb)
1a4f550a 1614{
0c7eb2eb 1615 struct QBUFFER __iomem *qbuffer = NULL;
1a4f550a
NC		 1616 switch (acb->adapter_type) {
1617
1618 case ACB_ADAPTER_TYPE_A: {
80da1adb
AV		 1619 struct MessageUnit_A __iomem *reg = acb->pmuA;
1620 qbuffer = (struct QBUFFER __iomem *)&reg->message_rbuffer;
1a4f550a
NC		 1621 }
1622 break;
1623
1624 case ACB_ADAPTER_TYPE_B: {
80da1adb 1625 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1626 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
1a4f550a
NC		 1627 }
1628 break;
cdd3cb15 1629 case ACB_ADAPTER_TYPE_C: {
c10b1d54 1630 struct MessageUnit_C __iomem *phbcmu = acb->pmuC;
cdd3cb15
NC		 1631 qbuffer = (struct QBUFFER __iomem *)&phbcmu->message_rbuffer;
1632 }
5b37479a
CH		 1633 break;
1634 case ACB_ADAPTER_TYPE_D: {
1635 struct MessageUnit_D *reg = acb->pmuD;
1636 qbuffer = (struct QBUFFER __iomem *)reg->message_rbuffer;
1637 }
1638 break;
1a4f550a
NC		 1639 }
1640 return qbuffer;
1641}
1642
80da1adb 1643static struct QBUFFER __iomem *arcmsr_get_iop_wqbuffer(struct AdapterControlBlock *acb)
1a4f550a 1644{
0c7eb2eb 1645 struct QBUFFER __iomem *pqbuffer = NULL;
1a4f550a
NC		 1646 switch (acb->adapter_type) {
1647
1648 case ACB_ADAPTER_TYPE_A: {
80da1adb
AV		 1649 struct MessageUnit_A __iomem *reg = acb->pmuA;
1650 pqbuffer = (struct QBUFFER __iomem *) &reg->message_wbuffer;
1a4f550a
NC		 1651 }
1652 break;
1653
1654 case ACB_ADAPTER_TYPE_B: {
80da1adb 1655 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 1656 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
1a4f550a
NC		 1657 }
1658 break;
cdd3cb15 1659 case ACB_ADAPTER_TYPE_C: {
c10b1d54 1660 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15 1661 pqbuffer = (struct QBUFFER __iomem *)&reg->message_wbuffer;
5b37479a
CH		 1662 }
1663 break;
1664 case ACB_ADAPTER_TYPE_D: {
1665 struct MessageUnit_D *reg = acb->pmuD;
1666 pqbuffer = (struct QBUFFER __iomem *)reg->message_wbuffer;
1667 }
1668 break;
1a4f550a
NC		 1669 }
1670 return pqbuffer;
1671}
1672
bb263c4e
CH		 1673static uint32_t
1674arcmsr_Read_iop_rqbuffer_in_DWORD(struct AdapterControlBlock *acb,
1675 struct QBUFFER __iomem *prbuffer)
1a4f550a 1676{
bb263c4e
CH		 1677 uint8_t *pQbuffer;
1678 uint8_t *buf1 = NULL;
1679 uint32_t __iomem *iop_data;
1680 uint32_t iop_len, data_len, *buf2 = NULL;
1681
1682 iop_data = (uint32_t __iomem *)prbuffer->data;
1683 iop_len = readl(&prbuffer->data_len);
1684 if (iop_len > 0) {
1685 buf1 = kmalloc(128, GFP_ATOMIC);
1686 buf2 = (uint32_t *)buf1;
1687 if (buf1 == NULL)
1688 return 0;
1689 data_len = iop_len;
1690 while (data_len >= 4) {
1691 *buf2++ = readl(iop_data);
1a4f550a 1692 iop_data++;
bb263c4e 1693 data_len -= 4;
1a4f550a 1694 }
bb263c4e
CH		 1695 if (data_len)
1696 *buf2 = readl(iop_data);
1697 buf2 = (uint32_t *)buf1;
1698 }
1699 while (iop_len > 0) {
2e9feb43 1700 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
bb263c4e 1701 *pQbuffer = *buf1;
2e9feb43 1702 acb->rqbuf_putIndex++;
bb263c4e 1703 /* if last, index number set it to 0 */
2e9feb43 1704 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
bb263c4e
CH		 1705 buf1++;
1706 iop_len--;
1707 }
2e9feb43 1708 kfree(buf2);
bb263c4e
CH		 1709 /* let IOP know data has been read */
1710 arcmsr_iop_message_read(acb);
1711 return 1;
1712}
1713
1714uint32_t
1715arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1716 struct QBUFFER __iomem *prbuffer) {
1717
1718 uint8_t *pQbuffer;
1719 uint8_t __iomem *iop_data;
1720 uint32_t iop_len;
1721
5b37479a 1722 if (acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D))
bb263c4e
CH		 1723 return arcmsr_Read_iop_rqbuffer_in_DWORD(acb, prbuffer);
1724 iop_data = (uint8_t __iomem *)prbuffer->data;
1725 iop_len = readl(&prbuffer->data_len);
1726 while (iop_len > 0) {
2e9feb43 1727 pQbuffer = &acb->rqbuffer[acb->rqbuf_putIndex];
bb263c4e 1728 *pQbuffer = readb(iop_data);
2e9feb43
CH		 1729 acb->rqbuf_putIndex++;
1730 acb->rqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
bb263c4e
CH		 1731 iop_data++;
1732 iop_len--;
1a4f550a 1733 }
bb263c4e
CH		 1734 arcmsr_iop_message_read(acb);
1735 return 1;
1736}
1a4f550a 1737
bb263c4e
CH		 1738static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1739{
1740 unsigned long flags;
1741 struct QBUFFER __iomem *prbuffer;
1742 int32_t buf_empty_len;
1743
1744 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
1745 prbuffer = arcmsr_get_iop_rqbuffer(acb);
2e9feb43 1746 buf_empty_len = (acb->rqbuf_putIndex - acb->rqbuf_getIndex - 1) &
bb263c4e
CH		 1747 (ARCMSR_MAX_QBUFFER - 1);
1748 if (buf_empty_len >= readl(&prbuffer->data_len)) {
1749 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1750 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1751 } else
1a4f550a 1752 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
bb263c4e
CH		 1753 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
1754}
1755
1756static void arcmsr_write_ioctldata2iop_in_DWORD(struct AdapterControlBlock *acb)
1757{
1758 uint8_t *pQbuffer;
1759 struct QBUFFER __iomem *pwbuffer;
1760 uint8_t *buf1 = NULL;
1761 uint32_t __iomem *iop_data;
1762 uint32_t allxfer_len = 0, data_len, *buf2 = NULL, data;
1763
1764 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
1765 buf1 = kmalloc(128, GFP_ATOMIC);
1766 buf2 = (uint32_t *)buf1;
1767 if (buf1 == NULL)
1768 return;
1769
1770 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
1771 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1772 iop_data = (uint32_t __iomem *)pwbuffer->data;
2e9feb43 1773 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
bb263c4e 1774 && (allxfer_len < 124)) {
2e9feb43 1775 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
bb263c4e 1776 *buf1 = *pQbuffer;
2e9feb43
CH		 1777 acb->wqbuf_getIndex++;
1778 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
bb263c4e
CH		 1779 buf1++;
1780 allxfer_len++;
1781 }
1782 data_len = allxfer_len;
1783 buf1 = (uint8_t *)buf2;
1784 while (data_len >= 4) {
1785 data = *buf2++;
1786 writel(data, iop_data);
1787 iop_data++;
1788 data_len -= 4;
1789 }
1790 if (data_len) {
1791 data = *buf2;
1792 writel(data, iop_data);
1793 }
1794 writel(allxfer_len, &pwbuffer->data_len);
1795 kfree(buf1);
1796 arcmsr_iop_message_wrote(acb);
1a4f550a
NC		 1797 }
1798}
1799
bb263c4e
CH		 1800void
1801arcmsr_write_ioctldata2iop(struct AdapterControlBlock *acb)
1a4f550a 1802{
bb263c4e
CH		 1803 uint8_t *pQbuffer;
1804 struct QBUFFER __iomem *pwbuffer;
1805 uint8_t __iomem *iop_data;
1806 int32_t allxfer_len = 0;
1a4f550a 1807
5b37479a 1808 if (acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) {
bb263c4e
CH		 1809 arcmsr_write_ioctldata2iop_in_DWORD(acb);
1810 return;
1811 }
1812 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READED) {
1a4f550a
NC		 1813 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READED);
1814 pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1815 iop_data = (uint8_t __iomem *)pwbuffer->data;
2e9feb43 1816 while ((acb->wqbuf_getIndex != acb->wqbuf_putIndex)
bb263c4e 1817 && (allxfer_len < 124)) {
2e9feb43 1818 pQbuffer = &acb->wqbuffer[acb->wqbuf_getIndex];
bb263c4e 1819 writeb(*pQbuffer, iop_data);
2e9feb43
CH		 1820 acb->wqbuf_getIndex++;
1821 acb->wqbuf_getIndex %= ARCMSR_MAX_QBUFFER;
1a4f550a
NC		 1822 iop_data++;
1823 allxfer_len++;
1824 }
bb263c4e 1825 writel(allxfer_len, &pwbuffer->data_len);
1a4f550a
NC		 1826 arcmsr_iop_message_wrote(acb);
1827 }
bb263c4e 1828}
1a4f550a 1829
bb263c4e
CH		 1830static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1831{
1832 unsigned long flags;
1833
1834 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
1835 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READED;
2e9feb43 1836 if (acb->wqbuf_getIndex != acb->wqbuf_putIndex)
bb263c4e 1837 arcmsr_write_ioctldata2iop(acb);
2e9feb43 1838 if (acb->wqbuf_getIndex == acb->wqbuf_putIndex)
1a4f550a 1839 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
bb263c4e 1840 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
1a4f550a
NC		 1841}
1842
626fa32c 1843static void arcmsr_hbaA_doorbell_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 1844{
1845 uint32_t outbound_doorbell;
80da1adb 1846 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a 1847 outbound_doorbell = readl(&reg->outbound_doorbell);
6b393722
CH		 1848 do {
1849 writel(outbound_doorbell, &reg->outbound_doorbell);
1850 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK)
1851 arcmsr_iop2drv_data_wrote_handle(acb);
1852 if (outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK)
1853 arcmsr_iop2drv_data_read_handle(acb);
1854 outbound_doorbell = readl(&reg->outbound_doorbell);
1855 } while (outbound_doorbell & (ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK
1856 | ARCMSR_OUTBOUND_IOP331_DATA_READ_OK));
1a4f550a 1857}
626fa32c 1858static void arcmsr_hbaC_doorbell_isr(struct AdapterControlBlock *pACB)
cdd3cb15
NC		 1859{
1860 uint32_t outbound_doorbell;
c10b1d54 1861 struct MessageUnit_C __iomem *reg = pACB->pmuC;
cdd3cb15
NC		 1862 /*
1863 *******************************************************************
1864 ** Maybe here we need to check wrqbuffer_lock is lock or not
1865 ** DOORBELL: din! don!
1866 ** check if there are any mail need to pack from firmware
1867 *******************************************************************
1868 */
1869 outbound_doorbell = readl(&reg->outbound_doorbell);
6b393722
CH		 1870 do {
1871 writel(outbound_doorbell, &reg->outbound_doorbell_clear);
1872 readl(&reg->outbound_doorbell_clear);
1873 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK)
1874 arcmsr_iop2drv_data_wrote_handle(pACB);
1875 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK)
1876 arcmsr_iop2drv_data_read_handle(pACB);
1877 if (outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE)
626fa32c 1878 arcmsr_hbaC_message_isr(pACB);
6b393722
CH		 1879 outbound_doorbell = readl(&reg->outbound_doorbell);
1880 } while (outbound_doorbell & (ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK
1881 | ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK
1882 | ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE));
cdd3cb15 1883}
5b37479a
CH		 1884
1885static void arcmsr_hbaD_doorbell_isr(struct AdapterControlBlock *pACB)
1886{
1887 uint32_t outbound_doorbell;
1888 struct MessageUnit_D *pmu = pACB->pmuD;
1889
1890 outbound_doorbell = readl(pmu->outbound_doorbell);
1891 do {
1892 writel(outbound_doorbell, pmu->outbound_doorbell);
1893 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE)
1894 arcmsr_hbaD_message_isr(pACB);
1895 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK)
1896 arcmsr_iop2drv_data_wrote_handle(pACB);
1897 if (outbound_doorbell & ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK)
1898 arcmsr_iop2drv_data_read_handle(pACB);
1899 outbound_doorbell = readl(pmu->outbound_doorbell);
1900 } while (outbound_doorbell & (ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK
1901 | ARCMSR_ARC1214_IOP2DRV_DATA_READ_OK
1902 | ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE));
1903}
1904
626fa32c 1905static void arcmsr_hbaA_postqueue_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 1906{
1907 uint32_t flag_ccb;
80da1adb 1908 struct MessageUnit_A __iomem *reg = acb->pmuA;
cdd3cb15
NC		 1909 struct ARCMSR_CDB *pARCMSR_CDB;
1910 struct CommandControlBlock *pCCB;
1911 bool error;
1a4f550a 1912 while ((flag_ccb = readl(&reg->outbound_queueport)) != 0xFFFFFFFF) {
cdd3cb15
NC		 1913 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));/*frame must be 32 bytes aligned*/
1914 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1915 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1916 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 1917 }
1918}
626fa32c 1919static void arcmsr_hbaB_postqueue_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 1920{
1921 uint32_t index;
1922 uint32_t flag_ccb;
80da1adb 1923 struct MessageUnit_B *reg = acb->pmuB;
cdd3cb15
NC		 1924 struct ARCMSR_CDB *pARCMSR_CDB;
1925 struct CommandControlBlock *pCCB;
1926 bool error;
1a4f550a 1927 index = reg->doneq_index;
c10b1d54
CH		 1928 while ((flag_ccb = reg->done_qbuffer[index]) != 0) {
1929 reg->done_qbuffer[index] = 0;
cdd3cb15
NC		 1930 pARCMSR_CDB = (struct ARCMSR_CDB *)(acb->vir2phy_offset+(flag_ccb << 5));/*frame must be 32 bytes aligned*/
1931 pCCB = container_of(pARCMSR_CDB, struct CommandControlBlock, arcmsr_cdb);
1932 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
1933 arcmsr_drain_donequeue(acb, pCCB, error);
1a4f550a
NC		 1934 index++;
1935 index %= ARCMSR_MAX_HBB_POSTQUEUE;
1936 reg->doneq_index = index;
1937 }
1938}
cdd3cb15 1939
626fa32c 1940static void arcmsr_hbaC_postqueue_isr(struct AdapterControlBlock *acb)
cdd3cb15 1941{
c10b1d54 1942 struct MessageUnit_C __iomem *phbcmu;
cdd3cb15
NC		 1943 struct ARCMSR_CDB *arcmsr_cdb;
1944 struct CommandControlBlock *ccb;
1945 uint32_t flag_ccb, ccb_cdb_phy, throttling = 0;
1946 int error;
1947
c10b1d54 1948 phbcmu = acb->pmuC;
cdd3cb15
NC		 1949 /* areca cdb command done */
1950 /* Use correct offset and size for syncing */
1951
6b393722
CH		 1952 while ((flag_ccb = readl(&phbcmu->outbound_queueport_low)) !=
1953 0xFFFFFFFF) {
1954 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
1955 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
1956 + ccb_cdb_phy);
1957 ccb = container_of(arcmsr_cdb, struct CommandControlBlock,
1958 arcmsr_cdb);
1959 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
1960 ? true : false;
1961 /* check if command done with no error */
1962 arcmsr_drain_donequeue(acb, ccb, error);
1963 throttling++;
1964 if (throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1965 writel(ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING,
1966 &phbcmu->inbound_doorbell);
1967 throttling = 0;
1968 }
cdd3cb15
NC		 1969 }
1970}
5b37479a
CH		 1971
1972static void arcmsr_hbaD_postqueue_isr(struct AdapterControlBlock *acb)
1973{
3b8155d5 1974 u32 outbound_write_pointer, doneq_index, index_stripped, toggle;
5b37479a
CH		 1975 uint32_t addressLow, ccb_cdb_phy;
1976 int error;
1977 struct MessageUnit_D *pmu;
1978 struct ARCMSR_CDB *arcmsr_cdb;
1979 struct CommandControlBlock *ccb;
1980 unsigned long flags;
1981
1982 spin_lock_irqsave(&acb->doneq_lock, flags);
1983 pmu = acb->pmuD;
1984 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
1985 doneq_index = pmu->doneq_index;
1986 if ((doneq_index & 0xFFF) != (outbound_write_pointer & 0xFFF)) {
1987 do {
3b8155d5
CH		 1988 toggle = doneq_index & 0x4000;
1989 index_stripped = (doneq_index & 0xFFF) + 1;
1990 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
1991 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
1992 ((toggle ^ 0x4000) + 1);
5b37479a
CH		 1993 doneq_index = pmu->doneq_index;
1994 addressLow = pmu->done_qbuffer[doneq_index &
1995 0xFFF].addressLow;
1996 ccb_cdb_phy = (addressLow & 0xFFFFFFF0);
1997 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset
1998 + ccb_cdb_phy);
1999 ccb = container_of(arcmsr_cdb,
2000 struct CommandControlBlock, arcmsr_cdb);
2001 error = (addressLow & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
2002 ? true : false;
2003 arcmsr_drain_donequeue(acb, ccb, error);
2004 writel(doneq_index, pmu->outboundlist_read_pointer);
2005 } while ((doneq_index & 0xFFF) !=
2006 (outbound_write_pointer & 0xFFF));
2007 }
2008 writel(ARCMSR_ARC1214_OUTBOUND_LIST_INTERRUPT_CLEAR,
2009 pmu->outboundlist_interrupt_cause);
2010 readl(pmu->outboundlist_interrupt_cause);
2011 spin_unlock_irqrestore(&acb->doneq_lock, flags);
2012}
2013
36b83ded
NC		 2014/*
2015**********************************************************************************
2016** Handle a message interrupt
2017**
cdd3cb15 2018** The only message interrupt we expect is in response to a query for the current adapter config.
36b83ded
NC		 2019** We want this in order to compare the drivemap so that we can detect newly-attached drives.
2020**********************************************************************************
2021*/
626fa32c 2022static void arcmsr_hbaA_message_isr(struct AdapterControlBlock *acb)
36b83ded 2023{
c10b1d54 2024 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded
NC		 2025 /*clear interrupt and message state*/
2026 writel(ARCMSR_MU_OUTBOUND_MESSAGE0_INT, &reg->outbound_intstatus);
2027 schedule_work(&acb->arcmsr_do_message_isr_bh);
2028}
626fa32c 2029static void arcmsr_hbaB_message_isr(struct AdapterControlBlock *acb)
36b83ded
NC		 2030{
2031 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 2032
36b83ded 2033 /*clear interrupt and message state*/
ae52e7f0 2034 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
36b83ded
NC		 2035 schedule_work(&acb->arcmsr_do_message_isr_bh);
2036}
cdd3cb15
NC		 2037/*
2038**********************************************************************************
2039** Handle a message interrupt
2040**
2041** The only message interrupt we expect is in response to a query for the
2042** current adapter config.
2043** We want this in order to compare the drivemap so that we can detect newly-attached drives.
2044**********************************************************************************
2045*/
626fa32c 2046static void arcmsr_hbaC_message_isr(struct AdapterControlBlock *acb)
cdd3cb15 2047{
c10b1d54 2048 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15
NC		 2049 /*clear interrupt and message state*/
2050 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);
2051 schedule_work(&acb->arcmsr_do_message_isr_bh);
2052}
2053
5b37479a
CH		 2054static void arcmsr_hbaD_message_isr(struct AdapterControlBlock *acb)
2055{
2056 struct MessageUnit_D *reg = acb->pmuD;
2057
2058 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE, reg->outbound_doorbell);
2059 readl(reg->outbound_doorbell);
2060 schedule_work(&acb->arcmsr_do_message_isr_bh);
2061}
2062
626fa32c 2063static int arcmsr_hbaA_handle_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 2064{
2065 uint32_t outbound_intstatus;
80da1adb 2066 struct MessageUnit_A __iomem *reg = acb->pmuA;
36b83ded 2067 outbound_intstatus = readl(&reg->outbound_intstatus) &
cdd3cb15 2068 acb->outbound_int_enable;
6b393722
CH		 2069 if (!(outbound_intstatus & ARCMSR_MU_OUTBOUND_HANDLE_INT))
2070 return IRQ_NONE;
2071 do {
2072 writel(outbound_intstatus, &reg->outbound_intstatus);
2073 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT)
626fa32c 2074 arcmsr_hbaA_doorbell_isr(acb);
6b393722 2075 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT)
626fa32c 2076 arcmsr_hbaA_postqueue_isr(acb);
6b393722 2077 if (outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT)
626fa32c 2078 arcmsr_hbaA_message_isr(acb);
6b393722
CH		 2079 outbound_intstatus = readl(&reg->outbound_intstatus) &
2080 acb->outbound_int_enable;
2081 } while (outbound_intstatus & (ARCMSR_MU_OUTBOUND_DOORBELL_INT
2082 | ARCMSR_MU_OUTBOUND_POSTQUEUE_INT
2083 | ARCMSR_MU_OUTBOUND_MESSAGE0_INT));
2084 return IRQ_HANDLED;
1a4f550a
NC		 2085}
2086
626fa32c 2087static int arcmsr_hbaB_handle_isr(struct AdapterControlBlock *acb)
1a4f550a
NC		 2088{
2089 uint32_t outbound_doorbell;
80da1adb 2090 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2091 outbound_doorbell = readl(reg->iop2drv_doorbell) &
cdd3cb15 2092 acb->outbound_int_enable;
1a4f550a 2093 if (!outbound_doorbell)
6b393722
CH		 2094 return IRQ_NONE;
2095 do {
2096 writel(~outbound_doorbell, reg->iop2drv_doorbell);
2097 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
2098 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK)
2099 arcmsr_iop2drv_data_wrote_handle(acb);
2100 if (outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK)
2101 arcmsr_iop2drv_data_read_handle(acb);
2102 if (outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE)
626fa32c 2103 arcmsr_hbaB_postqueue_isr(acb);
6b393722 2104 if (outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE)
626fa32c 2105 arcmsr_hbaB_message_isr(acb);
6b393722
CH		 2106 outbound_doorbell = readl(reg->iop2drv_doorbell) &
2107 acb->outbound_int_enable;
2108 } while (outbound_doorbell & (ARCMSR_IOP2DRV_DATA_WRITE_OK
2109 | ARCMSR_IOP2DRV_DATA_READ_OK
2110 | ARCMSR_IOP2DRV_CDB_DONE
2111 | ARCMSR_IOP2DRV_MESSAGE_CMD_DONE));
2112 return IRQ_HANDLED;
1a4f550a
NC		 2113}
2114
626fa32c 2115static int arcmsr_hbaC_handle_isr(struct AdapterControlBlock *pACB)
cdd3cb15
NC		 2116{
2117 uint32_t host_interrupt_status;
c10b1d54 2118 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
cdd3cb15
NC		 2119 /*
2120 *********************************************
2121 ** check outbound intstatus
2122 *********************************************
2123 */
6b393722
CH		 2124 host_interrupt_status = readl(&phbcmu->host_int_status) &
2125 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2126 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR);
2127 if (!host_interrupt_status)
2128 return IRQ_NONE;
2129 do {
2130 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)
626fa32c 2131 arcmsr_hbaC_doorbell_isr(pACB);
6b393722
CH		 2132 /* MU post queue interrupts*/
2133 if (host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)
626fa32c 2134 arcmsr_hbaC_postqueue_isr(pACB);
6b393722
CH		 2135 host_interrupt_status = readl(&phbcmu->host_int_status);
2136 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR |
2137 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR));
2138 return IRQ_HANDLED;
cdd3cb15 2139}
5b37479a
CH		 2140
2141static irqreturn_t arcmsr_hbaD_handle_isr(struct AdapterControlBlock *pACB)
2142{
2143 u32 host_interrupt_status;
2144 struct MessageUnit_D *pmu = pACB->pmuD;
2145
2146 host_interrupt_status = readl(pmu->host_int_status) &
2147 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
2148 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR);
2149 if (!host_interrupt_status)
2150 return IRQ_NONE;
2151 do {
2152 /* MU post queue interrupts*/
2153 if (host_interrupt_status &
2154 ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR)
2155 arcmsr_hbaD_postqueue_isr(pACB);
2156 if (host_interrupt_status &
2157 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR)
2158 arcmsr_hbaD_doorbell_isr(pACB);
2159 host_interrupt_status = readl(pmu->host_int_status);
2160 } while (host_interrupt_status &
2161 (ARCMSR_ARC1214_OUTBOUND_POSTQUEUE_ISR |
2162 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ISR));
2163 return IRQ_HANDLED;
2164}
2165
1a4f550a
NC		 2166static irqreturn_t arcmsr_interrupt(struct AdapterControlBlock *acb)
2167{
2168 switch (acb->adapter_type) {
6b393722 2169 case ACB_ADAPTER_TYPE_A:
626fa32c 2170 return arcmsr_hbaA_handle_isr(acb);
1a4f550a 2171 break;
6b393722 2172 case ACB_ADAPTER_TYPE_B:
626fa32c 2173 return arcmsr_hbaB_handle_isr(acb);
1a4f550a 2174 break;
6b393722 2175 case ACB_ADAPTER_TYPE_C:
626fa32c 2176 return arcmsr_hbaC_handle_isr(acb);
5b37479a
CH		 2177 case ACB_ADAPTER_TYPE_D:
2178 return arcmsr_hbaD_handle_isr(acb);
6b393722
CH		 2179 default:
2180 return IRQ_NONE;
1c57e86d 2181 }
1c57e86d
EC		 2182}
2183
2184static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2185{
2186 if (acb) {
2187 /* stop adapter background rebuild */
2188 if (acb->acb_flags & ACB_F_MSG_START_BGRB) {
1a4f550a 2189 uint32_t intmask_org;
1c57e86d 2190 acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1a4f550a 2191 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d
EC		 2192 arcmsr_stop_adapter_bgrb(acb);
2193 arcmsr_flush_adapter_cache(acb);
1a4f550a
NC		 2194 arcmsr_enable_outbound_ints(acb, intmask_org);
2195 }
2196 }
2197}
2198
bb263c4e
CH		 2199
2200void arcmsr_clear_iop2drv_rqueue_buffer(struct AdapterControlBlock *acb)
1a4f550a 2201{
bb263c4e
CH		 2202 uint32_t i;
2203
2204 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2205 for (i = 0; i < 15; i++) {
2206 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2207 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2e9feb43
CH		 2208 acb->rqbuf_getIndex = 0;
2209 acb->rqbuf_putIndex = 0;
bb263c4e
CH		 2210 arcmsr_iop_message_read(acb);
2211 mdelay(30);
2e9feb43
CH		 2212 } else if (acb->rqbuf_getIndex !=
2213 acb->rqbuf_putIndex) {
2214 acb->rqbuf_getIndex = 0;
2215 acb->rqbuf_putIndex = 0;
bb263c4e
CH		 2216 mdelay(30);
2217 } else
2218 break;
1c57e86d
EC		 2219 }
2220 }
2221}
2222
36b83ded 2223static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb,
bb263c4e 2224 struct scsi_cmnd *cmd)
1c57e86d 2225{
1c57e86d 2226 char *buffer;
bb263c4e
CH		 2227 unsigned short use_sg;
2228 int retvalue = 0, transfer_len = 0;
2229 unsigned long flags;
2230 struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2231 uint32_t controlcode = (uint32_t)cmd->cmnd[5] << 24 |
2232 (uint32_t)cmd->cmnd[6] << 16 |
2233 (uint32_t)cmd->cmnd[7] << 8 |
2234 (uint32_t)cmd->cmnd[8];
deff2627 2235 struct scatterlist *sg;
bb263c4e
CH		 2236
2237 use_sg = scsi_sg_count(cmd);
deff2627 2238 sg = scsi_sglist(cmd);
77dfce07 2239 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
bb263c4e 2240 if (use_sg > 1) {
deff2627
FT		 2241 retvalue = ARCMSR_MESSAGE_FAIL;
2242 goto message_out;
1c57e86d 2243 }
deff2627 2244 transfer_len += sg->length;
1c57e86d
EC		 2245 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2246 retvalue = ARCMSR_MESSAGE_FAIL;
bb263c4e 2247 pr_info("%s: ARCMSR_MESSAGE_FAIL!\n", __func__);
1c57e86d
EC		 2248 goto message_out;
2249 }
bb263c4e
CH		 2250 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *)buffer;
2251 switch (controlcode) {
1c57e86d 2252 case ARCMSR_MESSAGE_READ_RQBUFFER: {
69e562c2 2253 unsigned char *ver_addr;
2e9feb43 2254 uint8_t *ptmpQbuffer;
bb263c4e 2255 uint32_t allxfer_len = 0;
2e9feb43 2256 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
69e562c2 2257 if (!ver_addr) {
1a4f550a 2258 retvalue = ARCMSR_MESSAGE_FAIL;
bb263c4e 2259 pr_info("%s: memory not enough!\n", __func__);
1a4f550a
NC		 2260 goto message_out;
2261 }
69e562c2 2262 ptmpQbuffer = ver_addr;
bb263c4e 2263 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2e9feb43
CH		 2264 if (acb->rqbuf_getIndex != acb->rqbuf_putIndex) {
2265 unsigned int tail = acb->rqbuf_getIndex;
2266 unsigned int head = acb->rqbuf_putIndex;
2267 unsigned int cnt_to_end = CIRC_CNT_TO_END(head, tail, ARCMSR_MAX_QBUFFER);
2268
2269 allxfer_len = CIRC_CNT(head, tail, ARCMSR_MAX_QBUFFER);
2270 if (allxfer_len > ARCMSR_API_DATA_BUFLEN)
2271 allxfer_len = ARCMSR_API_DATA_BUFLEN;
2272
2273 if (allxfer_len <= cnt_to_end)
2274 memcpy(ptmpQbuffer, acb->rqbuffer + tail, allxfer_len);
2275 else {
2276 memcpy(ptmpQbuffer, acb->rqbuffer + tail, cnt_to_end);
2277 memcpy(ptmpQbuffer + cnt_to_end, acb->rqbuffer, allxfer_len - cnt_to_end);
bb263c4e 2278 }
2e9feb43 2279 acb->rqbuf_getIndex = (acb->rqbuf_getIndex + allxfer_len) % ARCMSR_MAX_QBUFFER;
1a4f550a 2280 }
bb263c4e
CH		 2281 memcpy(pcmdmessagefld->messagedatabuffer, ver_addr,
2282 allxfer_len);
1a4f550a 2283 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
80da1adb 2284 struct QBUFFER __iomem *prbuffer;
1a4f550a
NC		 2285 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2286 prbuffer = arcmsr_get_iop_rqbuffer(acb);
bb263c4e
CH		 2287 if (arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2288 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
ae52e7f0 2289 }
bb263c4e 2290 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
69e562c2 2291 kfree(ver_addr);
bb263c4e
CH		 2292 pcmdmessagefld->cmdmessage.Length = allxfer_len;
2293 if (acb->fw_flag == FW_DEADLOCK)
2294 pcmdmessagefld->cmdmessage.ReturnCode =
2295 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2296 else
2297 pcmdmessagefld->cmdmessage.ReturnCode =
2298 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 2299 break;
bb263c4e 2300 }
1a4f550a 2301 case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
69e562c2 2302 unsigned char *ver_addr;
2e9feb43 2303 int32_t user_len, cnt2end;
1a4f550a 2304 uint8_t *pQbuffer, *ptmpuserbuffer;
2e9feb43 2305 ver_addr = kmalloc(ARCMSR_API_DATA_BUFLEN, GFP_ATOMIC);
69e562c2 2306 if (!ver_addr) {
1a4f550a
NC		 2307 retvalue = ARCMSR_MESSAGE_FAIL;
2308 goto message_out;
2309 }
69e562c2 2310 ptmpuserbuffer = ver_addr;
1a4f550a 2311 user_len = pcmdmessagefld->cmdmessage.Length;
bb263c4e
CH		 2312 memcpy(ptmpuserbuffer,
2313 pcmdmessagefld->messagedatabuffer, user_len);
2314 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2e9feb43 2315 if (acb->wqbuf_putIndex != acb->wqbuf_getIndex) {
1a4f550a
NC		 2316 struct SENSE_DATA *sensebuffer =
2317 (struct SENSE_DATA *)cmd->sense_buffer;
bb263c4e 2318 arcmsr_write_ioctldata2iop(acb);
1a4f550a 2319 /* has error report sensedata */
bb263c4e 2320 sensebuffer->ErrorCode = SCSI_SENSE_CURRENT_ERRORS;
1a4f550a
NC		 2321 sensebuffer->SenseKey = ILLEGAL_REQUEST;
2322 sensebuffer->AdditionalSenseLength = 0x0A;
2323 sensebuffer->AdditionalSenseCode = 0x20;
2324 sensebuffer->Valid = 1;
2325 retvalue = ARCMSR_MESSAGE_FAIL;
2326 } else {
2e9feb43
CH		 2327 pQbuffer = &acb->wqbuffer[acb->wqbuf_putIndex];
2328 cnt2end = ARCMSR_MAX_QBUFFER - acb->wqbuf_putIndex;
2329 if (user_len > cnt2end) {
2330 memcpy(pQbuffer, ptmpuserbuffer, cnt2end);
2331 ptmpuserbuffer += cnt2end;
2332 user_len -= cnt2end;
2333 acb->wqbuf_putIndex = 0;
2334 pQbuffer = acb->wqbuffer;
2335 }
2336 memcpy(pQbuffer, ptmpuserbuffer, user_len);
2337 acb->wqbuf_putIndex += user_len;
2338 acb->wqbuf_putIndex %= ARCMSR_MAX_QBUFFER;
2339 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2340 acb->acb_flags &=
1a4f550a 2341 ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2e9feb43 2342 arcmsr_write_ioctldata2iop(acb);
1a4f550a 2343 }
1c57e86d 2344 }
bb263c4e
CH		 2345 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2346 kfree(ver_addr);
2347 if (acb->fw_flag == FW_DEADLOCK)
2348 pcmdmessagefld->cmdmessage.ReturnCode =
2349 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2350 else
2351 pcmdmessagefld->cmdmessage.ReturnCode =
2352 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 2353 break;
bb263c4e 2354 }
1c57e86d 2355 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
1a4f550a 2356 uint8_t *pQbuffer = acb->rqbuffer;
bb263c4e
CH		 2357
2358 arcmsr_clear_iop2drv_rqueue_buffer(acb);
2359 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
1a4f550a 2360 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2e9feb43
CH		 2361 acb->rqbuf_getIndex = 0;
2362 acb->rqbuf_putIndex = 0;
1a4f550a 2363 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
bb263c4e
CH		 2364 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2365 if (acb->fw_flag == FW_DEADLOCK)
ae52e7f0 2366 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 2367 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2368 else
ae52e7f0 2369 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e 2370 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 2371 break;
bb263c4e 2372 }
1c57e86d 2373 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
1a4f550a 2374 uint8_t *pQbuffer = acb->wqbuffer;
bb263c4e
CH		 2375 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2376 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2377 ACB_F_MESSAGE_WQBUFFER_READED);
2e9feb43
CH		 2378 acb->wqbuf_getIndex = 0;
2379 acb->wqbuf_putIndex = 0;
1a4f550a 2380 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
bb263c4e
CH		 2381 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2382 if (acb->fw_flag == FW_DEADLOCK)
2383 pcmdmessagefld->cmdmessage.ReturnCode =
2384 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2385 else
2386 pcmdmessagefld->cmdmessage.ReturnCode =
2387 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 2388 break;
bb263c4e 2389 }
1c57e86d 2390 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
1a4f550a 2391 uint8_t *pQbuffer;
bb263c4e
CH		 2392 arcmsr_clear_iop2drv_rqueue_buffer(acb);
2393 spin_lock_irqsave(&acb->rqbuffer_lock, flags);
2394 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2e9feb43
CH		 2395 acb->rqbuf_getIndex = 0;
2396 acb->rqbuf_putIndex = 0;
1a4f550a
NC		 2397 pQbuffer = acb->rqbuffer;
2398 memset(pQbuffer, 0, sizeof(struct QBUFFER));
bb263c4e
CH		 2399 spin_unlock_irqrestore(&acb->rqbuffer_lock, flags);
2400 spin_lock_irqsave(&acb->wqbuffer_lock, flags);
2401 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED |
2402 ACB_F_MESSAGE_WQBUFFER_READED);
2e9feb43
CH		 2403 acb->wqbuf_getIndex = 0;
2404 acb->wqbuf_putIndex = 0;
1a4f550a
NC		 2405 pQbuffer = acb->wqbuffer;
2406 memset(pQbuffer, 0, sizeof(struct QBUFFER));
bb263c4e
CH		 2407 spin_unlock_irqrestore(&acb->wqbuffer_lock, flags);
2408 if (acb->fw_flag == FW_DEADLOCK)
ae52e7f0 2409 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 2410 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2411 else
ae52e7f0 2412 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e 2413 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d 2414 break;
bb263c4e 2415 }
1c57e86d 2416 case ARCMSR_MESSAGE_RETURN_CODE_3F: {
bb263c4e 2417 if (acb->fw_flag == FW_DEADLOCK)
36b83ded 2418 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 2419 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2420 else
ae52e7f0 2421 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e 2422 ARCMSR_MESSAGE_RETURNCODE_3F;
1c57e86d 2423 break;
bb263c4e 2424 }
1c57e86d 2425 case ARCMSR_MESSAGE_SAY_HELLO: {
1a4f550a 2426 int8_t *hello_string = "Hello! I am ARCMSR";
bb263c4e 2427 if (acb->fw_flag == FW_DEADLOCK)
36b83ded 2428 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 2429 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2430 else
ae52e7f0 2431 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 2432 ARCMSR_MESSAGE_RETURNCODE_OK;
2433 memcpy(pcmdmessagefld->messagedatabuffer,
2434 hello_string, (int16_t)strlen(hello_string));
1c57e86d 2435 break;
bb263c4e
CH		 2436 }
2437 case ARCMSR_MESSAGE_SAY_GOODBYE: {
2438 if (acb->fw_flag == FW_DEADLOCK)
36b83ded 2439 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 2440 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2441 else
2442 pcmdmessagefld->cmdmessage.ReturnCode =
2443 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d
EC		 2444 arcmsr_iop_parking(acb);
2445 break;
bb263c4e
CH		 2446 }
2447 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2448 if (acb->fw_flag == FW_DEADLOCK)
36b83ded 2449 pcmdmessagefld->cmdmessage.ReturnCode =
bb263c4e
CH		 2450 ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON;
2451 else
2452 pcmdmessagefld->cmdmessage.ReturnCode =
2453 ARCMSR_MESSAGE_RETURNCODE_OK;
1c57e86d
EC		 2454 arcmsr_flush_adapter_cache(acb);
2455 break;
bb263c4e 2456 }
1c57e86d
EC		 2457 default:
2458 retvalue = ARCMSR_MESSAGE_FAIL;
bb263c4e
CH		 2459 pr_info("%s: unknown controlcode!\n", __func__);
2460 }
2461message_out:
2462 if (use_sg) {
2463 struct scatterlist *sg = scsi_sglist(cmd);
2464 kunmap_atomic(buffer - sg->offset);
1c57e86d 2465 }
1c57e86d
EC		 2466 return retvalue;
2467}
2468
2469static struct CommandControlBlock *arcmsr_get_freeccb(struct AdapterControlBlock *acb)
2470{
2471 struct list_head *head = &acb->ccb_free_list;
2472 struct CommandControlBlock *ccb = NULL;
ae52e7f0
NC		 2473 unsigned long flags;
2474 spin_lock_irqsave(&acb->ccblist_lock, flags);
1c57e86d
EC		 2475 if (!list_empty(head)) {
2476 ccb = list_entry(head->next, struct CommandControlBlock, list);
ae52e7f0 2477 list_del_init(&ccb->list);
cdd3cb15 2478 }else{
ae52e7f0 2479 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
c10b1d54 2480 return NULL;
1c57e86d 2481 }
ae52e7f0 2482 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 2483 return ccb;
2484}
2485
2486static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2487 struct scsi_cmnd *cmd)
2488{
2489 switch (cmd->cmnd[0]) {
2490 case INQUIRY: {
2491 unsigned char inqdata[36];
2492 char *buffer;
deff2627 2493 struct scatterlist *sg;
1c57e86d
EC		 2494
2495 if (cmd->device->lun) {
2496 cmd->result = (DID_TIME_OUT << 16);
2497 cmd->scsi_done(cmd);
2498 return;
2499 }
2500 inqdata[0] = TYPE_PROCESSOR;
2501 /* Periph Qualifier & Periph Dev Type */
2502 inqdata[1] = 0;
2503 /* rem media bit & Dev Type Modifier */
2504 inqdata[2] = 0;
a1f6e021 2505 /* ISO, ECMA, & ANSI versions */
1c57e86d
EC		 2506 inqdata[4] = 31;
2507 /* length of additional data */
2508 strncpy(&inqdata[8], "Areca ", 8);
2509 /* Vendor Identification */
2510 strncpy(&inqdata[16], "RAID controller ", 16);
2511 /* Product Identification */
2512 strncpy(&inqdata[32], "R001", 4); /* Product Revision */
1c57e86d 2513
deff2627 2514 sg = scsi_sglist(cmd);
77dfce07 2515 buffer = kmap_atomic(sg_page(sg)) + sg->offset;
deff2627 2516
1c57e86d 2517 memcpy(buffer, inqdata, sizeof(inqdata));
deff2627 2518 sg = scsi_sglist(cmd);
77dfce07 2519 kunmap_atomic(buffer - sg->offset);
1c57e86d 2520
1c57e86d
EC		 2521 cmd->scsi_done(cmd);
2522 }
2523 break;
2524 case WRITE_BUFFER:
2525 case READ_BUFFER: {
2526 if (arcmsr_iop_message_xfer(acb, cmd))
2527 cmd->result = (DID_ERROR << 16);
2528 cmd->scsi_done(cmd);
2529 }
2530 break;
2531 default:
2532 cmd->scsi_done(cmd);
2533 }
2534}
2535
f281233d 2536static int arcmsr_queue_command_lck(struct scsi_cmnd *cmd,
1c57e86d
EC		 2537 void (* done)(struct scsi_cmnd *))
2538{
2539 struct Scsi_Host *host = cmd->device->host;
1a4f550a 2540 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) host->hostdata;
1c57e86d
EC		 2541 struct CommandControlBlock *ccb;
2542 int target = cmd->device->id;
2543 int lun = cmd->device->lun;
36b83ded 2544 uint8_t scsicmd = cmd->cmnd[0];
1c57e86d
EC		 2545 cmd->scsi_done = done;
2546 cmd->host_scribble = NULL;
2547 cmd->result = 0;
cdd3cb15
NC		 2548 if ((scsicmd == SYNCHRONIZE_CACHE) ||(scsicmd == SEND_DIAGNOSTIC)){
2549 if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
2550 cmd->result = (DID_NO_CONNECT << 16);
36b83ded
NC		 2551 }
2552 cmd->scsi_done(cmd);
2553 return 0;
2554 }
a1f6e021 2555 if (target == 16) {
1c57e86d
EC		 2556 /* virtual device for iop message transfer */
2557 arcmsr_handle_virtual_command(acb, cmd);
2558 return 0;
2559 }
1c57e86d
EC		 2560 ccb = arcmsr_get_freeccb(acb);
2561 if (!ccb)
2562 return SCSI_MLQUEUE_HOST_BUSY;
cdd3cb15 2563 if (arcmsr_build_ccb( acb, ccb, cmd ) == FAILED) {
76d78300
NC		 2564 cmd->result = (DID_ERROR << 16) | (RESERVATION_CONFLICT << 1);
2565 cmd->scsi_done(cmd);
2566 return 0;
2567 }
1c57e86d
EC		 2568 arcmsr_post_ccb(acb, ccb);
2569 return 0;
2570}
2571
f281233d
JG		 2572static DEF_SCSI_QCMD(arcmsr_queue_command)
2573
626fa32c 2574static bool arcmsr_hbaA_get_config(struct AdapterControlBlock *acb)
1c57e86d 2575{
80da1adb 2576 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d
EC		 2577 char *acb_firm_model = acb->firm_model;
2578 char *acb_firm_version = acb->firm_version;
36b83ded 2579 char *acb_device_map = acb->device_map;
80da1adb
AV		 2580 char __iomem *iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]);
2581 char __iomem *iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]);
cdd3cb15 2582 char __iomem *iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]);
1c57e86d 2583 int count;
1c57e86d 2584 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
626fa32c 2585 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1a4f550a
NC		 2586 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2587 miscellaneous data' timeout \n", acb->host->host_no);
ae52e7f0 2588 return false;
1a4f550a 2589 }
1c57e86d 2590 count = 8;
cdd3cb15 2591 while (count){
1c57e86d
EC		 2592 *acb_firm_model = readb(iop_firm_model);
2593 acb_firm_model++;
2594 iop_firm_model++;
2595 count--;
2596 }
1a4f550a 2597
1c57e86d 2598 count = 16;
cdd3cb15 2599 while (count){
1c57e86d
EC		 2600 *acb_firm_version = readb(iop_firm_version);
2601 acb_firm_version++;
2602 iop_firm_version++;
2603 count--;
2604 }
1a4f550a 2605
cdd3cb15
NC		 2606 count=16;
2607 while(count){
2608 *acb_device_map = readb(iop_device_map);
2609 acb_device_map++;
2610 iop_device_map++;
2611 count--;
2612 }
a2c89bbc 2613 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
ae52e7f0 2614 acb->host->host_no,
a2c89bbc
CH		 2615 acb->firm_model,
2616 acb->firm_version);
cdd3cb15 2617 acb->signature = readl(&reg->message_rwbuffer[0]);
1c57e86d
EC		 2618 acb->firm_request_len = readl(&reg->message_rwbuffer[1]);
2619 acb->firm_numbers_queue = readl(&reg->message_rwbuffer[2]);
2620 acb->firm_sdram_size = readl(&reg->message_rwbuffer[3]);
2621 acb->firm_hd_channels = readl(&reg->message_rwbuffer[4]);
ae52e7f0
NC		 2622 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2623 return true;
1c57e86d 2624}
626fa32c 2625static bool arcmsr_hbaB_get_config(struct AdapterControlBlock *acb)
1a4f550a 2626{
80da1adb 2627 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0
NC		 2628 struct pci_dev *pdev = acb->pdev;
2629 void *dma_coherent;
2630 dma_addr_t dma_coherent_handle;
1a4f550a
NC		 2631 char *acb_firm_model = acb->firm_model;
2632 char *acb_firm_version = acb->firm_version;
36b83ded 2633 char *acb_device_map = acb->device_map;
ae52e7f0 2634 char __iomem *iop_firm_model;
1a4f550a 2635 /*firm_model,15,60-67*/
ae52e7f0 2636 char __iomem *iop_firm_version;
1a4f550a 2637 /*firm_version,17,68-83*/
ae52e7f0 2638 char __iomem *iop_device_map;
36b83ded 2639 /*firm_version,21,84-99*/
1a4f550a 2640 int count;
6e38adfc
CH		 2641
2642 acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_B), 32);
2643 dma_coherent = dma_alloc_coherent(&pdev->dev, acb->roundup_ccbsize,
2644 &dma_coherent_handle, GFP_KERNEL);
cdd3cb15 2645 if (!dma_coherent){
6e38adfc
CH		 2646 printk(KERN_NOTICE
2647 "arcmsr%d: dma_alloc_coherent got error for hbb mu\n",
2648 acb->host->host_no);
ae52e7f0
NC		 2649 return false;
2650 }
626fa32c 2651 acb->dma_coherent_handle2 = dma_coherent_handle;
6e38adfc 2652 acb->dma_coherent2 = dma_coherent;
ae52e7f0
NC		 2653 reg = (struct MessageUnit_B *)dma_coherent;
2654 acb->pmuB = reg;
cdd3cb15 2655 reg->drv2iop_doorbell= (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL);
ae52e7f0
NC		 2656 reg->drv2iop_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_DRV2IOP_DOORBELL_MASK);
2657 reg->iop2drv_doorbell = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL);
2658 reg->iop2drv_doorbell_mask = (uint32_t __iomem *)((unsigned long)acb->mem_base0 + ARCMSR_IOP2DRV_DOORBELL_MASK);
2659 reg->message_wbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_WBUFFER);
2660 reg->message_rbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RBUFFER);
2661 reg->message_rwbuffer = (uint32_t __iomem *)((unsigned long)acb->mem_base1 + ARCMSR_MESSAGE_RWBUFFER);
2662 iop_firm_model = (char __iomem *)(&reg->message_rwbuffer[15]); /*firm_model,15,60-67*/
2663 iop_firm_version = (char __iomem *)(&reg->message_rwbuffer[17]); /*firm_version,17,68-83*/
2664 iop_device_map = (char __iomem *)(&reg->message_rwbuffer[21]); /*firm_version,21,84-99*/
2665
2666 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
626fa32c 2667 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1a4f550a
NC		 2668 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2669 miscellaneous data' timeout \n", acb->host->host_no);
ae52e7f0 2670 return false;
1a4f550a 2671 }
1a4f550a 2672 count = 8;
cdd3cb15 2673 while (count){
1a4f550a
NC		 2674 *acb_firm_model = readb(iop_firm_model);
2675 acb_firm_model++;
2676 iop_firm_model++;
2677 count--;
2678 }
1a4f550a 2679 count = 16;
cdd3cb15 2680 while (count){
1a4f550a
NC		 2681 *acb_firm_version = readb(iop_firm_version);
2682 acb_firm_version++;
2683 iop_firm_version++;
2684 count--;
2685 }
2686
cdd3cb15
NC		 2687 count = 16;
2688 while(count){
2689 *acb_device_map = readb(iop_device_map);
2690 acb_device_map++;
2691 iop_device_map++;
2692 count--;
2693 }
2694
a2c89bbc 2695 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
cdd3cb15 2696 acb->host->host_no,
a2c89bbc
CH		 2697 acb->firm_model,
2698 acb->firm_version);
1a4f550a 2699
ae52e7f0 2700 acb->signature = readl(&reg->message_rwbuffer[1]);
cdd3cb15 2701 /*firm_signature,1,00-03*/
ae52e7f0 2702 acb->firm_request_len = readl(&reg->message_rwbuffer[2]);
1a4f550a 2703 /*firm_request_len,1,04-07*/
ae52e7f0 2704 acb->firm_numbers_queue = readl(&reg->message_rwbuffer[3]);
1a4f550a 2705 /*firm_numbers_queue,2,08-11*/
ae52e7f0 2706 acb->firm_sdram_size = readl(&reg->message_rwbuffer[4]);
1a4f550a 2707 /*firm_sdram_size,3,12-15*/
ae52e7f0 2708 acb->firm_hd_channels = readl(&reg->message_rwbuffer[5]);
1a4f550a 2709 /*firm_ide_channels,4,16-19*/
ae52e7f0
NC		 2710 acb->firm_cfg_version = readl(&reg->message_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2711 /*firm_ide_channels,4,16-19*/
2712 return true;
1a4f550a 2713}
cdd3cb15 2714
626fa32c 2715static bool arcmsr_hbaC_get_config(struct AdapterControlBlock *pACB)
cdd3cb15
NC		 2716{
2717 uint32_t intmask_org, Index, firmware_state = 0;
c10b1d54 2718 struct MessageUnit_C __iomem *reg = pACB->pmuC;
cdd3cb15
NC		 2719 char *acb_firm_model = pACB->firm_model;
2720 char *acb_firm_version = pACB->firm_version;
c10b1d54
CH		 2721 char __iomem *iop_firm_model = (char __iomem *)(&reg->msgcode_rwbuffer[15]); /*firm_model,15,60-67*/
2722 char __iomem *iop_firm_version = (char __iomem *)(&reg->msgcode_rwbuffer[17]); /*firm_version,17,68-83*/
cdd3cb15
NC		 2723 int count;
2724 /* disable all outbound interrupt */
2725 intmask_org = readl(&reg->host_int_mask); /* disable outbound message0 int */
2726 writel(intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE, &reg->host_int_mask);
2727 /* wait firmware ready */
2728 do {
2729 firmware_state = readl(&reg->outbound_msgaddr1);
2730 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
2731 /* post "get config" instruction */
2732 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
2733 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
2734 /* wait message ready */
2735 for (Index = 0; Index < 2000; Index++) {
2736 if (readl(&reg->outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
2737 writel(ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR, &reg->outbound_doorbell_clear);/*clear interrupt*/
2738 break;
2739 }
2740 udelay(10);
2741 } /*max 1 seconds*/
2742 if (Index >= 2000) {
2743 printk(KERN_NOTICE "arcmsr%d: wait 'get adapter firmware \
2744 miscellaneous data' timeout \n", pACB->host->host_no);
2745 return false;
2746 }
2747 count = 8;
2748 while (count) {
2749 *acb_firm_model = readb(iop_firm_model);
2750 acb_firm_model++;
2751 iop_firm_model++;
2752 count--;
2753 }
2754 count = 16;
2755 while (count) {
2756 *acb_firm_version = readb(iop_firm_version);
2757 acb_firm_version++;
2758 iop_firm_version++;
2759 count--;
2760 }
a2c89bbc 2761 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
cdd3cb15 2762 pACB->host->host_no,
a2c89bbc
CH		 2763 pACB->firm_model,
2764 pACB->firm_version);
cdd3cb15
NC		 2765 pACB->firm_request_len = readl(&reg->msgcode_rwbuffer[1]); /*firm_request_len,1,04-07*/
2766 pACB->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[2]); /*firm_numbers_queue,2,08-11*/
2767 pACB->firm_sdram_size = readl(&reg->msgcode_rwbuffer[3]); /*firm_sdram_size,3,12-15*/
2768 pACB->firm_hd_channels = readl(&reg->msgcode_rwbuffer[4]); /*firm_ide_channels,4,16-19*/
2769 pACB->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]); /*firm_cfg_version,25,100-103*/
2770 /*all interrupt service will be enable at arcmsr_iop_init*/
2771 return true;
2772}
5b37479a
CH		 2773
2774static bool arcmsr_hbaD_get_config(struct AdapterControlBlock *acb)
2775{
2776 char *acb_firm_model = acb->firm_model;
2777 char *acb_firm_version = acb->firm_version;
2778 char *acb_device_map = acb->device_map;
2779 char __iomem *iop_firm_model;
2780 char __iomem *iop_firm_version;
2781 char __iomem *iop_device_map;
2782 u32 count;
3b8155d5 2783 struct MessageUnit_D *reg;
5b37479a
CH		 2784 void *dma_coherent2;
2785 dma_addr_t dma_coherent_handle2;
2786 struct pci_dev *pdev = acb->pdev;
2787
2788 acb->roundup_ccbsize = roundup(sizeof(struct MessageUnit_D), 32);
2789 dma_coherent2 = dma_alloc_coherent(&pdev->dev, acb->roundup_ccbsize,
2790 &dma_coherent_handle2, GFP_KERNEL);
2791 if (!dma_coherent2) {
2792 pr_notice("DMA allocation failed...\n");
2793 return false;
2794 }
2795 memset(dma_coherent2, 0, acb->roundup_ccbsize);
2796 acb->dma_coherent_handle2 = dma_coherent_handle2;
2797 acb->dma_coherent2 = dma_coherent2;
2798 reg = (struct MessageUnit_D *)dma_coherent2;
2799 acb->pmuD = reg;
2800 reg->chip_id = acb->mem_base0 + ARCMSR_ARC1214_CHIP_ID;
2801 reg->cpu_mem_config = acb->mem_base0 +
2802 ARCMSR_ARC1214_CPU_MEMORY_CONFIGURATION;
2803 reg->i2o_host_interrupt_mask = acb->mem_base0 +
2804 ARCMSR_ARC1214_I2_HOST_INTERRUPT_MASK;
2805 reg->sample_at_reset = acb->mem_base0 + ARCMSR_ARC1214_SAMPLE_RESET;
2806 reg->reset_request = acb->mem_base0 + ARCMSR_ARC1214_RESET_REQUEST;
2807 reg->host_int_status = acb->mem_base0 +
2808 ARCMSR_ARC1214_MAIN_INTERRUPT_STATUS;
2809 reg->pcief0_int_enable = acb->mem_base0 +
2810 ARCMSR_ARC1214_PCIE_F0_INTERRUPT_ENABLE;
2811 reg->inbound_msgaddr0 = acb->mem_base0 +
2812 ARCMSR_ARC1214_INBOUND_MESSAGE0;
2813 reg->inbound_msgaddr1 = acb->mem_base0 +
2814 ARCMSR_ARC1214_INBOUND_MESSAGE1;
2815 reg->outbound_msgaddr0 = acb->mem_base0 +
2816 ARCMSR_ARC1214_OUTBOUND_MESSAGE0;
2817 reg->outbound_msgaddr1 = acb->mem_base0 +
2818 ARCMSR_ARC1214_OUTBOUND_MESSAGE1;
2819 reg->inbound_doorbell = acb->mem_base0 +
2820 ARCMSR_ARC1214_INBOUND_DOORBELL;
2821 reg->outbound_doorbell = acb->mem_base0 +
2822 ARCMSR_ARC1214_OUTBOUND_DOORBELL;
2823 reg->outbound_doorbell_enable = acb->mem_base0 +
2824 ARCMSR_ARC1214_OUTBOUND_DOORBELL_ENABLE;
2825 reg->inboundlist_base_low = acb->mem_base0 +
2826 ARCMSR_ARC1214_INBOUND_LIST_BASE_LOW;
2827 reg->inboundlist_base_high = acb->mem_base0 +
2828 ARCMSR_ARC1214_INBOUND_LIST_BASE_HIGH;
2829 reg->inboundlist_write_pointer = acb->mem_base0 +
2830 ARCMSR_ARC1214_INBOUND_LIST_WRITE_POINTER;
2831 reg->outboundlist_base_low = acb->mem_base0 +
2832 ARCMSR_ARC1214_OUTBOUND_LIST_BASE_LOW;
2833 reg->outboundlist_base_high = acb->mem_base0 +
2834 ARCMSR_ARC1214_OUTBOUND_LIST_BASE_HIGH;
2835 reg->outboundlist_copy_pointer = acb->mem_base0 +
2836 ARCMSR_ARC1214_OUTBOUND_LIST_COPY_POINTER;
2837 reg->outboundlist_read_pointer = acb->mem_base0 +
2838 ARCMSR_ARC1214_OUTBOUND_LIST_READ_POINTER;
2839 reg->outboundlist_interrupt_cause = acb->mem_base0 +
2840 ARCMSR_ARC1214_OUTBOUND_INTERRUPT_CAUSE;
2841 reg->outboundlist_interrupt_enable = acb->mem_base0 +
2842 ARCMSR_ARC1214_OUTBOUND_INTERRUPT_ENABLE;
2843 reg->message_wbuffer = acb->mem_base0 + ARCMSR_ARC1214_MESSAGE_WBUFFER;
2844 reg->message_rbuffer = acb->mem_base0 + ARCMSR_ARC1214_MESSAGE_RBUFFER;
2845 reg->msgcode_rwbuffer = acb->mem_base0 +
2846 ARCMSR_ARC1214_MESSAGE_RWBUFFER;
2847 iop_firm_model = (char __iomem *)(&reg->msgcode_rwbuffer[15]);
2848 iop_firm_version = (char __iomem *)(&reg->msgcode_rwbuffer[17]);
2849 iop_device_map = (char __iomem *)(&reg->msgcode_rwbuffer[21]);
2850 if (readl(acb->pmuD->outbound_doorbell) &
2851 ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE) {
2852 writel(ARCMSR_ARC1214_IOP2DRV_MESSAGE_CMD_DONE,
2853 acb->pmuD->outbound_doorbell);/*clear interrupt*/
2854 }
2855 /* post "get config" instruction */
2856 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, reg->inbound_msgaddr0);
2857 /* wait message ready */
2858 if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
2859 pr_notice("arcmsr%d: wait get adapter firmware "
2860 "miscellaneous data timeout\n", acb->host->host_no);
2861 dma_free_coherent(&acb->pdev->dev, acb->roundup_ccbsize,
2862 acb->dma_coherent2, acb->dma_coherent_handle2);
2863 return false;
2864 }
2865 count = 8;
2866 while (count) {
2867 *acb_firm_model = readb(iop_firm_model);
2868 acb_firm_model++;
2869 iop_firm_model++;
2870 count--;
2871 }
2872 count = 16;
2873 while (count) {
2874 *acb_firm_version = readb(iop_firm_version);
2875 acb_firm_version++;
2876 iop_firm_version++;
2877 count--;
2878 }
2879 count = 16;
2880 while (count) {
2881 *acb_device_map = readb(iop_device_map);
2882 acb_device_map++;
2883 iop_device_map++;
2884 count--;
2885 }
2886 acb->signature = readl(&reg->msgcode_rwbuffer[1]);
2887 /*firm_signature,1,00-03*/
2888 acb->firm_request_len = readl(&reg->msgcode_rwbuffer[2]);
2889 /*firm_request_len,1,04-07*/
2890 acb->firm_numbers_queue = readl(&reg->msgcode_rwbuffer[3]);
2891 /*firm_numbers_queue,2,08-11*/
2892 acb->firm_sdram_size = readl(&reg->msgcode_rwbuffer[4]);
2893 /*firm_sdram_size,3,12-15*/
2894 acb->firm_hd_channels = readl(&reg->msgcode_rwbuffer[5]);
2895 /*firm_hd_channels,4,16-19*/
2896 acb->firm_cfg_version = readl(&reg->msgcode_rwbuffer[25]);
2897 pr_notice("Areca RAID Controller%d: Model %s, F/W %s\n",
2898 acb->host->host_no,
2899 acb->firm_model,
2900 acb->firm_version);
2901 return true;
2902}
2903
ae52e7f0 2904static bool arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
1a4f550a 2905{
3df824af
CH		 2906 bool rtn = false;
2907
2908 switch (acb->adapter_type) {
2909 case ACB_ADAPTER_TYPE_A:
626fa32c 2910 rtn = arcmsr_hbaA_get_config(acb);
3df824af
CH		 2911 break;
2912 case ACB_ADAPTER_TYPE_B:
626fa32c 2913 rtn = arcmsr_hbaB_get_config(acb);
3df824af
CH		 2914 break;
2915 case ACB_ADAPTER_TYPE_C:
626fa32c 2916 rtn = arcmsr_hbaC_get_config(acb);
3df824af 2917 break;
5b37479a
CH		 2918 case ACB_ADAPTER_TYPE_D:
2919 rtn = arcmsr_hbaD_get_config(acb);
2920 break;
3df824af
CH		 2921 default:
2922 break;
2923 }
2924 if (acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD)
2925 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD;
cdd3cb15 2926 else
3df824af
CH		 2927 acb->maxOutstanding = acb->firm_numbers_queue - 1;
2928 acb->host->can_queue = acb->maxOutstanding;
2929 return rtn;
1a4f550a
NC		 2930}
2931
626fa32c 2932static int arcmsr_hbaA_polling_ccbdone(struct AdapterControlBlock *acb,
1c57e86d
EC		 2933 struct CommandControlBlock *poll_ccb)
2934{
80da1adb 2935 struct MessageUnit_A __iomem *reg = acb->pmuA;
1c57e86d 2936 struct CommandControlBlock *ccb;
ae52e7f0 2937 struct ARCMSR_CDB *arcmsr_cdb;
1c57e86d 2938 uint32_t flag_ccb, outbound_intstatus, poll_ccb_done = 0, poll_count = 0;
ae52e7f0 2939 int rtn;
cdd3cb15 2940 bool error;
1a4f550a 2941 polling_hba_ccb_retry:
1c57e86d 2942 poll_count++;
1a4f550a 2943 outbound_intstatus = readl(&reg->outbound_intstatus) & acb->outbound_int_enable;
1c57e86d
EC		 2944 writel(outbound_intstatus, &reg->outbound_intstatus);/*clear interrupt*/
2945 while (1) {
2946 if ((flag_ccb = readl(&reg->outbound_queueport)) == 0xFFFFFFFF) {
cdd3cb15 2947 if (poll_ccb_done){
ae52e7f0 2948 rtn = SUCCESS;
1c57e86d 2949 break;
cdd3cb15
NC		 2950 }else {
2951 msleep(25);
2952 if (poll_count > 100){
ae52e7f0 2953 rtn = FAILED;
1c57e86d 2954 break;
ae52e7f0 2955 }
1a4f550a 2956 goto polling_hba_ccb_retry;
1c57e86d
EC		 2957 }
2958 }
ae52e7f0
NC		 2959 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
2960 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
cab5aece 2961 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
1a4f550a
NC		 2962 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
2963 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
2964 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
1c57e86d
EC		 2965 " poll command abort successfully \n"
2966 , acb->host->host_no
2967 , ccb->pcmd->device->id
9cb78c16 2968 , (u32)ccb->pcmd->device->lun
1c57e86d
EC		 2969 , ccb);
2970 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 2971 arcmsr_ccb_complete(ccb);
1c57e86d
EC		 2972 continue;
2973 }
1a4f550a
NC		 2974 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
2975 " command done ccb = '0x%p'"
a1f6e021 2976 "ccboutstandingcount = %d \n"
1c57e86d
EC		 2977 , acb->host->host_no
2978 , ccb
2979 , atomic_read(&acb->ccboutstandingcount));
2980 continue;
cdd3cb15
NC		 2981 }
2982 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
2983 arcmsr_report_ccb_state(acb, ccb, error);
1a4f550a 2984 }
ae52e7f0
NC		 2985 return rtn;
2986}
1a4f550a 2987
626fa32c 2988static int arcmsr_hbaB_polling_ccbdone(struct AdapterControlBlock *acb,
1a4f550a
NC		 2989 struct CommandControlBlock *poll_ccb)
2990{
cdd3cb15 2991 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 2992 struct ARCMSR_CDB *arcmsr_cdb;
cdd3cb15
NC		 2993 struct CommandControlBlock *ccb;
2994 uint32_t flag_ccb, poll_ccb_done = 0, poll_count = 0;
ae52e7f0 2995 int index, rtn;
cdd3cb15 2996 bool error;
1a4f550a 2997 polling_hbb_ccb_retry:
97b99127 2998
cdd3cb15
NC		 2999 poll_count++;
3000 /* clear doorbell interrupt */
ae52e7f0 3001 writel(ARCMSR_DOORBELL_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
cdd3cb15
NC		 3002 while(1){
3003 index = reg->doneq_index;
c10b1d54
CH		 3004 flag_ccb = reg->done_qbuffer[index];
3005 if (flag_ccb == 0) {
cdd3cb15 3006 if (poll_ccb_done){
ae52e7f0 3007 rtn = SUCCESS;
cdd3cb15
NC		 3008 break;
3009 }else {
3010 msleep(25);
3011 if (poll_count > 100){
ae52e7f0 3012 rtn = FAILED;
cdd3cb15 3013 break;
1c57e86d 3014 }
cdd3cb15 3015 goto polling_hbb_ccb_retry;
1a4f550a 3016 }
cdd3cb15 3017 }
c10b1d54 3018 reg->done_qbuffer[index] = 0;
cdd3cb15
NC		 3019 index++;
3020 /*if last index number set it to 0 */
3021 index %= ARCMSR_MAX_HBB_POSTQUEUE;
3022 reg->doneq_index = index;
3023 /* check if command done with no error*/
ae52e7f0
NC		 3024 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + (flag_ccb << 5));
3025 ccb = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
cab5aece 3026 poll_ccb_done |= (ccb == poll_ccb) ? 1 : 0;
cdd3cb15
NC		 3027 if ((ccb->acb != acb) || (ccb->startdone != ARCMSR_CCB_START)) {
3028 if ((ccb->startdone == ARCMSR_CCB_ABORTED) || (ccb == poll_ccb)) {
ae52e7f0
NC		 3029 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3030 " poll command abort successfully \n"
cdd3cb15
NC		 3031 ,acb->host->host_no
3032 ,ccb->pcmd->device->id
9cb78c16 3033 ,(u32)ccb->pcmd->device->lun
cdd3cb15
NC		 3034 ,ccb);
3035 ccb->pcmd->result = DID_ABORT << 16;
ae52e7f0 3036 arcmsr_ccb_complete(ccb);
cdd3cb15
NC		 3037 continue;
3038 }
3039 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3040 " command done ccb = '0x%p'"
3041 "ccboutstandingcount = %d \n"
3042 , acb->host->host_no
3043 , ccb
3044 , atomic_read(&acb->ccboutstandingcount));
3045 continue;
3046 }
3047 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE0) ? true : false;
3048 arcmsr_report_ccb_state(acb, ccb, error);
3049 }
3050 return rtn;
3051}
3052
626fa32c
CH		 3053static int arcmsr_hbaC_polling_ccbdone(struct AdapterControlBlock *acb,
3054 struct CommandControlBlock *poll_ccb)
cdd3cb15 3055{
c10b1d54 3056 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15
NC		 3057 uint32_t flag_ccb, ccb_cdb_phy;
3058 struct ARCMSR_CDB *arcmsr_cdb;
3059 bool error;
3060 struct CommandControlBlock *pCCB;
3061 uint32_t poll_ccb_done = 0, poll_count = 0;
3062 int rtn;
3063polling_hbc_ccb_retry:
3064 poll_count++;
3065 while (1) {
3066 if ((readl(&reg->host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) == 0) {
3067 if (poll_ccb_done) {
3068 rtn = SUCCESS;
3069 break;
3070 } else {
3071 msleep(25);
3072 if (poll_count > 100) {
3073 rtn = FAILED;
3074 break;
1c57e86d 3075 }
cdd3cb15
NC		 3076 goto polling_hbc_ccb_retry;
3077 }
3078 }
3079 flag_ccb = readl(&reg->outbound_queueport_low);
3080 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
3081 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset + ccb_cdb_phy);/*frame must be 32 bytes aligned*/
3082 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock, arcmsr_cdb);
cab5aece 3083 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
cdd3cb15
NC		 3084 /* check ifcommand done with no error*/
3085 if ((pCCB->acb != acb) || (pCCB->startdone != ARCMSR_CCB_START)) {
3086 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3087 printk(KERN_NOTICE "arcmsr%d: scsi id = %d lun = %d ccb = '0x%p'"
3088 " poll command abort successfully \n"
1c57e86d 3089 , acb->host->host_no
cdd3cb15 3090 , pCCB->pcmd->device->id
9cb78c16 3091 , (u32)pCCB->pcmd->device->lun
cdd3cb15
NC		 3092 , pCCB);
3093 pCCB->pcmd->result = DID_ABORT << 16;
3094 arcmsr_ccb_complete(pCCB);
1a4f550a 3095 continue;
cdd3cb15
NC		 3096 }
3097 printk(KERN_NOTICE "arcmsr%d: polling get an illegal ccb"
3098 " command done ccb = '0x%p'"
3099 "ccboutstandingcount = %d \n"
3100 , acb->host->host_no
3101 , pCCB
3102 , atomic_read(&acb->ccboutstandingcount));
3103 continue;
ae52e7f0 3104 }
cdd3cb15
NC		 3105 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1) ? true : false;
3106 arcmsr_report_ccb_state(acb, pCCB, error);
3107 }
ae52e7f0 3108 return rtn;
1a4f550a 3109}
5b37479a
CH		 3110
3111static int arcmsr_hbaD_polling_ccbdone(struct AdapterControlBlock *acb,
3112 struct CommandControlBlock *poll_ccb)
3113{
3114 bool error;
3115 uint32_t poll_ccb_done = 0, poll_count = 0, flag_ccb, ccb_cdb_phy;
3b8155d5 3116 int rtn, doneq_index, index_stripped, outbound_write_pointer, toggle;
5b37479a
CH		 3117 unsigned long flags;
3118 struct ARCMSR_CDB *arcmsr_cdb;
3119 struct CommandControlBlock *pCCB;
3120 struct MessageUnit_D *pmu = acb->pmuD;
3121
3122polling_hbaD_ccb_retry:
3123 poll_count++;
3124 while (1) {
3b8155d5 3125 spin_lock_irqsave(&acb->doneq_lock, flags);
5b37479a
CH		 3126 outbound_write_pointer = pmu->done_qbuffer[0].addressLow + 1;
3127 doneq_index = pmu->doneq_index;
3128 if ((outbound_write_pointer & 0xFFF) == (doneq_index & 0xFFF)) {
3b8155d5 3129 spin_unlock_irqrestore(&acb->doneq_lock, flags);
5b37479a
CH		 3130 if (poll_ccb_done) {
3131 rtn = SUCCESS;
3132 break;
3133 } else {
3134 msleep(25);
3135 if (poll_count > 40) {
3136 rtn = FAILED;
3137 break;
3138 }
3139 goto polling_hbaD_ccb_retry;
3140 }
3141 }
3b8155d5
CH		 3142 toggle = doneq_index & 0x4000;
3143 index_stripped = (doneq_index & 0xFFF) + 1;
3144 index_stripped %= ARCMSR_MAX_ARC1214_DONEQUEUE;
3145 pmu->doneq_index = index_stripped ? (index_stripped | toggle) :
3146 ((toggle ^ 0x4000) + 1);
5b37479a 3147 doneq_index = pmu->doneq_index;
3b8155d5 3148 spin_unlock_irqrestore(&acb->doneq_lock, flags);
5b37479a
CH		 3149 flag_ccb = pmu->done_qbuffer[doneq_index & 0xFFF].addressLow;
3150 ccb_cdb_phy = (flag_ccb & 0xFFFFFFF0);
3151 arcmsr_cdb = (struct ARCMSR_CDB *)(acb->vir2phy_offset +
3152 ccb_cdb_phy);
3153 pCCB = container_of(arcmsr_cdb, struct CommandControlBlock,
3154 arcmsr_cdb);
3155 poll_ccb_done |= (pCCB == poll_ccb) ? 1 : 0;
3156 if ((pCCB->acb != acb) ||
3157 (pCCB->startdone != ARCMSR_CCB_START)) {
3158 if (pCCB->startdone == ARCMSR_CCB_ABORTED) {
3159 pr_notice("arcmsr%d: scsi id = %d "
3160 "lun = %d ccb = '0x%p' poll command "
3161 "abort successfully\n"
3162 , acb->host->host_no
3163 , pCCB->pcmd->device->id
3164 , (u32)pCCB->pcmd->device->lun
3165 , pCCB);
3166 pCCB->pcmd->result = DID_ABORT << 16;
3167 arcmsr_ccb_complete(pCCB);
3168 continue;
3169 }
3170 pr_notice("arcmsr%d: polling an illegal "
3171 "ccb command done ccb = '0x%p' "
3172 "ccboutstandingcount = %d\n"
3173 , acb->host->host_no
3174 , pCCB
3175 , atomic_read(&acb->ccboutstandingcount));
3176 continue;
3177 }
3178 error = (flag_ccb & ARCMSR_CCBREPLY_FLAG_ERROR_MODE1)
3179 ? true : false;
3180 arcmsr_report_ccb_state(acb, pCCB, error);
3181 }
3182 return rtn;
3183}
3184
ae52e7f0 3185static int arcmsr_polling_ccbdone(struct AdapterControlBlock *acb,
1a4f550a
NC		 3186 struct CommandControlBlock *poll_ccb)
3187{
ae52e7f0 3188 int rtn = 0;
1a4f550a
NC		 3189 switch (acb->adapter_type) {
3190
3191 case ACB_ADAPTER_TYPE_A: {
626fa32c 3192 rtn = arcmsr_hbaA_polling_ccbdone(acb, poll_ccb);
1a4f550a
NC		 3193 }
3194 break;
3195
3196 case ACB_ADAPTER_TYPE_B: {
626fa32c 3197 rtn = arcmsr_hbaB_polling_ccbdone(acb, poll_ccb);
1c57e86d 3198 }
cdd3cb15
NC		 3199 break;
3200 case ACB_ADAPTER_TYPE_C: {
626fa32c 3201 rtn = arcmsr_hbaC_polling_ccbdone(acb, poll_ccb);
cdd3cb15 3202 }
5b37479a
CH		 3203 break;
3204 case ACB_ADAPTER_TYPE_D:
3205 rtn = arcmsr_hbaD_polling_ccbdone(acb, poll_ccb);
3206 break;
1c57e86d 3207 }
ae52e7f0 3208 return rtn;
1c57e86d 3209}
1a4f550a
NC		 3210
3211static int arcmsr_iop_confirm(struct AdapterControlBlock *acb)
a1f6e021 3212{
ae52e7f0 3213 uint32_t cdb_phyaddr, cdb_phyaddr_hi32;
6e38adfc 3214 dma_addr_t dma_coherent_handle;
e2c70425 3215
1a4f550a
NC		 3216 /*
3217 ********************************************************************
3218 ** here we need to tell iop 331 our freeccb.HighPart
3219 ** if freeccb.HighPart is not zero
3220 ********************************************************************
3221 */
6e38adfc
CH		 3222 switch (acb->adapter_type) {
3223 case ACB_ADAPTER_TYPE_B:
5b37479a 3224 case ACB_ADAPTER_TYPE_D:
6e38adfc
CH		 3225 dma_coherent_handle = acb->dma_coherent_handle2;
3226 break;
3227 default:
3228 dma_coherent_handle = acb->dma_coherent_handle;
3229 break;
3230 }
3231 cdb_phyaddr = lower_32_bits(dma_coherent_handle);
3232 cdb_phyaddr_hi32 = upper_32_bits(dma_coherent_handle);
cdd3cb15 3233 acb->cdb_phyaddr_hi32 = cdb_phyaddr_hi32;
1a4f550a
NC		 3234 /*
3235 ***********************************************************************
3236 ** if adapter type B, set window of "post command Q"
3237 ***********************************************************************
3238 */
3239 switch (acb->adapter_type) {
3240
3241 case ACB_ADAPTER_TYPE_A: {
ae52e7f0 3242 if (cdb_phyaddr_hi32 != 0) {
80da1adb 3243 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 3244 writel(ARCMSR_SIGNATURE_SET_CONFIG, \
3245 &reg->message_rwbuffer[0]);
ae52e7f0 3246 writel(cdb_phyaddr_hi32, &reg->message_rwbuffer[1]);
1a4f550a
NC		 3247 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, \
3248 &reg->inbound_msgaddr0);
626fa32c 3249 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1a4f550a
NC		 3250 printk(KERN_NOTICE "arcmsr%d: ""set ccb high \
3251 part physical address timeout\n",
3252 acb->host->host_no);
3253 return 1;
a1f6e021 3254 }
1a4f550a
NC		 3255 }
3256 }
3257 break;
a1f6e021 3258
1a4f550a 3259 case ACB_ADAPTER_TYPE_B: {
80da1adb 3260 uint32_t __iomem *rwbuffer;
a1f6e021 3261
80da1adb 3262 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a
NC		 3263 reg->postq_index = 0;
3264 reg->doneq_index = 0;
ae52e7f0 3265 writel(ARCMSR_MESSAGE_SET_POST_WINDOW, reg->drv2iop_doorbell);
626fa32c 3266 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1a4f550a
NC		 3267 printk(KERN_NOTICE "arcmsr%d:can not set diver mode\n", \
3268 acb->host->host_no);
3269 return 1;
3270 }
ae52e7f0 3271 rwbuffer = reg->message_rwbuffer;
1a4f550a
NC		 3272 /* driver "set config" signature */
3273 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
3274 /* normal should be zero */
ae52e7f0 3275 writel(cdb_phyaddr_hi32, rwbuffer++);
1a4f550a 3276 /* postQ size (256 + 8)*4 */
6e38adfc 3277 writel(cdb_phyaddr, rwbuffer++);
1a4f550a 3278 /* doneQ size (256 + 8)*4 */
6e38adfc 3279 writel(cdb_phyaddr + 1056, rwbuffer++);
1a4f550a
NC		 3280 /* ccb maxQ size must be --> [(256 + 8)*4]*/
3281 writel(1056, rwbuffer);
3282
ae52e7f0 3283 writel(ARCMSR_MESSAGE_SET_CONFIG, reg->drv2iop_doorbell);
626fa32c 3284 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1a4f550a
NC		 3285 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
3286 timeout \n",acb->host->host_no);
3287 return 1;
3288 }
a5849726 3289 writel(ARCMSR_MESSAGE_START_DRIVER_MODE, reg->drv2iop_doorbell);
626fa32c 3290 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
a5849726
CH		 3291 pr_err("arcmsr%d: can't set driver mode.\n",
3292 acb->host->host_no);
3293 return 1;
3294 }
1a4f550a
NC		 3295 }
3296 break;
cdd3cb15
NC		 3297 case ACB_ADAPTER_TYPE_C: {
3298 if (cdb_phyaddr_hi32 != 0) {
c10b1d54 3299 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15 3300
8b7eb86f
TH		 3301 printk(KERN_NOTICE "arcmsr%d: cdb_phyaddr_hi32=0x%x\n",
3302 acb->adapter_index, cdb_phyaddr_hi32);
cdd3cb15
NC		 3303 writel(ARCMSR_SIGNATURE_SET_CONFIG, &reg->msgcode_rwbuffer[0]);
3304 writel(cdb_phyaddr_hi32, &reg->msgcode_rwbuffer[1]);
3305 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, &reg->inbound_msgaddr0);
3306 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
626fa32c 3307 if (!arcmsr_hbaC_wait_msgint_ready(acb)) {
cdd3cb15
NC		 3308 printk(KERN_NOTICE "arcmsr%d: 'set command Q window' \
3309 timeout \n", acb->host->host_no);
3310 return 1;
3311 }
3312 }
3313 }
5b37479a
CH		 3314 break;
3315 case ACB_ADAPTER_TYPE_D: {
3316 uint32_t __iomem *rwbuffer;
3317 struct MessageUnit_D *reg = acb->pmuD;
3318 reg->postq_index = 0;
3319 reg->doneq_index = 0;
3320 rwbuffer = reg->msgcode_rwbuffer;
3321 writel(ARCMSR_SIGNATURE_SET_CONFIG, rwbuffer++);
3322 writel(cdb_phyaddr_hi32, rwbuffer++);
3323 writel(cdb_phyaddr, rwbuffer++);
3324 writel(cdb_phyaddr + (ARCMSR_MAX_ARC1214_POSTQUEUE *
3325 sizeof(struct InBound_SRB)), rwbuffer++);
3326 writel(0x100, rwbuffer);
3327 writel(ARCMSR_INBOUND_MESG0_SET_CONFIG, reg->inbound_msgaddr0);
3328 if (!arcmsr_hbaD_wait_msgint_ready(acb)) {
3329 pr_notice("arcmsr%d: 'set command Q window' timeout\n",
3330 acb->host->host_no);
3331 return 1;
3332 }
3333 }
3334 break;
1a4f550a
NC		 3335 }
3336 return 0;
3337}
a1f6e021 3338
1a4f550a
NC		 3339static void arcmsr_wait_firmware_ready(struct AdapterControlBlock *acb)
3340{
3341 uint32_t firmware_state = 0;
1a4f550a
NC		 3342 switch (acb->adapter_type) {
3343
3344 case ACB_ADAPTER_TYPE_A: {
80da1adb 3345 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 3346 do {
3347 firmware_state = readl(&reg->outbound_msgaddr1);
3348 } while ((firmware_state & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0);
3349 }
3350 break;
3351
3352 case ACB_ADAPTER_TYPE_B: {
80da1adb 3353 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 3354 do {
ae52e7f0 3355 firmware_state = readl(reg->iop2drv_doorbell);
1a4f550a 3356 } while ((firmware_state & ARCMSR_MESSAGE_FIRMWARE_OK) == 0);
ae52e7f0 3357 writel(ARCMSR_DRV2IOP_END_OF_INTERRUPT, reg->drv2iop_doorbell);
1a4f550a
NC		 3358 }
3359 break;
cdd3cb15 3360 case ACB_ADAPTER_TYPE_C: {
c10b1d54 3361 struct MessageUnit_C __iomem *reg = acb->pmuC;
cdd3cb15
NC		 3362 do {
3363 firmware_state = readl(&reg->outbound_msgaddr1);
3364 } while ((firmware_state & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0);
3365 }
5b37479a
CH		 3366 break;
3367 case ACB_ADAPTER_TYPE_D: {
3368 struct MessageUnit_D *reg = acb->pmuD;
3369 do {
3370 firmware_state = readl(reg->outbound_msgaddr1);
3371 } while ((firmware_state &
3372 ARCMSR_ARC1214_MESSAGE_FIRMWARE_OK) == 0);
3373 }
3374 break;
a1f6e021 3375 }
1a4f550a
NC		 3376}
3377
626fa32c 3378static void arcmsr_hbaA_request_device_map(struct AdapterControlBlock *acb)
36b83ded
NC		 3379{
3380 struct MessageUnit_A __iomem *reg = acb->pmuA;
cdd3cb15 3381 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
97b99127 3382 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 3383 return;
36b83ded 3384 } else {
ae52e7f0 3385 acb->fw_flag = FW_NORMAL;
cdd3cb15 3386 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)){
36b83ded
NC		 3387 atomic_set(&acb->rq_map_token, 16);
3388 }
ae52e7f0 3389 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
97b99127
N		 3390 if (atomic_dec_and_test(&acb->rq_map_token)) {
3391 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 3392 return;
97b99127 3393 }
36b83ded 3394 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
cdd3cb15 3395 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
36b83ded 3396 }
36b83ded
NC		 3397 return;
3398}
3399
626fa32c 3400static void arcmsr_hbaB_request_device_map(struct AdapterControlBlock *acb)
36b83ded 3401{
c10b1d54 3402 struct MessageUnit_B *reg = acb->pmuB;
cdd3cb15 3403 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0 ) || ((acb->acb_flags & ACB_F_ABORT) != 0 )){
97b99127 3404 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
cdd3cb15
NC		 3405 return;
3406 } else {
3407 acb->fw_flag = FW_NORMAL;
3408 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
97b99127 3409 atomic_set(&acb->rq_map_token, 16);
cdd3cb15
NC		 3410 }
3411 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
97b99127
N		 3412 if (atomic_dec_and_test(&acb->rq_map_token)) {
3413 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
cdd3cb15 3414 return;
97b99127 3415 }
cdd3cb15
NC		 3416 writel(ARCMSR_MESSAGE_GET_CONFIG, reg->drv2iop_doorbell);
3417 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
3418 }
3419 return;
3420}
36b83ded 3421
626fa32c 3422static void arcmsr_hbaC_request_device_map(struct AdapterControlBlock *acb)
cdd3cb15
NC		 3423{
3424 struct MessageUnit_C __iomem *reg = acb->pmuC;
ae52e7f0 3425 if (unlikely(atomic_read(&acb->rq_map_token) == 0) || ((acb->acb_flags & ACB_F_BUS_RESET) != 0) || ((acb->acb_flags & ACB_F_ABORT) != 0)) {
97b99127 3426 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 3427 return;
36b83ded 3428 } else {
ae52e7f0
NC		 3429 acb->fw_flag = FW_NORMAL;
3430 if (atomic_read(&acb->ante_token_value) == atomic_read(&acb->rq_map_token)) {
36b83ded
NC		 3431 atomic_set(&acb->rq_map_token, 16);
3432 }
ae52e7f0 3433 atomic_set(&acb->ante_token_value, atomic_read(&acb->rq_map_token));
97b99127
N		 3434 if (atomic_dec_and_test(&acb->rq_map_token)) {
3435 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 3436 return;
97b99127 3437 }
cdd3cb15
NC		 3438 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG, &reg->inbound_msgaddr0);
3439 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &reg->inbound_doorbell);
3440 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
36b83ded 3441 }
36b83ded
NC		 3442 return;
3443}
3444
5b37479a
CH		 3445static void arcmsr_hbaD_request_device_map(struct AdapterControlBlock *acb)
3446{
3447 struct MessageUnit_D *reg = acb->pmuD;
3448
3449 if (unlikely(atomic_read(&acb->rq_map_token) == 0) ||
3450 ((acb->acb_flags & ACB_F_BUS_RESET) != 0) ||
3451 ((acb->acb_flags & ACB_F_ABORT) != 0)) {
3452 mod_timer(&acb->eternal_timer,
3453 jiffies + msecs_to_jiffies(6 * HZ));
3454 } else {
3455 acb->fw_flag = FW_NORMAL;
3456 if (atomic_read(&acb->ante_token_value) ==
3457 atomic_read(&acb->rq_map_token)) {
3458 atomic_set(&acb->rq_map_token, 16);
3459 }
3460 atomic_set(&acb->ante_token_value,
3461 atomic_read(&acb->rq_map_token));
3462 if (atomic_dec_and_test(&acb->rq_map_token)) {
3463 mod_timer(&acb->eternal_timer, jiffies +
3464 msecs_to_jiffies(6 * HZ));
3465 return;
3466 }
3467 writel(ARCMSR_INBOUND_MESG0_GET_CONFIG,
3468 reg->inbound_msgaddr0);
3469 mod_timer(&acb->eternal_timer, jiffies +
3470 msecs_to_jiffies(6 * HZ));
3471 }
3472}
3473
36b83ded
NC		 3474static void arcmsr_request_device_map(unsigned long pacb)
3475{
3476 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)pacb;
36b83ded
NC		 3477 switch (acb->adapter_type) {
3478 case ACB_ADAPTER_TYPE_A: {
626fa32c 3479 arcmsr_hbaA_request_device_map(acb);
36b83ded
NC		 3480 }
3481 break;
3482 case ACB_ADAPTER_TYPE_B: {
626fa32c 3483 arcmsr_hbaB_request_device_map(acb);
36b83ded
NC		 3484 }
3485 break;
cdd3cb15 3486 case ACB_ADAPTER_TYPE_C: {
626fa32c 3487 arcmsr_hbaC_request_device_map(acb);
cdd3cb15 3488 }
5b37479a
CH		 3489 break;
3490 case ACB_ADAPTER_TYPE_D:
3491 arcmsr_hbaD_request_device_map(acb);
3492 break;
36b83ded
NC		 3493 }
3494}
3495
626fa32c 3496static void arcmsr_hbaA_start_bgrb(struct AdapterControlBlock *acb)
1a4f550a 3497{
80da1adb 3498 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 3499 acb->acb_flags |= ACB_F_MSG_START_BGRB;
3500 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &reg->inbound_msgaddr0);
626fa32c 3501 if (!arcmsr_hbaA_wait_msgint_ready(acb)) {
1a4f550a
NC		 3502 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
3503 rebulid' timeout \n", acb->host->host_no);
a1f6e021 3504 }
a1f6e021 3505}
3506
626fa32c 3507static void arcmsr_hbaB_start_bgrb(struct AdapterControlBlock *acb)
1a4f550a 3508{
80da1adb 3509 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 3510 acb->acb_flags |= ACB_F_MSG_START_BGRB;
ae52e7f0 3511 writel(ARCMSR_MESSAGE_START_BGRB, reg->drv2iop_doorbell);
626fa32c 3512 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
1a4f550a
NC		 3513 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
3514 rebulid' timeout \n",acb->host->host_no);
3515 }
3516}
1c57e86d 3517
626fa32c 3518static void arcmsr_hbaC_start_bgrb(struct AdapterControlBlock *pACB)
cdd3cb15 3519{
c10b1d54 3520 struct MessageUnit_C __iomem *phbcmu = pACB->pmuC;
cdd3cb15
NC		 3521 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
3522 writel(ARCMSR_INBOUND_MESG0_START_BGRB, &phbcmu->inbound_msgaddr0);
3523 writel(ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE, &phbcmu->inbound_doorbell);
626fa32c 3524 if (!arcmsr_hbaC_wait_msgint_ready(pACB)) {
cdd3cb15
NC		 3525 printk(KERN_NOTICE "arcmsr%d: wait 'start adapter background \
3526 rebulid' timeout \n", pACB->host->host_no);
3527 }
3528 return;
3529}
5b37479a
CH		 3530
3531static void arcmsr_hbaD_start_bgrb(struct AdapterControlBlock *pACB)
3532{
3533 struct MessageUnit_D *pmu = pACB->pmuD;
3534
3535 pACB->acb_flags |= ACB_F_MSG_START_BGRB;
3536 writel(ARCMSR_INBOUND_MESG0_START_BGRB, pmu->inbound_msgaddr0);
3537 if (!arcmsr_hbaD_wait_msgint_ready(pACB)) {
3538 pr_notice("arcmsr%d: wait 'start adapter "
3539 "background rebulid' timeout\n", pACB->host->host_no);
3540 }
3541}
3542
1a4f550a 3543static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
1c57e86d 3544{
1a4f550a
NC		 3545 switch (acb->adapter_type) {
3546 case ACB_ADAPTER_TYPE_A:
626fa32c 3547 arcmsr_hbaA_start_bgrb(acb);
1a4f550a
NC		 3548 break;
3549 case ACB_ADAPTER_TYPE_B:
626fa32c 3550 arcmsr_hbaB_start_bgrb(acb);
1a4f550a 3551 break;
cdd3cb15 3552 case ACB_ADAPTER_TYPE_C:
626fa32c 3553 arcmsr_hbaC_start_bgrb(acb);
5b37479a
CH		 3554 break;
3555 case ACB_ADAPTER_TYPE_D:
3556 arcmsr_hbaD_start_bgrb(acb);
3557 break;
1a4f550a
NC		 3558 }
3559}
1c57e86d 3560
1a4f550a
NC		 3561static void arcmsr_clear_doorbell_queue_buffer(struct AdapterControlBlock *acb)
3562{
3563 switch (acb->adapter_type) {
3564 case ACB_ADAPTER_TYPE_A: {
80da1adb 3565 struct MessageUnit_A __iomem *reg = acb->pmuA;
1a4f550a
NC		 3566 uint32_t outbound_doorbell;
3567 /* empty doorbell Qbuffer if door bell ringed */
3568 outbound_doorbell = readl(&reg->outbound_doorbell);
3569 /*clear doorbell interrupt */
3570 writel(outbound_doorbell, &reg->outbound_doorbell);
3571 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
3572 }
3573 break;
1c57e86d 3574
1a4f550a 3575 case ACB_ADAPTER_TYPE_B: {
80da1adb 3576 struct MessageUnit_B *reg = acb->pmuB;
1a4f550a 3577 /*clear interrupt and message state*/
ae52e7f0
NC		 3578 writel(ARCMSR_MESSAGE_INT_CLEAR_PATTERN, reg->iop2drv_doorbell);
3579 writel(ARCMSR_DRV2IOP_DATA_READ_OK, reg->drv2iop_doorbell);
1a4f550a
NC		 3580 /* let IOP know data has been read */
3581 }
3582 break;
cdd3cb15 3583 case ACB_ADAPTER_TYPE_C: {
c10b1d54 3584 struct MessageUnit_C __iomem *reg = acb->pmuC;
5eb6bfa0 3585 uint32_t outbound_doorbell, i;
cdd3cb15
NC		 3586 /* empty doorbell Qbuffer if door bell ringed */
3587 outbound_doorbell = readl(&reg->outbound_doorbell);
3588 writel(outbound_doorbell, &reg->outbound_doorbell_clear);
3589 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK, &reg->inbound_doorbell);
5eb6bfa0
CH		 3590 for (i = 0; i < 200; i++) {
3591 msleep(20);
3592 outbound_doorbell = readl(&reg->outbound_doorbell);
3593 if (outbound_doorbell &
3594 ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
3595 writel(outbound_doorbell,
3596 &reg->outbound_doorbell_clear);
3597 writel(ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK,
3598 &reg->inbound_doorbell);
3599 } else
3600 break;
3601 }
cdd3cb15 3602 }
5b37479a
CH		 3603 break;
3604 case ACB_ADAPTER_TYPE_D: {
3605 struct MessageUnit_D *reg = acb->pmuD;
3606 uint32_t outbound_doorbell, i;
3607 /* empty doorbell Qbuffer if door bell ringed */
3608 outbound_doorbell = readl(reg->outbound_doorbell);
3609 writel(outbound_doorbell, reg->outbound_doorbell);
3610 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
3611 reg->inbound_doorbell);
3612 for (i = 0; i < 200; i++) {
3613 msleep(20);
3614 outbound_doorbell = readl(reg->outbound_doorbell);
3615 if (outbound_doorbell &
3616 ARCMSR_ARC1214_IOP2DRV_DATA_WRITE_OK) {
3617 writel(outbound_doorbell,
3618 reg->outbound_doorbell);
3619 writel(ARCMSR_ARC1214_DRV2IOP_DATA_OUT_READ,
3620 reg->inbound_doorbell);
3621 } else
3622 break;
3623 }
3624 }
3625 break;
1c57e86d 3626 }
1a4f550a 3627}
1c57e86d 3628
76d78300
NC		 3629static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
3630{
3631 switch (acb->adapter_type) {
3632 case ACB_ADAPTER_TYPE_A:
3633 return;
3634 case ACB_ADAPTER_TYPE_B:
3635 {
3636 struct MessageUnit_B *reg = acb->pmuB;
ae52e7f0 3637 writel(ARCMSR_MESSAGE_ACTIVE_EOI_MODE, reg->drv2iop_doorbell);
626fa32c 3638 if (!arcmsr_hbaB_wait_msgint_ready(acb)) {
76d78300
NC		 3639 printk(KERN_NOTICE "ARCMSR IOP enables EOI_MODE TIMEOUT");
3640 return;
3641 }
3642 }
3643 break;
cdd3cb15
NC		 3644 case ACB_ADAPTER_TYPE_C:
3645 return;
76d78300
NC		 3646 }
3647 return;
3648}
3649
36b83ded
NC		 3650static void arcmsr_hardware_reset(struct AdapterControlBlock *acb)
3651{
3652 uint8_t value[64];
cdd3cb15
NC		 3653 int i, count = 0;
3654 struct MessageUnit_A __iomem *pmuA = acb->pmuA;
3655 struct MessageUnit_C __iomem *pmuC = acb->pmuC;
5b37479a 3656 struct MessageUnit_D *pmuD = acb->pmuD;
6ad819b0 3657
36b83ded 3658 /* backup pci config data */
cdd3cb15 3659 printk(KERN_NOTICE "arcmsr%d: executing hw bus reset .....\n", acb->host->host_no);
36b83ded
NC		 3660 for (i = 0; i < 64; i++) {
3661 pci_read_config_byte(acb->pdev, i, &value[i]);
3662 }
3663 /* hardware reset signal */
ae52e7f0 3664 if ((acb->dev_id == 0x1680)) {
cdd3cb15
NC		 3665 writel(ARCMSR_ARC1680_BUS_RESET, &pmuA->reserved1[0]);
3666 } else if ((acb->dev_id == 0x1880)) {
3667 do {
3668 count++;
3669 writel(0xF, &pmuC->write_sequence);
3670 writel(0x4, &pmuC->write_sequence);
3671 writel(0xB, &pmuC->write_sequence);
3672 writel(0x2, &pmuC->write_sequence);
3673 writel(0x7, &pmuC->write_sequence);
3674 writel(0xD, &pmuC->write_sequence);
6ad819b0 3675 } while (((readl(&pmuC->host_diagnostic) & ARCMSR_ARC1880_DiagWrite_ENABLE) == 0) && (count < 5));
cdd3cb15 3676 writel(ARCMSR_ARC1880_RESET_ADAPTER, &pmuC->host_diagnostic);
5b37479a
CH		 3677 } else if ((acb->dev_id == 0x1214)) {
3678 writel(0x20, pmuD->reset_request);
ae52e7f0 3679 } else {
cdd3cb15 3680 pci_write_config_byte(acb->pdev, 0x84, 0x20);
ae52e7f0 3681 }
cdd3cb15 3682 msleep(2000);
36b83ded
NC		 3683 /* write back pci config data */
3684 for (i = 0; i < 64; i++) {
3685 pci_write_config_byte(acb->pdev, i, value[i]);
3686 }
3687 msleep(1000);
3688 return;
3689}
1a4f550a
NC		 3690static void arcmsr_iop_init(struct AdapterControlBlock *acb)
3691{
3692 uint32_t intmask_org;
cdd3cb15
NC		 3693 /* disable all outbound interrupt */
3694 intmask_org = arcmsr_disable_outbound_ints(acb);
76d78300
NC		 3695 arcmsr_wait_firmware_ready(acb);
3696 arcmsr_iop_confirm(acb);
1a4f550a
NC		 3697 /*start background rebuild*/
3698 arcmsr_start_adapter_bgrb(acb);
3699 /* empty doorbell Qbuffer if door bell ringed */
3700 arcmsr_clear_doorbell_queue_buffer(acb);
76d78300 3701 arcmsr_enable_eoi_mode(acb);
1a4f550a
NC		 3702 /* enable outbound Post Queue,outbound doorbell Interrupt */
3703 arcmsr_enable_outbound_ints(acb, intmask_org);
1c57e86d
EC		 3704 acb->acb_flags |= ACB_F_IOP_INITED;
3705}
3706
36b83ded 3707static uint8_t arcmsr_iop_reset(struct AdapterControlBlock *acb)
1c57e86d 3708{
1c57e86d
EC		 3709 struct CommandControlBlock *ccb;
3710 uint32_t intmask_org;
36b83ded 3711 uint8_t rtnval = 0x00;
1c57e86d 3712 int i = 0;
97b99127
N		 3713 unsigned long flags;
3714
1c57e86d 3715 if (atomic_read(&acb->ccboutstandingcount) != 0) {
36b83ded
NC		 3716 /* disable all outbound interrupt */
3717 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d 3718 /* talk to iop 331 outstanding command aborted */
36b83ded 3719 rtnval = arcmsr_abort_allcmd(acb);
1c57e86d 3720 /* clear all outbound posted Q */
1a4f550a 3721 arcmsr_done4abort_postqueue(acb);
1c57e86d
EC		 3722 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
3723 ccb = acb->pccb_pool[i];
a1f6e021 3724 if (ccb->startdone == ARCMSR_CCB_START) {
97b99127
N		 3725 scsi_dma_unmap(ccb->pcmd);
3726 ccb->startdone = ARCMSR_CCB_DONE;
3727 ccb->ccb_flags = 0;
3728 spin_lock_irqsave(&acb->ccblist_lock, flags);
3729 list_add_tail(&ccb->list, &acb->ccb_free_list);
3730 spin_unlock_irqrestore(&acb->ccblist_lock, flags);
1c57e86d
EC		 3731 }
3732 }
36b83ded 3733 atomic_set(&acb->ccboutstandingcount, 0);
1c57e86d
EC		 3734 /* enable all outbound interrupt */
3735 arcmsr_enable_outbound_ints(acb, intmask_org);
36b83ded 3736 return rtnval;
1c57e86d 3737 }
36b83ded 3738 return rtnval;
1c57e86d
EC		 3739}
3740
3741static int arcmsr_bus_reset(struct scsi_cmnd *cmd)
3742{
97b99127 3743 struct AdapterControlBlock *acb;
ae52e7f0
NC		 3744 uint32_t intmask_org, outbound_doorbell;
3745 int retry_count = 0;
3746 int rtn = FAILED;
ae52e7f0 3747 acb = (struct AdapterControlBlock *) cmd->device->host->hostdata;
cdd3cb15 3748 printk(KERN_ERR "arcmsr: executing bus reset eh.....num_resets = %d, num_aborts = %d \n", acb->num_resets, acb->num_aborts);
36b83ded 3749 acb->num_resets++;
36b83ded 3750
cdd3cb15
NC		 3751 switch(acb->adapter_type){
3752 case ACB_ADAPTER_TYPE_A:{
3753 if (acb->acb_flags & ACB_F_BUS_RESET){
ae52e7f0 3754 long timeout;
cdd3cb15
NC		 3755 printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
3756 timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
ae52e7f0
NC		 3757 if (timeout) {
3758 return SUCCESS;
3759 }
3760 }
3761 acb->acb_flags |= ACB_F_BUS_RESET;
cdd3cb15 3762 if (!arcmsr_iop_reset(acb)) {
ae52e7f0
NC		 3763 struct MessageUnit_A __iomem *reg;
3764 reg = acb->pmuA;
cdd3cb15
NC		 3765 arcmsr_hardware_reset(acb);
3766 acb->acb_flags &= ~ACB_F_IOP_INITED;
36b83ded 3767sleep_again:
8b7eb86f 3768 ssleep(ARCMSR_SLEEPTIME);
ae52e7f0 3769 if ((readl(&reg->outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) {
8b7eb86f
TH		 3770 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d\n", acb->host->host_no, retry_count);
3771 if (retry_count > ARCMSR_RETRYCOUNT) {
ae52e7f0 3772 acb->fw_flag = FW_DEADLOCK;
8b7eb86f 3773 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!!\n", acb->host->host_no);
ae52e7f0 3774 return FAILED;
cdd3cb15
NC		 3775 }
3776 retry_count++;
3777 goto sleep_again;
3778 }
3779 acb->acb_flags |= ACB_F_IOP_INITED;
3780 /* disable all outbound interrupt */
3781 intmask_org = arcmsr_disable_outbound_ints(acb);
ae52e7f0 3782 arcmsr_get_firmware_spec(acb);
cdd3cb15
NC		 3783 arcmsr_start_adapter_bgrb(acb);
3784 /* clear Qbuffer if door bell ringed */
3785 outbound_doorbell = readl(&reg->outbound_doorbell);
3786 writel(outbound_doorbell, &reg->outbound_doorbell); /*clear interrupt */
3787 writel(ARCMSR_INBOUND_DRIVER_DATA_READ_OK, &reg->inbound_doorbell);
3788 /* enable outbound Post Queue,outbound doorbell Interrupt */
3789 arcmsr_enable_outbound_ints(acb, intmask_org);
3790 atomic_set(&acb->rq_map_token, 16);
ae52e7f0
NC		 3791 atomic_set(&acb->ante_token_value, 16);
3792 acb->fw_flag = FW_NORMAL;
97b99127 3793 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0
NC		 3794 acb->acb_flags &= ~ACB_F_BUS_RESET;
3795 rtn = SUCCESS;
cdd3cb15 3796 printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
ae52e7f0
NC		 3797 } else {
3798 acb->acb_flags &= ~ACB_F_BUS_RESET;
97b99127
N		 3799 atomic_set(&acb->rq_map_token, 16);
3800 atomic_set(&acb->ante_token_value, 16);
3801 acb->fw_flag = FW_NORMAL;
3802 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
ae52e7f0 3803 rtn = SUCCESS;
cdd3cb15 3804 }
ae52e7f0 3805 break;
36b83ded 3806 }
ae52e7f0
NC		 3807 case ACB_ADAPTER_TYPE_B:{
3808 acb->acb_flags |= ACB_F_BUS_RESET;
cdd3cb15 3809 if (!arcmsr_iop_reset(acb)) {
ae52e7f0
NC		 3810 acb->acb_flags &= ~ACB_F_BUS_RESET;
3811 rtn = FAILED;
cdd3cb15
NC		 3812 } else {
3813 acb->acb_flags &= ~ACB_F_BUS_RESET;
97b99127
N		 3814 atomic_set(&acb->rq_map_token, 16);
3815 atomic_set(&acb->ante_token_value, 16);
3816 acb->fw_flag = FW_NORMAL;
3817 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
ae52e7f0 3818 rtn = SUCCESS;
cdd3cb15
NC		 3819 }
3820 break;
3821 }
3822 case ACB_ADAPTER_TYPE_C:{
3823 if (acb->acb_flags & ACB_F_BUS_RESET) {
3824 long timeout;
3825 printk(KERN_ERR "arcmsr: there is an bus reset eh proceeding.......\n");
3826 timeout = wait_event_timeout(wait_q, (acb->acb_flags & ACB_F_BUS_RESET) == 0, 220*HZ);
3827 if (timeout) {
3828 return SUCCESS;
3829 }
3830 }
3831 acb->acb_flags |= ACB_F_BUS_RESET;
3832 if (!arcmsr_iop_reset(acb)) {
3833 struct MessageUnit_C __iomem *reg;
3834 reg = acb->pmuC;
3835 arcmsr_hardware_reset(acb);
3836 acb->acb_flags &= ~ACB_F_IOP_INITED;
3837sleep:
8b7eb86f 3838 ssleep(ARCMSR_SLEEPTIME);
cdd3cb15 3839 if ((readl(&reg->host_diagnostic) & 0x04) != 0) {
8b7eb86f
TH		 3840 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, retry=%d\n", acb->host->host_no, retry_count);
3841 if (retry_count > ARCMSR_RETRYCOUNT) {
cdd3cb15 3842 acb->fw_flag = FW_DEADLOCK;
8b7eb86f 3843 printk(KERN_ERR "arcmsr%d: waiting for hw bus reset return, RETRY TERMINATED!!\n", acb->host->host_no);
cdd3cb15
NC		 3844 return FAILED;
3845 }
3846 retry_count++;
3847 goto sleep;
3848 }
3849 acb->acb_flags |= ACB_F_IOP_INITED;
3850 /* disable all outbound interrupt */
3851 intmask_org = arcmsr_disable_outbound_ints(acb);
3852 arcmsr_get_firmware_spec(acb);
3853 arcmsr_start_adapter_bgrb(acb);
3854 /* clear Qbuffer if door bell ringed */
5eb6bfa0 3855 arcmsr_clear_doorbell_queue_buffer(acb);
cdd3cb15
NC		 3856 /* enable outbound Post Queue,outbound doorbell Interrupt */
3857 arcmsr_enable_outbound_ints(acb, intmask_org);
3858 atomic_set(&acb->rq_map_token, 16);
3859 atomic_set(&acb->ante_token_value, 16);
3860 acb->fw_flag = FW_NORMAL;
97b99127 3861 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6 * HZ));
cdd3cb15
NC		 3862 acb->acb_flags &= ~ACB_F_BUS_RESET;
3863 rtn = SUCCESS;
3864 printk(KERN_ERR "arcmsr: scsi bus reset eh returns with success\n");
3865 } else {
3866 acb->acb_flags &= ~ACB_F_BUS_RESET;
97b99127
N		 3867 atomic_set(&acb->rq_map_token, 16);
3868 atomic_set(&acb->ante_token_value, 16);
3869 acb->fw_flag = FW_NORMAL;
3870 mod_timer(&acb->eternal_timer, jiffies + msecs_to_jiffies(6*HZ));
cdd3cb15
NC		 3871 rtn = SUCCESS;
3872 }
3873 break;
ae52e7f0 3874 }
5b37479a
CH		 3875 case ACB_ADAPTER_TYPE_D: {
3876 if (acb->acb_flags & ACB_F_BUS_RESET) {
3877 long timeout;
3878 pr_notice("arcmsr: there is an bus reset"
3879 " eh proceeding.......\n");
3880 timeout = wait_event_timeout(wait_q, (acb->acb_flags
3881 & ACB_F_BUS_RESET) == 0, 220 * HZ);
3882 if (timeout)
3883 return SUCCESS;
3884 }
3885 acb->acb_flags |= ACB_F_BUS_RESET;
3886 if (!arcmsr_iop_reset(acb)) {
3887 struct MessageUnit_D *reg;
3888 reg = acb->pmuD;
3889 arcmsr_hardware_reset(acb);
3890 acb->acb_flags &= ~ACB_F_IOP_INITED;
3891 nap:
3892 ssleep(ARCMSR_SLEEPTIME);
3893 if ((readl(reg->sample_at_reset) & 0x80) != 0) {
3894 pr_err("arcmsr%d: waiting for "
3895 "hw bus reset return, retry=%d\n",
3896 acb->host->host_no, retry_count);
3897 if (retry_count > ARCMSR_RETRYCOUNT) {
3898 acb->fw_flag = FW_DEADLOCK;
3899 pr_err("arcmsr%d: waiting for hw bus"
3900 " reset return, "
3901 "RETRY TERMINATED!!\n",
3902 acb->host->host_no);
3903 return FAILED;
3904 }
3905 retry_count++;
3906 goto nap;
3907 }
3908 acb->acb_flags |= ACB_F_IOP_INITED;
3909 /* disable all outbound interrupt */
3910 intmask_org = arcmsr_disable_outbound_ints(acb);
3911 arcmsr_get_firmware_spec(acb);
3912 arcmsr_start_adapter_bgrb(acb);
3913 arcmsr_clear_doorbell_queue_buffer(acb);
3914 arcmsr_enable_outbound_ints(acb, intmask_org);
3915 atomic_set(&acb->rq_map_token, 16);
3916 atomic_set(&acb->ante_token_value, 16);
3917 acb->fw_flag = FW_NORMAL;
3918 mod_timer(&acb->eternal_timer,
3919 jiffies + msecs_to_jiffies(6 * HZ));
3920 acb->acb_flags &= ~ACB_F_BUS_RESET;
3921 rtn = SUCCESS;
3922 pr_err("arcmsr: scsi bus reset "
3923 "eh returns with success\n");
3924 } else {
3925 acb->acb_flags &= ~ACB_F_BUS_RESET;
3926 atomic_set(&acb->rq_map_token, 16);
3927 atomic_set(&acb->ante_token_value, 16);
3928 acb->fw_flag = FW_NORMAL;
3929 mod_timer(&acb->eternal_timer,
3930 jiffies + msecs_to_jiffies(6 * HZ));
3931 rtn = SUCCESS;
3932 }
3933 break;
3934 }
ae52e7f0
NC		 3935 }
3936 return rtn;
1c57e86d
EC		 3937}
3938
ae52e7f0 3939static int arcmsr_abort_one_cmd(struct AdapterControlBlock *acb,
1c57e86d
EC		 3940 struct CommandControlBlock *ccb)
3941{
ae52e7f0 3942 int rtn;
ae52e7f0 3943 rtn = arcmsr_polling_ccbdone(acb, ccb);
ae52e7f0 3944 return rtn;
1c57e86d
EC		 3945}
3946
3947static int arcmsr_abort(struct scsi_cmnd *cmd)
3948{
3949 struct AdapterControlBlock *acb =
3950 (struct AdapterControlBlock *)cmd->device->host->hostdata;
3951 int i = 0;
ae52e7f0 3952 int rtn = FAILED;
cab5aece
CH		 3953 uint32_t intmask_org;
3954
1c57e86d 3955 printk(KERN_NOTICE
cab5aece 3956 "arcmsr%d: abort device command of scsi id = %d lun = %d\n",
9cb78c16 3957 acb->host->host_no, cmd->device->id, (u32)cmd->device->lun);
ae52e7f0 3958 acb->acb_flags |= ACB_F_ABORT;
1c57e86d 3959 acb->num_aborts++;
1c57e86d
EC		 3960 /*
3961 ************************************************
3962 ** the all interrupt service routine is locked
3963 ** we need to handle it as soon as possible and exit
3964 ************************************************
3965 */
cab5aece
CH		 3966 if (!atomic_read(&acb->ccboutstandingcount)) {
3967 acb->acb_flags &= ~ACB_F_ABORT;
ae52e7f0 3968 return rtn;
cab5aece 3969 }
1c57e86d 3970
cab5aece 3971 intmask_org = arcmsr_disable_outbound_ints(acb);
1c57e86d
EC		 3972 for (i = 0; i < ARCMSR_MAX_FREECCB_NUM; i++) {
3973 struct CommandControlBlock *ccb = acb->pccb_pool[i];
3974 if (ccb->startdone == ARCMSR_CCB_START && ccb->pcmd == cmd) {
ae52e7f0
NC		 3975 ccb->startdone = ARCMSR_CCB_ABORTED;
3976 rtn = arcmsr_abort_one_cmd(acb, ccb);
1c57e86d
EC		 3977 break;
3978 }
3979 }
ae52e7f0 3980 acb->acb_flags &= ~ACB_F_ABORT;
cab5aece 3981 arcmsr_enable_outbound_ints(acb, intmask_org);
ae52e7f0 3982 return rtn;
1c57e86d
EC		 3983}
3984
3985static const char *arcmsr_info(struct Scsi_Host *host)
3986{
3987 struct AdapterControlBlock *acb =
3988 (struct AdapterControlBlock *) host->hostdata;
3989 static char buf[256];
3990 char *type;
3991 int raid6 = 1;
1c57e86d
EC		 3992 switch (acb->pdev->device) {
3993 case PCI_DEVICE_ID_ARECA_1110:
1a4f550a
NC		 3994 case PCI_DEVICE_ID_ARECA_1200:
3995 case PCI_DEVICE_ID_ARECA_1202:
1c57e86d
EC		 3996 case PCI_DEVICE_ID_ARECA_1210:
3997 raid6 = 0;
3998 /*FALLTHRU*/
3999 case PCI_DEVICE_ID_ARECA_1120:
4000 case PCI_DEVICE_ID_ARECA_1130:
4001 case PCI_DEVICE_ID_ARECA_1160:
4002 case PCI_DEVICE_ID_ARECA_1170:
1a4f550a 4003 case PCI_DEVICE_ID_ARECA_1201:
1c57e86d
EC		 4004 case PCI_DEVICE_ID_ARECA_1220:
4005 case PCI_DEVICE_ID_ARECA_1230:
4006 case PCI_DEVICE_ID_ARECA_1260:
4007 case PCI_DEVICE_ID_ARECA_1270:
4008 case PCI_DEVICE_ID_ARECA_1280:
4009 type = "SATA";
4010 break;
5b37479a 4011 case PCI_DEVICE_ID_ARECA_1214:
1c57e86d
EC		 4012 case PCI_DEVICE_ID_ARECA_1380:
4013 case PCI_DEVICE_ID_ARECA_1381:
4014 case PCI_DEVICE_ID_ARECA_1680:
4015 case PCI_DEVICE_ID_ARECA_1681:
cdd3cb15 4016 case PCI_DEVICE_ID_ARECA_1880:
aaa64f69 4017 type = "SAS/SATA";
1c57e86d
EC		 4018 break;
4019 default:
aaa64f69
CH		 4020 type = "unknown";
4021 raid6 = 0;
1c57e86d
EC		 4022 break;
4023 }
aaa64f69
CH		 4024 sprintf(buf, "Areca %s RAID Controller %s\narcmsr version %s\n",
4025 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION);
1c57e86d
EC		 4026 return buf;
4027}
Linux 6.x block layer and io_uring tree(s)