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1da177e4 LT |
1 | /* |
2 | * Aic79xx register and scratch ram definitions. | |
3 | * | |
53467e63 | 4 | * Copyright (c) 1994-2001, 2004 Justin T. Gibbs. |
1da177e4 LT |
5 | * Copyright (c) 2000-2002 Adaptec Inc. |
6 | * All rights reserved. | |
7 | * | |
8 | * Redistribution and use in source and binary forms, with or without | |
9 | * modification, are permitted provided that the following conditions | |
10 | * are met: | |
11 | * 1. Redistributions of source code must retain the above copyright | |
12 | * notice, this list of conditions, and the following disclaimer, | |
13 | * without modification. | |
14 | * 2. Redistributions in binary form must reproduce at minimum a disclaimer | |
15 | * substantially similar to the "NO WARRANTY" disclaimer below | |
16 | * ("Disclaimer") and any redistribution must be conditioned upon | |
17 | * including a substantially similar Disclaimer requirement for further | |
18 | * binary redistribution. | |
19 | * 3. Neither the names of the above-listed copyright holders nor the names | |
20 | * of any contributors may be used to endorse or promote products derived | |
21 | * from this software without specific prior written permission. | |
22 | * | |
23 | * Alternatively, this software may be distributed under the terms of the | |
24 | * GNU General Public License ("GPL") version 2 as published by the Free | |
25 | * Software Foundation. | |
26 | * | |
27 | * NO WARRANTY | |
28 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS | |
29 | * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT | |
30 | * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR | |
31 | * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT | |
32 | * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL | |
33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS | |
34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) | |
35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, | |
36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING | |
37 | * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE | |
38 | * POSSIBILITY OF SUCH DAMAGES. | |
39 | * | |
40 | * $FreeBSD$ | |
41 | */ | |
53467e63 | 42 | VERSION = "$Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $" |
1da177e4 LT |
43 | |
44 | /* | |
45 | * This file is processed by the aic7xxx_asm utility for use in assembling | |
46 | * firmware for the aic79xx family of SCSI host adapters as well as to generate | |
47 | * a C header file for use in the kernel portion of the Aic79xx driver. | |
48 | */ | |
49 | ||
50 | /* Register window Modes */ | |
51 | #define M_DFF0 0 | |
52 | #define M_DFF1 1 | |
53 | #define M_CCHAN 2 | |
54 | #define M_SCSI 3 | |
55 | #define M_CFG 4 | |
56 | #define M_DST_SHIFT 4 | |
57 | ||
58 | #define MK_MODE(src, dst) ((src) | ((dst) << M_DST_SHIFT)) | |
59 | #define SET_MODE(src, dst) \ | |
60 | SET_SRC_MODE src; \ | |
61 | SET_DST_MODE dst; \ | |
62 | if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ | |
63 | mvi MK_MODE(src, dst) call set_mode_work_around; \ | |
64 | } else { \ | |
65 | mvi MODE_PTR, MK_MODE(src, dst); \ | |
66 | } | |
67 | ||
1da177e4 LT |
68 | #define RESTORE_MODE(mode) \ |
69 | if ((ahd->bugs & AHD_SET_MODE_BUG) != 0) { \ | |
70 | mov mode call set_mode_work_around; \ | |
71 | } else { \ | |
72 | mov MODE_PTR, mode; \ | |
73 | } | |
74 | ||
75 | #define SET_SEQINTCODE(code) \ | |
76 | if ((ahd->bugs & AHD_INTCOLLISION_BUG) != 0) { \ | |
77 | mvi code call set_seqint_work_around; \ | |
78 | } else { \ | |
79 | mvi SEQINTCODE, code; \ | |
80 | } | |
81 | ||
82 | /* | |
83 | * Mode Pointer | |
84 | * Controls which of the 5, 512byte, address spaces should be used | |
85 | * as the source and destination of any register accesses in our | |
86 | * register window. | |
87 | */ | |
88 | register MODE_PTR { | |
89 | address 0x000 | |
90 | access_mode RW | |
91 | field DST_MODE 0x70 | |
92 | field SRC_MODE 0x07 | |
93 | mode_pointer | |
94 | } | |
95 | ||
96 | const SRC_MODE_SHIFT 0 | |
97 | const DST_MODE_SHIFT 4 | |
98 | ||
99 | /* | |
100 | * Host Interrupt Status | |
101 | */ | |
102 | register INTSTAT { | |
103 | address 0x001 | |
104 | access_mode RW | |
105 | field HWERRINT 0x80 | |
106 | field BRKADRINT 0x40 | |
107 | field SWTMINT 0x20 | |
108 | field PCIINT 0x10 | |
109 | field SCSIINT 0x08 | |
110 | field SEQINT 0x04 | |
111 | field CMDCMPLT 0x02 | |
112 | field SPLTINT 0x01 | |
113 | mask INT_PEND 0xFF | |
114 | } | |
115 | ||
116 | /* | |
117 | * Sequencer Interrupt Code | |
118 | */ | |
119 | register SEQINTCODE { | |
120 | address 0x002 | |
121 | access_mode RW | |
122 | field { | |
123 | NO_SEQINT, /* No seqint pending. */ | |
124 | BAD_PHASE, /* unknown scsi bus phase */ | |
125 | SEND_REJECT, /* sending a message reject */ | |
126 | PROTO_VIOLATION, /* Protocol Violation */ | |
127 | NO_MATCH, /* no cmd match for reconnect */ | |
128 | IGN_WIDE_RES, /* Complex IGN Wide Res Msg */ | |
129 | PDATA_REINIT, /* | |
130 | * Returned to data phase | |
131 | * that requires data | |
132 | * transfer pointers to be | |
133 | * recalculated from the | |
134 | * transfer residual. | |
135 | */ | |
136 | HOST_MSG_LOOP, /* | |
137 | * The bus is ready for the | |
138 | * host to perform another | |
139 | * message transaction. This | |
140 | * mechanism is used for things | |
141 | * like sync/wide negotiation | |
142 | * that require a kernel based | |
143 | * message state engine. | |
144 | */ | |
145 | BAD_STATUS, /* Bad status from target */ | |
146 | DATA_OVERRUN, /* | |
147 | * Target attempted to write | |
148 | * beyond the bounds of its | |
149 | * command. | |
150 | */ | |
151 | MKMSG_FAILED, /* | |
152 | * Target completed command | |
153 | * without honoring our ATN | |
154 | * request to issue a message. | |
155 | */ | |
156 | MISSED_BUSFREE, /* | |
157 | * The sequencer never saw | |
158 | * the bus go free after | |
159 | * either a command complete | |
160 | * or disconnect message. | |
161 | */ | |
162 | DUMP_CARD_STATE, | |
163 | ILLEGAL_PHASE, | |
164 | INVALID_SEQINT, | |
165 | CFG4ISTAT_INTR, | |
166 | STATUS_OVERRUN, | |
167 | CFG4OVERRUN, | |
168 | ENTERING_NONPACK, | |
169 | TASKMGMT_FUNC_COMPLETE, /* | |
170 | * Task management function | |
171 | * request completed with | |
172 | * an expected busfree. | |
173 | */ | |
174 | TASKMGMT_CMD_CMPLT_OKAY, /* | |
175 | * A command with a non-zero | |
176 | * task management function | |
177 | * has completed via the normal | |
178 | * command completion method | |
179 | * for commands with a zero | |
180 | * task management function. | |
181 | * This happens when an attempt | |
182 | * to abort a command loses | |
183 | * the race for the command to | |
184 | * complete normally. | |
185 | */ | |
186 | TRACEPOINT0, | |
187 | TRACEPOINT1, | |
188 | TRACEPOINT2, | |
189 | TRACEPOINT3, | |
190 | SAW_HWERR, | |
191 | BAD_SCB_STATUS | |
192 | } | |
193 | } | |
194 | ||
195 | /* | |
196 | * Clear Host Interrupt | |
197 | */ | |
198 | register CLRINT { | |
199 | address 0x003 | |
200 | access_mode WO | |
201 | field CLRHWERRINT 0x80 /* Rev B or greater */ | |
202 | field CLRBRKADRINT 0x40 | |
203 | field CLRSWTMINT 0x20 | |
204 | field CLRPCIINT 0x10 | |
205 | field CLRSCSIINT 0x08 | |
206 | field CLRSEQINT 0x04 | |
207 | field CLRCMDINT 0x02 | |
208 | field CLRSPLTINT 0x01 | |
209 | } | |
210 | ||
211 | /* | |
212 | * Error Register | |
213 | */ | |
214 | register ERROR { | |
215 | address 0x004 | |
216 | access_mode RO | |
217 | field CIOPARERR 0x80 | |
218 | field CIOACCESFAIL 0x40 /* Rev B or greater */ | |
219 | field MPARERR 0x20 | |
220 | field DPARERR 0x10 | |
221 | field SQPARERR 0x08 | |
222 | field ILLOPCODE 0x04 | |
223 | field DSCTMOUT 0x02 | |
224 | } | |
225 | ||
226 | /* | |
227 | * Clear Error | |
228 | */ | |
229 | register CLRERR { | |
230 | address 0x004 | |
231 | access_mode WO | |
232 | field CLRCIOPARERR 0x80 | |
233 | field CLRCIOACCESFAIL 0x40 /* Rev B or greater */ | |
234 | field CLRMPARERR 0x20 | |
235 | field CLRDPARERR 0x10 | |
236 | field CLRSQPARERR 0x08 | |
237 | field CLRILLOPCODE 0x04 | |
238 | field CLRDSCTMOUT 0x02 | |
239 | } | |
240 | ||
241 | /* | |
242 | * Host Control Register | |
243 | * Overall host control of the device. | |
244 | */ | |
245 | register HCNTRL { | |
246 | address 0x005 | |
247 | access_mode RW | |
248 | field SEQ_RESET 0x80 /* Rev B or greater */ | |
249 | field POWRDN 0x40 | |
250 | field SWINT 0x10 | |
251 | field SWTIMER_START_B 0x08 /* Rev B or greater */ | |
252 | field PAUSE 0x04 | |
253 | field INTEN 0x02 | |
254 | field CHIPRST 0x01 | |
255 | field CHIPRSTACK 0x01 | |
256 | } | |
257 | ||
258 | /* | |
259 | * Host New SCB Queue Offset | |
260 | */ | |
261 | register HNSCB_QOFF { | |
262 | address 0x006 | |
263 | access_mode RW | |
264 | size 2 | |
265 | } | |
266 | ||
267 | /* | |
268 | * Host Empty SCB Queue Offset | |
269 | */ | |
270 | register HESCB_QOFF { | |
271 | address 0x008 | |
272 | access_mode RW | |
273 | } | |
274 | ||
275 | /* | |
276 | * Host Mailbox | |
277 | */ | |
278 | register HS_MAILBOX { | |
279 | address 0x00B | |
280 | access_mode RW | |
281 | mask HOST_TQINPOS 0x80 /* Boundary at either 0 or 128 */ | |
282 | mask ENINT_COALESCE 0x40 /* Perform interrupt coalescing */ | |
283 | } | |
284 | ||
285 | /* | |
286 | * Sequencer Interupt Status | |
287 | */ | |
288 | register SEQINTSTAT { | |
289 | address 0x00C | |
290 | access_mode RO | |
291 | field SEQ_SWTMRTO 0x10 | |
292 | field SEQ_SEQINT 0x08 | |
293 | field SEQ_SCSIINT 0x04 | |
294 | field SEQ_PCIINT 0x02 | |
295 | field SEQ_SPLTINT 0x01 | |
296 | } | |
297 | ||
298 | /* | |
299 | * Clear SEQ Interrupt | |
300 | */ | |
301 | register CLRSEQINTSTAT { | |
302 | address 0x00C | |
303 | access_mode WO | |
304 | field CLRSEQ_SWTMRTO 0x10 | |
305 | field CLRSEQ_SEQINT 0x08 | |
306 | field CLRSEQ_SCSIINT 0x04 | |
307 | field CLRSEQ_PCIINT 0x02 | |
308 | field CLRSEQ_SPLTINT 0x01 | |
309 | } | |
310 | ||
311 | /* | |
312 | * Software Timer | |
313 | */ | |
314 | register SWTIMER { | |
315 | address 0x00E | |
316 | access_mode RW | |
317 | size 2 | |
318 | } | |
319 | ||
320 | /* | |
321 | * SEQ New SCB Queue Offset | |
322 | */ | |
323 | register SNSCB_QOFF { | |
324 | address 0x010 | |
325 | access_mode RW | |
326 | size 2 | |
327 | modes M_CCHAN | |
328 | } | |
329 | ||
330 | /* | |
331 | * SEQ Empty SCB Queue Offset | |
332 | */ | |
333 | register SESCB_QOFF { | |
334 | address 0x012 | |
335 | access_mode RW | |
336 | modes M_CCHAN | |
337 | } | |
338 | ||
339 | /* | |
340 | * SEQ Done SCB Queue Offset | |
341 | */ | |
342 | register SDSCB_QOFF { | |
343 | address 0x014 | |
344 | access_mode RW | |
345 | modes M_CCHAN | |
346 | size 2 | |
347 | } | |
348 | ||
349 | /* | |
350 | * Queue Offset Control & Status | |
351 | */ | |
352 | register QOFF_CTLSTA { | |
353 | address 0x016 | |
354 | access_mode RW | |
355 | modes M_CCHAN | |
356 | field EMPTY_SCB_AVAIL 0x80 | |
357 | field NEW_SCB_AVAIL 0x40 | |
358 | field SDSCB_ROLLOVR 0x20 | |
359 | field HS_MAILBOX_ACT 0x10 | |
360 | field SCB_QSIZE 0x0F { | |
361 | SCB_QSIZE_4, | |
362 | SCB_QSIZE_8, | |
363 | SCB_QSIZE_16, | |
364 | SCB_QSIZE_32, | |
365 | SCB_QSIZE_64, | |
366 | SCB_QSIZE_128, | |
367 | SCB_QSIZE_256, | |
368 | SCB_QSIZE_512, | |
369 | SCB_QSIZE_1024, | |
370 | SCB_QSIZE_2048, | |
371 | SCB_QSIZE_4096, | |
372 | SCB_QSIZE_8192, | |
373 | SCB_QSIZE_16384 | |
374 | } | |
375 | } | |
376 | ||
377 | /* | |
378 | * Interrupt Control | |
379 | */ | |
380 | register INTCTL { | |
381 | address 0x018 | |
382 | access_mode RW | |
383 | field SWTMINTMASK 0x80 | |
384 | field SWTMINTEN 0x40 | |
385 | field SWTIMER_START 0x20 | |
386 | field AUTOCLRCMDINT 0x10 | |
387 | field PCIINTEN 0x08 | |
388 | field SCSIINTEN 0x04 | |
389 | field SEQINTEN 0x02 | |
390 | field SPLTINTEN 0x01 | |
391 | } | |
392 | ||
393 | /* | |
394 | * Data FIFO Control | |
395 | */ | |
396 | register DFCNTRL { | |
397 | address 0x019 | |
398 | access_mode RW | |
399 | modes M_DFF0, M_DFF1 | |
400 | field PRELOADEN 0x80 | |
401 | field SCSIENWRDIS 0x40 /* Rev B only. */ | |
402 | field SCSIEN 0x20 | |
403 | field SCSIENACK 0x20 | |
404 | field HDMAEN 0x08 | |
405 | field HDMAENACK 0x08 | |
406 | field DIRECTION 0x04 | |
407 | field DIRECTIONACK 0x04 | |
408 | field FIFOFLUSH 0x02 | |
409 | field FIFOFLUSHACK 0x02 | |
410 | field DIRECTIONEN 0x01 | |
411 | } | |
412 | ||
413 | /* | |
414 | * Device Space Command 0 | |
415 | */ | |
416 | register DSCOMMAND0 { | |
417 | address 0x019 | |
418 | access_mode RW | |
419 | modes M_CFG | |
420 | field CACHETHEN 0x80 /* Cache Threshold enable */ | |
421 | field DPARCKEN 0x40 /* Data Parity Check Enable */ | |
422 | field MPARCKEN 0x20 /* Memory Parity Check Enable */ | |
423 | field EXTREQLCK 0x10 /* External Request Lock */ | |
424 | field DISABLE_TWATE 0x02 /* Rev B or greater */ | |
425 | field CIOPARCKEN 0x01 /* Internal bus parity error enable */ | |
426 | } | |
427 | ||
428 | /* | |
429 | * Data FIFO Status | |
430 | */ | |
431 | register DFSTATUS { | |
432 | address 0x01A | |
433 | access_mode RO | |
434 | modes M_DFF0, M_DFF1 | |
435 | field PRELOAD_AVAIL 0x80 | |
436 | field PKT_PRELOAD_AVAIL 0x40 | |
437 | field MREQPEND 0x10 | |
438 | field HDONE 0x08 | |
439 | field DFTHRESH 0x04 | |
440 | field FIFOFULL 0x02 | |
441 | field FIFOEMP 0x01 | |
442 | } | |
443 | ||
444 | /* | |
445 | * S/G Cache Pointer | |
446 | */ | |
447 | register SG_CACHE_PRE { | |
448 | address 0x01B | |
449 | access_mode WO | |
450 | modes M_DFF0, M_DFF1 | |
451 | field SG_ADDR_MASK 0xf8 | |
452 | field ODD_SEG 0x04 | |
453 | field LAST_SEG 0x02 | |
454 | } | |
455 | ||
456 | register SG_CACHE_SHADOW { | |
457 | address 0x01B | |
458 | access_mode RO | |
459 | modes M_DFF0, M_DFF1 | |
460 | field SG_ADDR_MASK 0xf8 | |
461 | field ODD_SEG 0x04 | |
462 | field LAST_SEG 0x02 | |
463 | field LAST_SEG_DONE 0x01 | |
464 | } | |
465 | ||
466 | /* | |
467 | * Arbiter Control | |
468 | */ | |
469 | register ARBCTL { | |
470 | address 0x01B | |
471 | access_mode RW | |
472 | modes M_CFG | |
473 | field RESET_HARB 0x80 | |
474 | field RETRY_SWEN 0x08 | |
475 | field USE_TIME 0x07 | |
476 | } | |
477 | ||
478 | /* | |
479 | * Data Channel Host Address | |
480 | */ | |
481 | register HADDR { | |
482 | address 0x070 | |
483 | access_mode RW | |
484 | size 8 | |
485 | modes M_DFF0, M_DFF1 | |
486 | } | |
487 | ||
488 | /* | |
489 | * Host Overlay DMA Address | |
490 | */ | |
491 | register HODMAADR { | |
492 | address 0x070 | |
493 | access_mode RW | |
494 | size 8 | |
495 | modes M_SCSI | |
496 | } | |
497 | ||
498 | /* | |
499 | * PCI PLL Delay. | |
500 | */ | |
501 | register PLLDELAY { | |
502 | address 0x070 | |
503 | access_mode RW | |
504 | size 1 | |
505 | modes M_CFG | |
506 | field SPLIT_DROP_REQ 0x80 | |
507 | } | |
508 | ||
509 | /* | |
510 | * Data Channel Host Count | |
511 | */ | |
512 | register HCNT { | |
513 | address 0x078 | |
514 | access_mode RW | |
515 | size 3 | |
516 | modes M_DFF0, M_DFF1 | |
517 | } | |
518 | ||
519 | /* | |
520 | * Host Overlay DMA Count | |
521 | */ | |
522 | register HODMACNT { | |
523 | address 0x078 | |
524 | access_mode RW | |
525 | size 2 | |
526 | modes M_SCSI | |
527 | } | |
528 | ||
529 | /* | |
530 | * Host Overlay DMA Enable | |
531 | */ | |
532 | register HODMAEN { | |
533 | address 0x07A | |
534 | access_mode RW | |
535 | modes M_SCSI | |
536 | } | |
537 | ||
538 | /* | |
539 | * Scatter/Gather Host Address | |
540 | */ | |
541 | register SGHADDR { | |
542 | address 0x07C | |
543 | access_mode RW | |
544 | size 8 | |
545 | modes M_DFF0, M_DFF1 | |
546 | } | |
547 | ||
548 | /* | |
549 | * SCB Host Address | |
550 | */ | |
551 | register SCBHADDR { | |
552 | address 0x07C | |
553 | access_mode RW | |
554 | size 8 | |
555 | modes M_CCHAN | |
556 | } | |
557 | ||
558 | /* | |
559 | * Scatter/Gather Host Count | |
560 | */ | |
561 | register SGHCNT { | |
562 | address 0x084 | |
563 | access_mode RW | |
564 | modes M_DFF0, M_DFF1 | |
565 | } | |
566 | ||
567 | /* | |
568 | * SCB Host Count | |
569 | */ | |
570 | register SCBHCNT { | |
571 | address 0x084 | |
572 | access_mode RW | |
573 | modes M_CCHAN | |
574 | } | |
575 | ||
576 | /* | |
577 | * Data FIFO Threshold | |
578 | */ | |
579 | register DFF_THRSH { | |
580 | address 0x088 | |
581 | access_mode RW | |
582 | modes M_CFG | |
583 | field WR_DFTHRSH 0x70 { | |
584 | WR_DFTHRSH_MIN, | |
585 | WR_DFTHRSH_25, | |
586 | WR_DFTHRSH_50, | |
587 | WR_DFTHRSH_63, | |
588 | WR_DFTHRSH_75, | |
589 | WR_DFTHRSH_85, | |
590 | WR_DFTHRSH_90, | |
591 | WR_DFTHRSH_MAX | |
592 | } | |
593 | field RD_DFTHRSH 0x07 { | |
594 | RD_DFTHRSH_MIN, | |
595 | RD_DFTHRSH_25, | |
596 | RD_DFTHRSH_50, | |
597 | RD_DFTHRSH_63, | |
598 | RD_DFTHRSH_75, | |
599 | RD_DFTHRSH_85, | |
600 | RD_DFTHRSH_90, | |
601 | RD_DFTHRSH_MAX | |
602 | } | |
603 | } | |
604 | ||
605 | /* | |
606 | * ROM Address | |
607 | */ | |
608 | register ROMADDR { | |
609 | address 0x08A | |
610 | access_mode RW | |
611 | size 3 | |
612 | } | |
613 | ||
614 | /* | |
615 | * ROM Control | |
616 | */ | |
617 | register ROMCNTRL { | |
618 | address 0x08D | |
619 | access_mode RW | |
620 | field ROMOP 0xE0 | |
621 | field ROMSPD 0x18 | |
622 | field REPEAT 0x02 | |
623 | field RDY 0x01 | |
624 | } | |
625 | ||
626 | /* | |
627 | * ROM Data | |
628 | */ | |
629 | register ROMDATA { | |
630 | address 0x08E | |
631 | access_mode RW | |
632 | } | |
633 | ||
634 | /* | |
635 | * Data Channel Receive Message 0 | |
636 | */ | |
637 | register DCHRXMSG0 { | |
638 | address 0x090 | |
639 | access_mode RO | |
640 | modes M_DFF0, M_DFF1 | |
641 | field CDNUM 0xF8 | |
642 | field CFNUM 0x07 | |
643 | } | |
644 | ||
645 | /* | |
646 | * CMC Recieve Message 0 | |
647 | */ | |
648 | register CMCRXMSG0 { | |
649 | address 0x090 | |
650 | access_mode RO | |
651 | modes M_CCHAN | |
652 | field CDNUM 0xF8 | |
653 | field CFNUM 0x07 | |
654 | } | |
655 | ||
656 | /* | |
657 | * Overlay Recieve Message 0 | |
658 | */ | |
659 | register OVLYRXMSG0 { | |
660 | address 0x090 | |
661 | access_mode RO | |
662 | modes M_SCSI | |
663 | field CDNUM 0xF8 | |
664 | field CFNUM 0x07 | |
665 | } | |
666 | ||
667 | /* | |
668 | * Relaxed Order Enable | |
669 | */ | |
670 | register ROENABLE { | |
671 | address 0x090 | |
672 | access_mode RW | |
673 | modes M_CFG | |
674 | field MSIROEN 0x20 | |
675 | field OVLYROEN 0x10 | |
676 | field CMCROEN 0x08 | |
677 | field SGROEN 0x04 | |
678 | field DCH1ROEN 0x02 | |
679 | field DCH0ROEN 0x01 | |
680 | } | |
681 | ||
682 | /* | |
683 | * Data Channel Receive Message 1 | |
684 | */ | |
685 | register DCHRXMSG1 { | |
686 | address 0x091 | |
687 | access_mode RO | |
688 | modes M_DFF0, M_DFF1 | |
689 | field CBNUM 0xFF | |
690 | } | |
691 | ||
692 | /* | |
693 | * CMC Recieve Message 1 | |
694 | */ | |
695 | register CMCRXMSG1 { | |
696 | address 0x091 | |
697 | access_mode RO | |
698 | modes M_CCHAN | |
699 | field CBNUM 0xFF | |
700 | } | |
701 | ||
702 | /* | |
703 | * Overlay Recieve Message 1 | |
704 | */ | |
705 | register OVLYRXMSG1 { | |
706 | address 0x091 | |
707 | access_mode RO | |
708 | modes M_SCSI | |
709 | field CBNUM 0xFF | |
710 | } | |
711 | ||
712 | /* | |
713 | * No Snoop Enable | |
714 | */ | |
715 | register NSENABLE { | |
716 | address 0x091 | |
717 | access_mode RW | |
718 | modes M_CFG | |
719 | field MSINSEN 0x20 | |
720 | field OVLYNSEN 0x10 | |
721 | field CMCNSEN 0x08 | |
722 | field SGNSEN 0x04 | |
723 | field DCH1NSEN 0x02 | |
724 | field DCH0NSEN 0x01 | |
725 | } | |
726 | ||
727 | /* | |
728 | * Data Channel Receive Message 2 | |
729 | */ | |
730 | register DCHRXMSG2 { | |
731 | address 0x092 | |
732 | access_mode RO | |
733 | modes M_DFF0, M_DFF1 | |
734 | field MINDEX 0xFF | |
735 | } | |
736 | ||
737 | /* | |
738 | * CMC Recieve Message 2 | |
739 | */ | |
740 | register CMCRXMSG2 { | |
741 | address 0x092 | |
742 | access_mode RO | |
743 | modes M_CCHAN | |
744 | field MINDEX 0xFF | |
745 | } | |
746 | ||
747 | /* | |
748 | * Overlay Recieve Message 2 | |
749 | */ | |
750 | register OVLYRXMSG2 { | |
751 | address 0x092 | |
752 | access_mode RO | |
753 | modes M_SCSI | |
754 | field MINDEX 0xFF | |
755 | } | |
756 | ||
757 | /* | |
758 | * Outstanding Split Transactions | |
759 | */ | |
760 | register OST { | |
761 | address 0x092 | |
762 | access_mode RW | |
763 | modes M_CFG | |
764 | } | |
765 | ||
766 | /* | |
767 | * Data Channel Receive Message 3 | |
768 | */ | |
769 | register DCHRXMSG3 { | |
770 | address 0x093 | |
771 | access_mode RO | |
772 | modes M_DFF0, M_DFF1 | |
773 | field MCLASS 0x0F | |
774 | } | |
775 | ||
776 | /* | |
777 | * CMC Recieve Message 3 | |
778 | */ | |
779 | register CMCRXMSG3 { | |
780 | address 0x093 | |
781 | access_mode RO | |
782 | modes M_CCHAN | |
783 | field MCLASS 0x0F | |
784 | } | |
785 | ||
786 | /* | |
787 | * Overlay Recieve Message 3 | |
788 | */ | |
789 | register OVLYRXMSG3 { | |
790 | address 0x093 | |
791 | access_mode RO | |
792 | modes M_SCSI | |
793 | field MCLASS 0x0F | |
794 | } | |
795 | ||
796 | /* | |
797 | * PCI-X Control | |
798 | */ | |
799 | register PCIXCTL { | |
800 | address 0x093 | |
801 | access_mode RW | |
802 | modes M_CFG | |
803 | field SERRPULSE 0x80 | |
804 | field UNEXPSCIEN 0x20 | |
805 | field SPLTSMADIS 0x10 | |
806 | field SPLTSTADIS 0x08 | |
807 | field SRSPDPEEN 0x04 | |
808 | field TSCSERREN 0x02 | |
809 | field CMPABCDIS 0x01 | |
810 | } | |
811 | ||
812 | /* | |
813 | * CMC Sequencer Byte Count | |
814 | */ | |
815 | register CMCSEQBCNT { | |
816 | address 0x094 | |
817 | access_mode RO | |
818 | modes M_CCHAN | |
819 | } | |
820 | ||
821 | /* | |
822 | * Overlay Sequencer Byte Count | |
823 | */ | |
824 | register OVLYSEQBCNT { | |
825 | address 0x094 | |
826 | access_mode RO | |
827 | modes M_SCSI | |
828 | } | |
829 | ||
830 | /* | |
831 | * Data Channel Sequencer Byte Count | |
832 | */ | |
833 | register DCHSEQBCNT { | |
834 | address 0x094 | |
835 | access_mode RO | |
836 | size 2 | |
837 | modes M_DFF0, M_DFF1 | |
838 | } | |
839 | ||
840 | /* | |
841 | * Data Channel Split Status 0 | |
842 | */ | |
843 | register DCHSPLTSTAT0 { | |
844 | address 0x096 | |
845 | access_mode RW | |
846 | modes M_DFF0, M_DFF1 | |
847 | field STAETERM 0x80 | |
848 | field SCBCERR 0x40 | |
849 | field SCADERR 0x20 | |
850 | field SCDATBUCKET 0x10 | |
851 | field CNTNOTCMPLT 0x08 | |
852 | field RXOVRUN 0x04 | |
853 | field RXSCEMSG 0x02 | |
854 | field RXSPLTRSP 0x01 | |
855 | } | |
856 | ||
857 | /* | |
858 | * CMC Split Status 0 | |
859 | */ | |
860 | register CMCSPLTSTAT0 { | |
861 | address 0x096 | |
862 | access_mode RW | |
863 | modes M_CCHAN | |
864 | field STAETERM 0x80 | |
865 | field SCBCERR 0x40 | |
866 | field SCADERR 0x20 | |
867 | field SCDATBUCKET 0x10 | |
868 | field CNTNOTCMPLT 0x08 | |
869 | field RXOVRUN 0x04 | |
870 | field RXSCEMSG 0x02 | |
871 | field RXSPLTRSP 0x01 | |
872 | } | |
873 | ||
874 | /* | |
875 | * Overlay Split Status 0 | |
876 | */ | |
877 | register OVLYSPLTSTAT0 { | |
878 | address 0x096 | |
879 | access_mode RW | |
880 | modes M_SCSI | |
881 | field STAETERM 0x80 | |
882 | field SCBCERR 0x40 | |
883 | field SCADERR 0x20 | |
884 | field SCDATBUCKET 0x10 | |
885 | field CNTNOTCMPLT 0x08 | |
886 | field RXOVRUN 0x04 | |
887 | field RXSCEMSG 0x02 | |
888 | field RXSPLTRSP 0x01 | |
889 | } | |
890 | ||
891 | /* | |
892 | * Data Channel Split Status 1 | |
893 | */ | |
894 | register DCHSPLTSTAT1 { | |
895 | address 0x097 | |
896 | access_mode RW | |
897 | modes M_DFF0, M_DFF1 | |
898 | field RXDATABUCKET 0x01 | |
899 | } | |
900 | ||
901 | /* | |
902 | * CMC Split Status 1 | |
903 | */ | |
904 | register CMCSPLTSTAT1 { | |
905 | address 0x097 | |
906 | access_mode RW | |
907 | modes M_CCHAN | |
908 | field RXDATABUCKET 0x01 | |
909 | } | |
910 | ||
911 | /* | |
912 | * Overlay Split Status 1 | |
913 | */ | |
914 | register OVLYSPLTSTAT1 { | |
915 | address 0x097 | |
916 | access_mode RW | |
917 | modes M_SCSI | |
918 | field RXDATABUCKET 0x01 | |
919 | } | |
920 | ||
921 | /* | |
922 | * S/G Receive Message 0 | |
923 | */ | |
924 | register SGRXMSG0 { | |
925 | address 0x098 | |
926 | access_mode RO | |
927 | modes M_DFF0, M_DFF1 | |
928 | field CDNUM 0xF8 | |
929 | field CFNUM 0x07 | |
930 | } | |
931 | ||
932 | /* | |
933 | * S/G Receive Message 1 | |
934 | */ | |
935 | register SGRXMSG1 { | |
936 | address 0x099 | |
937 | access_mode RO | |
938 | modes M_DFF0, M_DFF1 | |
939 | field CBNUM 0xFF | |
940 | } | |
941 | ||
942 | /* | |
943 | * S/G Receive Message 2 | |
944 | */ | |
945 | register SGRXMSG2 { | |
946 | address 0x09A | |
947 | access_mode RO | |
948 | modes M_DFF0, M_DFF1 | |
949 | field MINDEX 0xFF | |
950 | } | |
951 | ||
952 | /* | |
953 | * S/G Receive Message 3 | |
954 | */ | |
955 | register SGRXMSG3 { | |
956 | address 0x09B | |
957 | access_mode RO | |
958 | modes M_DFF0, M_DFF1 | |
959 | field MCLASS 0x0F | |
960 | } | |
961 | ||
962 | /* | |
963 | * Slave Split Out Address 0 | |
964 | */ | |
965 | register SLVSPLTOUTADR0 { | |
966 | address 0x098 | |
967 | access_mode RO | |
968 | modes M_SCSI | |
969 | field LOWER_ADDR 0x7F | |
970 | } | |
971 | ||
972 | /* | |
973 | * Slave Split Out Address 1 | |
974 | */ | |
975 | register SLVSPLTOUTADR1 { | |
976 | address 0x099 | |
977 | access_mode RO | |
978 | modes M_SCSI | |
979 | field REQ_DNUM 0xF8 | |
980 | field REQ_FNUM 0x07 | |
981 | } | |
982 | ||
983 | /* | |
984 | * Slave Split Out Address 2 | |
985 | */ | |
986 | register SLVSPLTOUTADR2 { | |
987 | address 0x09A | |
988 | access_mode RO | |
989 | modes M_SCSI | |
990 | field REQ_BNUM 0xFF | |
991 | } | |
992 | ||
993 | /* | |
994 | * Slave Split Out Address 3 | |
995 | */ | |
996 | register SLVSPLTOUTADR3 { | |
997 | address 0x09B | |
998 | access_mode RO | |
999 | modes M_SCSI | |
1000 | field RLXORD 020 | |
1001 | field TAG_NUM 0x1F | |
1002 | } | |
1003 | ||
1004 | /* | |
1005 | * SG Sequencer Byte Count | |
1006 | */ | |
1007 | register SGSEQBCNT { | |
1008 | address 0x09C | |
1009 | access_mode RO | |
1010 | modes M_DFF0, M_DFF1 | |
1011 | } | |
1012 | ||
1013 | /* | |
1014 | * Slave Split Out Attribute 0 | |
1015 | */ | |
1016 | register SLVSPLTOUTATTR0 { | |
1017 | address 0x09C | |
1018 | access_mode RO | |
1019 | modes M_SCSI | |
1020 | field LOWER_BCNT 0xFF | |
1021 | } | |
1022 | ||
1023 | /* | |
1024 | * Slave Split Out Attribute 1 | |
1025 | */ | |
1026 | register SLVSPLTOUTATTR1 { | |
1027 | address 0x09D | |
1028 | access_mode RO | |
1029 | modes M_SCSI | |
1030 | field CMPLT_DNUM 0xF8 | |
1031 | field CMPLT_FNUM 0x07 | |
1032 | } | |
1033 | ||
1034 | /* | |
1035 | * Slave Split Out Attribute 2 | |
1036 | */ | |
1037 | register SLVSPLTOUTATTR2 { | |
1038 | address 0x09E | |
1039 | access_mode RO | |
1040 | size 2 | |
1041 | modes M_SCSI | |
1042 | field CMPLT_BNUM 0xFF | |
1043 | } | |
1044 | /* | |
1045 | * S/G Split Status 0 | |
1046 | */ | |
1047 | register SGSPLTSTAT0 { | |
1048 | address 0x09E | |
1049 | access_mode RW | |
1050 | modes M_DFF0, M_DFF1 | |
1051 | field STAETERM 0x80 | |
1052 | field SCBCERR 0x40 | |
1053 | field SCADERR 0x20 | |
1054 | field SCDATBUCKET 0x10 | |
1055 | field CNTNOTCMPLT 0x08 | |
1056 | field RXOVRUN 0x04 | |
1057 | field RXSCEMSG 0x02 | |
1058 | field RXSPLTRSP 0x01 | |
1059 | } | |
1060 | ||
1061 | /* | |
1062 | * S/G Split Status 1 | |
1063 | */ | |
1064 | register SGSPLTSTAT1 { | |
1065 | address 0x09F | |
1066 | access_mode RW | |
1067 | modes M_DFF0, M_DFF1 | |
1068 | field RXDATABUCKET 0x01 | |
1069 | } | |
1070 | ||
1071 | /* | |
1072 | * Special Function | |
1073 | */ | |
1074 | register SFUNCT { | |
1075 | address 0x09f | |
1076 | access_mode RW | |
1077 | modes M_CFG | |
1078 | field TEST_GROUP 0xF0 | |
1079 | field TEST_NUM 0x0F | |
1080 | } | |
1081 | ||
1082 | /* | |
1083 | * Data FIFO 0 PCI Status | |
1084 | */ | |
1085 | register DF0PCISTAT { | |
1086 | address 0x0A0 | |
1087 | access_mode RW | |
1088 | modes M_CFG | |
1089 | field DPE 0x80 | |
1090 | field SSE 0x40 | |
1091 | field RMA 0x20 | |
1092 | field RTA 0x10 | |
1093 | field SCAAPERR 0x08 | |
1094 | field RDPERR 0x04 | |
1095 | field TWATERR 0x02 | |
1096 | field DPR 0x01 | |
1097 | } | |
1098 | ||
1099 | /* | |
1100 | * Data FIFO 1 PCI Status | |
1101 | */ | |
1102 | register DF1PCISTAT { | |
1103 | address 0x0A1 | |
1104 | access_mode RW | |
1105 | modes M_CFG | |
1106 | field DPE 0x80 | |
1107 | field SSE 0x40 | |
1108 | field RMA 0x20 | |
1109 | field RTA 0x10 | |
1110 | field SCAAPERR 0x08 | |
1111 | field RDPERR 0x04 | |
1112 | field TWATERR 0x02 | |
1113 | field DPR 0x01 | |
1114 | } | |
1115 | ||
1116 | /* | |
1117 | * S/G PCI Status | |
1118 | */ | |
1119 | register SGPCISTAT { | |
1120 | address 0x0A2 | |
1121 | access_mode RW | |
1122 | modes M_CFG | |
1123 | field DPE 0x80 | |
1124 | field SSE 0x40 | |
1125 | field RMA 0x20 | |
1126 | field RTA 0x10 | |
1127 | field SCAAPERR 0x08 | |
1128 | field RDPERR 0x04 | |
1129 | field DPR 0x01 | |
1130 | } | |
1131 | ||
1132 | /* | |
1133 | * CMC PCI Status | |
1134 | */ | |
1135 | register CMCPCISTAT { | |
1136 | address 0x0A3 | |
1137 | access_mode RW | |
1138 | modes M_CFG | |
1139 | field DPE 0x80 | |
1140 | field SSE 0x40 | |
1141 | field RMA 0x20 | |
1142 | field RTA 0x10 | |
1143 | field SCAAPERR 0x08 | |
1144 | field RDPERR 0x04 | |
1145 | field TWATERR 0x02 | |
1146 | field DPR 0x01 | |
1147 | } | |
1148 | ||
1149 | /* | |
1150 | * Overlay PCI Status | |
1151 | */ | |
1152 | register OVLYPCISTAT { | |
1153 | address 0x0A4 | |
1154 | access_mode RW | |
1155 | modes M_CFG | |
1156 | field DPE 0x80 | |
1157 | field SSE 0x40 | |
1158 | field RMA 0x20 | |
1159 | field RTA 0x10 | |
1160 | field SCAAPERR 0x08 | |
1161 | field RDPERR 0x04 | |
1162 | field DPR 0x01 | |
1163 | } | |
1164 | ||
1165 | /* | |
1166 | * PCI Status for MSI Master DMA Transfer | |
1167 | */ | |
1168 | register MSIPCISTAT { | |
1169 | address 0x0A6 | |
1170 | access_mode RW | |
1171 | modes M_CFG | |
1172 | field SSE 0x40 | |
1173 | field RMA 0x20 | |
1174 | field RTA 0x10 | |
1175 | field CLRPENDMSI 0x08 | |
1176 | field TWATERR 0x02 | |
1177 | field DPR 0x01 | |
1178 | } | |
1179 | ||
1180 | /* | |
1181 | * PCI Status for Target | |
1182 | */ | |
1183 | register TARGPCISTAT { | |
1184 | address 0x0A7 | |
1185 | access_mode RW | |
1186 | modes M_CFG | |
1187 | field DPE 0x80 | |
1188 | field SSE 0x40 | |
1189 | field STA 0x08 | |
1190 | field TWATERR 0x02 | |
1191 | } | |
1192 | ||
1193 | /* | |
1194 | * LQ Packet In | |
11668bb6 | 1195 | * The last LQ Packet recieved |
1da177e4 LT |
1196 | */ |
1197 | register LQIN { | |
1198 | address 0x020 | |
1199 | access_mode RW | |
1200 | size 20 | |
1201 | modes M_DFF0, M_DFF1, M_SCSI | |
1202 | } | |
1203 | ||
1204 | /* | |
1205 | * SCB Type Pointer | |
1206 | * SCB offset for Target Mode SCB type information | |
1207 | */ | |
1208 | register TYPEPTR { | |
1209 | address 0x020 | |
1210 | access_mode RW | |
1211 | modes M_CFG | |
1212 | } | |
1213 | ||
1214 | /* | |
1215 | * Queue Tag Pointer | |
1216 | * SCB offset to the Two Byte tag identifier used for target mode. | |
1217 | */ | |
1218 | register TAGPTR { | |
1219 | address 0x021 | |
1220 | access_mode RW | |
1221 | modes M_CFG | |
1222 | } | |
1223 | ||
1224 | /* | |
1225 | * Logical Unit Number Pointer | |
1226 | * SCB offset to the LSB (little endian) of the lun field. | |
1227 | */ | |
1228 | register LUNPTR { | |
1229 | address 0x022 | |
1230 | access_mode RW | |
1231 | modes M_CFG | |
1232 | } | |
1233 | ||
1234 | /* | |
1235 | * Data Length Pointer | |
1236 | * SCB offset for the 4 byte data length field in target mode. | |
1237 | */ | |
1238 | register DATALENPTR { | |
1239 | address 0x023 | |
1240 | access_mode RW | |
1241 | modes M_CFG | |
1242 | } | |
1243 | ||
1244 | /* | |
1245 | * Status Length Pointer | |
1246 | * SCB offset to the two byte status field in target SCBs. | |
1247 | */ | |
1248 | register STATLENPTR { | |
1249 | address 0x024 | |
1250 | access_mode RW | |
1251 | modes M_CFG | |
1252 | } | |
1253 | ||
1254 | /* | |
1255 | * Command Length Pointer | |
1256 | * Scb offset for the CDB length field in initiator SCBs. | |
1257 | */ | |
1258 | register CMDLENPTR { | |
1259 | address 0x025 | |
1260 | access_mode RW | |
1261 | modes M_CFG | |
1262 | } | |
1263 | ||
1264 | /* | |
1265 | * Task Attribute Pointer | |
1266 | * Scb offset for the byte field specifying the attribute byte | |
1267 | * to be used in command packets. | |
1268 | */ | |
1269 | register ATTRPTR { | |
1270 | address 0x026 | |
1271 | access_mode RW | |
1272 | modes M_CFG | |
1273 | } | |
1274 | ||
1275 | /* | |
1276 | * Task Management Flags Pointer | |
1277 | * Scb offset for the byte field specifying the attribute flags | |
1278 | * byte to be used in command packets. | |
1279 | */ | |
1280 | register FLAGPTR { | |
1281 | address 0x027 | |
1282 | access_mode RW | |
1283 | modes M_CFG | |
1284 | } | |
1285 | ||
1286 | /* | |
1287 | * Command Pointer | |
1288 | * Scb offset for the first byte in the CDB for initiator SCBs. | |
1289 | */ | |
1290 | register CMDPTR { | |
1291 | address 0x028 | |
1292 | access_mode RW | |
1293 | modes M_CFG | |
1294 | } | |
1295 | ||
1296 | /* | |
1297 | * Queue Next Pointer | |
1298 | * Scb offset for the 2 byte "next scb link". | |
1299 | */ | |
1300 | register QNEXTPTR { | |
1301 | address 0x029 | |
1302 | access_mode RW | |
1303 | modes M_CFG | |
1304 | } | |
1305 | ||
1306 | /* | |
1307 | * SCSI ID Pointer | |
1308 | * Scb offset to the value to place in the SCSIID register | |
1309 | * during target mode connections. | |
1310 | */ | |
1311 | register IDPTR { | |
1312 | address 0x02A | |
1313 | access_mode RW | |
1314 | modes M_CFG | |
1315 | } | |
1316 | ||
1317 | /* | |
1318 | * Command Aborted Byte Pointer | |
1319 | * Offset to the SCB flags field that includes the | |
1320 | * "SCB aborted" status bit. | |
1321 | */ | |
1322 | register ABRTBYTEPTR { | |
1323 | address 0x02B | |
1324 | access_mode RW | |
1325 | modes M_CFG | |
1326 | } | |
1327 | ||
1328 | /* | |
1329 | * Command Aborted Bit Pointer | |
1330 | * Bit offset in the SCB flags field for "SCB aborted" status. | |
1331 | */ | |
1332 | register ABRTBITPTR { | |
1333 | address 0x02C | |
1334 | access_mode RW | |
1335 | modes M_CFG | |
1336 | } | |
1337 | ||
1338 | /* | |
1339 | * Rev B or greater. | |
1340 | */ | |
1341 | register MAXCMDBYTES { | |
1342 | address 0x02D | |
1343 | access_mode RW | |
1344 | modes M_CFG | |
1345 | } | |
1346 | ||
1347 | /* | |
1348 | * Rev B or greater. | |
1349 | */ | |
1350 | register MAXCMD2RCV { | |
1351 | address 0x02E | |
1352 | access_mode RW | |
1353 | modes M_CFG | |
1354 | } | |
1355 | ||
1356 | /* | |
1357 | * Rev B or greater. | |
1358 | */ | |
1359 | register SHORTTHRESH { | |
1360 | address 0x02F | |
1361 | access_mode RW | |
1362 | modes M_CFG | |
1363 | } | |
1364 | ||
1365 | /* | |
1366 | * Logical Unit Number Length | |
1367 | * The length, in bytes, of the SCB lun field. | |
1368 | */ | |
1369 | register LUNLEN { | |
1370 | address 0x030 | |
1371 | access_mode RW | |
1372 | modes M_CFG | |
1373 | mask ILUNLEN 0x0F | |
1374 | mask TLUNLEN 0xF0 | |
1375 | } | |
1376 | const LUNLEN_SINGLE_LEVEL_LUN 0xF | |
1377 | ||
1378 | /* | |
1379 | * CDB Limit | |
1380 | * The size, in bytes, of the embedded CDB field in initator SCBs. | |
1381 | */ | |
1382 | register CDBLIMIT { | |
1383 | address 0x031 | |
1384 | access_mode RW | |
1385 | modes M_CFG | |
1386 | } | |
1387 | ||
1388 | /* | |
1389 | * Maximum Commands | |
1390 | * The maximum number of commands to issue during a | |
1391 | * single packetized connection. | |
1392 | */ | |
1393 | register MAXCMD { | |
1394 | address 0x032 | |
1395 | access_mode RW | |
1396 | modes M_CFG | |
1397 | } | |
1398 | ||
1399 | /* | |
1400 | * Maximum Command Counter | |
1401 | * The number of commands already sent during this connection | |
1402 | */ | |
1403 | register MAXCMDCNT { | |
1404 | address 0x033 | |
1405 | access_mode RW | |
1406 | modes M_CFG | |
1407 | } | |
1408 | ||
1409 | /* | |
1410 | * LQ Packet Reserved Bytes | |
1411 | * The bytes to be sent in the currently reserved fileds | |
1412 | * of all LQ packets. | |
1413 | */ | |
1414 | register LQRSVD01 { | |
1415 | address 0x034 | |
1416 | access_mode RW | |
1417 | modes M_SCSI | |
1418 | } | |
1419 | register LQRSVD16 { | |
1420 | address 0x035 | |
1421 | access_mode RW | |
1422 | modes M_SCSI | |
1423 | } | |
1424 | register LQRSVD17 { | |
1425 | address 0x036 | |
1426 | access_mode RW | |
1427 | modes M_SCSI | |
1428 | } | |
1429 | ||
1430 | /* | |
1431 | * Command Reserved 0 | |
1432 | * The byte to be sent for the reserved byte 0 of | |
1433 | * outgoing command packets. | |
1434 | */ | |
1435 | register CMDRSVD0 { | |
1436 | address 0x037 | |
1437 | access_mode RW | |
1438 | modes M_CFG | |
1439 | } | |
1440 | ||
1441 | /* | |
1442 | * LQ Manager Control 0 | |
1443 | */ | |
1444 | register LQCTL0 { | |
1445 | address 0x038 | |
1446 | access_mode RW | |
1447 | modes M_CFG | |
1448 | field LQITARGCLT 0xC0 | |
1449 | field LQIINITGCLT 0x30 | |
1450 | field LQ0TARGCLT 0x0C | |
1451 | field LQ0INITGCLT 0x03 | |
1452 | } | |
1453 | ||
1454 | /* | |
1455 | * LQ Manager Control 1 | |
1456 | */ | |
1457 | register LQCTL1 { | |
1458 | address 0x038 | |
1459 | access_mode RW | |
1460 | modes M_DFF0, M_DFF1, M_SCSI | |
1461 | field PCI2PCI 0x04 | |
1462 | field SINGLECMD 0x02 | |
1463 | field ABORTPENDING 0x01 | |
1464 | } | |
1465 | ||
1466 | /* | |
1467 | * LQ Manager Control 2 | |
1468 | */ | |
1469 | register LQCTL2 { | |
1470 | address 0x039 | |
1471 | access_mode RW | |
1472 | modes M_DFF0, M_DFF1, M_SCSI | |
1473 | field LQIRETRY 0x80 | |
1474 | field LQICONTINUE 0x40 | |
1475 | field LQITOIDLE 0x20 | |
1476 | field LQIPAUSE 0x10 | |
1477 | field LQORETRY 0x08 | |
1478 | field LQOCONTINUE 0x04 | |
1479 | field LQOTOIDLE 0x02 | |
1480 | field LQOPAUSE 0x01 | |
1481 | } | |
1482 | ||
1483 | /* | |
1484 | * SCSI RAM BIST0 | |
1485 | */ | |
1486 | register SCSBIST0 { | |
1487 | address 0x039 | |
1488 | access_mode RW | |
1489 | modes M_CFG | |
1490 | field GSBISTERR 0x40 | |
1491 | field GSBISTDONE 0x20 | |
1492 | field GSBISTRUN 0x10 | |
1493 | field OSBISTERR 0x04 | |
1494 | field OSBISTDONE 0x02 | |
1495 | field OSBISTRUN 0x01 | |
1496 | } | |
1497 | ||
1498 | /* | |
1499 | * SCSI Sequence Control0 | |
1500 | */ | |
1501 | register SCSISEQ0 { | |
1502 | address 0x03A | |
1503 | access_mode RW | |
1504 | modes M_DFF0, M_DFF1, M_SCSI | |
1505 | field TEMODEO 0x80 | |
1506 | field ENSELO 0x40 | |
1507 | field ENARBO 0x20 | |
1508 | field FORCEBUSFREE 0x10 | |
1509 | field SCSIRSTO 0x01 | |
1510 | } | |
1511 | ||
1512 | /* | |
1513 | * SCSI RAM BIST 1 | |
1514 | */ | |
1515 | register SCSBIST1 { | |
1516 | address 0x03A | |
1517 | access_mode RW | |
1518 | modes M_CFG | |
1519 | field NTBISTERR 0x04 | |
1520 | field NTBISTDONE 0x02 | |
1521 | field NTBISTRUN 0x01 | |
1522 | } | |
1523 | ||
1524 | /* | |
1525 | * SCSI Sequence Control 1 | |
1526 | */ | |
1527 | register SCSISEQ1 { | |
1528 | address 0x03B | |
1529 | access_mode RW | |
1530 | modes M_DFF0, M_DFF1, M_SCSI | |
1531 | field MANUALCTL 0x40 | |
1532 | field ENSELI 0x20 | |
1533 | field ENRSELI 0x10 | |
1534 | field MANUALP 0x0C | |
1535 | field ENAUTOATNP 0x02 | |
1536 | field ALTSTIM 0x01 | |
1537 | } | |
1538 | ||
1539 | /* | |
1540 | * SCSI Transfer Control 0 | |
1541 | */ | |
1542 | register SXFRCTL0 { | |
1543 | address 0x03C | |
1544 | access_mode RW | |
1545 | modes M_SCSI | |
1546 | field DFON 0x80 | |
1547 | field DFPEXP 0x40 | |
1548 | field BIOSCANCELEN 0x10 | |
1549 | field SPIOEN 0x08 | |
1550 | } | |
1551 | ||
1552 | /* | |
1553 | * SCSI Transfer Control 1 | |
1554 | */ | |
1555 | register SXFRCTL1 { | |
1556 | address 0x03D | |
1557 | access_mode RW | |
1558 | modes M_SCSI | |
1559 | field BITBUCKET 0x80 | |
1560 | field ENSACHK 0x40 | |
1561 | field ENSPCHK 0x20 | |
1562 | field STIMESEL 0x18 | |
1563 | field ENSTIMER 0x04 | |
1564 | field ACTNEGEN 0x02 | |
1565 | field STPWEN 0x01 | |
1566 | } | |
1567 | ||
1568 | /* | |
1569 | * SCSI Transfer Control 2 | |
1570 | */ | |
1571 | register SXFRCTL2 { | |
1572 | address 0x03E | |
1573 | access_mode RW | |
1574 | modes M_SCSI | |
1575 | field AUTORSTDIS 0x10 | |
1576 | field CMDDMAEN 0x08 | |
1577 | field ASU 0x07 | |
1578 | } | |
1579 | ||
1580 | /* | |
1581 | * SCSI Bus Initiator IDs | |
1582 | * Bitmask of observed initiators on the bus. | |
1583 | */ | |
1584 | register BUSINITID { | |
1585 | address 0x03C | |
1586 | access_mode RW | |
1587 | modes M_CFG | |
1588 | size 2 | |
1589 | } | |
1590 | ||
1591 | /* | |
1592 | * Data Length Counters | |
1593 | * Packet byte counter. | |
1594 | */ | |
1595 | register DLCOUNT { | |
1596 | address 0x03C | |
1597 | access_mode RW | |
1598 | modes M_DFF0, M_DFF1 | |
1599 | size 3 | |
1600 | } | |
1601 | ||
1602 | /* | |
1603 | * Data FIFO Status | |
1604 | */ | |
1605 | register DFFSTAT { | |
1606 | address 0x03F | |
1607 | access_mode RW | |
1608 | modes M_SCSI | |
1609 | field FIFO1FREE 0x20 | |
1610 | field FIFO0FREE 0x10 | |
1611 | /* | |
1612 | * On the B, this enum only works | |
1613 | * in the read direction. For writes, | |
1614 | * you must use the B version of the | |
1615 | * CURRFIFO_0 definition which is defined | |
1616 | * as a constant outside of this register | |
1617 | * definition to avoid confusing the | |
1618 | * register pretty printing code. | |
1619 | */ | |
1620 | enum CURRFIFO 0x03 { | |
1621 | CURRFIFO_0, | |
1622 | CURRFIFO_1, | |
1623 | CURRFIFO_NONE 0x3 | |
1624 | } | |
1625 | } | |
1626 | ||
1627 | const B_CURRFIFO_0 0x2 | |
1628 | ||
1629 | /* | |
1630 | * SCSI Bus Target IDs | |
1631 | * Bitmask of observed targets on the bus. | |
1632 | */ | |
1633 | register BUSTARGID { | |
1634 | address 0x03E | |
1635 | access_mode RW | |
1636 | modes M_CFG | |
1637 | size 2 | |
1638 | } | |
1639 | ||
1640 | /* | |
1641 | * SCSI Control Signal Out | |
1642 | */ | |
1643 | register SCSISIGO { | |
1644 | address 0x040 | |
1645 | access_mode RW | |
1646 | modes M_DFF0, M_DFF1, M_SCSI | |
1647 | field CDO 0x80 | |
1648 | field IOO 0x40 | |
1649 | field MSGO 0x20 | |
1650 | field ATNO 0x10 | |
1651 | field SELO 0x08 | |
1652 | field BSYO 0x04 | |
1653 | field REQO 0x02 | |
1654 | field ACKO 0x01 | |
1655 | /* | |
1656 | * Possible phases to write into SCSISIG0 | |
1657 | */ | |
1658 | enum PHASE_MASK CDO|IOO|MSGO { | |
1659 | P_DATAOUT 0x0, | |
1660 | P_DATAIN IOO, | |
1661 | P_DATAOUT_DT P_DATAOUT|MSGO, | |
1662 | P_DATAIN_DT P_DATAIN|MSGO, | |
1663 | P_COMMAND CDO, | |
1664 | P_MESGOUT CDO|MSGO, | |
1665 | P_STATUS CDO|IOO, | |
1666 | P_MESGIN CDO|IOO|MSGO | |
1667 | } | |
1668 | } | |
1669 | ||
1670 | register SCSISIGI { | |
1671 | address 0x041 | |
1672 | access_mode RO | |
1673 | modes M_DFF0, M_DFF1, M_SCSI | |
1674 | field CDI 0x80 | |
1675 | field IOI 0x40 | |
1676 | field MSGI 0x20 | |
1677 | field ATNI 0x10 | |
1678 | field SELI 0x08 | |
1679 | field BSYI 0x04 | |
1680 | field REQI 0x02 | |
1681 | field ACKI 0x01 | |
1682 | /* | |
1683 | * Possible phases in SCSISIGI | |
1684 | */ | |
1685 | enum PHASE_MASK CDO|IOO|MSGO { | |
1686 | P_DATAOUT 0x0, | |
1687 | P_DATAIN IOO, | |
1688 | P_DATAOUT_DT P_DATAOUT|MSGO, | |
1689 | P_DATAIN_DT P_DATAIN|MSGO, | |
1690 | P_COMMAND CDO, | |
1691 | P_MESGOUT CDO|MSGO, | |
1692 | P_STATUS CDO|IOO, | |
1693 | P_MESGIN CDO|IOO|MSGO | |
1694 | } | |
1695 | } | |
1696 | ||
1697 | /* | |
1698 | * Multiple Target IDs | |
1699 | * Bitmask of ids to respond as a target. | |
1700 | */ | |
1701 | register MULTARGID { | |
1702 | address 0x040 | |
1703 | access_mode RW | |
1704 | modes M_CFG | |
1705 | size 2 | |
1706 | } | |
1707 | ||
1708 | /* | |
1709 | * SCSI Phase | |
1710 | */ | |
1711 | register SCSIPHASE { | |
1712 | address 0x042 | |
1713 | access_mode RO | |
1714 | modes M_DFF0, M_DFF1, M_SCSI | |
1715 | field STATUS_PHASE 0x20 | |
1716 | field COMMAND_PHASE 0x10 | |
1717 | field MSG_IN_PHASE 0x08 | |
1718 | field MSG_OUT_PHASE 0x04 | |
1719 | field DATA_PHASE_MASK 0x03 { | |
1720 | DATA_OUT_PHASE 0x01, | |
1721 | DATA_IN_PHASE 0x02 | |
1722 | } | |
1723 | } | |
1724 | ||
1725 | /* | |
1726 | * SCSI Data 0 Image | |
1727 | */ | |
1728 | register SCSIDAT0_IMG { | |
1729 | address 0x043 | |
1730 | access_mode RW | |
1731 | modes M_DFF0, M_DFF1, M_SCSI | |
1732 | } | |
1733 | ||
1734 | /* | |
1735 | * SCSI Latched Data | |
1736 | */ | |
1737 | register SCSIDAT { | |
1738 | address 0x044 | |
1739 | access_mode RW | |
1740 | modes M_DFF0, M_DFF1, M_SCSI | |
1741 | size 2 | |
1742 | } | |
1743 | ||
1744 | /* | |
1745 | * SCSI Data Bus | |
1746 | */ | |
1747 | register SCSIBUS { | |
1748 | address 0x046 | |
1749 | access_mode RW | |
1750 | modes M_DFF0, M_DFF1, M_SCSI | |
1751 | size 2 | |
1752 | } | |
1753 | ||
1754 | /* | |
1755 | * Target ID In | |
1756 | */ | |
1757 | register TARGIDIN { | |
1758 | address 0x048 | |
1759 | access_mode RO | |
1760 | modes M_DFF0, M_DFF1, M_SCSI | |
1761 | field CLKOUT 0x80 | |
1762 | field TARGID 0x0F | |
1763 | } | |
1764 | ||
1765 | /* | |
1766 | * Selection/Reselection ID | |
1767 | * Upper four bits are the device id. The ONEBIT is set when the re/selecting | |
1768 | * device did not set its own ID. | |
1769 | */ | |
1770 | register SELID { | |
1771 | address 0x049 | |
1772 | access_mode RW | |
1773 | modes M_DFF0, M_DFF1, M_SCSI | |
1774 | field SELID_MASK 0xf0 | |
1775 | field ONEBIT 0x08 | |
1776 | } | |
1777 | ||
1778 | /* | |
1779 | * SCSI Block Control | |
1780 | * Controls Bus type and channel selection. SELWIDE allows for the | |
1781 | * coexistence of 8bit and 16bit devices on a wide bus. | |
1782 | */ | |
1783 | register SBLKCTL { | |
1784 | address 0x04A | |
1785 | access_mode RW | |
1786 | modes M_DFF0, M_DFF1, M_SCSI | |
1787 | field DIAGLEDEN 0x80 | |
1788 | field DIAGLEDON 0x40 | |
1789 | field ENAB40 0x08 /* LVD transceiver active */ | |
1790 | field ENAB20 0x04 /* SE/HVD transceiver active */ | |
1791 | field SELWIDE 0x02 | |
1792 | } | |
1793 | ||
1794 | /* | |
1795 | * Option Mode | |
1796 | */ | |
1797 | register OPTIONMODE { | |
1798 | address 0x04A | |
1799 | access_mode RW | |
1800 | modes M_CFG | |
1801 | field BIOSCANCTL 0x80 | |
1802 | field AUTOACKEN 0x40 | |
1803 | field BIASCANCTL 0x20 | |
1804 | field BUSFREEREV 0x10 | |
1805 | field ENDGFORMCHK 0x04 | |
1806 | field AUTO_MSGOUT_DE 0x02 | |
1807 | mask OPTIONMODE_DEFAULTS AUTO_MSGOUT_DE | |
1808 | } | |
1809 | ||
1810 | /* | |
1811 | * SCSI Status 0 | |
1812 | */ | |
1813 | register SSTAT0 { | |
1814 | address 0x04B | |
1815 | access_mode RO | |
1816 | modes M_DFF0, M_DFF1, M_SCSI | |
1817 | field TARGET 0x80 /* Board acting as target */ | |
1818 | field SELDO 0x40 /* Selection Done */ | |
1819 | field SELDI 0x20 /* Board has been selected */ | |
1820 | field SELINGO 0x10 /* Selection In Progress */ | |
1821 | field IOERR 0x08 /* LVD Tranceiver mode changed */ | |
1822 | field OVERRUN 0x04 /* SCSI Offset overrun detected */ | |
1823 | field SPIORDY 0x02 /* SCSI PIO Ready */ | |
1824 | field ARBDO 0x01 /* Arbitration Done Out */ | |
1825 | } | |
1826 | ||
1827 | /* | |
1828 | * Clear SCSI Interrupt 0 | |
1829 | * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT0. | |
1830 | */ | |
1831 | register CLRSINT0 { | |
1832 | address 0x04B | |
1833 | access_mode WO | |
1834 | modes M_DFF0, M_DFF1, M_SCSI | |
1835 | field CLRSELDO 0x40 | |
1836 | field CLRSELDI 0x20 | |
1837 | field CLRSELINGO 0x10 | |
1838 | field CLRIOERR 0x08 | |
1839 | field CLROVERRUN 0x04 | |
1840 | field CLRSPIORDY 0x02 | |
1841 | field CLRARBDO 0x01 | |
1842 | } | |
1843 | ||
1844 | /* | |
1845 | * SCSI Interrupt Mode 0 | |
1846 | * Setting any bit will enable the corresponding function | |
1847 | * in SIMODE0 to interrupt via the IRQ pin. | |
1848 | */ | |
1849 | register SIMODE0 { | |
1850 | address 0x04B | |
1851 | access_mode RW | |
1852 | modes M_CFG | |
1853 | field ENSELDO 0x40 | |
1854 | field ENSELDI 0x20 | |
1855 | field ENSELINGO 0x10 | |
1856 | field ENIOERR 0x08 | |
1857 | field ENOVERRUN 0x04 | |
1858 | field ENSPIORDY 0x02 | |
1859 | field ENARBDO 0x01 | |
1860 | } | |
1861 | ||
1862 | /* | |
1863 | * SCSI Status 1 | |
1864 | */ | |
1865 | register SSTAT1 { | |
1866 | address 0x04C | |
1867 | access_mode RO | |
1868 | modes M_DFF0, M_DFF1, M_SCSI | |
1869 | field SELTO 0x80 | |
1870 | field ATNTARG 0x40 | |
1871 | field SCSIRSTI 0x20 | |
1872 | field PHASEMIS 0x10 | |
1873 | field BUSFREE 0x08 | |
1874 | field SCSIPERR 0x04 | |
1875 | field STRB2FAST 0x02 | |
1876 | field REQINIT 0x01 | |
1877 | } | |
1878 | ||
1879 | /* | |
1880 | * Clear SCSI Interrupt 1 | |
1881 | * Writing a 1 to a bit clears the associated SCSI Interrupt in SSTAT1. | |
1882 | */ | |
1883 | register CLRSINT1 { | |
1884 | address 0x04C | |
1885 | access_mode WO | |
1886 | modes M_DFF0, M_DFF1, M_SCSI | |
1887 | field CLRSELTIMEO 0x80 | |
1888 | field CLRATNO 0x40 | |
1889 | field CLRSCSIRSTI 0x20 | |
1890 | field CLRBUSFREE 0x08 | |
1891 | field CLRSCSIPERR 0x04 | |
1892 | field CLRSTRB2FAST 0x02 | |
1893 | field CLRREQINIT 0x01 | |
1894 | } | |
1895 | ||
1896 | /* | |
1897 | * SCSI Status 2 | |
1898 | */ | |
1899 | register SSTAT2 { | |
1900 | address 0x04d | |
1901 | access_mode RO | |
1902 | modes M_DFF0, M_DFF1, M_SCSI | |
1903 | field BUSFREETIME 0xc0 { | |
1904 | BUSFREE_LQO 0x40, | |
1905 | BUSFREE_DFF0 0x80, | |
1906 | BUSFREE_DFF1 0xC0 | |
1907 | } | |
1908 | field NONPACKREQ 0x20 | |
1909 | field EXP_ACTIVE 0x10 /* SCSI Expander Active */ | |
1910 | field BSYX 0x08 /* Busy Expander */ | |
1911 | field WIDE_RES 0x04 /* Modes 0 and 1 only */ | |
1912 | field SDONE 0x02 /* Modes 0 and 1 only */ | |
1913 | field DMADONE 0x01 /* Modes 0 and 1 only */ | |
1914 | } | |
1915 | ||
1916 | /* | |
1917 | * Clear SCSI Interrupt 2 | |
1918 | */ | |
1919 | register CLRSINT2 { | |
1920 | address 0x04D | |
1921 | access_mode WO | |
1922 | modes M_DFF0, M_DFF1, M_SCSI | |
1923 | field CLRNONPACKREQ 0x20 | |
1924 | field CLRWIDE_RES 0x04 /* Modes 0 and 1 only */ | |
1925 | field CLRSDONE 0x02 /* Modes 0 and 1 only */ | |
1926 | field CLRDMADONE 0x01 /* Modes 0 and 1 only */ | |
1927 | } | |
1928 | ||
1929 | /* | |
1930 | * SCSI Interrupt Mode 2 | |
1931 | */ | |
1932 | register SIMODE2 { | |
1933 | address 0x04D | |
1934 | access_mode RW | |
1935 | modes M_CFG | |
1936 | field ENWIDE_RES 0x04 | |
1937 | field ENSDONE 0x02 | |
1938 | field ENDMADONE 0x01 | |
1939 | } | |
1940 | ||
1941 | /* | |
1942 | * Physical Error Diagnosis | |
1943 | */ | |
1944 | register PERRDIAG { | |
1945 | address 0x04E | |
1946 | access_mode RO | |
1947 | modes M_DFF0, M_DFF1, M_SCSI | |
1948 | field HIZERO 0x80 | |
1949 | field HIPERR 0x40 | |
1950 | field PREVPHASE 0x20 | |
1951 | field PARITYERR 0x10 | |
1952 | field AIPERR 0x08 | |
1953 | field CRCERR 0x04 | |
1954 | field DGFORMERR 0x02 | |
1955 | field DTERR 0x01 | |
1956 | } | |
1957 | ||
1958 | /* | |
1959 | * LQI Manager Current State | |
1960 | */ | |
1961 | register LQISTATE { | |
1962 | address 0x04E | |
1963 | access_mode RO | |
1964 | modes M_CFG | |
1965 | } | |
1966 | ||
1967 | /* | |
1968 | * SCSI Offset Count | |
1969 | */ | |
1970 | register SOFFCNT { | |
1971 | address 0x04F | |
1972 | access_mode RO | |
1973 | modes M_DFF0, M_DFF1, M_SCSI | |
1974 | } | |
1975 | ||
1976 | /* | |
1977 | * LQO Manager Current State | |
1978 | */ | |
1979 | register LQOSTATE { | |
1980 | address 0x04F | |
1981 | access_mode RO | |
1982 | modes M_CFG | |
1983 | } | |
1984 | ||
1985 | /* | |
1986 | * LQI Manager Status | |
1987 | */ | |
1988 | register LQISTAT0 { | |
1989 | address 0x050 | |
1990 | access_mode RO | |
1991 | modes M_DFF0, M_DFF1, M_SCSI | |
1992 | field LQIATNQAS 0x20 | |
1993 | field LQICRCT1 0x10 | |
1994 | field LQICRCT2 0x08 | |
1995 | field LQIBADLQT 0x04 | |
1996 | field LQIATNLQ 0x02 | |
1997 | field LQIATNCMD 0x01 | |
1998 | } | |
1999 | ||
2000 | /* | |
2001 | * Clear LQI Interrupts 0 | |
2002 | */ | |
2003 | register CLRLQIINT0 { | |
2004 | address 0x050 | |
2005 | access_mode WO | |
2006 | modes M_DFF0, M_DFF1, M_SCSI | |
2007 | field CLRLQIATNQAS 0x20 | |
2008 | field CLRLQICRCT1 0x10 | |
2009 | field CLRLQICRCT2 0x08 | |
2010 | field CLRLQIBADLQT 0x04 | |
2011 | field CLRLQIATNLQ 0x02 | |
2012 | field CLRLQIATNCMD 0x01 | |
2013 | } | |
2014 | ||
2015 | /* | |
2016 | * LQI Manager Interrupt Mode 0 | |
2017 | */ | |
2018 | register LQIMODE0 { | |
2019 | address 0x050 | |
2020 | access_mode RW | |
2021 | modes M_CFG | |
2022 | field ENLQIATNQASK 0x20 | |
2023 | field ENLQICRCT1 0x10 | |
2024 | field ENLQICRCT2 0x08 | |
2025 | field ENLQIBADLQT 0x04 | |
2026 | field ENLQIATNLQ 0x02 | |
2027 | field ENLQIATNCMD 0x01 | |
2028 | } | |
2029 | ||
2030 | /* | |
2031 | * LQI Manager Status 1 | |
2032 | */ | |
2033 | register LQISTAT1 { | |
2034 | address 0x051 | |
2035 | access_mode RO | |
2036 | modes M_DFF0, M_DFF1, M_SCSI | |
2037 | field LQIPHASE_LQ 0x80 | |
2038 | field LQIPHASE_NLQ 0x40 | |
2039 | field LQIABORT 0x20 | |
2040 | field LQICRCI_LQ 0x10 | |
2041 | field LQICRCI_NLQ 0x08 | |
2042 | field LQIBADLQI 0x04 | |
2043 | field LQIOVERI_LQ 0x02 | |
2044 | field LQIOVERI_NLQ 0x01 | |
2045 | } | |
2046 | ||
2047 | /* | |
2048 | * Clear LQI Manager Interrupts1 | |
2049 | */ | |
2050 | register CLRLQIINT1 { | |
2051 | address 0x051 | |
2052 | access_mode WO | |
2053 | modes M_DFF0, M_DFF1, M_SCSI | |
2054 | field CLRLQIPHASE_LQ 0x80 | |
2055 | field CLRLQIPHASE_NLQ 0x40 | |
2056 | field CLRLIQABORT 0x20 | |
2057 | field CLRLQICRCI_LQ 0x10 | |
2058 | field CLRLQICRCI_NLQ 0x08 | |
2059 | field CLRLQIBADLQI 0x04 | |
2060 | field CLRLQIOVERI_LQ 0x02 | |
2061 | field CLRLQIOVERI_NLQ 0x01 | |
2062 | } | |
2063 | ||
2064 | /* | |
2065 | * LQI Manager Interrupt Mode 1 | |
2066 | */ | |
2067 | register LQIMODE1 { | |
2068 | address 0x051 | |
2069 | access_mode RW | |
2070 | modes M_CFG | |
2071 | field ENLQIPHASE_LQ 0x80 /* LQIPHASE1 */ | |
2072 | field ENLQIPHASE_NLQ 0x40 /* LQIPHASE2 */ | |
2073 | field ENLIQABORT 0x20 | |
2074 | field ENLQICRCI_LQ 0x10 /* LQICRCI1 */ | |
2075 | field ENLQICRCI_NLQ 0x08 /* LQICRCI2 */ | |
2076 | field ENLQIBADLQI 0x04 | |
2077 | field ENLQIOVERI_LQ 0x02 /* LQIOVERI1 */ | |
2078 | field ENLQIOVERI_NLQ 0x01 /* LQIOVERI2 */ | |
2079 | } | |
2080 | ||
2081 | /* | |
2082 | * LQI Manager Status 2 | |
2083 | */ | |
2084 | register LQISTAT2 { | |
2085 | address 0x052 | |
2086 | access_mode RO | |
2087 | modes M_DFF0, M_DFF1, M_SCSI | |
2088 | field PACKETIZED 0x80 | |
2089 | field LQIPHASE_OUTPKT 0x40 | |
2090 | field LQIWORKONLQ 0x20 | |
2091 | field LQIWAITFIFO 0x10 | |
2092 | field LQISTOPPKT 0x08 | |
2093 | field LQISTOPLQ 0x04 | |
2094 | field LQISTOPCMD 0x02 | |
2095 | field LQIGSAVAIL 0x01 | |
2096 | } | |
2097 | ||
2098 | /* | |
2099 | * SCSI Status 3 | |
2100 | */ | |
2101 | register SSTAT3 { | |
2102 | address 0x053 | |
2103 | access_mode RO | |
2104 | modes M_DFF0, M_DFF1, M_SCSI | |
2105 | field NTRAMPERR 0x02 | |
2106 | field OSRAMPERR 0x01 | |
2107 | } | |
2108 | ||
2109 | /* | |
2110 | * Clear SCSI Status 3 | |
2111 | */ | |
2112 | register CLRSINT3 { | |
2113 | address 0x053 | |
2114 | access_mode WO | |
2115 | modes M_DFF0, M_DFF1, M_SCSI | |
2116 | field CLRNTRAMPERR 0x02 | |
2117 | field CLROSRAMPERR 0x01 | |
2118 | } | |
2119 | ||
2120 | /* | |
2121 | * SCSI Interrupt Mode 3 | |
2122 | */ | |
2123 | register SIMODE3 { | |
2124 | address 0x053 | |
2125 | access_mode RW | |
2126 | modes M_CFG | |
2127 | field ENNTRAMPERR 0x02 | |
2128 | field ENOSRAMPERR 0x01 | |
2129 | } | |
2130 | ||
2131 | /* | |
2132 | * LQO Manager Status 0 | |
2133 | */ | |
2134 | register LQOSTAT0 { | |
2135 | address 0x054 | |
2136 | access_mode RO | |
2137 | modes M_DFF0, M_DFF1, M_SCSI | |
2138 | field LQOTARGSCBPERR 0x10 | |
2139 | field LQOSTOPT2 0x08 | |
2140 | field LQOATNLQ 0x04 | |
2141 | field LQOATNPKT 0x02 | |
2142 | field LQOTCRC 0x01 | |
2143 | } | |
2144 | ||
2145 | /* | |
2146 | * Clear LQO Manager interrupt 0 | |
2147 | */ | |
2148 | register CLRLQOINT0 { | |
2149 | address 0x054 | |
2150 | access_mode WO | |
2151 | modes M_DFF0, M_DFF1, M_SCSI | |
2152 | field CLRLQOTARGSCBPERR 0x10 | |
2153 | field CLRLQOSTOPT2 0x08 | |
2154 | field CLRLQOATNLQ 0x04 | |
2155 | field CLRLQOATNPKT 0x02 | |
2156 | field CLRLQOTCRC 0x01 | |
2157 | } | |
2158 | ||
2159 | /* | |
2160 | * LQO Manager Interrupt Mode 0 | |
2161 | */ | |
2162 | register LQOMODE0 { | |
2163 | address 0x054 | |
2164 | access_mode RW | |
2165 | modes M_CFG | |
2166 | field ENLQOTARGSCBPERR 0x10 | |
2167 | field ENLQOSTOPT2 0x08 | |
2168 | field ENLQOATNLQ 0x04 | |
2169 | field ENLQOATNPKT 0x02 | |
2170 | field ENLQOTCRC 0x01 | |
2171 | } | |
2172 | ||
2173 | /* | |
2174 | * LQO Manager Status 1 | |
2175 | */ | |
2176 | register LQOSTAT1 { | |
2177 | address 0x055 | |
2178 | access_mode RO | |
2179 | modes M_DFF0, M_DFF1, M_SCSI | |
2180 | field LQOINITSCBPERR 0x10 | |
2181 | field LQOSTOPI2 0x08 | |
2182 | field LQOBADQAS 0x04 | |
2183 | field LQOBUSFREE 0x02 | |
2184 | field LQOPHACHGINPKT 0x01 | |
2185 | } | |
2186 | ||
2187 | /* | |
2188 | * Clear LOQ Interrupt 1 | |
2189 | */ | |
2190 | register CLRLQOINT1 { | |
2191 | address 0x055 | |
2192 | access_mode WO | |
2193 | modes M_DFF0, M_DFF1, M_SCSI | |
2194 | field CLRLQOINITSCBPERR 0x10 | |
2195 | field CLRLQOSTOPI2 0x08 | |
2196 | field CLRLQOBADQAS 0x04 | |
2197 | field CLRLQOBUSFREE 0x02 | |
2198 | field CLRLQOPHACHGINPKT 0x01 | |
2199 | } | |
2200 | ||
2201 | /* | |
2202 | * LQO Manager Interrupt Mode 1 | |
2203 | */ | |
2204 | register LQOMODE1 { | |
2205 | address 0x055 | |
2206 | access_mode RW | |
2207 | modes M_CFG | |
2208 | field ENLQOINITSCBPERR 0x10 | |
2209 | field ENLQOSTOPI2 0x08 | |
2210 | field ENLQOBADQAS 0x04 | |
2211 | field ENLQOBUSFREE 0x02 | |
2212 | field ENLQOPHACHGINPKT 0x01 | |
2213 | } | |
2214 | ||
2215 | /* | |
2216 | * LQO Manager Status 2 | |
2217 | */ | |
2218 | register LQOSTAT2 { | |
2219 | address 0x056 | |
2220 | access_mode RO | |
2221 | modes M_DFF0, M_DFF1, M_SCSI | |
2222 | field LQOPKT 0xE0 | |
2223 | field LQOWAITFIFO 0x10 | |
2224 | field LQOPHACHGOUTPKT 0x02 /* outside of packet boundaries. */ | |
2225 | field LQOSTOP0 0x01 /* Stopped after sending all packets */ | |
2226 | } | |
2227 | ||
2228 | /* | |
2229 | * Output Synchronizer Space Count | |
2230 | */ | |
2231 | register OS_SPACE_CNT { | |
2232 | address 0x056 | |
2233 | access_mode RO | |
2234 | modes M_CFG | |
2235 | } | |
2236 | ||
2237 | /* | |
2238 | * SCSI Interrupt Mode 1 | |
2239 | * Setting any bit will enable the corresponding function | |
2240 | * in SIMODE1 to interrupt via the IRQ pin. | |
2241 | */ | |
2242 | register SIMODE1 { | |
2243 | address 0x057 | |
2244 | access_mode RW | |
2245 | modes M_DFF0, M_DFF1, M_SCSI | |
2246 | field ENSELTIMO 0x80 | |
2247 | field ENATNTARG 0x40 | |
2248 | field ENSCSIRST 0x20 | |
2249 | field ENPHASEMIS 0x10 | |
2250 | field ENBUSFREE 0x08 | |
2251 | field ENSCSIPERR 0x04 | |
2252 | field ENSTRB2FAST 0x02 | |
2253 | field ENREQINIT 0x01 | |
2254 | } | |
2255 | ||
2256 | /* | |
2257 | * Good Status FIFO | |
2258 | */ | |
2259 | register GSFIFO { | |
2260 | address 0x058 | |
2261 | access_mode RO | |
2262 | size 2 | |
2263 | modes M_DFF0, M_DFF1, M_SCSI | |
2264 | } | |
2265 | ||
2266 | /* | |
2267 | * Data FIFO SCSI Transfer Control | |
2268 | */ | |
2269 | register DFFSXFRCTL { | |
2270 | address 0x05A | |
2271 | access_mode RW | |
2272 | modes M_DFF0, M_DFF1 | |
2273 | field DFFBITBUCKET 0x08 | |
2274 | field CLRSHCNT 0x04 | |
2275 | field CLRCHN 0x02 | |
2276 | field RSTCHN 0x01 | |
2277 | } | |
2278 | ||
2279 | /* | |
2280 | * Next SCSI Control Block | |
2281 | */ | |
2282 | register NEXTSCB { | |
2283 | address 0x05A | |
2284 | access_mode RW | |
2285 | size 2 | |
2286 | modes M_SCSI | |
2287 | } | |
2288 | ||
2289 | /* Rev B only. */ | |
2290 | register LQOSCSCTL { | |
2291 | address 0x05A | |
2292 | access_mode RW | |
2293 | size 1 | |
2294 | modes M_CFG | |
2295 | field LQOH2A_VERSION 0x80 | |
2296 | field LQONOCHKOVER 0x01 | |
2297 | } | |
2298 | ||
2299 | /* | |
2300 | * SEQ Interrupts | |
2301 | */ | |
2302 | register SEQINTSRC { | |
2303 | address 0x05B | |
2304 | access_mode RO | |
2305 | modes M_DFF0, M_DFF1 | |
2306 | field CTXTDONE 0x40 | |
2307 | field SAVEPTRS 0x20 | |
2308 | field CFG4DATA 0x10 | |
2309 | field CFG4ISTAT 0x08 | |
2310 | field CFG4TSTAT 0x04 | |
2311 | field CFG4ICMD 0x02 | |
2312 | field CFG4TCMD 0x01 | |
2313 | } | |
2314 | ||
2315 | /* | |
2316 | * Clear Arp Interrupts | |
2317 | */ | |
2318 | register CLRSEQINTSRC { | |
2319 | address 0x05B | |
2320 | access_mode WO | |
2321 | modes M_DFF0, M_DFF1 | |
2322 | field CLRCTXTDONE 0x40 | |
2323 | field CLRSAVEPTRS 0x20 | |
2324 | field CLRCFG4DATA 0x10 | |
2325 | field CLRCFG4ISTAT 0x08 | |
2326 | field CLRCFG4TSTAT 0x04 | |
2327 | field CLRCFG4ICMD 0x02 | |
2328 | field CLRCFG4TCMD 0x01 | |
2329 | } | |
2330 | ||
2331 | /* | |
2332 | * SEQ Interrupt Enabled (Shared) | |
2333 | */ | |
2334 | register SEQIMODE { | |
2335 | address 0x05C | |
2336 | access_mode RW | |
2337 | modes M_DFF0, M_DFF1 | |
2338 | field ENCTXTDONE 0x40 | |
2339 | field ENSAVEPTRS 0x20 | |
2340 | field ENCFG4DATA 0x10 | |
2341 | field ENCFG4ISTAT 0x08 | |
2342 | field ENCFG4TSTAT 0x04 | |
2343 | field ENCFG4ICMD 0x02 | |
2344 | field ENCFG4TCMD 0x01 | |
2345 | } | |
2346 | ||
2347 | /* | |
2348 | * Current SCSI Control Block | |
2349 | */ | |
2350 | register CURRSCB { | |
2351 | address 0x05C | |
2352 | access_mode RW | |
2353 | size 2 | |
2354 | modes M_SCSI | |
2355 | } | |
2356 | ||
2357 | /* | |
2358 | * Data FIFO Status | |
2359 | */ | |
2360 | register MDFFSTAT { | |
2361 | address 0x05D | |
2362 | access_mode RO | |
2363 | modes M_DFF0, M_DFF1 | |
2364 | field SHCNTNEGATIVE 0x40 /* Rev B or higher */ | |
2365 | field SHCNTMINUS1 0x20 /* Rev B or higher */ | |
2366 | field LASTSDONE 0x10 | |
2367 | field SHVALID 0x08 | |
2368 | field DLZERO 0x04 /* FIFO data ends on packet boundary. */ | |
2369 | field DATAINFIFO 0x02 | |
2370 | field FIFOFREE 0x01 | |
2371 | } | |
2372 | ||
2373 | /* | |
2374 | * CRC Control | |
2375 | */ | |
2376 | register CRCCONTROL { | |
2377 | address 0x05d | |
2378 | access_mode RW | |
2379 | modes M_CFG | |
2380 | field CRCVALCHKEN 0x40 | |
2381 | } | |
2382 | ||
2383 | /* | |
2384 | * SCSI Test Control | |
2385 | */ | |
2386 | register SCSITEST { | |
2387 | address 0x05E | |
2388 | access_mode RW | |
2389 | modes M_CFG | |
2390 | field CNTRTEST 0x08 | |
2391 | field SEL_TXPLL_DEBUG 0x04 | |
2392 | } | |
2393 | ||
2394 | /* | |
2395 | * Data FIFO Queue Tag | |
2396 | */ | |
2397 | register DFFTAG { | |
2398 | address 0x05E | |
2399 | access_mode RW | |
2400 | size 2 | |
2401 | modes M_DFF0, M_DFF1 | |
2402 | } | |
2403 | ||
2404 | /* | |
2405 | * Last SCSI Control Block | |
2406 | */ | |
2407 | register LASTSCB { | |
2408 | address 0x05E | |
2409 | access_mode RW | |
2410 | size 2 | |
2411 | modes M_SCSI | |
2412 | } | |
2413 | ||
2414 | /* | |
2415 | * SCSI I/O Cell Power-down Control | |
2416 | */ | |
2417 | register IOPDNCTL { | |
2418 | address 0x05F | |
2419 | access_mode RW | |
2420 | modes M_CFG | |
2421 | field DISABLE_OE 0x80 | |
2422 | field PDN_IDIST 0x04 | |
2423 | field PDN_DIFFSENSE 0x01 | |
2424 | } | |
2425 | ||
2426 | /* | |
2427 | * Shaddow Host Address. | |
2428 | */ | |
2429 | register SHADDR { | |
2430 | address 0x060 | |
2431 | access_mode RO | |
2432 | size 8 | |
2433 | modes M_DFF0, M_DFF1 | |
2434 | } | |
2435 | ||
2436 | /* | |
2437 | * Data Group CRC Interval. | |
2438 | */ | |
2439 | register DGRPCRCI { | |
2440 | address 0x060 | |
2441 | access_mode RW | |
2442 | size 2 | |
2443 | modes M_CFG | |
2444 | } | |
2445 | ||
2446 | /* | |
2447 | * Data Transfer Negotiation Address | |
2448 | */ | |
2449 | register NEGOADDR { | |
2450 | address 0x060 | |
2451 | access_mode RW | |
2452 | modes M_SCSI | |
2453 | } | |
2454 | ||
2455 | /* | |
2456 | * Data Transfer Negotiation Data - Period Byte | |
2457 | */ | |
2458 | register NEGPERIOD { | |
2459 | address 0x061 | |
2460 | access_mode RW | |
2461 | modes M_SCSI | |
2462 | } | |
2463 | ||
2464 | /* | |
2465 | * Packetized CRC Interval | |
2466 | */ | |
2467 | register PACKCRCI { | |
2468 | address 0x062 | |
2469 | access_mode RW | |
2470 | size 2 | |
2471 | modes M_CFG | |
2472 | } | |
2473 | ||
2474 | /* | |
2475 | * Data Transfer Negotiation Data - Offset Byte | |
2476 | */ | |
2477 | register NEGOFFSET { | |
2478 | address 0x062 | |
2479 | access_mode RW | |
2480 | modes M_SCSI | |
2481 | } | |
2482 | ||
2483 | /* | |
2484 | * Data Transfer Negotiation Data - PPR Options | |
2485 | */ | |
2486 | register NEGPPROPTS { | |
2487 | address 0x063 | |
2488 | access_mode RW | |
2489 | modes M_SCSI | |
2490 | field PPROPT_PACE 0x08 | |
2491 | field PPROPT_QAS 0x04 | |
2492 | field PPROPT_DT 0x02 | |
2493 | field PPROPT_IUT 0x01 | |
2494 | } | |
2495 | ||
2496 | /* | |
2497 | * Data Transfer Negotiation Data - Connection Options | |
2498 | */ | |
2499 | register NEGCONOPTS { | |
2500 | address 0x064 | |
2501 | access_mode RW | |
2502 | modes M_SCSI | |
2503 | field ENSNAPSHOT 0x40 | |
2504 | field RTI_WRTDIS 0x20 | |
2505 | field RTI_OVRDTRN 0x10 | |
2506 | field ENSLOWCRC 0x08 | |
2507 | field ENAUTOATNI 0x04 | |
2508 | field ENAUTOATNO 0x02 | |
2509 | field WIDEXFER 0x01 | |
2510 | } | |
2511 | ||
2512 | /* | |
2513 | * Negotiation Table Annex Column Index. | |
2514 | */ | |
2515 | register ANNEXCOL { | |
2516 | address 0x065 | |
2517 | access_mode RW | |
2518 | modes M_SCSI | |
2519 | } | |
2520 | ||
2521 | register SCSCHKN { | |
2522 | address 0x066 | |
2523 | access_mode RW | |
2524 | modes M_CFG | |
2525 | field STSELSKIDDIS 0x40 | |
2526 | field CURRFIFODEF 0x20 | |
2527 | field WIDERESEN 0x10 | |
2528 | field SDONEMSKDIS 0x08 | |
2529 | field DFFACTCLR 0x04 | |
2530 | field SHVALIDSTDIS 0x02 | |
2531 | field LSTSGCLRDIS 0x01 | |
2532 | } | |
2533 | ||
2534 | const AHD_ANNEXCOL_PER_DEV0 4 | |
2535 | const AHD_NUM_PER_DEV_ANNEXCOLS 4 | |
2536 | const AHD_ANNEXCOL_PRECOMP_SLEW 4 | |
2537 | const AHD_PRECOMP_MASK 0x07 | |
2538 | const AHD_PRECOMP_SHIFT 0 | |
2539 | const AHD_PRECOMP_CUTBACK_17 0x04 | |
2540 | const AHD_PRECOMP_CUTBACK_29 0x06 | |
2541 | const AHD_PRECOMP_CUTBACK_37 0x07 | |
2542 | const AHD_SLEWRATE_MASK 0x78 | |
2543 | const AHD_SLEWRATE_SHIFT 3 | |
2544 | /* | |
2545 | * Rev A has only a single bit (high bit of field) of slew adjustment. | |
2546 | * Rev B has 4 bits. The current default happens to be the same for both. | |
2547 | */ | |
2548 | const AHD_SLEWRATE_DEF_REVA 0x08 | |
2549 | const AHD_SLEWRATE_DEF_REVB 0x08 | |
2550 | ||
2551 | /* Rev A does not have any amplitude setting. */ | |
2552 | const AHD_ANNEXCOL_AMPLITUDE 6 | |
2553 | const AHD_AMPLITUDE_MASK 0x7 | |
2554 | const AHD_AMPLITUDE_SHIFT 0 | |
2555 | const AHD_AMPLITUDE_DEF 0x7 | |
2556 | ||
2557 | /* | |
2558 | * Negotiation Table Annex Data Port. | |
2559 | */ | |
2560 | register ANNEXDAT { | |
2561 | address 0x066 | |
2562 | access_mode RW | |
2563 | modes M_SCSI | |
2564 | } | |
2565 | ||
2566 | /* | |
2567 | * Initiator's Own Id. | |
2568 | * The SCSI ID to use for Selection Out and seen during a reselection.. | |
2569 | */ | |
2570 | register IOWNID { | |
2571 | address 0x067 | |
2572 | access_mode RW | |
2573 | modes M_SCSI | |
2574 | } | |
2575 | ||
2576 | /* | |
2577 | * 960MHz Phase-Locked Loop Control 0 | |
2578 | */ | |
2579 | register PLL960CTL0 { | |
2580 | address 0x068 | |
2581 | access_mode RW | |
2582 | modes M_CFG | |
2583 | field PLL_VCOSEL 0x80 | |
2584 | field PLL_PWDN 0x40 | |
2585 | field PLL_NS 0x30 | |
2586 | field PLL_ENLUD 0x08 | |
2587 | field PLL_ENLPF 0x04 | |
2588 | field PLL_DLPF 0x02 | |
2589 | field PLL_ENFBM 0x01 | |
2590 | } | |
2591 | ||
2592 | /* | |
2593 | * Target Own Id | |
2594 | */ | |
2595 | register TOWNID { | |
2596 | address 0x069 | |
2597 | access_mode RW | |
2598 | modes M_SCSI | |
2599 | } | |
2600 | ||
2601 | /* | |
2602 | * 960MHz Phase-Locked Loop Control 1 | |
2603 | */ | |
2604 | register PLL960CTL1 { | |
2605 | address 0x069 | |
2606 | access_mode RW | |
2607 | modes M_CFG | |
2608 | field PLL_CNTEN 0x80 | |
2609 | field PLL_CNTCLR 0x40 | |
2610 | field PLL_RST 0x01 | |
2611 | } | |
2612 | ||
2613 | /* | |
2614 | * Expander Signature | |
2615 | */ | |
2616 | register XSIG { | |
2617 | address 0x06A | |
2618 | access_mode RW | |
2619 | modes M_SCSI | |
2620 | } | |
2621 | ||
2622 | /* | |
2623 | * Shadow Byte Count | |
2624 | */ | |
2625 | register SHCNT { | |
2626 | address 0x068 | |
2627 | access_mode RW | |
2628 | size 3 | |
2629 | modes M_DFF0, M_DFF1 | |
2630 | } | |
2631 | ||
2632 | /* | |
2633 | * Selection Out ID | |
2634 | */ | |
2635 | register SELOID { | |
2636 | address 0x06B | |
2637 | access_mode RW | |
2638 | modes M_SCSI | |
2639 | } | |
2640 | ||
2641 | /* | |
2642 | * 960-MHz Phase-Locked Loop Test Count | |
2643 | */ | |
2644 | register PLL960CNT0 { | |
2645 | address 0x06A | |
2646 | access_mode RO | |
2647 | size 2 | |
2648 | modes M_CFG | |
2649 | } | |
2650 | ||
2651 | /* | |
2652 | * 400-MHz Phase-Locked Loop Control 0 | |
2653 | */ | |
2654 | register PLL400CTL0 { | |
2655 | address 0x06C | |
2656 | access_mode RW | |
2657 | modes M_CFG | |
2658 | field PLL_VCOSEL 0x80 | |
2659 | field PLL_PWDN 0x40 | |
2660 | field PLL_NS 0x30 | |
2661 | field PLL_ENLUD 0x08 | |
2662 | field PLL_ENLPF 0x04 | |
2663 | field PLL_DLPF 0x02 | |
2664 | field PLL_ENFBM 0x01 | |
2665 | } | |
2666 | ||
2667 | /* | |
2668 | * Arbitration Fairness | |
2669 | */ | |
2670 | register FAIRNESS { | |
2671 | address 0x06C | |
2672 | access_mode RW | |
2673 | size 2 | |
2674 | modes M_SCSI | |
2675 | } | |
2676 | ||
2677 | /* | |
2678 | * 400-MHz Phase-Locked Loop Control 1 | |
2679 | */ | |
2680 | register PLL400CTL1 { | |
2681 | address 0x06D | |
2682 | access_mode RW | |
2683 | modes M_CFG | |
2684 | field PLL_CNTEN 0x80 | |
2685 | field PLL_CNTCLR 0x40 | |
2686 | field PLL_RST 0x01 | |
2687 | } | |
2688 | ||
2689 | /* | |
2690 | * Arbitration Unfairness | |
2691 | */ | |
2692 | register UNFAIRNESS { | |
2693 | address 0x06E | |
2694 | access_mode RW | |
2695 | size 2 | |
2696 | modes M_SCSI | |
2697 | } | |
2698 | ||
2699 | /* | |
2700 | * 400-MHz Phase-Locked Loop Test Count | |
2701 | */ | |
2702 | register PLL400CNT0 { | |
2703 | address 0x06E | |
2704 | access_mode RO | |
2705 | size 2 | |
2706 | modes M_CFG | |
2707 | } | |
2708 | ||
2709 | /* | |
2710 | * SCB Page Pointer | |
2711 | */ | |
2712 | register SCBPTR { | |
2713 | address 0x0A8 | |
2714 | access_mode RW | |
2715 | size 2 | |
2716 | modes M_DFF0, M_DFF1, M_CCHAN, M_SCSI | |
2717 | } | |
2718 | ||
2719 | /* | |
2720 | * CMC SCB Array Count | |
2721 | * Number of bytes to transfer between CMC SCB memory and SCBRAM. | |
2722 | * Transfers must be 8byte aligned and sized. | |
2723 | */ | |
2724 | register CCSCBACNT { | |
2725 | address 0x0AB | |
2726 | access_mode RW | |
2727 | modes M_CCHAN | |
2728 | } | |
2729 | ||
2730 | /* | |
2731 | * SCB Autopointer | |
2732 | * SCB-Next Address Snooping logic. When an SCB is transferred to | |
2733 | * the card, the next SCB address to be used by the CMC array can | |
2734 | * be autoloaded from that transfer. | |
2735 | */ | |
2736 | register SCBAUTOPTR { | |
2737 | address 0x0AB | |
2738 | access_mode RW | |
2739 | modes M_CFG | |
2740 | field AUSCBPTR_EN 0x80 | |
2741 | field SCBPTR_ADDR 0x38 | |
2742 | field SCBPTR_OFF 0x07 | |
2743 | } | |
2744 | ||
2745 | /* | |
2746 | * CMC SG Ram Address Pointer | |
2747 | */ | |
2748 | register CCSGADDR { | |
2749 | address 0x0AC | |
2750 | access_mode RW | |
2751 | modes M_DFF0, M_DFF1 | |
2752 | } | |
2753 | ||
2754 | /* | |
2755 | * CMC SCB RAM Address Pointer | |
2756 | */ | |
2757 | register CCSCBADDR { | |
2758 | address 0x0AC | |
2759 | access_mode RW | |
2760 | modes M_CCHAN | |
2761 | } | |
2762 | ||
2763 | /* | |
2764 | * CMC SCB Ram Back-up Address Pointer | |
2765 | * Indicates the true stop location of transfers halted prior | |
2766 | * to SCBHCNT going to 0. | |
2767 | */ | |
2768 | register CCSCBADR_BK { | |
2769 | address 0x0AC | |
2770 | access_mode RO | |
2771 | modes M_CFG | |
2772 | } | |
2773 | ||
2774 | /* | |
2775 | * CMC SG Control | |
2776 | */ | |
2777 | register CCSGCTL { | |
2778 | address 0x0AD | |
2779 | access_mode RW | |
2780 | modes M_DFF0, M_DFF1 | |
2781 | field CCSGDONE 0x80 | |
2782 | field SG_CACHE_AVAIL 0x10 | |
2783 | field CCSGENACK 0x08 | |
2784 | mask CCSGEN 0x0C | |
2785 | field SG_FETCH_REQ 0x02 | |
2786 | field CCSGRESET 0x01 | |
2787 | } | |
2788 | ||
2789 | /* | |
2790 | * CMD SCB Control | |
2791 | */ | |
2792 | register CCSCBCTL { | |
2793 | address 0x0AD | |
2794 | access_mode RW | |
2795 | modes M_CCHAN | |
2796 | field CCSCBDONE 0x80 | |
2797 | field ARRDONE 0x40 | |
2798 | field CCARREN 0x10 | |
2799 | field CCSCBEN 0x08 | |
2800 | field CCSCBDIR 0x04 | |
2801 | field CCSCBRESET 0x01 | |
2802 | } | |
2803 | ||
2804 | /* | |
2805 | * CMC Ram BIST | |
2806 | */ | |
2807 | register CMC_RAMBIST { | |
2808 | address 0x0AD | |
2809 | access_mode RW | |
2810 | modes M_CFG | |
2811 | field SG_ELEMENT_SIZE 0x80 | |
2812 | field SCBRAMBIST_FAIL 0x40 | |
2813 | field SG_BIST_FAIL 0x20 | |
2814 | field SG_BIST_EN 0x10 | |
2815 | field CMC_BUFFER_BIST_FAIL 0x02 | |
2816 | field CMC_BUFFER_BIST_EN 0x01 | |
2817 | } | |
2818 | ||
2819 | /* | |
2820 | * CMC SG RAM Data Port | |
2821 | */ | |
2822 | register CCSGRAM { | |
2823 | address 0x0B0 | |
2824 | access_mode RW | |
2825 | modes M_DFF0, M_DFF1 | |
2826 | } | |
2827 | ||
2828 | /* | |
2829 | * CMC SCB RAM Data Port | |
2830 | */ | |
2831 | register CCSCBRAM { | |
2832 | address 0x0B0 | |
2833 | access_mode RW | |
2834 | modes M_CCHAN | |
2835 | } | |
2836 | ||
2837 | /* | |
2838 | * Flex DMA Address. | |
2839 | */ | |
2840 | register FLEXADR { | |
2841 | address 0x0B0 | |
2842 | access_mode RW | |
2843 | size 3 | |
2844 | modes M_SCSI | |
2845 | } | |
2846 | ||
2847 | /* | |
2848 | * Flex DMA Byte Count | |
2849 | */ | |
2850 | register FLEXCNT { | |
2851 | address 0x0B3 | |
2852 | access_mode RW | |
2853 | size 2 | |
2854 | modes M_SCSI | |
2855 | } | |
2856 | ||
2857 | /* | |
2858 | * Flex DMA Status | |
2859 | */ | |
2860 | register FLEXDMASTAT { | |
2861 | address 0x0B5 | |
2862 | access_mode RW | |
2863 | modes M_SCSI | |
2864 | field FLEXDMAERR 0x02 | |
2865 | field FLEXDMADONE 0x01 | |
2866 | } | |
2867 | ||
2868 | /* | |
2869 | * Flex DMA Data Port | |
2870 | */ | |
2871 | register FLEXDATA { | |
2872 | address 0x0B6 | |
2873 | access_mode RW | |
2874 | modes M_SCSI | |
2875 | } | |
2876 | ||
2877 | /* | |
2878 | * Board Data | |
2879 | */ | |
2880 | register BRDDAT { | |
2881 | address 0x0B8 | |
2882 | access_mode RW | |
2883 | modes M_SCSI | |
2884 | } | |
2885 | ||
2886 | /* | |
2887 | * Board Control | |
2888 | */ | |
2889 | register BRDCTL { | |
2890 | address 0x0B9 | |
2891 | access_mode RW | |
2892 | modes M_SCSI | |
2893 | field FLXARBACK 0x80 | |
2894 | field FLXARBREQ 0x40 | |
2895 | field BRDADDR 0x38 | |
2896 | field BRDEN 0x04 | |
2897 | field BRDRW 0x02 | |
2898 | field BRDSTB 0x01 | |
2899 | } | |
2900 | ||
2901 | /* | |
2902 | * Serial EEPROM Address | |
2903 | */ | |
2904 | register SEEADR { | |
2905 | address 0x0BA | |
2906 | access_mode RW | |
2907 | modes M_SCSI | |
2908 | } | |
2909 | ||
2910 | /* | |
2911 | * Serial EEPROM Data | |
2912 | */ | |
2913 | register SEEDAT { | |
2914 | address 0x0BC | |
2915 | access_mode RW | |
2916 | size 2 | |
2917 | modes M_SCSI | |
2918 | } | |
2919 | ||
2920 | /* | |
2921 | * Serial EEPROM Status | |
2922 | */ | |
2923 | register SEESTAT { | |
2924 | address 0x0BE | |
2925 | access_mode RO | |
2926 | modes M_SCSI | |
2927 | field INIT_DONE 0x80 | |
2928 | field SEEOPCODE 0x70 | |
2929 | field LDALTID_L 0x08 | |
2930 | field SEEARBACK 0x04 | |
2931 | field SEEBUSY 0x02 | |
2932 | field SEESTART 0x01 | |
2933 | } | |
2934 | ||
2935 | /* | |
2936 | * Serial EEPROM Control | |
2937 | */ | |
2938 | register SEECTL { | |
2939 | address 0x0BE | |
2940 | access_mode RW | |
2941 | modes M_SCSI | |
2942 | field SEEOPCODE 0x70 { | |
2943 | SEEOP_ERASE 0x70, | |
2944 | SEEOP_READ 0x60, | |
2945 | SEEOP_WRITE 0x50, | |
2946 | /* | |
2947 | * The following four commands use special | |
2948 | * addresses for differentiation. | |
2949 | */ | |
2950 | SEEOP_ERAL 0x40 | |
2951 | } | |
2952 | mask SEEOP_EWEN 0x40 | |
2953 | mask SEEOP_WALL 0x40 | |
2954 | mask SEEOP_EWDS 0x40 | |
2955 | field SEERST 0x02 | |
2956 | field SEESTART 0x01 | |
2957 | } | |
2958 | ||
2959 | const SEEOP_ERAL_ADDR 0x80 | |
2960 | const SEEOP_EWEN_ADDR 0xC0 | |
2961 | const SEEOP_WRAL_ADDR 0x40 | |
2962 | const SEEOP_EWDS_ADDR 0x00 | |
2963 | ||
2964 | /* | |
2965 | * SCB Counter | |
2966 | */ | |
2967 | register SCBCNT { | |
2968 | address 0x0BF | |
2969 | access_mode RW | |
2970 | modes M_SCSI | |
2971 | } | |
2972 | ||
2973 | /* | |
2974 | * Data FIFO Write Address | |
2975 | * Pointer to the next QWD location to be written to the data FIFO. | |
2976 | */ | |
2977 | register DFWADDR { | |
2978 | address 0x0C0 | |
2979 | access_mode RW | |
2980 | size 2 | |
2981 | modes M_DFF0, M_DFF1 | |
2982 | } | |
2983 | ||
2984 | /* | |
2985 | * DSP Filter Control | |
2986 | */ | |
2987 | register DSPFLTRCTL { | |
2988 | address 0x0C0 | |
2989 | access_mode RW | |
2990 | modes M_CFG | |
2991 | field FLTRDISABLE 0x20 | |
2992 | field EDGESENSE 0x10 | |
2993 | field DSPFCNTSEL 0x0F | |
2994 | } | |
2995 | ||
2996 | /* | |
2997 | * DSP Data Channel Control | |
2998 | */ | |
2999 | register DSPDATACTL { | |
3000 | address 0x0C1 | |
3001 | access_mode RW | |
3002 | modes M_CFG | |
3003 | field BYPASSENAB 0x80 | |
3004 | field DESQDIS 0x10 | |
3005 | field RCVROFFSTDIS 0x04 | |
3006 | field XMITOFFSTDIS 0x02 | |
3007 | } | |
3008 | ||
3009 | /* | |
3010 | * Data FIFO Read Address | |
3011 | * Pointer to the next QWD location to be read from the data FIFO. | |
3012 | */ | |
3013 | register DFRADDR { | |
3014 | address 0x0C2 | |
3015 | access_mode RW | |
3016 | size 2 | |
3017 | modes M_DFF0, M_DFF1 | |
3018 | } | |
3019 | ||
3020 | /* | |
3021 | * DSP REQ Control | |
3022 | */ | |
3023 | register DSPREQCTL { | |
3024 | address 0x0C2 | |
3025 | access_mode RW | |
3026 | modes M_CFG | |
3027 | field MANREQCTL 0xC0 | |
3028 | field MANREQDLY 0x3F | |
3029 | } | |
3030 | ||
3031 | /* | |
3032 | * DSP ACK Control | |
3033 | */ | |
3034 | register DSPACKCTL { | |
3035 | address 0x0C3 | |
3036 | access_mode RW | |
3037 | modes M_CFG | |
3038 | field MANACKCTL 0xC0 | |
3039 | field MANACKDLY 0x3F | |
3040 | } | |
3041 | ||
3042 | /* | |
3043 | * Data FIFO Data | |
3044 | * Read/Write byte port into the data FIFO. The read and write | |
3045 | * FIFO pointers increment with each read and write respectively | |
3046 | * to this port. | |
3047 | */ | |
3048 | register DFDAT { | |
3049 | address 0x0C4 | |
3050 | access_mode RW | |
3051 | modes M_DFF0, M_DFF1 | |
3052 | } | |
3053 | ||
3054 | /* | |
3055 | * DSP Channel Select | |
3056 | */ | |
3057 | register DSPSELECT { | |
3058 | address 0x0C4 | |
3059 | access_mode RW | |
3060 | modes M_CFG | |
3061 | field AUTOINCEN 0x80 | |
3062 | field DSPSEL 0x1F | |
3063 | } | |
3064 | ||
3065 | const NUMDSPS 0x14 | |
3066 | ||
3067 | /* | |
3068 | * Write Bias Control | |
3069 | */ | |
3070 | register WRTBIASCTL { | |
3071 | address 0x0C5 | |
3072 | access_mode WO | |
3073 | modes M_CFG | |
3074 | field AUTOXBCDIS 0x80 | |
3075 | field XMITMANVAL 0x3F | |
3076 | } | |
3077 | ||
3078 | /* | |
3079 | * Currently the WRTBIASCTL is the same as the default. | |
3080 | */ | |
3081 | const WRTBIASCTL_HP_DEFAULT 0x0 | |
3082 | ||
3083 | /* | |
3084 | * Receiver Bias Control | |
3085 | */ | |
3086 | register RCVRBIOSCTL { | |
3087 | address 0x0C6 | |
3088 | access_mode WO | |
3089 | modes M_CFG | |
3090 | field AUTORBCDIS 0x80 | |
3091 | field RCVRMANVAL 0x3F | |
3092 | } | |
3093 | ||
3094 | /* | |
3095 | * Write Bias Calculator | |
3096 | */ | |
3097 | register WRTBIASCALC { | |
3098 | address 0x0C7 | |
3099 | access_mode RO | |
3100 | modes M_CFG | |
3101 | } | |
3102 | ||
3103 | /* | |
3104 | * Data FIFO Pointers | |
3105 | * Contains the byte offset from DFWADDR and DWRADDR to the current | |
3106 | * FIFO write/read locations. | |
3107 | */ | |
3108 | register DFPTRS { | |
3109 | address 0x0C8 | |
3110 | access_mode RW | |
3111 | modes M_DFF0, M_DFF1 | |
3112 | } | |
3113 | ||
3114 | /* | |
3115 | * Receiver Bias Calculator | |
3116 | */ | |
3117 | register RCVRBIASCALC { | |
3118 | address 0x0C8 | |
3119 | access_mode RO | |
3120 | modes M_CFG | |
3121 | } | |
3122 | ||
3123 | /* | |
3124 | * Data FIFO Backup Read Pointer | |
3125 | * Contains the data FIFO address to be restored if the last | |
3126 | * data accessed from the data FIFO was not transferred successfully. | |
3127 | */ | |
3128 | register DFBKPTR { | |
3129 | address 0x0C9 | |
3130 | access_mode RW | |
3131 | size 2 | |
3132 | modes M_DFF0, M_DFF1 | |
3133 | } | |
3134 | ||
3135 | /* | |
3136 | * Skew Calculator | |
3137 | */ | |
3138 | register SKEWCALC { | |
3139 | address 0x0C9 | |
3140 | access_mode RO | |
3141 | modes M_CFG | |
3142 | } | |
3143 | ||
3144 | /* | |
3145 | * Data FIFO Debug Control | |
3146 | */ | |
3147 | register DFDBCTL { | |
3148 | address 0x0CB | |
3149 | access_mode RW | |
3150 | modes M_DFF0, M_DFF1 | |
3151 | field DFF_CIO_WR_RDY 0x20 | |
3152 | field DFF_CIO_RD_RDY 0x10 | |
3153 | field DFF_DIR_ERR 0x08 | |
3154 | field DFF_RAMBIST_FAIL 0x04 | |
3155 | field DFF_RAMBIST_DONE 0x02 | |
3156 | field DFF_RAMBIST_EN 0x01 | |
3157 | } | |
3158 | ||
3159 | /* | |
3160 | * Data FIFO Space Count | |
3161 | * Number of FIFO locations that are free. | |
3162 | */ | |
3163 | register DFSCNT { | |
3164 | address 0x0CC | |
3165 | access_mode RO | |
3166 | size 2 | |
3167 | modes M_DFF0, M_DFF1 | |
3168 | } | |
3169 | ||
3170 | /* | |
3171 | * Data FIFO Byte Count | |
3172 | * Number of filled FIFO locations. | |
3173 | */ | |
3174 | register DFBCNT { | |
3175 | address 0x0CE | |
3176 | access_mode RO | |
3177 | size 2 | |
3178 | modes M_DFF0, M_DFF1 | |
3179 | } | |
3180 | ||
3181 | /* | |
3182 | * Sequencer Program Overlay Address. | |
3183 | * Low address must be written prior to high address. | |
3184 | */ | |
3185 | register OVLYADDR { | |
3186 | address 0x0D4 | |
3187 | modes M_SCSI | |
3188 | size 2 | |
3189 | access_mode RW | |
3190 | } | |
3191 | ||
3192 | /* | |
3193 | * Sequencer Control 0 | |
3194 | * Error detection mode, speed configuration, | |
3195 | * single step, breakpoints and program load. | |
3196 | */ | |
3197 | register SEQCTL0 { | |
3198 | address 0x0D6 | |
3199 | access_mode RW | |
3200 | field PERRORDIS 0x80 | |
3201 | field PAUSEDIS 0x40 | |
3202 | field FAILDIS 0x20 | |
3203 | field FASTMODE 0x10 | |
3204 | field BRKADRINTEN 0x08 | |
3205 | field STEP 0x04 | |
3206 | field SEQRESET 0x02 | |
3207 | field LOADRAM 0x01 | |
3208 | } | |
3209 | ||
3210 | /* | |
3211 | * Sequencer Control 1 | |
3212 | * Instruction RAM Diagnostics | |
3213 | */ | |
3214 | register SEQCTL1 { | |
3215 | address 0x0D7 | |
3216 | access_mode RW | |
3217 | field OVRLAY_DATA_CHK 0x08 | |
3218 | field RAMBIST_DONE 0x04 | |
3219 | field RAMBIST_FAIL 0x02 | |
3220 | field RAMBIST_EN 0x01 | |
3221 | } | |
3222 | ||
3223 | /* | |
3224 | * Sequencer Flags | |
3225 | * Zero and Carry state of the ALU. | |
3226 | */ | |
3227 | register FLAGS { | |
3228 | address 0x0D8 | |
3229 | access_mode RO | |
3230 | field ZERO 0x02 | |
3231 | field CARRY 0x01 | |
3232 | } | |
3233 | ||
3234 | /* | |
3235 | * Sequencer Interrupt Control | |
3236 | */ | |
3237 | register SEQINTCTL { | |
3238 | address 0x0D9 | |
3239 | access_mode RW | |
3240 | field INTVEC1DSL 0x80 | |
3241 | field INT1_CONTEXT 0x20 | |
3242 | field SCS_SEQ_INT1M1 0x10 | |
3243 | field SCS_SEQ_INT1M0 0x08 | |
3244 | field INTMASK2 0x04 | |
3245 | field INTMASK1 0x02 | |
3246 | field IRET 0x01 | |
3247 | } | |
3248 | ||
3249 | /* | |
3250 | * Sequencer RAM Data Port | |
3251 | * Single byte window into the Sequencer Instruction Ram area starting | |
3252 | * at the address specified by OVLYADDR. To write a full instruction word, | |
3253 | * simply write four bytes in succession. OVLYADDR will increment after the | |
3254 | * most significant instrution byte (the byte with the parity bit) is written. | |
3255 | */ | |
3256 | register SEQRAM { | |
3257 | address 0x0DA | |
3258 | access_mode RW | |
3259 | } | |
3260 | ||
3261 | /* | |
3262 | * Sequencer Program Counter | |
3263 | * Low byte must be written prior to high byte. | |
3264 | */ | |
3265 | register PRGMCNT { | |
3266 | address 0x0DE | |
3267 | access_mode RW | |
3268 | size 2 | |
3269 | } | |
3270 | ||
3271 | /* | |
3272 | * Accumulator | |
3273 | */ | |
3274 | register ACCUM { | |
3275 | address 0x0E0 | |
3276 | access_mode RW | |
3277 | accumulator | |
3278 | } | |
3279 | ||
3280 | /* | |
3281 | * Source Index Register | |
3282 | * Incrementing index for reads of SINDIR and the destination (low byte only) | |
3283 | * for any immediate operands passed in jmp, jc, jnc, call instructions. | |
3284 | * Example: | |
3285 | * mvi 0xFF call some_routine; | |
3286 | * | |
3287 | * Will set SINDEX[0] to 0xFF and call the routine "some_routine. | |
3288 | */ | |
3289 | register SINDEX { | |
3290 | address 0x0E2 | |
3291 | access_mode RW | |
3292 | size 2 | |
3293 | sindex | |
3294 | } | |
3295 | ||
3296 | /* | |
3297 | * Destination Index Register | |
3298 | * Incrementing index for writes to DINDIR. Can be used as a scratch register. | |
3299 | */ | |
3300 | register DINDEX { | |
3301 | address 0x0E4 | |
3302 | access_mode RW | |
3303 | size 2 | |
3304 | } | |
3305 | ||
3306 | /* | |
3307 | * Break Address | |
3308 | * Sequencer instruction breakpoint address address. | |
3309 | */ | |
3310 | register BRKADDR0 { | |
3311 | address 0x0E6 | |
3312 | access_mode RW | |
3313 | } | |
3314 | ||
3315 | register BRKADDR1 { | |
3316 | address 0x0E6 | |
3317 | access_mode RW | |
3318 | field BRKDIS 0x80 /* Disable Breakpoint */ | |
3319 | } | |
3320 | ||
3321 | /* | |
3322 | * All Ones | |
3323 | * All reads to this register return the value 0xFF. | |
3324 | */ | |
3325 | register ALLONES { | |
3326 | address 0x0E8 | |
3327 | access_mode RO | |
3328 | allones | |
3329 | } | |
3330 | ||
3331 | /* | |
3332 | * All Zeros | |
3333 | * All reads to this register return the value 0. | |
3334 | */ | |
3335 | register ALLZEROS { | |
3336 | address 0x0EA | |
3337 | access_mode RO | |
3338 | allzeros | |
3339 | } | |
3340 | ||
3341 | /* | |
3342 | * No Destination | |
3343 | * Writes to this register have no effect. | |
3344 | */ | |
3345 | register NONE { | |
3346 | address 0x0EA | |
3347 | access_mode WO | |
3348 | none | |
3349 | } | |
3350 | ||
3351 | /* | |
3352 | * Source Index Indirect | |
3353 | * Reading this register is equivalent to reading (register_base + SINDEX) and | |
3354 | * incrementing SINDEX by 1. | |
3355 | */ | |
3356 | register SINDIR { | |
3357 | address 0x0EC | |
3358 | access_mode RO | |
3359 | } | |
3360 | ||
3361 | /* | |
3362 | * Destination Index Indirect | |
3363 | * Writing this register is equivalent to writing to (register_base + DINDEX) | |
3364 | * and incrementing DINDEX by 1. | |
3365 | */ | |
3366 | register DINDIR { | |
3367 | address 0x0ED | |
3368 | access_mode WO | |
3369 | } | |
3370 | ||
3371 | /* | |
3372 | * Function One | |
3373 | * 2's complement to bit value conversion. Write the 2's complement value | |
3374 | * (0-7 only) to the top nibble and retrieve the bit indexed by that value | |
3375 | * on the next read of this register. | |
3376 | * Example: | |
3377 | * Write 0x60 | |
3378 | * Read 0x40 | |
3379 | */ | |
3380 | register FUNCTION1 { | |
3381 | address 0x0F0 | |
3382 | access_mode RW | |
3383 | } | |
3384 | ||
3385 | /* | |
3386 | * Stack | |
3387 | * Window into the stack. Each stack location is 10 bits wide reported | |
3388 | * low byte followed by high byte. There are 8 stack locations. | |
3389 | */ | |
3390 | register STACK { | |
3391 | address 0x0F2 | |
3392 | access_mode RW | |
3393 | } | |
3394 | ||
3395 | /* | |
3396 | * Interrupt Vector 1 Address | |
3397 | * Interrupt branch address for SCS SEQ_INT1 mode 0 and 1 interrupts. | |
3398 | */ | |
3399 | register INTVEC1_ADDR { | |
3400 | address 0x0F4 | |
3401 | access_mode RW | |
3402 | size 2 | |
3403 | modes M_CFG | |
3404 | } | |
3405 | ||
3406 | /* | |
3407 | * Current Address | |
3408 | * Address of the SEQRAM instruction currently executing instruction. | |
3409 | */ | |
3410 | register CURADDR { | |
3411 | address 0x0F4 | |
3412 | access_mode RW | |
3413 | size 2 | |
3414 | modes M_SCSI | |
3415 | } | |
3416 | ||
3417 | /* | |
3418 | * Interrupt Vector 2 Address | |
3419 | * Interrupt branch address for HST_SEQ_INT2 interrupts. | |
3420 | */ | |
3421 | register INTVEC2_ADDR { | |
3422 | address 0x0F6 | |
3423 | access_mode RW | |
3424 | size 2 | |
3425 | modes M_CFG | |
3426 | } | |
3427 | ||
3428 | /* | |
3429 | * Last Address | |
3430 | * Address of the SEQRAM instruction executed prior to the current instruction. | |
3431 | */ | |
3432 | register LASTADDR { | |
3433 | address 0x0F6 | |
3434 | access_mode RW | |
3435 | size 2 | |
3436 | modes M_SCSI | |
3437 | } | |
3438 | ||
3439 | register AHD_PCI_CONFIG_BASE { | |
3440 | address 0x100 | |
3441 | access_mode RW | |
3442 | size 256 | |
3443 | modes M_CFG | |
3444 | } | |
3445 | ||
3446 | /* ---------------------- Scratch RAM Offsets ------------------------- */ | |
3447 | scratch_ram { | |
3448 | /* Mode Specific */ | |
3449 | address 0x0A0 | |
3450 | size 8 | |
3451 | modes 0, 1, 2, 3 | |
3452 | REG0 { | |
3453 | size 2 | |
3454 | } | |
3455 | REG1 { | |
3456 | size 2 | |
3457 | } | |
3458 | REG_ISR { | |
3459 | size 2 | |
3460 | } | |
3461 | SG_STATE { | |
3462 | size 1 | |
3463 | field SEGS_AVAIL 0x01 | |
3464 | field LOADING_NEEDED 0x02 | |
3465 | field FETCH_INPROG 0x04 | |
3466 | } | |
3467 | /* | |
3468 | * Track whether the transfer byte count for | |
3469 | * the current data phase is odd. | |
3470 | */ | |
3471 | DATA_COUNT_ODD { | |
3472 | size 1 | |
3473 | } | |
3474 | } | |
3475 | ||
3476 | scratch_ram { | |
3477 | /* Mode Specific */ | |
3478 | address 0x0F8 | |
3479 | size 8 | |
3480 | modes 0, 1, 2, 3 | |
3481 | LONGJMP_ADDR { | |
3482 | size 2 | |
3483 | } | |
3484 | ACCUM_SAVE { | |
3485 | size 1 | |
3486 | } | |
3487 | } | |
3488 | ||
3489 | ||
3490 | scratch_ram { | |
3491 | address 0x100 | |
3492 | size 128 | |
3493 | modes 0, 1, 2, 3 | |
3494 | /* | |
3495 | * Per "other-id" execution queues. We use an array of | |
3496 | * tail pointers into lists of SCBs sorted by "other-id". | |
3497 | * The execution head pointer threads the head SCBs for | |
3498 | * each list. | |
3499 | */ | |
3500 | WAITING_SCB_TAILS { | |
3501 | size 32 | |
3502 | } | |
3503 | WAITING_TID_HEAD { | |
3504 | size 2 | |
3505 | } | |
3506 | WAITING_TID_TAIL { | |
3507 | size 2 | |
3508 | } | |
3509 | /* | |
3510 | * SCBID of the next SCB in the new SCB queue. | |
3511 | */ | |
3512 | NEXT_QUEUED_SCB_ADDR { | |
3513 | size 4 | |
3514 | } | |
3515 | /* | |
3516 | * head of list of SCBs that have | |
3517 | * completed but have not been | |
3518 | * put into the qoutfifo. | |
3519 | */ | |
3520 | COMPLETE_SCB_HEAD { | |
3521 | size 2 | |
3522 | } | |
3523 | /* | |
3524 | * The list of completed SCBs in | |
3525 | * the active DMA. | |
3526 | */ | |
3527 | COMPLETE_SCB_DMAINPROG_HEAD { | |
3528 | size 2 | |
3529 | } | |
3530 | /* | |
3531 | * head of list of SCBs that have | |
3532 | * completed but need to be uploaded | |
3533 | * to the host prior to being completed. | |
3534 | */ | |
3535 | COMPLETE_DMA_SCB_HEAD { | |
3536 | size 2 | |
3537 | } | |
11668bb6 HR |
3538 | /* |
3539 | * tail of list of SCBs that have | |
3540 | * completed but need to be uploaded | |
3541 | * to the host prior to being completed. | |
3542 | */ | |
3543 | COMPLETE_DMA_SCB_TAIL { | |
3544 | size 2 | |
3545 | } | |
3546 | /* | |
3547 | * head of list of SCBs that have | |
3548 | * been uploaded to the host, but cannot | |
3549 | * be completed until the QFREEZE is in | |
3550 | * full effect (i.e. no selections pending). | |
3551 | */ | |
3552 | COMPLETE_ON_QFREEZE_HEAD { | |
3553 | size 2 | |
3554 | } | |
3555 | /* | |
3556 | * Counting semaphore to prevent new select-outs | |
3557 | * The queue is frozen so long as the sequencer | |
3558 | * and kernel freeze counts differ. | |
3559 | */ | |
1da177e4 LT |
3560 | QFREEZE_COUNT { |
3561 | size 2 | |
3562 | } | |
11668bb6 HR |
3563 | KERNEL_QFREEZE_COUNT { |
3564 | size 2 | |
3565 | } | |
1da177e4 LT |
3566 | /* |
3567 | * Mode to restore on legacy idle loop exit. | |
3568 | */ | |
3569 | SAVED_MODE { | |
3570 | size 1 | |
3571 | } | |
3572 | /* | |
3573 | * Single byte buffer used to designate the type or message | |
3574 | * to send to a target. | |
3575 | */ | |
3576 | MSG_OUT { | |
3577 | size 1 | |
3578 | } | |
3579 | /* Parameters for DMA Logic */ | |
3580 | DMAPARAMS { | |
3581 | size 1 | |
3582 | field PRELOADEN 0x80 | |
3583 | field WIDEODD 0x40 | |
3584 | field SCSIEN 0x20 | |
3585 | field SDMAEN 0x10 | |
3586 | field SDMAENACK 0x10 | |
3587 | field HDMAEN 0x08 | |
3588 | field HDMAENACK 0x08 | |
3589 | field DIRECTION 0x04 /* Set indicates PCI->SCSI */ | |
3590 | field FIFOFLUSH 0x02 | |
3591 | field FIFORESET 0x01 | |
3592 | } | |
3593 | SEQ_FLAGS { | |
3594 | size 1 | |
3595 | field NOT_IDENTIFIED 0x80 | |
3596 | field NO_CDB_SENT 0x40 | |
3597 | field TARGET_CMD_IS_TAGGED 0x40 | |
3598 | field DPHASE 0x20 | |
3599 | /* Target flags */ | |
3600 | field TARG_CMD_PENDING 0x10 | |
3601 | field CMDPHASE_PENDING 0x08 | |
3602 | field DPHASE_PENDING 0x04 | |
3603 | field SPHASE_PENDING 0x02 | |
3604 | field NO_DISCONNECT 0x01 | |
3605 | } | |
3606 | /* | |
3607 | * Temporary storage for the | |
3608 | * target/channel/lun of a | |
3609 | * reconnecting target | |
3610 | */ | |
3611 | SAVED_SCSIID { | |
3612 | size 1 | |
3613 | } | |
3614 | SAVED_LUN { | |
3615 | size 1 | |
3616 | } | |
3617 | /* | |
3618 | * The last bus phase as seen by the sequencer. | |
3619 | */ | |
3620 | LASTPHASE { | |
3621 | size 1 | |
3622 | field CDI 0x80 | |
3623 | field IOI 0x40 | |
3624 | field MSGI 0x20 | |
3625 | field P_BUSFREE 0x01 | |
3626 | enum PHASE_MASK CDO|IOO|MSGO { | |
3627 | P_DATAOUT 0x0, | |
3628 | P_DATAIN IOO, | |
3629 | P_DATAOUT_DT P_DATAOUT|MSGO, | |
3630 | P_DATAIN_DT P_DATAIN|MSGO, | |
3631 | P_COMMAND CDO, | |
3632 | P_MESGOUT CDO|MSGO, | |
3633 | P_STATUS CDO|IOO, | |
3634 | P_MESGIN CDO|IOO|MSGO | |
3635 | } | |
3636 | } | |
3637 | /* | |
3638 | * Value to "or" into the SCBPTR[1] value to | |
3639 | * indicate that an entry in the QINFIFO is valid. | |
3640 | */ | |
3641 | QOUTFIFO_ENTRY_VALID_TAG { | |
3642 | size 1 | |
3643 | } | |
11668bb6 HR |
3644 | /* |
3645 | * Kernel and sequencer offsets into the queue of | |
3646 | * incoming target mode command descriptors. The | |
3647 | * queue is full when the KERNEL_TQINPOS == TQINPOS. | |
3648 | */ | |
3649 | KERNEL_TQINPOS { | |
3650 | size 1 | |
3651 | } | |
be0d6768 | 3652 | TQINPOS { |
11668bb6 HR |
3653 | size 1 |
3654 | } | |
1da177e4 LT |
3655 | /* |
3656 | * Base address of our shared data with the kernel driver in host | |
3657 | * memory. This includes the qoutfifo and target mode | |
3658 | * incoming command queue. | |
3659 | */ | |
3660 | SHARED_DATA_ADDR { | |
3661 | size 4 | |
3662 | } | |
3663 | /* | |
3664 | * Pointer to location in host memory for next | |
3665 | * position in the qoutfifo. | |
3666 | */ | |
3667 | QOUTFIFO_NEXT_ADDR { | |
3668 | size 4 | |
3669 | } | |
1da177e4 LT |
3670 | ARG_1 { |
3671 | size 1 | |
3672 | mask SEND_MSG 0x80 | |
3673 | mask SEND_SENSE 0x40 | |
3674 | mask SEND_REJ 0x20 | |
3675 | mask MSGOUT_PHASEMIS 0x10 | |
3676 | mask EXIT_MSG_LOOP 0x08 | |
3677 | mask CONT_MSG_LOOP_WRITE 0x04 | |
3678 | mask CONT_MSG_LOOP_READ 0x03 | |
3679 | mask CONT_MSG_LOOP_TARG 0x02 | |
3680 | alias RETURN_1 | |
3681 | } | |
3682 | ARG_2 { | |
3683 | size 1 | |
3684 | alias RETURN_2 | |
3685 | } | |
3686 | ||
3687 | /* | |
3688 | * Snapshot of MSG_OUT taken after each message is sent. | |
3689 | */ | |
3690 | LAST_MSG { | |
3691 | size 1 | |
3692 | } | |
3693 | ||
3694 | /* | |
3695 | * Sequences the kernel driver has okayed for us. This allows | |
3696 | * the driver to do things like prevent initiator or target | |
3697 | * operations. | |
3698 | */ | |
3699 | SCSISEQ_TEMPLATE { | |
3700 | size 1 | |
3701 | field MANUALCTL 0x40 | |
3702 | field ENSELI 0x20 | |
3703 | field ENRSELI 0x10 | |
3704 | field MANUALP 0x0C | |
3705 | field ENAUTOATNP 0x02 | |
3706 | field ALTSTIM 0x01 | |
3707 | } | |
3708 | ||
3709 | /* | |
3710 | * The initiator specified tag for this target mode transaction. | |
3711 | */ | |
3712 | INITIATOR_TAG { | |
3713 | size 1 | |
3714 | } | |
3715 | ||
3716 | SEQ_FLAGS2 { | |
3717 | size 1 | |
53467e63 HR |
3718 | field PENDING_MK_MESSAGE 0x01 |
3719 | field TARGET_MSG_PENDING 0x02 | |
3720 | field SELECTOUT_QFROZEN 0x04 | |
1da177e4 LT |
3721 | } |
3722 | ||
3723 | ALLOCFIFO_SCBPTR { | |
3724 | size 2 | |
3725 | } | |
3726 | ||
3727 | /* | |
3728 | * The maximum amount of time to wait, when interrupt coalescing | |
3729 | * is enabled, before issueing a CMDCMPLT interrupt for a completed | |
3730 | * command. | |
3731 | */ | |
3732 | INT_COALESCING_TIMER { | |
3733 | size 2 | |
3734 | } | |
3735 | ||
3736 | /* | |
3737 | * The maximum number of commands to coalesce into a single interrupt. | |
3738 | * Actually the 2's complement of that value to simplify sequencer | |
3739 | * code. | |
3740 | */ | |
3741 | INT_COALESCING_MAXCMDS { | |
3742 | size 1 | |
3743 | } | |
3744 | ||
3745 | /* | |
3746 | * The minimum number of commands still outstanding required | |
3747 | * to continue coalescing (2's complement of value). | |
3748 | */ | |
3749 | INT_COALESCING_MINCMDS { | |
3750 | size 1 | |
3751 | } | |
3752 | ||
3753 | /* | |
3754 | * Number of commands "in-flight". | |
3755 | */ | |
3756 | CMDS_PENDING { | |
3757 | size 2 | |
3758 | } | |
3759 | ||
3760 | /* | |
3761 | * The count of commands that have been coalesced. | |
3762 | */ | |
3763 | INT_COALESCING_CMDCOUNT { | |
3764 | size 1 | |
3765 | } | |
3766 | ||
3767 | /* | |
3768 | * Since the HS_MAIBOX is self clearing, copy its contents to | |
3769 | * this position in scratch ram every time it changes. | |
3770 | */ | |
3771 | LOCAL_HS_MAILBOX { | |
3772 | size 1 | |
3773 | } | |
3774 | /* | |
3775 | * Target-mode CDB type to CDB length table used | |
3776 | * in non-packetized operation. | |
3777 | */ | |
3778 | CMDSIZE_TABLE { | |
3779 | size 8 | |
3780 | } | |
53467e63 HR |
3781 | /* |
3782 | * When an SCB with the MK_MESSAGE flag is | |
3783 | * queued to the controller, it cannot enter | |
3784 | * the waiting for selection list until the | |
3785 | * selections for any previously queued | |
3786 | * commands to that target complete. During | |
3787 | * the wait, the MK_MESSAGE SCB is queued | |
3788 | * here. | |
3789 | */ | |
3790 | MK_MESSAGE_SCB { | |
3791 | size 2 | |
3792 | } | |
3793 | /* | |
3794 | * Saved SCSIID of MK_MESSAGE_SCB to avoid | |
3795 | * an extra SCBPTR operation when deciding | |
3796 | * if the MK_MESSAGE_SCB can be run. | |
3797 | */ | |
3798 | MK_MESSAGE_SCSIID { | |
3799 | size 1 | |
3800 | } | |
1da177e4 LT |
3801 | } |
3802 | ||
3803 | /************************* Hardware SCB Definition ****************************/ | |
3804 | scb { | |
3805 | address 0x180 | |
3806 | size 64 | |
3807 | modes 0, 1, 2, 3 | |
3808 | SCB_RESIDUAL_DATACNT { | |
3809 | size 4 | |
3810 | alias SCB_CDB_STORE | |
3811 | alias SCB_HOST_CDB_PTR | |
3812 | } | |
3813 | SCB_RESIDUAL_SGPTR { | |
3814 | size 4 | |
3815 | field SG_ADDR_MASK 0xf8 /* In the last byte */ | |
3816 | field SG_OVERRUN_RESID 0x02 /* In the first byte */ | |
3817 | field SG_LIST_NULL 0x01 /* In the first byte */ | |
3818 | } | |
3819 | SCB_SCSI_STATUS { | |
3820 | size 1 | |
3821 | alias SCB_HOST_CDB_LEN | |
3822 | } | |
3823 | SCB_TARGET_PHASES { | |
3824 | size 1 | |
3825 | } | |
3826 | SCB_TARGET_DATA_DIR { | |
3827 | size 1 | |
3828 | } | |
3829 | SCB_TARGET_ITAG { | |
3830 | size 1 | |
3831 | } | |
3832 | SCB_SENSE_BUSADDR { | |
3833 | /* | |
3834 | * Only valid if CDB length is less than 13 bytes or | |
3835 | * we are using a CDB pointer. Otherwise contains | |
3836 | * the last 4 bytes of embedded cdb information. | |
3837 | */ | |
3838 | size 4 | |
3839 | alias SCB_NEXT_COMPLETE | |
3840 | } | |
3841 | SCB_TAG { | |
3842 | alias SCB_FIFO_USE_COUNT | |
3843 | size 2 | |
3844 | } | |
3845 | SCB_CONTROL { | |
3846 | size 1 | |
3847 | field TARGET_SCB 0x80 | |
3848 | field DISCENB 0x40 | |
3849 | field TAG_ENB 0x20 | |
3850 | field MK_MESSAGE 0x10 | |
3851 | field STATUS_RCVD 0x08 | |
3852 | field DISCONNECTED 0x04 | |
3853 | field SCB_TAG_TYPE 0x03 | |
3854 | } | |
3855 | SCB_SCSIID { | |
3856 | size 1 | |
3857 | field TID 0xF0 | |
3858 | field OID 0x0F | |
3859 | } | |
3860 | SCB_LUN { | |
3861 | size 1 | |
3862 | field LID 0xff | |
3863 | } | |
3864 | SCB_TASK_ATTRIBUTE { | |
3865 | size 1 | |
3866 | /* | |
3867 | * Overloaded field for non-packetized | |
3868 | * ignore wide residue message handling. | |
3869 | */ | |
3870 | field SCB_XFERLEN_ODD 0x01 | |
3871 | } | |
3872 | SCB_CDB_LEN { | |
3873 | size 1 | |
3874 | field SCB_CDB_LEN_PTR 0x80 /* CDB in host memory */ | |
3875 | } | |
3876 | SCB_TASK_MANAGEMENT { | |
3877 | size 1 | |
3878 | } | |
3879 | SCB_DATAPTR { | |
3880 | size 8 | |
3881 | } | |
3882 | SCB_DATACNT { | |
3883 | /* | |
3884 | * The last byte is really the high address bits for | |
3885 | * the data address. | |
3886 | */ | |
3887 | size 4 | |
3888 | field SG_LAST_SEG 0x80 /* In the fourth byte */ | |
3889 | field SG_HIGH_ADDR_BITS 0x7F /* In the fourth byte */ | |
3890 | } | |
3891 | SCB_SGPTR { | |
3892 | size 4 | |
3893 | field SG_STATUS_VALID 0x04 /* In the first byte */ | |
3894 | field SG_FULL_RESID 0x02 /* In the first byte */ | |
3895 | field SG_LIST_NULL 0x01 /* In the first byte */ | |
3896 | } | |
3897 | SCB_BUSADDR { | |
3898 | size 4 | |
3899 | } | |
3900 | SCB_NEXT { | |
3901 | alias SCB_NEXT_SCB_BUSADDR | |
3902 | size 2 | |
3903 | } | |
3904 | SCB_NEXT2 { | |
3905 | size 2 | |
3906 | } | |
3907 | SCB_SPARE { | |
3908 | size 8 | |
3909 | alias SCB_PKT_LUN | |
3910 | } | |
3911 | SCB_DISCONNECTED_LISTS { | |
3912 | size 8 | |
3913 | } | |
3914 | } | |
3915 | ||
3916 | /*********************************** Constants ********************************/ | |
3917 | const MK_MESSAGE_BIT_OFFSET 4 | |
3918 | const TID_SHIFT 4 | |
3919 | const TARGET_CMD_CMPLT 0xfe | |
3920 | const INVALID_ADDR 0x80 | |
3921 | #define SCB_LIST_NULL 0xff | |
3922 | #define QOUTFIFO_ENTRY_VALID_TOGGLE 0x80 | |
3923 | ||
3924 | const CCSGADDR_MAX 0x80 | |
3925 | const CCSCBADDR_MAX 0x80 | |
3926 | const CCSGRAM_MAXSEGS 16 | |
3927 | ||
3928 | /* Selection Timeout Timer Constants */ | |
3929 | const STIMESEL_SHIFT 3 | |
3930 | const STIMESEL_MIN 0x18 | |
3931 | const STIMESEL_BUG_ADJ 0x8 | |
3932 | ||
3933 | /* WDTR Message values */ | |
3934 | const BUS_8_BIT 0x00 | |
3935 | const BUS_16_BIT 0x01 | |
3936 | const BUS_32_BIT 0x02 | |
3937 | ||
3938 | /* Offset maximums */ | |
3939 | const MAX_OFFSET 0xfe | |
3940 | const MAX_OFFSET_PACED 0xfe | |
3941 | const MAX_OFFSET_PACED_BUG 0x7f | |
3942 | /* | |
3943 | * Some 160 devices incorrectly accept 0xfe as a | |
3944 | * sync offset, but will overrun this value. Limit | |
3945 | * to 0x7f for speed lower than U320 which will | |
3946 | * avoid the persistent sync offset overruns. | |
3947 | */ | |
3948 | const MAX_OFFSET_NON_PACED 0x7f | |
3949 | const HOST_MSG 0xff | |
3950 | ||
3951 | /* | |
3952 | * The size of our sense buffers. | |
3953 | * Sense buffer mapping can be handled in either of two ways. | |
3954 | * The first is to allocate a dmamap for each transaction. | |
3955 | * Depending on the architecture, dmamaps can be costly. The | |
3956 | * alternative is to statically map the buffers in much the same | |
3957 | * way we handle our scatter gather lists. The driver implements | |
3958 | * the later. | |
3959 | */ | |
3960 | const AHD_SENSE_BUFSIZE 256 | |
3961 | ||
3962 | /* Target mode command processing constants */ | |
3963 | const CMD_GROUP_CODE_SHIFT 0x05 | |
3964 | ||
3965 | const STATUS_BUSY 0x08 | |
3966 | const STATUS_QUEUE_FULL 0x28 | |
3967 | const STATUS_PKT_SENSE 0xFF | |
3968 | const TARGET_DATA_IN 1 | |
3969 | ||
3970 | const SCB_TRANSFER_SIZE_FULL_LUN 56 | |
3971 | const SCB_TRANSFER_SIZE_1BYTE_LUN 48 | |
3972 | /* PKT_OVERRUN_BUFSIZE must be a multiple of 256 less than 64K */ | |
3973 | const PKT_OVERRUN_BUFSIZE 512 | |
3974 | ||
3975 | /* | |
3976 | * Timer parameters. | |
3977 | */ | |
3978 | const AHD_TIMER_US_PER_TICK 25 | |
3979 | const AHD_TIMER_MAX_TICKS 0xFFFF | |
3980 | const AHD_TIMER_MAX_US (AHD_TIMER_MAX_TICKS * AHD_TIMER_US_PER_TICK) | |
3981 | ||
3982 | /* | |
3983 | * Downloaded (kernel inserted) constants | |
3984 | */ | |
3985 | const SG_PREFETCH_CNT download | |
3986 | const SG_PREFETCH_CNT_LIMIT download | |
3987 | const SG_PREFETCH_ALIGN_MASK download | |
3988 | const SG_PREFETCH_ADDR_MASK download | |
3989 | const SG_SIZEOF download | |
3990 | const PKT_OVERRUN_BUFOFFSET download | |
3991 | const SCB_TRANSFER_SIZE download | |
11668bb6 | 3992 | const CACHELINE_MASK download |
1da177e4 LT |
3993 | |
3994 | /* | |
3995 | * BIOS SCB offsets | |
3996 | */ | |
3997 | const NVRAM_SCB_OFFSET 0x2C |