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[PATCH] libata: kill NULL qc handling from ->eng_timeout callbacks
[linux-2.6-block.git] / drivers / scsi / ahci.c
CommitLineData
1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
af36d7f0
JG		 4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
1da177e4 30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
af36d7f0 31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
1da177e4
LT		 32 *
33 */
34
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/init.h>
39#include <linux/blkdev.h>
40#include <linux/delay.h>
41#include <linux/interrupt.h>
42#include <linux/sched.h>
87507cfd 43#include <linux/dma-mapping.h>
a9524a76 44#include <linux/device.h>
1da177e4 45#include <scsi/scsi_host.h>
193515d5 46#include <scsi/scsi_cmnd.h>
1da177e4
LT		 47#include <linux/libata.h>
48#include <asm/io.h>
49
50#define DRV_NAME "ahci"
7bdd7208 51#define DRV_VERSION "1.2"
1da177e4
LT		 52
53
54enum {
55 AHCI_PCI_BAR = 5,
56 AHCI_MAX_SG = 168, /* hardware max is 64K */
57 AHCI_DMA_BOUNDARY = 0xffffffff,
58 AHCI_USE_CLUSTERING = 0,
59 AHCI_CMD_SLOT_SZ = 32 * 32,
60 AHCI_RX_FIS_SZ = 256,
61 AHCI_CMD_TBL_HDR = 0x80,
a0ea7328 62 AHCI_CMD_TBL_CDB = 0x40,
1da177e4
LT		 63 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
64 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
65 AHCI_RX_FIS_SZ,
66 AHCI_IRQ_ON_SG = (1 << 31),
67 AHCI_CMD_ATAPI = (1 << 5),
68 AHCI_CMD_WRITE = (1 << 6),
22b49985
TH		 69 AHCI_CMD_RESET = (1 << 8),
70 AHCI_CMD_CLR_BUSY = (1 << 10),
1da177e4
LT		 71
72 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
73
74 board_ahci = 0,
75
76 /* global controller registers */
77 HOST_CAP = 0x00, /* host capabilities */
78 HOST_CTL = 0x04, /* global host control */
79 HOST_IRQ_STAT = 0x08, /* interrupt status */
80 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
81 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
82
83 /* HOST_CTL bits */
84 HOST_RESET = (1 << 0), /* reset controller; self-clear */
85 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
86 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
87
88 /* HOST_CAP bits */
89 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
22b49985 90 HOST_CAP_CLO = (1 << 24), /* Command List Override support */
1da177e4
LT		 91
92 /* registers for each SATA port */
93 PORT_LST_ADDR = 0x00, /* command list DMA addr */
94 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
95 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
96 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
97 PORT_IRQ_STAT = 0x10, /* interrupt status */
98 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
99 PORT_CMD = 0x18, /* port command */
100 PORT_TFDATA = 0x20, /* taskfile data */
101 PORT_SIG = 0x24, /* device TF signature */
102 PORT_CMD_ISSUE = 0x38, /* command issue */
103 PORT_SCR = 0x28, /* SATA phy register block */
104 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
105 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
106 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
107 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
108
109 /* PORT_IRQ_{STAT,MASK} bits */
110 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
111 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
112 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
113 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
114 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
115 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
116 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
117 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
118
119 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
120 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
121 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
122 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
123 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
124 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
125 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
126 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
127 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
128
129 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
130 PORT_IRQ_HBUS_ERR |
131 PORT_IRQ_HBUS_DATA_ERR |
132 PORT_IRQ_IF_ERR,
133 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
134 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
135 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
136 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
137 PORT_IRQ_D2H_REG_FIS,
138
139 /* PORT_CMD bits */
02eaa666 140 PORT_CMD_ATAPI = (1 << 24), /* Device is ATAPI */
1da177e4
LT		 141 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
142 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
143 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
22b49985 144 PORT_CMD_CLO = (1 << 3), /* Command list override */
1da177e4
LT		 145 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
146 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
147 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
148
149 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
150 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
151 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
4b0060f4
JG		 152
153 /* hpriv->flags bits */
154 AHCI_FLAG_MSI = (1 << 0),
1da177e4
LT		 155};
156
157struct ahci_cmd_hdr {
158 u32 opts;
159 u32 status;
160 u32 tbl_addr;
161 u32 tbl_addr_hi;
162 u32 reserved[4];
163};
164
165struct ahci_sg {
166 u32 addr;
167 u32 addr_hi;
168 u32 reserved;
169 u32 flags_size;
170};
171
172struct ahci_host_priv {
173 unsigned long flags;
174 u32 cap; /* cache of HOST_CAP register */
175 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
176};
177
178struct ahci_port_priv {
179 struct ahci_cmd_hdr *cmd_slot;
180 dma_addr_t cmd_slot_dma;
181 void *cmd_tbl;
182 dma_addr_t cmd_tbl_dma;
183 struct ahci_sg *cmd_tbl_sg;
184 void *rx_fis;
185 dma_addr_t rx_fis_dma;
186};
187
188static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
189static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
190static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
9a3d9eb0 191static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc);
1da177e4
LT		 192static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
193static void ahci_phy_reset(struct ata_port *ap);
194static void ahci_irq_clear(struct ata_port *ap);
195static void ahci_eng_timeout(struct ata_port *ap);
196static int ahci_port_start(struct ata_port *ap);
197static void ahci_port_stop(struct ata_port *ap);
1da177e4
LT		 198static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
199static void ahci_qc_prep(struct ata_queued_cmd *qc);
200static u8 ahci_check_status(struct ata_port *ap);
1da177e4 201static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
907f4678 202static void ahci_remove_one (struct pci_dev *pdev);
1da177e4 203
193515d5 204static struct scsi_host_template ahci_sht = {
1da177e4
LT		 205 .module = THIS_MODULE,
206 .name = DRV_NAME,
207 .ioctl = ata_scsi_ioctl,
208 .queuecommand = ata_scsi_queuecmd,
35daeb8f 209 .eh_timed_out = ata_scsi_timed_out,
1da177e4
LT		 210 .eh_strategy_handler = ata_scsi_error,
211 .can_queue = ATA_DEF_QUEUE,
212 .this_id = ATA_SHT_THIS_ID,
213 .sg_tablesize = AHCI_MAX_SG,
214 .max_sectors = ATA_MAX_SECTORS,
215 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
216 .emulated = ATA_SHT_EMULATED,
217 .use_clustering = AHCI_USE_CLUSTERING,
218 .proc_name = DRV_NAME,
219 .dma_boundary = AHCI_DMA_BOUNDARY,
220 .slave_configure = ata_scsi_slave_config,
221 .bios_param = ata_std_bios_param,
1da177e4
LT		 222};
223
057ace5e 224static const struct ata_port_operations ahci_ops = {
1da177e4
LT		 225 .port_disable = ata_port_disable,
226
227 .check_status = ahci_check_status,
228 .check_altstatus = ahci_check_status,
1da177e4
LT		 229 .dev_select = ata_noop_dev_select,
230
231 .tf_read = ahci_tf_read,
232
233 .phy_reset = ahci_phy_reset,
234
235 .qc_prep = ahci_qc_prep,
236 .qc_issue = ahci_qc_issue,
237
238 .eng_timeout = ahci_eng_timeout,
239
240 .irq_handler = ahci_interrupt,
241 .irq_clear = ahci_irq_clear,
242
243 .scr_read = ahci_scr_read,
244 .scr_write = ahci_scr_write,
245
246 .port_start = ahci_port_start,
247 .port_stop = ahci_port_stop,
1da177e4
LT		 248};
249
98ac62de 250static const struct ata_port_info ahci_port_info[] = {
1da177e4
LT		 251 /* board_ahci */
252 {
253 .sht = &ahci_sht,
254 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
255 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
256 ATA_FLAG_PIO_DMA,
7da79312 257 .pio_mask = 0x1f, /* pio0-4 */
1da177e4
LT		 258 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
259 .port_ops = &ahci_ops,
260 },
261};
262
3b7d697d 263static const struct pci_device_id ahci_pci_tbl[] = {
1da177e4
LT		 264 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ICH6 */
266 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ICH6M */
268 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_ahci }, /* ICH7 */
270 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_ahci }, /* ICH7M */
272 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 board_ahci }, /* ICH7R */
274 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
275 board_ahci }, /* ULi M5288 */
680d3235
JG		 276 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
277 board_ahci }, /* ESB2 */
278 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
279 board_ahci }, /* ESB2 */
280 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
281 board_ahci }, /* ESB2 */
3db368f7
JG		 282 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
283 board_ahci }, /* ICH7-M DH */
f285757c
JG		 284 { PCI_VENDOR_ID_INTEL, 0x2821, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
285 board_ahci }, /* ICH8 */
286 { PCI_VENDOR_ID_INTEL, 0x2822, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
287 board_ahci }, /* ICH8 */
288 { PCI_VENDOR_ID_INTEL, 0x2824, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
289 board_ahci }, /* ICH8 */
290 { PCI_VENDOR_ID_INTEL, 0x2829, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
291 board_ahci }, /* ICH8M */
292 { PCI_VENDOR_ID_INTEL, 0x282a, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
293 board_ahci }, /* ICH8M */
bd12097c
JG		 294 { 0x197b, 0x2360, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
295 board_ahci }, /* JMicron JMB360 */
9220a2d0
JG		 296 { 0x197b, 0x2363, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
297 board_ahci }, /* JMicron JMB363 */
1da177e4
LT		 298 { } /* terminate list */
299};
300
301
302static struct pci_driver ahci_pci_driver = {
303 .name = DRV_NAME,
304 .id_table = ahci_pci_tbl,
305 .probe = ahci_init_one,
907f4678 306 .remove = ahci_remove_one,
1da177e4
LT		 307};
308
309
310static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
311{
312 return base + 0x100 + (port * 0x80);
313}
314
ea6ba10b 315static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
1da177e4 316{
ea6ba10b 317 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
1da177e4
LT		 318}
319
1da177e4
LT		 320static int ahci_port_start(struct ata_port *ap)
321{
322 struct device *dev = ap->host_set->dev;
323 struct ahci_host_priv *hpriv = ap->host_set->private_data;
324 struct ahci_port_priv *pp;
ea6ba10b
JG		 325 void __iomem *mmio = ap->host_set->mmio_base;
326 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
327 void *mem;
1da177e4 328 dma_addr_t mem_dma;
6037d6bb 329 int rc;
1da177e4 330
1da177e4 331 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
0a139e79
TH		 332 if (!pp)
333 return -ENOMEM;
1da177e4
LT		 334 memset(pp, 0, sizeof(*pp));
335
6037d6bb
JG		 336 rc = ata_pad_alloc(ap, dev);
337 if (rc) {
cedc9a47 338 kfree(pp);
6037d6bb 339 return rc;
cedc9a47
JG		 340 }
341
1da177e4
LT		 342 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
343 if (!mem) {
6037d6bb 344 ata_pad_free(ap, dev);
0a139e79
TH		 345 kfree(pp);
346 return -ENOMEM;
1da177e4
LT		 347 }
348 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
349
350 /*
351 * First item in chunk of DMA memory: 32-slot command table,
352 * 32 bytes each in size
353 */
354 pp->cmd_slot = mem;
355 pp->cmd_slot_dma = mem_dma;
356
357 mem += AHCI_CMD_SLOT_SZ;
358 mem_dma += AHCI_CMD_SLOT_SZ;
359
360 /*
361 * Second item: Received-FIS area
362 */
363 pp->rx_fis = mem;
364 pp->rx_fis_dma = mem_dma;
365
366 mem += AHCI_RX_FIS_SZ;
367 mem_dma += AHCI_RX_FIS_SZ;
368
369 /*
370 * Third item: data area for storing a single command
371 * and its scatter-gather table
372 */
373 pp->cmd_tbl = mem;
374 pp->cmd_tbl_dma = mem_dma;
375
376 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
377
378 ap->private_data = pp;
379
380 if (hpriv->cap & HOST_CAP_64)
381 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
382 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
383 readl(port_mmio + PORT_LST_ADDR); /* flush */
384
385 if (hpriv->cap & HOST_CAP_64)
386 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
387 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
388 readl(port_mmio + PORT_FIS_ADDR); /* flush */
389
390 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
391 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
392 PORT_CMD_START, port_mmio + PORT_CMD);
393 readl(port_mmio + PORT_CMD); /* flush */
394
395 return 0;
1da177e4
LT		 396}
397
398
399static void ahci_port_stop(struct ata_port *ap)
400{
401 struct device *dev = ap->host_set->dev;
402 struct ahci_port_priv *pp = ap->private_data;
ea6ba10b
JG		 403 void __iomem *mmio = ap->host_set->mmio_base;
404 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4
LT		 405 u32 tmp;
406
407 tmp = readl(port_mmio + PORT_CMD);
408 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
409 writel(tmp, port_mmio + PORT_CMD);
410 readl(port_mmio + PORT_CMD); /* flush */
411
412 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
413 * this is slightly incorrect.
414 */
415 msleep(500);
416
417 ap->private_data = NULL;
418 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
419 pp->cmd_slot, pp->cmd_slot_dma);
6037d6bb 420 ata_pad_free(ap, dev);
1da177e4 421 kfree(pp);
1da177e4
LT		 422}
423
424static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
425{
426 unsigned int sc_reg;
427
428 switch (sc_reg_in) {
429 case SCR_STATUS: sc_reg = 0; break;
430 case SCR_CONTROL: sc_reg = 1; break;
431 case SCR_ERROR: sc_reg = 2; break;
432 case SCR_ACTIVE: sc_reg = 3; break;
433 default:
434 return 0xffffffffU;
435 }
436
1e4f2a96 437 return readl((void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 438}
439
440
441static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
442 u32 val)
443{
444 unsigned int sc_reg;
445
446 switch (sc_reg_in) {
447 case SCR_STATUS: sc_reg = 0; break;
448 case SCR_CONTROL: sc_reg = 1; break;
449 case SCR_ERROR: sc_reg = 2; break;
450 case SCR_ACTIVE: sc_reg = 3; break;
451 default:
452 return;
453 }
454
1e4f2a96 455 writel(val, (void __iomem *) ap->ioaddr.scr_addr + (sc_reg * 4));
1da177e4
LT		 456}
457
7c76d1e8
TH		 458static int ahci_stop_engine(struct ata_port *ap)
459{
460 void __iomem *mmio = ap->host_set->mmio_base;
461 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
462 int work;
463 u32 tmp;
464
465 tmp = readl(port_mmio + PORT_CMD);
466 tmp &= ~PORT_CMD_START;
467 writel(tmp, port_mmio + PORT_CMD);
468
469 /* wait for engine to stop. TODO: this could be
470 * as long as 500 msec
471 */
472 work = 1000;
473 while (work-- > 0) {
474 tmp = readl(port_mmio + PORT_CMD);
475 if ((tmp & PORT_CMD_LIST_ON) == 0)
476 return 0;
477 udelay(10);
478 }
479
480 return -EIO;
481}
482
483static void ahci_start_engine(struct ata_port *ap)
484{
485 void __iomem *mmio = ap->host_set->mmio_base;
486 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
487 u32 tmp;
488
489 tmp = readl(port_mmio + PORT_CMD);
490 tmp |= PORT_CMD_START;
491 writel(tmp, port_mmio + PORT_CMD);
492 readl(port_mmio + PORT_CMD); /* flush */
493}
494
422b7595 495static unsigned int ahci_dev_classify(struct ata_port *ap)
1da177e4
LT		 496{
497 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
498 struct ata_taskfile tf;
422b7595
TH		 499 u32 tmp;
500
501 tmp = readl(port_mmio + PORT_SIG);
502 tf.lbah = (tmp >> 24) & 0xff;
503 tf.lbam = (tmp >> 16) & 0xff;
504 tf.lbal = (tmp >> 8) & 0xff;
505 tf.nsect = (tmp) & 0xff;
506
507 return ata_dev_classify(&tf);
508}
509
510static void ahci_phy_reset(struct ata_port *ap)
511{
512 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4 513 struct ata_device *dev = &ap->device[0];
02eaa666 514 u32 new_tmp, tmp;
1da177e4 515
e0bfd149 516 ahci_stop_engine(ap);
1da177e4 517 __sata_phy_reset(ap);
e0bfd149 518 ahci_start_engine(ap);
1da177e4
LT		 519
520 if (ap->flags & ATA_FLAG_PORT_DISABLED)
521 return;
522
422b7595 523 dev->class = ahci_dev_classify(ap);
02eaa666 524 if (!ata_dev_present(dev)) {
1da177e4 525 ata_port_disable(ap);
02eaa666
JG		 526 return;
527 }
528
529 /* Make sure port's ATAPI bit is set appropriately */
530 new_tmp = tmp = readl(port_mmio + PORT_CMD);
531 if (dev->class == ATA_DEV_ATAPI)
532 new_tmp |= PORT_CMD_ATAPI;
533 else
534 new_tmp &= ~PORT_CMD_ATAPI;
535 if (new_tmp != tmp) {
536 writel(new_tmp, port_mmio + PORT_CMD);
537 readl(port_mmio + PORT_CMD); /* flush */
538 }
1da177e4
LT		 539}
540
541static u8 ahci_check_status(struct ata_port *ap)
542{
1e4f2a96 543 void __iomem *mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4
LT		 544
545 return readl(mmio + PORT_TFDATA) & 0xFF;
546}
547
1da177e4
LT		 548static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
549{
550 struct ahci_port_priv *pp = ap->private_data;
551 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
552
553 ata_tf_from_fis(d2h_fis, tf);
554}
555
828d09de 556static unsigned int ahci_fill_sg(struct ata_queued_cmd *qc)
1da177e4
LT		 557{
558 struct ahci_port_priv *pp = qc->ap->private_data;
cedc9a47
JG		 559 struct scatterlist *sg;
560 struct ahci_sg *ahci_sg;
828d09de 561 unsigned int n_sg = 0;
1da177e4
LT		 562
563 VPRINTK("ENTER\n");
564
565 /*
566 * Next, the S/G list.
567 */
cedc9a47
JG		 568 ahci_sg = pp->cmd_tbl_sg;
569 ata_for_each_sg(sg, qc) {
570 dma_addr_t addr = sg_dma_address(sg);
571 u32 sg_len = sg_dma_len(sg);
572
573 ahci_sg->addr = cpu_to_le32(addr & 0xffffffff);
574 ahci_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
575 ahci_sg->flags_size = cpu_to_le32(sg_len - 1);
828d09de 576
cedc9a47 577 ahci_sg++;
828d09de 578 n_sg++;
1da177e4 579 }
828d09de
JG		 580
581 return n_sg;
1da177e4
LT		 582}
583
584static void ahci_qc_prep(struct ata_queued_cmd *qc)
585{
a0ea7328
JG		 586 struct ata_port *ap = qc->ap;
587 struct ahci_port_priv *pp = ap->private_data;
1da177e4
LT		 588 u32 opts;
589 const u32 cmd_fis_len = 5; /* five dwords */
828d09de 590 unsigned int n_elem;
1da177e4
LT		 591
592 /*
593 * Fill in command slot information (currently only one slot,
594 * slot 0, is currently since we don't do queueing)
595 */
596
828d09de 597 opts = cmd_fis_len;
1da177e4
LT		 598 if (qc->tf.flags & ATA_TFLAG_WRITE)
599 opts |= AHCI_CMD_WRITE;
a0ea7328 600 if (is_atapi_taskfile(&qc->tf))
1da177e4 601 opts |= AHCI_CMD_ATAPI;
1da177e4
LT		 602
603 pp->cmd_slot[0].opts = cpu_to_le32(opts);
604 pp->cmd_slot[0].status = 0;
605 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
606 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
607
608 /*
609 * Fill in command table information. First, the header,
610 * a SATA Register - Host to Device command FIS.
611 */
612 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
a0ea7328
JG		 613 if (opts & AHCI_CMD_ATAPI) {
614 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
615 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
616 }
1da177e4
LT		 617
618 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
619 return;
620
828d09de
JG		 621 n_elem = ahci_fill_sg(qc);
622
623 pp->cmd_slot[0].opts |= cpu_to_le32(n_elem << 16);
1da177e4
LT		 624}
625
c2cd76ff 626static void ahci_restart_port(struct ata_port *ap, u32 irq_stat)
1da177e4 627{
ea6ba10b
JG		 628 void __iomem *mmio = ap->host_set->mmio_base;
629 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4 630 u32 tmp;
1da177e4 631
c2cd76ff
JG		 632 if ((ap->device[0].class != ATA_DEV_ATAPI) ||
633 ((irq_stat & PORT_IRQ_TF_ERR) == 0))
634 printk(KERN_WARNING "ata%u: port reset, "
635 "p_is %x is %x pis %x cmd %x tf %x ss %x se %x\n",
636 ap->id,
637 irq_stat,
638 readl(mmio + HOST_IRQ_STAT),
639 readl(port_mmio + PORT_IRQ_STAT),
640 readl(port_mmio + PORT_CMD),
641 readl(port_mmio + PORT_TFDATA),
642 readl(port_mmio + PORT_SCR_STAT),
643 readl(port_mmio + PORT_SCR_ERR));
9f68a248 644
1da177e4 645 /* stop DMA */
7c76d1e8 646 ahci_stop_engine(ap);
1da177e4
LT		 647
648 /* clear SATA phy error, if any */
649 tmp = readl(port_mmio + PORT_SCR_ERR);
650 writel(tmp, port_mmio + PORT_SCR_ERR);
651
652 /* if DRQ/BSY is set, device needs to be reset.
653 * if so, issue COMRESET
654 */
655 tmp = readl(port_mmio + PORT_TFDATA);
656 if (tmp & (ATA_BUSY | ATA_DRQ)) {
657 writel(0x301, port_mmio + PORT_SCR_CTL);
658 readl(port_mmio + PORT_SCR_CTL); /* flush */
659 udelay(10);
660 writel(0x300, port_mmio + PORT_SCR_CTL);
661 readl(port_mmio + PORT_SCR_CTL); /* flush */
662 }
663
664 /* re-start DMA */
7c76d1e8 665 ahci_start_engine(ap);
1da177e4
LT		 666}
667
668static void ahci_eng_timeout(struct ata_port *ap)
669{
b8f6153e 670 struct ata_host_set *host_set = ap->host_set;
ea6ba10b
JG		 671 void __iomem *mmio = host_set->mmio_base;
672 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4 673 struct ata_queued_cmd *qc;
b8f6153e 674 unsigned long flags;
1da177e4 675
9f68a248 676 printk(KERN_WARNING "ata%u: handling error/timeout\n", ap->id);
1da177e4 677
b8f6153e
JG		 678 spin_lock_irqsave(&host_set->lock, flags);
679
f6379020 680 ahci_restart_port(ap, readl(port_mmio + PORT_IRQ_STAT));
1da177e4 681 qc = ata_qc_from_tag(ap, ap->active_tag);
f6379020 682 qc->err_mask |= AC_ERR_TIMEOUT;
1da177e4 683
b8f6153e 684 spin_unlock_irqrestore(&host_set->lock, flags);
a72ec4ce 685
f6379020 686 ata_eh_qc_complete(qc);
1da177e4
LT		 687}
688
689static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
690{
ea6ba10b
JG		 691 void __iomem *mmio = ap->host_set->mmio_base;
692 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
1da177e4
LT		 693 u32 status, serr, ci;
694
695 serr = readl(port_mmio + PORT_SCR_ERR);
696 writel(serr, port_mmio + PORT_SCR_ERR);
697
698 status = readl(port_mmio + PORT_IRQ_STAT);
699 writel(status, port_mmio + PORT_IRQ_STAT);
700
701 ci = readl(port_mmio + PORT_CMD_ISSUE);
702 if (likely((ci & 0x1) == 0)) {
703 if (qc) {
a22e2eb0
AL		 704 assert(qc->err_mask == 0);
705 ata_qc_complete(qc);
1da177e4
LT		 706 qc = NULL;
707 }
708 }
709
710 if (status & PORT_IRQ_FATAL) {
ad36d1a5
JG		 711 unsigned int err_mask;
712 if (status & PORT_IRQ_TF_ERR)
713 err_mask = AC_ERR_DEV;
714 else if (status & PORT_IRQ_IF_ERR)
715 err_mask = AC_ERR_ATA_BUS;
716 else
717 err_mask = AC_ERR_HOST_BUS;
718
9f68a248 719 /* command processing has stopped due to error; restart */
c2cd76ff 720 ahci_restart_port(ap, status);
9f68a248 721
a22e2eb0 722 if (qc) {
284b6481 723 qc->err_mask |= err_mask;
a22e2eb0
AL		 724 ata_qc_complete(qc);
725 }
1da177e4
LT		 726 }
727
728 return 1;
729}
730
731static void ahci_irq_clear(struct ata_port *ap)
732{
733 /* TODO */
734}
735
736static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
737{
738 struct ata_host_set *host_set = dev_instance;
739 struct ahci_host_priv *hpriv;
740 unsigned int i, handled = 0;
ea6ba10b 741 void __iomem *mmio;
1da177e4
LT		 742 u32 irq_stat, irq_ack = 0;
743
744 VPRINTK("ENTER\n");
745
746 hpriv = host_set->private_data;
747 mmio = host_set->mmio_base;
748
749 /* sigh. 0xffffffff is a valid return from h/w */
750 irq_stat = readl(mmio + HOST_IRQ_STAT);
751 irq_stat &= hpriv->port_map;
752 if (!irq_stat)
753 return IRQ_NONE;
754
755 spin_lock(&host_set->lock);
756
757 for (i = 0; i < host_set->n_ports; i++) {
758 struct ata_port *ap;
1da177e4 759
67846b30
JG		 760 if (!(irq_stat & (1 << i)))
761 continue;
762
1da177e4 763 ap = host_set->ports[i];
67846b30 764 if (ap) {
1da177e4
LT		 765 struct ata_queued_cmd *qc;
766 qc = ata_qc_from_tag(ap, ap->active_tag);
67846b30
JG		 767 if (!ahci_host_intr(ap, qc))
768 if (ata_ratelimit()) {
769 struct pci_dev *pdev =
a9524a76
JG		 770 to_pci_dev(ap->host_set->dev);
771 dev_printk(KERN_WARNING, &pdev->dev,
772 "unhandled interrupt on port %u\n",
773 i);
67846b30
JG		 774 }
775
776 VPRINTK("port %u\n", i);
777 } else {
778 VPRINTK("port %u (no irq)\n", i);
779 if (ata_ratelimit()) {
780 struct pci_dev *pdev =
a9524a76
JG		 781 to_pci_dev(ap->host_set->dev);
782 dev_printk(KERN_WARNING, &pdev->dev,
783 "interrupt on disabled port %u\n", i);
67846b30 784 }
1da177e4 785 }
67846b30
JG		 786
787 irq_ack |= (1 << i);
1da177e4
LT		 788 }
789
790 if (irq_ack) {
791 writel(irq_ack, mmio + HOST_IRQ_STAT);
792 handled = 1;
793 }
794
795 spin_unlock(&host_set->lock);
796
797 VPRINTK("EXIT\n");
798
799 return IRQ_RETVAL(handled);
800}
801
9a3d9eb0 802static unsigned int ahci_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 803{
804 struct ata_port *ap = qc->ap;
ea6ba10b 805 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
1da177e4 806
1da177e4
LT		 807 writel(1, port_mmio + PORT_CMD_ISSUE);
808 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
809
810 return 0;
811}
812
813static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
814 unsigned int port_idx)
815{
816 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
817 base = ahci_port_base_ul(base, port_idx);
818 VPRINTK("base now==0x%lx\n", base);
819
820 port->cmd_addr = base;
821 port->scr_addr = base + PORT_SCR;
822
823 VPRINTK("EXIT\n");
824}
825
826static int ahci_host_init(struct ata_probe_ent *probe_ent)
827{
828 struct ahci_host_priv *hpriv = probe_ent->private_data;
829 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
830 void __iomem *mmio = probe_ent->mmio_base;
831 u32 tmp, cap_save;
1da177e4
LT		 832 unsigned int i, j, using_dac;
833 int rc;
834 void __iomem *port_mmio;
835
836 cap_save = readl(mmio + HOST_CAP);
837 cap_save &= ( (1<<28) | (1<<17) );
838 cap_save |= (1 << 27);
839
840 /* global controller reset */
841 tmp = readl(mmio + HOST_CTL);
842 if ((tmp & HOST_RESET) == 0) {
843 writel(tmp | HOST_RESET, mmio + HOST_CTL);
844 readl(mmio + HOST_CTL); /* flush */
845 }
846
847 /* reset must complete within 1 second, or
848 * the hardware should be considered fried.
849 */
850 ssleep(1);
851
852 tmp = readl(mmio + HOST_CTL);
853 if (tmp & HOST_RESET) {
a9524a76
JG		 854 dev_printk(KERN_ERR, &pdev->dev,
855 "controller reset failed (0x%x)\n", tmp);
1da177e4
LT		 856 return -EIO;
857 }
858
859 writel(HOST_AHCI_EN, mmio + HOST_CTL);
860 (void) readl(mmio + HOST_CTL); /* flush */
861 writel(cap_save, mmio + HOST_CAP);
862 writel(0xf, mmio + HOST_PORTS_IMPL);
863 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
864
bd12097c
JG		 865 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
866 u16 tmp16;
867
868 pci_read_config_word(pdev, 0x92, &tmp16);
869 tmp16 |= 0xf;
870 pci_write_config_word(pdev, 0x92, tmp16);
871 }
1da177e4
LT		 872
873 hpriv->cap = readl(mmio + HOST_CAP);
874 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
875 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
876
877 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
878 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
879
880 using_dac = hpriv->cap & HOST_CAP_64;
881 if (using_dac &&
882 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
883 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
884 if (rc) {
885 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
886 if (rc) {
a9524a76
JG		 887 dev_printk(KERN_ERR, &pdev->dev,
888 "64-bit DMA enable failed\n");
1da177e4
LT		 889 return rc;
890 }
891 }
1da177e4
LT		 892 } else {
893 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
894 if (rc) {
a9524a76
JG		 895 dev_printk(KERN_ERR, &pdev->dev,
896 "32-bit DMA enable failed\n");
1da177e4
LT		 897 return rc;
898 }
899 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
900 if (rc) {
a9524a76
JG		 901 dev_printk(KERN_ERR, &pdev->dev,
902 "32-bit consistent DMA enable failed\n");
1da177e4
LT		 903 return rc;
904 }
905 }
906
907 for (i = 0; i < probe_ent->n_ports; i++) {
908#if 0 /* BIOSen initialize this incorrectly */
909 if (!(hpriv->port_map & (1 << i)))
910 continue;
911#endif
912
913 port_mmio = ahci_port_base(mmio, i);
914 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
915
916 ahci_setup_port(&probe_ent->port[i],
917 (unsigned long) mmio, i);
918
919 /* make sure port is not active */
920 tmp = readl(port_mmio + PORT_CMD);
921 VPRINTK("PORT_CMD 0x%x\n", tmp);
922 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
923 PORT_CMD_FIS_RX | PORT_CMD_START)) {
924 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
925 PORT_CMD_FIS_RX | PORT_CMD_START);
926 writel(tmp, port_mmio + PORT_CMD);
927 readl(port_mmio + PORT_CMD); /* flush */
928
929 /* spec says 500 msecs for each bit, so
930 * this is slightly incorrect.
931 */
932 msleep(500);
933 }
934
935 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
936
937 j = 0;
938 while (j < 100) {
939 msleep(10);
940 tmp = readl(port_mmio + PORT_SCR_STAT);
941 if ((tmp & 0xf) == 0x3)
942 break;
943 j++;
944 }
945
946 tmp = readl(port_mmio + PORT_SCR_ERR);
947 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
948 writel(tmp, port_mmio + PORT_SCR_ERR);
949
950 /* ack any pending irq events for this port */
951 tmp = readl(port_mmio + PORT_IRQ_STAT);
952 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
953 if (tmp)
954 writel(tmp, port_mmio + PORT_IRQ_STAT);
955
956 writel(1 << i, mmio + HOST_IRQ_STAT);
957
958 /* set irq mask (enables interrupts) */
959 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
960 }
961
962 tmp = readl(mmio + HOST_CTL);
963 VPRINTK("HOST_CTL 0x%x\n", tmp);
964 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
965 tmp = readl(mmio + HOST_CTL);
966 VPRINTK("HOST_CTL 0x%x\n", tmp);
967
968 pci_set_master(pdev);
969
970 return 0;
971}
972
1da177e4
LT		 973static void ahci_print_info(struct ata_probe_ent *probe_ent)
974{
975 struct ahci_host_priv *hpriv = probe_ent->private_data;
976 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
ea6ba10b 977 void __iomem *mmio = probe_ent->mmio_base;
1da177e4
LT		 978 u32 vers, cap, impl, speed;
979 const char *speed_s;
980 u16 cc;
981 const char *scc_s;
982
983 vers = readl(mmio + HOST_VERSION);
984 cap = hpriv->cap;
985 impl = hpriv->port_map;
986
987 speed = (cap >> 20) & 0xf;
988 if (speed == 1)
989 speed_s = "1.5";
990 else if (speed == 2)
991 speed_s = "3";
992 else
993 speed_s = "?";
994
995 pci_read_config_word(pdev, 0x0a, &cc);
996 if (cc == 0x0101)
997 scc_s = "IDE";
998 else if (cc == 0x0106)
999 scc_s = "SATA";
1000 else if (cc == 0x0104)
1001 scc_s = "RAID";
1002 else
1003 scc_s = "unknown";
1004
a9524a76
JG		 1005 dev_printk(KERN_INFO, &pdev->dev,
1006 "AHCI %02x%02x.%02x%02x "
1da177e4
LT		 1007 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
1008 ,
1da177e4
LT		 1009
1010 (vers >> 24) & 0xff,
1011 (vers >> 16) & 0xff,
1012 (vers >> 8) & 0xff,
1013 vers & 0xff,
1014
1015 ((cap >> 8) & 0x1f) + 1,
1016 (cap & 0x1f) + 1,
1017 speed_s,
1018 impl,
1019 scc_s);
1020
a9524a76
JG		 1021 dev_printk(KERN_INFO, &pdev->dev,
1022 "flags: "
1da177e4
LT		 1023 "%s%s%s%s%s%s"
1024 "%s%s%s%s%s%s%s\n"
1025 ,
1da177e4
LT		 1026
1027 cap & (1 << 31) ? "64bit " : "",
1028 cap & (1 << 30) ? "ncq " : "",
1029 cap & (1 << 28) ? "ilck " : "",
1030 cap & (1 << 27) ? "stag " : "",
1031 cap & (1 << 26) ? "pm " : "",
1032 cap & (1 << 25) ? "led " : "",
1033
1034 cap & (1 << 24) ? "clo " : "",
1035 cap & (1 << 19) ? "nz " : "",
1036 cap & (1 << 18) ? "only " : "",
1037 cap & (1 << 17) ? "pmp " : "",
1038 cap & (1 << 15) ? "pio " : "",
1039 cap & (1 << 14) ? "slum " : "",
1040 cap & (1 << 13) ? "part " : ""
1041 );
1042}
1043
1044static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1045{
1046 static int printed_version;
1047 struct ata_probe_ent *probe_ent = NULL;
1048 struct ahci_host_priv *hpriv;
1049 unsigned long base;
ea6ba10b 1050 void __iomem *mmio_base;
1da177e4 1051 unsigned int board_idx = (unsigned int) ent->driver_data;
907f4678 1052 int have_msi, pci_dev_busy = 0;
1da177e4
LT		 1053 int rc;
1054
1055 VPRINTK("ENTER\n");
1056
1057 if (!printed_version++)
a9524a76 1058 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1da177e4
LT		 1059
1060 rc = pci_enable_device(pdev);
1061 if (rc)
1062 return rc;
1063
1064 rc = pci_request_regions(pdev, DRV_NAME);
1065 if (rc) {
1066 pci_dev_busy = 1;
1067 goto err_out;
1068 }
1069
907f4678
JG		 1070 if (pci_enable_msi(pdev) == 0)
1071 have_msi = 1;
1072 else {
1073 pci_intx(pdev, 1);
1074 have_msi = 0;
1075 }
1da177e4
LT		 1076
1077 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1078 if (probe_ent == NULL) {
1079 rc = -ENOMEM;
907f4678 1080 goto err_out_msi;
1da177e4
LT		 1081 }
1082
1083 memset(probe_ent, 0, sizeof(*probe_ent));
1084 probe_ent->dev = pci_dev_to_dev(pdev);
1085 INIT_LIST_HEAD(&probe_ent->node);
1086
374b1873 1087 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
1da177e4
LT		 1088 if (mmio_base == NULL) {
1089 rc = -ENOMEM;
1090 goto err_out_free_ent;
1091 }
1092 base = (unsigned long) mmio_base;
1093
1094 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1095 if (!hpriv) {
1096 rc = -ENOMEM;
1097 goto err_out_iounmap;
1098 }
1099 memset(hpriv, 0, sizeof(*hpriv));
1100
1101 probe_ent->sht = ahci_port_info[board_idx].sht;
1102 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1103 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1104 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1105 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1106
1107 probe_ent->irq = pdev->irq;
1108 probe_ent->irq_flags = SA_SHIRQ;
1109 probe_ent->mmio_base = mmio_base;
1110 probe_ent->private_data = hpriv;
1111
4b0060f4
JG		 1112 if (have_msi)
1113 hpriv->flags |= AHCI_FLAG_MSI;
907f4678 1114
bd12097c
JG		 1115 /* JMicron-specific fixup: make sure we're in AHCI mode */
1116 if (pdev->vendor == 0x197b)
1117 pci_write_config_byte(pdev, 0x41, 0xa1);
1118
1da177e4
LT		 1119 /* initialize adapter */
1120 rc = ahci_host_init(probe_ent);
1121 if (rc)
1122 goto err_out_hpriv;
1123
1124 ahci_print_info(probe_ent);
1125
1126 /* FIXME: check ata_device_add return value */
1127 ata_device_add(probe_ent);
1128 kfree(probe_ent);
1129
1130 return 0;
1131
1132err_out_hpriv:
1133 kfree(hpriv);
1134err_out_iounmap:
374b1873 1135 pci_iounmap(pdev, mmio_base);
1da177e4
LT		 1136err_out_free_ent:
1137 kfree(probe_ent);
907f4678
JG		 1138err_out_msi:
1139 if (have_msi)
1140 pci_disable_msi(pdev);
1141 else
1142 pci_intx(pdev, 0);
1da177e4
LT		 1143 pci_release_regions(pdev);
1144err_out:
1145 if (!pci_dev_busy)
1146 pci_disable_device(pdev);
1147 return rc;
1148}
1149
907f4678
JG		 1150static void ahci_remove_one (struct pci_dev *pdev)
1151{
1152 struct device *dev = pci_dev_to_dev(pdev);
1153 struct ata_host_set *host_set = dev_get_drvdata(dev);
1154 struct ahci_host_priv *hpriv = host_set->private_data;
1155 struct ata_port *ap;
1156 unsigned int i;
1157 int have_msi;
1158
1159 for (i = 0; i < host_set->n_ports; i++) {
1160 ap = host_set->ports[i];
1161
1162 scsi_remove_host(ap->host);
1163 }
1164
4b0060f4 1165 have_msi = hpriv->flags & AHCI_FLAG_MSI;
907f4678 1166 free_irq(host_set->irq, host_set);
907f4678
JG		 1167
1168 for (i = 0; i < host_set->n_ports; i++) {
1169 ap = host_set->ports[i];
1170
1171 ata_scsi_release(ap->host);
1172 scsi_host_put(ap->host);
1173 }
1174
e005f01d 1175 kfree(hpriv);
374b1873 1176 pci_iounmap(pdev, host_set->mmio_base);
ead5de99
JG		 1177 kfree(host_set);
1178
907f4678
JG		 1179 if (have_msi)
1180 pci_disable_msi(pdev);
1181 else
1182 pci_intx(pdev, 0);
1183 pci_release_regions(pdev);
907f4678
JG		 1184 pci_disable_device(pdev);
1185 dev_set_drvdata(dev, NULL);
1186}
1da177e4
LT		 1187
1188static int __init ahci_init(void)
1189{
1190 return pci_module_init(&ahci_pci_driver);
1191}
1192
1da177e4
LT		 1193static void __exit ahci_exit(void)
1194{
1195 pci_unregister_driver(&ahci_pci_driver);
1196}
1197
1198
1199MODULE_AUTHOR("Jeff Garzik");
1200MODULE_DESCRIPTION("AHCI SATA low-level driver");
1201MODULE_LICENSE("GPL");
1202MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
6885433c 1203MODULE_VERSION(DRV_VERSION);
1da177e4
LT		 1204
1205module_init(ahci_init);
1206module_exit(ahci_exit);
Linux 6.x block layer and io_uring tree(s)