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[linux-2.6-block.git] / drivers / scsi / ahci.c
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1da177e4
LT		 1/*
2 * ahci.c - AHCI SATA support
3 *
4 * Copyright 2004 Red Hat, Inc.
5 *
6 * The contents of this file are subject to the Open
7 * Software License version 1.1 that can be found at
8 * http://www.opensource.org/licenses/osl-1.1.txt and is included herein
9 * by reference.
10 *
11 * Alternatively, the contents of this file may be used under the terms
12 * of the GNU General Public License version 2 (the "GPL") as distributed
13 * in the kernel source COPYING file, in which case the provisions of
14 * the GPL are applicable instead of the above. If you wish to allow
15 * the use of your version of this file only under the terms of the
16 * GPL and not to allow others to use your version of this file under
17 * the OSL, indicate your decision by deleting the provisions above and
18 * replace them with the notice and other provisions required by the GPL.
19 * If you do not delete the provisions above, a recipient may use your
20 * version of this file under either the OSL or the GPL.
21 *
22 * Version 1.0 of the AHCI specification:
23 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
24 *
25 */
26
27#include <linux/kernel.h>
28#include <linux/module.h>
29#include <linux/pci.h>
30#include <linux/init.h>
31#include <linux/blkdev.h>
32#include <linux/delay.h>
33#include <linux/interrupt.h>
34#include <linux/sched.h>
87507cfd 35#include <linux/dma-mapping.h>
1da177e4
LT		 36#include "scsi.h"
37#include <scsi/scsi_host.h>
38#include <linux/libata.h>
39#include <asm/io.h>
40
41#define DRV_NAME "ahci"
42#define DRV_VERSION "1.00"
43
44
45enum {
46 AHCI_PCI_BAR = 5,
47 AHCI_MAX_SG = 168, /* hardware max is 64K */
48 AHCI_DMA_BOUNDARY = 0xffffffff,
49 AHCI_USE_CLUSTERING = 0,
50 AHCI_CMD_SLOT_SZ = 32 * 32,
51 AHCI_RX_FIS_SZ = 256,
52 AHCI_CMD_TBL_HDR = 0x80,
53 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
54 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
55 AHCI_RX_FIS_SZ,
56 AHCI_IRQ_ON_SG = (1 << 31),
57 AHCI_CMD_ATAPI = (1 << 5),
58 AHCI_CMD_WRITE = (1 << 6),
59
60 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
61
62 board_ahci = 0,
63
64 /* global controller registers */
65 HOST_CAP = 0x00, /* host capabilities */
66 HOST_CTL = 0x04, /* global host control */
67 HOST_IRQ_STAT = 0x08, /* interrupt status */
68 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
69 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
70
71 /* HOST_CTL bits */
72 HOST_RESET = (1 << 0), /* reset controller; self-clear */
73 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
74 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
75
76 /* HOST_CAP bits */
77 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
78
79 /* registers for each SATA port */
80 PORT_LST_ADDR = 0x00, /* command list DMA addr */
81 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
82 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
83 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
84 PORT_IRQ_STAT = 0x10, /* interrupt status */
85 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
86 PORT_CMD = 0x18, /* port command */
87 PORT_TFDATA = 0x20, /* taskfile data */
88 PORT_SIG = 0x24, /* device TF signature */
89 PORT_CMD_ISSUE = 0x38, /* command issue */
90 PORT_SCR = 0x28, /* SATA phy register block */
91 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
92 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
93 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
94 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
95
96 /* PORT_IRQ_{STAT,MASK} bits */
97 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
98 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
99 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
100 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
101 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
102 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
103 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
104 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
105
106 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
107 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
108 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
109 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
110 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
111 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
112 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
113 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
114 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
115
116 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
117 PORT_IRQ_HBUS_ERR |
118 PORT_IRQ_HBUS_DATA_ERR |
119 PORT_IRQ_IF_ERR,
120 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
121 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
122 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
123 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
124 PORT_IRQ_D2H_REG_FIS,
125
126 /* PORT_CMD bits */
127 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
128 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
129 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
130 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
131 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
132 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
133
134 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
135 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
136 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
137};
138
139struct ahci_cmd_hdr {
140 u32 opts;
141 u32 status;
142 u32 tbl_addr;
143 u32 tbl_addr_hi;
144 u32 reserved[4];
145};
146
147struct ahci_sg {
148 u32 addr;
149 u32 addr_hi;
150 u32 reserved;
151 u32 flags_size;
152};
153
154struct ahci_host_priv {
155 unsigned long flags;
907f4678 156 unsigned int have_msi; /* is PCI MSI enabled? */
1da177e4
LT		 157 u32 cap; /* cache of HOST_CAP register */
158 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
159};
160
161struct ahci_port_priv {
162 struct ahci_cmd_hdr *cmd_slot;
163 dma_addr_t cmd_slot_dma;
164 void *cmd_tbl;
165 dma_addr_t cmd_tbl_dma;
166 struct ahci_sg *cmd_tbl_sg;
167 void *rx_fis;
168 dma_addr_t rx_fis_dma;
169};
170
171static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
172static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
173static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
174static int ahci_qc_issue(struct ata_queued_cmd *qc);
175static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
176static void ahci_phy_reset(struct ata_port *ap);
177static void ahci_irq_clear(struct ata_port *ap);
178static void ahci_eng_timeout(struct ata_port *ap);
179static int ahci_port_start(struct ata_port *ap);
180static void ahci_port_stop(struct ata_port *ap);
181static void ahci_host_stop(struct ata_host_set *host_set);
182static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
183static void ahci_qc_prep(struct ata_queued_cmd *qc);
184static u8 ahci_check_status(struct ata_port *ap);
185static u8 ahci_check_err(struct ata_port *ap);
186static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
907f4678 187static void ahci_remove_one (struct pci_dev *pdev);
1da177e4
LT		 188
189static Scsi_Host_Template ahci_sht = {
190 .module = THIS_MODULE,
191 .name = DRV_NAME,
192 .ioctl = ata_scsi_ioctl,
193 .queuecommand = ata_scsi_queuecmd,
194 .eh_strategy_handler = ata_scsi_error,
195 .can_queue = ATA_DEF_QUEUE,
196 .this_id = ATA_SHT_THIS_ID,
197 .sg_tablesize = AHCI_MAX_SG,
198 .max_sectors = ATA_MAX_SECTORS,
199 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
200 .emulated = ATA_SHT_EMULATED,
201 .use_clustering = AHCI_USE_CLUSTERING,
202 .proc_name = DRV_NAME,
203 .dma_boundary = AHCI_DMA_BOUNDARY,
204 .slave_configure = ata_scsi_slave_config,
205 .bios_param = ata_std_bios_param,
206 .ordered_flush = 1,
207};
208
209static struct ata_port_operations ahci_ops = {
210 .port_disable = ata_port_disable,
211
212 .check_status = ahci_check_status,
213 .check_altstatus = ahci_check_status,
214 .check_err = ahci_check_err,
215 .dev_select = ata_noop_dev_select,
216
217 .tf_read = ahci_tf_read,
218
219 .phy_reset = ahci_phy_reset,
220
221 .qc_prep = ahci_qc_prep,
222 .qc_issue = ahci_qc_issue,
223
224 .eng_timeout = ahci_eng_timeout,
225
226 .irq_handler = ahci_interrupt,
227 .irq_clear = ahci_irq_clear,
228
229 .scr_read = ahci_scr_read,
230 .scr_write = ahci_scr_write,
231
232 .port_start = ahci_port_start,
233 .port_stop = ahci_port_stop,
234 .host_stop = ahci_host_stop,
235};
236
237static struct ata_port_info ahci_port_info[] = {
238 /* board_ahci */
239 {
240 .sht = &ahci_sht,
241 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
242 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
243 ATA_FLAG_PIO_DMA,
244 .pio_mask = 0x03, /* pio3-4 */
245 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
246 .port_ops = &ahci_ops,
247 },
248};
249
250static struct pci_device_id ahci_pci_tbl[] = {
251 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
252 board_ahci }, /* ICH6 */
253 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
254 board_ahci }, /* ICH6M */
255 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
256 board_ahci }, /* ICH7 */
257 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
258 board_ahci }, /* ICH7M */
259 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
260 board_ahci }, /* ICH7R */
261 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
262 board_ahci }, /* ULi M5288 */
680d3235
JG		 263 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
264 board_ahci }, /* ESB2 */
265 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
266 board_ahci }, /* ESB2 */
267 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
268 board_ahci }, /* ESB2 */
1da177e4
LT		 269 { } /* terminate list */
270};
271
272
273static struct pci_driver ahci_pci_driver = {
274 .name = DRV_NAME,
275 .id_table = ahci_pci_tbl,
276 .probe = ahci_init_one,
907f4678 277 .remove = ahci_remove_one,
1da177e4
LT		 278};
279
280
281static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
282{
283 return base + 0x100 + (port * 0x80);
284}
285
286static inline void *ahci_port_base (void *base, unsigned int port)
287{
288 return (void *) ahci_port_base_ul((unsigned long)base, port);
289}
290
291static void ahci_host_stop(struct ata_host_set *host_set)
292{
293 struct ahci_host_priv *hpriv = host_set->private_data;
294 kfree(hpriv);
aa8f0dc6
JG		 295
296 ata_host_stop(host_set);
1da177e4
LT		 297}
298
299static int ahci_port_start(struct ata_port *ap)
300{
301 struct device *dev = ap->host_set->dev;
302 struct ahci_host_priv *hpriv = ap->host_set->private_data;
303 struct ahci_port_priv *pp;
304 int rc;
305 void *mem, *mmio = ap->host_set->mmio_base;
306 void *port_mmio = ahci_port_base(mmio, ap->port_no);
307 dma_addr_t mem_dma;
308
309 rc = ata_port_start(ap);
310 if (rc)
311 return rc;
312
313 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
314 if (!pp) {
315 rc = -ENOMEM;
316 goto err_out;
317 }
318 memset(pp, 0, sizeof(*pp));
319
320 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
321 if (!mem) {
322 rc = -ENOMEM;
323 goto err_out_kfree;
324 }
325 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
326
327 /*
328 * First item in chunk of DMA memory: 32-slot command table,
329 * 32 bytes each in size
330 */
331 pp->cmd_slot = mem;
332 pp->cmd_slot_dma = mem_dma;
333
334 mem += AHCI_CMD_SLOT_SZ;
335 mem_dma += AHCI_CMD_SLOT_SZ;
336
337 /*
338 * Second item: Received-FIS area
339 */
340 pp->rx_fis = mem;
341 pp->rx_fis_dma = mem_dma;
342
343 mem += AHCI_RX_FIS_SZ;
344 mem_dma += AHCI_RX_FIS_SZ;
345
346 /*
347 * Third item: data area for storing a single command
348 * and its scatter-gather table
349 */
350 pp->cmd_tbl = mem;
351 pp->cmd_tbl_dma = mem_dma;
352
353 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
354
355 ap->private_data = pp;
356
357 if (hpriv->cap & HOST_CAP_64)
358 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
359 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
360 readl(port_mmio + PORT_LST_ADDR); /* flush */
361
362 if (hpriv->cap & HOST_CAP_64)
363 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
364 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
365 readl(port_mmio + PORT_FIS_ADDR); /* flush */
366
367 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
368 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
369 PORT_CMD_START, port_mmio + PORT_CMD);
370 readl(port_mmio + PORT_CMD); /* flush */
371
372 return 0;
373
374err_out_kfree:
375 kfree(pp);
376err_out:
377 ata_port_stop(ap);
378 return rc;
379}
380
381
382static void ahci_port_stop(struct ata_port *ap)
383{
384 struct device *dev = ap->host_set->dev;
385 struct ahci_port_priv *pp = ap->private_data;
386 void *mmio = ap->host_set->mmio_base;
387 void *port_mmio = ahci_port_base(mmio, ap->port_no);
388 u32 tmp;
389
390 tmp = readl(port_mmio + PORT_CMD);
391 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
392 writel(tmp, port_mmio + PORT_CMD);
393 readl(port_mmio + PORT_CMD); /* flush */
394
395 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
396 * this is slightly incorrect.
397 */
398 msleep(500);
399
400 ap->private_data = NULL;
401 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
402 pp->cmd_slot, pp->cmd_slot_dma);
403 kfree(pp);
404 ata_port_stop(ap);
405}
406
407static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
408{
409 unsigned int sc_reg;
410
411 switch (sc_reg_in) {
412 case SCR_STATUS: sc_reg = 0; break;
413 case SCR_CONTROL: sc_reg = 1; break;
414 case SCR_ERROR: sc_reg = 2; break;
415 case SCR_ACTIVE: sc_reg = 3; break;
416 default:
417 return 0xffffffffU;
418 }
419
420 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
421}
422
423
424static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
425 u32 val)
426{
427 unsigned int sc_reg;
428
429 switch (sc_reg_in) {
430 case SCR_STATUS: sc_reg = 0; break;
431 case SCR_CONTROL: sc_reg = 1; break;
432 case SCR_ERROR: sc_reg = 2; break;
433 case SCR_ACTIVE: sc_reg = 3; break;
434 default:
435 return;
436 }
437
438 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
439}
440
441static void ahci_phy_reset(struct ata_port *ap)
442{
443 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
444 struct ata_taskfile tf;
445 struct ata_device *dev = &ap->device[0];
446 u32 tmp;
447
448 __sata_phy_reset(ap);
449
450 if (ap->flags & ATA_FLAG_PORT_DISABLED)
451 return;
452
453 tmp = readl(port_mmio + PORT_SIG);
454 tf.lbah = (tmp >> 24) & 0xff;
455 tf.lbam = (tmp >> 16) & 0xff;
456 tf.lbal = (tmp >> 8) & 0xff;
457 tf.nsect = (tmp) & 0xff;
458
459 dev->class = ata_dev_classify(&tf);
460 if (!ata_dev_present(dev))
461 ata_port_disable(ap);
462}
463
464static u8 ahci_check_status(struct ata_port *ap)
465{
466 void *mmio = (void *) ap->ioaddr.cmd_addr;
467
468 return readl(mmio + PORT_TFDATA) & 0xFF;
469}
470
471static u8 ahci_check_err(struct ata_port *ap)
472{
473 void *mmio = (void *) ap->ioaddr.cmd_addr;
474
475 return (readl(mmio + PORT_TFDATA) >> 8) & 0xFF;
476}
477
478static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
479{
480 struct ahci_port_priv *pp = ap->private_data;
481 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
482
483 ata_tf_from_fis(d2h_fis, tf);
484}
485
486static void ahci_fill_sg(struct ata_queued_cmd *qc)
487{
488 struct ahci_port_priv *pp = qc->ap->private_data;
489 unsigned int i;
490
491 VPRINTK("ENTER\n");
492
493 /*
494 * Next, the S/G list.
495 */
496 for (i = 0; i < qc->n_elem; i++) {
497 u32 sg_len;
498 dma_addr_t addr;
499
500 addr = sg_dma_address(&qc->sg[i]);
501 sg_len = sg_dma_len(&qc->sg[i]);
502
503 pp->cmd_tbl_sg[i].addr = cpu_to_le32(addr & 0xffffffff);
504 pp->cmd_tbl_sg[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
505 pp->cmd_tbl_sg[i].flags_size = cpu_to_le32(sg_len - 1);
506 }
507}
508
509static void ahci_qc_prep(struct ata_queued_cmd *qc)
510{
511 struct ahci_port_priv *pp = qc->ap->private_data;
512 u32 opts;
513 const u32 cmd_fis_len = 5; /* five dwords */
514
515 /*
516 * Fill in command slot information (currently only one slot,
517 * slot 0, is currently since we don't do queueing)
518 */
519
520 opts = (qc->n_elem << 16) | cmd_fis_len;
521 if (qc->tf.flags & ATA_TFLAG_WRITE)
522 opts |= AHCI_CMD_WRITE;
523
524 switch (qc->tf.protocol) {
525 case ATA_PROT_ATAPI:
526 case ATA_PROT_ATAPI_NODATA:
527 case ATA_PROT_ATAPI_DMA:
528 opts |= AHCI_CMD_ATAPI;
529 break;
530
531 default:
532 /* do nothing */
533 break;
534 }
535
536 pp->cmd_slot[0].opts = cpu_to_le32(opts);
537 pp->cmd_slot[0].status = 0;
538 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
539 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
540
541 /*
542 * Fill in command table information. First, the header,
543 * a SATA Register - Host to Device command FIS.
544 */
545 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
546
547 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
548 return;
549
550 ahci_fill_sg(qc);
551}
552
553static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
554{
555 void *mmio = ap->host_set->mmio_base;
556 void *port_mmio = ahci_port_base(mmio, ap->port_no);
557 u32 tmp;
558 int work;
559
560 /* stop DMA */
561 tmp = readl(port_mmio + PORT_CMD);
562 tmp &= ~PORT_CMD_START;
563 writel(tmp, port_mmio + PORT_CMD);
564
565 /* wait for engine to stop. TODO: this could be
566 * as long as 500 msec
567 */
568 work = 1000;
569 while (work-- > 0) {
570 tmp = readl(port_mmio + PORT_CMD);
571 if ((tmp & PORT_CMD_LIST_ON) == 0)
572 break;
573 udelay(10);
574 }
575
576 /* clear SATA phy error, if any */
577 tmp = readl(port_mmio + PORT_SCR_ERR);
578 writel(tmp, port_mmio + PORT_SCR_ERR);
579
580 /* if DRQ/BSY is set, device needs to be reset.
581 * if so, issue COMRESET
582 */
583 tmp = readl(port_mmio + PORT_TFDATA);
584 if (tmp & (ATA_BUSY | ATA_DRQ)) {
585 writel(0x301, port_mmio + PORT_SCR_CTL);
586 readl(port_mmio + PORT_SCR_CTL); /* flush */
587 udelay(10);
588 writel(0x300, port_mmio + PORT_SCR_CTL);
589 readl(port_mmio + PORT_SCR_CTL); /* flush */
590 }
591
592 /* re-start DMA */
593 tmp = readl(port_mmio + PORT_CMD);
594 tmp |= PORT_CMD_START;
595 writel(tmp, port_mmio + PORT_CMD);
596 readl(port_mmio + PORT_CMD); /* flush */
597
598 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
599}
600
601static void ahci_eng_timeout(struct ata_port *ap)
602{
603 void *mmio = ap->host_set->mmio_base;
604 void *port_mmio = ahci_port_base(mmio, ap->port_no);
605 struct ata_queued_cmd *qc;
606
607 DPRINTK("ENTER\n");
608
609 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
610
611 qc = ata_qc_from_tag(ap, ap->active_tag);
612 if (!qc) {
613 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
614 ap->id);
615 } else {
616 /* hack alert! We cannot use the supplied completion
617 * function from inside the ->eh_strategy_handler() thread.
618 * libata is the only user of ->eh_strategy_handler() in
619 * any kernel, so the default scsi_done() assumes it is
620 * not being called from the SCSI EH.
621 */
622 qc->scsidone = scsi_finish_command;
623 ata_qc_complete(qc, ATA_ERR);
624 }
625
626}
627
628static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
629{
630 void *mmio = ap->host_set->mmio_base;
631 void *port_mmio = ahci_port_base(mmio, ap->port_no);
632 u32 status, serr, ci;
633
634 serr = readl(port_mmio + PORT_SCR_ERR);
635 writel(serr, port_mmio + PORT_SCR_ERR);
636
637 status = readl(port_mmio + PORT_IRQ_STAT);
638 writel(status, port_mmio + PORT_IRQ_STAT);
639
640 ci = readl(port_mmio + PORT_CMD_ISSUE);
641 if (likely((ci & 0x1) == 0)) {
642 if (qc) {
643 ata_qc_complete(qc, 0);
644 qc = NULL;
645 }
646 }
647
648 if (status & PORT_IRQ_FATAL) {
649 ahci_intr_error(ap, status);
650 if (qc)
651 ata_qc_complete(qc, ATA_ERR);
652 }
653
654 return 1;
655}
656
657static void ahci_irq_clear(struct ata_port *ap)
658{
659 /* TODO */
660}
661
662static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
663{
664 struct ata_host_set *host_set = dev_instance;
665 struct ahci_host_priv *hpriv;
666 unsigned int i, handled = 0;
667 void *mmio;
668 u32 irq_stat, irq_ack = 0;
669
670 VPRINTK("ENTER\n");
671
672 hpriv = host_set->private_data;
673 mmio = host_set->mmio_base;
674
675 /* sigh. 0xffffffff is a valid return from h/w */
676 irq_stat = readl(mmio + HOST_IRQ_STAT);
677 irq_stat &= hpriv->port_map;
678 if (!irq_stat)
679 return IRQ_NONE;
680
681 spin_lock(&host_set->lock);
682
683 for (i = 0; i < host_set->n_ports; i++) {
684 struct ata_port *ap;
685 u32 tmp;
686
687 VPRINTK("port %u\n", i);
688 ap = host_set->ports[i];
689 tmp = irq_stat & (1 << i);
690 if (tmp && ap) {
691 struct ata_queued_cmd *qc;
692 qc = ata_qc_from_tag(ap, ap->active_tag);
693 if (ahci_host_intr(ap, qc))
694 irq_ack |= (1 << i);
695 }
696 }
697
698 if (irq_ack) {
699 writel(irq_ack, mmio + HOST_IRQ_STAT);
700 handled = 1;
701 }
702
703 spin_unlock(&host_set->lock);
704
705 VPRINTK("EXIT\n");
706
707 return IRQ_RETVAL(handled);
708}
709
710static int ahci_qc_issue(struct ata_queued_cmd *qc)
711{
712 struct ata_port *ap = qc->ap;
713 void *port_mmio = (void *) ap->ioaddr.cmd_addr;
714
715 writel(1, port_mmio + PORT_SCR_ACT);
716 readl(port_mmio + PORT_SCR_ACT); /* flush */
717
718 writel(1, port_mmio + PORT_CMD_ISSUE);
719 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
720
721 return 0;
722}
723
724static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
725 unsigned int port_idx)
726{
727 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
728 base = ahci_port_base_ul(base, port_idx);
729 VPRINTK("base now==0x%lx\n", base);
730
731 port->cmd_addr = base;
732 port->scr_addr = base + PORT_SCR;
733
734 VPRINTK("EXIT\n");
735}
736
737static int ahci_host_init(struct ata_probe_ent *probe_ent)
738{
739 struct ahci_host_priv *hpriv = probe_ent->private_data;
740 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
741 void __iomem *mmio = probe_ent->mmio_base;
742 u32 tmp, cap_save;
743 u16 tmp16;
744 unsigned int i, j, using_dac;
745 int rc;
746 void __iomem *port_mmio;
747
748 cap_save = readl(mmio + HOST_CAP);
749 cap_save &= ( (1<<28) | (1<<17) );
750 cap_save |= (1 << 27);
751
752 /* global controller reset */
753 tmp = readl(mmio + HOST_CTL);
754 if ((tmp & HOST_RESET) == 0) {
755 writel(tmp | HOST_RESET, mmio + HOST_CTL);
756 readl(mmio + HOST_CTL); /* flush */
757 }
758
759 /* reset must complete within 1 second, or
760 * the hardware should be considered fried.
761 */
762 ssleep(1);
763
764 tmp = readl(mmio + HOST_CTL);
765 if (tmp & HOST_RESET) {
766 printk(KERN_ERR DRV_NAME "(%s): controller reset failed (0x%x)\n",
767 pci_name(pdev), tmp);
768 return -EIO;
769 }
770
771 writel(HOST_AHCI_EN, mmio + HOST_CTL);
772 (void) readl(mmio + HOST_CTL); /* flush */
773 writel(cap_save, mmio + HOST_CAP);
774 writel(0xf, mmio + HOST_PORTS_IMPL);
775 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
776
777 pci_read_config_word(pdev, 0x92, &tmp16);
778 tmp16 |= 0xf;
779 pci_write_config_word(pdev, 0x92, tmp16);
780
781 hpriv->cap = readl(mmio + HOST_CAP);
782 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
783 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
784
785 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
786 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
787
788 using_dac = hpriv->cap & HOST_CAP_64;
789 if (using_dac &&
790 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
791 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
792 if (rc) {
793 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
794 if (rc) {
795 printk(KERN_ERR DRV_NAME "(%s): 64-bit DMA enable failed\n",
796 pci_name(pdev));
797 return rc;
798 }
799 }
800
801 hpriv->flags |= HOST_CAP_64;
802 } else {
803 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
804 if (rc) {
805 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
806 pci_name(pdev));
807 return rc;
808 }
809 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
810 if (rc) {
811 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
812 pci_name(pdev));
813 return rc;
814 }
815 }
816
817 for (i = 0; i < probe_ent->n_ports; i++) {
818#if 0 /* BIOSen initialize this incorrectly */
819 if (!(hpriv->port_map & (1 << i)))
820 continue;
821#endif
822
823 port_mmio = ahci_port_base(mmio, i);
824 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
825
826 ahci_setup_port(&probe_ent->port[i],
827 (unsigned long) mmio, i);
828
829 /* make sure port is not active */
830 tmp = readl(port_mmio + PORT_CMD);
831 VPRINTK("PORT_CMD 0x%x\n", tmp);
832 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
833 PORT_CMD_FIS_RX | PORT_CMD_START)) {
834 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
835 PORT_CMD_FIS_RX | PORT_CMD_START);
836 writel(tmp, port_mmio + PORT_CMD);
837 readl(port_mmio + PORT_CMD); /* flush */
838
839 /* spec says 500 msecs for each bit, so
840 * this is slightly incorrect.
841 */
842 msleep(500);
843 }
844
845 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
846
847 j = 0;
848 while (j < 100) {
849 msleep(10);
850 tmp = readl(port_mmio + PORT_SCR_STAT);
851 if ((tmp & 0xf) == 0x3)
852 break;
853 j++;
854 }
855
856 tmp = readl(port_mmio + PORT_SCR_ERR);
857 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
858 writel(tmp, port_mmio + PORT_SCR_ERR);
859
860 /* ack any pending irq events for this port */
861 tmp = readl(port_mmio + PORT_IRQ_STAT);
862 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
863 if (tmp)
864 writel(tmp, port_mmio + PORT_IRQ_STAT);
865
866 writel(1 << i, mmio + HOST_IRQ_STAT);
867
868 /* set irq mask (enables interrupts) */
869 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
870 }
871
872 tmp = readl(mmio + HOST_CTL);
873 VPRINTK("HOST_CTL 0x%x\n", tmp);
874 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
875 tmp = readl(mmio + HOST_CTL);
876 VPRINTK("HOST_CTL 0x%x\n", tmp);
877
878 pci_set_master(pdev);
879
880 return 0;
881}
882
883/* move to PCI layer, integrate w/ MSI stuff */
907f4678 884static void pci_intx(struct pci_dev *pdev, int enable)
1da177e4 885{
907f4678 886 u16 pci_command, new;
1da177e4
LT		 887
888 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
907f4678
JG		 889
890 if (enable)
891 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
892 else
893 new = pci_command | PCI_COMMAND_INTX_DISABLE;
894
895 if (new != pci_command)
1da177e4 896 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
1da177e4
LT		 897}
898
899static void ahci_print_info(struct ata_probe_ent *probe_ent)
900{
901 struct ahci_host_priv *hpriv = probe_ent->private_data;
902 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
903 void *mmio = probe_ent->mmio_base;
904 u32 vers, cap, impl, speed;
905 const char *speed_s;
906 u16 cc;
907 const char *scc_s;
908
909 vers = readl(mmio + HOST_VERSION);
910 cap = hpriv->cap;
911 impl = hpriv->port_map;
912
913 speed = (cap >> 20) & 0xf;
914 if (speed == 1)
915 speed_s = "1.5";
916 else if (speed == 2)
917 speed_s = "3";
918 else
919 speed_s = "?";
920
921 pci_read_config_word(pdev, 0x0a, &cc);
922 if (cc == 0x0101)
923 scc_s = "IDE";
924 else if (cc == 0x0106)
925 scc_s = "SATA";
926 else if (cc == 0x0104)
927 scc_s = "RAID";
928 else
929 scc_s = "unknown";
930
931 printk(KERN_INFO DRV_NAME "(%s) AHCI %02x%02x.%02x%02x "
932 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
933 ,
934 pci_name(pdev),
935
936 (vers >> 24) & 0xff,
937 (vers >> 16) & 0xff,
938 (vers >> 8) & 0xff,
939 vers & 0xff,
940
941 ((cap >> 8) & 0x1f) + 1,
942 (cap & 0x1f) + 1,
943 speed_s,
944 impl,
945 scc_s);
946
947 printk(KERN_INFO DRV_NAME "(%s) flags: "
948 "%s%s%s%s%s%s"
949 "%s%s%s%s%s%s%s\n"
950 ,
951 pci_name(pdev),
952
953 cap & (1 << 31) ? "64bit " : "",
954 cap & (1 << 30) ? "ncq " : "",
955 cap & (1 << 28) ? "ilck " : "",
956 cap & (1 << 27) ? "stag " : "",
957 cap & (1 << 26) ? "pm " : "",
958 cap & (1 << 25) ? "led " : "",
959
960 cap & (1 << 24) ? "clo " : "",
961 cap & (1 << 19) ? "nz " : "",
962 cap & (1 << 18) ? "only " : "",
963 cap & (1 << 17) ? "pmp " : "",
964 cap & (1 << 15) ? "pio " : "",
965 cap & (1 << 14) ? "slum " : "",
966 cap & (1 << 13) ? "part " : ""
967 );
968}
969
970static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
971{
972 static int printed_version;
973 struct ata_probe_ent *probe_ent = NULL;
974 struct ahci_host_priv *hpriv;
975 unsigned long base;
976 void *mmio_base;
977 unsigned int board_idx = (unsigned int) ent->driver_data;
907f4678 978 int have_msi, pci_dev_busy = 0;
1da177e4
LT		 979 int rc;
980
981 VPRINTK("ENTER\n");
982
983 if (!printed_version++)
984 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
985
986 rc = pci_enable_device(pdev);
987 if (rc)
988 return rc;
989
990 rc = pci_request_regions(pdev, DRV_NAME);
991 if (rc) {
992 pci_dev_busy = 1;
993 goto err_out;
994 }
995
907f4678
JG		 996 if (pci_enable_msi(pdev) == 0)
997 have_msi = 1;
998 else {
999 pci_intx(pdev, 1);
1000 have_msi = 0;
1001 }
1da177e4
LT		 1002
1003 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
1004 if (probe_ent == NULL) {
1005 rc = -ENOMEM;
907f4678 1006 goto err_out_msi;
1da177e4
LT		 1007 }
1008
1009 memset(probe_ent, 0, sizeof(*probe_ent));
1010 probe_ent->dev = pci_dev_to_dev(pdev);
1011 INIT_LIST_HEAD(&probe_ent->node);
1012
1013 mmio_base = ioremap(pci_resource_start(pdev, AHCI_PCI_BAR),
1014 pci_resource_len(pdev, AHCI_PCI_BAR));
1015 if (mmio_base == NULL) {
1016 rc = -ENOMEM;
1017 goto err_out_free_ent;
1018 }
1019 base = (unsigned long) mmio_base;
1020
1021 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1022 if (!hpriv) {
1023 rc = -ENOMEM;
1024 goto err_out_iounmap;
1025 }
1026 memset(hpriv, 0, sizeof(*hpriv));
1027
1028 probe_ent->sht = ahci_port_info[board_idx].sht;
1029 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1030 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1031 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1032 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1033
1034 probe_ent->irq = pdev->irq;
1035 probe_ent->irq_flags = SA_SHIRQ;
1036 probe_ent->mmio_base = mmio_base;
1037 probe_ent->private_data = hpriv;
1038
907f4678
JG		 1039 hpriv->have_msi = have_msi;
1040
1da177e4
LT		 1041 /* initialize adapter */
1042 rc = ahci_host_init(probe_ent);
1043 if (rc)
1044 goto err_out_hpriv;
1045
1046 ahci_print_info(probe_ent);
1047
1048 /* FIXME: check ata_device_add return value */
1049 ata_device_add(probe_ent);
1050 kfree(probe_ent);
1051
1052 return 0;
1053
1054err_out_hpriv:
1055 kfree(hpriv);
1056err_out_iounmap:
1057 iounmap(mmio_base);
1058err_out_free_ent:
1059 kfree(probe_ent);
907f4678
JG		 1060err_out_msi:
1061 if (have_msi)
1062 pci_disable_msi(pdev);
1063 else
1064 pci_intx(pdev, 0);
1da177e4
LT		 1065 pci_release_regions(pdev);
1066err_out:
1067 if (!pci_dev_busy)
1068 pci_disable_device(pdev);
1069 return rc;
1070}
1071
907f4678
JG		 1072static void ahci_remove_one (struct pci_dev *pdev)
1073{
1074 struct device *dev = pci_dev_to_dev(pdev);
1075 struct ata_host_set *host_set = dev_get_drvdata(dev);
1076 struct ahci_host_priv *hpriv = host_set->private_data;
1077 struct ata_port *ap;
1078 unsigned int i;
1079 int have_msi;
1080
1081 for (i = 0; i < host_set->n_ports; i++) {
1082 ap = host_set->ports[i];
1083
1084 scsi_remove_host(ap->host);
1085 }
1086
1087 have_msi = hpriv->have_msi;
1088 free_irq(host_set->irq, host_set);
1089 host_set->ops->host_stop(host_set);
1090 iounmap(host_set->mmio_base);
1091
1092 for (i = 0; i < host_set->n_ports; i++) {
1093 ap = host_set->ports[i];
1094
1095 ata_scsi_release(ap->host);
1096 scsi_host_put(ap->host);
1097 }
1098
1099 if (have_msi)
1100 pci_disable_msi(pdev);
1101 else
1102 pci_intx(pdev, 0);
1103 pci_release_regions(pdev);
1104 kfree(host_set);
1105 pci_disable_device(pdev);
1106 dev_set_drvdata(dev, NULL);
1107}
1da177e4
LT		 1108
1109static int __init ahci_init(void)
1110{
1111 return pci_module_init(&ahci_pci_driver);
1112}
1113
1114
1115static void __exit ahci_exit(void)
1116{
1117 pci_unregister_driver(&ahci_pci_driver);
1118}
1119
1120
1121MODULE_AUTHOR("Jeff Garzik");
1122MODULE_DESCRIPTION("AHCI SATA low-level driver");
1123MODULE_LICENSE("GPL");
1124MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1125
1126module_init(ahci_init);
1127module_exit(ahci_exit);
Linux 6.x block layer and io_uring tree(s)