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advansys: Remove ASC_SCSI_REQ_Q
[linux-block.git] / drivers / scsi / advansys.c
CommitLineData
01fbfe0b 1#define DRV_NAME "advansys"
8c6af9e1 2#define ASC_VERSION "3.4" /* AdvanSys Driver Version */
1da177e4
LT		 3
4/*
5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
6 *
7 * Copyright (c) 1995-2000 Advanced System Products, Inc.
8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
8c6af9e1 9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
1da177e4
LT		 10 * All Rights Reserved.
11 *
8c6af9e1
MW		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18/*
1da177e4
LT		 19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
20 * changed its name to ConnectCom Solutions, Inc.
8c6af9e1 21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
1da177e4
LT		 22 */
23
1da177e4 24#include <linux/module.h>
1da177e4
LT		 25#include <linux/string.h>
26#include <linux/kernel.h>
27#include <linux/types.h>
28#include <linux/ioport.h>
29#include <linux/interrupt.h>
30#include <linux/delay.h>
31#include <linux/slab.h>
32#include <linux/mm.h>
33#include <linux/proc_fs.h>
34#include <linux/init.h>
35#include <linux/blkdev.h>
c304ec94 36#include <linux/isa.h>
b09e05a7 37#include <linux/eisa.h>
8c6af9e1 38#include <linux/pci.h>
1da177e4
LT		 39#include <linux/spinlock.h>
40#include <linux/dma-mapping.h>
989bb5f5 41#include <linux/firmware.h>
1da177e4
LT		 42
43#include <asm/io.h>
1da177e4
LT		 44#include <asm/dma.h>
45
8c6af9e1
MW		 46#include <scsi/scsi_cmnd.h>
47#include <scsi/scsi_device.h>
48#include <scsi/scsi_tcq.h>
49#include <scsi/scsi.h>
50#include <scsi/scsi_host.h>
51
4bd6d7f3 52/* FIXME:
1da177e4 53 *
4bd6d7f3
MW		 54 * 1. Although all of the necessary command mapping places have the
55 * appropriate dma_map.. APIs, the driver still processes its internal
56 * queue using bus_to_virt() and virt_to_bus() which are illegal under
57 * the API. The entire queue processing structure will need to be
58 * altered to fix this.
59 * 2. Need to add memory mapping workaround. Test the memory mapping.
60 * If it doesn't work revert to I/O port access. Can a test be done
61 * safely?
62 * 3. Handle an interrupt not working. Keep an interrupt counter in
63 * the interrupt handler. In the timeout function if the interrupt
64 * has not occurred then print a message and run in polled mode.
65 * 4. Need to add support for target mode commands, cf. CAM XPT.
66 * 5. check DMA mapping functions for failure
349d2c44
MW		 67 * 6. Use scsi_transport_spi
68 * 7. advansys_info is not safe against multiple simultaneous callers
9d0e96eb 69 * 8. Add module_param to override ISA/VLB ioport array
1da177e4
LT		 70 */
71#warning this driver is still not properly converted to the DMA API
72
1da177e4
LT		 73/* Enable driver /proc statistics. */
74#define ADVANSYS_STATS
75
76/* Enable driver tracing. */
b352f923 77#undef ADVANSYS_DEBUG
1da177e4 78
1da177e4
LT		 79typedef unsigned char uchar;
80
1da177e4 81#define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0)
1da177e4 82
2672ea86
DJ		 83#define PCI_VENDOR_ID_ASP 0x10cd
84#define PCI_DEVICE_ID_ASP_1200A 0x1100
85#define PCI_DEVICE_ID_ASP_ABP940 0x1200
86#define PCI_DEVICE_ID_ASP_ABP940U 0x1300
87#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300
88#define PCI_DEVICE_ID_38C0800_REV1 0x2500
89#define PCI_DEVICE_ID_38C1600_REV1 0x2700
90
1da177e4
LT		 91/*
92 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists.
93 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ()
94 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the
95 * SRB structure.
96 */
97#define CC_VERY_LONG_SG_LIST 0
98#define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr)
99
9d511a4b 100#define PortAddr unsigned int /* port address size */
1da177e4
LT		 101#define inp(port) inb(port)
102#define outp(port, byte) outb((byte), (port))
103
104#define inpw(port) inw(port)
105#define outpw(port, word) outw((word), (port))
106
107#define ASC_MAX_SG_QUEUE 7
108#define ASC_MAX_SG_LIST 255
109
110#define ASC_CS_TYPE unsigned short
111
112#define ASC_IS_ISA (0x0001)
113#define ASC_IS_ISAPNP (0x0081)
114#define ASC_IS_EISA (0x0002)
115#define ASC_IS_PCI (0x0004)
116#define ASC_IS_PCI_ULTRA (0x0104)
117#define ASC_IS_PCMCIA (0x0008)
118#define ASC_IS_MCA (0x0020)
119#define ASC_IS_VL (0x0040)
1da177e4
LT		 120#define ASC_IS_WIDESCSI_16 (0x0100)
121#define ASC_IS_WIDESCSI_32 (0x0200)
122#define ASC_IS_BIG_ENDIAN (0x8000)
95c9f162 123
1da177e4
LT		 124#define ASC_CHIP_MIN_VER_VL (0x01)
125#define ASC_CHIP_MAX_VER_VL (0x07)
126#define ASC_CHIP_MIN_VER_PCI (0x09)
127#define ASC_CHIP_MAX_VER_PCI (0x0F)
128#define ASC_CHIP_VER_PCI_BIT (0x08)
129#define ASC_CHIP_MIN_VER_ISA (0x11)
130#define ASC_CHIP_MIN_VER_ISA_PNP (0x21)
131#define ASC_CHIP_MAX_VER_ISA (0x27)
132#define ASC_CHIP_VER_ISA_BIT (0x30)
133#define ASC_CHIP_VER_ISAPNP_BIT (0x20)
134#define ASC_CHIP_VER_ASYN_BUG (0x21)
135#define ASC_CHIP_VER_PCI 0x08
136#define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02)
137#define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03)
138#define ASC_CHIP_MIN_VER_EISA (0x41)
139#define ASC_CHIP_MAX_VER_EISA (0x47)
140#define ASC_CHIP_VER_EISA_BIT (0x40)
141#define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
1da177e4 142#define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL)
1da177e4 143#define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL)
1da177e4 144#define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL)
1da177e4
LT		 145
146#define ASC_SCSI_ID_BITS 3
147#define ASC_SCSI_TIX_TYPE uchar
148#define ASC_ALL_DEVICE_BIT_SET 0xFF
149#define ASC_SCSI_BIT_ID_TYPE uchar
150#define ASC_MAX_TID 7
151#define ASC_MAX_LUN 7
152#define ASC_SCSI_WIDTH_BIT_SET 0xFF
153#define ASC_MAX_SENSE_LEN 32
154#define ASC_MIN_SENSE_LEN 14
1da177e4
LT		 155#define ASC_SCSI_RESET_HOLD_TIME_US 60
156
f05ec594
MW		 157/*
158 * Narrow boards only support 12-byte commands, while wide boards
159 * extend to 16-byte commands.
160 */
161#define ASC_MAX_CDB_LEN 12
162#define ADV_MAX_CDB_LEN 16
163
1da177e4 164#define MS_SDTR_LEN 0x03
1da177e4 165#define MS_WDTR_LEN 0x02
1da177e4
LT		 166
167#define ASC_SG_LIST_PER_Q 7
168#define QS_FREE 0x00
169#define QS_READY 0x01
170#define QS_DISC1 0x02
171#define QS_DISC2 0x04
172#define QS_BUSY 0x08
173#define QS_ABORTED 0x40
174#define QS_DONE 0x80
175#define QC_NO_CALLBACK 0x01
176#define QC_SG_SWAP_QUEUE 0x02
177#define QC_SG_HEAD 0x04
178#define QC_DATA_IN 0x08
179#define QC_DATA_OUT 0x10
180#define QC_URGENT 0x20
181#define QC_MSG_OUT 0x40
182#define QC_REQ_SENSE 0x80
183#define QCSG_SG_XFER_LIST 0x02
184#define QCSG_SG_XFER_MORE 0x04
185#define QCSG_SG_XFER_END 0x08
186#define QD_IN_PROGRESS 0x00
187#define QD_NO_ERROR 0x01
188#define QD_ABORTED_BY_HOST 0x02
189#define QD_WITH_ERROR 0x04
190#define QD_INVALID_REQUEST 0x80
191#define QD_INVALID_HOST_NUM 0x81
192#define QD_INVALID_DEVICE 0x82
193#define QD_ERR_INTERNAL 0xFF
194#define QHSTA_NO_ERROR 0x00
195#define QHSTA_M_SEL_TIMEOUT 0x11
196#define QHSTA_M_DATA_OVER_RUN 0x12
197#define QHSTA_M_DATA_UNDER_RUN 0x12
198#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
199#define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14
200#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
201#define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22
202#define QHSTA_D_HOST_ABORT_FAILED 0x23
203#define QHSTA_D_EXE_SCSI_Q_FAILED 0x24
204#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
205#define QHSTA_D_ASPI_NO_BUF_POOL 0x26
206#define QHSTA_M_WTM_TIMEOUT 0x41
207#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
208#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
209#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
210#define QHSTA_M_TARGET_STATUS_BUSY 0x45
211#define QHSTA_M_BAD_TAG_CODE 0x46
212#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47
213#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
214#define QHSTA_D_LRAM_CMP_ERROR 0x81
215#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
216#define ASC_FLAG_SCSIQ_REQ 0x01
217#define ASC_FLAG_BIOS_SCSIQ_REQ 0x02
218#define ASC_FLAG_BIOS_ASYNC_IO 0x04
219#define ASC_FLAG_SRB_LINEAR_ADDR 0x08
220#define ASC_FLAG_WIN16 0x10
221#define ASC_FLAG_WIN32 0x20
222#define ASC_FLAG_ISA_OVER_16MB 0x40
223#define ASC_FLAG_DOS_VM_CALLBACK 0x80
224#define ASC_TAG_FLAG_EXTRA_BYTES 0x10
225#define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04
226#define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08
227#define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
228#define ASC_SCSIQ_CPY_BEG 4
229#define ASC_SCSIQ_SGHD_CPY_BEG 2
230#define ASC_SCSIQ_B_FWD 0
231#define ASC_SCSIQ_B_BWD 1
232#define ASC_SCSIQ_B_STATUS 2
233#define ASC_SCSIQ_B_QNO 3
234#define ASC_SCSIQ_B_CNTL 4
235#define ASC_SCSIQ_B_SG_QUEUE_CNT 5
236#define ASC_SCSIQ_D_DATA_ADDR 8
237#define ASC_SCSIQ_D_DATA_CNT 12
238#define ASC_SCSIQ_B_SENSE_LEN 20
239#define ASC_SCSIQ_DONE_INFO_BEG 22
240#define ASC_SCSIQ_D_SRBPTR 22
241#define ASC_SCSIQ_B_TARGET_IX 26
242#define ASC_SCSIQ_B_CDB_LEN 28
243#define ASC_SCSIQ_B_TAG_CODE 29
244#define ASC_SCSIQ_W_VM_ID 30
245#define ASC_SCSIQ_DONE_STATUS 32
246#define ASC_SCSIQ_HOST_STATUS 33
247#define ASC_SCSIQ_SCSI_STATUS 34
248#define ASC_SCSIQ_CDB_BEG 36
249#define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
250#define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60
251#define ASC_SCSIQ_B_FIRST_SG_WK_QP 48
252#define ASC_SCSIQ_B_SG_WK_QP 49
253#define ASC_SCSIQ_B_SG_WK_IX 50
254#define ASC_SCSIQ_W_ALT_DC1 52
255#define ASC_SCSIQ_B_LIST_CNT 6
256#define ASC_SCSIQ_B_CUR_LIST_CNT 7
257#define ASC_SGQ_B_SG_CNTL 4
258#define ASC_SGQ_B_SG_HEAD_QP 5
259#define ASC_SGQ_B_SG_LIST_CNT 6
260#define ASC_SGQ_B_SG_CUR_LIST_CNT 7
261#define ASC_SGQ_LIST_BEG 8
262#define ASC_DEF_SCSI1_QNG 4
263#define ASC_MAX_SCSI1_QNG 4
264#define ASC_DEF_SCSI2_QNG 16
265#define ASC_MAX_SCSI2_QNG 32
266#define ASC_TAG_CODE_MASK 0x23
267#define ASC_STOP_REQ_RISC_STOP 0x01
268#define ASC_STOP_ACK_RISC_STOP 0x03
269#define ASC_STOP_CLEAN_UP_BUSY_Q 0x10
270#define ASC_STOP_CLEAN_UP_DISC_Q 0x20
271#define ASC_STOP_HOST_REQ_RISC_HALT 0x40
272#define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
273#define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
274#define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID))
275#define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID)
276#define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID)
277#define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
278#define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6))
279
280typedef struct asc_scsiq_1 {
27c868c2
MW		 281 uchar status;
282 uchar q_no;
283 uchar cntl;
284 uchar sg_queue_cnt;
285 uchar target_id;
286 uchar target_lun;
95cfab6c
HR		 287 __le32 data_addr;
288 __le32 data_cnt;
289 __le32 sense_addr;
27c868c2
MW		 290 uchar sense_len;
291 uchar extra_bytes;
1da177e4
LT		 292} ASC_SCSIQ_1;
293
294typedef struct asc_scsiq_2 {
9c17c62a 295 u32 srb_tag;
27c868c2
MW		 296 uchar target_ix;
297 uchar flag;
298 uchar cdb_len;
299 uchar tag_code;
300 ushort vm_id;
1da177e4
LT		 301} ASC_SCSIQ_2;
302
303typedef struct asc_scsiq_3 {
27c868c2
MW		 304 uchar done_stat;
305 uchar host_stat;
306 uchar scsi_stat;
307 uchar scsi_msg;
1da177e4
LT		 308} ASC_SCSIQ_3;
309
310typedef struct asc_scsiq_4 {
27c868c2
MW		 311 uchar cdb[ASC_MAX_CDB_LEN];
312 uchar y_first_sg_list_qp;
313 uchar y_working_sg_qp;
314 uchar y_working_sg_ix;
315 uchar y_res;
316 ushort x_req_count;
317 ushort x_reconnect_rtn;
95cfab6c
HR		 318 __le32 x_saved_data_addr;
319 __le32 x_saved_data_cnt;
1da177e4
LT		 320} ASC_SCSIQ_4;
321
322typedef struct asc_q_done_info {
27c868c2
MW		 323 ASC_SCSIQ_2 d2;
324 ASC_SCSIQ_3 d3;
325 uchar q_status;
326 uchar q_no;
327 uchar cntl;
328 uchar sense_len;
329 uchar extra_bytes;
330 uchar res;
95cfab6c 331 u32 remain_bytes;
1da177e4
LT		 332} ASC_QDONE_INFO;
333
334typedef struct asc_sg_list {
95cfab6c
HR		 335 __le32 addr;
336 __le32 bytes;
1da177e4
LT		 337} ASC_SG_LIST;
338
339typedef struct asc_sg_head {
27c868c2
MW		 340 ushort entry_cnt;
341 ushort queue_cnt;
342 ushort entry_to_copy;
343 ushort res;
05848b6e 344 ASC_SG_LIST sg_list[0];
1da177e4
LT		 345} ASC_SG_HEAD;
346
1da177e4 347typedef struct asc_scsi_q {
27c868c2
MW		 348 ASC_SCSIQ_1 q1;
349 ASC_SCSIQ_2 q2;
350 uchar *cdbptr;
351 ASC_SG_HEAD *sg_head;
352 ushort remain_sg_entry_cnt;
353 ushort next_sg_index;
1da177e4
LT		 354} ASC_SCSI_Q;
355
1da177e4 356typedef struct asc_scsi_bios_req_q {
27c868c2
MW		 357 ASC_SCSIQ_1 r1;
358 ASC_SCSIQ_2 r2;
359 uchar *cdbptr;
360 ASC_SG_HEAD *sg_head;
361 uchar *sense_ptr;
362 ASC_SCSIQ_3 r3;
363 uchar cdb[ASC_MAX_CDB_LEN];
364 uchar sense[ASC_MIN_SENSE_LEN];
1da177e4
LT		 365} ASC_SCSI_BIOS_REQ_Q;
366
367typedef struct asc_risc_q {
27c868c2
MW		 368 uchar fwd;
369 uchar bwd;
370 ASC_SCSIQ_1 i1;
371 ASC_SCSIQ_2 i2;
372 ASC_SCSIQ_3 i3;
373 ASC_SCSIQ_4 i4;
1da177e4
LT		 374} ASC_RISC_Q;
375
376typedef struct asc_sg_list_q {
27c868c2
MW		 377 uchar seq_no;
378 uchar q_no;
379 uchar cntl;
380 uchar sg_head_qp;
381 uchar sg_list_cnt;
382 uchar sg_cur_list_cnt;
1da177e4
LT		 383} ASC_SG_LIST_Q;
384
385typedef struct asc_risc_sg_list_q {
27c868c2
MW		 386 uchar fwd;
387 uchar bwd;
388 ASC_SG_LIST_Q sg;
389 ASC_SG_LIST sg_list[7];
1da177e4
LT		 390} ASC_RISC_SG_LIST_Q;
391
1da177e4 392#define ASCQ_ERR_Q_STATUS 0x0D
1da177e4
LT		 393#define ASCQ_ERR_CUR_QNG 0x17
394#define ASCQ_ERR_SG_Q_LINKS 0x18
1da177e4
LT		 395#define ASCQ_ERR_ISR_RE_ENTRY 0x1A
396#define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B
397#define ASCQ_ERR_ISR_ON_CRITICAL 0x1C
1da177e4
LT		 398
399/*
400 * Warning code values are set in ASC_DVC_VAR 'warn_code'.
401 */
402#define ASC_WARN_NO_ERROR 0x0000
403#define ASC_WARN_IO_PORT_ROTATE 0x0001
404#define ASC_WARN_EEPROM_CHKSUM 0x0002
405#define ASC_WARN_IRQ_MODIFIED 0x0004
406#define ASC_WARN_AUTO_CONFIG 0x0008
407#define ASC_WARN_CMD_QNG_CONFLICT 0x0010
408#define ASC_WARN_EEPROM_RECOVER 0x0020
409#define ASC_WARN_CFG_MSW_RECOVER 0x0040
1da177e4
LT		 410
411/*
720349a8 412 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'.
1da177e4 413 */
720349a8
MW		 414#define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */
415#define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */
416#define ASC_IERR_SET_PC_ADDR 0x0004
417#define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */
418#define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */
419#define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */
420#define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */
421#define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */
422#define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */
423#define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */
424#define ASC_IERR_NO_BUS_TYPE 0x0400
425#define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
426#define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */
427#define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */
1da177e4 428
1da177e4
LT		 429#define ASC_DEF_MAX_TOTAL_QNG (0xF0)
430#define ASC_MIN_TAG_Q_PER_DVC (0x04)
95c9f162 431#define ASC_MIN_FREE_Q (0x02)
1da177e4
LT		 432#define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
433#define ASC_MAX_TOTAL_QNG 240
434#define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
435#define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8
436#define ASC_MAX_PCI_INRAM_TOTAL_QNG 20
437#define ASC_MAX_INRAM_TAG_QNG 16
1da177e4 438#define ASC_IOADR_GAP 0x10
1da177e4
LT		 439#define ASC_SYN_MAX_OFFSET 0x0F
440#define ASC_DEF_SDTR_OFFSET 0x0F
1da177e4 441#define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02
afbb68c3
MW		 442#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
443
444/* The narrow chip only supports a limited selection of transfer rates.
445 * These are encoded in the range 0..7 or 0..15 depending whether the chip
446 * is Ultra-capable or not. These tables let us convert from one to the other.
447 */
448static const unsigned char asc_syn_xfer_period[8] = {
449 25, 30, 35, 40, 50, 60, 70, 85
450};
451
452static const unsigned char asc_syn_ultra_xfer_period[16] = {
453 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
454};
1da177e4
LT		 455
456typedef struct ext_msg {
27c868c2
MW		 457 uchar msg_type;
458 uchar msg_len;
459 uchar msg_req;
460 union {
461 struct {
462 uchar sdtr_xfer_period;
463 uchar sdtr_req_ack_offset;
464 } sdtr;
465 struct {
466 uchar wdtr_width;
467 } wdtr;
468 struct {
469 uchar mdp_b3;
470 uchar mdp_b2;
471 uchar mdp_b1;
472 uchar mdp_b0;
473 } mdp;
474 } u_ext_msg;
475 uchar res;
1da177e4
LT		 476} EXT_MSG;
477
478#define xfer_period u_ext_msg.sdtr.sdtr_xfer_period
479#define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset
480#define wdtr_width u_ext_msg.wdtr.wdtr_width
481#define mdp_b3 u_ext_msg.mdp_b3
482#define mdp_b2 u_ext_msg.mdp_b2
483#define mdp_b1 u_ext_msg.mdp_b1
484#define mdp_b0 u_ext_msg.mdp_b0
485
486typedef struct asc_dvc_cfg {
27c868c2
MW		 487 ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
488 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
489 ASC_SCSI_BIT_ID_TYPE disc_enable;
490 ASC_SCSI_BIT_ID_TYPE sdtr_enable;
491 uchar chip_scsi_id;
492 uchar isa_dma_speed;
493 uchar isa_dma_channel;
494 uchar chip_version;
27c868c2
MW		 495 ushort mcode_date;
496 ushort mcode_version;
497 uchar max_tag_qng[ASC_MAX_TID + 1];
27c868c2 498 uchar sdtr_period_offset[ASC_MAX_TID + 1];
27c868c2 499 uchar adapter_info[6];
1da177e4
LT		 500} ASC_DVC_CFG;
501
502#define ASC_DEF_DVC_CNTL 0xFFFF
503#define ASC_DEF_CHIP_SCSI_ID 7
504#define ASC_DEF_ISA_DMA_SPEED 4
1da177e4
LT		 505#define ASC_INIT_STATE_BEG_GET_CFG 0x0001
506#define ASC_INIT_STATE_END_GET_CFG 0x0002
507#define ASC_INIT_STATE_BEG_SET_CFG 0x0004
508#define ASC_INIT_STATE_END_SET_CFG 0x0008
509#define ASC_INIT_STATE_BEG_LOAD_MC 0x0010
510#define ASC_INIT_STATE_END_LOAD_MC 0x0020
511#define ASC_INIT_STATE_BEG_INQUIRY 0x0040
512#define ASC_INIT_STATE_END_INQUIRY 0x0080
513#define ASC_INIT_RESET_SCSI_DONE 0x0100
514#define ASC_INIT_STATE_WITHOUT_EEP 0x8000
1da177e4
LT		 515#define ASC_BUG_FIX_IF_NOT_DWB 0x0001
516#define ASC_BUG_FIX_ASYN_USE_SYN 0x0002
1da177e4
LT		 517#define ASC_MIN_TAGGED_CMD 7
518#define ASC_MAX_SCSI_RESET_WAIT 30
d10fb2c7 519#define ASC_OVERRUN_BSIZE 64
1da177e4 520
27c868c2 521struct asc_dvc_var; /* Forward Declaration. */
1da177e4 522
1da177e4 523typedef struct asc_dvc_var {
27c868c2
MW		 524 PortAddr iop_base;
525 ushort err_code;
526 ushort dvc_cntl;
527 ushort bug_fix_cntl;
528 ushort bus_type;
27c868c2
MW		 529 ASC_SCSI_BIT_ID_TYPE init_sdtr;
530 ASC_SCSI_BIT_ID_TYPE sdtr_done;
531 ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
532 ASC_SCSI_BIT_ID_TYPE unit_not_ready;
533 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
534 ASC_SCSI_BIT_ID_TYPE start_motor;
7d5d408c 535 uchar *overrun_buf;
d10fb2c7 536 dma_addr_t overrun_dma;
27c868c2
MW		 537 uchar scsi_reset_wait;
538 uchar chip_no;
ae26759e 539 bool is_in_int;
27c868c2
MW		 540 uchar max_total_qng;
541 uchar cur_total_qng;
542 uchar in_critical_cnt;
27c868c2
MW		 543 uchar last_q_shortage;
544 ushort init_state;
545 uchar cur_dvc_qng[ASC_MAX_TID + 1];
546 uchar max_dvc_qng[ASC_MAX_TID + 1];
547 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
548 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
afbb68c3 549 const uchar *sdtr_period_tbl;
27c868c2
MW		 550 ASC_DVC_CFG *cfg;
551 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
552 char redo_scam;
553 ushort res2;
554 uchar dos_int13_table[ASC_MAX_TID + 1];
95cfab6c 555 unsigned int max_dma_count;
27c868c2
MW		 556 ASC_SCSI_BIT_ID_TYPE no_scam;
557 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
afbb68c3 558 uchar min_sdtr_index;
27c868c2 559 uchar max_sdtr_index;
27c868c2 560 struct asc_board *drv_ptr;
95cfab6c 561 unsigned int uc_break;
1da177e4
LT		 562} ASC_DVC_VAR;
563
564typedef struct asc_dvc_inq_info {
27c868c2 565 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1da177e4
LT		 566} ASC_DVC_INQ_INFO;
567
568typedef struct asc_cap_info {
95cfab6c
HR		 569 u32 lba;
570 u32 blk_size;
1da177e4
LT		 571} ASC_CAP_INFO;
572
573typedef struct asc_cap_info_array {
27c868c2 574 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
1da177e4
LT		 575} ASC_CAP_INFO_ARRAY;
576
577#define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001
578#define ASC_MCNTL_NULL_TARGET (ushort)0x0002
579#define ASC_CNTL_INITIATOR (ushort)0x0001
580#define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002
581#define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004
582#define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008
583#define ASC_CNTL_NO_SCAM (ushort)0x0010
584#define ASC_CNTL_INT_MULTI_Q (ushort)0x0080
585#define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040
586#define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100
587#define ASC_CNTL_RESET_SCSI (ushort)0x0200
588#define ASC_CNTL_INIT_INQUIRY (ushort)0x0400
589#define ASC_CNTL_INIT_VERBOSE (ushort)0x0800
590#define ASC_CNTL_SCSI_PARITY (ushort)0x1000
591#define ASC_CNTL_BURST_MODE (ushort)0x2000
592#define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
593#define ASC_EEP_DVC_CFG_BEG_VL 2
594#define ASC_EEP_MAX_DVC_ADDR_VL 15
595#define ASC_EEP_DVC_CFG_BEG 32
596#define ASC_EEP_MAX_DVC_ADDR 45
1da177e4 597#define ASC_EEP_MAX_RETRY 20
1da177e4
LT		 598
599/*
600 * These macros keep the chip SCSI id and ISA DMA speed
601 * bitfields in board order. C bitfields aren't portable
602 * between big and little-endian platforms so they are
603 * not used.
604 */
605
606#define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f)
607#define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4)
608#define ASC_EEP_SET_CHIP_ID(cfg, sid) \
609 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
610#define ASC_EEP_SET_DMA_SPD(cfg, spd) \
611 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
612
613typedef struct asceep_config {
27c868c2
MW		 614 ushort cfg_lsw;
615 ushort cfg_msw;
616 uchar init_sdtr;
617 uchar disc_enable;
618 uchar use_cmd_qng;
619 uchar start_motor;
620 uchar max_total_qng;
621 uchar max_tag_qng;
622 uchar bios_scan;
623 uchar power_up_wait;
624 uchar no_scam;
625 uchar id_speed; /* low order 4 bits is chip scsi id */
626 /* high order 4 bits is isa dma speed */
627 uchar dos_int13_table[ASC_MAX_TID + 1];
628 uchar adapter_info[6];
629 ushort cntl;
630 ushort chksum;
1da177e4
LT		 631} ASCEEP_CONFIG;
632
1da177e4
LT		 633#define ASC_EEP_CMD_READ 0x80
634#define ASC_EEP_CMD_WRITE 0x40
635#define ASC_EEP_CMD_WRITE_ABLE 0x30
636#define ASC_EEP_CMD_WRITE_DISABLE 0x00
1da177e4
LT		 637#define ASCV_MSGOUT_BEG 0x0000
638#define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
639#define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
640#define ASCV_BREAK_SAVED_CODE (ushort)0x0006
641#define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8)
642#define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3)
643#define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4)
644#define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8)
645#define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8)
646#define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020
647#define ASCV_BREAK_ADDR (ushort)0x0028
648#define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A
649#define ASCV_BREAK_CONTROL (ushort)0x002C
650#define ASCV_BREAK_HIT_COUNT (ushort)0x002E
651
652#define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030
653#define ASCV_MCODE_CHKSUM_W (ushort)0x0032
654#define ASCV_MCODE_SIZE_W (ushort)0x0034
655#define ASCV_STOP_CODE_B (ushort)0x0036
656#define ASCV_DVC_ERR_CODE_B (ushort)0x0037
657#define ASCV_OVERRUN_PADDR_D (ushort)0x0038
658#define ASCV_OVERRUN_BSIZE_D (ushort)0x003C
659#define ASCV_HALTCODE_W (ushort)0x0040
660#define ASCV_CHKSUM_W (ushort)0x0042
661#define ASCV_MC_DATE_W (ushort)0x0044
662#define ASCV_MC_VER_W (ushort)0x0046
663#define ASCV_NEXTRDY_B (ushort)0x0048
664#define ASCV_DONENEXT_B (ushort)0x0049
665#define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
666#define ASCV_SCSIBUSY_B (ushort)0x004B
667#define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C
668#define ASCV_CURCDB_B (ushort)0x004D
669#define ASCV_RCLUN_B (ushort)0x004E
670#define ASCV_BUSY_QHEAD_B (ushort)0x004F
671#define ASCV_DISC1_QHEAD_B (ushort)0x0050
672#define ASCV_DISC_ENABLE_B (ushort)0x0052
673#define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
674#define ASCV_HOSTSCSI_ID_B (ushort)0x0055
675#define ASCV_MCODE_CNTL_B (ushort)0x0056
676#define ASCV_NULL_TARGET_B (ushort)0x0057
677#define ASCV_FREE_Q_HEAD_W (ushort)0x0058
678#define ASCV_DONE_Q_TAIL_W (ushort)0x005A
679#define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1)
680#define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1)
681#define ASCV_HOST_FLAG_B (ushort)0x005D
682#define ASCV_TOTAL_READY_Q_B (ushort)0x0064
683#define ASCV_VER_SERIAL_B (ushort)0x0065
684#define ASCV_HALTCODE_SAVED_W (ushort)0x0066
685#define ASCV_WTM_FLAG_B (ushort)0x0068
686#define ASCV_RISC_FLAG_B (ushort)0x006A
687#define ASCV_REQ_SG_LIST_QP (ushort)0x006B
688#define ASC_HOST_FLAG_IN_ISR 0x01
689#define ASC_HOST_FLAG_ACK_INT 0x02
690#define ASC_RISC_FLAG_GEN_INT 0x01
691#define ASC_RISC_FLAG_REQ_SG_LIST 0x02
692#define IOP_CTRL (0x0F)
693#define IOP_STATUS (0x0E)
694#define IOP_INT_ACK IOP_STATUS
695#define IOP_REG_IFC (0x0D)
696#define IOP_SYN_OFFSET (0x0B)
697#define IOP_EXTRA_CONTROL (0x0D)
698#define IOP_REG_PC (0x0C)
699#define IOP_RAM_ADDR (0x0A)
700#define IOP_RAM_DATA (0x08)
701#define IOP_EEP_DATA (0x06)
702#define IOP_EEP_CMD (0x07)
703#define IOP_VERSION (0x03)
704#define IOP_CONFIG_HIGH (0x04)
705#define IOP_CONFIG_LOW (0x02)
706#define IOP_SIG_BYTE (0x01)
707#define IOP_SIG_WORD (0x00)
708#define IOP_REG_DC1 (0x0E)
709#define IOP_REG_DC0 (0x0C)
710#define IOP_REG_SB (0x0B)
711#define IOP_REG_DA1 (0x0A)
712#define IOP_REG_DA0 (0x08)
713#define IOP_REG_SC (0x09)
714#define IOP_DMA_SPEED (0x07)
715#define IOP_REG_FLAG (0x07)
716#define IOP_FIFO_H (0x06)
717#define IOP_FIFO_L (0x04)
718#define IOP_REG_ID (0x05)
719#define IOP_REG_QP (0x03)
720#define IOP_REG_IH (0x02)
721#define IOP_REG_IX (0x01)
722#define IOP_REG_AX (0x00)
723#define IFC_REG_LOCK (0x00)
724#define IFC_REG_UNLOCK (0x09)
725#define IFC_WR_EN_FILTER (0x10)
726#define IFC_RD_NO_EEPROM (0x10)
727#define IFC_SLEW_RATE (0x20)
728#define IFC_ACT_NEG (0x40)
729#define IFC_INP_FILTER (0x80)
730#define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK)
731#define SC_SEL (uchar)(0x80)
732#define SC_BSY (uchar)(0x40)
733#define SC_ACK (uchar)(0x20)
734#define SC_REQ (uchar)(0x10)
735#define SC_ATN (uchar)(0x08)
736#define SC_IO (uchar)(0x04)
737#define SC_CD (uchar)(0x02)
738#define SC_MSG (uchar)(0x01)
739#define SEC_SCSI_CTL (uchar)(0x80)
740#define SEC_ACTIVE_NEGATE (uchar)(0x40)
741#define SEC_SLEW_RATE (uchar)(0x20)
742#define SEC_ENABLE_FILTER (uchar)(0x10)
743#define ASC_HALT_EXTMSG_IN (ushort)0x8000
744#define ASC_HALT_CHK_CONDITION (ushort)0x8100
745#define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
746#define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300
747#define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400
748#define ASC_HALT_SDTR_REJECTED (ushort)0x4000
749#define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
750#define ASC_MAX_QNO 0xF8
751#define ASC_DATA_SEC_BEG (ushort)0x0080
752#define ASC_DATA_SEC_END (ushort)0x0080
753#define ASC_CODE_SEC_BEG (ushort)0x0080
754#define ASC_CODE_SEC_END (ushort)0x0080
755#define ASC_QADR_BEG (0x4000)
756#define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64)
757#define ASC_QADR_END (ushort)0x7FFF
758#define ASC_QLAST_ADR (ushort)0x7FC0
759#define ASC_QBLK_SIZE 0x40
760#define ASC_BIOS_DATA_QBEG 0xF8
761#define ASC_MIN_ACTIVE_QNO 0x01
762#define ASC_QLINK_END 0xFF
763#define ASC_EEPROM_WORDS 0x10
764#define ASC_MAX_MGS_LEN 0x10
765#define ASC_BIOS_ADDR_DEF 0xDC00
766#define ASC_BIOS_SIZE 0x3800
767#define ASC_BIOS_RAM_OFF 0x3800
768#define ASC_BIOS_RAM_SIZE 0x800
769#define ASC_BIOS_MIN_ADDR 0xC000
770#define ASC_BIOS_MAX_ADDR 0xEC00
771#define ASC_BIOS_BANK_SIZE 0x0400
772#define ASC_MCODE_START_ADDR 0x0080
773#define ASC_CFG0_HOST_INT_ON 0x0020
774#define ASC_CFG0_BIOS_ON 0x0040
775#define ASC_CFG0_VERA_BURST_ON 0x0080
776#define ASC_CFG0_SCSI_PARITY_ON 0x0800
777#define ASC_CFG1_SCSI_TARGET_ON 0x0080
778#define ASC_CFG1_LRAM_8BITS_ON 0x0800
779#define ASC_CFG_MSW_CLR_MASK 0x3080
780#define CSW_TEST1 (ASC_CS_TYPE)0x8000
781#define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000
782#define CSW_RESERVED1 (ASC_CS_TYPE)0x2000
783#define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000
784#define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800
785#define CSW_TEST2 (ASC_CS_TYPE)0x0400
786#define CSW_TEST3 (ASC_CS_TYPE)0x0200
787#define CSW_RESERVED2 (ASC_CS_TYPE)0x0100
788#define CSW_DMA_DONE (ASC_CS_TYPE)0x0080
789#define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040
790#define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020
791#define CSW_HALTED (ASC_CS_TYPE)0x0010
792#define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
793#define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004
794#define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002
795#define CSW_INT_PENDING (ASC_CS_TYPE)0x0001
796#define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
797#define CIW_INT_ACK (ASC_CS_TYPE)0x0100
798#define CIW_TEST1 (ASC_CS_TYPE)0x0200
799#define CIW_TEST2 (ASC_CS_TYPE)0x0400
800#define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800
801#define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000
802#define CC_CHIP_RESET (uchar)0x80
803#define CC_SCSI_RESET (uchar)0x40
804#define CC_HALT (uchar)0x20
805#define CC_SINGLE_STEP (uchar)0x10
806#define CC_DMA_ABLE (uchar)0x08
807#define CC_TEST (uchar)0x04
808#define CC_BANK_ONE (uchar)0x02
809#define CC_DIAG (uchar)0x01
810#define ASC_1000_ID0W 0x04C1
811#define ASC_1000_ID0W_FIX 0x00C1
812#define ASC_1000_ID1B 0x25
1da177e4 813#define ASC_EISA_REV_IOP_MASK (0x0C83)
1da177e4
LT		 814#define ASC_EISA_CFG_IOP_MASK (0x0C86)
815#define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000)
1da177e4
LT		 816#define INS_HALTINT (ushort)0x6281
817#define INS_HALT (ushort)0x6280
818#define INS_SINT (ushort)0x6200
819#define INS_RFLAG_WTM (ushort)0x7380
820#define ASC_MC_SAVE_CODE_WSIZE 0x500
821#define ASC_MC_SAVE_DATA_WSIZE 0x40
822
823typedef struct asc_mc_saved {
27c868c2
MW		 824 ushort data[ASC_MC_SAVE_DATA_WSIZE];
825 ushort code[ASC_MC_SAVE_CODE_WSIZE];
1da177e4
LT		 826} ASC_MC_SAVED;
827
828#define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
829#define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
830#define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
831#define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
832#define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
833#define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
834#define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B)
835#define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B)
836#define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
837#define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val)
51219358
MW		 838#define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
839#define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
840#define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
841#define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
1da177e4
LT		 842#define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE)
843#define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD)
844#define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION)
845#define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW)
846#define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH)
847#define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data)
848#define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data)
849#define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD)
850#define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data)
851#define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA)
852#define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data)
853#define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
854#define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
855#define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA)
856#define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data)
857#define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC)
858#define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data)
859#define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
860#define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val)
861#define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL)
862#define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val)
863#define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET)
864#define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data)
865#define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data)
866#define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC)
867#define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
868#define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
869#define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL)
870#define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data)
871#define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX)
872#define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data)
873#define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX)
874#define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data)
875#define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH)
876#define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data)
877#define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP)
878#define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data)
879#define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L)
880#define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data)
881#define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H)
882#define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data)
883#define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED)
884#define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data)
885#define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0)
886#define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data)
887#define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1)
888#define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data)
889#define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0)
890#define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data)
891#define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1)
892#define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data)
893#define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID)
894#define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data)
895
1da177e4
LT		 896/*
897 * These macros are used to convert a virtual address to a
898 * 32-bit value. This currently can be used on Linux Alpha
899 * which uses 64-bit virtual address but a 32-bit bus address.
900 * This is likely to break in the future, but doing this now
901 * will give us time to change the HW and FW to handle 64-bit
902 * addresses.
903 */
1da177e4
LT		 904#define ADV_U32_TO_VADDR bus_to_virt
905
27c868c2 906#define AdvPortAddr void __iomem * /* Virtual memory address size */
1da177e4
LT		 907
908/*
909 * Define Adv Library required memory access macros.
910 */
911#define ADV_MEM_READB(addr) readb(addr)
912#define ADV_MEM_READW(addr) readw(addr)
913#define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
914#define ADV_MEM_WRITEW(addr, word) writew(word, addr)
915#define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
916
1da177e4
LT		 917/*
918 * Define total number of simultaneous maximum element scatter-gather
919 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
920 * maximum number of outstanding commands per wide host adapter. Each
921 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
922 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
923 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
924 * structures or 255 scatter-gather elements.
1da177e4
LT		 925 */
926#define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG
927
928/*
98d41c29 929 * Define maximum number of scatter-gather elements per request.
1da177e4
LT		 930 */
931#define ADV_MAX_SG_LIST 255
98d41c29 932#define NO_OF_SG_PER_BLOCK 15
1da177e4 933
1da177e4
LT		 934#define ADV_EEP_DVC_CFG_BEGIN (0x00)
935#define ADV_EEP_DVC_CFG_END (0x15)
27c868c2 936#define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */
1da177e4
LT		 937#define ADV_EEP_MAX_WORD_ADDR (0x1E)
938
939#define ADV_EEP_DELAY_MS 100
940
27c868c2
MW		 941#define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */
942#define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */
1da177e4
LT		 943/*
944 * For the ASC3550 Bit 13 is Termination Polarity control bit.
945 * For later ICs Bit 13 controls whether the CIS (Card Information
946 * Service Section) is loaded from EEPROM.
947 */
27c868c2
MW		 948#define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */
949#define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */
1da177e4
LT		 950/*
951 * ASC38C1600 Bit 11
952 *
953 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
954 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
955 * Function 0 will specify INT B.
956 *
957 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
958 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
959 * Function 1 will specify INT A.
960 */
27c868c2
MW		 961#define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */
962
963typedef struct adveep_3550_config {
964 /* Word Offset, Description */
965
966 ushort cfg_lsw; /* 00 power up initialization */
967 /* bit 13 set - Term Polarity Control */
968 /* bit 14 set - BIOS Enable */
969 /* bit 15 set - Big Endian Mode */
970 ushort cfg_msw; /* 01 unused */
971 ushort disc_enable; /* 02 disconnect enable */
972 ushort wdtr_able; /* 03 Wide DTR able */
973 ushort sdtr_able; /* 04 Synchronous DTR able */
974 ushort start_motor; /* 05 send start up motor */
975 ushort tagqng_able; /* 06 tag queuing able */
976 ushort bios_scan; /* 07 BIOS device control */
977 ushort scam_tolerant; /* 08 no scam */
978
979 uchar adapter_scsi_id; /* 09 Host Adapter ID */
980 uchar bios_boot_delay; /* power up wait */
981
982 uchar scsi_reset_delay; /* 10 reset delay */
983 uchar bios_id_lun; /* first boot device scsi id & lun */
984 /* high nibble is lun */
985 /* low nibble is scsi id */
986
987 uchar termination; /* 11 0 - automatic */
988 /* 1 - low off / high off */
989 /* 2 - low off / high on */
990 /* 3 - low on / high on */
991 /* There is no low on / high off */
992
993 uchar reserved1; /* reserved byte (not used) */
994
995 ushort bios_ctrl; /* 12 BIOS control bits */
996 /* bit 0 BIOS don't act as initiator. */
997 /* bit 1 BIOS > 1 GB support */
998 /* bit 2 BIOS > 2 Disk Support */
999 /* bit 3 BIOS don't support removables */
1000 /* bit 4 BIOS support bootable CD */
1001 /* bit 5 BIOS scan enabled */
1002 /* bit 6 BIOS support multiple LUNs */
1003 /* bit 7 BIOS display of message */
1004 /* bit 8 SCAM disabled */
1005 /* bit 9 Reset SCSI bus during init. */
1006 /* bit 10 */
1007 /* bit 11 No verbose initialization. */
1008 /* bit 12 SCSI parity enabled */
1009 /* bit 13 */
1010 /* bit 14 */
1011 /* bit 15 */
1012 ushort ultra_able; /* 13 ULTRA speed able */
1013 ushort reserved2; /* 14 reserved */
1014 uchar max_host_qng; /* 15 maximum host queuing */
1015 uchar max_dvc_qng; /* maximum per device queuing */
1016 ushort dvc_cntl; /* 16 control bit for driver */
1017 ushort bug_fix; /* 17 control bit for bug fix */
1018 ushort serial_number_word1; /* 18 Board serial number word 1 */
1019 ushort serial_number_word2; /* 19 Board serial number word 2 */
1020 ushort serial_number_word3; /* 20 Board serial number word 3 */
1021 ushort check_sum; /* 21 EEP check sum */
1022 uchar oem_name[16]; /* 22 OEM name */
1023 ushort dvc_err_code; /* 30 last device driver error code */
1024 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1025 ushort adv_err_addr; /* 32 last uc error address */
1026 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1027 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1028 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1029 ushort num_of_err; /* 36 number of error */
1da177e4
LT		 1030} ADVEEP_3550_CONFIG;
1031
27c868c2
MW		 1032typedef struct adveep_38C0800_config {
1033 /* Word Offset, Description */
1034
1035 ushort cfg_lsw; /* 00 power up initialization */
1036 /* bit 13 set - Load CIS */
1037 /* bit 14 set - BIOS Enable */
1038 /* bit 15 set - Big Endian Mode */
1039 ushort cfg_msw; /* 01 unused */
1040 ushort disc_enable; /* 02 disconnect enable */
1041 ushort wdtr_able; /* 03 Wide DTR able */
1042 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1043 ushort start_motor; /* 05 send start up motor */
1044 ushort tagqng_able; /* 06 tag queuing able */
1045 ushort bios_scan; /* 07 BIOS device control */
1046 ushort scam_tolerant; /* 08 no scam */
1047
1048 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1049 uchar bios_boot_delay; /* power up wait */
1050
1051 uchar scsi_reset_delay; /* 10 reset delay */
1052 uchar bios_id_lun; /* first boot device scsi id & lun */
1053 /* high nibble is lun */
1054 /* low nibble is scsi id */
1055
1056 uchar termination_se; /* 11 0 - automatic */
1057 /* 1 - low off / high off */
1058 /* 2 - low off / high on */
1059 /* 3 - low on / high on */
1060 /* There is no low on / high off */
1061
1062 uchar termination_lvd; /* 11 0 - automatic */
1063 /* 1 - low off / high off */
1064 /* 2 - low off / high on */
1065 /* 3 - low on / high on */
1066 /* There is no low on / high off */
1067
1068 ushort bios_ctrl; /* 12 BIOS control bits */
1069 /* bit 0 BIOS don't act as initiator. */
1070 /* bit 1 BIOS > 1 GB support */
1071 /* bit 2 BIOS > 2 Disk Support */
1072 /* bit 3 BIOS don't support removables */
1073 /* bit 4 BIOS support bootable CD */
1074 /* bit 5 BIOS scan enabled */
1075 /* bit 6 BIOS support multiple LUNs */
1076 /* bit 7 BIOS display of message */
1077 /* bit 8 SCAM disabled */
1078 /* bit 9 Reset SCSI bus during init. */
1079 /* bit 10 */
1080 /* bit 11 No verbose initialization. */
1081 /* bit 12 SCSI parity enabled */
1082 /* bit 13 */
1083 /* bit 14 */
1084 /* bit 15 */
1085 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1086 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1087 uchar max_host_qng; /* 15 maximum host queueing */
1088 uchar max_dvc_qng; /* maximum per device queuing */
1089 ushort dvc_cntl; /* 16 control bit for driver */
1090 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1091 ushort serial_number_word1; /* 18 Board serial number word 1 */
1092 ushort serial_number_word2; /* 19 Board serial number word 2 */
1093 ushort serial_number_word3; /* 20 Board serial number word 3 */
1094 ushort check_sum; /* 21 EEP check sum */
1095 uchar oem_name[16]; /* 22 OEM name */
1096 ushort dvc_err_code; /* 30 last device driver error code */
1097 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1098 ushort adv_err_addr; /* 32 last uc error address */
1099 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1100 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1101 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1102 ushort reserved36; /* 36 reserved */
1103 ushort reserved37; /* 37 reserved */
1104 ushort reserved38; /* 38 reserved */
1105 ushort reserved39; /* 39 reserved */
1106 ushort reserved40; /* 40 reserved */
1107 ushort reserved41; /* 41 reserved */
1108 ushort reserved42; /* 42 reserved */
1109 ushort reserved43; /* 43 reserved */
1110 ushort reserved44; /* 44 reserved */
1111 ushort reserved45; /* 45 reserved */
1112 ushort reserved46; /* 46 reserved */
1113 ushort reserved47; /* 47 reserved */
1114 ushort reserved48; /* 48 reserved */
1115 ushort reserved49; /* 49 reserved */
1116 ushort reserved50; /* 50 reserved */
1117 ushort reserved51; /* 51 reserved */
1118 ushort reserved52; /* 52 reserved */
1119 ushort reserved53; /* 53 reserved */
1120 ushort reserved54; /* 54 reserved */
1121 ushort reserved55; /* 55 reserved */
1122 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1123 ushort cisprt_msw; /* 57 CIS PTR MSW */
1124 ushort subsysvid; /* 58 SubSystem Vendor ID */
1125 ushort subsysid; /* 59 SubSystem ID */
1126 ushort reserved60; /* 60 reserved */
1127 ushort reserved61; /* 61 reserved */
1128 ushort reserved62; /* 62 reserved */
1129 ushort reserved63; /* 63 reserved */
1da177e4
LT		 1130} ADVEEP_38C0800_CONFIG;
1131
27c868c2
MW		 1132typedef struct adveep_38C1600_config {
1133 /* Word Offset, Description */
1134
1135 ushort cfg_lsw; /* 00 power up initialization */
1136 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */
1137 /* clear - Func. 0 INTA, Func. 1 INTB */
1138 /* bit 13 set - Load CIS */
1139 /* bit 14 set - BIOS Enable */
1140 /* bit 15 set - Big Endian Mode */
1141 ushort cfg_msw; /* 01 unused */
1142 ushort disc_enable; /* 02 disconnect enable */
1143 ushort wdtr_able; /* 03 Wide DTR able */
1144 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */
1145 ushort start_motor; /* 05 send start up motor */
1146 ushort tagqng_able; /* 06 tag queuing able */
1147 ushort bios_scan; /* 07 BIOS device control */
1148 ushort scam_tolerant; /* 08 no scam */
1149
1150 uchar adapter_scsi_id; /* 09 Host Adapter ID */
1151 uchar bios_boot_delay; /* power up wait */
1152
1153 uchar scsi_reset_delay; /* 10 reset delay */
1154 uchar bios_id_lun; /* first boot device scsi id & lun */
1155 /* high nibble is lun */
1156 /* low nibble is scsi id */
1157
1158 uchar termination_se; /* 11 0 - automatic */
1159 /* 1 - low off / high off */
1160 /* 2 - low off / high on */
1161 /* 3 - low on / high on */
1162 /* There is no low on / high off */
1163
1164 uchar termination_lvd; /* 11 0 - automatic */
1165 /* 1 - low off / high off */
1166 /* 2 - low off / high on */
1167 /* 3 - low on / high on */
1168 /* There is no low on / high off */
1169
1170 ushort bios_ctrl; /* 12 BIOS control bits */
1171 /* bit 0 BIOS don't act as initiator. */
1172 /* bit 1 BIOS > 1 GB support */
1173 /* bit 2 BIOS > 2 Disk Support */
1174 /* bit 3 BIOS don't support removables */
1175 /* bit 4 BIOS support bootable CD */
1176 /* bit 5 BIOS scan enabled */
1177 /* bit 6 BIOS support multiple LUNs */
1178 /* bit 7 BIOS display of message */
1179 /* bit 8 SCAM disabled */
1180 /* bit 9 Reset SCSI bus during init. */
1181 /* bit 10 Basic Integrity Checking disabled */
1182 /* bit 11 No verbose initialization. */
1183 /* bit 12 SCSI parity enabled */
1184 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1185 /* bit 14 */
1186 /* bit 15 */
1187 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */
1188 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */
1189 uchar max_host_qng; /* 15 maximum host queueing */
1190 uchar max_dvc_qng; /* maximum per device queuing */
1191 ushort dvc_cntl; /* 16 control bit for driver */
1192 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */
1193 ushort serial_number_word1; /* 18 Board serial number word 1 */
1194 ushort serial_number_word2; /* 19 Board serial number word 2 */
1195 ushort serial_number_word3; /* 20 Board serial number word 3 */
1196 ushort check_sum; /* 21 EEP check sum */
1197 uchar oem_name[16]; /* 22 OEM name */
1198 ushort dvc_err_code; /* 30 last device driver error code */
1199 ushort adv_err_code; /* 31 last uc and Adv Lib error code */
1200 ushort adv_err_addr; /* 32 last uc error address */
1201 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */
1202 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */
1203 ushort saved_adv_err_addr; /* 35 saved last uc error address */
1204 ushort reserved36; /* 36 reserved */
1205 ushort reserved37; /* 37 reserved */
1206 ushort reserved38; /* 38 reserved */
1207 ushort reserved39; /* 39 reserved */
1208 ushort reserved40; /* 40 reserved */
1209 ushort reserved41; /* 41 reserved */
1210 ushort reserved42; /* 42 reserved */
1211 ushort reserved43; /* 43 reserved */
1212 ushort reserved44; /* 44 reserved */
1213 ushort reserved45; /* 45 reserved */
1214 ushort reserved46; /* 46 reserved */
1215 ushort reserved47; /* 47 reserved */
1216 ushort reserved48; /* 48 reserved */
1217 ushort reserved49; /* 49 reserved */
1218 ushort reserved50; /* 50 reserved */
1219 ushort reserved51; /* 51 reserved */
1220 ushort reserved52; /* 52 reserved */
1221 ushort reserved53; /* 53 reserved */
1222 ushort reserved54; /* 54 reserved */
1223 ushort reserved55; /* 55 reserved */
1224 ushort cisptr_lsw; /* 56 CIS PTR LSW */
1225 ushort cisprt_msw; /* 57 CIS PTR MSW */
1226 ushort subsysvid; /* 58 SubSystem Vendor ID */
1227 ushort subsysid; /* 59 SubSystem ID */
1228 ushort reserved60; /* 60 reserved */
1229 ushort reserved61; /* 61 reserved */
1230 ushort reserved62; /* 62 reserved */
1231 ushort reserved63; /* 63 reserved */
1da177e4
LT		 1232} ADVEEP_38C1600_CONFIG;
1233
1234/*
1235 * EEPROM Commands
1236 */
1237#define ASC_EEP_CMD_DONE 0x0200
1da177e4
LT		 1238
1239/* bios_ctrl */
1240#define BIOS_CTRL_BIOS 0x0001
1241#define BIOS_CTRL_EXTENDED_XLAT 0x0002
1242#define BIOS_CTRL_GT_2_DISK 0x0004
1243#define BIOS_CTRL_BIOS_REMOVABLE 0x0008
1244#define BIOS_CTRL_BOOTABLE_CD 0x0010
1245#define BIOS_CTRL_MULTIPLE_LUN 0x0040
1246#define BIOS_CTRL_DISPLAY_MSG 0x0080
1247#define BIOS_CTRL_NO_SCAM 0x0100
1248#define BIOS_CTRL_RESET_SCSI_BUS 0x0200
1249#define BIOS_CTRL_INIT_VERBOSE 0x0800
1250#define BIOS_CTRL_SCSI_PARITY 0x1000
1251#define BIOS_CTRL_AIPP_DIS 0x2000
1252
27c868c2 1253#define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */
1da177e4 1254
27c868c2 1255#define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1da177e4
LT		 1256
1257/*
1258 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1259 * a special 16K Adv Library and Microcode version. After the issue is
1260 * resolved, should restore 32K support.
1261 *
1262 * #define ADV_38C1600_MEMSIZE 0x8000L * 32 KB Internal Memory *
1263 */
27c868c2 1264#define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */
1da177e4
LT		 1265
1266/*
1267 * Byte I/O register address from base of 'iop_base'.
1268 */
1269#define IOPB_INTR_STATUS_REG 0x00
1270#define IOPB_CHIP_ID_1 0x01
1271#define IOPB_INTR_ENABLES 0x02
1272#define IOPB_CHIP_TYPE_REV 0x03
1273#define IOPB_RES_ADDR_4 0x04
1274#define IOPB_RES_ADDR_5 0x05
1275#define IOPB_RAM_DATA 0x06
1276#define IOPB_RES_ADDR_7 0x07
1277#define IOPB_FLAG_REG 0x08
1278#define IOPB_RES_ADDR_9 0x09
1279#define IOPB_RISC_CSR 0x0A
1280#define IOPB_RES_ADDR_B 0x0B
1281#define IOPB_RES_ADDR_C 0x0C
1282#define IOPB_RES_ADDR_D 0x0D
1283#define IOPB_SOFT_OVER_WR 0x0E
1284#define IOPB_RES_ADDR_F 0x0F
1285#define IOPB_MEM_CFG 0x10
1286#define IOPB_RES_ADDR_11 0x11
1287#define IOPB_GPIO_DATA 0x12
1288#define IOPB_RES_ADDR_13 0x13
1289#define IOPB_FLASH_PAGE 0x14
1290#define IOPB_RES_ADDR_15 0x15
1291#define IOPB_GPIO_CNTL 0x16
1292#define IOPB_RES_ADDR_17 0x17
1293#define IOPB_FLASH_DATA 0x18
1294#define IOPB_RES_ADDR_19 0x19
1295#define IOPB_RES_ADDR_1A 0x1A
1296#define IOPB_RES_ADDR_1B 0x1B
1297#define IOPB_RES_ADDR_1C 0x1C
1298#define IOPB_RES_ADDR_1D 0x1D
1299#define IOPB_RES_ADDR_1E 0x1E
1300#define IOPB_RES_ADDR_1F 0x1F
1301#define IOPB_DMA_CFG0 0x20
1302#define IOPB_DMA_CFG1 0x21
1303#define IOPB_TICKLE 0x22
1304#define IOPB_DMA_REG_WR 0x23
1305#define IOPB_SDMA_STATUS 0x24
1306#define IOPB_SCSI_BYTE_CNT 0x25
1307#define IOPB_HOST_BYTE_CNT 0x26
1308#define IOPB_BYTE_LEFT_TO_XFER 0x27
1309#define IOPB_BYTE_TO_XFER_0 0x28
1310#define IOPB_BYTE_TO_XFER_1 0x29
1311#define IOPB_BYTE_TO_XFER_2 0x2A
1312#define IOPB_BYTE_TO_XFER_3 0x2B
1313#define IOPB_ACC_GRP 0x2C
1314#define IOPB_RES_ADDR_2D 0x2D
1315#define IOPB_DEV_ID 0x2E
1316#define IOPB_RES_ADDR_2F 0x2F
1317#define IOPB_SCSI_DATA 0x30
1318#define IOPB_RES_ADDR_31 0x31
1319#define IOPB_RES_ADDR_32 0x32
1320#define IOPB_SCSI_DATA_HSHK 0x33
1321#define IOPB_SCSI_CTRL 0x34
1322#define IOPB_RES_ADDR_35 0x35
1323#define IOPB_RES_ADDR_36 0x36
1324#define IOPB_RES_ADDR_37 0x37
1325#define IOPB_RAM_BIST 0x38
1326#define IOPB_PLL_TEST 0x39
1327#define IOPB_PCI_INT_CFG 0x3A
1328#define IOPB_RES_ADDR_3B 0x3B
1329#define IOPB_RFIFO_CNT 0x3C
1330#define IOPB_RES_ADDR_3D 0x3D
1331#define IOPB_RES_ADDR_3E 0x3E
1332#define IOPB_RES_ADDR_3F 0x3F
1333
1334/*
1335 * Word I/O register address from base of 'iop_base'.
1336 */
27c868c2
MW		 1337#define IOPW_CHIP_ID_0 0x00 /* CID0 */
1338#define IOPW_CTRL_REG 0x02 /* CC */
1339#define IOPW_RAM_ADDR 0x04 /* LA */
1340#define IOPW_RAM_DATA 0x06 /* LD */
1da177e4 1341#define IOPW_RES_ADDR_08 0x08
27c868c2
MW		 1342#define IOPW_RISC_CSR 0x0A /* CSR */
1343#define IOPW_SCSI_CFG0 0x0C /* CFG0 */
1344#define IOPW_SCSI_CFG1 0x0E /* CFG1 */
1da177e4 1345#define IOPW_RES_ADDR_10 0x10
27c868c2 1346#define IOPW_SEL_MASK 0x12 /* SM */
1da177e4 1347#define IOPW_RES_ADDR_14 0x14
27c868c2 1348#define IOPW_FLASH_ADDR 0x16 /* FA */
1da177e4 1349#define IOPW_RES_ADDR_18 0x18
27c868c2
MW		 1350#define IOPW_EE_CMD 0x1A /* EC */
1351#define IOPW_EE_DATA 0x1C /* ED */
1352#define IOPW_SFIFO_CNT 0x1E /* SFC */
1da177e4 1353#define IOPW_RES_ADDR_20 0x20
27c868c2
MW		 1354#define IOPW_Q_BASE 0x22 /* QB */
1355#define IOPW_QP 0x24 /* QP */
1356#define IOPW_IX 0x26 /* IX */
1357#define IOPW_SP 0x28 /* SP */
1358#define IOPW_PC 0x2A /* PC */
1da177e4
LT		 1359#define IOPW_RES_ADDR_2C 0x2C
1360#define IOPW_RES_ADDR_2E 0x2E
27c868c2
MW		 1361#define IOPW_SCSI_DATA 0x30 /* SD */
1362#define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */
1363#define IOPW_SCSI_CTRL 0x34 /* SC */
1364#define IOPW_HSHK_CFG 0x36 /* HCFG */
1365#define IOPW_SXFR_STATUS 0x36 /* SXS */
1366#define IOPW_SXFR_CNTL 0x38 /* SXL */
1367#define IOPW_SXFR_CNTH 0x3A /* SXH */
1da177e4 1368#define IOPW_RES_ADDR_3C 0x3C
27c868c2 1369#define IOPW_RFIFO_DATA 0x3E /* RFD */
1da177e4
LT		 1370
1371/*
1372 * Doubleword I/O register address from base of 'iop_base'.
1373 */
1374#define IOPDW_RES_ADDR_0 0x00
1375#define IOPDW_RAM_DATA 0x04
1376#define IOPDW_RES_ADDR_8 0x08
1377#define IOPDW_RES_ADDR_C 0x0C
1378#define IOPDW_RES_ADDR_10 0x10
1379#define IOPDW_COMMA 0x14
1380#define IOPDW_COMMB 0x18
1381#define IOPDW_RES_ADDR_1C 0x1C
1382#define IOPDW_SDMA_ADDR0 0x20
1383#define IOPDW_SDMA_ADDR1 0x24
1384#define IOPDW_SDMA_COUNT 0x28
1385#define IOPDW_SDMA_ERROR 0x2C
1386#define IOPDW_RDMA_ADDR0 0x30
1387#define IOPDW_RDMA_ADDR1 0x34
1388#define IOPDW_RDMA_COUNT 0x38
1389#define IOPDW_RDMA_ERROR 0x3C
1390
1391#define ADV_CHIP_ID_BYTE 0x25
1392#define ADV_CHIP_ID_WORD 0x04C1
1393
1da177e4
LT		 1394#define ADV_INTR_ENABLE_HOST_INTR 0x01
1395#define ADV_INTR_ENABLE_SEL_INTR 0x02
1396#define ADV_INTR_ENABLE_DPR_INTR 0x04
1397#define ADV_INTR_ENABLE_RTA_INTR 0x08
1398#define ADV_INTR_ENABLE_RMA_INTR 0x10
1399#define ADV_INTR_ENABLE_RST_INTR 0x20
1400#define ADV_INTR_ENABLE_DPE_INTR 0x40
1401#define ADV_INTR_ENABLE_GLOBAL_INTR 0x80
1402
1403#define ADV_INTR_STATUS_INTRA 0x01
1404#define ADV_INTR_STATUS_INTRB 0x02
1405#define ADV_INTR_STATUS_INTRC 0x04
1406
1407#define ADV_RISC_CSR_STOP (0x0000)
1408#define ADV_RISC_TEST_COND (0x2000)
1409#define ADV_RISC_CSR_RUN (0x4000)
1410#define ADV_RISC_CSR_SINGLE_STEP (0x8000)
1411
1412#define ADV_CTRL_REG_HOST_INTR 0x0100
1413#define ADV_CTRL_REG_SEL_INTR 0x0200
1414#define ADV_CTRL_REG_DPR_INTR 0x0400
1415#define ADV_CTRL_REG_RTA_INTR 0x0800
1416#define ADV_CTRL_REG_RMA_INTR 0x1000
1417#define ADV_CTRL_REG_RES_BIT14 0x2000
1418#define ADV_CTRL_REG_DPE_INTR 0x4000
1419#define ADV_CTRL_REG_POWER_DONE 0x8000
1420#define ADV_CTRL_REG_ANY_INTR 0xFF00
1421
1422#define ADV_CTRL_REG_CMD_RESET 0x00C6
1423#define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5
1424#define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4
1425#define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3
1426#define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2
1427
1428#define ADV_TICKLE_NOP 0x00
1429#define ADV_TICKLE_A 0x01
1430#define ADV_TICKLE_B 0x02
1431#define ADV_TICKLE_C 0x03
1432
1da177e4
LT		 1433#define AdvIsIntPending(port) \
1434 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1435
1436/*
1437 * SCSI_CFG0 Register bit definitions
1438 */
27c868c2
MW		 1439#define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */
1440#define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */
1441#define EVEN_PARITY 0x1000 /* Select Even Parity */
1442#define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1443#define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */
1444#define PRIM_MODE 0x0100 /* Primitive SCSI mode */
1445#define SCAM_EN 0x0080 /* Enable SCAM selection */
1446#define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1447#define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1448#define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */
1449#define OUR_ID 0x000F /* SCSI ID */
1da177e4
LT		 1450
1451/*
1452 * SCSI_CFG1 Register bit definitions
1453 */
27c868c2
MW		 1454#define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */
1455#define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1456#define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */
1457#define FILTER_SEL 0x0C00 /* Filter Period Selection */
1458#define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */
1459#define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1460#define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1461#define ACTIVE_DBL 0x0200 /* Disable Active Negation */
1462#define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */
1463#define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */
1464#define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */
1465#define TERM_CTL 0x0030 /* External SCSI Termination Bits */
1466#define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */
1467#define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */
1468#define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */
1da177e4
LT		 1469
1470/*
1471 * Addendum for ASC-38C0800 Chip
1472 *
1473 * The ASC-38C1600 Chip uses the same definitions except that the
1474 * bus mode override bits [12:10] have been moved to byte register
1475 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1476 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1477 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1478 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1479 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1480 */
27c868c2
MW		 1481#define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */
1482#define HVD_LVD_SE 0x1C00 /* Device Detect Bits */
1483#define HVD 0x1000 /* HVD Device Detect */
1484#define LVD 0x0800 /* LVD Device Detect */
1485#define SE 0x0400 /* SE Device Detect */
1486#define TERM_LVD 0x00C0 /* LVD Termination Bits */
1487#define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */
1488#define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */
1489#define TERM_SE 0x0030 /* SE Termination Bits */
1490#define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */
1491#define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */
1492#define C_DET_LVD 0x000C /* LVD Cable Detect Bits */
1493#define C_DET3 0x0008 /* Cable Detect for LVD External Wide */
1494#define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */
1495#define C_DET_SE 0x0003 /* SE Cable Detect Bits */
1496#define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */
1497#define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */
1da177e4
LT		 1498
1499#define CABLE_ILLEGAL_A 0x7
1500 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */
1501
1502#define CABLE_ILLEGAL_B 0xB
1503 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */
1504
1505/*
1506 * MEM_CFG Register bit definitions
1507 */
27c868c2
MW		 1508#define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */
1509#define FAST_EE_CLK 0x20 /* Diagnostic Bit */
1510#define RAM_SZ 0x1C /* Specify size of RAM to RISC */
1511#define RAM_SZ_2KB 0x00 /* 2 KB */
1512#define RAM_SZ_4KB 0x04 /* 4 KB */
1513#define RAM_SZ_8KB 0x08 /* 8 KB */
1514#define RAM_SZ_16KB 0x0C /* 16 KB */
1515#define RAM_SZ_32KB 0x10 /* 32 KB */
1516#define RAM_SZ_64KB 0x14 /* 64 KB */
1da177e4
LT		 1517
1518/*
1519 * DMA_CFG0 Register bit definitions
1520 *
1521 * This register is only accessible to the host.
1522 */
27c868c2
MW		 1523#define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */
1524#define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */
1525#define FIFO_THRESH_16B 0x00 /* 16 bytes */
1526#define FIFO_THRESH_32B 0x20 /* 32 bytes */
1527#define FIFO_THRESH_48B 0x30 /* 48 bytes */
1528#define FIFO_THRESH_64B 0x40 /* 64 bytes */
1529#define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */
1530#define FIFO_THRESH_96B 0x60 /* 96 bytes */
1531#define FIFO_THRESH_112B 0x70 /* 112 bytes */
1532#define START_CTL 0x0C /* DMA start conditions */
1533#define START_CTL_TH 0x00 /* Wait threshold level (default) */
1534#define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */
1535#define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */
1536#define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */
1537#define READ_CMD 0x03 /* Memory Read Method */
1538#define READ_CMD_MR 0x00 /* Memory Read */
1539#define READ_CMD_MRL 0x02 /* Memory Read Long */
1540#define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */
1da177e4
LT		 1541
1542/*
1543 * ASC-38C0800 RAM BIST Register bit definitions
1544 */
1545#define RAM_TEST_MODE 0x80
1546#define PRE_TEST_MODE 0x40
1547#define NORMAL_MODE 0x00
1548#define RAM_TEST_DONE 0x10
1549#define RAM_TEST_STATUS 0x0F
1550#define RAM_TEST_HOST_ERROR 0x08
1551#define RAM_TEST_INTRAM_ERROR 0x04
1552#define RAM_TEST_RISC_ERROR 0x02
1553#define RAM_TEST_SCSI_ERROR 0x01
1554#define RAM_TEST_SUCCESS 0x00
1555#define PRE_TEST_VALUE 0x05
1556#define NORMAL_VALUE 0x00
1557
1558/*
1559 * ASC38C1600 Definitions
1560 *
1561 * IOPB_PCI_INT_CFG Bit Field Definitions
1562 */
1563
27c868c2 1564#define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */
1da177e4
LT		 1565
1566/*
1567 * Bit 1 can be set to change the interrupt for the Function to operate in
1568 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1569 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1570 * mode, otherwise the operating mode is undefined.
1571 */
1572#define TOTEMPOLE 0x02
1573
1574/*
1575 * Bit 0 can be used to change the Int Pin for the Function. The value is
1576 * 0 by default for both Functions with Function 0 using INT A and Function
1577 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1578 * INT A is used.
1579 *
1580 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1581 * value specified in the PCI Configuration Space.
1582 */
1583#define INTAB 0x01
1584
1da177e4
LT		 1585/*
1586 * Adv Library Status Definitions
1587 */
1588#define ADV_TRUE 1
1589#define ADV_FALSE 0
1da177e4
LT		 1590#define ADV_SUCCESS 1
1591#define ADV_BUSY 0
1592#define ADV_ERROR (-1)
1593
1da177e4
LT		 1594/*
1595 * ADV_DVC_VAR 'warn_code' values
1596 */
27c868c2
MW		 1597#define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */
1598#define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */
1599#define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */
27c868c2 1600#define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */
1da177e4 1601
27c868c2
MW		 1602#define ADV_MAX_TID 15 /* max. target identifier */
1603#define ADV_MAX_LUN 7 /* max. logical unit number */
1da177e4 1604
1da177e4
LT		 1605/*
1606 * Fixed locations of microcode operating variables.
1607 */
27c868c2
MW		 1608#define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */
1609#define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */
1610#define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */
1611#define ASC_MC_VERSION_DATE 0x0038 /* microcode version */
1612#define ASC_MC_VERSION_NUM 0x003A /* microcode number */
1613#define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */
1614#define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */
1615#define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */
1616#define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */
1617#define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */
1618#define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */
1619#define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */
1620#define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */
1da177e4
LT		 1621#define ASC_MC_CHIP_TYPE 0x009A
1622#define ASC_MC_INTRB_CODE 0x009B
1623#define ASC_MC_WDTR_ABLE 0x009C
1624#define ASC_MC_SDTR_ABLE 0x009E
1625#define ASC_MC_TAGQNG_ABLE 0x00A0
1626#define ASC_MC_DISC_ENABLE 0x00A2
1627#define ASC_MC_IDLE_CMD_STATUS 0x00A4
1628#define ASC_MC_IDLE_CMD 0x00A6
1629#define ASC_MC_IDLE_CMD_PARAMETER 0x00A8
1630#define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC
1631#define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE
1632#define ASC_MC_DEFAULT_MEM_CFG 0x00B0
1633#define ASC_MC_DEFAULT_SEL_MASK 0x00B2
1634#define ASC_MC_SDTR_DONE 0x00B6
1635#define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0
1636#define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0
1637#define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100
27c868c2 1638#define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */
1da177e4 1639#define ASC_MC_WDTR_DONE 0x0124
27c868c2 1640#define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */
1da177e4
LT		 1641#define ASC_MC_ICQ 0x0160
1642#define ASC_MC_IRQ 0x0164
1643#define ASC_MC_PPR_ABLE 0x017A
1644
1645/*
1646 * BIOS LRAM variable absolute offsets.
1647 */
1648#define BIOS_CODESEG 0x54
1649#define BIOS_CODELEN 0x56
1650#define BIOS_SIGNATURE 0x58
1651#define BIOS_VERSION 0x5A
1652
1653/*
1654 * Microcode Control Flags
1655 *
1656 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1657 * and handled by the microcode.
1658 */
27c868c2
MW		 1659#define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */
1660#define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */
1da177e4
LT		 1661
1662/*
1663 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1664 */
1665#define HSHK_CFG_WIDE_XFR 0x8000
1666#define HSHK_CFG_RATE 0x0F00
1667#define HSHK_CFG_OFFSET 0x001F
1668
27c868c2
MW		 1669#define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */
1670#define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */
1671#define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */
1672#define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */
1673
1674#define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1675#define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */
1676#define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1677#define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */
1678#define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1679
1680#define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */
1681#define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */
1682#define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */
1683#define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */
1684#define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */
1da177e4
LT		 1685/*
1686 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1687 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1688 */
27c868c2
MW		 1689#define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */
1690#define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */
1da177e4
LT		 1691
1692/*
1693 * All fields here are accessed by the board microcode and need to be
1694 * little-endian.
1695 */
27c868c2 1696typedef struct adv_carr_t {
98b96a7d
HR		 1697 __le32 carr_va; /* Carrier Virtual Address */
1698 __le32 carr_pa; /* Carrier Physical Address */
9fef6ba4 1699 __le32 areq_vpa; /* ADV_SCSI_REQ_Q Virtual or Physical Address */
27c868c2
MW		 1700 /*
1701 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer
1702 *
1703 * next_vpa [3:1] Reserved Bits
1704 * next_vpa [0] Done Flag set in Response Queue.
1705 */
98b96a7d 1706 __le32 next_vpa;
1da177e4
LT		 1707} ADV_CARR_T;
1708
1709/*
1710 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1711 */
1712#define ASC_NEXT_VPA_MASK 0xFFFFFFF0
1713
1714#define ASC_RQ_DONE 0x00000001
1715#define ASC_RQ_GOOD 0x00000002
1716#define ASC_CQ_STOPPER 0x00000000
1717
1718#define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK)
1719
98b96a7d
HR		 1720/*
1721 * Each carrier is 64 bytes, and we need three additional
1722 * carrier for icq, irq, and the termination carrier.
1723 */
1724#define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3)
1da177e4
LT		 1725
1726#define ADV_CARRIER_BUFSIZE \
98b96a7d 1727 (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T))
1da177e4
LT		 1728
1729/*
9fef6ba4 1730 * ADV_SCSI_REQ_Q 'a_flag' definitions
1da177e4
LT		 1731 *
1732 * The Adv Library should limit use to the lower nibble (4 bits) of
1733 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag.
1734 */
27c868c2
MW		 1735#define ADV_POLL_REQUEST 0x01 /* poll for request completion */
1736#define ADV_SCSIQ_DONE 0x02 /* request done */
1737#define ADV_DONT_RETRY 0x08 /* don't do retry */
1da177e4 1738
27c868c2
MW		 1739#define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */
1740#define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */
1741#define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */
1da177e4
LT		 1742
1743/*
1744 * Adapter temporary configuration structure
1745 *
1746 * This structure can be discarded after initialization. Don't add
1747 * fields here needed after initialization.
1748 *
1749 * Field naming convention:
1750 *
1751 * *_enable indicates the field enables or disables a feature. The
1752 * value of the field is never reset.
1753 */
1754typedef struct adv_dvc_cfg {
27c868c2
MW		 1755 ushort disc_enable; /* enable disconnection */
1756 uchar chip_version; /* chip version */
1757 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
27c868c2
MW		 1758 ushort control_flag; /* Microcode Control Flag */
1759 ushort mcode_date; /* Microcode date */
1760 ushort mcode_version; /* Microcode version */
27c868c2
MW		 1761 ushort serial1; /* EEPROM serial number word 1 */
1762 ushort serial2; /* EEPROM serial number word 2 */
1763 ushort serial3; /* EEPROM serial number word 3 */
1da177e4
LT		 1764} ADV_DVC_CFG;
1765
1766struct adv_dvc_var;
1767struct adv_scsi_req_q;
1768
0ce53822 1769typedef struct adv_sg_block {
27c868c2
MW		 1770 uchar reserved1;
1771 uchar reserved2;
1772 uchar reserved3;
1773 uchar sg_cnt; /* Valid entries in block. */
0ce53822 1774 __le32 sg_ptr; /* Pointer to next sg block. */
27c868c2 1775 struct {
0ce53822
HR		 1776 __le32 sg_addr; /* SG element address. */
1777 __le32 sg_count; /* SG element count. */
27c868c2 1778 } sg_list[NO_OF_SG_PER_BLOCK];
1da177e4
LT		 1779} ADV_SG_BLOCK;
1780
1781/*
1782 * ADV_SCSI_REQ_Q - microcode request structure
1783 *
1784 * All fields in this structure up to byte 60 are used by the microcode.
1785 * The microcode makes assumptions about the size and ordering of fields
1786 * in this structure. Do not change the structure definition here without
1787 * coordinating the change with the microcode.
1788 *
1789 * All fields accessed by microcode must be maintained in little_endian
1790 * order.
1791 */
1792typedef struct adv_scsi_req_q {
27c868c2
MW		 1793 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */
1794 uchar target_cmd;
1795 uchar target_id; /* Device target identifier. */
1796 uchar target_lun; /* Device target logical unit number. */
95cfab6c
HR		 1797 __le32 data_addr; /* Data buffer physical address. */
1798 __le32 data_cnt; /* Data count. Ucode sets to residual. */
811ddc05 1799 __le32 sense_addr;
98b96a7d 1800 __le32 carr_pa;
27c868c2
MW		 1801 uchar mflag;
1802 uchar sense_len;
1803 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */
1804 uchar scsi_cntl;
1805 uchar done_status; /* Completion status. */
1806 uchar scsi_status; /* SCSI status byte. */
1807 uchar host_status; /* Ucode host status. */
1808 uchar sg_working_ix;
1809 uchar cdb[12]; /* SCSI CDB bytes 0-11. */
95cfab6c 1810 __le32 sg_real_addr; /* SG list physical address. */
98b96a7d 1811 __le32 scsiq_rptr;
27c868c2 1812 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */
98b96a7d
HR		 1813 __le32 scsiq_ptr;
1814 __le32 carr_va;
27c868c2
MW		 1815 /*
1816 * End of microcode structure - 60 bytes. The rest of the structure
1817 * is used by the Adv Library and ignored by the microcode.
1818 */
9c17c62a 1819 u32 srb_tag;
27c868c2 1820 uchar a_flag;
98b96a7d
HR		 1821 uchar pad[3]; /* Pad out to a word boundary. */
1822 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */
1da177e4
LT		 1823} ADV_SCSI_REQ_Q;
1824
98d41c29
MW		 1825/*
1826 * The following two structures are used to process Wide Board requests.
1827 *
1828 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
9c17c62a
HR		 1829 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
1830 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
1831 * to the Mid-Level SCSI request structure.
98d41c29
MW		 1832 *
1833 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1834 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1835 * up to 255 scatter-gather elements may be used per request or
1836 * ADV_SCSI_REQ_Q.
1837 *
1838 * Both structures must be 32 byte aligned.
1839 */
1840typedef struct adv_sgblk {
1841 ADV_SG_BLOCK sg_block; /* Sgblock structure. */
0ce53822 1842 dma_addr_t sg_addr; /* Physical address */
98d41c29
MW		 1843 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */
1844} adv_sgblk_t;
1845
1846typedef struct adv_req {
1847 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */
4b47e464 1848 uchar align[24]; /* Request structure padding. */
98d41c29 1849 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */
4b47e464 1850 dma_addr_t req_addr;
98d41c29 1851 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */
4b47e464 1852} adv_req_t __aligned(32);
98d41c29
MW		 1853
1854/*
1855 * Adapter operation variable structure.
1856 *
1857 * One structure is required per host adapter.
1858 *
1859 * Field naming convention:
1860 *
1861 * *_able indicates both whether a feature should be enabled or disabled
1862 * and whether a device isi capable of the feature. At initialization
1863 * this field may be set, but later if a device is found to be incapable
1864 * of the feature, the field is cleared.
1865 */
1866typedef struct adv_dvc_var {
1867 AdvPortAddr iop_base; /* I/O port address */
1868 ushort err_code; /* fatal error code */
1869 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */
1870 ushort wdtr_able; /* try WDTR for a device */
1871 ushort sdtr_able; /* try SDTR for a device */
1872 ushort ultra_able; /* try SDTR Ultra speed for a device */
1873 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */
1874 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */
1875 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */
1876 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */
1877 ushort tagqng_able; /* try tagged queuing with a device */
1878 ushort ppr_able; /* PPR message capable per TID bitmask. */
1879 uchar max_dvc_qng; /* maximum number of tagged commands per device */
1880 ushort start_motor; /* start motor command allowed */
1881 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */
1882 uchar chip_no; /* should be assigned by caller */
1883 uchar max_host_qng; /* maximum number of Q'ed command allowed */
1884 ushort no_scam; /* scam_tolerant of EEPROM */
1885 struct asc_board *drv_ptr; /* driver pointer to private structure */
1886 uchar chip_scsi_id; /* chip SCSI target ID */
1887 uchar chip_type;
1888 uchar bist_err_code;
98b96a7d 1889 ADV_CARR_T *carrier;
98d41c29 1890 ADV_CARR_T *carr_freelist; /* Carrier free list. */
98b96a7d 1891 dma_addr_t carrier_addr;
98d41c29
MW		 1892 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */
1893 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */
1894 ushort carr_pending_cnt; /* Count of pending carriers. */
98d41c29
MW		 1895 /*
1896 * Note: The following fields will not be used after initialization. The
1897 * driver may discard the buffer after initialization is done.
1898 */
1899 ADV_DVC_CFG *cfg; /* temporary configuration structure */
1900} ADV_DVC_VAR;
1901
1da177e4
LT		 1902/*
1903 * Microcode idle loop commands
1904 */
1905#define IDLE_CMD_COMPLETED 0
1906#define IDLE_CMD_STOP_CHIP 0x0001
1907#define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002
1908#define IDLE_CMD_SEND_INT 0x0004
1909#define IDLE_CMD_ABORT 0x0008
1910#define IDLE_CMD_DEVICE_RESET 0x0010
27c868c2
MW		 1911#define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */
1912#define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */
1da177e4
LT		 1913#define IDLE_CMD_SCSIREQ 0x0080
1914
1915#define IDLE_CMD_STATUS_SUCCESS 0x0001
1916#define IDLE_CMD_STATUS_FAILURE 0x0002
1917
1918/*
1919 * AdvSendIdleCmd() flag definitions.
1920 */
1921#define ADV_NOWAIT 0x01
1922
1923/*
1924 * Wait loop time out values.
1925 */
27c868c2
MW		 1926#define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */
1927#define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */
27c868c2 1928#define SCSI_MAX_RETRY 10 /* retry count */
1da177e4 1929
27c868c2
MW		 1930#define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */
1931#define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */
1932#define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */
1933#define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */
1da177e4 1934
27c868c2 1935#define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */
1da177e4 1936
1da177e4
LT		 1937/* Read byte from a register. */
1938#define AdvReadByteRegister(iop_base, reg_off) \
1939 (ADV_MEM_READB((iop_base) + (reg_off)))
1940
1941/* Write byte to a register. */
1942#define AdvWriteByteRegister(iop_base, reg_off, byte) \
1943 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1944
1945/* Read word (2 bytes) from a register. */
1946#define AdvReadWordRegister(iop_base, reg_off) \
1947 (ADV_MEM_READW((iop_base) + (reg_off)))
1948
1949/* Write word (2 bytes) to a register. */
1950#define AdvWriteWordRegister(iop_base, reg_off, word) \
1951 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
1952
1953/* Write dword (4 bytes) to a register. */
1954#define AdvWriteDWordRegister(iop_base, reg_off, dword) \
1955 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
1956
1957/* Read byte from LRAM. */
1958#define AdvReadByteLram(iop_base, addr, byte) \
1959do { \
1960 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1961 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
1962} while (0)
1963
1964/* Write byte to LRAM. */
1965#define AdvWriteByteLram(iop_base, addr, byte) \
1966 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1967 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
1968
1969/* Read word (2 bytes) from LRAM. */
1970#define AdvReadWordLram(iop_base, addr, word) \
1971do { \
1972 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1973 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
1974} while (0)
1975
1976/* Write word (2 bytes) to LRAM. */
1977#define AdvWriteWordLram(iop_base, addr, word) \
1978 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1979 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1980
1981/* Write little-endian double word (4 bytes) to LRAM */
1982/* Because of unspecified C language ordering don't use auto-increment. */
1983#define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
1984 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1985 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1986 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
1987 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
1988 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1989 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
1990
1991/* Read word (2 bytes) from LRAM assuming that the address is already set. */
1992#define AdvReadWordAutoIncLram(iop_base) \
1993 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
1994
1995/* Write word (2 bytes) to LRAM assuming that the address is already set. */
1996#define AdvWriteWordAutoIncLram(iop_base, word) \
1997 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1998
1da177e4
LT		 1999/*
2000 * Define macro to check for Condor signature.
2001 *
2002 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
2003 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
2004 */
2005#define AdvFindSignature(iop_base) \
2006 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
2007 ADV_CHIP_ID_BYTE) && \
2008 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
2009 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE)
2010
2011/*
2012 * Define macro to Return the version number of the chip at 'iop_base'.
2013 *
2014 * The second parameter 'bus_type' is currently unused.
2015 */
2016#define AdvGetChipVersion(iop_base, bus_type) \
2017 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
2018
2019/*
9c17c62a 2020 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
9fef6ba4 2021 * match the ADV_SCSI_REQ_Q 'srb_tag' field.
1da177e4
LT		 2022 *
2023 * If the request has not yet been sent to the device it will simply be
2024 * aborted from RISC memory. If the request is disconnected it will be
2025 * aborted on reselection by sending an Abort Message to the target ID.
2026 *
2027 * Return value:
2028 * ADV_TRUE(1) - Queue was successfully aborted.
2029 * ADV_FALSE(0) - Queue was not found on the active queue list.
2030 */
9c17c62a
HR		 2031#define AdvAbortQueue(asc_dvc, srb_tag) \
2032 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
2033 (ADV_DCNT) (srb_tag))
1da177e4
LT		 2034
2035/*
2036 * Send a Bus Device Reset Message to the specified target ID.
2037 *
2038 * All outstanding commands will be purged if sending the
2039 * Bus Device Reset Message is successful.
2040 *
2041 * Return Value:
2042 * ADV_TRUE(1) - All requests on the target are purged.
2043 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
2044 * are not purged.
2045 */
2046#define AdvResetDevice(asc_dvc, target_id) \
9c17c62a
HR		 2047 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \
2048 (ADV_DCNT) (target_id))
1da177e4
LT		 2049
2050/*
2051 * SCSI Wide Type definition.
2052 */
2053#define ADV_SCSI_BIT_ID_TYPE ushort
2054
2055/*
2056 * AdvInitScsiTarget() 'cntl_flag' options.
2057 */
2058#define ADV_SCAN_LUN 0x01
2059#define ADV_CAPINFO_NOLUN 0x02
2060
2061/*
2062 * Convert target id to target id bit mask.
2063 */
2064#define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID))
2065
2066/*
9fef6ba4 2067 * ADV_SCSI_REQ_Q 'done_status' and 'host_status' return values.
1da177e4
LT		 2068 */
2069
27c868c2 2070#define QD_NO_STATUS 0x00 /* Request not completed yet. */
1da177e4
LT		 2071#define QD_NO_ERROR 0x01
2072#define QD_ABORTED_BY_HOST 0x02
2073#define QD_WITH_ERROR 0x04
2074
2075#define QHSTA_NO_ERROR 0x00
2076#define QHSTA_M_SEL_TIMEOUT 0x11
2077#define QHSTA_M_DATA_OVER_RUN 0x12
2078#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2079#define QHSTA_M_QUEUE_ABORTED 0x15
27c868c2
MW		 2080#define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */
2081#define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */
2082#define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */
2083#define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */
2084#define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */
2085#define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */
2086#define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */
1da177e4 2087/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
27c868c2
MW		 2088#define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */
2089#define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */
2090#define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */
2091#define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */
2092#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */
2093#define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */
2094#define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */
2095#define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */
1da177e4
LT		 2096#define QHSTA_M_WTM_TIMEOUT 0x41
2097#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42
2098#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43
2099#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
27c868c2
MW		 2100#define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */
2101#define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */
2102#define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */
1da177e4 2103
1da177e4 2104/* Return the address that is aligned at the next doubleword >= to 'addr'. */
1da177e4
LT		 2105#define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F)
2106
2107/*
2108 * Total contiguous memory needed for driver SG blocks.
2109 *
2110 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2111 * number of scatter-gather elements the driver supports in a
2112 * single request.
2113 */
2114
2115#define ADV_SG_LIST_MAX_BYTE_SIZE \
2116 (sizeof(ADV_SG_BLOCK) * \
2117 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2118
d2411495 2119/* struct asc_board flags */
27c868c2 2120#define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */
1da177e4
LT		 2121
2122#define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
1da177e4 2123
27c868c2 2124#define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */
1da177e4 2125
27c868c2 2126#define ASC_INFO_SIZE 128 /* advansys_info() line size */
1da177e4 2127
1da177e4
LT		 2128/* Asc Library return codes */
2129#define ASC_TRUE 1
2130#define ASC_FALSE 0
2131#define ASC_NOERROR 1
2132#define ASC_BUSY 0
2133#define ASC_ERROR (-1)
2134
2135/* struct scsi_cmnd function return codes */
2136#define STATUS_BYTE(byte) (byte)
2137#define MSG_BYTE(byte) ((byte) << 8)
2138#define HOST_BYTE(byte) ((byte) << 16)
2139#define DRIVER_BYTE(byte) ((byte) << 24)
2140
d2411495 2141#define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
1da177e4 2142#ifndef ADVANSYS_STATS
27c868c2 2143#define ASC_STATS_ADD(shost, counter, count)
1da177e4 2144#else /* ADVANSYS_STATS */
27c868c2 2145#define ASC_STATS_ADD(shost, counter, count) \
d2411495 2146 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
1da177e4
LT		 2147#endif /* ADVANSYS_STATS */
2148
1da177e4
LT		 2149/* If the result wraps when calculating tenths, return 0. */
2150#define ASC_TENTHS(num, den) \
2151 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2152 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2153
2154/*
2155 * Display a message to the console.
2156 */
2157#define ASC_PRINT(s) \
2158 { \
2159 printk("advansys: "); \
2160 printk(s); \
2161 }
2162
2163#define ASC_PRINT1(s, a1) \
2164 { \
2165 printk("advansys: "); \
2166 printk((s), (a1)); \
2167 }
2168
2169#define ASC_PRINT2(s, a1, a2) \
2170 { \
2171 printk("advansys: "); \
2172 printk((s), (a1), (a2)); \
2173 }
2174
2175#define ASC_PRINT3(s, a1, a2, a3) \
2176 { \
2177 printk("advansys: "); \
2178 printk((s), (a1), (a2), (a3)); \
2179 }
2180
2181#define ASC_PRINT4(s, a1, a2, a3, a4) \
2182 { \
2183 printk("advansys: "); \
2184 printk((s), (a1), (a2), (a3), (a4)); \
2185 }
2186
1da177e4
LT		 2187#ifndef ADVANSYS_DEBUG
2188
b352f923 2189#define ASC_DBG(lvl, s...)
1da177e4 2190#define ASC_DBG_PRT_SCSI_HOST(lvl, s)
1da177e4
LT		 2191#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2192#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2193#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2194#define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2195#define ASC_DBG_PRT_HEX(lvl, name, start, length)
2196#define ASC_DBG_PRT_CDB(lvl, cdb, len)
2197#define ASC_DBG_PRT_SENSE(lvl, sense, len)
2198#define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2199
2200#else /* ADVANSYS_DEBUG */
2201
2202/*
2203 * Debugging Message Levels:
2204 * 0: Errors Only
2205 * 1: High-Level Tracing
2206 * 2-N: Verbose Tracing
2207 */
2208
b352f923
MW		 2209#define ASC_DBG(lvl, format, arg...) { \
2210 if (asc_dbglvl >= (lvl)) \
2211 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \
cadbd4a5 2212 __func__ , ## arg); \
b352f923 2213}
1da177e4
LT		 2214
2215#define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2216 { \
2217 if (asc_dbglvl >= (lvl)) { \
2218 asc_prt_scsi_host(s); \
2219 } \
2220 }
2221
1da177e4
LT		 2222#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2223 { \
2224 if (asc_dbglvl >= (lvl)) { \
2225 asc_prt_asc_scsi_q(scsiqp); \
2226 } \
2227 }
2228
2229#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2230 { \
2231 if (asc_dbglvl >= (lvl)) { \
2232 asc_prt_asc_qdone_info(qdone); \
2233 } \
2234 }
2235
2236#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2237 { \
2238 if (asc_dbglvl >= (lvl)) { \
2239 asc_prt_adv_scsi_req_q(scsiqp); \
2240 } \
2241 }
2242
2243#define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2244 { \
2245 if (asc_dbglvl >= (lvl)) { \
2246 asc_prt_hex((name), (start), (length)); \
2247 } \
2248 }
2249
2250#define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2251 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2252
2253#define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2254 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2255
2256#define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2257 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2258#endif /* ADVANSYS_DEBUG */
2259
1da177e4
LT		 2260#ifdef ADVANSYS_STATS
2261
2262/* Per board statistics structure */
2263struct asc_stats {
27c868c2 2264 /* Driver Entrypoint Statistics */
95cfab6c
HR		 2265 unsigned int queuecommand; /* # calls to advansys_queuecommand() */
2266 unsigned int reset; /* # calls to advansys_eh_bus_reset() */
2267 unsigned int biosparam; /* # calls to advansys_biosparam() */
2268 unsigned int interrupt; /* # advansys_interrupt() calls */
2269 unsigned int callback; /* # calls to asc/adv_isr_callback() */
2270 unsigned int done; /* # calls to request's scsi_done function */
2271 unsigned int build_error; /* # asc/adv_build_req() ASC_ERROR returns. */
2272 unsigned int adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */
2273 unsigned int adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */
27c868c2 2274 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
95cfab6c
HR		 2275 unsigned int exe_noerror; /* # ASC_NOERROR returns. */
2276 unsigned int exe_busy; /* # ASC_BUSY returns. */
2277 unsigned int exe_error; /* # ASC_ERROR returns. */
2278 unsigned int exe_unknown; /* # unknown returns. */
27c868c2 2279 /* Data Transfer Statistics */
95cfab6c
HR		 2280 unsigned int xfer_cnt; /* # I/O requests received */
2281 unsigned int xfer_elem; /* # scatter-gather elements */
2282 unsigned int xfer_sect; /* # 512-byte blocks */
1da177e4
LT		 2283};
2284#endif /* ADVANSYS_STATS */
2285
1da177e4
LT		 2286/*
2287 * Structure allocated for each board.
2288 *
8dfb5379 2289 * This structure is allocated by scsi_host_alloc() at the end
1da177e4
LT		 2290 * of the 'Scsi_Host' structure starting at the 'hostdata'
2291 * field. It is guaranteed to be allocated from DMA-able memory.
2292 */
d2411495 2293struct asc_board {
394dbf3f 2294 struct device *dev;
9c17c62a 2295 struct Scsi_Host *shost;
27c868c2 2296 uint flags; /* Board flags */
d361db48 2297 unsigned int irq;
27c868c2
MW		 2298 union {
2299 ASC_DVC_VAR asc_dvc_var; /* Narrow board */
2300 ADV_DVC_VAR adv_dvc_var; /* Wide board */
2301 } dvc_var;
2302 union {
2303 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */
2304 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */
2305 } dvc_cfg;
2306 ushort asc_n_io_port; /* Number I/O ports. */
27c868c2 2307 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */
27c868c2
MW		 2308 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2309 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */
2310 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2311 union {
2312 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */
2313 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */
2314 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */
2315 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */
2316 } eep_config;
27c868c2 2317 /* /proc/scsi/advansys/[0...] */
1da177e4 2318#ifdef ADVANSYS_STATS
27c868c2
MW		 2319 struct asc_stats asc_stats; /* Board statistics */
2320#endif /* ADVANSYS_STATS */
2321 /*
2322 * The following fields are used only for Narrow Boards.
2323 */
27c868c2
MW		 2324 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */
2325 /*
2326 * The following fields are used only for Wide Boards.
2327 */
2328 void __iomem *ioremap_addr; /* I/O Memory remap address. */
2329 ushort ioport; /* I/O Port address. */
27c868c2 2330 adv_req_t *adv_reqp; /* Request structures. */
4b47e464
HR		 2331 dma_addr_t adv_reqp_addr;
2332 size_t adv_reqp_size;
0ce53822 2333 struct dma_pool *adv_sgblk_pool; /* Scatter-gather structures. */
27c868c2
MW		 2334 ushort bios_signature; /* BIOS Signature. */
2335 ushort bios_version; /* BIOS Version. */
2336 ushort bios_codeseg; /* BIOS Code Segment. */
2337 ushort bios_codelen; /* BIOS Code Segment Length. */
d2411495 2338};
1da177e4 2339
d10fb2c7
MW		 2340#define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2341 dvc_var.asc_dvc_var)
13ac2d9c
MW		 2342#define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2343 dvc_var.adv_dvc_var)
2344#define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2345
1da177e4 2346#ifdef ADVANSYS_DEBUG
27c868c2 2347static int asc_dbglvl = 3;
1da177e4 2348
1da177e4 2349/*
51219358 2350 * asc_prt_asc_dvc_var()
1da177e4 2351 */
51219358 2352static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
1da177e4 2353{
51219358 2354 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
27c868c2 2355
51219358
MW		 2356 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2357 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2358
2359 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2360 (unsigned)h->init_sdtr);
2361
2362 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2363 "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2364 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2365 (unsigned)h->chip_no);
2366
2367 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2368 "%u,\n", (unsigned)h->queue_full_or_busy,
2369 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2370
2371 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2372 "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2373 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2374 (unsigned)h->in_critical_cnt);
2375
2376 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2377 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2378 (unsigned)h->init_state, (unsigned)h->no_scam,
2379 (unsigned)h->pci_fix_asyn_xfer);
2380
d361db48 2381 printk(" cfg 0x%lx\n", (ulong)h->cfg);
1da177e4
LT		 2382}
2383
51219358
MW		 2384/*
2385 * asc_prt_asc_dvc_cfg()
2386 */
2387static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
6ed1ef07 2388{
51219358 2389 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
6ed1ef07 2390
51219358
MW		 2391 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2392 h->can_tagged_qng, h->cmd_qng_enabled);
2393 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2394 h->disc_enable, h->sdtr_enable);
6ed1ef07 2395
b08fc565
MW		 2396 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, "
2397 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed,
2398 h->isa_dma_channel, h->chip_version);
51219358 2399
d10fb2c7
MW		 2400 printk(" mcode_date 0x%x, mcode_version %d\n",
2401 h->mcode_date, h->mcode_version);
6ed1ef07
MW		 2402}
2403
1da177e4 2404/*
51219358 2405 * asc_prt_adv_dvc_var()
1da177e4 2406 *
51219358 2407 * Display an ADV_DVC_VAR structure.
1da177e4 2408 */
51219358 2409static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
1da177e4 2410{
51219358 2411 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
27c868c2 2412
51219358
MW		 2413 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2414 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
1da177e4 2415
b352f923
MW		 2416 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n",
2417 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
1da177e4 2418
d361db48
MW		 2419 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n",
2420 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
1da177e4 2421
98b96a7d 2422 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n",
51219358 2423 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
98b96a7d 2424 h->carr_freelist);
1da177e4 2425
98b96a7d 2426 printk(" icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp);
1da177e4 2427
51219358
MW		 2428 printk(" no_scam 0x%x, tagqng_able 0x%x\n",
2429 (unsigned)h->no_scam, (unsigned)h->tagqng_able);
1da177e4 2430
51219358
MW		 2431 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n",
2432 (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2433}
1da177e4 2434
51219358
MW		 2435/*
2436 * asc_prt_adv_dvc_cfg()
2437 *
2438 * Display an ADV_DVC_CFG structure.
2439 */
2440static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2441{
2442 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
27c868c2 2443
51219358
MW		 2444 printk(" disc_enable 0x%x, termination 0x%x\n",
2445 h->disc_enable, h->termination);
1da177e4 2446
51219358
MW		 2447 printk(" chip_version 0x%x, mcode_date 0x%x\n",
2448 h->chip_version, h->mcode_date);
27c868c2 2449
b352f923
MW		 2450 printk(" mcode_version 0x%x, control_flag 0x%x\n",
2451 h->mcode_version, h->control_flag);
1da177e4
LT		 2452}
2453
2454/*
b352f923 2455 * asc_prt_scsi_host()
1da177e4 2456 */
b352f923 2457static void asc_prt_scsi_host(struct Scsi_Host *s)
1da177e4 2458{
b352f923 2459 struct asc_board *boardp = shost_priv(s);
51219358 2460
71610f55 2461 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
50d14a70 2462 printk(" host_busy %u, host_no %d,\n",
74665016 2463 atomic_read(&s->host_busy), s->host_no);
51219358 2464
b352f923
MW		 2465 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2466 (ulong)s->base, (ulong)s->io_port, boardp->irq);
51219358 2467
b352f923
MW		 2468 printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2469 s->dma_channel, s->this_id, s->can_queue);
1da177e4 2470
b352f923
MW		 2471 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n",
2472 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma);
27c868c2 2473
b352f923
MW		 2474 if (ASC_NARROW_BOARD(boardp)) {
2475 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2476 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2477 } else {
2478 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2479 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
074c8fe4 2480 }
1da177e4
LT		 2481}
2482
51219358
MW		 2483/*
2484 * asc_prt_hex()
2485 *
2486 * Print hexadecimal output in 4 byte groupings 32 bytes
2487 * or 8 double-words per line.
2488 */
2489static void asc_prt_hex(char *f, uchar *s, int l)
47d853cc 2490{
51219358
MW		 2491 int i;
2492 int j;
2493 int k;
2494 int m;
47d853cc 2495
51219358
MW		 2496 printk("%s: (%d bytes)\n", f, l);
2497
2498 for (i = 0; i < l; i += 32) {
2499
2500 /* Display a maximum of 8 double-words per line. */
2501 if ((k = (l - i) / 4) >= 8) {
2502 k = 8;
2503 m = 0;
47d853cc 2504 } else {
51219358 2505 m = (l - i) % 4;
47d853cc
MW		 2506 }
2507
51219358
MW		 2508 for (j = 0; j < k; j++) {
2509 printk(" %2.2X%2.2X%2.2X%2.2X",
2510 (unsigned)s[i + (j * 4)],
2511 (unsigned)s[i + (j * 4) + 1],
2512 (unsigned)s[i + (j * 4) + 2],
2513 (unsigned)s[i + (j * 4) + 3]);
47d853cc 2514 }
47d853cc 2515
51219358
MW		 2516 switch (m) {
2517 case 0:
2518 default:
2519 break;
2520 case 1:
2521 printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2522 break;
2523 case 2:
2524 printk(" %2.2X%2.2X",
2525 (unsigned)s[i + (j * 4)],
2526 (unsigned)s[i + (j * 4) + 1]);
2527 break;
2528 case 3:
2529 printk(" %2.2X%2.2X%2.2X",
2530 (unsigned)s[i + (j * 4) + 1],
2531 (unsigned)s[i + (j * 4) + 2],
2532 (unsigned)s[i + (j * 4) + 3]);
2533 break;
2534 }
47d853cc 2535
51219358 2536 printk("\n");
47d853cc
MW		 2537 }
2538}
b352f923
MW		 2539
2540/*
2541 * asc_prt_asc_scsi_q()
2542 */
2543static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2544{
2545 ASC_SG_HEAD *sgp;
2546 int i;
2547
2548 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2549
2550 printk
9c17c62a
HR		 2551 (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
2552 q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
b352f923
MW		 2553 q->q2.tag_code);
2554
2555 printk
2556 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2557 (ulong)le32_to_cpu(q->q1.data_addr),
2558 (ulong)le32_to_cpu(q->q1.data_cnt),
2559 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2560
2561 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2562 (ulong)q->cdbptr, q->q2.cdb_len,
2563 (ulong)q->sg_head, q->q1.sg_queue_cnt);
2564
2565 if (q->sg_head) {
2566 sgp = q->sg_head;
2567 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2568 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2569 sgp->queue_cnt);
2570 for (i = 0; i < sgp->entry_cnt; i++) {
2571 printk(" [%u]: addr 0x%lx, bytes %lu\n",
2572 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2573 (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2574 }
2575
2576 }
2577}
2578
2579/*
2580 * asc_prt_asc_qdone_info()
2581 */
2582static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2583{
2584 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
9c17c62a
HR		 2585 printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
2586 q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
b352f923
MW		 2587 q->d2.tag_code);
2588 printk
2589 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2590 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2591}
2592
2593/*
2594 * asc_prt_adv_sgblock()
2595 *
2596 * Display an ADV_SG_BLOCK structure.
2597 */
2598static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2599{
2600 int i;
2601
0ce53822 2602 printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
b352f923
MW		 2603 (ulong)b, sgblockno);
2604 printk(" sg_cnt %u, sg_ptr 0x%lx\n",
2605 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr));
2606 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2607 if (b->sg_ptr != 0)
2608 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2609 for (i = 0; i < b->sg_cnt; i++) {
2610 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n",
2611 i, (ulong)b->sg_list[i].sg_addr,
2612 (ulong)b->sg_list[i].sg_count);
2613 }
2614}
2615
2616/*
2617 * asc_prt_adv_scsi_req_q()
2618 *
2619 * Display an ADV_SCSI_REQ_Q structure.
2620 */
2621static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2622{
2623 int sg_blk_cnt;
0ce53822
HR		 2624 struct adv_sg_block *sg_ptr;
2625 adv_sgblk_t *sgblkp;
b352f923
MW		 2626
2627 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2628
9c17c62a
HR		 2629 printk(" target_id %u, target_lun %u, srb_tag 0x%x, a_flag 0x%x\n",
2630 q->target_id, q->target_lun, q->srb_tag, q->a_flag);
b352f923 2631
98b96a7d
HR		 2632 printk(" cntl 0x%x, data_addr 0x%lx\n",
2633 q->cntl, (ulong)le32_to_cpu(q->data_addr));
b352f923
MW		 2634
2635 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2636 (ulong)le32_to_cpu(q->data_cnt),
2637 (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2638
2639 printk
2640 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2641 q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2642
2643 printk(" sg_working_ix 0x%x, target_cmd %u\n",
2644 q->sg_working_ix, q->target_cmd);
2645
2646 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2647 (ulong)le32_to_cpu(q->scsiq_rptr),
2648 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2649
2650 /* Display the request's ADV_SG_BLOCK structures. */
2651 if (q->sg_list_ptr != NULL) {
0ce53822 2652 sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block);
b352f923 2653 sg_blk_cnt = 0;
0ce53822
HR		 2654 while (sgblkp) {
2655 sg_ptr = &sgblkp->sg_block;
b352f923
MW		 2656 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2657 if (sg_ptr->sg_ptr == 0) {
2658 break;
2659 }
0ce53822 2660 sgblkp = sgblkp->next_sgblkp;
b352f923
MW		 2661 sg_blk_cnt++;
2662 }
2663 }
2664}
51219358 2665#endif /* ADVANSYS_DEBUG */
47d853cc 2666
1da177e4 2667/*
51219358 2668 * advansys_info()
47d853cc 2669 *
51219358
MW		 2670 * Return suitable for printing on the console with the argument
2671 * adapter's configuration information.
2672 *
2673 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2674 * otherwise the static 'info' array will be overrun.
1da177e4 2675 */
51219358 2676static const char *advansys_info(struct Scsi_Host *shost)
1da177e4 2677{
51219358 2678 static char info[ASC_INFO_SIZE];
d2411495 2679 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2680 ASC_DVC_VAR *asc_dvc_varp;
2681 ADV_DVC_VAR *adv_dvc_varp;
2682 char *busname;
2683 char *widename = NULL;
1da177e4 2684
51219358
MW		 2685 if (ASC_NARROW_BOARD(boardp)) {
2686 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
b352f923 2687 ASC_DBG(1, "begin\n");
51219358
MW		 2688 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
2689 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) ==
2690 ASC_IS_ISAPNP) {
2691 busname = "ISA PnP";
2692 } else {
2693 busname = "ISA";
2694 }
2695 sprintf(info,
2696 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X",
2697 ASC_VERSION, busname,
2698 (ulong)shost->io_port,
2699 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
d361db48 2700 boardp->irq, shost->dma_channel);
51219358
MW		 2701 } else {
2702 if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2703 busname = "VL";
2704 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2705 busname = "EISA";
2706 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2707 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2708 == ASC_IS_PCI_ULTRA) {
2709 busname = "PCI Ultra";
2710 } else {
2711 busname = "PCI";
2712 }
2713 } else {
2714 busname = "?";
9d0e96eb
MW		 2715 shost_printk(KERN_ERR, shost, "unknown bus "
2716 "type %d\n", asc_dvc_varp->bus_type);
51219358
MW		 2717 }
2718 sprintf(info,
2719 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2720 ASC_VERSION, busname, (ulong)shost->io_port,
2721 (ulong)shost->io_port + ASC_IOADR_GAP - 1,
d361db48 2722 boardp->irq);
51219358
MW		 2723 }
2724 } else {
2725 /*
2726 * Wide Adapter Information
2727 *
2728 * Memory-mapped I/O is used instead of I/O space to access
2729 * the adapter, but display the I/O Port range. The Memory
2730 * I/O address is displayed through the driver /proc file.
2731 */
2732 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2733 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2734 widename = "Ultra-Wide";
2735 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2736 widename = "Ultra2-Wide";
2737 } else {
2738 widename = "Ultra3-Wide";
2739 }
2740 sprintf(info,
2741 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2742 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
d361db48 2743 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
51219358
MW		 2744 }
2745 BUG_ON(strlen(info) >= ASC_INFO_SIZE);
b352f923 2746 ASC_DBG(1, "end\n");
51219358 2747 return info;
47d853cc
MW		 2748}
2749
51219358 2750#ifdef CONFIG_PROC_FS
47d853cc
MW		 2751
2752/*
51219358 2753 * asc_prt_board_devices()
47d853cc 2754 *
51219358 2755 * Print driver information for devices attached to the board.
47d853cc 2756 */
b59fb6fd 2757static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
47d853cc 2758{
d2411495 2759 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2760 int chip_scsi_id;
2761 int i;
47d853cc 2762
b59fb6fd
AV		 2763 seq_printf(m,
2764 "\nDevice Information for AdvanSys SCSI Host %d:\n",
2765 shost->host_no);
47d853cc 2766
51219358
MW		 2767 if (ASC_NARROW_BOARD(boardp)) {
2768 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2769 } else {
2770 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
47d853cc
MW		 2771 }
2772
2f979427 2773 seq_puts(m, "Target IDs Detected:");
51219358 2774 for (i = 0; i <= ADV_MAX_TID; i++) {
b59fb6fd
AV		 2775 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2776 seq_printf(m, " %X,", i);
27c868c2 2777 }
b59fb6fd 2778 seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
47d853cc
MW		 2779}
2780
2781/*
51219358 2782 * Display Wide Board BIOS Information.
47d853cc 2783 */
b59fb6fd 2784static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
47d853cc 2785{
d2411495 2786 struct asc_board *boardp = shost_priv(shost);
51219358
MW		 2787 ushort major, minor, letter;
2788
2f979427 2789 seq_puts(m, "\nROM BIOS Version: ");
47d853cc
MW		 2790
2791 /*
51219358
MW		 2792 * If the BIOS saved a valid signature, then fill in
2793 * the BIOS code segment base address.
47d853cc 2794 */
51219358 2795 if (boardp->bios_signature != 0x55AA) {
3d30079c
RV		 2796 seq_puts(m, "Disabled or Pre-3.1\n"
2797 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2798 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
51219358
MW		 2799 } else {
2800 major = (boardp->bios_version >> 12) & 0xF;
2801 minor = (boardp->bios_version >> 8) & 0xF;
2802 letter = (boardp->bios_version & 0xFF);
47d853cc 2803
b59fb6fd 2804 seq_printf(m, "%d.%d%c\n",
51219358
MW		 2805 major, minor,
2806 letter >= 26 ? '?' : letter + 'A');
51219358
MW		 2807 /*
2808 * Current available ROM BIOS release is 3.1I for UW
2809 * and 3.2I for U2W. This code doesn't differentiate
2810 * UW and U2W boards.
2811 */
2812 if (major < 3 || (major <= 3 && minor < 1) ||
2813 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
3d30079c
RV		 2814 seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2815 "ftp://ftp.connectcom.net/pub\n");
51219358
MW		 2816 }
2817 }
1da177e4
LT		 2818}
2819
1da177e4 2820/*
51219358
MW		 2821 * Add serial number to information bar if signature AAh
2822 * is found in at bit 15-9 (7 bits) of word 1.
1da177e4 2823 *
51219358 2824 * Serial Number consists fo 12 alpha-numeric digits.
1da177e4 2825 *
51219358
MW		 2826 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits)
2827 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits)
2828 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits)
2829 * 5 - Product revision (A-J) Word0: " "
1da177e4 2830 *
51219358
MW		 2831 * Signature Word1: 15-9 (7 bits)
2832 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2833 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits)
1da177e4 2834 *
51219358 2835 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
1da177e4 2836 *
51219358 2837 * Note 1: Only production cards will have a serial number.
1da177e4 2838 *
51219358 2839 * Note 2: Signature is most significant 7 bits (0xFE).
1da177e4 2840 *
51219358 2841 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
1da177e4 2842 */
51219358 2843static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
1da177e4 2844{
51219358 2845 ushort w, num;
27c868c2 2846
51219358
MW		 2847 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2848 return ASC_FALSE;
2849 } else {
2850 /*
2851 * First word - 6 digits.
2852 */
2853 w = serialnum[0];
27c868c2 2854
51219358
MW		 2855 /* Product type - 1st digit. */
2856 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2857 /* Product type is P=Prototype */
2858 *cp += 0x8;
2859 }
2860 cp++;
2861
2862 /* Manufacturing location - 2nd digit. */
2863 *cp++ = 'A' + ((w & 0x1C00) >> 10);
2864
2865 /* Product ID - 3rd, 4th digits. */
2866 num = w & 0x3FF;
2867 *cp++ = '0' + (num / 100);
2868 num %= 100;
2869 *cp++ = '0' + (num / 10);
2870
2871 /* Product revision - 5th digit. */
2872 *cp++ = 'A' + (num % 10);
27c868c2 2873
27c868c2 2874 /*
51219358 2875 * Second word
27c868c2 2876 */
51219358 2877 w = serialnum[1];
27c868c2
MW		 2878
2879 /*
51219358 2880 * Year - 6th digit.
27c868c2 2881 *
51219358
MW		 2882 * If bit 15 of third word is set, then the
2883 * last digit of the year is greater than 7.
27c868c2 2884 */
51219358
MW		 2885 if (serialnum[2] & 0x8000) {
2886 *cp++ = '8' + ((w & 0x1C0) >> 6);
2887 } else {
2888 *cp++ = '0' + ((w & 0x1C0) >> 6);
27c868c2
MW		 2889 }
2890
51219358
MW		 2891 /* Week of year - 7th, 8th digits. */
2892 num = w & 0x003F;
2893 *cp++ = '0' + num / 10;
2894 num %= 10;
2895 *cp++ = '0' + num;
27c868c2
MW		 2896
2897 /*
51219358 2898 * Third word
27c868c2 2899 */
51219358 2900 w = serialnum[2] & 0x7FFF;
1da177e4 2901
51219358
MW		 2902 /* Serial number - 9th digit. */
2903 *cp++ = 'A' + (w / 1000);
27c868c2 2904
51219358
MW		 2905 /* 10th, 11th, 12th digits. */
2906 num = w % 1000;
2907 *cp++ = '0' + num / 100;
2908 num %= 100;
2909 *cp++ = '0' + num / 10;
2910 num %= 10;
2911 *cp++ = '0' + num;
2912
2913 *cp = '\0'; /* Null Terminate the string. */
2914 return ASC_TRUE;
2915 }
1da177e4
LT		 2916}
2917
2918/*
51219358 2919 * asc_prt_asc_board_eeprom()
1da177e4 2920 *
51219358 2921 * Print board EEPROM configuration.
1da177e4 2922 */
b59fb6fd 2923static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 2924{
d2411495 2925 struct asc_board *boardp = shost_priv(shost);
51219358 2926 ASC_DVC_VAR *asc_dvc_varp;
51219358
MW		 2927 ASCEEP_CONFIG *ep;
2928 int i;
2929#ifdef CONFIG_ISA
2930 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 };
2931#endif /* CONFIG_ISA */
2932 uchar serialstr[13];
27c868c2 2933
51219358
MW		 2934 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2935 ep = &boardp->eep_config.asc_eep;
27c868c2 2936
b59fb6fd
AV		 2937 seq_printf(m,
2938 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2939 shost->host_no);
1da177e4 2940
51219358 2941 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
b59fb6fd
AV		 2942 == ASC_TRUE)
2943 seq_printf(m, " Serial Number: %s\n", serialstr);
2944 else if (ep->adapter_info[5] == 0xBB)
2f979427
RV		 2945 seq_puts(m,
2946 " Default Settings Used for EEPROM-less Adapter.\n");
b59fb6fd 2947 else
2f979427 2948 seq_puts(m, " Serial Number Signature Not Present.\n");
b59fb6fd
AV		 2949
2950 seq_printf(m,
2951 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2952 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
2953 ep->max_tag_qng);
2954
2955 seq_printf(m,
2956 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
2957
2f979427 2958 seq_puts(m, " Target ID: ");
b59fb6fd
AV		 2959 for (i = 0; i <= ASC_MAX_TID; i++)
2960 seq_printf(m, " %d", i);
b59fb6fd 2961
3d30079c 2962 seq_puts(m, "\n Disconnects: ");
b59fb6fd
AV		 2963 for (i = 0; i <= ASC_MAX_TID; i++)
2964 seq_printf(m, " %c",
2965 (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
b59fb6fd 2966
3d30079c 2967 seq_puts(m, "\n Command Queuing: ");
b59fb6fd
AV		 2968 for (i = 0; i <= ASC_MAX_TID; i++)
2969 seq_printf(m, " %c",
2970 (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
b59fb6fd 2971
3d30079c 2972 seq_puts(m, "\n Start Motor: ");
b59fb6fd
AV		 2973 for (i = 0; i <= ASC_MAX_TID; i++)
2974 seq_printf(m, " %c",
2975 (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
b59fb6fd 2976
3d30079c 2977 seq_puts(m, "\n Synchronous Transfer:");
b59fb6fd
AV		 2978 for (i = 0; i <= ASC_MAX_TID; i++)
2979 seq_printf(m, " %c",
2980 (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 2981 seq_putc(m, '\n');
51219358
MW		 2982
2983#ifdef CONFIG_ISA
2984 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
b59fb6fd
AV		 2985 seq_printf(m,
2986 " Host ISA DMA speed: %d MB/S\n",
2987 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]);
51219358
MW		 2988 }
2989#endif /* CONFIG_ISA */
1da177e4
LT		 2990}
2991
2992/*
51219358 2993 * asc_prt_adv_board_eeprom()
1da177e4 2994 *
51219358 2995 * Print board EEPROM configuration.
1da177e4 2996 */
b59fb6fd 2997static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 2998{
d2411495 2999 struct asc_board *boardp = shost_priv(shost);
51219358 3000 ADV_DVC_VAR *adv_dvc_varp;
27c868c2 3001 int i;
51219358
MW		 3002 char *termstr;
3003 uchar serialstr[13];
3004 ADVEEP_3550_CONFIG *ep_3550 = NULL;
3005 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
3006 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
3007 ushort word;
3008 ushort *wordp;
3009 ushort sdtr_speed = 0;
27c868c2 3010
51219358
MW		 3011 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
3012 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3013 ep_3550 = &boardp->eep_config.adv_3550_eep;
3014 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3015 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
27c868c2 3016 } else {
51219358 3017 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
27c868c2 3018 }
1da177e4 3019
b59fb6fd
AV		 3020 seq_printf(m,
3021 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
3022 shost->host_no);
27c868c2 3023
51219358
MW		 3024 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3025 wordp = &ep_3550->serial_number_word1;
3026 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3027 wordp = &ep_38C0800->serial_number_word1;
3028 } else {
3029 wordp = &ep_38C1600->serial_number_word1;
3030 }
27c868c2 3031
b59fb6fd
AV		 3032 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
3033 seq_printf(m, " Serial Number: %s\n", serialstr);
3034 else
2f979427 3035 seq_puts(m, " Serial Number Signature Not Present.\n");
27c868c2 3036
b59fb6fd
AV		 3037 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3038 seq_printf(m,
3039 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3040 ep_3550->adapter_scsi_id,
3041 ep_3550->max_host_qng, ep_3550->max_dvc_qng);
3042 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3043 seq_printf(m,
3044 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3045 ep_38C0800->adapter_scsi_id,
3046 ep_38C0800->max_host_qng,
3047 ep_38C0800->max_dvc_qng);
3048 else
3049 seq_printf(m,
3050 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
3051 ep_38C1600->adapter_scsi_id,
3052 ep_38C1600->max_host_qng,
3053 ep_38C1600->max_dvc_qng);
51219358
MW		 3054 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3055 word = ep_3550->termination;
3056 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3057 word = ep_38C0800->termination_lvd;
3058 } else {
3059 word = ep_38C1600->termination_lvd;
3060 }
3061 switch (word) {
3062 case 1:
3063 termstr = "Low Off/High Off";
3064 break;
3065 case 2:
3066 termstr = "Low Off/High On";
3067 break;
3068 case 3:
3069 termstr = "Low On/High On";
3070 break;
3071 default:
3072 case 0:
3073 termstr = "Automatic";
3074 break;
27c868c2 3075 }
1da177e4 3076
b59fb6fd
AV		 3077 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
3078 seq_printf(m,
3079 " termination: %u (%s), bios_ctrl: 0x%x\n",
3080 ep_3550->termination, termstr,
3081 ep_3550->bios_ctrl);
3082 else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
3083 seq_printf(m,
3084 " termination: %u (%s), bios_ctrl: 0x%x\n",
3085 ep_38C0800->termination_lvd, termstr,
3086 ep_38C0800->bios_ctrl);
3087 else
3088 seq_printf(m,
3089 " termination: %u (%s), bios_ctrl: 0x%x\n",
3090 ep_38C1600->termination_lvd, termstr,
3091 ep_38C1600->bios_ctrl);
1da177e4 3092
2f979427 3093 seq_puts(m, " Target ID: ");
b59fb6fd
AV		 3094 for (i = 0; i <= ADV_MAX_TID; i++)
3095 seq_printf(m, " %X", i);
f50332ff 3096 seq_putc(m, '\n');
1da177e4 3097
51219358
MW		 3098 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3099 word = ep_3550->disc_enable;
3100 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3101 word = ep_38C0800->disc_enable;
3102 } else {
3103 word = ep_38C1600->disc_enable;
3104 }
2f979427 3105 seq_puts(m, " Disconnects: ");
b59fb6fd
AV		 3106 for (i = 0; i <= ADV_MAX_TID; i++)
3107 seq_printf(m, " %c",
3108 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3109 seq_putc(m, '\n');
1da177e4 3110
51219358
MW		 3111 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3112 word = ep_3550->tagqng_able;
3113 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3114 word = ep_38C0800->tagqng_able;
3115 } else {
3116 word = ep_38C1600->tagqng_able;
3117 }
2f979427 3118 seq_puts(m, " Command Queuing: ");
b59fb6fd
AV		 3119 for (i = 0; i <= ADV_MAX_TID; i++)
3120 seq_printf(m, " %c",
3121 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3122 seq_putc(m, '\n');
1da177e4 3123
51219358
MW		 3124 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3125 word = ep_3550->start_motor;
3126 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3127 word = ep_38C0800->start_motor;
27c868c2 3128 } else {
51219358
MW		 3129 word = ep_38C1600->start_motor;
3130 }
2f979427 3131 seq_puts(m, " Start Motor: ");
b59fb6fd
AV		 3132 for (i = 0; i <= ADV_MAX_TID; i++)
3133 seq_printf(m, " %c",
3134 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3135 seq_putc(m, '\n');
27c868c2 3136
51219358 3137 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2f979427 3138 seq_puts(m, " Synchronous Transfer:");
b59fb6fd
AV		 3139 for (i = 0; i <= ADV_MAX_TID; i++)
3140 seq_printf(m, " %c",
3141 (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3142 'Y' : 'N');
f50332ff 3143 seq_putc(m, '\n');
51219358 3144 }
27c868c2 3145
51219358 3146 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2f979427 3147 seq_puts(m, " Ultra Transfer: ");
b59fb6fd
AV		 3148 for (i = 0; i <= ADV_MAX_TID; i++)
3149 seq_printf(m, " %c",
3150 (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3151 ? 'Y' : 'N');
f50332ff 3152 seq_putc(m, '\n');
51219358 3153 }
27c868c2 3154
51219358
MW		 3155 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3156 word = ep_3550->wdtr_able;
3157 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3158 word = ep_38C0800->wdtr_able;
3159 } else {
3160 word = ep_38C1600->wdtr_able;
3161 }
2f979427 3162 seq_puts(m, " Wide Transfer: ");
b59fb6fd
AV		 3163 for (i = 0; i <= ADV_MAX_TID; i++)
3164 seq_printf(m, " %c",
3165 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
f50332ff 3166 seq_putc(m, '\n');
1da177e4 3167
51219358
MW		 3168 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3169 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
2f979427 3170 seq_puts(m, " Synchronous Transfer Speed (Mhz):\n ");
51219358
MW		 3171 for (i = 0; i <= ADV_MAX_TID; i++) {
3172 char *speed_str;
1da177e4 3173
51219358
MW		 3174 if (i == 0) {
3175 sdtr_speed = adv_dvc_varp->sdtr_speed1;
3176 } else if (i == 4) {
3177 sdtr_speed = adv_dvc_varp->sdtr_speed2;
3178 } else if (i == 8) {
3179 sdtr_speed = adv_dvc_varp->sdtr_speed3;
3180 } else if (i == 12) {
3181 sdtr_speed = adv_dvc_varp->sdtr_speed4;
3182 }
3183 switch (sdtr_speed & ADV_MAX_TID) {
3184 case 0:
3185 speed_str = "Off";
3186 break;
3187 case 1:
3188 speed_str = " 5";
3189 break;
3190 case 2:
3191 speed_str = " 10";
3192 break;
3193 case 3:
3194 speed_str = " 20";
3195 break;
3196 case 4:
3197 speed_str = " 40";
3198 break;
3199 case 5:
3200 speed_str = " 80";
3201 break;
3202 default:
3203 speed_str = "Unk";
3204 break;
3205 }
b59fb6fd
AV		 3206 seq_printf(m, "%X:%s ", i, speed_str);
3207 if (i == 7)
2f979427 3208 seq_puts(m, "\n ");
51219358
MW		 3209 sdtr_speed >>= 4;
3210 }
f50332ff 3211 seq_putc(m, '\n');
51219358 3212 }
1da177e4
LT		 3213}
3214
3215/*
51219358 3216 * asc_prt_driver_conf()
1da177e4 3217 */
b59fb6fd 3218static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3219{
d2411495 3220 struct asc_board *boardp = shost_priv(shost);
51219358 3221 int chip_scsi_id;
27c868c2 3222
b59fb6fd
AV		 3223 seq_printf(m,
3224 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3225 shost->host_no);
27c868c2 3226
b59fb6fd 3227 seq_printf(m,
1abf635d 3228 " host_busy %u, max_id %u, max_lun %llu, max_channel %u\n",
74665016 3229 atomic_read(&shost->host_busy), shost->max_id,
b59fb6fd 3230 shost->max_lun, shost->max_channel);
95c9f162 3231
b59fb6fd
AV		 3232 seq_printf(m,
3233 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3234 shost->unique_id, shost->can_queue, shost->this_id,
3235 shost->sg_tablesize, shost->cmd_per_lun);
95c9f162 3236
b59fb6fd
AV		 3237 seq_printf(m,
3238 " unchecked_isa_dma %d, use_clustering %d\n",
3239 shost->unchecked_isa_dma, shost->use_clustering);
95c9f162 3240
b59fb6fd 3241 seq_printf(m,
31491e1a 3242 " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
eac0b0c7 3243 boardp->flags, shost->last_reset, jiffies,
b59fb6fd 3244 boardp->asc_n_io_port);
27c868c2 3245
31491e1a 3246 seq_printf(m, " io_port 0x%lx\n", shost->io_port);
27c868c2 3247
51219358
MW		 3248 if (ASC_NARROW_BOARD(boardp)) {
3249 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
3250 } else {
3251 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
27c868c2 3252 }
1da177e4
LT		 3253}
3254
3255/*
51219358 3256 * asc_prt_asc_board_info()
1da177e4 3257 *
51219358 3258 * Print dynamic board configuration information.
1da177e4 3259 */
b59fb6fd 3260static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3261{
d2411495 3262 struct asc_board *boardp = shost_priv(shost);
51219358 3263 int chip_scsi_id;
51219358
MW		 3264 ASC_DVC_VAR *v;
3265 ASC_DVC_CFG *c;
3266 int i;
3267 int renegotiate = 0;
27c868c2 3268
51219358
MW		 3269 v = &boardp->dvc_var.asc_dvc_var;
3270 c = &boardp->dvc_cfg.asc_dvc_cfg;
3271 chip_scsi_id = c->chip_scsi_id;
27c868c2 3272
b59fb6fd
AV		 3273 seq_printf(m,
3274 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3275 shost->host_no);
27c868c2 3276
b59fb6fd
AV		 3277 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3278 "mcode_version 0x%x, err_code %u\n",
3279 c->chip_version, c->mcode_date, c->mcode_version,
3280 v->err_code);
1da177e4 3281
51219358 3282 /* Current number of commands waiting for the host. */
b59fb6fd
AV		 3283 seq_printf(m,
3284 " Total Command Pending: %d\n", v->cur_total_qng);
1da177e4 3285
2f979427 3286 seq_puts(m, " Command Queuing:");
51219358
MW		 3287 for (i = 0; i <= ASC_MAX_TID; i++) {
3288 if ((chip_scsi_id == i) ||
3289 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3290 continue;
27c868c2 3291 }
b59fb6fd
AV		 3292 seq_printf(m, " %X:%c",
3293 i,
3294 (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
51219358 3295 }
27c868c2 3296
51219358 3297 /* Current number of commands waiting for a device. */
3d30079c 3298 seq_puts(m, "\n Command Queue Pending:");
51219358
MW		 3299 for (i = 0; i <= ASC_MAX_TID; i++) {
3300 if ((chip_scsi_id == i) ||
3301 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3302 continue;
27c868c2 3303 }
b59fb6fd 3304 seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
27c868c2 3305 }
1da177e4 3306
51219358 3307 /* Current limit on number of commands that can be sent to a device. */
3d30079c 3308 seq_puts(m, "\n Command Queue Limit:");
51219358
MW		 3309 for (i = 0; i <= ASC_MAX_TID; i++) {
3310 if ((chip_scsi_id == i) ||
3311 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3312 continue;
3313 }
b59fb6fd 3314 seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
27c868c2 3315 }
1da177e4 3316
51219358 3317 /* Indicate whether the device has returned queue full status. */
3d30079c 3318 seq_puts(m, "\n Command Queue Full:");
51219358
MW		 3319 for (i = 0; i <= ASC_MAX_TID; i++) {
3320 if ((chip_scsi_id == i) ||
3321 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3322 continue;
3323 }
b59fb6fd
AV		 3324 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3325 seq_printf(m, " %X:Y-%d",
3326 i, boardp->queue_full_cnt[i]);
3327 else
3328 seq_printf(m, " %X:N", i);
51219358 3329 }
1da177e4 3330
3d30079c 3331 seq_puts(m, "\n Synchronous Transfer:");
51219358
MW		 3332 for (i = 0; i <= ASC_MAX_TID; i++) {
3333 if ((chip_scsi_id == i) ||
3334 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3335 continue;
3336 }
b59fb6fd
AV		 3337 seq_printf(m, " %X:%c",
3338 i,
3339 (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3340 }
f50332ff 3341 seq_putc(m, '\n');
1da177e4 3342
51219358
MW		 3343 for (i = 0; i <= ASC_MAX_TID; i++) {
3344 uchar syn_period_ix;
1da177e4 3345
51219358
MW		 3346 if ((chip_scsi_id == i) ||
3347 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3348 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3349 continue;
27c868c2 3350 }
27c868c2 3351
b59fb6fd 3352 seq_printf(m, " %X:", i);
27c868c2 3353
51219358 3354 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
2f979427 3355 seq_puts(m, " Asynchronous");
51219358
MW		 3356 } else {
3357 syn_period_ix =
3358 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3359 1);
27c868c2 3360
b59fb6fd
AV		 3361 seq_printf(m,
3362 " Transfer Period Factor: %d (%d.%d Mhz),",
3363 v->sdtr_period_tbl[syn_period_ix],
3364 250 / v->sdtr_period_tbl[syn_period_ix],
3365 ASC_TENTHS(250,
3366 v->sdtr_period_tbl[syn_period_ix]));
27c868c2 3367
b59fb6fd
AV		 3368 seq_printf(m, " REQ/ACK Offset: %d",
3369 boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
51219358 3370 }
1da177e4 3371
51219358 3372 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
2f979427 3373 seq_puts(m, "*\n");
51219358
MW		 3374 renegotiate = 1;
3375 } else {
f50332ff 3376 seq_putc(m, '\n');
51219358 3377 }
27c868c2 3378 }
1da177e4 3379
51219358 3380 if (renegotiate) {
2f979427 3381 seq_puts(m, " * = Re-negotiation pending before next command.\n");
27c868c2 3382 }
1da177e4
LT		 3383}
3384
1da177e4 3385/*
51219358 3386 * asc_prt_adv_board_info()
1da177e4 3387 *
51219358 3388 * Print dynamic board configuration information.
1da177e4 3389 */
b59fb6fd 3390static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3391{
d2411495 3392 struct asc_board *boardp = shost_priv(shost);
27c868c2 3393 int i;
51219358
MW		 3394 ADV_DVC_VAR *v;
3395 ADV_DVC_CFG *c;
3396 AdvPortAddr iop_base;
3397 ushort chip_scsi_id;
3398 ushort lramword;
3399 uchar lrambyte;
3400 ushort tagqng_able;
3401 ushort sdtr_able, wdtr_able;
3402 ushort wdtr_done, sdtr_done;
3403 ushort period = 0;
3404 int renegotiate = 0;
27c868c2 3405
51219358
MW		 3406 v = &boardp->dvc_var.adv_dvc_var;
3407 c = &boardp->dvc_cfg.adv_dvc_cfg;
3408 iop_base = v->iop_base;
3409 chip_scsi_id = v->chip_scsi_id;
3410
b59fb6fd
AV		 3411 seq_printf(m,
3412 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3413 shost->host_no);
27c868c2 3414
b59fb6fd
AV		 3415 seq_printf(m,
3416 " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
31491e1a 3417 (unsigned long)v->iop_base,
b59fb6fd
AV		 3418 AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3419 v->err_code);
1da177e4 3420
b59fb6fd
AV		 3421 seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3422 "mcode_version 0x%x\n", c->chip_version,
3423 c->mcode_date, c->mcode_version);
51219358
MW		 3424
3425 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
2f979427 3426 seq_puts(m, " Queuing Enabled:");
27c868c2 3427 for (i = 0; i <= ADV_MAX_TID; i++) {
51219358
MW		 3428 if ((chip_scsi_id == i) ||
3429 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3430 continue;
27c868c2 3431 }
51219358 3432
b59fb6fd
AV		 3433 seq_printf(m, " %X:%c",
3434 i,
3435 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3436 }
1da177e4 3437
3d30079c 3438 seq_puts(m, "\n Queue Limit:");
51219358
MW		 3439 for (i = 0; i <= ADV_MAX_TID; i++) {
3440 if ((chip_scsi_id == i) ||
3441 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3442 continue;
3443 }
1da177e4 3444
51219358
MW		 3445 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3446 lrambyte);
27c868c2 3447
b59fb6fd 3448 seq_printf(m, " %X:%d", i, lrambyte);
51219358 3449 }
27c868c2 3450
3d30079c 3451 seq_puts(m, "\n Command Pending:");
51219358
MW		 3452 for (i = 0; i <= ADV_MAX_TID; i++) {
3453 if ((chip_scsi_id == i) ||
3454 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3455 continue;
3456 }
27c868c2 3457
51219358
MW		 3458 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3459 lrambyte);
1da177e4 3460
b59fb6fd 3461 seq_printf(m, " %X:%d", i, lrambyte);
51219358 3462 }
f50332ff 3463 seq_putc(m, '\n');
1da177e4 3464
51219358 3465 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
2f979427 3466 seq_puts(m, " Wide Enabled:");
51219358
MW		 3467 for (i = 0; i <= ADV_MAX_TID; i++) {
3468 if ((chip_scsi_id == i) ||
3469 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3470 continue;
27c868c2 3471 }
51219358 3472
b59fb6fd
AV		 3473 seq_printf(m, " %X:%c",
3474 i,
3475 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
27c868c2 3476 }
f50332ff 3477 seq_putc(m, '\n');
1da177e4 3478
51219358 3479 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
2f979427 3480 seq_puts(m, " Transfer Bit Width:");
51219358
MW		 3481 for (i = 0; i <= ADV_MAX_TID; i++) {
3482 if ((chip_scsi_id == i) ||
3483 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3484 continue;
3485 }
1da177e4 3486
51219358
MW		 3487 AdvReadWordLram(iop_base,
3488 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3489 lramword);
27c868c2 3490
b59fb6fd
AV		 3491 seq_printf(m, " %X:%d",
3492 i, (lramword & 0x8000) ? 16 : 8);
27c868c2 3493
51219358
MW		 3494 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3495 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
f50332ff 3496 seq_putc(m, '*');
51219358 3497 renegotiate = 1;
27c868c2 3498 }
51219358 3499 }
f50332ff 3500 seq_putc(m, '\n');
27c868c2 3501
51219358 3502 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
2f979427 3503 seq_puts(m, " Synchronous Enabled:");
51219358
MW		 3504 for (i = 0; i <= ADV_MAX_TID; i++) {
3505 if ((chip_scsi_id == i) ||
3506 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3507 continue;
3508 }
27c868c2 3509
b59fb6fd
AV		 3510 seq_printf(m, " %X:%c",
3511 i,
3512 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
51219358 3513 }
f50332ff 3514 seq_putc(m, '\n');
27c868c2 3515
51219358
MW		 3516 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3517 for (i = 0; i <= ADV_MAX_TID; i++) {
27c868c2 3518
51219358
MW		 3519 AdvReadWordLram(iop_base,
3520 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3521 lramword);
3522 lramword &= ~0x8000;
27c868c2 3523
51219358
MW		 3524 if ((chip_scsi_id == i) ||
3525 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3526 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3527 continue;
27c868c2
MW		 3528 }
3529
b59fb6fd 3530 seq_printf(m, " %X:", i);
27c868c2 3531
51219358 3532 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */
2f979427 3533 seq_puts(m, " Asynchronous");
51219358 3534 } else {
2f979427 3535 seq_puts(m, " Transfer Period Factor: ");
27c868c2 3536
51219358 3537 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */
2f979427 3538 seq_puts(m, "9 (80.0 Mhz),");
51219358 3539 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */
2f979427 3540 seq_puts(m, "10 (40.0 Mhz),");
51219358 3541 } else { /* 20 Mhz or below. */
27c868c2 3542
51219358
MW		 3543 period = (((lramword >> 8) * 25) + 50) / 4;
3544
3545 if (period == 0) { /* Should never happen. */
31491e1a 3546 seq_printf(m, "%d (? Mhz), ", period);
51219358 3547 } else {
b59fb6fd
AV		 3548 seq_printf(m,
3549 "%d (%d.%d Mhz),",
3550 period, 250 / period,
3551 ASC_TENTHS(250, period));
51219358
MW		 3552 }
3553 }
3554
b59fb6fd
AV		 3555 seq_printf(m, " REQ/ACK Offset: %d",
3556 lramword & 0x1F);
51219358
MW		 3557 }
3558
3559 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
2f979427 3560 seq_puts(m, "*\n");
51219358
MW		 3561 renegotiate = 1;
3562 } else {
f50332ff 3563 seq_putc(m, '\n');
51219358 3564 }
27c868c2 3565 }
51219358
MW		 3566
3567 if (renegotiate) {
2f979427 3568 seq_puts(m, " * = Re-negotiation pending before next command.\n");
51219358 3569 }
51219358
MW		 3570}
3571
3572#ifdef ADVANSYS_STATS
3573/*
3574 * asc_prt_board_stats()
1da177e4 3575 */
b59fb6fd 3576static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3577{
d2411495
MW		 3578 struct asc_board *boardp = shost_priv(shost);
3579 struct asc_stats *s = &boardp->asc_stats;
27c868c2 3580
b59fb6fd
AV		 3581 seq_printf(m,
3582 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3583 shost->host_no);
51219358 3584
b59fb6fd 3585 seq_printf(m,
31491e1a 3586 " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
b59fb6fd
AV		 3587 s->queuecommand, s->reset, s->biosparam,
3588 s->interrupt);
27c868c2 3589
b59fb6fd 3590 seq_printf(m,
31491e1a 3591 " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
b59fb6fd
AV		 3592 s->callback, s->done, s->build_error,
3593 s->adv_build_noreq, s->adv_build_nosg);
27c868c2 3594
b59fb6fd 3595 seq_printf(m,
31491e1a 3596 " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
b59fb6fd
AV		 3597 s->exe_noerror, s->exe_busy, s->exe_error,
3598 s->exe_unknown);
51219358
MW		 3599
3600 /*
3601 * Display data transfer statistics.
3602 */
52c334e9 3603 if (s->xfer_cnt > 0) {
31491e1a 3604 seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
b59fb6fd 3605 s->xfer_cnt, s->xfer_elem);
27c868c2 3606
31491e1a 3607 seq_printf(m, "xfer_bytes %u.%01u kb\n",
b59fb6fd 3608 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
1da177e4 3609
51219358 3610 /* Scatter gather transfer statistics */
31491e1a 3611 seq_printf(m, " avg_num_elem %u.%01u, ",
b59fb6fd
AV		 3612 s->xfer_elem / s->xfer_cnt,
3613 ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
51219358 3614
31491e1a 3615 seq_printf(m, "avg_elem_size %u.%01u kb, ",
b59fb6fd
AV		 3616 (s->xfer_sect / 2) / s->xfer_elem,
3617 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
51219358 3618
31491e1a 3619 seq_printf(m, "avg_xfer_size %u.%01u kb\n",
b59fb6fd
AV		 3620 (s->xfer_sect / 2) / s->xfer_cnt,
3621 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
27c868c2 3622 }
1da177e4 3623}
51219358 3624#endif /* ADVANSYS_STATS */
1da177e4
LT		 3625
3626/*
b59fb6fd 3627 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
1da177e4 3628 *
b59fb6fd
AV		 3629 * m: seq_file to print into
3630 * shost: Scsi_Host
1da177e4 3631 *
51219358
MW		 3632 * Return the number of bytes read from or written to a
3633 * /proc/scsi/advansys/[0...] file.
1da177e4 3634 */
51219358 3635static int
b59fb6fd 3636advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
1da177e4 3637{
d2411495 3638 struct asc_board *boardp = shost_priv(shost);
27c868c2 3639
b352f923 3640 ASC_DBG(1, "begin\n");
51219358 3641
51219358
MW		 3642 /*
3643 * User read of /proc/scsi/advansys/[0...] file.
3644 */
1da177e4 3645
51219358
MW		 3646 /*
3647 * Get board configuration information.
3648 *
3649 * advansys_info() returns the board string from its own static buffer.
3650 */
51219358 3651 /* Copy board information. */
b59fb6fd 3652 seq_printf(m, "%s\n", (char *)advansys_info(shost));
51219358
MW		 3653 /*
3654 * Display Wide Board BIOS Information.
3655 */
b59fb6fd
AV		 3656 if (!ASC_NARROW_BOARD(boardp))
3657 asc_prt_adv_bios(m, shost);
1da177e4 3658
51219358
MW		 3659 /*
3660 * Display driver information for each device attached to the board.
3661 */
b59fb6fd 3662 asc_prt_board_devices(m, shost);
51219358
MW		 3663
3664 /*
3665 * Display EEPROM configuration for the board.
3666 */
b59fb6fd
AV		 3667 if (ASC_NARROW_BOARD(boardp))
3668 asc_prt_asc_board_eeprom(m, shost);
3669 else
3670 asc_prt_adv_board_eeprom(m, shost);
1da177e4 3671
51219358
MW		 3672 /*
3673 * Display driver configuration and information for the board.
3674 */
b59fb6fd 3675 asc_prt_driver_conf(m, shost);
1da177e4 3676
51219358
MW		 3677#ifdef ADVANSYS_STATS
3678 /*
3679 * Display driver statistics for the board.
3680 */
b59fb6fd 3681 asc_prt_board_stats(m, shost);
51219358 3682#endif /* ADVANSYS_STATS */
1da177e4 3683
51219358
MW		 3684 /*
3685 * Display Asc Library dynamic configuration information
3686 * for the board.
3687 */
b59fb6fd
AV		 3688 if (ASC_NARROW_BOARD(boardp))
3689 asc_prt_asc_board_info(m, shost);
3690 else
3691 asc_prt_adv_board_info(m, shost);
3692 return 0;
51219358
MW		 3693}
3694#endif /* CONFIG_PROC_FS */
3695
3696static void asc_scsi_done(struct scsi_cmnd *scp)
3697{
52c334e9 3698 scsi_dma_unmap(scp);
51219358 3699 ASC_STATS(scp->device->host, done);
51219358
MW		 3700 scp->scsi_done(scp);
3701}
3702
3703static void AscSetBank(PortAddr iop_base, uchar bank)
3704{
3705 uchar val;
3706
3707 val = AscGetChipControl(iop_base) &
3708 (~
3709 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3710 CC_CHIP_RESET));
3711 if (bank == 1) {
3712 val |= CC_BANK_ONE;
3713 } else if (bank == 2) {
3714 val |= CC_DIAG | CC_BANK_ONE;
27c868c2 3715 } else {
51219358 3716 val &= ~CC_BANK_ONE;
27c868c2 3717 }
51219358 3718 AscSetChipControl(iop_base, val);
51219358
MW		 3719}
3720
3721static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3722{
3723 AscSetBank(iop_base, 1);
3724 AscWriteChipIH(iop_base, ins_code);
3725 AscSetBank(iop_base, 0);
51219358
MW		 3726}
3727
3728static int AscStartChip(PortAddr iop_base)
3729{
3730 AscSetChipControl(iop_base, 0);
3731 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3732 return (0);
27c868c2 3733 }
51219358
MW		 3734 return (1);
3735}
27c868c2 3736
ae26759e 3737static bool AscStopChip(PortAddr iop_base)
51219358
MW		 3738{
3739 uchar cc_val;
3740
3741 cc_val =
3742 AscGetChipControl(iop_base) &
3743 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3744 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3745 AscSetChipIH(iop_base, INS_HALT);
3746 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3747 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
ae26759e 3748 return false;
27c868c2 3749 }
ae26759e 3750 return true;
51219358 3751}
27c868c2 3752
d647c783 3753static bool AscIsChipHalted(PortAddr iop_base)
51219358
MW		 3754{
3755 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3756 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
d647c783 3757 return true;
27c868c2 3758 }
27c868c2 3759 }
d647c783 3760 return false;
51219358 3761}
27c868c2 3762
d647c783 3763static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
51219358
MW		 3764{
3765 PortAddr iop_base;
3766 int i = 10;
3767
3768 iop_base = asc_dvc->iop_base;
3769 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3770 && (i-- > 0)) {
3771 mdelay(100);
27c868c2 3772 }
51219358
MW		 3773 AscStopChip(iop_base);
3774 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3775 udelay(60);
3776 AscSetChipIH(iop_base, INS_RFLAG_WTM);
3777 AscSetChipIH(iop_base, INS_HALT);
3778 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3779 AscSetChipControl(iop_base, CC_HALT);
3780 mdelay(200);
3781 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3782 AscSetChipStatus(iop_base, 0);
3783 return (AscIsChipHalted(iop_base));
3784}
27c868c2 3785
51219358
MW		 3786static int AscFindSignature(PortAddr iop_base)
3787{
3788 ushort sig_word;
27c868c2 3789
b352f923 3790 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
51219358
MW		 3791 iop_base, AscGetChipSignatureByte(iop_base));
3792 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
b352f923 3793 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
51219358
MW		 3794 iop_base, AscGetChipSignatureWord(iop_base));
3795 sig_word = AscGetChipSignatureWord(iop_base);
3796 if ((sig_word == (ushort)ASC_1000_ID0W) ||
3797 (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3798 return (1);
27c868c2 3799 }
27c868c2 3800 }
51219358 3801 return (0);
27c868c2
MW		 3802}
3803
51219358 3804static void AscEnableInterrupt(PortAddr iop_base)
1da177e4 3805{
51219358 3806 ushort cfg;
27c868c2 3807
51219358
MW		 3808 cfg = AscGetChipCfgLsw(iop_base);
3809 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
51219358 3810}
27c868c2 3811
51219358
MW		 3812static void AscDisableInterrupt(PortAddr iop_base)
3813{
3814 ushort cfg;
27c868c2 3815
51219358
MW		 3816 cfg = AscGetChipCfgLsw(iop_base);
3817 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
51219358 3818}
27c868c2 3819
51219358
MW		 3820static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3821{
3822 unsigned char byte_data;
3823 unsigned short word_data;
27c868c2 3824
51219358
MW		 3825 if (isodd_word(addr)) {
3826 AscSetChipLramAddr(iop_base, addr - 1);
3827 word_data = AscGetChipLramData(iop_base);
3828 byte_data = (word_data >> 8) & 0xFF;
3829 } else {
3830 AscSetChipLramAddr(iop_base, addr);
3831 word_data = AscGetChipLramData(iop_base);
3832 byte_data = word_data & 0xFF;
3833 }
3834 return byte_data;
3835}
27c868c2 3836
51219358
MW		 3837static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3838{
3839 ushort word_data;
27c868c2 3840
51219358
MW		 3841 AscSetChipLramAddr(iop_base, addr);
3842 word_data = AscGetChipLramData(iop_base);
3843 return (word_data);
3844}
27c868c2 3845
51219358 3846#if CC_VERY_LONG_SG_LIST
95cfab6c 3847static u32 AscReadLramDWord(PortAddr iop_base, ushort addr)
51219358
MW		 3848{
3849 ushort val_low, val_high;
95cfab6c 3850 u32 dword_data;
27c868c2 3851
51219358
MW		 3852 AscSetChipLramAddr(iop_base, addr);
3853 val_low = AscGetChipLramData(iop_base);
3854 val_high = AscGetChipLramData(iop_base);
95cfab6c 3855 dword_data = ((u32) val_high << 16) | (u32) val_low;
51219358
MW		 3856 return (dword_data);
3857}
3858#endif /* CC_VERY_LONG_SG_LIST */
3859
3860static void
3861AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3862{
3863 int i;
3864
3865 AscSetChipLramAddr(iop_base, s_addr);
3866 for (i = 0; i < words; i++) {
3867 AscSetChipLramData(iop_base, set_wval);
27c868c2 3868 }
51219358 3869}
1da177e4 3870
51219358
MW		 3871static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3872{
3873 AscSetChipLramAddr(iop_base, addr);
3874 AscSetChipLramData(iop_base, word_val);
51219358
MW		 3875}
3876
3877static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3878{
3879 ushort word_data;
3880
3881 if (isodd_word(addr)) {
3882 addr--;
3883 word_data = AscReadLramWord(iop_base, addr);
3884 word_data &= 0x00FF;
3885 word_data |= (((ushort)byte_val << 8) & 0xFF00);
3886 } else {
3887 word_data = AscReadLramWord(iop_base, addr);
3888 word_data &= 0xFF00;
3889 word_data |= ((ushort)byte_val & 0x00FF);
3890 }
3891 AscWriteLramWord(iop_base, addr, word_data);
1da177e4
LT		 3892}
3893
3894/*
51219358 3895 * Copy 2 bytes to LRAM.
1da177e4 3896 *
51219358
MW		 3897 * The source data is assumed to be in little-endian order in memory
3898 * and is maintained in little-endian order when written to LRAM.
1da177e4 3899 */
51219358 3900static void
989bb5f5
JSR		 3901AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
3902 const uchar *s_buffer, int words)
1da177e4 3903{
27c868c2 3904 int i;
27c868c2 3905
51219358
MW		 3906 AscSetChipLramAddr(iop_base, s_addr);
3907 for (i = 0; i < 2 * words; i += 2) {
3908 /*
3909 * On a little-endian system the second argument below
3910 * produces a little-endian ushort which is written to
3911 * LRAM in little-endian order. On a big-endian system
3912 * the second argument produces a big-endian ushort which
3913 * is "transparently" byte-swapped by outpw() and written
3914 * in little-endian order to LRAM.
3915 */
3916 outpw(iop_base + IOP_RAM_DATA,
3917 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
3918 }
51219358 3919}
27c868c2 3920
51219358
MW		 3921/*
3922 * Copy 4 bytes to LRAM.
3923 *
3924 * The source data is assumed to be in little-endian order in memory
25985edc 3925 * and is maintained in little-endian order when written to LRAM.
51219358
MW		 3926 */
3927static void
3928AscMemDWordCopyPtrToLram(PortAddr iop_base,
3929 ushort s_addr, uchar *s_buffer, int dwords)
3930{
3931 int i;
27c868c2 3932
51219358
MW		 3933 AscSetChipLramAddr(iop_base, s_addr);
3934 for (i = 0; i < 4 * dwords; i += 4) {
3935 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */
3936 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */
3937 }
51219358 3938}
27c868c2 3939
51219358
MW		 3940/*
3941 * Copy 2 bytes from LRAM.
3942 *
3943 * The source data is assumed to be in little-endian order in LRAM
3944 * and is maintained in little-endian order when written to memory.
3945 */
3946static void
3947AscMemWordCopyPtrFromLram(PortAddr iop_base,
3948 ushort s_addr, uchar *d_buffer, int words)
3949{
3950 int i;
3951 ushort word;
27c868c2 3952
51219358
MW		 3953 AscSetChipLramAddr(iop_base, s_addr);
3954 for (i = 0; i < 2 * words; i += 2) {
3955 word = inpw(iop_base + IOP_RAM_DATA);
3956 d_buffer[i] = word & 0xff;
3957 d_buffer[i + 1] = (word >> 8) & 0xff;
27c868c2 3958 }
51219358 3959}
27c868c2 3960
95cfab6c 3961static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
51219358 3962{
95cfab6c 3963 u32 sum = 0;
51219358 3964 int i;
27c868c2 3965
51219358
MW		 3966 for (i = 0; i < words; i++, s_addr += 2) {
3967 sum += AscReadLramWord(iop_base, s_addr);
27c868c2 3968 }
51219358
MW		 3969 return (sum);
3970}
27c868c2 3971
f33134e5 3972static void AscInitLram(ASC_DVC_VAR *asc_dvc)
51219358
MW		 3973{
3974 uchar i;
3975 ushort s_addr;
3976 PortAddr iop_base;
27c868c2 3977
51219358 3978 iop_base = asc_dvc->iop_base;
51219358
MW		 3979 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
3980 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
3981 64) >> 1));
3982 i = ASC_MIN_ACTIVE_QNO;
3983 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
3984 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3985 (uchar)(i + 1));
3986 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3987 (uchar)(asc_dvc->max_total_qng));
3988 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3989 (uchar)i);
3990 i++;
3991 s_addr += ASC_QBLK_SIZE;
3992 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
3993 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3994 (uchar)(i + 1));
3995 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3996 (uchar)(i - 1));
3997 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3998 (uchar)i);
27c868c2 3999 }
51219358
MW		 4000 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
4001 (uchar)ASC_QLINK_END);
4002 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
4003 (uchar)(asc_dvc->max_total_qng - 1));
4004 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
4005 (uchar)asc_dvc->max_total_qng);
4006 i++;
4007 s_addr += ASC_QBLK_SIZE;
4008 for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
4009 i++, s_addr += ASC_QBLK_SIZE) {
4010 AscWriteLramByte(iop_base,
4011 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
4012 AscWriteLramByte(iop_base,
4013 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
4014 AscWriteLramByte(iop_base,
4015 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
27c868c2 4016 }
1da177e4
LT		 4017}
4018
95cfab6c 4019static u32
989bb5f5
JSR		 4020AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
4021 const uchar *mcode_buf, ushort mcode_size)
1da177e4 4022{
95cfab6c 4023 u32 chksum;
51219358
MW		 4024 ushort mcode_word_size;
4025 ushort mcode_chksum;
27c868c2 4026
51219358
MW		 4027 /* Write the microcode buffer starting at LRAM address 0. */
4028 mcode_word_size = (ushort)(mcode_size >> 1);
4029 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
4030 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
27c868c2 4031
51219358 4032 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
b352f923 4033 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
51219358
MW		 4034 mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
4035 (ushort)ASC_CODE_SEC_BEG,
4036 (ushort)((mcode_size -
4037 s_addr - (ushort)
4038 ASC_CODE_SEC_BEG) /
4039 2));
b352f923 4040 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
51219358
MW		 4041 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
4042 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
b352f923 4043 return chksum;
51219358 4044}
27c868c2 4045
51219358
MW		 4046static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
4047{
4048 PortAddr iop_base;
4049 int i;
4050 ushort lram_addr;
4051
4052 iop_base = asc_dvc->iop_base;
4053 AscPutRiscVarFreeQHead(iop_base, 1);
4054 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4055 AscPutVarFreeQHead(iop_base, 1);
4056 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
4057 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
4058 (uchar)((int)asc_dvc->max_total_qng + 1));
4059 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
4060 (uchar)((int)asc_dvc->max_total_qng + 2));
4061 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
4062 asc_dvc->max_total_qng);
4063 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
4064 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
4065 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
4066 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
4067 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
4068 AscPutQDoneInProgress(iop_base, 0);
4069 lram_addr = ASC_QADR_BEG;
4070 for (i = 0; i < 32; i++, lram_addr += 2) {
4071 AscWriteLramWord(iop_base, lram_addr, 0);
4072 }
4073}
4074
f33134e5 4075static int AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
51219358
MW		 4076{
4077 int i;
f33134e5 4078 int warn_code;
51219358 4079 PortAddr iop_base;
95cfab6c
HR		 4080 __le32 phy_addr;
4081 __le32 phy_size;
d10fb2c7 4082 struct asc_board *board = asc_dvc_to_board(asc_dvc);
51219358
MW		 4083
4084 iop_base = asc_dvc->iop_base;
4085 warn_code = 0;
4086 for (i = 0; i <= ASC_MAX_TID; i++) {
4087 AscPutMCodeInitSDTRAtID(iop_base, i,
4088 asc_dvc->cfg->sdtr_period_offset[i]);
4089 }
4090
4091 AscInitQLinkVar(asc_dvc);
4092 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
4093 asc_dvc->cfg->disc_enable);
4094 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
4095 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
4096
d10fb2c7
MW		 4097 /* Ensure overrun buffer is aligned on an 8 byte boundary. */
4098 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
4099 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
4100 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
9a908c1a
HRK		 4101 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
4102 warn_code = -ENOMEM;
4103 goto err_dma_map;
4104 }
d10fb2c7 4105 phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
51219358
MW		 4106 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
4107 (uchar *)&phy_addr, 1);
d10fb2c7 4108 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
51219358
MW		 4109 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
4110 (uchar *)&phy_size, 1);
4111
4112 asc_dvc->cfg->mcode_date =
4113 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
4114 asc_dvc->cfg->mcode_version =
4115 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
4116
4117 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
4118 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4119 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
f33134e5 4120 warn_code = -EINVAL;
9a908c1a 4121 goto err_mcode_start;
51219358
MW		 4122 }
4123 if (AscStartChip(iop_base) != 1) {
4124 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
f33134e5 4125 warn_code = -EIO;
9a908c1a 4126 goto err_mcode_start;
51219358
MW		 4127 }
4128
4129 return warn_code;
9a908c1a
HRK		 4130
4131err_mcode_start:
4132 dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4133 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4134err_dma_map:
4135 asc_dvc->overrun_dma = 0;
4136 return warn_code;
51219358
MW		 4137}
4138
f33134e5 4139static int AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
51219358 4140{
989bb5f5
JSR		 4141 const struct firmware *fw;
4142 const char fwname[] = "advansys/mcode.bin";
4143 int err;
4144 unsigned long chksum;
f33134e5 4145 int warn_code;
51219358
MW		 4146 PortAddr iop_base;
4147
4148 iop_base = asc_dvc->iop_base;
4149 warn_code = 0;
4150 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4151 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4152 AscResetChipAndScsiBus(asc_dvc);
4153 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4154 }
4155 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4156 if (asc_dvc->err_code != 0)
f33134e5 4157 return ASC_ERROR;
51219358
MW		 4158 if (!AscFindSignature(asc_dvc->iop_base)) {
4159 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4160 return warn_code;
4161 }
4162 AscDisableInterrupt(iop_base);
f33134e5 4163 AscInitLram(asc_dvc);
989bb5f5
JSR		 4164
4165 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4166 if (err) {
4167 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4168 fwname, err);
cf747445 4169 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4170 return err;
4171 }
4172 if (fw->size < 4) {
4173 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4174 fw->size, fwname);
4175 release_firmware(fw);
cf747445 4176 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4177 return -EINVAL;
4178 }
4179 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4180 (fw->data[1] << 8) | fw->data[0];
4181 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4182 if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4183 fw->size - 4) != chksum) {
51219358 4184 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
989bb5f5 4185 release_firmware(fw);
51219358
MW		 4186 return warn_code;
4187 }
989bb5f5 4188 release_firmware(fw);
51219358 4189 warn_code |= AscInitMicroCodeVar(asc_dvc);
9a908c1a
HRK		 4190 if (!asc_dvc->overrun_dma)
4191 return warn_code;
51219358
MW		 4192 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4193 AscEnableInterrupt(iop_base);
4194 return warn_code;
4195}
4196
4197/*
4198 * Load the Microcode
4199 *
4200 * Write the microcode image to RISC memory starting at address 0.
4201 *
4202 * The microcode is stored compressed in the following format:
4203 *
4204 * 254 word (508 byte) table indexed by byte code followed
4205 * by the following byte codes:
4206 *
4207 * 1-Byte Code:
4208 * 00: Emit word 0 in table.
4209 * 01: Emit word 1 in table.
4210 * .
4211 * FD: Emit word 253 in table.
4212 *
4213 * Multi-Byte Code:
4214 * FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4215 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4216 *
4217 * Returns 0 or an error if the checksum doesn't match
4218 */
989bb5f5
JSR		 4219static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4220 int size, int memsize, int chksum)
51219358
MW		 4221{
4222 int i, j, end, len = 0;
95cfab6c 4223 u32 sum;
51219358
MW		 4224
4225 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4226
4227 for (i = 253 * 2; i < size; i++) {
4228 if (buf[i] == 0xff) {
4229 unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4230 for (j = 0; j < buf[i + 1]; j++) {
4231 AdvWriteWordAutoIncLram(iop_base, word);
4232 len += 2;
4233 }
4234 i += 3;
4235 } else if (buf[i] == 0xfe) {
4236 unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4237 AdvWriteWordAutoIncLram(iop_base, word);
4238 i += 2;
4239 len += 2;
4240 } else {
951b62c1 4241 unsigned int off = buf[i] * 2;
51219358
MW		 4242 unsigned short word = (buf[off + 1] << 8) | buf[off];
4243 AdvWriteWordAutoIncLram(iop_base, word);
4244 len += 2;
4245 }
4246 }
4247
4248 end = len;
4249
4250 while (len < memsize) {
4251 AdvWriteWordAutoIncLram(iop_base, 0);
4252 len += 2;
4253 }
4254
4255 /* Verify the microcode checksum. */
4256 sum = 0;
4257 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4258
4259 for (len = 0; len < end; len += 2) {
4260 sum += AdvReadWordAutoIncLram(iop_base);
4261 }
4262
4263 if (sum != chksum)
4264 return ASC_IERR_MCODE_CHKSUM;
4265
4266 return 0;
4267}
4268
98b96a7d 4269static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc)
51219358 4270{
98b96a7d
HR		 4271 off_t carr_offset = 0, next_offset;
4272 dma_addr_t carr_paddr;
4273 int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i;
51219358 4274
98b96a7d
HR		 4275 for (i = 0; i < carr_num; i++) {
4276 carr_offset = i * sizeof(ADV_CARR_T);
4277 /* Get physical address of the carrier 'carrp'. */
4278 carr_paddr = adv_dvc->carrier_addr + carr_offset;
4279
4280 adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr);
4281 adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset);
4282 adv_dvc->carrier[i].areq_vpa = 0;
4283 next_offset = carr_offset + sizeof(ADV_CARR_T);
4284 if (i == carr_num)
4285 next_offset = ~0;
4286 adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset);
51219358 4287 }
98b96a7d
HR		 4288 /*
4289 * We cannot have a carrier with 'carr_va' of '0', as
4290 * a reference to this carrier would be interpreted as
4291 * list termination.
4292 * So start at carrier 1 with the freelist.
4293 */
4294 adv_dvc->carr_freelist = &adv_dvc->carrier[1];
4295}
51219358 4296
98b96a7d
HR		 4297static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset)
4298{
4299 int index;
51219358 4300
98b96a7d 4301 BUG_ON(offset > ADV_CARRIER_BUFSIZE);
51219358 4302
98b96a7d
HR		 4303 index = offset / sizeof(ADV_CARR_T);
4304 return &adv_dvc->carrier[index];
4305}
51219358 4306
98b96a7d
HR		 4307static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc)
4308{
4309 ADV_CARR_T *carrp = adv_dvc->carr_freelist;
4310 u32 next_vpa = le32_to_cpu(carrp->next_vpa);
4311
4312 if (next_vpa == 0 || next_vpa == ~0) {
4313 ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa);
4314 return NULL;
4315 }
51219358 4316
98b96a7d
HR		 4317 adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa);
4318 /*
4319 * insert stopper carrier to terminate list
4320 */
4321 carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER);
4322
4323 return carrp;
51219358
MW		 4324}
4325
4b47e464
HR		 4326/*
4327 * 'offset' is the index in the request pointer array
4328 */
4329static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset)
4330{
4331 struct asc_board *boardp = adv_dvc->drv_ptr;
4332
4333 BUG_ON(offset > adv_dvc->max_host_qng);
4334 return &boardp->adv_reqp[offset];
4335}
4336
51219358
MW		 4337/*
4338 * Send an idle command to the chip and wait for completion.
4339 *
4340 * Command completion is polled for once per microsecond.
4341 *
4342 * The function can be called from anywhere including an interrupt handler.
4343 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4344 * functions to prevent reentrancy.
4345 *
4346 * Return Values:
4347 * ADV_TRUE - command completed successfully
4348 * ADV_FALSE - command failed
4349 * ADV_ERROR - command timed out
4350 */
4351static int
4352AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
95cfab6c 4353 ushort idle_cmd, u32 idle_cmd_parameter)
51219358 4354{
95cfab6c 4355 int result, i, j;
51219358
MW		 4356 AdvPortAddr iop_base;
4357
4358 iop_base = asc_dvc->iop_base;
4359
4360 /*
4361 * Clear the idle command status which is set by the microcode
4362 * to a non-zero value to indicate when the command is completed.
4363 * The non-zero result is one of the IDLE_CMD_STATUS_* values
4364 */
4365 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4366
4367 /*
4368 * Write the idle command value after the idle command parameter
4369 * has been written to avoid a race condition. If the order is not
4370 * followed, the microcode may process the idle command before the
4371 * parameters have been written to LRAM.
4372 */
4373 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4374 cpu_to_le32(idle_cmd_parameter));
4375 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4376
4377 /*
4378 * Tickle the RISC to tell it to process the idle command.
4379 */
4380 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4381 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4382 /*
4383 * Clear the tickle value. In the ASC-3550 the RISC flag
4384 * command 'clr_tickle_b' does not work unless the host
4385 * value is cleared.
4386 */
4387 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4388 }
4389
4390 /* Wait for up to 100 millisecond for the idle command to timeout. */
4391 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4392 /* Poll once each microsecond for command completion. */
4393 for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4394 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4395 result);
4396 if (result != 0)
4397 return result;
4398 udelay(1);
4399 }
4400 }
4401
4402 BUG(); /* The idle command should never timeout. */
4403 return ADV_ERROR;
4404}
4405
4406/*
4407 * Reset SCSI Bus and purge all outstanding requests.
4408 *
4409 * Return Value:
4410 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset.
4411 * ADV_FALSE(0) - Microcode command failed.
4412 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4413 * may be hung which requires driver recovery.
4414 */
4415static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4416{
4417 int status;
4418
4419 /*
4420 * Send the SCSI Bus Reset idle start idle command which asserts
4421 * the SCSI Bus Reset signal.
4422 */
4423 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4424 if (status != ADV_TRUE) {
4425 return status;
4426 }
4427
4428 /*
4429 * Delay for the specified SCSI Bus Reset hold time.
4430 *
4431 * The hold time delay is done on the host because the RISC has no
4432 * microsecond accurate timer.
4433 */
4434 udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4435
4436 /*
4437 * Send the SCSI Bus Reset end idle command which de-asserts
4438 * the SCSI Bus Reset signal and purges any pending requests.
4439 */
4440 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4441 if (status != ADV_TRUE) {
4442 return status;
4443 }
4444
4445 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4446
4447 return status;
4448}
4449
4450/*
4451 * Initialize the ASC-3550.
4452 *
4453 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4454 *
4455 * For a non-fatal error return a warning code. If there are no warnings
4456 * then 0 is returned.
4457 *
4458 * Needed after initialization for error recovery.
4459 */
4460static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4461{
989bb5f5
JSR		 4462 const struct firmware *fw;
4463 const char fwname[] = "advansys/3550.bin";
51219358
MW		 4464 AdvPortAddr iop_base;
4465 ushort warn_code;
4466 int begin_addr;
4467 int end_addr;
4468 ushort code_sum;
4469 int word;
4470 int i;
989bb5f5
JSR		 4471 int err;
4472 unsigned long chksum;
51219358
MW		 4473 ushort scsi_cfg1;
4474 uchar tid;
4475 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4476 ushort wdtr_able = 0, sdtr_able, tagqng_able;
4477 uchar max_cmd[ADV_MAX_TID + 1];
4478
4479 /* If there is already an error, don't continue. */
4480 if (asc_dvc->err_code != 0)
4481 return ADV_ERROR;
4482
4483 /*
4484 * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4485 */
4486 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4487 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4488 return ADV_ERROR;
4489 }
4490
4491 warn_code = 0;
4492 iop_base = asc_dvc->iop_base;
4493
4494 /*
4495 * Save the RISC memory BIOS region before writing the microcode.
4496 * The BIOS may already be loaded and using its RISC LRAM region
4497 * so its region must be saved and restored.
4498 *
4499 * Note: This code makes the assumption, which is currently true,
4500 * that a chip reset does not clear RISC LRAM.
4501 */
4502 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4503 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4504 bios_mem[i]);
4505 }
4506
4507 /*
4508 * Save current per TID negotiated values.
4509 */
4510 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) {
4511 ushort bios_version, major, minor;
4512
4513 bios_version =
4514 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2];
4515 major = (bios_version >> 12) & 0xF;
4516 minor = (bios_version >> 8) & 0xF;
4517 if (major < 3 || (major == 3 && minor == 1)) {
4518 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */
4519 AdvReadWordLram(iop_base, 0x120, wdtr_able);
4520 } else {
4521 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4522 }
4523 }
4524 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4525 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4526 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4527 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4528 max_cmd[tid]);
4529 }
4530
989bb5f5
JSR		 4531 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4532 if (err) {
4533 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4534 fwname, err);
cf747445 4535 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4536 return err;
4537 }
4538 if (fw->size < 4) {
4539 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4540 fw->size, fwname);
4541 release_firmware(fw);
cf747445 4542 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 4543 return -EINVAL;
4544 }
4545 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4546 (fw->data[1] << 8) | fw->data[0];
4547 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
4548 fw->size - 4, ADV_3550_MEMSIZE,
4549 chksum);
4550 release_firmware(fw);
51219358
MW		 4551 if (asc_dvc->err_code)
4552 return ADV_ERROR;
4553
4554 /*
4555 * Restore the RISC memory BIOS region.
4556 */
4557 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4558 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4559 bios_mem[i]);
4560 }
4561
4562 /*
4563 * Calculate and write the microcode code checksum to the microcode
4564 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
4565 */
4566 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
4567 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
4568 code_sum = 0;
4569 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
4570 for (word = begin_addr; word < end_addr; word += 2) {
4571 code_sum += AdvReadWordAutoIncLram(iop_base);
4572 }
4573 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
4574
4575 /*
4576 * Read and save microcode version and date.
4577 */
4578 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
4579 asc_dvc->cfg->mcode_date);
4580 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
4581 asc_dvc->cfg->mcode_version);
4582
4583 /*
4584 * Set the chip type to indicate the ASC3550.
4585 */
4586 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550);
4587
4588 /*
4589 * If the PCI Configuration Command Register "Parity Error Response
4590 * Control" Bit was clear (0), then set the microcode variable
4591 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
4592 * to ignore DMA parity errors.
4593 */
4594 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
4595 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4596 word |= CONTROL_FLAG_IGNORE_PERR;
4597 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
4598 }
4599
4600 /*
4601 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO
4602 * threshold of 128 bytes. This register is only accessible to the host.
4603 */
4604 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
4605 START_CTL_EMFU | READ_CMD_MRM);
4606
4607 /*
4608 * Microcode operating variables for WDTR, SDTR, and command tag
4609 * queuing will be set in slave_configure() based on what a
4610 * device reports it is capable of in Inquiry byte 7.
4611 *
4612 * If SCSI Bus Resets have been disabled, then directly set
4613 * SDTR and WDTR from the EEPROM configuration. This will allow
4614 * the BIOS and warm boot to work without a SCSI bus hang on
4615 * the Inquiry caused by host and target mismatched DTR values.
4616 * Without the SCSI Bus Reset, before an Inquiry a device can't
4617 * be assumed to be in Asynchronous, Narrow mode.
4618 */
4619 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
4620 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
4621 asc_dvc->wdtr_able);
4622 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
4623 asc_dvc->sdtr_able);
4624 }
4625
4626 /*
4627 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2,
4628 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID
4629 * bitmask. These values determine the maximum SDTR speed negotiated
4630 * with a device.
4631 *
4632 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
4633 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
4634 * without determining here whether the device supports SDTR.
4635 *
4636 * 4-bit speed SDTR speed name
4637 * =========== ===============
4638 * 0000b (0x0) SDTR disabled
4639 * 0001b (0x1) 5 Mhz
4640 * 0010b (0x2) 10 Mhz
4641 * 0011b (0x3) 20 Mhz (Ultra)
4642 * 0100b (0x4) 40 Mhz (LVD/Ultra2)
4643 * 0101b (0x5) 80 Mhz (LVD2/Ultra3)
4644 * 0110b (0x6) Undefined
4645 * .
4646 * 1111b (0xF) Undefined
4647 */
4648 word = 0;
4649 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4650 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) {
4651 /* Set Ultra speed for TID 'tid'. */
4652 word |= (0x3 << (4 * (tid % 4)));
4653 } else {
4654 /* Set Fast speed for TID 'tid'. */
4655 word |= (0x2 << (4 * (tid % 4)));
4656 }
4657 if (tid == 3) { /* Check if done with sdtr_speed1. */
4658 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word);
4659 word = 0;
4660 } else if (tid == 7) { /* Check if done with sdtr_speed2. */
4661 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word);
4662 word = 0;
4663 } else if (tid == 11) { /* Check if done with sdtr_speed3. */
4664 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word);
4665 word = 0;
4666 } else if (tid == 15) { /* Check if done with sdtr_speed4. */
4667 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word);
4668 /* End of loop. */
4669 }
4670 }
4671
4672 /*
4673 * Set microcode operating variable for the disconnect per TID bitmask.
4674 */
4675 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
4676 asc_dvc->cfg->disc_enable);
4677
4678 /*
4679 * Set SCSI_CFG0 Microcode Default Value.
4680 *
4681 * The microcode will set the SCSI_CFG0 register using this value
4682 * after it is started below.
4683 */
4684 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
4685 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
4686 asc_dvc->chip_scsi_id);
4687
4688 /*
4689 * Determine SCSI_CFG1 Microcode Default Value.
4690 *
4691 * The microcode will set the SCSI_CFG1 register using this value
4692 * after it is started below.
4693 */
4694
4695 /* Read current SCSI_CFG1 Register value. */
4696 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
4697
4698 /*
4699 * If all three connectors are in use, return an error.
4700 */
4701 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 ||
4702 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) {
4703 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION;
4704 return ADV_ERROR;
4705 }
4706
4707 /*
4708 * If the internal narrow cable is reversed all of the SCSI_CTRL
4709 * register signals will be set. Check for and return an error if
4710 * this condition is found.
4711 */
4712 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
4713 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
4714 return ADV_ERROR;
4715 }
4716
4717 /*
4718 * If this is a differential board and a single-ended device
4719 * is attached to one of the connectors, return an error.
4720 */
4721 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) {
4722 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE;
4723 return ADV_ERROR;
4724 }
4725
4726 /*
4727 * If automatic termination control is enabled, then set the
4728 * termination value based on a table listed in a_condor.h.
4729 *
4730 * If manual termination was specified with an EEPROM setting
4731 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and
4732 * is ready to be 'ored' into SCSI_CFG1.
4733 */
4734 if (asc_dvc->cfg->termination == 0) {
4735 /*
4736 * The software always controls termination by setting TERM_CTL_SEL.
4737 * If TERM_CTL_SEL were set to 0, the hardware would set termination.
4738 */
4739 asc_dvc->cfg->termination |= TERM_CTL_SEL;
4740
4741 switch (scsi_cfg1 & CABLE_DETECT) {
4742 /* TERM_CTL_H: on, TERM_CTL_L: on */
4743 case 0x3:
4744 case 0x7:
4745 case 0xB:
4746 case 0xD:
4747 case 0xE:
4748 case 0xF:
4749 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L);
4750 break;
4751
4752 /* TERM_CTL_H: on, TERM_CTL_L: off */
4753 case 0x1:
4754 case 0x5:
4755 case 0x9:
4756 case 0xA:
4757 case 0xC:
4758 asc_dvc->cfg->termination |= TERM_CTL_H;
4759 break;
4760
4761 /* TERM_CTL_H: off, TERM_CTL_L: off */
4762 case 0x2:
4763 case 0x6:
4764 break;
4765 }
4766 }
4767
4768 /*
4769 * Clear any set TERM_CTL_H and TERM_CTL_L bits.
4770 */
4771 scsi_cfg1 &= ~TERM_CTL;
4772
4773 /*
4774 * Invert the TERM_CTL_H and TERM_CTL_L bits and then
4775 * set 'scsi_cfg1'. The TERM_POL bit does not need to be
4776 * referenced, because the hardware internally inverts
4777 * the Termination High and Low bits if TERM_POL is set.
4778 */
4779 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL));
4780
4781 /*
4782 * Set SCSI_CFG1 Microcode Default Value
4783 *
4784 * Set filter value and possibly modified termination control
4785 * bits in the Microcode SCSI_CFG1 Register Value.
4786 *
4787 * The microcode will set the SCSI_CFG1 register using this value
4788 * after it is started below.
4789 */
4790 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1,
4791 FLTR_DISABLE | scsi_cfg1);
4792
4793 /*
4794 * Set MEM_CFG Microcode Default Value
4795 *
4796 * The microcode will set the MEM_CFG register using this value
4797 * after it is started below.
4798 *
4799 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
4800 * are defined.
4801 *
4802 * ASC-3550 has 8KB internal memory.
4803 */
4804 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
4805 BIOS_EN | RAM_SZ_8KB);
4806
4807 /*
4808 * Set SEL_MASK Microcode Default Value
4809 *
4810 * The microcode will set the SEL_MASK register using this value
4811 * after it is started below.
4812 */
4813 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
4814 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
4815
4816 AdvBuildCarrierFreelist(asc_dvc);
4817
4818 /*
4819 * Set-up the Host->RISC Initiator Command Queue (ICQ).
4820 */
4821
98b96a7d
HR		 4822 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
4823 if (!asc_dvc->icq_sp) {
51219358
MW		 4824 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4825 return ADV_ERROR;
4826 }
51219358
MW		 4827
4828 /*
4829 * Set RISC ICQ physical address start value.
4830 */
4831 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
4832
4833 /*
4834 * Set-up the RISC->Host Initiator Response Queue (IRQ).
4835 */
98b96a7d
HR		 4836 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
4837 if (!asc_dvc->irq_sp) {
51219358
MW		 4838 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
4839 return ADV_ERROR;
4840 }
51219358
MW		 4841
4842 /*
4843 * Set RISC IRQ physical address start value.
4844 */
4845 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
4846 asc_dvc->carr_pending_cnt = 0;
4847
4848 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
4849 (ADV_INTR_ENABLE_HOST_INTR |
4850 ADV_INTR_ENABLE_GLOBAL_INTR));
4851
4852 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
4853 AdvWriteWordRegister(iop_base, IOPW_PC, word);
4854
4855 /* finally, finally, gentlemen, start your engine */
4856 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
4857
4858 /*
4859 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
4860 * Resets should be performed. The RISC has to be running
4861 * to issue a SCSI Bus Reset.
4862 */
4863 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
4864 /*
4865 * If the BIOS Signature is present in memory, restore the
4866 * BIOS Handshake Configuration Table and do not perform
4867 * a SCSI Bus Reset.
4868 */
4869 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
4870 0x55AA) {
4871 /*
4872 * Restore per TID negotiated values.
4873 */
4874 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4875 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4876 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
4877 tagqng_able);
4878 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4879 AdvWriteByteLram(iop_base,
4880 ASC_MC_NUMBER_OF_MAX_CMD + tid,
4881 max_cmd[tid]);
4882 }
4883 } else {
4884 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
4885 warn_code = ASC_WARN_BUSRESET_ERROR;
4886 }
4887 }
4888 }
4889
4890 return warn_code;
4891}
4892
4893/*
4894 * Initialize the ASC-38C0800.
4895 *
4896 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4897 *
4898 * For a non-fatal error return a warning code. If there are no warnings
4899 * then 0 is returned.
4900 *
4901 * Needed after initialization for error recovery.
4902 */
4903static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc)
4904{
989bb5f5
JSR		 4905 const struct firmware *fw;
4906 const char fwname[] = "advansys/38C0800.bin";
51219358
MW		 4907 AdvPortAddr iop_base;
4908 ushort warn_code;
4909 int begin_addr;
4910 int end_addr;
4911 ushort code_sum;
4912 int word;
4913 int i;
989bb5f5
JSR		 4914 int err;
4915 unsigned long chksum;
51219358
MW		 4916 ushort scsi_cfg1;
4917 uchar byte;
4918 uchar tid;
4919 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
4920 ushort wdtr_able, sdtr_able, tagqng_able;
4921 uchar max_cmd[ADV_MAX_TID + 1];
4922
4923 /* If there is already an error, don't continue. */
4924 if (asc_dvc->err_code != 0)
4925 return ADV_ERROR;
4926
4927 /*
4928 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800.
4929 */
4930 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) {
4931 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4932 return ADV_ERROR;
4933 }
4934
4935 warn_code = 0;
4936 iop_base = asc_dvc->iop_base;
4937
4938 /*
4939 * Save the RISC memory BIOS region before writing the microcode.
4940 * The BIOS may already be loaded and using its RISC LRAM region
4941 * so its region must be saved and restored.
4942 *
4943 * Note: This code makes the assumption, which is currently true,
4944 * that a chip reset does not clear RISC LRAM.
4945 */
4946 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4947 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
4948 bios_mem[i]);
4949 }
4950
4951 /*
4952 * Save current per TID negotiated values.
4953 */
4954 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
4955 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
4956 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
4957 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
4958 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
4959 max_cmd[tid]);
4960 }
4961
4962 /*
4963 * RAM BIST (RAM Built-In Self Test)
4964 *
4965 * Address : I/O base + offset 0x38h register (byte).
4966 * Function: Bit 7-6(RW) : RAM mode
4967 * Normal Mode : 0x00
4968 * Pre-test Mode : 0x40
4969 * RAM Test Mode : 0x80
4970 * Bit 5 : unused
4971 * Bit 4(RO) : Done bit
4972 * Bit 3-0(RO) : Status
4973 * Host Error : 0x08
4974 * Int_RAM Error : 0x04
4975 * RISC Error : 0x02
4976 * SCSI Error : 0x01
4977 * No Error : 0x00
4978 *
4979 * Note: RAM BIST code should be put right here, before loading the
4980 * microcode and after saving the RISC memory BIOS region.
4981 */
4982
4983 /*
4984 * LRAM Pre-test
4985 *
4986 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
4987 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
4988 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
4989 * to NORMAL_MODE, return an error too.
4990 */
4991 for (i = 0; i < 2; i++) {
4992 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
4993 mdelay(10); /* Wait for 10ms before reading back. */
4994 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
4995 if ((byte & RAM_TEST_DONE) == 0
4996 || (byte & 0x0F) != PRE_TEST_VALUE) {
4997 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
4998 return ADV_ERROR;
4999 }
5000
5001 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5002 mdelay(10); /* Wait for 10ms before reading back. */
5003 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5004 != NORMAL_VALUE) {
5005 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5006 return ADV_ERROR;
5007 }
5008 }
5009
5010 /*
5011 * LRAM Test - It takes about 1.5 ms to run through the test.
5012 *
5013 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5014 * If Done bit not set or Status not 0, save register byte, set the
5015 * err_code, and return an error.
5016 */
5017 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5018 mdelay(10); /* Wait for 10ms before checking status. */
5019
5020 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5021 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5022 /* Get here if Done bit not set or Status not 0. */
5023 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5024 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5025 return ADV_ERROR;
5026 }
5027
5028 /* We need to reset back to normal mode after LRAM test passes. */
5029 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5030
989bb5f5
JSR		 5031 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5032 if (err) {
5033 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5034 fwname, err);
cf747445 5035 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5036 return err;
5037 }
5038 if (fw->size < 4) {
5039 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5040 fw->size, fwname);
5041 release_firmware(fw);
cf747445 5042 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5043 return -EINVAL;
5044 }
5045 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5046 (fw->data[1] << 8) | fw->data[0];
5047 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5048 fw->size - 4, ADV_38C0800_MEMSIZE,
5049 chksum);
5050 release_firmware(fw);
51219358
MW		 5051 if (asc_dvc->err_code)
5052 return ADV_ERROR;
5053
5054 /*
5055 * Restore the RISC memory BIOS region.
5056 */
5057 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5058 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5059 bios_mem[i]);
5060 }
5061
5062 /*
5063 * Calculate and write the microcode code checksum to the microcode
5064 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5065 */
5066 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5067 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5068 code_sum = 0;
5069 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5070 for (word = begin_addr; word < end_addr; word += 2) {
5071 code_sum += AdvReadWordAutoIncLram(iop_base);
5072 }
5073 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5074
5075 /*
5076 * Read microcode version and date.
5077 */
5078 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5079 asc_dvc->cfg->mcode_date);
5080 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5081 asc_dvc->cfg->mcode_version);
5082
5083 /*
5084 * Set the chip type to indicate the ASC38C0800.
5085 */
5086 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800);
5087
5088 /*
5089 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5090 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5091 * cable detection and then we are able to read C_DET[3:0].
5092 *
5093 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5094 * Microcode Default Value' section below.
5095 */
5096 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5097 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5098 scsi_cfg1 | DIS_TERM_DRV);
5099
5100 /*
5101 * If the PCI Configuration Command Register "Parity Error Response
5102 * Control" Bit was clear (0), then set the microcode variable
5103 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5104 * to ignore DMA parity errors.
5105 */
5106 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5107 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5108 word |= CONTROL_FLAG_IGNORE_PERR;
5109 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5110 }
5111
5112 /*
5113 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2]
5114 * bits for the default FIFO threshold.
5115 *
5116 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes.
5117 *
5118 * For DMA Errata #4 set the BC_THRESH_ENB bit.
5119 */
5120 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5121 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH |
5122 READ_CMD_MRM);
5123
5124 /*
5125 * Microcode operating variables for WDTR, SDTR, and command tag
5126 * queuing will be set in slave_configure() based on what a
5127 * device reports it is capable of in Inquiry byte 7.
5128 *
5129 * If SCSI Bus Resets have been disabled, then directly set
5130 * SDTR and WDTR from the EEPROM configuration. This will allow
5131 * the BIOS and warm boot to work without a SCSI bus hang on
5132 * the Inquiry caused by host and target mismatched DTR values.
5133 * Without the SCSI Bus Reset, before an Inquiry a device can't
5134 * be assumed to be in Asynchronous, Narrow mode.
5135 */
5136 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5137 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5138 asc_dvc->wdtr_able);
5139 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5140 asc_dvc->sdtr_able);
5141 }
5142
5143 /*
5144 * Set microcode operating variables for DISC and SDTR_SPEED1,
5145 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5146 * configuration values.
5147 *
5148 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5149 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5150 * without determining here whether the device supports SDTR.
5151 */
5152 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5153 asc_dvc->cfg->disc_enable);
5154 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5155 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5156 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5157 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5158
5159 /*
5160 * Set SCSI_CFG0 Microcode Default Value.
5161 *
5162 * The microcode will set the SCSI_CFG0 register using this value
5163 * after it is started below.
5164 */
5165 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5166 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5167 asc_dvc->chip_scsi_id);
5168
5169 /*
5170 * Determine SCSI_CFG1 Microcode Default Value.
5171 *
5172 * The microcode will set the SCSI_CFG1 register using this value
5173 * after it is started below.
5174 */
5175
5176 /* Read current SCSI_CFG1 Register value. */
5177 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5178
5179 /*
5180 * If the internal narrow cable is reversed all of the SCSI_CTRL
5181 * register signals will be set. Check for and return an error if
5182 * this condition is found.
5183 */
5184 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5185 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5186 return ADV_ERROR;
5187 }
5188
5189 /*
5190 * All kind of combinations of devices attached to one of four
5191 * connectors are acceptable except HVD device attached. For example,
5192 * LVD device can be attached to SE connector while SE device attached
5193 * to LVD connector. If LVD device attached to SE connector, it only
5194 * runs up to Ultra speed.
5195 *
5196 * If an HVD device is attached to one of LVD connectors, return an
5197 * error. However, there is no way to detect HVD device attached to
5198 * SE connectors.
5199 */
5200 if (scsi_cfg1 & HVD) {
5201 asc_dvc->err_code = ASC_IERR_HVD_DEVICE;
5202 return ADV_ERROR;
5203 }
5204
5205 /*
5206 * If either SE or LVD automatic termination control is enabled, then
5207 * set the termination value based on a table listed in a_condor.h.
5208 *
5209 * If manual termination was specified with an EEPROM setting then
5210 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready
5211 * to be 'ored' into SCSI_CFG1.
5212 */
5213 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5214 /* SE automatic termination control is enabled. */
5215 switch (scsi_cfg1 & C_DET_SE) {
5216 /* TERM_SE_HI: on, TERM_SE_LO: on */
5217 case 0x1:
5218 case 0x2:
5219 case 0x3:
5220 asc_dvc->cfg->termination |= TERM_SE;
5221 break;
5222
5223 /* TERM_SE_HI: on, TERM_SE_LO: off */
5224 case 0x0:
5225 asc_dvc->cfg->termination |= TERM_SE_HI;
5226 break;
5227 }
5228 }
5229
5230 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) {
5231 /* LVD automatic termination control is enabled. */
5232 switch (scsi_cfg1 & C_DET_LVD) {
5233 /* TERM_LVD_HI: on, TERM_LVD_LO: on */
5234 case 0x4:
5235 case 0x8:
5236 case 0xC:
5237 asc_dvc->cfg->termination |= TERM_LVD;
5238 break;
5239
5240 /* TERM_LVD_HI: off, TERM_LVD_LO: off */
5241 case 0x0:
5242 break;
5243 }
5244 }
5245
5246 /*
5247 * Clear any set TERM_SE and TERM_LVD bits.
5248 */
5249 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD);
5250
5251 /*
5252 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'.
5253 */
5254 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0);
5255
5256 /*
5257 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE
5258 * bits and set possibly modified termination control bits in the
5259 * Microcode SCSI_CFG1 Register Value.
5260 */
5261 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE);
5262
5263 /*
5264 * Set SCSI_CFG1 Microcode Default Value
5265 *
5266 * Set possibly modified termination control and reset DIS_TERM_DRV
5267 * bits in the Microcode SCSI_CFG1 Register Value.
5268 *
5269 * The microcode will set the SCSI_CFG1 register using this value
5270 * after it is started below.
5271 */
5272 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5273
5274 /*
5275 * Set MEM_CFG Microcode Default Value
5276 *
5277 * The microcode will set the MEM_CFG register using this value
5278 * after it is started below.
5279 *
5280 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5281 * are defined.
5282 *
5283 * ASC-38C0800 has 16KB internal memory.
5284 */
5285 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5286 BIOS_EN | RAM_SZ_16KB);
5287
5288 /*
5289 * Set SEL_MASK Microcode Default Value
5290 *
5291 * The microcode will set the SEL_MASK register using this value
5292 * after it is started below.
5293 */
5294 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5295 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5296
5297 AdvBuildCarrierFreelist(asc_dvc);
5298
5299 /*
5300 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5301 */
5302
98b96a7d
HR		 5303 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5304 if (!asc_dvc->icq_sp) {
5305 ASC_DBG(0, "Failed to get ICQ carrier\n");
51219358
MW		 5306 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5307 return ADV_ERROR;
5308 }
51219358
MW		 5309
5310 /*
5311 * Set RISC ICQ physical address start value.
5312 * carr_pa is LE, must be native before write
5313 */
5314 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5315
5316 /*
5317 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5318 */
98b96a7d
HR		 5319 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5320 if (!asc_dvc->irq_sp) {
5321 ASC_DBG(0, "Failed to get IRQ carrier\n");
51219358
MW		 5322 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5323 return ADV_ERROR;
5324 }
51219358
MW		 5325
5326 /*
5327 * Set RISC IRQ physical address start value.
5328 *
5329 * carr_pa is LE, must be native before write *
5330 */
5331 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5332 asc_dvc->carr_pending_cnt = 0;
5333
5334 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5335 (ADV_INTR_ENABLE_HOST_INTR |
5336 ADV_INTR_ENABLE_GLOBAL_INTR));
5337
5338 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5339 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5340
5341 /* finally, finally, gentlemen, start your engine */
5342 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5343
5344 /*
5345 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5346 * Resets should be performed. The RISC has to be running
5347 * to issue a SCSI Bus Reset.
5348 */
5349 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5350 /*
5351 * If the BIOS Signature is present in memory, restore the
5352 * BIOS Handshake Configuration Table and do not perform
5353 * a SCSI Bus Reset.
5354 */
5355 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5356 0x55AA) {
5357 /*
5358 * Restore per TID negotiated values.
5359 */
5360 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5361 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5362 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5363 tagqng_able);
5364 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5365 AdvWriteByteLram(iop_base,
5366 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5367 max_cmd[tid]);
5368 }
5369 } else {
5370 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5371 warn_code = ASC_WARN_BUSRESET_ERROR;
5372 }
5373 }
5374 }
5375
5376 return warn_code;
5377}
5378
5379/*
5380 * Initialize the ASC-38C1600.
5381 *
5382 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
5383 *
5384 * For a non-fatal error return a warning code. If there are no warnings
5385 * then 0 is returned.
5386 *
5387 * Needed after initialization for error recovery.
5388 */
5389static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc)
5390{
989bb5f5
JSR		 5391 const struct firmware *fw;
5392 const char fwname[] = "advansys/38C1600.bin";
51219358
MW		 5393 AdvPortAddr iop_base;
5394 ushort warn_code;
5395 int begin_addr;
5396 int end_addr;
5397 ushort code_sum;
5398 long word;
5399 int i;
989bb5f5
JSR		 5400 int err;
5401 unsigned long chksum;
51219358
MW		 5402 ushort scsi_cfg1;
5403 uchar byte;
5404 uchar tid;
5405 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */
5406 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able;
5407 uchar max_cmd[ASC_MAX_TID + 1];
5408
5409 /* If there is already an error, don't continue. */
5410 if (asc_dvc->err_code != 0) {
5411 return ADV_ERROR;
5412 }
5413
5414 /*
5415 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600.
5416 */
5417 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
5418 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
5419 return ADV_ERROR;
5420 }
5421
5422 warn_code = 0;
5423 iop_base = asc_dvc->iop_base;
5424
5425 /*
5426 * Save the RISC memory BIOS region before writing the microcode.
5427 * The BIOS may already be loaded and using its RISC LRAM region
5428 * so its region must be saved and restored.
5429 *
5430 * Note: This code makes the assumption, which is currently true,
5431 * that a chip reset does not clear RISC LRAM.
5432 */
5433 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5434 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5435 bios_mem[i]);
5436 }
5437
5438 /*
5439 * Save current per TID negotiated values.
5440 */
5441 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5442 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5443 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5444 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5445 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5446 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5447 max_cmd[tid]);
5448 }
5449
5450 /*
5451 * RAM BIST (Built-In Self Test)
5452 *
5453 * Address : I/O base + offset 0x38h register (byte).
5454 * Function: Bit 7-6(RW) : RAM mode
5455 * Normal Mode : 0x00
5456 * Pre-test Mode : 0x40
5457 * RAM Test Mode : 0x80
5458 * Bit 5 : unused
5459 * Bit 4(RO) : Done bit
5460 * Bit 3-0(RO) : Status
5461 * Host Error : 0x08
5462 * Int_RAM Error : 0x04
5463 * RISC Error : 0x02
5464 * SCSI Error : 0x01
5465 * No Error : 0x00
5466 *
5467 * Note: RAM BIST code should be put right here, before loading the
5468 * microcode and after saving the RISC memory BIOS region.
5469 */
5470
5471 /*
5472 * LRAM Pre-test
5473 *
5474 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds.
5475 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return
5476 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset
5477 * to NORMAL_MODE, return an error too.
5478 */
5479 for (i = 0; i < 2; i++) {
5480 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE);
5481 mdelay(10); /* Wait for 10ms before reading back. */
5482 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5483 if ((byte & RAM_TEST_DONE) == 0
5484 || (byte & 0x0F) != PRE_TEST_VALUE) {
5485 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5486 return ADV_ERROR;
5487 }
5488
5489 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5490 mdelay(10); /* Wait for 10ms before reading back. */
5491 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST)
5492 != NORMAL_VALUE) {
5493 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST;
5494 return ADV_ERROR;
5495 }
5496 }
5497
5498 /*
5499 * LRAM Test - It takes about 1.5 ms to run through the test.
5500 *
5501 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds.
5502 * If Done bit not set or Status not 0, save register byte, set the
5503 * err_code, and return an error.
5504 */
5505 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE);
5506 mdelay(10); /* Wait for 10ms before checking status. */
5507
5508 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST);
5509 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) {
5510 /* Get here if Done bit not set or Status not 0. */
5511 asc_dvc->bist_err_code = byte; /* for BIOS display message */
5512 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST;
5513 return ADV_ERROR;
5514 }
5515
5516 /* We need to reset back to normal mode after LRAM test passes. */
5517 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE);
5518
989bb5f5
JSR		 5519 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
5520 if (err) {
5521 printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
5522 fwname, err);
cf747445 5523 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5524 return err;
5525 }
5526 if (fw->size < 4) {
5527 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
5528 fw->size, fwname);
5529 release_firmware(fw);
cf747445 5530 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM;
989bb5f5
JSR		 5531 return -EINVAL;
5532 }
5533 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
5534 (fw->data[1] << 8) | fw->data[0];
5535 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4],
5536 fw->size - 4, ADV_38C1600_MEMSIZE,
5537 chksum);
5538 release_firmware(fw);
51219358
MW		 5539 if (asc_dvc->err_code)
5540 return ADV_ERROR;
5541
5542 /*
5543 * Restore the RISC memory BIOS region.
5544 */
5545 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
5546 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),
5547 bios_mem[i]);
5548 }
5549
5550 /*
5551 * Calculate and write the microcode code checksum to the microcode
5552 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C).
5553 */
5554 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr);
5555 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr);
5556 code_sum = 0;
5557 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr);
5558 for (word = begin_addr; word < end_addr; word += 2) {
5559 code_sum += AdvReadWordAutoIncLram(iop_base);
5560 }
5561 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum);
5562
5563 /*
5564 * Read microcode version and date.
5565 */
5566 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE,
5567 asc_dvc->cfg->mcode_date);
5568 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM,
5569 asc_dvc->cfg->mcode_version);
5570
5571 /*
5572 * Set the chip type to indicate the ASC38C1600.
5573 */
5574 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600);
5575
5576 /*
5577 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register.
5578 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current
5579 * cable detection and then we are able to read C_DET[3:0].
5580 *
5581 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1
5582 * Microcode Default Value' section below.
5583 */
5584 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5585 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1,
5586 scsi_cfg1 | DIS_TERM_DRV);
5587
5588 /*
5589 * If the PCI Configuration Command Register "Parity Error Response
5590 * Control" Bit was clear (0), then set the microcode variable
5591 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode
5592 * to ignore DMA parity errors.
5593 */
5594 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) {
5595 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5596 word |= CONTROL_FLAG_IGNORE_PERR;
5597 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5598 }
5599
5600 /*
5601 * If the BIOS control flag AIPP (Asynchronous Information
5602 * Phase Protection) disable bit is not set, then set the firmware
5603 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable
5604 * AIPP checking and encoding.
5605 */
5606 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) {
5607 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5608 word |= CONTROL_FLAG_ENABLE_AIPP;
5609 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word);
5610 }
5611
5612 /*
5613 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4],
5614 * and START_CTL_TH [3:2].
5615 */
5616 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0,
5617 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM);
5618
5619 /*
5620 * Microcode operating variables for WDTR, SDTR, and command tag
5621 * queuing will be set in slave_configure() based on what a
5622 * device reports it is capable of in Inquiry byte 7.
5623 *
5624 * If SCSI Bus Resets have been disabled, then directly set
5625 * SDTR and WDTR from the EEPROM configuration. This will allow
5626 * the BIOS and warm boot to work without a SCSI bus hang on
5627 * the Inquiry caused by host and target mismatched DTR values.
5628 * Without the SCSI Bus Reset, before an Inquiry a device can't
5629 * be assumed to be in Asynchronous, Narrow mode.
5630 */
5631 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) {
5632 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE,
5633 asc_dvc->wdtr_able);
5634 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE,
5635 asc_dvc->sdtr_able);
5636 }
5637
5638 /*
5639 * Set microcode operating variables for DISC and SDTR_SPEED1,
5640 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM
5641 * configuration values.
5642 *
5643 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2,
5644 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them
5645 * without determining here whether the device supports SDTR.
5646 */
5647 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE,
5648 asc_dvc->cfg->disc_enable);
5649 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1);
5650 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2);
5651 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3);
5652 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4);
5653
5654 /*
5655 * Set SCSI_CFG0 Microcode Default Value.
5656 *
5657 * The microcode will set the SCSI_CFG0 register using this value
5658 * after it is started below.
5659 */
5660 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0,
5661 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN |
5662 asc_dvc->chip_scsi_id);
5663
5664 /*
5665 * Calculate SCSI_CFG1 Microcode Default Value.
5666 *
5667 * The microcode will set the SCSI_CFG1 register using this value
5668 * after it is started below.
5669 *
5670 * Each ASC-38C1600 function has only two cable detect bits.
5671 * The bus mode override bits are in IOPB_SOFT_OVER_WR.
5672 */
5673 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1);
5674
5675 /*
5676 * If the cable is reversed all of the SCSI_CTRL register signals
5677 * will be set. Check for and return an error if this condition is
5678 * found.
5679 */
5680 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) {
5681 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE;
5682 return ADV_ERROR;
5683 }
5684
5685 /*
5686 * Each ASC-38C1600 function has two connectors. Only an HVD device
5687 * can not be connected to either connector. An LVD device or SE device
5688 * may be connected to either connecor. If an SE device is connected,
5689 * then at most Ultra speed (20 Mhz) can be used on both connectors.
5690 *
5691 * If an HVD device is attached, return an error.
5692 */
5693 if (scsi_cfg1 & HVD) {
5694 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE;
5695 return ADV_ERROR;
5696 }
5697
5698 /*
5699 * Each function in the ASC-38C1600 uses only the SE cable detect and
5700 * termination because there are two connectors for each function. Each
5701 * function may use either LVD or SE mode. Corresponding the SE automatic
5702 * termination control EEPROM bits are used for each function. Each
5703 * function has its own EEPROM. If SE automatic control is enabled for
5704 * the function, then set the termination value based on a table listed
5705 * in a_condor.h.
5706 *
5707 * If manual termination is specified in the EEPROM for the function,
5708 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is
5709 * ready to be 'ored' into SCSI_CFG1.
5710 */
5711 if ((asc_dvc->cfg->termination & TERM_SE) == 0) {
5712 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
5713 /* SE automatic termination control is enabled. */
5714 switch (scsi_cfg1 & C_DET_SE) {
5715 /* TERM_SE_HI: on, TERM_SE_LO: on */
5716 case 0x1:
5717 case 0x2:
5718 case 0x3:
5719 asc_dvc->cfg->termination |= TERM_SE;
5720 break;
5721
5722 case 0x0:
5723 if (PCI_FUNC(pdev->devfn) == 0) {
5724 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */
5725 } else {
5726 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */
5727 asc_dvc->cfg->termination |= TERM_SE_HI;
5728 }
5729 break;
5730 }
5731 }
5732
5733 /*
5734 * Clear any set TERM_SE bits.
5735 */
5736 scsi_cfg1 &= ~TERM_SE;
5737
5738 /*
5739 * Invert the TERM_SE bits and then set 'scsi_cfg1'.
5740 */
5741 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE);
5742
5743 /*
5744 * Clear Big Endian and Terminator Polarity bits and set possibly
5745 * modified termination control bits in the Microcode SCSI_CFG1
5746 * Register Value.
5747 *
5748 * Big Endian bit is not used even on big endian machines.
5749 */
5750 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL);
5751
5752 /*
5753 * Set SCSI_CFG1 Microcode Default Value
5754 *
5755 * Set possibly modified termination control bits in the Microcode
5756 * SCSI_CFG1 Register Value.
5757 *
5758 * The microcode will set the SCSI_CFG1 register using this value
5759 * after it is started below.
5760 */
5761 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1);
5762
5763 /*
5764 * Set MEM_CFG Microcode Default Value
5765 *
5766 * The microcode will set the MEM_CFG register using this value
5767 * after it is started below.
5768 *
5769 * MEM_CFG may be accessed as a word or byte, but only bits 0-7
5770 * are defined.
5771 *
5772 * ASC-38C1600 has 32KB internal memory.
5773 *
5774 * XXX - Since ASC38C1600 Rev.3 has a Local RAM failure issue, we come
5775 * out a special 16K Adv Library and Microcode version. After the issue
5776 * resolved, we should turn back to the 32K support. Both a_condor.h and
5777 * mcode.sas files also need to be updated.
5778 *
5779 * AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5780 * BIOS_EN | RAM_SZ_32KB);
5781 */
5782 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG,
5783 BIOS_EN | RAM_SZ_16KB);
5784
5785 /*
5786 * Set SEL_MASK Microcode Default Value
5787 *
5788 * The microcode will set the SEL_MASK register using this value
5789 * after it is started below.
5790 */
5791 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK,
5792 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id));
5793
5794 AdvBuildCarrierFreelist(asc_dvc);
5795
5796 /*
5797 * Set-up the Host->RISC Initiator Command Queue (ICQ).
5798 */
98b96a7d
HR		 5799 asc_dvc->icq_sp = adv_get_next_carrier(asc_dvc);
5800 if (!asc_dvc->icq_sp) {
51219358
MW		 5801 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5802 return ADV_ERROR;
5803 }
51219358
MW		 5804
5805 /*
5806 * Set RISC ICQ physical address start value. Initialize the
5807 * COMMA register to the same value otherwise the RISC will
5808 * prematurely detect a command is available.
5809 */
5810 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa);
5811 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
5812 le32_to_cpu(asc_dvc->icq_sp->carr_pa));
5813
5814 /*
5815 * Set-up the RISC->Host Initiator Response Queue (IRQ).
5816 */
98b96a7d
HR		 5817 asc_dvc->irq_sp = adv_get_next_carrier(asc_dvc);
5818 if (!asc_dvc->irq_sp) {
51219358
MW		 5819 asc_dvc->err_code |= ASC_IERR_NO_CARRIER;
5820 return ADV_ERROR;
5821 }
51219358
MW		 5822
5823 /*
5824 * Set RISC IRQ physical address start value.
5825 */
5826 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa);
5827 asc_dvc->carr_pending_cnt = 0;
5828
5829 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES,
5830 (ADV_INTR_ENABLE_HOST_INTR |
5831 ADV_INTR_ENABLE_GLOBAL_INTR));
5832 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word);
5833 AdvWriteWordRegister(iop_base, IOPW_PC, word);
5834
5835 /* finally, finally, gentlemen, start your engine */
5836 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN);
5837
5838 /*
5839 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus
5840 * Resets should be performed. The RISC has to be running
5841 * to issue a SCSI Bus Reset.
5842 */
5843 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) {
5844 /*
5845 * If the BIOS Signature is present in memory, restore the
5846 * per TID microcode operating variables.
5847 */
5848 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] ==
5849 0x55AA) {
5850 /*
5851 * Restore per TID negotiated values.
5852 */
5853 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5854 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5855 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5856 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
5857 tagqng_able);
5858 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
5859 AdvWriteByteLram(iop_base,
5860 ASC_MC_NUMBER_OF_MAX_CMD + tid,
5861 max_cmd[tid]);
5862 }
5863 } else {
5864 if (AdvResetSB(asc_dvc) != ADV_TRUE) {
5865 warn_code = ASC_WARN_BUSRESET_ERROR;
5866 }
5867 }
5868 }
5869
5870 return warn_code;
5871}
5872
5873/*
5874 * Reset chip and SCSI Bus.
5875 *
5876 * Return Value:
5877 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful.
5878 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure.
5879 */
5880static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc)
5881{
5882 int status;
5883 ushort wdtr_able, sdtr_able, tagqng_able;
5884 ushort ppr_able = 0;
5885 uchar tid, max_cmd[ADV_MAX_TID + 1];
5886 AdvPortAddr iop_base;
5887 ushort bios_sig;
5888
5889 iop_base = asc_dvc->iop_base;
5890
5891 /*
5892 * Save current per TID negotiated values.
5893 */
5894 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5895 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5896 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5897 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5898 }
5899 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5900 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5901 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5902 max_cmd[tid]);
5903 }
5904
5905 /*
5906 * Force the AdvInitAsc3550/38C0800Driver() function to
5907 * perform a SCSI Bus Reset by clearing the BIOS signature word.
5908 * The initialization functions assumes a SCSI Bus Reset is not
5909 * needed if the BIOS signature word is present.
5910 */
5911 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5912 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0);
5913
5914 /*
5915 * Stop chip and reset it.
5916 */
5917 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP);
5918 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET);
5919 mdelay(100);
5920 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
5921 ADV_CTRL_REG_CMD_WR_IO_REG);
5922
5923 /*
5924 * Reset Adv Library error code, if any, and try
5925 * re-initializing the chip.
5926 */
5927 asc_dvc->err_code = 0;
5928 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5929 status = AdvInitAsc38C1600Driver(asc_dvc);
5930 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
5931 status = AdvInitAsc38C0800Driver(asc_dvc);
5932 } else {
5933 status = AdvInitAsc3550Driver(asc_dvc);
5934 }
5935
5936 /* Translate initialization return value to status value. */
5937 if (status == 0) {
5938 status = ADV_TRUE;
5939 } else {
5940 status = ADV_FALSE;
5941 }
5942
5943 /*
5944 * Restore the BIOS signature word.
5945 */
5946 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig);
5947
5948 /*
5949 * Restore per TID negotiated values.
5950 */
5951 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
5952 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
5953 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
5954 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able);
5955 }
5956 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
5957 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
5958 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid,
5959 max_cmd[tid]);
5960 }
5961
5962 return status;
5963}
5964
5965/*
5966 * adv_async_callback() - Adv Library asynchronous event callback function.
5967 */
5968static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code)
5969{
5970 switch (code) {
5971 case ADV_ASYNC_SCSI_BUS_RESET_DET:
5972 /*
5973 * The firmware detected a SCSI Bus reset.
5974 */
b352f923 5975 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n");
51219358
MW		 5976 break;
5977
5978 case ADV_ASYNC_RDMA_FAILURE:
5979 /*
5980 * Handle RDMA failure by resetting the SCSI Bus and
5981 * possibly the chip if it is unresponsive. Log the error
5982 * with a unique code.
5983 */
b352f923 5984 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n");
51219358
MW		 5985 AdvResetChipAndSB(adv_dvc_varp);
5986 break;
5987
5988 case ADV_HOST_SCSI_BUS_RESET:
5989 /*
5990 * Host generated SCSI bus reset occurred.
5991 */
b352f923 5992 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n");
51219358
MW		 5993 break;
5994
5995 default:
b352f923 5996 ASC_DBG(0, "unknown code 0x%x\n", code);
51219358
MW		 5997 break;
5998 }
5999}
6000
6001/*
6002 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR().
6003 *
6004 * Callback function for the Wide SCSI Adv Library.
6005 */
6006static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp)
6007{
9c17c62a
HR		 6008 struct asc_board *boardp = adv_dvc_varp->drv_ptr;
6009 u32 srb_tag;
51219358
MW		 6010 adv_req_t *reqp;
6011 adv_sgblk_t *sgblkp;
6012 struct scsi_cmnd *scp;
95cfab6c 6013 u32 resid_cnt;
811ddc05 6014 dma_addr_t sense_addr;
51219358 6015
9c17c62a
HR		 6016 ASC_DBG(1, "adv_dvc_varp 0x%p, scsiqp 0x%p\n",
6017 adv_dvc_varp, scsiqp);
51219358
MW		 6018 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
6019
6020 /*
6021 * Get the adv_req_t structure for the command that has been
6022 * completed. The adv_req_t structure actually contains the
6023 * completed ADV_SCSI_REQ_Q structure.
6024 */
9c17c62a
HR		 6025 srb_tag = le32_to_cpu(scsiqp->srb_tag);
6026 scp = scsi_host_find_tag(boardp->shost, scsiqp->srb_tag);
51219358 6027
b352f923 6028 ASC_DBG(1, "scp 0x%p\n", scp);
51219358
MW		 6029 if (scp == NULL) {
6030 ASC_PRINT
6031 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n");
6032 return;
6033 }
6034 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6035
9c17c62a
HR		 6036 reqp = (adv_req_t *)scp->host_scribble;
6037 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp);
6038 if (reqp == NULL) {
6039 ASC_PRINT("adv_isr_callback: reqp is NULL\n");
6040 return;
6041 }
6042 /*
6043 * Remove backreferences to avoid duplicate
6044 * command completions.
6045 */
6046 scp->host_scribble = NULL;
6047 reqp->cmndp = NULL;
51219358 6048
9c17c62a
HR		 6049 ASC_STATS(boardp->shost, callback);
6050 ASC_DBG(1, "shost 0x%p\n", boardp->shost);
51219358 6051
811ddc05
HR		 6052 sense_addr = le32_to_cpu(scsiqp->sense_addr);
6053 dma_unmap_single(boardp->dev, sense_addr,
6054 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
6055
51219358
MW		 6056 /*
6057 * 'done_status' contains the command's ending status.
6058 */
6059 switch (scsiqp->done_status) {
6060 case QD_NO_ERROR:
b352f923 6061 ASC_DBG(2, "QD_NO_ERROR\n");
51219358
MW		 6062 scp->result = 0;
6063
6064 /*
6065 * Check for an underrun condition.
6066 *
6067 * If there was no error and an underrun condition, then
6068 * then return the number of underrun bytes.
6069 */
6070 resid_cnt = le32_to_cpu(scsiqp->data_cnt);
52c334e9
MW		 6071 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 &&
6072 resid_cnt <= scsi_bufflen(scp)) {
b352f923 6073 ASC_DBG(1, "underrun condition %lu bytes\n",
51219358 6074 (ulong)resid_cnt);
52c334e9 6075 scsi_set_resid(scp, resid_cnt);
51219358
MW		 6076 }
6077 break;
6078
6079 case QD_WITH_ERROR:
b352f923 6080 ASC_DBG(2, "QD_WITH_ERROR\n");
51219358
MW		 6081 switch (scsiqp->host_status) {
6082 case QHSTA_NO_ERROR:
6083 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) {
b352f923 6084 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
51219358 6085 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
b80ca4f7 6086 SCSI_SENSE_BUFFERSIZE);
51219358
MW		 6087 /*
6088 * Note: The 'status_byte()' macro used by
6089 * target drivers defined in scsi.h shifts the
6090 * status byte returned by host drivers right
6091 * by 1 bit. This is why target drivers also
6092 * use right shifted status byte definitions.
6093 * For instance target drivers use
6094 * CHECK_CONDITION, defined to 0x1, instead of
6095 * the SCSI defined check condition value of
6096 * 0x2. Host drivers are supposed to return
6097 * the status byte as it is defined by SCSI.
6098 */
6099 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
6100 STATUS_BYTE(scsiqp->scsi_status);
6101 } else {
6102 scp->result = STATUS_BYTE(scsiqp->scsi_status);
6103 }
6104 break;
6105
6106 default:
6107 /* Some other QHSTA error occurred. */
b352f923 6108 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status);
51219358
MW		 6109 scp->result = HOST_BYTE(DID_BAD_TARGET);
6110 break;
6111 }
6112 break;
6113
6114 case QD_ABORTED_BY_HOST:
b352f923 6115 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
51219358
MW		 6116 scp->result =
6117 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status);
6118 break;
6119
6120 default:
b352f923 6121 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status);
51219358
MW		 6122 scp->result =
6123 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status);
6124 break;
6125 }
6126
6127 /*
6128 * If the 'init_tidmask' bit isn't already set for the target and the
6129 * current request finished normally, then set the bit for the target
6130 * to indicate that a device is present.
6131 */
6132 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
6133 scsiqp->done_status == QD_NO_ERROR &&
6134 scsiqp->host_status == QHSTA_NO_ERROR) {
6135 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
6136 }
6137
6138 asc_scsi_done(scp);
6139
6140 /*
6141 * Free all 'adv_sgblk_t' structures allocated for the request.
6142 */
6143 while ((sgblkp = reqp->sgblkp) != NULL) {
6144 /* Remove 'sgblkp' from the request list. */
6145 reqp->sgblkp = sgblkp->next_sgblkp;
6146
0ce53822
HR		 6147 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
6148 sgblkp->sg_addr);
51219358
MW		 6149 }
6150
b352f923 6151 ASC_DBG(1, "done\n");
51219358
MW		 6152}
6153
6154/*
6155 * Adv Library Interrupt Service Routine
6156 *
6157 * This function is called by a driver's interrupt service routine.
6158 * The function disables and re-enables interrupts.
6159 *
6160 * When a microcode idle command is completed, the ADV_DVC_VAR
6161 * 'idle_cmd_done' field is set to ADV_TRUE.
6162 *
6163 * Note: AdvISR() can be called when interrupts are disabled or even
6164 * when there is no hardware interrupt condition present. It will
6165 * always check for completed idle commands and microcode requests.
6166 * This is an important feature that shouldn't be changed because it
6167 * allows commands to be completed from polling mode loops.
6168 *
6169 * Return:
6170 * ADV_TRUE(1) - interrupt was pending
6171 * ADV_FALSE(0) - no interrupt was pending
6172 */
6173static int AdvISR(ADV_DVC_VAR *asc_dvc)
6174{
6175 AdvPortAddr iop_base;
6176 uchar int_stat;
6177 ushort target_bit;
6178 ADV_CARR_T *free_carrp;
95cfab6c 6179 __le32 irq_next_vpa;
51219358 6180 ADV_SCSI_REQ_Q *scsiq;
4b47e464 6181 adv_req_t *reqp;
51219358
MW		 6182
6183 iop_base = asc_dvc->iop_base;
6184
6185 /* Reading the register clears the interrupt. */
6186 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG);
6187
6188 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB |
6189 ADV_INTR_STATUS_INTRC)) == 0) {
6190 return ADV_FALSE;
6191 }
6192
6193 /*
6194 * Notify the driver of an asynchronous microcode condition by
6195 * calling the adv_async_callback function. The function
6196 * is passed the microcode ASC_MC_INTRB_CODE byte value.
6197 */
6198 if (int_stat & ADV_INTR_STATUS_INTRB) {
6199 uchar intrb_code;
6200
6201 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code);
6202
6203 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
6204 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
6205 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE &&
6206 asc_dvc->carr_pending_cnt != 0) {
6207 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
6208 ADV_TICKLE_A);
6209 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
6210 AdvWriteByteRegister(iop_base,
6211 IOPB_TICKLE,
6212 ADV_TICKLE_NOP);
6213 }
6214 }
6215 }
6216
6217 adv_async_callback(asc_dvc, intrb_code);
6218 }
6219
6220 /*
6221 * Check if the IRQ stopper carrier contains a completed request.
6222 */
6223 while (((irq_next_vpa =
6224 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) {
6225 /*
6226 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure.
6227 * The RISC will have set 'areq_vpa' to a virtual address.
6228 *
9fef6ba4 6229 * The firmware will have copied the ADV_SCSI_REQ_Q.scsiq_ptr
51219358 6230 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion
9fef6ba4 6231 * below complements the conversion of ADV_SCSI_REQ_Q.scsiq_ptr'
51219358
MW		 6232 * in AdvExeScsiQueue().
6233 */
4b47e464
HR		 6234 u32 pa_offset = le32_to_cpu(asc_dvc->irq_sp->areq_vpa);
6235 ASC_DBG(1, "irq_sp %p areq_vpa %u\n",
6236 asc_dvc->irq_sp, pa_offset);
6237 reqp = adv_get_reqp(asc_dvc, pa_offset);
6238 scsiq = &reqp->scsi_req_q;
51219358
MW		 6239
6240 /*
6241 * Request finished with good status and the queue was not
6242 * DMAed to host memory by the firmware. Set all status fields
6243 * to indicate good status.
6244 */
6245 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) {
6246 scsiq->done_status = QD_NO_ERROR;
6247 scsiq->host_status = scsiq->scsi_status = 0;
6248 scsiq->data_cnt = 0L;
6249 }
6250
6251 /*
6252 * Advance the stopper pointer to the next carrier
6253 * ignoring the lower four bits. Free the previous
6254 * stopper carrier.
6255 */
6256 free_carrp = asc_dvc->irq_sp;
98b96a7d
HR		 6257 asc_dvc->irq_sp = adv_get_carrier(asc_dvc,
6258 ASC_GET_CARRP(irq_next_vpa));
51219358 6259
98b96a7d 6260 free_carrp->next_vpa = asc_dvc->carr_freelist->carr_va;
51219358
MW		 6261 asc_dvc->carr_freelist = free_carrp;
6262 asc_dvc->carr_pending_cnt--;
6263
6264 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id);
6265
6266 /*
6267 * Clear request microcode control flag.
6268 */
6269 scsiq->cntl = 0;
6270
6271 /*
6272 * Notify the driver of the completed request by passing
6273 * the ADV_SCSI_REQ_Q pointer to its callback function.
6274 */
6275 scsiq->a_flag |= ADV_SCSIQ_DONE;
6276 adv_isr_callback(asc_dvc, scsiq);
6277 /*
6278 * Note: After the driver callback function is called, 'scsiq'
6279 * can no longer be referenced.
6280 *
6281 * Fall through and continue processing other completed
6282 * requests...
6283 */
6284 }
6285 return ADV_TRUE;
6286}
6287
6288static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code)
6289{
6290 if (asc_dvc->err_code == 0) {
6291 asc_dvc->err_code = err_code;
6292 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W,
6293 err_code);
6294 }
6295 return err_code;
6296}
6297
6298static void AscAckInterrupt(PortAddr iop_base)
6299{
6300 uchar host_flag;
6301 uchar risc_flag;
6302 ushort loop;
6303
6304 loop = 0;
6305 do {
6306 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B);
6307 if (loop++ > 0x7FFF) {
6308 break;
6309 }
6310 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0);
6311 host_flag =
6312 AscReadLramByte(iop_base,
6313 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT);
6314 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
6315 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT));
6316 AscSetChipStatus(iop_base, CIW_INT_ACK);
6317 loop = 0;
6318 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) {
6319 AscSetChipStatus(iop_base, CIW_INT_ACK);
6320 if (loop++ > 3) {
6321 break;
6322 }
6323 }
6324 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
51219358
MW		 6325}
6326
6327static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time)
6328{
afbb68c3 6329 const uchar *period_table;
51219358
MW		 6330 int max_index;
6331 int min_index;
6332 int i;
6333
6334 period_table = asc_dvc->sdtr_period_tbl;
6335 max_index = (int)asc_dvc->max_sdtr_index;
afbb68c3 6336 min_index = (int)asc_dvc->min_sdtr_index;
51219358
MW		 6337 if ((syn_time <= period_table[max_index])) {
6338 for (i = min_index; i < (max_index - 1); i++) {
6339 if (syn_time <= period_table[i]) {
6340 return (uchar)i;
6341 }
6342 }
6343 return (uchar)max_index;
6344 } else {
6345 return (uchar)(max_index + 1);
6346 }
6347}
6348
6349static uchar
6350AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset)
6351{
6352 EXT_MSG sdtr_buf;
6353 uchar sdtr_period_index;
6354 PortAddr iop_base;
6355
6356 iop_base = asc_dvc->iop_base;
6357 sdtr_buf.msg_type = EXTENDED_MESSAGE;
6358 sdtr_buf.msg_len = MS_SDTR_LEN;
6359 sdtr_buf.msg_req = EXTENDED_SDTR;
6360 sdtr_buf.xfer_period = sdtr_period;
6361 sdtr_offset &= ASC_SYN_MAX_OFFSET;
6362 sdtr_buf.req_ack_offset = sdtr_offset;
6363 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
6364 if (sdtr_period_index <= asc_dvc->max_sdtr_index) {
6365 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6366 (uchar *)&sdtr_buf,
6367 sizeof(EXT_MSG) >> 1);
6368 return ((sdtr_period_index << 4) | sdtr_offset);
6369 } else {
6370 sdtr_buf.req_ack_offset = 0;
6371 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG,
6372 (uchar *)&sdtr_buf,
6373 sizeof(EXT_MSG) >> 1);
6374 return 0;
6375 }
6376}
6377
6378static uchar
6379AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset)
6380{
6381 uchar byte;
6382 uchar sdtr_period_ix;
6383
6384 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period);
afbb68c3 6385 if (sdtr_period_ix > asc_dvc->max_sdtr_index)
51219358 6386 return 0xFF;
51219358
MW		 6387 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET);
6388 return byte;
6389}
6390
d647c783 6391static bool AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data)
51219358
MW		 6392{
6393 ASC_SCSI_BIT_ID_TYPE org_id;
6394 int i;
d647c783 6395 bool sta = true;
51219358
MW		 6396
6397 AscSetBank(iop_base, 1);
6398 org_id = AscReadChipDvcID(iop_base);
6399 for (i = 0; i <= ASC_MAX_TID; i++) {
6400 if (org_id == (0x01 << i))
6401 break;
6402 }
6403 org_id = (ASC_SCSI_BIT_ID_TYPE) i;
6404 AscWriteChipDvcID(iop_base, id);
6405 if (AscReadChipDvcID(iop_base) == (0x01 << id)) {
6406 AscSetBank(iop_base, 0);
6407 AscSetChipSyn(iop_base, sdtr_data);
6408 if (AscGetChipSyn(iop_base) != sdtr_data) {
d647c783 6409 sta = false;
51219358
MW		 6410 }
6411 } else {
d647c783 6412 sta = false;
51219358
MW		 6413 }
6414 AscSetBank(iop_base, 1);
6415 AscWriteChipDvcID(iop_base, org_id);
6416 AscSetBank(iop_base, 0);
6417 return (sta);
6418}
6419
6420static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no)
6421{
6422 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
6423 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data);
6424}
6425
6f0d2e1d 6426static void AscIsrChipHalted(ASC_DVC_VAR *asc_dvc)
51219358
MW		 6427{
6428 EXT_MSG ext_msg;
6429 EXT_MSG out_msg;
6430 ushort halt_q_addr;
ae26759e 6431 bool sdtr_accept;
51219358
MW		 6432 ushort int_halt_code;
6433 ASC_SCSI_BIT_ID_TYPE scsi_busy;
6434 ASC_SCSI_BIT_ID_TYPE target_id;
6435 PortAddr iop_base;
6436 uchar tag_code;
6437 uchar q_status;
6438 uchar halt_qp;
6439 uchar sdtr_data;
6440 uchar target_ix;
6441 uchar q_cntl, tid_no;
6442 uchar cur_dvc_qng;
6443 uchar asyn_sdtr;
6444 uchar scsi_status;
d2411495 6445 struct asc_board *boardp;
51219358
MW		 6446
6447 BUG_ON(!asc_dvc->drv_ptr);
6448 boardp = asc_dvc->drv_ptr;
6449
6450 iop_base = asc_dvc->iop_base;
6451 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W);
6452
6453 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B);
6454 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp);
6455 target_ix = AscReadLramByte(iop_base,
6456 (ushort)(halt_q_addr +
6457 (ushort)ASC_SCSIQ_B_TARGET_IX));
6458 q_cntl = AscReadLramByte(iop_base,
6459 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6460 tid_no = ASC_TIX_TO_TID(target_ix);
6461 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no);
6462 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6463 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB;
6464 } else {
6465 asyn_sdtr = 0;
6466 }
6467 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) {
6468 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6469 AscSetChipSDTR(iop_base, 0, tid_no);
6470 boardp->sdtr_data[tid_no] = 0;
6471 }
6472 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6473 return;
51219358
MW		 6474 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) {
6475 if (asc_dvc->pci_fix_asyn_xfer & target_id) {
6476 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6477 boardp->sdtr_data[tid_no] = asyn_sdtr;
6478 }
6479 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6480 return;
51219358
MW		 6481 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) {
6482 AscMemWordCopyPtrFromLram(iop_base,
6483 ASCV_MSGIN_BEG,
6484 (uchar *)&ext_msg,
6485 sizeof(EXT_MSG) >> 1);
6486
6487 if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6488 ext_msg.msg_req == EXTENDED_SDTR &&
6489 ext_msg.msg_len == MS_SDTR_LEN) {
ae26759e 6490 sdtr_accept = true;
51219358
MW		 6491 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) {
6492
ae26759e 6493 sdtr_accept = false;
51219358
MW		 6494 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET;
6495 }
6496 if ((ext_msg.xfer_period <
afbb68c3 6497 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index])
51219358
MW		 6498 || (ext_msg.xfer_period >
6499 asc_dvc->sdtr_period_tbl[asc_dvc->
6500 max_sdtr_index])) {
ae26759e 6501 sdtr_accept = false;
51219358
MW		 6502 ext_msg.xfer_period =
6503 asc_dvc->sdtr_period_tbl[asc_dvc->
afbb68c3 6504 min_sdtr_index];
51219358
MW		 6505 }
6506 if (sdtr_accept) {
6507 sdtr_data =
6508 AscCalSDTRData(asc_dvc, ext_msg.xfer_period,
6509 ext_msg.req_ack_offset);
6510 if ((sdtr_data == 0xFF)) {
6511
6512 q_cntl |= QC_MSG_OUT;
6513 asc_dvc->init_sdtr &= ~target_id;
6514 asc_dvc->sdtr_done &= ~target_id;
6515 AscSetChipSDTR(iop_base, asyn_sdtr,
6516 tid_no);
6517 boardp->sdtr_data[tid_no] = asyn_sdtr;
6518 }
6519 }
6520 if (ext_msg.req_ack_offset == 0) {
6521
6522 q_cntl &= ~QC_MSG_OUT;
6523 asc_dvc->init_sdtr &= ~target_id;
6524 asc_dvc->sdtr_done &= ~target_id;
6525 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6526 } else {
6527 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) {
51219358
MW		 6528 q_cntl &= ~QC_MSG_OUT;
6529 asc_dvc->sdtr_done |= target_id;
6530 asc_dvc->init_sdtr |= target_id;
6531 asc_dvc->pci_fix_asyn_xfer &=
6532 ~target_id;
6533 sdtr_data =
6534 AscCalSDTRData(asc_dvc,
6535 ext_msg.xfer_period,
6536 ext_msg.
6537 req_ack_offset);
6538 AscSetChipSDTR(iop_base, sdtr_data,
6539 tid_no);
6540 boardp->sdtr_data[tid_no] = sdtr_data;
6541 } else {
51219358
MW		 6542 q_cntl |= QC_MSG_OUT;
6543 AscMsgOutSDTR(asc_dvc,
6544 ext_msg.xfer_period,
6545 ext_msg.req_ack_offset);
6546 asc_dvc->pci_fix_asyn_xfer &=
6547 ~target_id;
6548 sdtr_data =
6549 AscCalSDTRData(asc_dvc,
6550 ext_msg.xfer_period,
6551 ext_msg.
6552 req_ack_offset);
6553 AscSetChipSDTR(iop_base, sdtr_data,
6554 tid_no);
6555 boardp->sdtr_data[tid_no] = sdtr_data;
6556 asc_dvc->sdtr_done |= target_id;
6557 asc_dvc->init_sdtr |= target_id;
6558 }
6559 }
6560
6561 AscWriteLramByte(iop_base,
6562 (ushort)(halt_q_addr +
6563 (ushort)ASC_SCSIQ_B_CNTL),
6564 q_cntl);
6565 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6566 return;
51219358
MW		 6567 } else if (ext_msg.msg_type == EXTENDED_MESSAGE &&
6568 ext_msg.msg_req == EXTENDED_WDTR &&
6569 ext_msg.msg_len == MS_WDTR_LEN) {
6570
6571 ext_msg.wdtr_width = 0;
6572 AscMemWordCopyPtrToLram(iop_base,
6573 ASCV_MSGOUT_BEG,
6574 (uchar *)&ext_msg,
6575 sizeof(EXT_MSG) >> 1);
6576 q_cntl |= QC_MSG_OUT;
6577 AscWriteLramByte(iop_base,
6578 (ushort)(halt_q_addr +
6579 (ushort)ASC_SCSIQ_B_CNTL),
6580 q_cntl);
6581 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6582 return;
51219358
MW		 6583 } else {
6584
6585 ext_msg.msg_type = MESSAGE_REJECT;
6586 AscMemWordCopyPtrToLram(iop_base,
6587 ASCV_MSGOUT_BEG,
6588 (uchar *)&ext_msg,
6589 sizeof(EXT_MSG) >> 1);
6590 q_cntl |= QC_MSG_OUT;
6591 AscWriteLramByte(iop_base,
6592 (ushort)(halt_q_addr +
6593 (ushort)ASC_SCSIQ_B_CNTL),
6594 q_cntl);
6595 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6596 return;
51219358
MW		 6597 }
6598 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) {
6599
6600 q_cntl |= QC_REQ_SENSE;
6601
6602 if ((asc_dvc->init_sdtr & target_id) != 0) {
6603
6604 asc_dvc->sdtr_done &= ~target_id;
6605
6606 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
6607 q_cntl |= QC_MSG_OUT;
6608 AscMsgOutSDTR(asc_dvc,
6609 asc_dvc->
6610 sdtr_period_tbl[(sdtr_data >> 4) &
6611 (uchar)(asc_dvc->
6612 max_sdtr_index -
6613 1)],
6614 (uchar)(sdtr_data & (uchar)
6615 ASC_SYN_MAX_OFFSET));
6616 }
6617
6618 AscWriteLramByte(iop_base,
6619 (ushort)(halt_q_addr +
6620 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6621
6622 tag_code = AscReadLramByte(iop_base,
6623 (ushort)(halt_q_addr + (ushort)
6624 ASC_SCSIQ_B_TAG_CODE));
6625 tag_code &= 0xDC;
6626 if ((asc_dvc->pci_fix_asyn_xfer & target_id)
6627 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id)
6628 ) {
6629
6630 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT
6631 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX);
6632
6633 }
6634 AscWriteLramByte(iop_base,
6635 (ushort)(halt_q_addr +
6636 (ushort)ASC_SCSIQ_B_TAG_CODE),
6637 tag_code);
6638
6639 q_status = AscReadLramByte(iop_base,
6640 (ushort)(halt_q_addr + (ushort)
6641 ASC_SCSIQ_B_STATUS));
6642 q_status |= (QS_READY | QS_BUSY);
6643 AscWriteLramByte(iop_base,
6644 (ushort)(halt_q_addr +
6645 (ushort)ASC_SCSIQ_B_STATUS),
6646 q_status);
6647
6648 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B);
6649 scsi_busy &= ~target_id;
6650 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6651
6652 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6653 return;
51219358
MW		 6654 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) {
6655
6656 AscMemWordCopyPtrFromLram(iop_base,
6657 ASCV_MSGOUT_BEG,
6658 (uchar *)&out_msg,
6659 sizeof(EXT_MSG) >> 1);
6660
6661 if ((out_msg.msg_type == EXTENDED_MESSAGE) &&
6662 (out_msg.msg_len == MS_SDTR_LEN) &&
6663 (out_msg.msg_req == EXTENDED_SDTR)) {
6664
6665 asc_dvc->init_sdtr &= ~target_id;
6666 asc_dvc->sdtr_done &= ~target_id;
6667 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no);
6668 boardp->sdtr_data[tid_no] = asyn_sdtr;
6669 }
6670 q_cntl &= ~QC_MSG_OUT;
6671 AscWriteLramByte(iop_base,
6672 (ushort)(halt_q_addr +
6673 (ushort)ASC_SCSIQ_B_CNTL), q_cntl);
6674 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6675 return;
51219358
MW		 6676 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) {
6677
6678 scsi_status = AscReadLramByte(iop_base,
6679 (ushort)((ushort)halt_q_addr +
6680 (ushort)
6681 ASC_SCSIQ_SCSI_STATUS));
6682 cur_dvc_qng =
6683 AscReadLramByte(iop_base,
6684 (ushort)((ushort)ASC_QADR_BEG +
6685 (ushort)target_ix));
6686 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) {
6687
6688 scsi_busy = AscReadLramByte(iop_base,
6689 (ushort)ASCV_SCSIBUSY_B);
6690 scsi_busy |= target_id;
6691 AscWriteLramByte(iop_base,
6692 (ushort)ASCV_SCSIBUSY_B, scsi_busy);
6693 asc_dvc->queue_full_or_busy |= target_id;
6694
6695 if (scsi_status == SAM_STAT_TASK_SET_FULL) {
6696 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) {
6697 cur_dvc_qng -= 1;
6698 asc_dvc->max_dvc_qng[tid_no] =
6699 cur_dvc_qng;
6700
6701 AscWriteLramByte(iop_base,
6702 (ushort)((ushort)
6703 ASCV_MAX_DVC_QNG_BEG
6704 + (ushort)
6705 tid_no),
6706 cur_dvc_qng);
6707
6708 /*
6709 * Set the device queue depth to the
6710 * number of active requests when the
6711 * QUEUE FULL condition was encountered.
6712 */
6713 boardp->queue_full |= target_id;
6714 boardp->queue_full_cnt[tid_no] =
6715 cur_dvc_qng;
6716 }
6717 }
6718 }
6719 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6720 return;
51219358
MW		 6721 }
6722#if CC_VERY_LONG_SG_LIST
6723 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) {
6724 uchar q_no;
6725 ushort q_addr;
6726 uchar sg_wk_q_no;
6727 uchar first_sg_wk_q_no;
6728 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */
6729 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */
6730 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */
6731 ushort sg_list_dwords;
6732 ushort sg_entry_cnt;
6733 uchar next_qp;
6734 int i;
6735
6736 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP);
6737 if (q_no == ASC_QLINK_END)
6738 return 0;
6739
6740 q_addr = ASC_QNO_TO_QADDR(q_no);
6741
6742 /*
9fef6ba4 6743 * Convert the request's SRB pointer to a host ASC_SCSI_Q
51219358 6744 * structure pointer using a macro provided by the driver.
9fef6ba4 6745 * The ASC_SCSI_Q pointer provides a pointer to the
51219358
MW		 6746 * host ASC_SG_HEAD structure.
6747 */
6748 /* Read request's SRB pointer. */
6749 scsiq = (ASC_SCSI_Q *)
6750 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base,
6751 (ushort)
6752 (q_addr +
6753 ASC_SCSIQ_D_SRBPTR))));
6754
6755 /*
6756 * Get request's first and working SG queue.
6757 */
6758 sg_wk_q_no = AscReadLramByte(iop_base,
6759 (ushort)(q_addr +
6760 ASC_SCSIQ_B_SG_WK_QP));
6761
6762 first_sg_wk_q_no = AscReadLramByte(iop_base,
6763 (ushort)(q_addr +
6764 ASC_SCSIQ_B_FIRST_SG_WK_QP));
6765
6766 /*
6767 * Reset request's working SG queue back to the
6768 * first SG queue.
6769 */
6770 AscWriteLramByte(iop_base,
6771 (ushort)(q_addr +
6772 (ushort)ASC_SCSIQ_B_SG_WK_QP),
6773 first_sg_wk_q_no);
6774
6775 sg_head = scsiq->sg_head;
6776
6777 /*
6778 * Set sg_entry_cnt to the number of SG elements
6779 * that will be completed on this interrupt.
6780 *
6781 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1
6782 * SG elements. The data_cnt and data_addr fields which
6783 * add 1 to the SG element capacity are not used when
6784 * restarting SG handling after a halt.
6785 */
6786 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) {
6787 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
6788
6789 /*
6790 * Keep track of remaining number of SG elements that
6791 * will need to be handled on the next interrupt.
6792 */
6793 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1);
6794 } else {
6795 sg_entry_cnt = scsiq->remain_sg_entry_cnt;
6796 scsiq->remain_sg_entry_cnt = 0;
6797 }
6798
6799 /*
6800 * Copy SG elements into the list of allocated SG queues.
6801 *
6802 * Last index completed is saved in scsiq->next_sg_index.
6803 */
6804 next_qp = first_sg_wk_q_no;
6805 q_addr = ASC_QNO_TO_QADDR(next_qp);
6806 scsi_sg_q.sg_head_qp = q_no;
6807 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
6808 for (i = 0; i < sg_head->queue_cnt; i++) {
6809 scsi_sg_q.seq_no = i + 1;
6810 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
6811 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
6812 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
6813 /*
6814 * After very first SG queue RISC FW uses next
6815 * SG queue first element then checks sg_list_cnt
6816 * against zero and then decrements, so set
6817 * sg_list_cnt 1 less than number of SG elements
6818 * in each SG queue.
6819 */
6820 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1;
6821 scsi_sg_q.sg_cur_list_cnt =
6822 ASC_SG_LIST_PER_Q - 1;
6823 } else {
6824 /*
6825 * This is the last SG queue in the list of
6826 * allocated SG queues. If there are more
6827 * SG elements than will fit in the allocated
6828 * queues, then set the QCSG_SG_XFER_MORE flag.
6829 */
6830 if (scsiq->remain_sg_entry_cnt != 0) {
6831 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
6832 } else {
6833 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
6834 }
6835 /* equals sg_entry_cnt * 2 */
6836 sg_list_dwords = sg_entry_cnt << 1;
6837 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1;
6838 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1;
6839 sg_entry_cnt = 0;
6840 }
6841
6842 scsi_sg_q.q_no = next_qp;
6843 AscMemWordCopyPtrToLram(iop_base,
6844 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
6845 (uchar *)&scsi_sg_q,
6846 sizeof(ASC_SG_LIST_Q) >> 1);
6847
6848 AscMemDWordCopyPtrToLram(iop_base,
6849 q_addr + ASC_SGQ_LIST_BEG,
6850 (uchar *)&sg_head->
6851 sg_list[scsiq->next_sg_index],
6852 sg_list_dwords);
6853
6854 scsiq->next_sg_index += ASC_SG_LIST_PER_Q;
6855
6856 /*
6857 * If the just completed SG queue contained the
6858 * last SG element, then no more SG queues need
6859 * to be written.
6860 */
6861 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) {
6862 break;
6863 }
6864
6865 next_qp = AscReadLramByte(iop_base,
6866 (ushort)(q_addr +
6867 ASC_SCSIQ_B_FWD));
6868 q_addr = ASC_QNO_TO_QADDR(next_qp);
6869 }
6870
6871 /*
6872 * Clear the halt condition so the RISC will be restarted
6873 * after the return.
6874 */
6875 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
6f0d2e1d 6876 return;
51219358
MW		 6877 }
6878#endif /* CC_VERY_LONG_SG_LIST */
6f0d2e1d 6879 return;
51219358 6880}
1da177e4 6881
1da177e4 6882/*
51219358
MW		 6883 * void
6884 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
1da177e4 6885 *
51219358
MW		 6886 * Calling/Exit State:
6887 * none
1da177e4 6888 *
51219358
MW		 6889 * Description:
6890 * Input an ASC_QDONE_INFO structure from the chip
1da177e4 6891 */
51219358
MW		 6892static void
6893DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words)
6894{
6895 int i;
6896 ushort word;
6897
6898 AscSetChipLramAddr(iop_base, s_addr);
6899 for (i = 0; i < 2 * words; i += 2) {
6900 if (i == 10) {
6901 continue;
6902 }
6903 word = inpw(iop_base + IOP_RAM_DATA);
6904 inbuf[i] = word & 0xff;
6905 inbuf[i + 1] = (word >> 8) & 0xff;
6906 }
6907 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words);
6908}
6909
6910static uchar
6911_AscCopyLramScsiDoneQ(PortAddr iop_base,
6912 ushort q_addr,
95cfab6c 6913 ASC_QDONE_INFO *scsiq, unsigned int max_dma_count)
51219358
MW		 6914{
6915 ushort _val;
6916 uchar sg_queue_cnt;
6917
6918 DvcGetQinfo(iop_base,
6919 q_addr + ASC_SCSIQ_DONE_INFO_BEG,
6920 (uchar *)scsiq,
6921 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2);
6922
6923 _val = AscReadLramWord(iop_base,
6924 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS));
6925 scsiq->q_status = (uchar)_val;
6926 scsiq->q_no = (uchar)(_val >> 8);
6927 _val = AscReadLramWord(iop_base,
6928 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL));
6929 scsiq->cntl = (uchar)_val;
6930 sg_queue_cnt = (uchar)(_val >> 8);
6931 _val = AscReadLramWord(iop_base,
6932 (ushort)(q_addr +
6933 (ushort)ASC_SCSIQ_B_SENSE_LEN));
6934 scsiq->sense_len = (uchar)_val;
6935 scsiq->extra_bytes = (uchar)(_val >> 8);
6936
6937 /*
6938 * Read high word of remain bytes from alternate location.
6939 */
95cfab6c
HR		 6940 scsiq->remain_bytes = (((u32)AscReadLramWord(iop_base,
6941 (ushort)(q_addr +
6942 (ushort)
6943 ASC_SCSIQ_W_ALT_DC1)))
51219358
MW		 6944 << 16);
6945 /*
6946 * Read low word of remain bytes from original location.
6947 */
6948 scsiq->remain_bytes += AscReadLramWord(iop_base,
6949 (ushort)(q_addr + (ushort)
6950 ASC_SCSIQ_DW_REMAIN_XFER_CNT));
6951
6952 scsiq->remain_bytes &= max_dma_count;
6953 return sg_queue_cnt;
6954}
6955
6956/*
6957 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR().
6958 *
6959 * Interrupt callback function for the Narrow SCSI Asc Library.
6960 */
6961static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep)
6962{
9c17c62a
HR		 6963 struct asc_board *boardp = asc_dvc_varp->drv_ptr;
6964 u32 srb_tag;
51219358 6965 struct scsi_cmnd *scp;
51219358 6966
b352f923 6967 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep);
51219358
MW		 6968 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep);
6969
9c17c62a
HR		 6970 /*
6971 * Decrease the srb_tag by 1 to find the SCSI command
6972 */
6973 srb_tag = qdonep->d2.srb_tag - 1;
6974 scp = scsi_host_find_tag(boardp->shost, srb_tag);
b249c7fd 6975 if (!scp)
51219358 6976 return;
b249c7fd 6977
51219358
MW		 6978 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len);
6979
9c17c62a 6980 ASC_STATS(boardp->shost, callback);
51219358 6981
b249c7fd 6982 dma_unmap_single(boardp->dev, scp->SCp.dma_handle,
b80ca4f7 6983 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
51219358
MW		 6984 /*
6985 * 'qdonep' contains the command's ending status.
6986 */
6987 switch (qdonep->d3.done_stat) {
6988 case QD_NO_ERROR:
b352f923 6989 ASC_DBG(2, "QD_NO_ERROR\n");
51219358
MW		 6990 scp->result = 0;
6991
6992 /*
6993 * Check for an underrun condition.
6994 *
6995 * If there was no error and an underrun condition, then
6996 * return the number of underrun bytes.
6997 */
52c334e9
MW		 6998 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 &&
6999 qdonep->remain_bytes <= scsi_bufflen(scp)) {
b352f923 7000 ASC_DBG(1, "underrun condition %u bytes\n",
51219358 7001 (unsigned)qdonep->remain_bytes);
52c334e9 7002 scsi_set_resid(scp, qdonep->remain_bytes);
51219358
MW		 7003 }
7004 break;
7005
7006 case QD_WITH_ERROR:
b352f923 7007 ASC_DBG(2, "QD_WITH_ERROR\n");
51219358
MW		 7008 switch (qdonep->d3.host_stat) {
7009 case QHSTA_NO_ERROR:
7010 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) {
b352f923 7011 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n");
51219358 7012 ASC_DBG_PRT_SENSE(2, scp->sense_buffer,
b80ca4f7 7013 SCSI_SENSE_BUFFERSIZE);
51219358
MW		 7014 /*
7015 * Note: The 'status_byte()' macro used by
7016 * target drivers defined in scsi.h shifts the
7017 * status byte returned by host drivers right
7018 * by 1 bit. This is why target drivers also
7019 * use right shifted status byte definitions.
7020 * For instance target drivers use
7021 * CHECK_CONDITION, defined to 0x1, instead of
7022 * the SCSI defined check condition value of
7023 * 0x2. Host drivers are supposed to return
7024 * the status byte as it is defined by SCSI.
7025 */
7026 scp->result = DRIVER_BYTE(DRIVER_SENSE) |
7027 STATUS_BYTE(qdonep->d3.scsi_stat);
7028 } else {
7029 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat);
7030 }
7031 break;
7032
7033 default:
7034 /* QHSTA error occurred */
b352f923 7035 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat);
51219358
MW		 7036 scp->result = HOST_BYTE(DID_BAD_TARGET);
7037 break;
7038 }
7039 break;
7040
7041 case QD_ABORTED_BY_HOST:
b352f923 7042 ASC_DBG(1, "QD_ABORTED_BY_HOST\n");
51219358
MW		 7043 scp->result =
7044 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3.
7045 scsi_msg) |
7046 STATUS_BYTE(qdonep->d3.scsi_stat);
7047 break;
7048
7049 default:
b352f923 7050 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat);
51219358
MW		 7051 scp->result =
7052 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3.
7053 scsi_msg) |
7054 STATUS_BYTE(qdonep->d3.scsi_stat);
7055 break;
7056 }
7057
7058 /*
7059 * If the 'init_tidmask' bit isn't already set for the target and the
7060 * current request finished normally, then set the bit for the target
7061 * to indicate that a device is present.
7062 */
7063 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 &&
7064 qdonep->d3.done_stat == QD_NO_ERROR &&
7065 qdonep->d3.host_stat == QHSTA_NO_ERROR) {
7066 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id);
7067 }
1da177e4 7068
51219358 7069 asc_scsi_done(scp);
51219358
MW		 7070}
7071
7072static int AscIsrQDone(ASC_DVC_VAR *asc_dvc)
7073{
7074 uchar next_qp;
7075 uchar n_q_used;
7076 uchar sg_list_qp;
7077 uchar sg_queue_cnt;
7078 uchar q_cnt;
7079 uchar done_q_tail;
7080 uchar tid_no;
7081 ASC_SCSI_BIT_ID_TYPE scsi_busy;
7082 ASC_SCSI_BIT_ID_TYPE target_id;
7083 PortAddr iop_base;
7084 ushort q_addr;
7085 ushort sg_q_addr;
7086 uchar cur_target_qng;
7087 ASC_QDONE_INFO scsiq_buf;
7088 ASC_QDONE_INFO *scsiq;
ae26759e 7089 bool false_overrun;
51219358
MW		 7090
7091 iop_base = asc_dvc->iop_base;
7092 n_q_used = 1;
7093 scsiq = (ASC_QDONE_INFO *)&scsiq_buf;
7094 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base);
7095 q_addr = ASC_QNO_TO_QADDR(done_q_tail);
7096 next_qp = AscReadLramByte(iop_base,
7097 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD));
7098 if (next_qp != ASC_QLINK_END) {
7099 AscPutVarDoneQTail(iop_base, next_qp);
7100 q_addr = ASC_QNO_TO_QADDR(next_qp);
7101 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq,
7102 asc_dvc->max_dma_count);
7103 AscWriteLramByte(iop_base,
7104 (ushort)(q_addr +
7105 (ushort)ASC_SCSIQ_B_STATUS),
7106 (uchar)(scsiq->
7107 q_status & (uchar)~(QS_READY |
7108 QS_ABORTED)));
7109 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix);
7110 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix);
7111 if ((scsiq->cntl & QC_SG_HEAD) != 0) {
7112 sg_q_addr = q_addr;
7113 sg_list_qp = next_qp;
7114 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) {
7115 sg_list_qp = AscReadLramByte(iop_base,
7116 (ushort)(sg_q_addr
7117 + (ushort)
7118 ASC_SCSIQ_B_FWD));
7119 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp);
7120 if (sg_list_qp == ASC_QLINK_END) {
7121 AscSetLibErrorCode(asc_dvc,
7122 ASCQ_ERR_SG_Q_LINKS);
7123 scsiq->d3.done_stat = QD_WITH_ERROR;
7124 scsiq->d3.host_stat =
7125 QHSTA_D_QDONE_SG_LIST_CORRUPTED;
7126 goto FATAL_ERR_QDONE;
7127 }
7128 AscWriteLramByte(iop_base,
7129 (ushort)(sg_q_addr + (ushort)
7130 ASC_SCSIQ_B_STATUS),
7131 QS_FREE);
7132 }
7133 n_q_used = sg_queue_cnt + 1;
7134 AscPutVarDoneQTail(iop_base, sg_list_qp);
7135 }
7136 if (asc_dvc->queue_full_or_busy & target_id) {
7137 cur_target_qng = AscReadLramByte(iop_base,
7138 (ushort)((ushort)
7139 ASC_QADR_BEG
7140 + (ushort)
7141 scsiq->d2.
7142 target_ix));
7143 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) {
7144 scsi_busy = AscReadLramByte(iop_base, (ushort)
7145 ASCV_SCSIBUSY_B);
7146 scsi_busy &= ~target_id;
7147 AscWriteLramByte(iop_base,
7148 (ushort)ASCV_SCSIBUSY_B,
7149 scsi_busy);
7150 asc_dvc->queue_full_or_busy &= ~target_id;
7151 }
7152 }
7153 if (asc_dvc->cur_total_qng >= n_q_used) {
7154 asc_dvc->cur_total_qng -= n_q_used;
7155 if (asc_dvc->cur_dvc_qng[tid_no] != 0) {
7156 asc_dvc->cur_dvc_qng[tid_no]--;
7157 }
7158 } else {
7159 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG);
7160 scsiq->d3.done_stat = QD_WITH_ERROR;
7161 goto FATAL_ERR_QDONE;
7162 }
9c17c62a 7163 if ((scsiq->d2.srb_tag == 0UL) ||
51219358
MW		 7164 ((scsiq->q_status & QS_ABORTED) != 0)) {
7165 return (0x11);
7166 } else if (scsiq->q_status == QS_DONE) {
ae26759e
HR		 7167 /*
7168 * This is also curious.
7169 * false_overrun will _always_ be set to 'false'
7170 */
7171 false_overrun = false;
51219358 7172 if (scsiq->extra_bytes != 0) {
95cfab6c 7173 scsiq->remain_bytes += scsiq->extra_bytes;
51219358
MW		 7174 }
7175 if (scsiq->d3.done_stat == QD_WITH_ERROR) {
7176 if (scsiq->d3.host_stat ==
7177 QHSTA_M_DATA_OVER_RUN) {
7178 if ((scsiq->
7179 cntl & (QC_DATA_IN | QC_DATA_OUT))
7180 == 0) {
7181 scsiq->d3.done_stat =
7182 QD_NO_ERROR;
7183 scsiq->d3.host_stat =
7184 QHSTA_NO_ERROR;
7185 } else if (false_overrun) {
7186 scsiq->d3.done_stat =
7187 QD_NO_ERROR;
7188 scsiq->d3.host_stat =
7189 QHSTA_NO_ERROR;
7190 }
7191 } else if (scsiq->d3.host_stat ==
7192 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) {
7193 AscStopChip(iop_base);
7194 AscSetChipControl(iop_base,
7195 (uchar)(CC_SCSI_RESET
7196 | CC_HALT));
7197 udelay(60);
7198 AscSetChipControl(iop_base, CC_HALT);
7199 AscSetChipStatus(iop_base,
7200 CIW_CLR_SCSI_RESET_INT);
7201 AscSetChipStatus(iop_base, 0);
7202 AscSetChipControl(iop_base, 0);
7203 }
7204 }
7205 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7206 asc_isr_callback(asc_dvc, scsiq);
7207 } else {
7208 if ((AscReadLramByte(iop_base,
7209 (ushort)(q_addr + (ushort)
7210 ASC_SCSIQ_CDB_BEG))
7211 == START_STOP)) {
7212 asc_dvc->unit_not_ready &= ~target_id;
7213 if (scsiq->d3.done_stat != QD_NO_ERROR) {
7214 asc_dvc->start_motor &=
7215 ~target_id;
7216 }
7217 }
7218 }
7219 return (1);
7220 } else {
7221 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS);
7222 FATAL_ERR_QDONE:
7223 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) {
7224 asc_isr_callback(asc_dvc, scsiq);
7225 }
7226 return (0x80);
7227 }
7228 }
7229 return (0);
7230}
1da177e4 7231
51219358
MW		 7232static int AscISR(ASC_DVC_VAR *asc_dvc)
7233{
7234 ASC_CS_TYPE chipstat;
7235 PortAddr iop_base;
7236 ushort saved_ram_addr;
7237 uchar ctrl_reg;
7238 uchar saved_ctrl_reg;
7239 int int_pending;
7240 int status;
7241 uchar host_flag;
1da177e4 7242
51219358 7243 iop_base = asc_dvc->iop_base;
ae26759e 7244 int_pending = ASC_FALSE;
1da177e4 7245
51219358
MW		 7246 if (AscIsIntPending(iop_base) == 0)
7247 return int_pending;
7248
7249 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) {
ae26759e 7250 return ASC_ERROR;
51219358
MW		 7251 }
7252 if (asc_dvc->in_critical_cnt != 0) {
7253 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL);
ae26759e 7254 return ASC_ERROR;
51219358
MW		 7255 }
7256 if (asc_dvc->is_in_int) {
7257 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY);
ae26759e 7258 return ASC_ERROR;
51219358 7259 }
ae26759e 7260 asc_dvc->is_in_int = true;
51219358
MW		 7261 ctrl_reg = AscGetChipControl(iop_base);
7262 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET |
7263 CC_SINGLE_STEP | CC_DIAG | CC_TEST));
7264 chipstat = AscGetChipStatus(iop_base);
7265 if (chipstat & CSW_SCSI_RESET_LATCH) {
7266 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) {
7267 int i = 10;
ae26759e 7268 int_pending = ASC_TRUE;
51219358
MW		 7269 asc_dvc->sdtr_done = 0;
7270 saved_ctrl_reg &= (uchar)(~CC_HALT);
7271 while ((AscGetChipStatus(iop_base) &
7272 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) {
7273 mdelay(100);
7274 }
7275 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT));
7276 AscSetChipControl(iop_base, CC_HALT);
7277 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
7278 AscSetChipStatus(iop_base, 0);
7279 chipstat = AscGetChipStatus(iop_base);
7280 }
7281 }
7282 saved_ram_addr = AscGetChipLramAddr(iop_base);
7283 host_flag = AscReadLramByte(iop_base,
7284 ASCV_HOST_FLAG_B) &
7285 (uchar)(~ASC_HOST_FLAG_IN_ISR);
7286 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B,
7287 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR));
7288 if ((chipstat & CSW_INT_PENDING) || (int_pending)) {
7289 AscAckInterrupt(iop_base);
ae26759e 7290 int_pending = ASC_TRUE;
51219358 7291 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) {
6f0d2e1d
HR		 7292 AscIsrChipHalted(asc_dvc);
7293 saved_ctrl_reg &= (uchar)(~CC_HALT);
51219358 7294 } else {
51219358
MW		 7295 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) {
7296 while (((status =
7297 AscIsrQDone(asc_dvc)) & 0x01) != 0) {
7298 }
7299 } else {
7300 do {
7301 if ((status =
7302 AscIsrQDone(asc_dvc)) == 1) {
7303 break;
7304 }
7305 } while (status == 0x11);
7306 }
7307 if ((status & 0x80) != 0)
ae26759e 7308 int_pending = ASC_ERROR;
51219358
MW		 7309 }
7310 }
7311 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag);
7312 AscSetChipLramAddr(iop_base, saved_ram_addr);
7313 AscSetChipControl(iop_base, saved_ctrl_reg);
ae26759e 7314 asc_dvc->is_in_int = false;
51219358
MW		 7315 return int_pending;
7316}
1da177e4
LT		 7317
7318/*
51219358 7319 * advansys_reset()
1da177e4 7320 *
eac0b0c7 7321 * Reset the host associated with the command 'scp'.
1da177e4 7322 *
51219358
MW		 7323 * This function runs its own thread. Interrupts must be blocked but
7324 * sleeping is allowed and no locking other than for host structures is
7325 * required. Returns SUCCESS or FAILED.
1da177e4 7326 */
51219358 7327static int advansys_reset(struct scsi_cmnd *scp)
1da177e4 7328{
52fa0777 7329 struct Scsi_Host *shost = scp->device->host;
d2411495 7330 struct asc_board *boardp = shost_priv(shost);
52fa0777 7331 unsigned long flags;
27c868c2 7332 int status;
51219358 7333 int ret = SUCCESS;
27c868c2 7334
b352f923 7335 ASC_DBG(1, "0x%p\n", scp);
27c868c2 7336
52fa0777 7337 ASC_STATS(shost, reset);
27c868c2 7338
eac0b0c7 7339 scmd_printk(KERN_INFO, scp, "SCSI host reset started...\n");
51219358
MW		 7340
7341 if (ASC_NARROW_BOARD(boardp)) {
52fa0777 7342 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
1da177e4 7343
52fa0777 7344 /* Reset the chip and SCSI bus. */
b352f923 7345 ASC_DBG(1, "before AscInitAsc1000Driver()\n");
52fa0777 7346 status = AscInitAsc1000Driver(asc_dvc);
27c868c2 7347
6070d81e 7348 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */
9a908c1a 7349 if (asc_dvc->err_code || !asc_dvc->overrun_dma) {
eac0b0c7 7350 scmd_printk(KERN_INFO, scp, "SCSI host reset error: "
9a908c1a
HRK		 7351 "0x%x, status: 0x%x\n", asc_dvc->err_code,
7352 status);
51219358
MW		 7353 ret = FAILED;
7354 } else if (status) {
eac0b0c7 7355 scmd_printk(KERN_INFO, scp, "SCSI host reset warning: "
52fa0777 7356 "0x%x\n", status);
27c868c2 7357 } else {
eac0b0c7 7358 scmd_printk(KERN_INFO, scp, "SCSI host reset "
52fa0777 7359 "successful\n");
27c868c2 7360 }
a9f4a59a 7361
b352f923 7362 ASC_DBG(1, "after AscInitAsc1000Driver()\n");
a9f4a59a 7363 } else {
a9f4a59a 7364 /*
51219358
MW		 7365 * If the suggest reset bus flags are set, then reset the bus.
7366 * Otherwise only reset the device.
a9f4a59a 7367 */
52fa0777 7368 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
a9f4a59a
MW		 7369
7370 /*
eac0b0c7 7371 * Reset the chip and SCSI bus.
a9f4a59a 7372 */
b352f923 7373 ASC_DBG(1, "before AdvResetChipAndSB()\n");
52fa0777 7374 switch (AdvResetChipAndSB(adv_dvc)) {
51219358 7375 case ASC_TRUE:
eac0b0c7 7376 scmd_printk(KERN_INFO, scp, "SCSI host reset "
52fa0777 7377 "successful\n");
51219358
MW		 7378 break;
7379 case ASC_FALSE:
7380 default:
eac0b0c7 7381 scmd_printk(KERN_INFO, scp, "SCSI host reset error\n");
51219358
MW		 7382 ret = FAILED;
7383 break;
b9d96614 7384 }
f092d229 7385 spin_lock_irqsave(shost->host_lock, flags);
52fa0777 7386 AdvISR(adv_dvc);
eac0b0c7 7387 spin_unlock_irqrestore(shost->host_lock, flags);
b9d96614
MW		 7388 }
7389
b352f923 7390 ASC_DBG(1, "ret %d\n", ret);
b9d96614 7391
51219358 7392 return ret;
b9d96614
MW		 7393}
7394
1da177e4 7395/*
51219358 7396 * advansys_biosparam()
1da177e4 7397 *
51219358
MW		 7398 * Translate disk drive geometry if the "BIOS greater than 1 GB"
7399 * support is enabled for a drive.
1da177e4 7400 *
51219358
MW		 7401 * ip (information pointer) is an int array with the following definition:
7402 * ip[0]: heads
7403 * ip[1]: sectors
7404 * ip[2]: cylinders
1da177e4 7405 */
51219358
MW		 7406static int
7407advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev,
7408 sector_t capacity, int ip[])
1da177e4 7409{
d2411495 7410 struct asc_board *boardp = shost_priv(sdev->host);
1da177e4 7411
b352f923 7412 ASC_DBG(1, "begin\n");
51219358 7413 ASC_STATS(sdev->host, biosparam);
51219358
MW		 7414 if (ASC_NARROW_BOARD(boardp)) {
7415 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl &
7416 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) {
7417 ip[0] = 255;
7418 ip[1] = 63;
7419 } else {
7420 ip[0] = 64;
7421 ip[1] = 32;
7422 }
7423 } else {
7424 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl &
7425 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) {
7426 ip[0] = 255;
7427 ip[1] = 63;
7428 } else {
7429 ip[0] = 64;
7430 ip[1] = 32;
7431 }
27c868c2 7432 }
51219358 7433 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]);
b352f923 7434 ASC_DBG(1, "end\n");
51219358
MW		 7435 return 0;
7436}
1da177e4 7437
51219358
MW		 7438/*
7439 * First-level interrupt handler.
7440 *
7441 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host.
7442 */
7443static irqreturn_t advansys_interrupt(int irq, void *dev_id)
7444{
51219358 7445 struct Scsi_Host *shost = dev_id;
d2411495 7446 struct asc_board *boardp = shost_priv(shost);
51219358 7447 irqreturn_t result = IRQ_NONE;
27c868c2 7448
b352f923 7449 ASC_DBG(2, "boardp 0x%p\n", boardp);
f092d229 7450 spin_lock(shost->host_lock);
51219358
MW		 7451 if (ASC_NARROW_BOARD(boardp)) {
7452 if (AscIsIntPending(shost->io_port)) {
7453 result = IRQ_HANDLED;
7454 ASC_STATS(shost, interrupt);
b352f923 7455 ASC_DBG(1, "before AscISR()\n");
51219358
MW		 7456 AscISR(&boardp->dvc_var.asc_dvc_var);
7457 }
7458 } else {
b352f923 7459 ASC_DBG(1, "before AdvISR()\n");
51219358
MW		 7460 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) {
7461 result = IRQ_HANDLED;
7462 ASC_STATS(shost, interrupt);
7463 }
27c868c2 7464 }
f092d229 7465 spin_unlock(shost->host_lock);
1da177e4 7466
b352f923 7467 ASC_DBG(1, "end\n");
51219358
MW		 7468 return result;
7469}
27c868c2 7470
d647c783 7471static bool AscHostReqRiscHalt(PortAddr iop_base)
51219358
MW		 7472{
7473 int count = 0;
d647c783 7474 bool sta = false;
51219358
MW		 7475 uchar saved_stop_code;
7476
7477 if (AscIsChipHalted(iop_base))
d647c783 7478 return true;
51219358
MW		 7479 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B);
7480 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
7481 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP);
7482 do {
7483 if (AscIsChipHalted(iop_base)) {
d647c783 7484 sta = true;
51219358 7485 break;
27c868c2 7486 }
51219358
MW		 7487 mdelay(100);
7488 } while (count++ < 20);
7489 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code);
d647c783 7490 return sta;
51219358 7491}
1da177e4 7492
d647c783 7493static bool
51219358
MW		 7494AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data)
7495{
d647c783 7496 bool sta = false;
1da177e4 7497
51219358
MW		 7498 if (AscHostReqRiscHalt(iop_base)) {
7499 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data);
7500 AscStartChip(iop_base);
27c868c2 7501 }
51219358
MW		 7502 return sta;
7503}
1da177e4 7504
51219358
MW		 7505static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev)
7506{
7507 char type = sdev->type;
7508 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id;
27c868c2 7509
51219358
MW		 7510 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN))
7511 return;
7512 if (asc_dvc->init_sdtr & tid_bits)
7513 return;
27c868c2 7514
51219358
MW		 7515 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0))
7516 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits;
27c868c2 7517
51219358
MW		 7518 asc_dvc->pci_fix_asyn_xfer |= tid_bits;
7519 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) ||
7520 (type == TYPE_ROM) || (type == TYPE_TAPE))
7521 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits;
7522
7523 if (asc_dvc->pci_fix_asyn_xfer & tid_bits)
7524 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id,
7525 ASYN_SDTR_DATA_FIX_PCI_REV_AB);
7526}
1da177e4 7527
51219358
MW		 7528static void
7529advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc)
7530{
7531 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id;
7532 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng;
27c868c2 7533
51219358
MW		 7534 if (sdev->lun == 0) {
7535 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr;
7536 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) {
7537 asc_dvc->init_sdtr |= tid_bit;
7538 } else {
7539 asc_dvc->init_sdtr &= ~tid_bit;
7540 }
7541
7542 if (orig_init_sdtr != asc_dvc->init_sdtr)
7543 AscAsyncFix(asc_dvc, sdev);
27c868c2 7544 }
1da177e4 7545
51219358
MW		 7546 if (sdev->tagged_supported) {
7547 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) {
7548 if (sdev->lun == 0) {
7549 asc_dvc->cfg->can_tagged_qng |= tid_bit;
7550 asc_dvc->use_tagged_qng |= tid_bit;
7551 }
db5ed4df 7552 scsi_change_queue_depth(sdev,
51219358 7553 asc_dvc->max_dvc_qng[sdev->id]);
27c868c2 7554 }
51219358
MW		 7555 } else {
7556 if (sdev->lun == 0) {
7557 asc_dvc->cfg->can_tagged_qng &= ~tid_bit;
7558 asc_dvc->use_tagged_qng &= ~tid_bit;
27c868c2
MW		 7559 }
7560 }
1da177e4 7561
51219358
MW		 7562 if ((sdev->lun == 0) &&
7563 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) {
7564 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B,
7565 asc_dvc->cfg->disc_enable);
7566 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B,
7567 asc_dvc->use_tagged_qng);
7568 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B,
7569 asc_dvc->cfg->can_tagged_qng);
27c868c2 7570
51219358
MW		 7571 asc_dvc->max_dvc_qng[sdev->id] =
7572 asc_dvc->cfg->max_tag_qng[sdev->id];
7573 AscWriteLramByte(asc_dvc->iop_base,
7574 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id),
7575 asc_dvc->max_dvc_qng[sdev->id]);
7576 }
7577}
27c868c2 7578
51219358
MW		 7579/*
7580 * Wide Transfers
7581 *
7582 * If the EEPROM enabled WDTR for the device and the device supports wide
7583 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and
7584 * write the new value to the microcode.
7585 */
7586static void
7587advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask)
7588{
7589 unsigned short cfg_word;
7590 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
7591 if ((cfg_word & tidmask) != 0)
7592 return;
27c868c2 7593
51219358
MW		 7594 cfg_word |= tidmask;
7595 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word);
27c868c2
MW		 7596
7597 /*
51219358
MW		 7598 * Clear the microcode SDTR and WDTR negotiation done indicators for
7599 * the target to cause it to negotiate with the new setting set above.
7600 * WDTR when accepted causes the target to enter asynchronous mode, so
7601 * SDTR must be negotiated.
27c868c2 7602 */
51219358
MW		 7603 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7604 cfg_word &= ~tidmask;
7605 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7606 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7607 cfg_word &= ~tidmask;
7608 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word);
7609}
1da177e4 7610
51219358
MW		 7611/*
7612 * Synchronous Transfers
7613 *
7614 * If the EEPROM enabled SDTR for the device and the device
7615 * supports synchronous transfers, then turn on the device's
7616 * 'sdtr_able' bit. Write the new value to the microcode.
7617 */
7618static void
7619advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask)
7620{
7621 unsigned short cfg_word;
7622 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
7623 if ((cfg_word & tidmask) != 0)
7624 return;
1da177e4 7625
51219358
MW		 7626 cfg_word |= tidmask;
7627 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word);
1da177e4 7628
27c868c2 7629 /*
51219358
MW		 7630 * Clear the microcode "SDTR negotiation" done indicator for the
7631 * target to cause it to negotiate with the new setting set above.
27c868c2 7632 */
51219358
MW		 7633 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7634 cfg_word &= ~tidmask;
7635 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word);
7636}
27c868c2 7637
51219358
MW		 7638/*
7639 * PPR (Parallel Protocol Request) Capable
7640 *
7641 * If the device supports DT mode, then it must be PPR capable.
7642 * The PPR message will be used in place of the SDTR and WDTR
7643 * messages to negotiate synchronous speed and offset, transfer
7644 * width, and protocol options.
7645 */
7646static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc,
7647 AdvPortAddr iop_base, unsigned short tidmask)
7648{
7649 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7650 adv_dvc->ppr_able |= tidmask;
7651 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able);
7652}
27c868c2 7653
51219358
MW		 7654static void
7655advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc)
7656{
7657 AdvPortAddr iop_base = adv_dvc->iop_base;
7658 unsigned short tidmask = 1 << sdev->id;
7659
7660 if (sdev->lun == 0) {
7661 /*
7662 * Handle WDTR, SDTR, and Tag Queuing. If the feature
7663 * is enabled in the EEPROM and the device supports the
7664 * feature, then enable it in the microcode.
7665 */
27c868c2 7666
51219358
MW		 7667 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr)
7668 advansys_wide_enable_wdtr(iop_base, tidmask);
7669 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr)
7670 advansys_wide_enable_sdtr(iop_base, tidmask);
7671 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr)
7672 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask);
7673
7674 /*
7675 * Tag Queuing is disabled for the BIOS which runs in polled
7676 * mode and would see no benefit from Tag Queuing. Also by
7677 * disabling Tag Queuing in the BIOS devices with Tag Queuing
7678 * bugs will at least work with the BIOS.
7679 */
7680 if ((adv_dvc->tagqng_able & tidmask) &&
7681 sdev->tagged_supported) {
7682 unsigned short cfg_word;
7683 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word);
7684 cfg_word |= tidmask;
7685 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE,
7686 cfg_word);
7687 AdvWriteByteLram(iop_base,
7688 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id,
7689 adv_dvc->max_dvc_qng);
27c868c2
MW		 7690 }
7691 }
1da177e4 7692
db5ed4df
CH		 7693 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported)
7694 scsi_change_queue_depth(sdev, adv_dvc->max_dvc_qng);
51219358 7695}
27c868c2 7696
51219358
MW		 7697/*
7698 * Set the number of commands to queue per device for the
7699 * specified host adapter.
7700 */
7701static int advansys_slave_configure(struct scsi_device *sdev)
7702{
d2411495 7703 struct asc_board *boardp = shost_priv(sdev->host);
27c868c2 7704
51219358
MW		 7705 if (ASC_NARROW_BOARD(boardp))
7706 advansys_narrow_slave_configure(sdev,
7707 &boardp->dvc_var.asc_dvc_var);
7708 else
7709 advansys_wide_slave_configure(sdev,
7710 &boardp->dvc_var.adv_dvc_var);
1da177e4 7711
51219358
MW		 7712 return 0;
7713}
27c868c2 7714
b249c7fd
MW		 7715static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp)
7716{
7717 struct asc_board *board = shost_priv(scp->device->host);
7718 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer,
b80ca4f7 7719 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
b249c7fd 7720 dma_cache_sync(board->dev, scp->sense_buffer,
b80ca4f7 7721 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
b249c7fd
MW		 7722 return cpu_to_le32(scp->SCp.dma_handle);
7723}
7724
d2411495 7725static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
05848b6e 7726 struct asc_scsi_q *asc_scsi_q)
51219358 7727{
b249c7fd 7728 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var;
52c334e9 7729 int use_sg;
9c17c62a 7730 u32 srb_tag;
52c334e9 7731
05848b6e 7732 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q));
27c868c2
MW		 7733
7734 /*
9c17c62a
HR		 7735 * Set the srb_tag to the command tag + 1, as
7736 * srb_tag '0' is used internally by the chip.
27c868c2 7737 */
9c17c62a
HR		 7738 srb_tag = scp->request->tag + 1;
7739 asc_scsi_q->q2.srb_tag = srb_tag;
27c868c2
MW		 7740
7741 /*
51219358 7742 * Build the ASC_SCSI_Q request.
27c868c2 7743 */
05848b6e
MW		 7744 asc_scsi_q->cdbptr = &scp->cmnd[0];
7745 asc_scsi_q->q2.cdb_len = scp->cmd_len;
7746 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id);
7747 asc_scsi_q->q1.target_lun = scp->device->lun;
7748 asc_scsi_q->q2.target_ix =
51219358 7749 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun);
b249c7fd 7750 asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp);
b80ca4f7 7751 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE;
27c868c2
MW		 7752
7753 /*
51219358
MW		 7754 * If there are any outstanding requests for the current target,
7755 * then every 255th request send an ORDERED request. This heuristic
7756 * tries to retain the benefit of request sorting while preventing
7757 * request starvation. 255 is the max number of tags or pending commands
7758 * a device may have outstanding.
7759 *
7760 * The request count is incremented below for every successfully
7761 * started request.
27c868c2 7762 *
27c868c2 7763 */
b249c7fd 7764 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) &&
51219358 7765 (boardp->reqcnt[scp->device->id] % 255) == 0) {
68d81f40 7766 asc_scsi_q->q2.tag_code = ORDERED_QUEUE_TAG;
51219358 7767 } else {
68d81f40 7768 asc_scsi_q->q2.tag_code = SIMPLE_QUEUE_TAG;
51219358 7769 }
27c868c2 7770
52c334e9
MW		 7771 /* Build ASC_SCSI_Q */
7772 use_sg = scsi_dma_map(scp);
7773 if (use_sg != 0) {
51219358 7774 int sgcnt;
51219358 7775 struct scatterlist *slp;
05848b6e 7776 struct asc_sg_head *asc_sg_head;
27c868c2 7777
51219358 7778 if (use_sg > scp->device->host->sg_tablesize) {
9d0e96eb
MW		 7779 scmd_printk(KERN_ERR, scp, "use_sg %d > "
7780 "sg_tablesize %d\n", use_sg,
7781 scp->device->host->sg_tablesize);
52c334e9 7782 scsi_dma_unmap(scp);
51219358
MW		 7783 scp->result = HOST_BYTE(DID_ERROR);
7784 return ASC_ERROR;
7785 }
27c868c2 7786
05848b6e
MW		 7787 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) +
7788 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC);
7789 if (!asc_sg_head) {
52c334e9 7790 scsi_dma_unmap(scp);
05848b6e
MW		 7791 scp->result = HOST_BYTE(DID_SOFT_ERROR);
7792 return ASC_ERROR;
7793 }
51219358 7794
05848b6e
MW		 7795 asc_scsi_q->q1.cntl |= QC_SG_HEAD;
7796 asc_scsi_q->sg_head = asc_sg_head;
7797 asc_scsi_q->q1.data_cnt = 0;
7798 asc_scsi_q->q1.data_addr = 0;
51219358 7799 /* This is a byte value, otherwise it would need to be swapped. */
05848b6e 7800 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg;
52c334e9 7801 ASC_STATS_ADD(scp->device->host, xfer_elem,
05848b6e 7802 asc_sg_head->entry_cnt);
51219358
MW		 7803
7804 /*
7805 * Convert scatter-gather list into ASC_SG_HEAD list.
7806 */
52c334e9 7807 scsi_for_each_sg(scp, slp, use_sg, sgcnt) {
05848b6e 7808 asc_sg_head->sg_list[sgcnt].addr =
51219358 7809 cpu_to_le32(sg_dma_address(slp));
05848b6e 7810 asc_sg_head->sg_list[sgcnt].bytes =
51219358 7811 cpu_to_le32(sg_dma_len(slp));
52c334e9
MW		 7812 ASC_STATS_ADD(scp->device->host, xfer_sect,
7813 DIV_ROUND_UP(sg_dma_len(slp), 512));
27c868c2
MW		 7814 }
7815 }
1da177e4 7816
52c334e9
MW		 7817 ASC_STATS(scp->device->host, xfer_cnt);
7818
b352f923 7819 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q);
51219358
MW		 7820 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
7821
7822 return ASC_NOERROR;
27c868c2 7823}
1da177e4 7824
27c868c2 7825/*
51219358 7826 * Build scatter-gather list for Adv Library (Wide Board).
27c868c2 7827 *
51219358
MW		 7828 * Additional ADV_SG_BLOCK structures will need to be allocated
7829 * if the total number of scatter-gather elements exceeds
7830 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are
7831 * assumed to be physically contiguous.
27c868c2 7832 *
51219358
MW		 7833 * Return:
7834 * ADV_SUCCESS(1) - SG List successfully created
7835 * ADV_ERROR(-1) - SG List creation failed
27c868c2 7836 */
51219358 7837static int
4b47e464
HR		 7838adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp,
7839 ADV_SCSI_REQ_Q *scsiqp, struct scsi_cmnd *scp, int use_sg)
27c868c2 7840{
0ce53822 7841 adv_sgblk_t *sgblkp, *prev_sgblkp;
51219358
MW		 7842 struct scatterlist *slp;
7843 int sg_elem_cnt;
7844 ADV_SG_BLOCK *sg_block, *prev_sg_block;
0ce53822 7845 dma_addr_t sgblk_paddr;
27c868c2 7846 int i;
27c868c2 7847
52c334e9 7848 slp = scsi_sglist(scp);
51219358 7849 sg_elem_cnt = use_sg;
0ce53822 7850 prev_sgblkp = NULL;
51219358
MW		 7851 prev_sg_block = NULL;
7852 reqp->sgblkp = NULL;
1da177e4 7853
51219358
MW		 7854 for (;;) {
7855 /*
7856 * Allocate a 'adv_sgblk_t' structure from the board free
7857 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK
7858 * (15) scatter-gather elements.
7859 */
0ce53822
HR		 7860 sgblkp = dma_pool_alloc(boardp->adv_sgblk_pool, GFP_ATOMIC,
7861 &sgblk_paddr);
7862 if (!sgblkp) {
b352f923 7863 ASC_DBG(1, "no free adv_sgblk_t\n");
51219358 7864 ASC_STATS(scp->device->host, adv_build_nosg);
1da177e4 7865
51219358
MW		 7866 /*
7867 * Allocation failed. Free 'adv_sgblk_t' structures
7868 * already allocated for the request.
7869 */
7870 while ((sgblkp = reqp->sgblkp) != NULL) {
7871 /* Remove 'sgblkp' from the request list. */
7872 reqp->sgblkp = sgblkp->next_sgblkp;
0ce53822
HR		 7873 sgblkp->next_sgblkp = NULL;
7874 dma_pool_free(boardp->adv_sgblk_pool, sgblkp,
7875 sgblkp->sg_addr);
51219358
MW		 7876 }
7877 return ASC_BUSY;
7878 }
51219358 7879 /* Complete 'adv_sgblk_t' board allocation. */
0ce53822 7880 sgblkp->sg_addr = sgblk_paddr;
51219358 7881 sgblkp->next_sgblkp = NULL;
0ce53822 7882 sg_block = &sgblkp->sg_block;
27c868c2 7883
51219358
MW		 7884 /*
7885 * Check if this is the first 'adv_sgblk_t' for the
7886 * request.
7887 */
7888 if (reqp->sgblkp == NULL) {
7889 /* Request's first scatter-gather block. */
7890 reqp->sgblkp = sgblkp;
27c868c2 7891
51219358
MW		 7892 /*
7893 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical
7894 * address pointers.
7895 */
7896 scsiqp->sg_list_ptr = sg_block;
0ce53822 7897 scsiqp->sg_real_addr = cpu_to_le32(sgblk_paddr);
51219358
MW		 7898 } else {
7899 /* Request's second or later scatter-gather block. */
0ce53822 7900 prev_sgblkp->next_sgblkp = sgblkp;
51219358
MW		 7901
7902 /*
7903 * Point the previous ADV_SG_BLOCK structure to
7904 * the newly allocated ADV_SG_BLOCK structure.
7905 */
0ce53822 7906 prev_sg_block->sg_ptr = cpu_to_le32(sgblk_paddr);
27c868c2 7907 }
1da177e4 7908
51219358
MW		 7909 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) {
7910 sg_block->sg_list[i].sg_addr =
7911 cpu_to_le32(sg_dma_address(slp));
7912 sg_block->sg_list[i].sg_count =
7913 cpu_to_le32(sg_dma_len(slp));
52c334e9
MW		 7914 ASC_STATS_ADD(scp->device->host, xfer_sect,
7915 DIV_ROUND_UP(sg_dma_len(slp), 512));
27c868c2 7916
0ce53822
HR		 7917 if (--sg_elem_cnt == 0) {
7918 /*
7919 * Last ADV_SG_BLOCK and scatter-gather entry.
7920 */
51219358 7921 sg_block->sg_cnt = i + 1;
0ce53822 7922 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */
51219358
MW		 7923 return ADV_SUCCESS;
7924 }
7925 slp++;
7926 }
7927 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK;
7928 prev_sg_block = sg_block;
0ce53822 7929 prev_sgblkp = sgblkp;
27c868c2 7930 }
51219358 7931}
1da177e4 7932
51219358
MW		 7933/*
7934 * Build a request structure for the Adv Library (Wide Board).
7935 *
7936 * If an adv_req_t can not be allocated to issue the request,
7937 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR.
7938 *
9fef6ba4 7939 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the
51219358
MW		 7940 * microcode for DMA addresses or math operations are byte swapped
7941 * to little-endian order.
7942 */
7943static int
d2411495 7944adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp,
4b47e464 7945 adv_req_t **adv_reqpp)
51219358 7946{
9c17c62a 7947 u32 srb_tag = scp->request->tag;
51219358
MW		 7948 adv_req_t *reqp;
7949 ADV_SCSI_REQ_Q *scsiqp;
51219358 7950 int ret;
52c334e9 7951 int use_sg;
811ddc05 7952 dma_addr_t sense_addr;
1da177e4 7953
27c868c2 7954 /*
51219358
MW		 7955 * Allocate an adv_req_t structure from the board to execute
7956 * the command.
27c868c2 7957 */
9c17c62a
HR		 7958 reqp = &boardp->adv_reqp[srb_tag];
7959 if (reqp->cmndp && reqp->cmndp != scp ) {
b352f923 7960 ASC_DBG(1, "no free adv_req_t\n");
51219358
MW		 7961 ASC_STATS(scp->device->host, adv_build_noreq);
7962 return ASC_BUSY;
27c868c2 7963 }
1da177e4 7964
4b47e464
HR		 7965 reqp->req_addr = boardp->adv_reqp_addr + (srb_tag * sizeof(adv_req_t));
7966
7967 scsiqp = &reqp->scsi_req_q;
27c868c2
MW		 7968
7969 /*
51219358 7970 * Initialize the structure.
27c868c2 7971 */
51219358 7972 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0;
27c868c2
MW		 7973
7974 /*
9c17c62a 7975 * Set the srb_tag to the command tag.
27c868c2 7976 */
9c17c62a 7977 scsiqp->srb_tag = srb_tag;
27c868c2
MW		 7978
7979 /*
4b47e464 7980 * Set 'host_scribble' to point to the adv_req_t structure.
27c868c2 7981 */
51219358 7982 reqp->cmndp = scp;
9c17c62a 7983 scp->host_scribble = (void *)reqp;
27c868c2
MW		 7984
7985 /*
51219358 7986 * Build the ADV_SCSI_REQ_Q request.
27c868c2 7987 */
51219358
MW		 7988
7989 /* Set CDB length and copy it to the request structure. */
7990 scsiqp->cdb_len = scp->cmd_len;
7991 /* Copy first 12 CDB bytes to cdb[]. */
811ddc05 7992 memcpy(scsiqp->cdb, scp->cmnd, scp->cmd_len < 12 ? scp->cmd_len : 12);
51219358 7993 /* Copy last 4 CDB bytes, if present, to cdb16[]. */
811ddc05
HR		 7994 if (scp->cmd_len > 12) {
7995 int cdb16_len = scp->cmd_len - 12;
7996
7997 memcpy(scsiqp->cdb16, &scp->cmnd[12], cdb16_len);
27c868c2 7998 }
1da177e4 7999
51219358
MW		 8000 scsiqp->target_id = scp->device->id;
8001 scsiqp->target_lun = scp->device->lun;
8002
811ddc05
HR		 8003 sense_addr = dma_map_single(boardp->dev, scp->sense_buffer,
8004 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE);
8005 scsiqp->sense_addr = cpu_to_le32(sense_addr);
8006 scsiqp->sense_len = cpu_to_le32(SCSI_SENSE_BUFFERSIZE);
27c868c2 8007
52c334e9 8008 /* Build ADV_SCSI_REQ_Q */
51219358 8009
52c334e9
MW		 8010 use_sg = scsi_dma_map(scp);
8011 if (use_sg == 0) {
8012 /* Zero-length transfer */
51219358 8013 reqp->sgblkp = NULL;
52c334e9 8014 scsiqp->data_cnt = 0;
52c334e9
MW		 8015
8016 scsiqp->data_addr = 0;
51219358
MW		 8017 scsiqp->sg_list_ptr = NULL;
8018 scsiqp->sg_real_addr = 0;
51219358 8019 } else {
51219358 8020 if (use_sg > ADV_MAX_SG_LIST) {
9d0e96eb
MW		 8021 scmd_printk(KERN_ERR, scp, "use_sg %d > "
8022 "ADV_MAX_SG_LIST %d\n", use_sg,
51219358 8023 scp->device->host->sg_tablesize);
52c334e9 8024 scsi_dma_unmap(scp);
51219358 8025 scp->result = HOST_BYTE(DID_ERROR);
9c17c62a
HR		 8026 reqp->cmndp = NULL;
8027 scp->host_scribble = NULL;
51219358
MW		 8028
8029 return ASC_ERROR;
8030 }
8031
52c334e9
MW		 8032 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp));
8033
4b47e464 8034 ret = adv_get_sglist(boardp, reqp, scsiqp, scp, use_sg);
51219358 8035 if (ret != ADV_SUCCESS) {
9c17c62a
HR		 8036 scsi_dma_unmap(scp);
8037 scp->result = HOST_BYTE(DID_ERROR);
8038 reqp->cmndp = NULL;
8039 scp->host_scribble = NULL;
51219358
MW		 8040
8041 return ret;
8042 }
8043
52c334e9 8044 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg);
27c868c2 8045 }
1da177e4 8046
52c334e9
MW		 8047 ASC_STATS(scp->device->host, xfer_cnt);
8048
51219358
MW		 8049 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp);
8050 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len);
27c868c2 8051
4b47e464 8052 *adv_reqpp = reqp;
27c868c2 8053
51219358
MW		 8054 return ASC_NOERROR;
8055}
8056
8057static int AscSgListToQueue(int sg_list)
8058{
8059 int n_sg_list_qs;
8060
8061 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q);
8062 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0)
8063 n_sg_list_qs++;
8064 return n_sg_list_qs + 1;
8065}
8066
8067static uint
8068AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs)
8069{
8070 uint cur_used_qs;
8071 uint cur_free_qs;
8072 ASC_SCSI_BIT_ID_TYPE target_id;
8073 uchar tid_no;
8074
8075 target_id = ASC_TIX_TO_TARGET_ID(target_ix);
8076 tid_no = ASC_TIX_TO_TID(target_ix);
8077 if ((asc_dvc->unit_not_ready & target_id) ||
8078 (asc_dvc->queue_full_or_busy & target_id)) {
8079 return 0;
8080 }
8081 if (n_qs == 1) {
8082 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8083 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q;
8084 } else {
8085 cur_used_qs = (uint) asc_dvc->cur_total_qng +
8086 (uint) ASC_MIN_FREE_Q;
8087 }
8088 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) {
8089 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs;
8090 if (asc_dvc->cur_dvc_qng[tid_no] >=
8091 asc_dvc->max_dvc_qng[tid_no]) {
8092 return 0;
8093 }
8094 return cur_free_qs;
8095 }
8096 if (n_qs > 1) {
8097 if ((n_qs > asc_dvc->last_q_shortage)
8098 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) {
8099 asc_dvc->last_q_shortage = n_qs;
8100 }
8101 }
8102 return 0;
8103}
8104
8105static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head)
8106{
8107 ushort q_addr;
8108 uchar next_qp;
8109 uchar q_status;
8110
8111 q_addr = ASC_QNO_TO_QADDR(free_q_head);
8112 q_status = (uchar)AscReadLramByte(iop_base,
8113 (ushort)(q_addr +
8114 ASC_SCSIQ_B_STATUS));
8115 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD));
8116 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END))
8117 return next_qp;
8118 return ASC_QLINK_END;
8119}
8120
8121static uchar
8122AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q)
8123{
8124 uchar i;
27c868c2 8125
51219358
MW		 8126 for (i = 0; i < n_free_q; i++) {
8127 free_q_head = AscAllocFreeQueue(iop_base, free_q_head);
8128 if (free_q_head == ASC_QLINK_END)
8129 break;
8130 }
8131 return free_q_head;
8132}
27c868c2 8133
51219358
MW		 8134/*
8135 * void
8136 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8137 *
8138 * Calling/Exit State:
8139 * none
8140 *
8141 * Description:
8142 * Output an ASC_SCSI_Q structure to the chip
8143 */
8144static void
8145DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words)
8146{
8147 int i;
8148
8149 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words);
8150 AscSetChipLramAddr(iop_base, s_addr);
8151 for (i = 0; i < 2 * words; i += 2) {
8152 if (i == 4 || i == 20) {
8153 continue;
8154 }
8155 outpw(iop_base + IOP_RAM_DATA,
8156 ((ushort)outbuf[i + 1] << 8) | outbuf[i]);
27c868c2 8157 }
51219358 8158}
1da177e4 8159
51219358
MW		 8160static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8161{
8162 ushort q_addr;
8163 uchar tid_no;
8164 uchar sdtr_data;
8165 uchar syn_period_ix;
8166 uchar syn_offset;
8167 PortAddr iop_base;
8168
8169 iop_base = asc_dvc->iop_base;
8170 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) &&
8171 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) {
8172 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix);
8173 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8174 syn_period_ix =
8175 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1);
8176 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET;
8177 AscMsgOutSDTR(asc_dvc,
8178 asc_dvc->sdtr_period_tbl[syn_period_ix],
8179 syn_offset);
8180 scsiq->q1.cntl |= QC_MSG_OUT;
8181 }
8182 q_addr = ASC_QNO_TO_QADDR(q_no);
8183 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) {
68d81f40 8184 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
27c868c2 8185 }
51219358
MW		 8186 scsiq->q1.status = QS_FREE;
8187 AscMemWordCopyPtrToLram(iop_base,
8188 q_addr + ASC_SCSIQ_CDB_BEG,
8189 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1);
8190
8191 DvcPutScsiQ(iop_base,
8192 q_addr + ASC_SCSIQ_CPY_BEG,
8193 (uchar *)&scsiq->q1.cntl,
8194 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1);
8195 AscWriteLramWord(iop_base,
8196 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS),
8197 (ushort)(((ushort)scsiq->q1.
8198 q_no << 8) | (ushort)QS_READY));
8199 return 1;
8200}
8201
8202static int
8203AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no)
8204{
8205 int sta;
8206 int i;
8207 ASC_SG_HEAD *sg_head;
8208 ASC_SG_LIST_Q scsi_sg_q;
95cfab6c
HR		 8209 __le32 saved_data_addr;
8210 __le32 saved_data_cnt;
51219358
MW		 8211 PortAddr iop_base;
8212 ushort sg_list_dwords;
8213 ushort sg_index;
8214 ushort sg_entry_cnt;
8215 ushort q_addr;
8216 uchar next_qp;
1da177e4 8217
51219358
MW		 8218 iop_base = asc_dvc->iop_base;
8219 sg_head = scsiq->sg_head;
8220 saved_data_addr = scsiq->q1.data_addr;
8221 saved_data_cnt = scsiq->q1.data_cnt;
37f64608
HR		 8222 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr);
8223 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes);
51219358 8224#if CC_VERY_LONG_SG_LIST
27c868c2 8225 /*
51219358
MW		 8226 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST
8227 * then not all SG elements will fit in the allocated queues.
8228 * The rest of the SG elements will be copied when the RISC
8229 * completes the SG elements that fit and halts.
27c868c2 8230 */
51219358
MW		 8231 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8232 /*
8233 * Set sg_entry_cnt to be the number of SG elements that
8234 * will fit in the allocated SG queues. It is minus 1, because
8235 * the first SG element is handled above. ASC_MAX_SG_LIST is
8236 * already inflated by 1 to account for this. For example it
8237 * may be 50 which is 1 + 7 queues * 7 SG elements.
8238 */
8239 sg_entry_cnt = ASC_MAX_SG_LIST - 1;
27c868c2 8240
51219358
MW		 8241 /*
8242 * Keep track of remaining number of SG elements that will
8243 * need to be handled from a_isr.c.
8244 */
8245 scsiq->remain_sg_entry_cnt =
8246 sg_head->entry_cnt - ASC_MAX_SG_LIST;
8247 } else {
8248#endif /* CC_VERY_LONG_SG_LIST */
8249 /*
8250 * Set sg_entry_cnt to be the number of SG elements that
8251 * will fit in the allocated SG queues. It is minus 1, because
8252 * the first SG element is handled above.
8253 */
8254 sg_entry_cnt = sg_head->entry_cnt - 1;
8255#if CC_VERY_LONG_SG_LIST
8256 }
8257#endif /* CC_VERY_LONG_SG_LIST */
8258 if (sg_entry_cnt != 0) {
8259 scsiq->q1.cntl |= QC_SG_HEAD;
8260 q_addr = ASC_QNO_TO_QADDR(q_no);
8261 sg_index = 1;
8262 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt;
8263 scsi_sg_q.sg_head_qp = q_no;
8264 scsi_sg_q.cntl = QCSG_SG_XFER_LIST;
8265 for (i = 0; i < sg_head->queue_cnt; i++) {
8266 scsi_sg_q.seq_no = i + 1;
8267 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) {
8268 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2);
8269 sg_entry_cnt -= ASC_SG_LIST_PER_Q;
8270 if (i == 0) {
8271 scsi_sg_q.sg_list_cnt =
8272 ASC_SG_LIST_PER_Q;
8273 scsi_sg_q.sg_cur_list_cnt =
8274 ASC_SG_LIST_PER_Q;
8275 } else {
8276 scsi_sg_q.sg_list_cnt =
8277 ASC_SG_LIST_PER_Q - 1;
8278 scsi_sg_q.sg_cur_list_cnt =
8279 ASC_SG_LIST_PER_Q - 1;
8280 }
8281 } else {
8282#if CC_VERY_LONG_SG_LIST
8283 /*
8284 * This is the last SG queue in the list of
8285 * allocated SG queues. If there are more
8286 * SG elements than will fit in the allocated
8287 * queues, then set the QCSG_SG_XFER_MORE flag.
8288 */
8289 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) {
8290 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE;
8291 } else {
8292#endif /* CC_VERY_LONG_SG_LIST */
8293 scsi_sg_q.cntl |= QCSG_SG_XFER_END;
8294#if CC_VERY_LONG_SG_LIST
8295 }
8296#endif /* CC_VERY_LONG_SG_LIST */
8297 sg_list_dwords = sg_entry_cnt << 1;
8298 if (i == 0) {
8299 scsi_sg_q.sg_list_cnt = sg_entry_cnt;
8300 scsi_sg_q.sg_cur_list_cnt =
8301 sg_entry_cnt;
8302 } else {
8303 scsi_sg_q.sg_list_cnt =
8304 sg_entry_cnt - 1;
8305 scsi_sg_q.sg_cur_list_cnt =
8306 sg_entry_cnt - 1;
8307 }
8308 sg_entry_cnt = 0;
8309 }
8310 next_qp = AscReadLramByte(iop_base,
8311 (ushort)(q_addr +
8312 ASC_SCSIQ_B_FWD));
8313 scsi_sg_q.q_no = next_qp;
8314 q_addr = ASC_QNO_TO_QADDR(next_qp);
8315 AscMemWordCopyPtrToLram(iop_base,
8316 q_addr + ASC_SCSIQ_SGHD_CPY_BEG,
8317 (uchar *)&scsi_sg_q,
8318 sizeof(ASC_SG_LIST_Q) >> 1);
8319 AscMemDWordCopyPtrToLram(iop_base,
8320 q_addr + ASC_SGQ_LIST_BEG,
8321 (uchar *)&sg_head->
8322 sg_list[sg_index],
8323 sg_list_dwords);
8324 sg_index += ASC_SG_LIST_PER_Q;
8325 scsiq->next_sg_index = sg_index;
27c868c2 8326 }
51219358
MW		 8327 } else {
8328 scsiq->q1.cntl &= ~QC_SG_HEAD;
27c868c2 8329 }
51219358
MW		 8330 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no);
8331 scsiq->q1.data_addr = saved_data_addr;
8332 scsiq->q1.data_cnt = saved_data_cnt;
8333 return (sta);
8334}
27c868c2 8335
51219358
MW		 8336static int
8337AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required)
8338{
8339 PortAddr iop_base;
8340 uchar free_q_head;
8341 uchar next_qp;
8342 uchar tid_no;
8343 uchar target_ix;
8344 int sta;
27c868c2 8345
51219358
MW		 8346 iop_base = asc_dvc->iop_base;
8347 target_ix = scsiq->q2.target_ix;
8348 tid_no = ASC_TIX_TO_TID(target_ix);
8349 sta = 0;
8350 free_q_head = (uchar)AscGetVarFreeQHead(iop_base);
8351 if (n_q_required > 1) {
8352 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head,
8353 (uchar)n_q_required);
8354 if (next_qp != ASC_QLINK_END) {
8355 asc_dvc->last_q_shortage = 0;
8356 scsiq->sg_head->queue_cnt = n_q_required - 1;
8357 scsiq->q1.q_no = free_q_head;
8358 sta = AscPutReadySgListQueue(asc_dvc, scsiq,
8359 free_q_head);
8360 }
8361 } else if (n_q_required == 1) {
8362 next_qp = AscAllocFreeQueue(iop_base, free_q_head);
8363 if (next_qp != ASC_QLINK_END) {
8364 scsiq->q1.q_no = free_q_head;
8365 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head);
27c868c2
MW		 8366 }
8367 }
51219358
MW		 8368 if (sta == 1) {
8369 AscPutVarFreeQHead(iop_base, next_qp);
8370 asc_dvc->cur_total_qng += n_q_required;
8371 asc_dvc->cur_dvc_qng[tid_no]++;
27c868c2 8372 }
51219358
MW		 8373 return sta;
8374}
27c868c2 8375
51219358
MW		 8376#define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16
8377static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = {
8378 INQUIRY,
8379 REQUEST_SENSE,
8380 READ_CAPACITY,
8381 READ_TOC,
8382 MODE_SELECT,
8383 MODE_SENSE,
8384 MODE_SELECT_10,
8385 MODE_SENSE_10,
8386 0xFF,
8387 0xFF,
8388 0xFF,
8389 0xFF,
8390 0xFF,
8391 0xFF,
8392 0xFF,
8393 0xFF
8394};
27c868c2 8395
51219358
MW		 8396static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq)
8397{
8398 PortAddr iop_base;
8399 int sta;
8400 int n_q_required;
ae26759e 8401 bool disable_syn_offset_one_fix;
51219358 8402 int i;
95cfab6c 8403 u32 addr;
51219358
MW		 8404 ushort sg_entry_cnt = 0;
8405 ushort sg_entry_cnt_minus_one = 0;
8406 uchar target_ix;
8407 uchar tid_no;
8408 uchar sdtr_data;
8409 uchar extra_bytes;
8410 uchar scsi_cmd;
8411 uchar disable_cmd;
8412 ASC_SG_HEAD *sg_head;
95cfab6c 8413 unsigned long data_cnt;
27c868c2 8414
51219358
MW		 8415 iop_base = asc_dvc->iop_base;
8416 sg_head = scsiq->sg_head;
8417 if (asc_dvc->err_code != 0)
f1138a84 8418 return ASC_ERROR;
51219358
MW		 8419 scsiq->q1.q_no = 0;
8420 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) {
8421 scsiq->q1.extra_bytes = 0;
27c868c2 8422 }
51219358
MW		 8423 sta = 0;
8424 target_ix = scsiq->q2.target_ix;
8425 tid_no = ASC_TIX_TO_TID(target_ix);
8426 n_q_required = 1;
8427 if (scsiq->cdbptr[0] == REQUEST_SENSE) {
8428 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) {
8429 asc_dvc->sdtr_done &= ~scsiq->q1.target_id;
8430 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no);
8431 AscMsgOutSDTR(asc_dvc,
8432 asc_dvc->
8433 sdtr_period_tbl[(sdtr_data >> 4) &
8434 (uchar)(asc_dvc->
8435 max_sdtr_index -
8436 1)],
8437 (uchar)(sdtr_data & (uchar)
8438 ASC_SYN_MAX_OFFSET));
8439 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT);
8440 }
8441 }
8442 if (asc_dvc->in_critical_cnt != 0) {
8443 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY);
f1138a84 8444 return ASC_ERROR;
51219358
MW		 8445 }
8446 asc_dvc->in_critical_cnt++;
8447 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8448 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) {
8449 asc_dvc->in_critical_cnt--;
f1138a84 8450 return ASC_ERROR;
51219358
MW		 8451 }
8452#if !CC_VERY_LONG_SG_LIST
8453 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8454 asc_dvc->in_critical_cnt--;
f1138a84 8455 return ASC_ERROR;
51219358
MW		 8456 }
8457#endif /* !CC_VERY_LONG_SG_LIST */
8458 if (sg_entry_cnt == 1) {
37f64608
HR		 8459 scsiq->q1.data_addr = cpu_to_le32(sg_head->sg_list[0].addr);
8460 scsiq->q1.data_cnt = cpu_to_le32(sg_head->sg_list[0].bytes);
51219358
MW		 8461 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE);
8462 }
8463 sg_entry_cnt_minus_one = sg_entry_cnt - 1;
8464 }
8465 scsi_cmd = scsiq->cdbptr[0];
ae26759e 8466 disable_syn_offset_one_fix = false;
51219358
MW		 8467 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) &&
8468 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) {
8469 if (scsiq->q1.cntl & QC_SG_HEAD) {
8470 data_cnt = 0;
8471 for (i = 0; i < sg_entry_cnt; i++) {
95cfab6c
HR		 8472 data_cnt += le32_to_cpu(sg_head->sg_list[i].
8473 bytes);
51219358
MW		 8474 }
8475 } else {
8476 data_cnt = le32_to_cpu(scsiq->q1.data_cnt);
8477 }
8478 if (data_cnt != 0UL) {
8479 if (data_cnt < 512UL) {
ae26759e 8480 disable_syn_offset_one_fix = true;
51219358
MW		 8481 } else {
8482 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST;
8483 i++) {
8484 disable_cmd =
8485 _syn_offset_one_disable_cmd[i];
8486 if (disable_cmd == 0xFF) {
8487 break;
8488 }
8489 if (scsi_cmd == disable_cmd) {
8490 disable_syn_offset_one_fix =
ae26759e 8491 true;
51219358
MW		 8492 break;
8493 }
8494 }
8495 }
8496 }
8497 }
8498 if (disable_syn_offset_one_fix) {
68d81f40 8499 scsiq->q2.tag_code &= ~SIMPLE_QUEUE_TAG;
51219358
MW		 8500 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX |
8501 ASC_TAG_FLAG_DISABLE_DISCONNECT);
8502 } else {
8503 scsiq->q2.tag_code &= 0x27;
8504 }
8505 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) {
8506 if (asc_dvc->bug_fix_cntl) {
8507 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8508 if ((scsi_cmd == READ_6) ||
8509 (scsi_cmd == READ_10)) {
95cfab6c 8510 addr = le32_to_cpu(sg_head->
51219358
MW		 8511 sg_list
8512 [sg_entry_cnt_minus_one].
8513 addr) +
95cfab6c 8514 le32_to_cpu(sg_head->
51219358
MW		 8515 sg_list
8516 [sg_entry_cnt_minus_one].
8517 bytes);
8518 extra_bytes =
8519 (uchar)((ushort)addr & 0x0003);
8520 if ((extra_bytes != 0)
8521 &&
8522 ((scsiq->q2.
8523 tag_code &
8524 ASC_TAG_FLAG_EXTRA_BYTES)
8525 == 0)) {
8526 scsiq->q2.tag_code |=
8527 ASC_TAG_FLAG_EXTRA_BYTES;
8528 scsiq->q1.extra_bytes =
8529 extra_bytes;
8530 data_cnt =
8531 le32_to_cpu(sg_head->
8532 sg_list
8533 [sg_entry_cnt_minus_one].
8534 bytes);
95cfab6c 8535 data_cnt -= extra_bytes;
51219358
MW		 8536 sg_head->
8537 sg_list
8538 [sg_entry_cnt_minus_one].
8539 bytes =
8540 cpu_to_le32(data_cnt);
8541 }
8542 }
8543 }
8544 }
8545 sg_head->entry_to_copy = sg_head->entry_cnt;
8546#if CC_VERY_LONG_SG_LIST
27c868c2 8547 /*
51219358
MW		 8548 * Set the sg_entry_cnt to the maximum possible. The rest of
8549 * the SG elements will be copied when the RISC completes the
8550 * SG elements that fit and halts.
27c868c2 8551 */
51219358
MW		 8552 if (sg_entry_cnt > ASC_MAX_SG_LIST) {
8553 sg_entry_cnt = ASC_MAX_SG_LIST;
8554 }
8555#endif /* CC_VERY_LONG_SG_LIST */
8556 n_q_required = AscSgListToQueue(sg_entry_cnt);
8557 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >=
8558 (uint) n_q_required)
8559 || ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8560 if ((sta =
8561 AscSendScsiQueue(asc_dvc, scsiq,
8562 n_q_required)) == 1) {
8563 asc_dvc->in_critical_cnt--;
8564 return (sta);
27c868c2 8565 }
51219358
MW		 8566 }
8567 } else {
8568 if (asc_dvc->bug_fix_cntl) {
8569 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) {
8570 if ((scsi_cmd == READ_6) ||
8571 (scsi_cmd == READ_10)) {
8572 addr =
8573 le32_to_cpu(scsiq->q1.data_addr) +
8574 le32_to_cpu(scsiq->q1.data_cnt);
8575 extra_bytes =
8576 (uchar)((ushort)addr & 0x0003);
8577 if ((extra_bytes != 0)
8578 &&
8579 ((scsiq->q2.
8580 tag_code &
8581 ASC_TAG_FLAG_EXTRA_BYTES)
8582 == 0)) {
8583 data_cnt =
8584 le32_to_cpu(scsiq->q1.
8585 data_cnt);
8586 if (((ushort)data_cnt & 0x01FF)
8587 == 0) {
8588 scsiq->q2.tag_code |=
8589 ASC_TAG_FLAG_EXTRA_BYTES;
95cfab6c 8590 data_cnt -= extra_bytes;
51219358
MW		 8591 scsiq->q1.data_cnt =
8592 cpu_to_le32
8593 (data_cnt);
8594 scsiq->q1.extra_bytes =
8595 extra_bytes;
8596 }
8597 }
8598 }
8599 }
8600 }
8601 n_q_required = 1;
8602 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) ||
8603 ((scsiq->q1.cntl & QC_URGENT) != 0)) {
8604 if ((sta = AscSendScsiQueue(asc_dvc, scsiq,
8605 n_q_required)) == 1) {
8606 asc_dvc->in_critical_cnt--;
8607 return (sta);
27c868c2
MW		 8608 }
8609 }
8610 }
51219358
MW		 8611 asc_dvc->in_critical_cnt--;
8612 return (sta);
1da177e4
LT		 8613}
8614
8615/*
51219358 8616 * AdvExeScsiQueue() - Send a request to the RISC microcode program.
1da177e4 8617 *
51219358
MW		 8618 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q,
8619 * add the carrier to the ICQ (Initiator Command Queue), and tickle the
8620 * RISC to notify it a new command is ready to be executed.
8621 *
8622 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be
8623 * set to SCSI_MAX_RETRY.
8624 *
9fef6ba4 8625 * Multi-byte fields in the ADV_SCSI_REQ_Q that are used by the microcode
51219358
MW		 8626 * for DMA addresses or math operations are byte swapped to little-endian
8627 * order.
8628 *
8629 * Return:
8630 * ADV_SUCCESS(1) - The request was successfully queued.
8631 * ADV_BUSY(0) - Resource unavailable; Retry again after pending
8632 * request completes.
8633 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure
8634 * host IC error.
8635 */
4b47e464 8636static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, adv_req_t *reqp)
51219358
MW		 8637{
8638 AdvPortAddr iop_base;
51219358 8639 ADV_CARR_T *new_carrp;
4b47e464 8640 ADV_SCSI_REQ_Q *scsiq = &reqp->scsi_req_q;
1da177e4 8641
27c868c2 8642 /*
51219358 8643 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID.
27c868c2 8644 */
51219358
MW		 8645 if (scsiq->target_id > ADV_MAX_TID) {
8646 scsiq->host_status = QHSTA_M_INVALID_DEVICE;
8647 scsiq->done_status = QD_WITH_ERROR;
27c868c2
MW		 8648 return ADV_ERROR;
8649 }
1da177e4 8650
51219358 8651 iop_base = asc_dvc->iop_base;
1da177e4 8652
27c868c2 8653 /*
51219358
MW		 8654 * Allocate a carrier ensuring at least one carrier always
8655 * remains on the freelist and initialize fields.
27c868c2 8656 */
98b96a7d
HR		 8657 new_carrp = adv_get_next_carrier(asc_dvc);
8658 if (!new_carrp) {
8659 ASC_DBG(1, "No free carriers\n");
51219358 8660 return ADV_BUSY;
27c868c2 8661 }
1da177e4 8662
98b96a7d 8663 asc_dvc->carr_pending_cnt++;
27c868c2
MW		 8664
8665 /*
51219358 8666 * Clear the ADV_SCSI_REQ_Q done flag.
27c868c2 8667 */
51219358 8668 scsiq->a_flag &= ~ADV_SCSIQ_DONE;
27c868c2 8669
51219358 8670 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */
4b47e464
HR		 8671 scsiq->scsiq_ptr = cpu_to_le32(scsiq->srb_tag);
8672 scsiq->scsiq_rptr = cpu_to_le32(reqp->req_addr);
51219358 8673
98b96a7d 8674 scsiq->carr_va = asc_dvc->icq_sp->carr_va;
51219358 8675 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa;
1da177e4 8676
27c868c2 8677 /*
51219358
MW		 8678 * Use the current stopper to send the ADV_SCSI_REQ_Q command to
8679 * the microcode. The newly allocated stopper will become the new
8680 * stopper.
27c868c2 8681 */
4b47e464 8682 asc_dvc->icq_sp->areq_vpa = scsiq->scsiq_rptr;
1da177e4 8683
27c868c2 8684 /*
51219358
MW		 8685 * Set the 'next_vpa' pointer for the old stopper to be the
8686 * physical address of the new stopper. The RISC can only
8687 * follow physical addresses.
27c868c2 8688 */
51219358 8689 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa;
27c868c2
MW		 8690
8691 /*
51219358 8692 * Set the host adapter stopper pointer to point to the new carrier.
27c868c2 8693 */
51219358
MW		 8694 asc_dvc->icq_sp = new_carrp;
8695
8696 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 ||
8697 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
8698 /*
8699 * Tickle the RISC to tell it to read its Command Queue Head pointer.
8700 */
8701 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A);
8702 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
8703 /*
8704 * Clear the tickle value. In the ASC-3550 the RISC flag
8705 * command 'clr_tickle_a' does not work unless the host
8706 * value is cleared.
8707 */
8708 AdvWriteByteRegister(iop_base, IOPB_TICKLE,
8709 ADV_TICKLE_NOP);
8710 }
8711 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
8712 /*
8713 * Notify the RISC a carrier is ready by writing the physical
8714 * address of the new carrier stopper to the COMMA register.
8715 */
8716 AdvWriteDWordRegister(iop_base, IOPDW_COMMA,
8717 le32_to_cpu(new_carrp->carr_pa));
27c868c2 8718 }
1da177e4 8719
51219358
MW		 8720 return ADV_SUCCESS;
8721}
8722
8723/*
8724 * Execute a single 'Scsi_Cmnd'.
51219358
MW		 8725 */
8726static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp)
8727{
41d2493d 8728 int ret, err_code;
d2411495 8729 struct asc_board *boardp = shost_priv(scp->device->host);
51219358 8730
b352f923 8731 ASC_DBG(1, "scp 0x%p\n", scp);
27c868c2 8732
51219358 8733 if (ASC_NARROW_BOARD(boardp)) {
41d2493d 8734 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var;
05848b6e 8735 struct asc_scsi_q asc_scsi_q;
27c868c2 8736
41d2493d 8737 /* asc_build_req() can not return ASC_BUSY. */
05848b6e
MW		 8738 ret = asc_build_req(boardp, scp, &asc_scsi_q);
8739 if (ret == ASC_ERROR) {
51219358
MW		 8740 ASC_STATS(scp->device->host, build_error);
8741 return ASC_ERROR;
8742 }
1da177e4 8743
41d2493d 8744 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q);
05848b6e 8745 kfree(asc_scsi_q.sg_head);
41d2493d 8746 err_code = asc_dvc->err_code;
51219358 8747 } else {
41d2493d 8748 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var;
4b47e464 8749 adv_req_t *adv_reqp;
27c868c2 8750
4b47e464 8751 switch (adv_build_req(boardp, scp, &adv_reqp)) {
51219358 8752 case ASC_NOERROR:
b352f923 8753 ASC_DBG(3, "adv_build_req ASC_NOERROR\n");
51219358
MW		 8754 break;
8755 case ASC_BUSY:
b352f923 8756 ASC_DBG(1, "adv_build_req ASC_BUSY\n");
51219358
MW		 8757 /*
8758 * The asc_stats fields 'adv_build_noreq' and
8759 * 'adv_build_nosg' count wide board busy conditions.
8760 * They are updated in adv_build_req and
8761 * adv_get_sglist, respectively.
8762 */
8763 return ASC_BUSY;
8764 case ASC_ERROR:
8765 default:
b352f923 8766 ASC_DBG(1, "adv_build_req ASC_ERROR\n");
51219358
MW		 8767 ASC_STATS(scp->device->host, build_error);
8768 return ASC_ERROR;
8769 }
8770
4b47e464 8771 ret = AdvExeScsiQueue(adv_dvc, adv_reqp);
41d2493d
MW		 8772 err_code = adv_dvc->err_code;
8773 }
8774
8775 switch (ret) {
8776 case ASC_NOERROR:
8777 ASC_STATS(scp->device->host, exe_noerror);
8778 /*
8779 * Increment monotonically increasing per device
8780 * successful request counter. Wrapping doesn't matter.
8781 */
8782 boardp->reqcnt[scp->device->id]++;
b352f923 8783 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n");
41d2493d
MW		 8784 break;
8785 case ASC_BUSY:
4b47e464 8786 ASC_DBG(1, "ExeScsiQueue() ASC_BUSY\n");
41d2493d
MW		 8787 ASC_STATS(scp->device->host, exe_busy);
8788 break;
8789 case ASC_ERROR:
9d0e96eb
MW		 8790 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, "
8791 "err_code 0x%x\n", err_code);
41d2493d
MW		 8792 ASC_STATS(scp->device->host, exe_error);
8793 scp->result = HOST_BYTE(DID_ERROR);
8794 break;
8795 default:
9d0e96eb
MW		 8796 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, "
8797 "err_code 0x%x\n", err_code);
41d2493d
MW		 8798 ASC_STATS(scp->device->host, exe_unknown);
8799 scp->result = HOST_BYTE(DID_ERROR);
8800 break;
27c868c2 8801 }
1da177e4 8802
b352f923 8803 ASC_DBG(1, "end\n");
51219358
MW		 8804 return ret;
8805}
27c868c2 8806
51219358
MW		 8807/*
8808 * advansys_queuecommand() - interrupt-driven I/O entrypoint.
8809 *
8810 * This function always returns 0. Command return status is saved
8811 * in the 'scp' result field.
8812 */
8813static int
f281233d 8814advansys_queuecommand_lck(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *))
51219358
MW		 8815{
8816 struct Scsi_Host *shost = scp->device->host;
51219358 8817 int asc_res, result = 0;
27c868c2 8818
51219358
MW		 8819 ASC_STATS(shost, queuecommand);
8820 scp->scsi_done = done;
27c868c2 8821
51219358 8822 asc_res = asc_execute_scsi_cmnd(scp);
51219358
MW		 8823
8824 switch (asc_res) {
8825 case ASC_NOERROR:
8826 break;
8827 case ASC_BUSY:
8828 result = SCSI_MLQUEUE_HOST_BUSY;
8829 break;
8830 case ASC_ERROR:
8831 default:
8832 asc_scsi_done(scp);
8833 break;
8834 }
8835
8836 return result;
8837}
8838
f281233d
JG		 8839static DEF_SCSI_QCMD(advansys_queuecommand)
8840
6f039790 8841static ushort AscGetEisaChipCfg(PortAddr iop_base)
51219358
MW		 8842{
8843 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8844 (PortAddr) (ASC_EISA_CFG_IOP_MASK);
8845 return inpw(eisa_cfg_iop);
8846}
8847
8848/*
8849 * Return the BIOS address of the adapter at the specified
8850 * I/O port and with the specified bus type.
8851 */
6f039790
GKH		 8852static unsigned short AscGetChipBiosAddress(PortAddr iop_base,
8853 unsigned short bus_type)
51219358
MW		 8854{
8855 unsigned short cfg_lsw;
8856 unsigned short bios_addr;
27c868c2
MW		 8857
8858 /*
51219358
MW		 8859 * The PCI BIOS is re-located by the motherboard BIOS. Because
8860 * of this the driver can not determine where a PCI BIOS is
8861 * loaded and executes.
27c868c2 8862 */
51219358
MW		 8863 if (bus_type & ASC_IS_PCI)
8864 return 0;
27c868c2 8865
51219358
MW		 8866 if ((bus_type & ASC_IS_EISA) != 0) {
8867 cfg_lsw = AscGetEisaChipCfg(iop_base);
8868 cfg_lsw &= 0x000F;
8869 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE;
8870 return bios_addr;
8871 }
27c868c2 8872
51219358 8873 cfg_lsw = AscGetChipCfgLsw(iop_base);
27c868c2
MW		 8874
8875 /*
51219358 8876 * ISA PnP uses the top bit as the 32K BIOS flag
27c868c2 8877 */
51219358
MW		 8878 if (bus_type == ASC_IS_ISAPNP)
8879 cfg_lsw &= 0x7FFF;
8880 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE;
8881 return bios_addr;
8882}
8883
6f039790 8884static uchar AscSetChipScsiID(PortAddr iop_base, uchar new_host_id)
51219358
MW		 8885{
8886 ushort cfg_lsw;
8887
8888 if (AscGetChipScsiID(iop_base) == new_host_id) {
8889 return (new_host_id);
27c868c2 8890 }
51219358
MW		 8891 cfg_lsw = AscGetChipCfgLsw(iop_base);
8892 cfg_lsw &= 0xF8FF;
8893 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8);
8894 AscSetChipCfgLsw(iop_base, cfg_lsw);
8895 return (AscGetChipScsiID(iop_base));
8896}
27c868c2 8897
6f039790 8898static unsigned char AscGetChipScsiCtrl(PortAddr iop_base)
51219358
MW		 8899{
8900 unsigned char sc;
27c868c2 8901
51219358
MW		 8902 AscSetBank(iop_base, 1);
8903 sc = inp(iop_base + IOP_REG_SC);
8904 AscSetBank(iop_base, 0);
8905 return sc;
8906}
27c868c2 8907
6f039790
GKH		 8908static unsigned char AscGetChipVersion(PortAddr iop_base,
8909 unsigned short bus_type)
51219358
MW		 8910{
8911 if (bus_type & ASC_IS_EISA) {
8912 PortAddr eisa_iop;
8913 unsigned char revision;
8914 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) |
8915 (PortAddr) ASC_EISA_REV_IOP_MASK;
8916 revision = inp(eisa_iop);
8917 return ASC_CHIP_MIN_VER_EISA - 1 + revision;
27c868c2 8918 }
51219358
MW		 8919 return AscGetChipVerNo(iop_base);
8920}
27c868c2 8921
51219358 8922#ifdef CONFIG_ISA
6f039790 8923static void AscEnableIsaDma(uchar dma_channel)
51219358
MW		 8924{
8925 if (dma_channel < 4) {
8926 outp(0x000B, (ushort)(0xC0 | dma_channel));
8927 outp(0x000A, dma_channel);
8928 } else if (dma_channel < 8) {
8929 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4)));
8930 outp(0x00D4, (ushort)(dma_channel - 4));
8931 }
51219358
MW		 8932}
8933#endif /* CONFIG_ISA */
8934
8935static int AscStopQueueExe(PortAddr iop_base)
8936{
8937 int count = 0;
8938
8939 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) {
8940 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B,
8941 ASC_STOP_REQ_RISC_STOP);
8942 do {
8943 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) &
8944 ASC_STOP_ACK_RISC_STOP) {
8945 return (1);
8946 }
8947 mdelay(100);
8948 } while (count++ < 20);
8949 }
8950 return (0);
8951}
8952
95cfab6c 8953static unsigned int AscGetMaxDmaCount(ushort bus_type)
51219358
MW		 8954{
8955 if (bus_type & ASC_IS_ISA)
8956 return ASC_MAX_ISA_DMA_COUNT;
8957 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL))
8958 return ASC_MAX_VL_DMA_COUNT;
8959 return ASC_MAX_PCI_DMA_COUNT;
27c868c2 8960}
1da177e4 8961
51219358 8962#ifdef CONFIG_ISA
6f039790 8963static ushort AscGetIsaDmaChannel(PortAddr iop_base)
27c868c2 8964{
51219358 8965 ushort channel;
1da177e4 8966
51219358
MW		 8967 channel = AscGetChipCfgLsw(iop_base) & 0x0003;
8968 if (channel == 0x03)
8969 return (0);
8970 else if (channel == 0x00)
8971 return (7);
8972 return (channel + 4);
8973}
1da177e4 8974
6f039790 8975static ushort AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel)
51219358
MW		 8976{
8977 ushort cfg_lsw;
8978 uchar value;
1da177e4 8979
51219358
MW		 8980 if ((dma_channel >= 5) && (dma_channel <= 7)) {
8981 if (dma_channel == 7)
8982 value = 0x00;
8983 else
8984 value = dma_channel - 4;
8985 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC;
8986 cfg_lsw |= value;
8987 AscSetChipCfgLsw(iop_base, cfg_lsw);
8988 return (AscGetIsaDmaChannel(iop_base));
8989 }
8990 return 0;
8991}
1da177e4 8992
6f039790 8993static uchar AscGetIsaDmaSpeed(PortAddr iop_base)
51219358
MW		 8994{
8995 uchar speed_value;
1da177e4 8996
51219358
MW		 8997 AscSetBank(iop_base, 1);
8998 speed_value = AscReadChipDmaSpeed(iop_base);
8999 speed_value &= 0x07;
9000 AscSetBank(iop_base, 0);
9001 return speed_value;
9002}
1da177e4 9003
6f039790 9004static uchar AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value)
51219358
MW		 9005{
9006 speed_value &= 0x07;
9007 AscSetBank(iop_base, 1);
9008 AscWriteChipDmaSpeed(iop_base, speed_value);
9009 AscSetBank(iop_base, 0);
9010 return AscGetIsaDmaSpeed(iop_base);
9011}
9012#endif /* CONFIG_ISA */
1da177e4 9013
f33134e5 9014static void AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc)
51219358
MW		 9015{
9016 int i;
9017 PortAddr iop_base;
51219358 9018 uchar chip_version;
1da177e4 9019
51219358 9020 iop_base = asc_dvc->iop_base;
51219358
MW		 9021 asc_dvc->err_code = 0;
9022 if ((asc_dvc->bus_type &
9023 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) {
9024 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE;
27c868c2 9025 }
51219358
MW		 9026 AscSetChipControl(iop_base, CC_HALT);
9027 AscSetChipStatus(iop_base, 0);
9028 asc_dvc->bug_fix_cntl = 0;
9029 asc_dvc->pci_fix_asyn_xfer = 0;
9030 asc_dvc->pci_fix_asyn_xfer_always = 0;
421f91d2 9031 /* asc_dvc->init_state initialized in AscInitGetConfig(). */
51219358
MW		 9032 asc_dvc->sdtr_done = 0;
9033 asc_dvc->cur_total_qng = 0;
ae26759e 9034 asc_dvc->is_in_int = false;
51219358
MW		 9035 asc_dvc->in_critical_cnt = 0;
9036 asc_dvc->last_q_shortage = 0;
9037 asc_dvc->use_tagged_qng = 0;
9038 asc_dvc->no_scam = 0;
9039 asc_dvc->unit_not_ready = 0;
9040 asc_dvc->queue_full_or_busy = 0;
9041 asc_dvc->redo_scam = 0;
9042 asc_dvc->res2 = 0;
afbb68c3 9043 asc_dvc->min_sdtr_index = 0;
51219358
MW		 9044 asc_dvc->cfg->can_tagged_qng = 0;
9045 asc_dvc->cfg->cmd_qng_enabled = 0;
9046 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL;
9047 asc_dvc->init_sdtr = 0;
9048 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG;
9049 asc_dvc->scsi_reset_wait = 3;
9050 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET;
9051 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type);
9052 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET;
9053 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET;
9054 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID;
51219358
MW		 9055 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type);
9056 asc_dvc->cfg->chip_version = chip_version;
afbb68c3 9057 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period;
51219358
MW		 9058 asc_dvc->max_sdtr_index = 7;
9059 if ((asc_dvc->bus_type & ASC_IS_PCI) &&
9060 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) {
9061 asc_dvc->bus_type = ASC_IS_PCI_ULTRA;
afbb68c3 9062 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period;
51219358
MW		 9063 asc_dvc->max_sdtr_index = 15;
9064 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) {
9065 AscSetExtraControl(iop_base,
9066 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9067 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) {
9068 AscSetExtraControl(iop_base,
9069 (SEC_ACTIVE_NEGATE |
9070 SEC_ENABLE_FILTER));
27c868c2
MW		 9071 }
9072 }
51219358
MW		 9073 if (asc_dvc->bus_type == ASC_IS_PCI) {
9074 AscSetExtraControl(iop_base,
9075 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE));
9076 }
1da177e4 9077
51219358
MW		 9078 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED;
9079#ifdef CONFIG_ISA
9080 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) {
9081 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) {
9082 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT);
9083 asc_dvc->bus_type = ASC_IS_ISAPNP;
27c868c2 9084 }
51219358
MW		 9085 asc_dvc->cfg->isa_dma_channel =
9086 (uchar)AscGetIsaDmaChannel(iop_base);
27c868c2 9087 }
51219358
MW		 9088#endif /* CONFIG_ISA */
9089 for (i = 0; i <= ASC_MAX_TID; i++) {
9090 asc_dvc->cur_dvc_qng[i] = 0;
9091 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG;
9092 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L;
9093 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L;
9094 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG;
27c868c2 9095 }
51219358 9096}
1da177e4 9097
6f039790 9098static int AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg)
51219358
MW		 9099{
9100 int retry;
27c868c2 9101
51219358
MW		 9102 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) {
9103 unsigned char read_back;
9104 AscSetChipEEPCmd(iop_base, cmd_reg);
9105 mdelay(1);
9106 read_back = AscGetChipEEPCmd(iop_base);
9107 if (read_back == cmd_reg)
9108 return 1;
27c868c2 9109 }
51219358
MW		 9110 return 0;
9111}
1da177e4 9112
6f039790 9113static void AscWaitEEPRead(void)
51219358
MW		 9114{
9115 mdelay(1);
27c868c2 9116}
1da177e4 9117
6f039790 9118static ushort AscReadEEPWord(PortAddr iop_base, uchar addr)
27c868c2 9119{
51219358
MW		 9120 ushort read_wval;
9121 uchar cmd_reg;
27c868c2 9122
51219358
MW		 9123 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9124 AscWaitEEPRead();
9125 cmd_reg = addr | ASC_EEP_CMD_READ;
9126 AscWriteEEPCmdReg(iop_base, cmd_reg);
9127 AscWaitEEPRead();
9128 read_wval = AscGetChipEEPData(iop_base);
9129 AscWaitEEPRead();
9130 return read_wval;
9131}
27c868c2 9132
6f039790
GKH		 9133static ushort AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9134 ushort bus_type)
51219358
MW		 9135{
9136 ushort wval;
9137 ushort sum;
9138 ushort *wbuf;
9139 int cfg_beg;
9140 int cfg_end;
9141 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9142 int s_addr;
27c868c2 9143
51219358
MW		 9144 wbuf = (ushort *)cfg_buf;
9145 sum = 0;
9146 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */
9147 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9148 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9149 sum += *wbuf;
9150 }
9151 if (bus_type & ASC_IS_VL) {
9152 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9153 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9154 } else {
9155 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9156 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9157 }
9158 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9159 wval = AscReadEEPWord(iop_base, (uchar)s_addr);
9160 if (s_addr <= uchar_end_in_config) {
9161 /*
9162 * Swap all char fields - must unswap bytes already swapped
9163 * by AscReadEEPWord().
9164 */
9165 *wbuf = le16_to_cpu(wval);
9166 } else {
9167 /* Don't swap word field at the end - cntl field. */
9168 *wbuf = wval;
9169 }
9170 sum += wval; /* Checksum treats all EEPROM data as words. */
9171 }
27c868c2 9172 /*
51219358
MW		 9173 * Read the checksum word which will be compared against 'sum'
9174 * by the caller. Word field already swapped.
27c868c2 9175 */
51219358
MW		 9176 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr);
9177 return sum;
9178}
1da177e4 9179
6f039790 9180static int AscTestExternalLram(ASC_DVC_VAR *asc_dvc)
51219358
MW		 9181{
9182 PortAddr iop_base;
9183 ushort q_addr;
9184 ushort saved_word;
9185 int sta;
1da177e4 9186
51219358
MW		 9187 iop_base = asc_dvc->iop_base;
9188 sta = 0;
9189 q_addr = ASC_QNO_TO_QADDR(241);
9190 saved_word = AscReadLramWord(iop_base, q_addr);
9191 AscSetChipLramAddr(iop_base, q_addr);
9192 AscSetChipLramData(iop_base, 0x55AA);
9193 mdelay(10);
9194 AscSetChipLramAddr(iop_base, q_addr);
9195 if (AscGetChipLramData(iop_base) == 0x55AA) {
9196 sta = 1;
9197 AscWriteLramWord(iop_base, q_addr, saved_word);
9198 }
9199 return (sta);
9200}
1da177e4 9201
6f039790 9202static void AscWaitEEPWrite(void)
51219358
MW		 9203{
9204 mdelay(20);
51219358 9205}
1da177e4 9206
6f039790 9207static int AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg)
51219358
MW		 9208{
9209 ushort read_back;
9210 int retry;
1da177e4 9211
51219358 9212 retry = 0;
ae26759e 9213 while (true) {
51219358
MW		 9214 AscSetChipEEPData(iop_base, data_reg);
9215 mdelay(1);
9216 read_back = AscGetChipEEPData(iop_base);
9217 if (read_back == data_reg) {
9218 return (1);
9219 }
9220 if (retry++ > ASC_EEP_MAX_RETRY) {
9221 return (0);
9222 }
27c868c2 9223 }
51219358 9224}
27c868c2 9225
6f039790 9226static ushort AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val)
51219358
MW		 9227{
9228 ushort read_wval;
9229
9230 read_wval = AscReadEEPWord(iop_base, addr);
9231 if (read_wval != word_val) {
9232 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE);
9233 AscWaitEEPRead();
9234 AscWriteEEPDataReg(iop_base, word_val);
9235 AscWaitEEPRead();
9236 AscWriteEEPCmdReg(iop_base,
9237 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr));
9238 AscWaitEEPWrite();
9239 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE);
9240 AscWaitEEPRead();
9241 return (AscReadEEPWord(iop_base, addr));
9242 }
9243 return (read_wval);
9244}
9245
6f039790
GKH		 9246static int AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9247 ushort bus_type)
51219358
MW		 9248{
9249 int n_error;
9250 ushort *wbuf;
9251 ushort word;
9252 ushort sum;
9253 int s_addr;
9254 int cfg_beg;
9255 int cfg_end;
9256 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2;
9257
9258 wbuf = (ushort *)cfg_buf;
9259 n_error = 0;
9260 sum = 0;
9261 /* Write two config words; AscWriteEEPWord() will swap bytes. */
9262 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9263 sum += *wbuf;
9264 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9265 n_error++;
27c868c2 9266 }
51219358
MW		 9267 }
9268 if (bus_type & ASC_IS_VL) {
9269 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9270 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9271 } else {
9272 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9273 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9274 }
9275 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9276 if (s_addr <= uchar_end_in_config) {
9277 /*
9278 * This is a char field. Swap char fields before they are
9279 * swapped again by AscWriteEEPWord().
9280 */
9281 word = cpu_to_le16(*wbuf);
9282 if (word !=
9283 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) {
9284 n_error++;
9285 }
9286 } else {
9287 /* Don't swap word field at the end - cntl field. */
9288 if (*wbuf !=
9289 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) {
9290 n_error++;
9291 }
27c868c2 9292 }
51219358
MW		 9293 sum += *wbuf; /* Checksum calculated from word values. */
9294 }
9295 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */
9296 *wbuf = sum;
9297 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) {
9298 n_error++;
27c868c2 9299 }
1da177e4 9300
51219358
MW		 9301 /* Read EEPROM back again. */
9302 wbuf = (ushort *)cfg_buf;
27c868c2 9303 /*
51219358 9304 * Read two config words; Byte-swapping done by AscReadEEPWord().
27c868c2 9305 */
51219358
MW		 9306 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) {
9307 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) {
9308 n_error++;
27c868c2
MW		 9309 }
9310 }
51219358
MW		 9311 if (bus_type & ASC_IS_VL) {
9312 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL;
9313 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL;
9314 } else {
9315 cfg_beg = ASC_EEP_DVC_CFG_BEG;
9316 cfg_end = ASC_EEP_MAX_DVC_ADDR;
9317 }
9318 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) {
9319 if (s_addr <= uchar_end_in_config) {
9320 /*
9321 * Swap all char fields. Must unswap bytes already swapped
9322 * by AscReadEEPWord().
9323 */
9324 word =
9325 le16_to_cpu(AscReadEEPWord
9326 (iop_base, (uchar)s_addr));
27c868c2 9327 } else {
51219358
MW		 9328 /* Don't swap word field at the end - cntl field. */
9329 word = AscReadEEPWord(iop_base, (uchar)s_addr);
9330 }
9331 if (*wbuf != word) {
9332 n_error++;
27c868c2
MW		 9333 }
9334 }
51219358
MW		 9335 /* Read checksum; Byte swapping not needed. */
9336 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) {
9337 n_error++;
27c868c2 9338 }
51219358
MW		 9339 return n_error;
9340}
1da177e4 9341
6f039790
GKH		 9342static int AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf,
9343 ushort bus_type)
51219358
MW		 9344{
9345 int retry;
9346 int n_error;
27c868c2 9347
51219358 9348 retry = 0;
ae26759e 9349 while (true) {
51219358
MW		 9350 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf,
9351 bus_type)) == 0) {
9352 break;
9353 }
9354 if (++retry > ASC_EEP_MAX_RETRY) {
9355 break;
9356 }
9357 }
9358 return n_error;
9359}
27c868c2 9360
f33134e5 9361static int AscInitFromEEP(ASC_DVC_VAR *asc_dvc)
51219358
MW		 9362{
9363 ASCEEP_CONFIG eep_config_buf;
9364 ASCEEP_CONFIG *eep_config;
9365 PortAddr iop_base;
9366 ushort chksum;
9367 ushort warn_code;
9368 ushort cfg_msw, cfg_lsw;
9369 int i;
9370 int write_eep = 0;
27c868c2 9371
51219358
MW		 9372 iop_base = asc_dvc->iop_base;
9373 warn_code = 0;
9374 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE);
9375 AscStopQueueExe(iop_base);
ae26759e 9376 if ((AscStopChip(iop_base)) ||
51219358
MW		 9377 (AscGetChipScsiCtrl(iop_base) != 0)) {
9378 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE;
9379 AscResetChipAndScsiBus(asc_dvc);
9380 mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
9381 }
d647c783 9382 if (!AscIsChipHalted(iop_base)) {
51219358
MW		 9383 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
9384 return (warn_code);
9385 }
9386 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
9387 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
9388 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
9389 return (warn_code);
9390 }
9391 eep_config = (ASCEEP_CONFIG *)&eep_config_buf;
9392 cfg_msw = AscGetChipCfgMsw(iop_base);
9393 cfg_lsw = AscGetChipCfgLsw(iop_base);
9394 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9395 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9396 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9397 AscSetChipCfgMsw(iop_base, cfg_msw);
9398 }
9399 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type);
b352f923 9400 ASC_DBG(1, "chksum 0x%x\n", chksum);
51219358
MW		 9401 if (chksum == 0) {
9402 chksum = 0xaa55;
9403 }
9404 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9405 warn_code |= ASC_WARN_AUTO_CONFIG;
9406 if (asc_dvc->cfg->chip_version == 3) {
9407 if (eep_config->cfg_lsw != cfg_lsw) {
9408 warn_code |= ASC_WARN_EEPROM_RECOVER;
9409 eep_config->cfg_lsw =
9410 AscGetChipCfgLsw(iop_base);
9411 }
9412 if (eep_config->cfg_msw != cfg_msw) {
9413 warn_code |= ASC_WARN_EEPROM_RECOVER;
9414 eep_config->cfg_msw =
9415 AscGetChipCfgMsw(iop_base);
9416 }
9417 }
9418 }
9419 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9420 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON;
b352f923 9421 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum);
51219358
MW		 9422 if (chksum != eep_config->chksum) {
9423 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) ==
9424 ASC_CHIP_VER_PCI_ULTRA_3050) {
b352f923 9425 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n");
51219358
MW		 9426 eep_config->init_sdtr = 0xFF;
9427 eep_config->disc_enable = 0xFF;
9428 eep_config->start_motor = 0xFF;
9429 eep_config->use_cmd_qng = 0;
9430 eep_config->max_total_qng = 0xF0;
9431 eep_config->max_tag_qng = 0x20;
9432 eep_config->cntl = 0xBFFF;
9433 ASC_EEP_SET_CHIP_ID(eep_config, 7);
9434 eep_config->no_scam = 0;
9435 eep_config->adapter_info[0] = 0;
9436 eep_config->adapter_info[1] = 0;
9437 eep_config->adapter_info[2] = 0;
9438 eep_config->adapter_info[3] = 0;
9439 eep_config->adapter_info[4] = 0;
9440 /* Indicate EEPROM-less board. */
9441 eep_config->adapter_info[5] = 0xBB;
27c868c2 9442 } else {
51219358
MW		 9443 ASC_PRINT
9444 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n");
9445 write_eep = 1;
9446 warn_code |= ASC_WARN_EEPROM_CHKSUM;
9447 }
9448 }
9449 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr;
9450 asc_dvc->cfg->disc_enable = eep_config->disc_enable;
9451 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng;
9452 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config);
9453 asc_dvc->start_motor = eep_config->start_motor;
9454 asc_dvc->dvc_cntl = eep_config->cntl;
9455 asc_dvc->no_scam = eep_config->no_scam;
9456 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0];
9457 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1];
9458 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2];
9459 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3];
9460 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4];
9461 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5];
9462 if (!AscTestExternalLram(asc_dvc)) {
9463 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) ==
9464 ASC_IS_PCI_ULTRA)) {
9465 eep_config->max_total_qng =
9466 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG;
9467 eep_config->max_tag_qng =
9468 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG;
9469 } else {
9470 eep_config->cfg_msw |= 0x0800;
9471 cfg_msw |= 0x0800;
9472 AscSetChipCfgMsw(iop_base, cfg_msw);
9473 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG;
9474 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG;
27c868c2 9475 }
51219358
MW		 9476 } else {
9477 }
9478 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) {
9479 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG;
9480 }
9481 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) {
9482 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG;
9483 }
9484 if (eep_config->max_tag_qng > eep_config->max_total_qng) {
9485 eep_config->max_tag_qng = eep_config->max_total_qng;
9486 }
9487 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) {
9488 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC;
9489 }
9490 asc_dvc->max_total_qng = eep_config->max_total_qng;
9491 if ((eep_config->use_cmd_qng & eep_config->disc_enable) !=
9492 eep_config->use_cmd_qng) {
9493 eep_config->disc_enable = eep_config->use_cmd_qng;
9494 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9495 }
51219358
MW		 9496 ASC_EEP_SET_CHIP_ID(eep_config,
9497 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID);
9498 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config);
9499 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) &&
9500 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) {
afbb68c3 9501 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX;
27c868c2 9502 }
1da177e4 9503
51219358
MW		 9504 for (i = 0; i <= ASC_MAX_TID; i++) {
9505 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i];
9506 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng;
9507 asc_dvc->cfg->sdtr_period_offset[i] =
9508 (uchar)(ASC_DEF_SDTR_OFFSET |
afbb68c3 9509 (asc_dvc->min_sdtr_index << 4));
51219358
MW		 9510 }
9511 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base);
9512 if (write_eep) {
9513 if ((i = AscSetEEPConfig(iop_base, eep_config,
9514 asc_dvc->bus_type)) != 0) {
9515 ASC_PRINT1
9516 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n",
9517 i);
27c868c2 9518 } else {
51219358
MW		 9519 ASC_PRINT
9520 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n");
27c868c2
MW		 9521 }
9522 }
51219358 9523 return (warn_code);
1da177e4
LT		 9524}
9525
6f039790 9526static int AscInitGetConfig(struct Scsi_Host *shost)
1da177e4 9527{
9d0e96eb
MW		 9528 struct asc_board *board = shost_priv(shost);
9529 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
51219358 9530 unsigned short warn_code = 0;
27c868c2 9531
51219358
MW		 9532 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG;
9533 if (asc_dvc->err_code != 0)
9534 return asc_dvc->err_code;
27c868c2 9535
51219358 9536 if (AscFindSignature(asc_dvc->iop_base)) {
f33134e5
HR		 9537 AscInitAscDvcVar(asc_dvc);
9538 warn_code = AscInitFromEEP(asc_dvc);
51219358
MW		 9539 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG;
9540 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT)
9541 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT;
9542 } else {
9543 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9544 }
27c868c2 9545
51219358
MW		 9546 switch (warn_code) {
9547 case 0: /* No error */
9548 break;
9549 case ASC_WARN_IO_PORT_ROTATE:
9d0e96eb
MW		 9550 shost_printk(KERN_WARNING, shost, "I/O port address "
9551 "modified\n");
51219358
MW		 9552 break;
9553 case ASC_WARN_AUTO_CONFIG:
9d0e96eb
MW		 9554 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9555 "enabled\n");
51219358
MW		 9556 break;
9557 case ASC_WARN_EEPROM_CHKSUM:
9d0e96eb 9558 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
51219358
MW		 9559 break;
9560 case ASC_WARN_IRQ_MODIFIED:
9d0e96eb 9561 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
51219358
MW		 9562 break;
9563 case ASC_WARN_CMD_QNG_CONFLICT:
9d0e96eb
MW		 9564 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o "
9565 "disconnects\n");
51219358
MW		 9566 break;
9567 default:
9d0e96eb
MW		 9568 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9569 warn_code);
51219358
MW		 9570 break;
9571 }
1da177e4 9572
9d0e96eb
MW		 9573 if (asc_dvc->err_code != 0)
9574 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9575 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
27c868c2 9576
51219358
MW		 9577 return asc_dvc->err_code;
9578}
1da177e4 9579
6f039790 9580static int AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
51219358 9581{
9d0e96eb
MW		 9582 struct asc_board *board = shost_priv(shost);
9583 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var;
51219358
MW		 9584 PortAddr iop_base = asc_dvc->iop_base;
9585 unsigned short cfg_msw;
9586 unsigned short warn_code = 0;
1da177e4 9587
51219358
MW		 9588 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG;
9589 if (asc_dvc->err_code != 0)
9590 return asc_dvc->err_code;
9591 if (!AscFindSignature(asc_dvc->iop_base)) {
9592 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
9593 return asc_dvc->err_code;
27c868c2 9594 }
1da177e4 9595
51219358
MW		 9596 cfg_msw = AscGetChipCfgMsw(iop_base);
9597 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) {
9598 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK;
9599 warn_code |= ASC_WARN_CFG_MSW_RECOVER;
9600 AscSetChipCfgMsw(iop_base, cfg_msw);
9601 }
9602 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) !=
9603 asc_dvc->cfg->cmd_qng_enabled) {
9604 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled;
9605 warn_code |= ASC_WARN_CMD_QNG_CONFLICT;
9606 }
9607 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) {
9608 warn_code |= ASC_WARN_AUTO_CONFIG;
9609 }
51219358
MW		 9610#ifdef CONFIG_PCI
9611 if (asc_dvc->bus_type & ASC_IS_PCI) {
9612 cfg_msw &= 0xFFC0;
9613 AscSetChipCfgMsw(iop_base, cfg_msw);
9614 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) {
27c868c2 9615 } else {
51219358
MW		 9616 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
9617 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
9618 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB;
9619 asc_dvc->bug_fix_cntl |=
9620 ASC_BUG_FIX_ASYN_USE_SYN;
9621 }
27c868c2 9622 }
51219358
MW		 9623 } else
9624#endif /* CONFIG_PCI */
9625 if (asc_dvc->bus_type == ASC_IS_ISAPNP) {
9626 if (AscGetChipVersion(iop_base, asc_dvc->bus_type)
9627 == ASC_CHIP_VER_ASYN_BUG) {
9628 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN;
27c868c2
MW		 9629 }
9630 }
51219358
MW		 9631 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) !=
9632 asc_dvc->cfg->chip_scsi_id) {
9633 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID;
9634 }
9635#ifdef CONFIG_ISA
9636 if (asc_dvc->bus_type & ASC_IS_ISA) {
9637 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel);
9638 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed);
9639 }
9640#endif /* CONFIG_ISA */
1da177e4 9641
51219358
MW		 9642 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG;
9643
9644 switch (warn_code) {
9645 case 0: /* No error. */
9646 break;
9647 case ASC_WARN_IO_PORT_ROTATE:
9d0e96eb
MW		 9648 shost_printk(KERN_WARNING, shost, "I/O port address "
9649 "modified\n");
51219358
MW		 9650 break;
9651 case ASC_WARN_AUTO_CONFIG:
9d0e96eb
MW		 9652 shost_printk(KERN_WARNING, shost, "I/O port increment switch "
9653 "enabled\n");
51219358
MW		 9654 break;
9655 case ASC_WARN_EEPROM_CHKSUM:
9d0e96eb 9656 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n");
51219358
MW		 9657 break;
9658 case ASC_WARN_IRQ_MODIFIED:
9d0e96eb 9659 shost_printk(KERN_WARNING, shost, "IRQ modified\n");
51219358
MW		 9660 break;
9661 case ASC_WARN_CMD_QNG_CONFLICT:
9d0e96eb
MW		 9662 shost_printk(KERN_WARNING, shost, "tag queuing w/o "
9663 "disconnects\n");
51219358
MW		 9664 break;
9665 default:
9d0e96eb
MW		 9666 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n",
9667 warn_code);
51219358 9668 break;
27c868c2 9669 }
1da177e4 9670
9d0e96eb
MW		 9671 if (asc_dvc->err_code != 0)
9672 shost_printk(KERN_ERR, shost, "error 0x%x at init_state "
9673 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state);
27c868c2 9674
51219358
MW		 9675 return asc_dvc->err_code;
9676}
27c868c2 9677
51219358
MW		 9678/*
9679 * EEPROM Configuration.
9680 *
9681 * All drivers should use this structure to set the default EEPROM
9682 * configuration. The BIOS now uses this structure when it is built.
9683 * Additional structure information can be found in a_condor.h where
9684 * the structure is defined.
9685 *
9686 * The *_Field_IsChar structs are needed to correct for endianness.
9687 * These values are read from the board 16 bits at a time directly
9688 * into the structs. Because some fields are char, the values will be
9689 * in the wrong order. The *_Field_IsChar tells when to flip the
9690 * bytes. Data read and written to PCI memory is automatically swapped
9691 * on big-endian platforms so char fields read as words are actually being
9692 * unswapped on big-endian platforms.
9693 */
6f039790 9694static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config = {
51219358
MW		 9695 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */
9696 0x0000, /* cfg_msw */
9697 0xFFFF, /* disc_enable */
9698 0xFFFF, /* wdtr_able */
9699 0xFFFF, /* sdtr_able */
9700 0xFFFF, /* start_motor */
9701 0xFFFF, /* tagqng_able */
9702 0xFFFF, /* bios_scan */
9703 0, /* scam_tolerant */
9704 7, /* adapter_scsi_id */
9705 0, /* bios_boot_delay */
9706 3, /* scsi_reset_delay */
9707 0, /* bios_id_lun */
9708 0, /* termination */
9709 0, /* reserved1 */
9710 0xFFE7, /* bios_ctrl */
9711 0xFFFF, /* ultra_able */
9712 0, /* reserved2 */
9713 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */
9714 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9715 0, /* dvc_cntl */
9716 0, /* bug_fix */
9717 0, /* serial_number_word1 */
9718 0, /* serial_number_word2 */
9719 0, /* serial_number_word3 */
9720 0, /* check_sum */
9721 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9722 , /* oem_name[16] */
9723 0, /* dvc_err_code */
9724 0, /* adv_err_code */
9725 0, /* adv_err_addr */
9726 0, /* saved_dvc_err_code */
9727 0, /* saved_adv_err_code */
9728 0, /* saved_adv_err_addr */
9729 0 /* num_of_err */
9730};
27c868c2 9731
6f039790 9732static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar = {
51219358
MW		 9733 0, /* cfg_lsw */
9734 0, /* cfg_msw */
9735 0, /* -disc_enable */
9736 0, /* wdtr_able */
9737 0, /* sdtr_able */
9738 0, /* start_motor */
9739 0, /* tagqng_able */
9740 0, /* bios_scan */
9741 0, /* scam_tolerant */
9742 1, /* adapter_scsi_id */
9743 1, /* bios_boot_delay */
9744 1, /* scsi_reset_delay */
9745 1, /* bios_id_lun */
9746 1, /* termination */
9747 1, /* reserved1 */
9748 0, /* bios_ctrl */
9749 0, /* ultra_able */
9750 0, /* reserved2 */
9751 1, /* max_host_qng */
9752 1, /* max_dvc_qng */
9753 0, /* dvc_cntl */
9754 0, /* bug_fix */
9755 0, /* serial_number_word1 */
9756 0, /* serial_number_word2 */
9757 0, /* serial_number_word3 */
9758 0, /* check_sum */
9759 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9760 , /* oem_name[16] */
9761 0, /* dvc_err_code */
9762 0, /* adv_err_code */
9763 0, /* adv_err_addr */
9764 0, /* saved_dvc_err_code */
9765 0, /* saved_adv_err_code */
9766 0, /* saved_adv_err_addr */
9767 0 /* num_of_err */
9768};
1da177e4 9769
6f039790 9770static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config = {
51219358
MW		 9771 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9772 0x0000, /* 01 cfg_msw */
9773 0xFFFF, /* 02 disc_enable */
9774 0xFFFF, /* 03 wdtr_able */
9775 0x4444, /* 04 sdtr_speed1 */
9776 0xFFFF, /* 05 start_motor */
9777 0xFFFF, /* 06 tagqng_able */
9778 0xFFFF, /* 07 bios_scan */
9779 0, /* 08 scam_tolerant */
9780 7, /* 09 adapter_scsi_id */
9781 0, /* bios_boot_delay */
9782 3, /* 10 scsi_reset_delay */
9783 0, /* bios_id_lun */
9784 0, /* 11 termination_se */
9785 0, /* termination_lvd */
9786 0xFFE7, /* 12 bios_ctrl */
9787 0x4444, /* 13 sdtr_speed2 */
9788 0x4444, /* 14 sdtr_speed3 */
9789 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9790 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9791 0, /* 16 dvc_cntl */
9792 0x4444, /* 17 sdtr_speed4 */
9793 0, /* 18 serial_number_word1 */
9794 0, /* 19 serial_number_word2 */
9795 0, /* 20 serial_number_word3 */
9796 0, /* 21 check_sum */
9797 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9798 , /* 22-29 oem_name[16] */
9799 0, /* 30 dvc_err_code */
9800 0, /* 31 adv_err_code */
9801 0, /* 32 adv_err_addr */
9802 0, /* 33 saved_dvc_err_code */
9803 0, /* 34 saved_adv_err_code */
9804 0, /* 35 saved_adv_err_addr */
9805 0, /* 36 reserved */
9806 0, /* 37 reserved */
9807 0, /* 38 reserved */
9808 0, /* 39 reserved */
9809 0, /* 40 reserved */
9810 0, /* 41 reserved */
9811 0, /* 42 reserved */
9812 0, /* 43 reserved */
9813 0, /* 44 reserved */
9814 0, /* 45 reserved */
9815 0, /* 46 reserved */
9816 0, /* 47 reserved */
9817 0, /* 48 reserved */
9818 0, /* 49 reserved */
9819 0, /* 50 reserved */
9820 0, /* 51 reserved */
9821 0, /* 52 reserved */
9822 0, /* 53 reserved */
9823 0, /* 54 reserved */
9824 0, /* 55 reserved */
9825 0, /* 56 cisptr_lsw */
9826 0, /* 57 cisprt_msw */
9827 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9828 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */
9829 0, /* 60 reserved */
9830 0, /* 61 reserved */
9831 0, /* 62 reserved */
9832 0 /* 63 reserved */
9833};
27c868c2 9834
6f039790 9835static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar = {
51219358
MW		 9836 0, /* 00 cfg_lsw */
9837 0, /* 01 cfg_msw */
9838 0, /* 02 disc_enable */
9839 0, /* 03 wdtr_able */
9840 0, /* 04 sdtr_speed1 */
9841 0, /* 05 start_motor */
9842 0, /* 06 tagqng_able */
9843 0, /* 07 bios_scan */
9844 0, /* 08 scam_tolerant */
9845 1, /* 09 adapter_scsi_id */
9846 1, /* bios_boot_delay */
9847 1, /* 10 scsi_reset_delay */
9848 1, /* bios_id_lun */
9849 1, /* 11 termination_se */
9850 1, /* termination_lvd */
9851 0, /* 12 bios_ctrl */
9852 0, /* 13 sdtr_speed2 */
9853 0, /* 14 sdtr_speed3 */
9854 1, /* 15 max_host_qng */
9855 1, /* max_dvc_qng */
9856 0, /* 16 dvc_cntl */
9857 0, /* 17 sdtr_speed4 */
9858 0, /* 18 serial_number_word1 */
9859 0, /* 19 serial_number_word2 */
9860 0, /* 20 serial_number_word3 */
9861 0, /* 21 check_sum */
9862 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9863 , /* 22-29 oem_name[16] */
9864 0, /* 30 dvc_err_code */
9865 0, /* 31 adv_err_code */
9866 0, /* 32 adv_err_addr */
9867 0, /* 33 saved_dvc_err_code */
9868 0, /* 34 saved_adv_err_code */
9869 0, /* 35 saved_adv_err_addr */
9870 0, /* 36 reserved */
9871 0, /* 37 reserved */
9872 0, /* 38 reserved */
9873 0, /* 39 reserved */
9874 0, /* 40 reserved */
9875 0, /* 41 reserved */
9876 0, /* 42 reserved */
9877 0, /* 43 reserved */
9878 0, /* 44 reserved */
9879 0, /* 45 reserved */
9880 0, /* 46 reserved */
9881 0, /* 47 reserved */
9882 0, /* 48 reserved */
9883 0, /* 49 reserved */
9884 0, /* 50 reserved */
9885 0, /* 51 reserved */
9886 0, /* 52 reserved */
9887 0, /* 53 reserved */
9888 0, /* 54 reserved */
9889 0, /* 55 reserved */
9890 0, /* 56 cisptr_lsw */
9891 0, /* 57 cisprt_msw */
9892 0, /* 58 subsysvid */
9893 0, /* 59 subsysid */
9894 0, /* 60 reserved */
9895 0, /* 61 reserved */
9896 0, /* 62 reserved */
9897 0 /* 63 reserved */
9898};
27c868c2 9899
6f039790 9900static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config = {
51219358
MW		 9901 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */
9902 0x0000, /* 01 cfg_msw */
9903 0xFFFF, /* 02 disc_enable */
9904 0xFFFF, /* 03 wdtr_able */
9905 0x5555, /* 04 sdtr_speed1 */
9906 0xFFFF, /* 05 start_motor */
9907 0xFFFF, /* 06 tagqng_able */
9908 0xFFFF, /* 07 bios_scan */
9909 0, /* 08 scam_tolerant */
9910 7, /* 09 adapter_scsi_id */
9911 0, /* bios_boot_delay */
9912 3, /* 10 scsi_reset_delay */
9913 0, /* bios_id_lun */
9914 0, /* 11 termination_se */
9915 0, /* termination_lvd */
9916 0xFFE7, /* 12 bios_ctrl */
9917 0x5555, /* 13 sdtr_speed2 */
9918 0x5555, /* 14 sdtr_speed3 */
9919 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */
9920 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */
9921 0, /* 16 dvc_cntl */
9922 0x5555, /* 17 sdtr_speed4 */
9923 0, /* 18 serial_number_word1 */
9924 0, /* 19 serial_number_word2 */
9925 0, /* 20 serial_number_word3 */
9926 0, /* 21 check_sum */
9927 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
9928 , /* 22-29 oem_name[16] */
9929 0, /* 30 dvc_err_code */
9930 0, /* 31 adv_err_code */
9931 0, /* 32 adv_err_addr */
9932 0, /* 33 saved_dvc_err_code */
9933 0, /* 34 saved_adv_err_code */
9934 0, /* 35 saved_adv_err_addr */
9935 0, /* 36 reserved */
9936 0, /* 37 reserved */
9937 0, /* 38 reserved */
9938 0, /* 39 reserved */
9939 0, /* 40 reserved */
9940 0, /* 41 reserved */
9941 0, /* 42 reserved */
9942 0, /* 43 reserved */
9943 0, /* 44 reserved */
9944 0, /* 45 reserved */
9945 0, /* 46 reserved */
9946 0, /* 47 reserved */
9947 0, /* 48 reserved */
9948 0, /* 49 reserved */
9949 0, /* 50 reserved */
9950 0, /* 51 reserved */
9951 0, /* 52 reserved */
9952 0, /* 53 reserved */
9953 0, /* 54 reserved */
9954 0, /* 55 reserved */
9955 0, /* 56 cisptr_lsw */
9956 0, /* 57 cisprt_msw */
9957 PCI_VENDOR_ID_ASP, /* 58 subsysvid */
9958 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */
9959 0, /* 60 reserved */
9960 0, /* 61 reserved */
9961 0, /* 62 reserved */
9962 0 /* 63 reserved */
9963};
1da177e4 9964
6f039790 9965static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar = {
51219358
MW		 9966 0, /* 00 cfg_lsw */
9967 0, /* 01 cfg_msw */
9968 0, /* 02 disc_enable */
9969 0, /* 03 wdtr_able */
9970 0, /* 04 sdtr_speed1 */
9971 0, /* 05 start_motor */
9972 0, /* 06 tagqng_able */
9973 0, /* 07 bios_scan */
9974 0, /* 08 scam_tolerant */
9975 1, /* 09 adapter_scsi_id */
9976 1, /* bios_boot_delay */
9977 1, /* 10 scsi_reset_delay */
9978 1, /* bios_id_lun */
9979 1, /* 11 termination_se */
9980 1, /* termination_lvd */
9981 0, /* 12 bios_ctrl */
9982 0, /* 13 sdtr_speed2 */
9983 0, /* 14 sdtr_speed3 */
9984 1, /* 15 max_host_qng */
9985 1, /* max_dvc_qng */
9986 0, /* 16 dvc_cntl */
9987 0, /* 17 sdtr_speed4 */
9988 0, /* 18 serial_number_word1 */
9989 0, /* 19 serial_number_word2 */
9990 0, /* 20 serial_number_word3 */
9991 0, /* 21 check_sum */
9992 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1}
9993 , /* 22-29 oem_name[16] */
9994 0, /* 30 dvc_err_code */
9995 0, /* 31 adv_err_code */
9996 0, /* 32 adv_err_addr */
9997 0, /* 33 saved_dvc_err_code */
9998 0, /* 34 saved_adv_err_code */
9999 0, /* 35 saved_adv_err_addr */
10000 0, /* 36 reserved */
10001 0, /* 37 reserved */
10002 0, /* 38 reserved */
10003 0, /* 39 reserved */
10004 0, /* 40 reserved */
10005 0, /* 41 reserved */
10006 0, /* 42 reserved */
10007 0, /* 43 reserved */
10008 0, /* 44 reserved */
10009 0, /* 45 reserved */
10010 0, /* 46 reserved */
10011 0, /* 47 reserved */
10012 0, /* 48 reserved */
10013 0, /* 49 reserved */
10014 0, /* 50 reserved */
10015 0, /* 51 reserved */
10016 0, /* 52 reserved */
10017 0, /* 53 reserved */
10018 0, /* 54 reserved */
10019 0, /* 55 reserved */
10020 0, /* 56 cisptr_lsw */
10021 0, /* 57 cisprt_msw */
10022 0, /* 58 subsysvid */
10023 0, /* 59 subsysid */
10024 0, /* 60 reserved */
10025 0, /* 61 reserved */
10026 0, /* 62 reserved */
10027 0 /* 63 reserved */
10028};
1da177e4 10029
51219358 10030#ifdef CONFIG_PCI
1da177e4 10031/*
51219358 10032 * Wait for EEPROM command to complete
1da177e4 10033 */
6f039790 10034static void AdvWaitEEPCmd(AdvPortAddr iop_base)
1da177e4 10035{
51219358 10036 int eep_delay_ms;
27c868c2 10037
51219358
MW		 10038 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) {
10039 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) &
10040 ASC_EEP_CMD_DONE) {
10041 break;
27c868c2 10042 }
51219358 10043 mdelay(1);
27c868c2 10044 }
51219358
MW		 10045 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) ==
10046 0)
10047 BUG();
1da177e4
LT		 10048}
10049
10050/*
51219358 10051 * Read the EEPROM from specified location
1da177e4 10052 */
6f039790 10053static ushort AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr)
51219358
MW		 10054{
10055 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10056 ASC_EEP_CMD_READ | eep_word_addr);
10057 AdvWaitEEPCmd(iop_base);
10058 return AdvReadWordRegister(iop_base, IOPW_EE_DATA);
10059}
10060
10061/*
10062 * Write the EEPROM from 'cfg_buf'.
10063 */
6f039790
GKH		 10064static void AdvSet3550EEPConfig(AdvPortAddr iop_base,
10065 ADVEEP_3550_CONFIG *cfg_buf)
1da177e4 10066{
27c868c2 10067 ushort *wbuf;
51219358 10068 ushort addr, chksum;
27c868c2
MW		 10069 ushort *charfields;
10070
27c868c2 10071 wbuf = (ushort *)cfg_buf;
51219358 10072 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
27c868c2
MW		 10073 chksum = 0;
10074
51219358
MW		 10075 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10076 AdvWaitEEPCmd(iop_base);
10077
10078 /*
10079 * Write EEPROM from word 0 to word 20.
10080 */
10081 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10082 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10083 ushort word;
10084
27c868c2 10085 if (*charfields++) {
51219358 10086 word = cpu_to_le16(*wbuf);
27c868c2 10087 } else {
51219358 10088 word = *wbuf;
27c868c2 10089 }
51219358
MW		 10090 chksum += *wbuf; /* Checksum is calculated from word values. */
10091 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10092 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10093 ASC_EEP_CMD_WRITE | addr);
10094 AdvWaitEEPCmd(iop_base);
10095 mdelay(ADV_EEP_DELAY_MS);
27c868c2 10096 }
51219358
MW		 10097
10098 /*
10099 * Write EEPROM checksum at word 21.
10100 */
10101 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10102 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10103 AdvWaitEEPCmd(iop_base);
27c868c2
MW		 10104 wbuf++;
10105 charfields++;
10106
51219358
MW		 10107 /*
10108 * Write EEPROM OEM name at words 22 to 29.
10109 */
10110 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10111 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10112 ushort word;
10113
27c868c2 10114 if (*charfields++) {
51219358
MW		 10115 word = cpu_to_le16(*wbuf);
10116 } else {
10117 word = *wbuf;
27c868c2 10118 }
51219358
MW		 10119 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10120 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10121 ASC_EEP_CMD_WRITE | addr);
10122 AdvWaitEEPCmd(iop_base);
27c868c2 10123 }
51219358
MW		 10124 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10125 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 10126}
10127
10128/*
51219358 10129 * Write the EEPROM from 'cfg_buf'.
1da177e4 10130 */
6f039790
GKH		 10131static void AdvSet38C0800EEPConfig(AdvPortAddr iop_base,
10132 ADVEEP_38C0800_CONFIG *cfg_buf)
1da177e4 10133{
27c868c2 10134 ushort *wbuf;
27c868c2 10135 ushort *charfields;
51219358 10136 ushort addr, chksum;
27c868c2 10137
27c868c2 10138 wbuf = (ushort *)cfg_buf;
51219358 10139 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
27c868c2
MW		 10140 chksum = 0;
10141
51219358
MW		 10142 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10143 AdvWaitEEPCmd(iop_base);
10144
10145 /*
10146 * Write EEPROM from word 0 to word 20.
10147 */
10148 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10149 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10150 ushort word;
10151
27c868c2 10152 if (*charfields++) {
51219358 10153 word = cpu_to_le16(*wbuf);
27c868c2 10154 } else {
51219358 10155 word = *wbuf;
27c868c2 10156 }
51219358
MW		 10157 chksum += *wbuf; /* Checksum is calculated from word values. */
10158 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10159 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10160 ASC_EEP_CMD_WRITE | addr);
10161 AdvWaitEEPCmd(iop_base);
10162 mdelay(ADV_EEP_DELAY_MS);
27c868c2 10163 }
51219358
MW		 10164
10165 /*
10166 * Write EEPROM checksum at word 21.
10167 */
10168 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10169 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10170 AdvWaitEEPCmd(iop_base);
27c868c2
MW		 10171 wbuf++;
10172 charfields++;
10173
51219358
MW		 10174 /*
10175 * Write EEPROM OEM name at words 22 to 29.
10176 */
10177 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10178 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10179 ushort word;
10180
27c868c2 10181 if (*charfields++) {
51219358
MW		 10182 word = cpu_to_le16(*wbuf);
10183 } else {
10184 word = *wbuf;
27c868c2 10185 }
51219358
MW		 10186 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10187 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10188 ASC_EEP_CMD_WRITE | addr);
10189 AdvWaitEEPCmd(iop_base);
27c868c2 10190 }
51219358 10191 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
27c868c2 10192 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 10193}
10194
10195/*
10196 * Write the EEPROM from 'cfg_buf'.
10197 */
6f039790
GKH		 10198static void AdvSet38C1600EEPConfig(AdvPortAddr iop_base,
10199 ADVEEP_38C1600_CONFIG *cfg_buf)
1da177e4 10200{
27c868c2 10201 ushort *wbuf;
27c868c2 10202 ushort *charfields;
51219358 10203 ushort addr, chksum;
27c868c2
MW		 10204
10205 wbuf = (ushort *)cfg_buf;
51219358 10206 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
27c868c2
MW		 10207 chksum = 0;
10208
10209 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE);
10210 AdvWaitEEPCmd(iop_base);
10211
10212 /*
10213 * Write EEPROM from word 0 to word 20.
10214 */
10215 for (addr = ADV_EEP_DVC_CFG_BEGIN;
10216 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) {
10217 ushort word;
10218
10219 if (*charfields++) {
10220 word = cpu_to_le16(*wbuf);
10221 } else {
10222 word = *wbuf;
10223 }
10224 chksum += *wbuf; /* Checksum is calculated from word values. */
10225 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10226 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10227 ASC_EEP_CMD_WRITE | addr);
10228 AdvWaitEEPCmd(iop_base);
b009bef6 10229 mdelay(ADV_EEP_DELAY_MS);
27c868c2 10230 }
1da177e4 10231
27c868c2
MW		 10232 /*
10233 * Write EEPROM checksum at word 21.
10234 */
10235 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum);
10236 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr);
10237 AdvWaitEEPCmd(iop_base);
10238 wbuf++;
10239 charfields++;
10240
10241 /*
10242 * Write EEPROM OEM name at words 22 to 29.
10243 */
10244 for (addr = ADV_EEP_DVC_CTL_BEGIN;
10245 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) {
10246 ushort word;
10247
10248 if (*charfields++) {
10249 word = cpu_to_le16(*wbuf);
10250 } else {
10251 word = *wbuf;
10252 }
10253 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word);
10254 AdvWriteWordRegister(iop_base, IOPW_EE_CMD,
10255 ASC_EEP_CMD_WRITE | addr);
10256 AdvWaitEEPCmd(iop_base);
10257 }
10258 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE);
10259 AdvWaitEEPCmd(iop_base);
1da177e4
LT		 10260}
10261
10262/*
51219358
MW		 10263 * Read EEPROM configuration into the specified buffer.
10264 *
10265 * Return a checksum based on the EEPROM configuration read.
1da177e4 10266 */
6f039790
GKH		 10267static ushort AdvGet3550EEPConfig(AdvPortAddr iop_base,
10268 ADVEEP_3550_CONFIG *cfg_buf)
1da177e4 10269{
51219358 10270 ushort wval, chksum;
27c868c2 10271 ushort *wbuf;
51219358 10272 int eep_addr;
27c868c2 10273 ushort *charfields;
27c868c2 10274
51219358 10275 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar;
27c868c2 10276 wbuf = (ushort *)cfg_buf;
27c868c2
MW		 10277 chksum = 0;
10278
51219358
MW		 10279 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10280 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10281 wval = AdvReadEEPWord(iop_base, eep_addr);
10282 chksum += wval; /* Checksum is calculated from word values. */
10283 if (*charfields++) {
10284 *wbuf = le16_to_cpu(wval);
10285 } else {
10286 *wbuf = wval;
10287 }
10288 }
10289 /* Read checksum word. */
10290 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10291 wbuf++;
10292 charfields++;
27c868c2 10293
51219358
MW		 10294 /* Read rest of EEPROM not covered by the checksum. */
10295 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10296 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10297 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
10298 if (*charfields++) {
10299 *wbuf = le16_to_cpu(*wbuf);
10300 }
10301 }
10302 return chksum;
10303}
10304
10305/*
10306 * Read EEPROM configuration into the specified buffer.
10307 *
10308 * Return a checksum based on the EEPROM configuration read.
10309 */
6f039790
GKH		 10310static ushort AdvGet38C0800EEPConfig(AdvPortAddr iop_base,
10311 ADVEEP_38C0800_CONFIG *cfg_buf)
51219358
MW		 10312{
10313 ushort wval, chksum;
10314 ushort *wbuf;
10315 int eep_addr;
10316 ushort *charfields;
27c868c2 10317
51219358
MW		 10318 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar;
10319 wbuf = (ushort *)cfg_buf;
10320 chksum = 0;
10321
10322 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10323 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10324 wval = AdvReadEEPWord(iop_base, eep_addr);
10325 chksum += wval; /* Checksum is calculated from word values. */
27c868c2 10326 if (*charfields++) {
51219358 10327 *wbuf = le16_to_cpu(wval);
27c868c2 10328 } else {
51219358 10329 *wbuf = wval;
27c868c2 10330 }
27c868c2 10331 }
51219358
MW		 10332 /* Read checksum word. */
10333 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2
MW		 10334 wbuf++;
10335 charfields++;
10336
51219358
MW		 10337 /* Read rest of EEPROM not covered by the checksum. */
10338 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10339 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10340 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2 10341 if (*charfields++) {
51219358 10342 *wbuf = le16_to_cpu(*wbuf);
27c868c2 10343 }
27c868c2 10344 }
51219358 10345 return chksum;
1da177e4
LT		 10346}
10347
10348/*
51219358
MW		 10349 * Read EEPROM configuration into the specified buffer.
10350 *
10351 * Return a checksum based on the EEPROM configuration read.
1da177e4 10352 */
6f039790
GKH		 10353static ushort AdvGet38C1600EEPConfig(AdvPortAddr iop_base,
10354 ADVEEP_38C1600_CONFIG *cfg_buf)
1da177e4 10355{
51219358 10356 ushort wval, chksum;
27c868c2 10357 ushort *wbuf;
51219358 10358 int eep_addr;
27c868c2 10359 ushort *charfields;
27c868c2 10360
27c868c2 10361 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar;
51219358 10362 wbuf = (ushort *)cfg_buf;
27c868c2
MW		 10363 chksum = 0;
10364
51219358
MW		 10365 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN;
10366 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) {
10367 wval = AdvReadEEPWord(iop_base, eep_addr);
10368 chksum += wval; /* Checksum is calculated from word values. */
27c868c2 10369 if (*charfields++) {
51219358 10370 *wbuf = le16_to_cpu(wval);
27c868c2 10371 } else {
51219358 10372 *wbuf = wval;
27c868c2 10373 }
27c868c2 10374 }
51219358
MW		 10375 /* Read checksum word. */
10376 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2
MW		 10377 wbuf++;
10378 charfields++;
10379
51219358
MW		 10380 /* Read rest of EEPROM not covered by the checksum. */
10381 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN;
10382 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) {
10383 *wbuf = AdvReadEEPWord(iop_base, eep_addr);
27c868c2 10384 if (*charfields++) {
51219358 10385 *wbuf = le16_to_cpu(*wbuf);
27c868c2 10386 }
27c868c2 10387 }
51219358 10388 return chksum;
1da177e4
LT		 10389}
10390
1da177e4 10391/*
51219358
MW		 10392 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10393 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10394 * all of this is done.
1da177e4 10395 *
51219358 10396 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 10397 *
51219358
MW		 10398 * For a non-fatal error return a warning code. If there are no warnings
10399 * then 0 is returned.
1da177e4 10400 *
51219358 10401 * Note: Chip is stopped on entry.
1da177e4 10402 */
6f039790 10403static int AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10404{
27c868c2 10405 AdvPortAddr iop_base;
51219358
MW		 10406 ushort warn_code;
10407 ADVEEP_3550_CONFIG eep_config;
1da177e4 10408
27c868c2 10409 iop_base = asc_dvc->iop_base;
1da177e4 10410
51219358 10411 warn_code = 0;
27c868c2
MW		 10412
10413 /*
51219358
MW		 10414 * Read the board's EEPROM configuration.
10415 *
10416 * Set default values if a bad checksum is found.
27c868c2 10417 */
51219358
MW		 10418 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) {
10419 warn_code |= ASC_WARN_EEPROM_CHKSUM;
27c868c2 10420
51219358
MW		 10421 /*
10422 * Set EEPROM default values.
10423 */
10424 memcpy(&eep_config, &Default_3550_EEPROM_Config,
10425 sizeof(ADVEEP_3550_CONFIG));
27c868c2 10426
51219358
MW		 10427 /*
10428 * Assume the 6 byte board serial number that was read from
10429 * EEPROM is correct even if the EEPROM checksum failed.
10430 */
10431 eep_config.serial_number_word3 =
10432 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
27c868c2 10433
51219358
MW		 10434 eep_config.serial_number_word2 =
10435 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
27c868c2 10436
51219358
MW		 10437 eep_config.serial_number_word1 =
10438 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
27c868c2 10439
51219358
MW		 10440 AdvSet3550EEPConfig(iop_base, &eep_config);
10441 }
10442 /*
10443 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10444 * EEPROM configuration that was read.
10445 *
10446 * This is the mapping of EEPROM fields to Adv Library fields.
10447 */
10448 asc_dvc->wdtr_able = eep_config.wdtr_able;
10449 asc_dvc->sdtr_able = eep_config.sdtr_able;
10450 asc_dvc->ultra_able = eep_config.ultra_able;
10451 asc_dvc->tagqng_able = eep_config.tagqng_able;
10452 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10453 asc_dvc->max_host_qng = eep_config.max_host_qng;
10454 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10455 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10456 asc_dvc->start_motor = eep_config.start_motor;
10457 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10458 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10459 asc_dvc->no_scam = eep_config.scam_tolerant;
10460 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10461 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10462 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
27c868c2 10463
27c868c2 10464 /*
51219358
MW		 10465 * Set the host maximum queuing (max. 253, min. 16) and the per device
10466 * maximum queuing (max. 63, min. 4).
27c868c2 10467 */
51219358
MW		 10468 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10469 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10470 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10471 /* If the value is zero, assume it is uninitialized. */
10472 if (eep_config.max_host_qng == 0) {
10473 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10474 } else {
10475 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10476 }
10477 }
10478
10479 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10480 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10481 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10482 /* If the value is zero, assume it is uninitialized. */
10483 if (eep_config.max_dvc_qng == 0) {
10484 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10485 } else {
10486 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10487 }
10488 }
27c868c2
MW		 10489
10490 /*
51219358
MW		 10491 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10492 * set 'max_dvc_qng' to 'max_host_qng'.
27c868c2 10493 */
51219358
MW		 10494 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10495 eep_config.max_dvc_qng = eep_config.max_host_qng;
10496 }
27c868c2
MW		 10497
10498 /*
51219358
MW		 10499 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10500 * values based on possibly adjusted EEPROM values.
27c868c2 10501 */
51219358
MW		 10502 asc_dvc->max_host_qng = eep_config.max_host_qng;
10503 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
27c868c2
MW		 10504
10505 /*
51219358
MW		 10506 * If the EEPROM 'termination' field is set to automatic (0), then set
10507 * the ADV_DVC_CFG 'termination' field to automatic also.
10508 *
10509 * If the termination is specified with a non-zero 'termination'
10510 * value check that a legal value is set and set the ADV_DVC_CFG
10511 * 'termination' field appropriately.
27c868c2 10512 */
51219358
MW		 10513 if (eep_config.termination == 0) {
10514 asc_dvc->cfg->termination = 0; /* auto termination */
10515 } else {
10516 /* Enable manual control with low off / high off. */
10517 if (eep_config.termination == 1) {
10518 asc_dvc->cfg->termination = TERM_CTL_SEL;
27c868c2 10519
51219358
MW		 10520 /* Enable manual control with low off / high on. */
10521 } else if (eep_config.termination == 2) {
10522 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H;
10523
10524 /* Enable manual control with low on / high on. */
10525 } else if (eep_config.termination == 3) {
10526 asc_dvc->cfg->termination =
10527 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L;
10528 } else {
27c868c2 10529 /*
51219358
MW		 10530 * The EEPROM 'termination' field contains a bad value. Use
10531 * automatic termination instead.
27c868c2 10532 */
51219358
MW		 10533 asc_dvc->cfg->termination = 0;
10534 warn_code |= ASC_WARN_EEPROM_TERMINATION;
27c868c2 10535 }
27c868c2 10536 }
1da177e4 10537
51219358 10538 return warn_code;
1da177e4
LT		 10539}
10540
10541/*
51219358
MW		 10542 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and
10543 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while
10544 * all of this is done.
1da177e4 10545 *
51219358
MW		 10546 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
10547 *
10548 * For a non-fatal error return a warning code. If there are no warnings
10549 * then 0 is returned.
10550 *
10551 * Note: Chip is stopped on entry.
1da177e4 10552 */
6f039790 10553static int AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10554{
51219358
MW		 10555 AdvPortAddr iop_base;
10556 ushort warn_code;
10557 ADVEEP_38C0800_CONFIG eep_config;
10558 uchar tid, termination;
10559 ushort sdtr_speed = 0;
27c868c2 10560
51219358 10561 iop_base = asc_dvc->iop_base;
1da177e4 10562
51219358 10563 warn_code = 0;
27c868c2
MW		 10564
10565 /*
51219358
MW		 10566 * Read the board's EEPROM configuration.
10567 *
10568 * Set default values if a bad checksum is found.
27c868c2 10569 */
51219358
MW		 10570 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) !=
10571 eep_config.check_sum) {
10572 warn_code |= ASC_WARN_EEPROM_CHKSUM;
27c868c2 10573
51219358
MW		 10574 /*
10575 * Set EEPROM default values.
10576 */
10577 memcpy(&eep_config, &Default_38C0800_EEPROM_Config,
10578 sizeof(ADVEEP_38C0800_CONFIG));
1da177e4 10579
51219358
MW		 10580 /*
10581 * Assume the 6 byte board serial number that was read from
10582 * EEPROM is correct even if the EEPROM checksum failed.
10583 */
10584 eep_config.serial_number_word3 =
10585 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
1da177e4 10586
51219358
MW		 10587 eep_config.serial_number_word2 =
10588 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
27c868c2 10589
51219358
MW		 10590 eep_config.serial_number_word1 =
10591 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
27c868c2 10592
51219358 10593 AdvSet38C0800EEPConfig(iop_base, &eep_config);
27c868c2 10594 }
27c868c2 10595 /*
51219358
MW		 10596 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the
10597 * EEPROM configuration that was read.
10598 *
10599 * This is the mapping of EEPROM fields to Adv Library fields.
27c868c2 10600 */
51219358
MW		 10601 asc_dvc->wdtr_able = eep_config.wdtr_able;
10602 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10603 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10604 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10605 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10606 asc_dvc->tagqng_able = eep_config.tagqng_able;
10607 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10608 asc_dvc->max_host_qng = eep_config.max_host_qng;
10609 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10610 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID);
10611 asc_dvc->start_motor = eep_config.start_motor;
10612 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10613 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10614 asc_dvc->no_scam = eep_config.scam_tolerant;
10615 asc_dvc->cfg->serial1 = eep_config.serial_number_word1;
10616 asc_dvc->cfg->serial2 = eep_config.serial_number_word2;
10617 asc_dvc->cfg->serial3 = eep_config.serial_number_word3;
27c868c2
MW		 10618
10619 /*
51219358
MW		 10620 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10621 * are set, then set an 'sdtr_able' bit for it.
27c868c2 10622 */
51219358
MW		 10623 asc_dvc->sdtr_able = 0;
10624 for (tid = 0; tid <= ADV_MAX_TID; tid++) {
10625 if (tid == 0) {
10626 sdtr_speed = asc_dvc->sdtr_speed1;
10627 } else if (tid == 4) {
10628 sdtr_speed = asc_dvc->sdtr_speed2;
10629 } else if (tid == 8) {
10630 sdtr_speed = asc_dvc->sdtr_speed3;
10631 } else if (tid == 12) {
10632 sdtr_speed = asc_dvc->sdtr_speed4;
10633 }
10634 if (sdtr_speed & ADV_MAX_TID) {
10635 asc_dvc->sdtr_able |= (1 << tid);
10636 }
10637 sdtr_speed >>= 4;
10638 }
27c868c2
MW		 10639
10640 /*
51219358
MW		 10641 * Set the host maximum queuing (max. 253, min. 16) and the per device
10642 * maximum queuing (max. 63, min. 4).
27c868c2 10643 */
51219358
MW		 10644 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10645 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10646 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10647 /* If the value is zero, assume it is uninitialized. */
10648 if (eep_config.max_host_qng == 0) {
10649 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10650 } else {
10651 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
10652 }
27c868c2 10653 }
1da177e4 10654
51219358
MW		 10655 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10656 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10657 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10658 /* If the value is zero, assume it is uninitialized. */
10659 if (eep_config.max_dvc_qng == 0) {
10660 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10661 } else {
10662 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10663 }
10664 }
10665
10666 /*
10667 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10668 * set 'max_dvc_qng' to 'max_host_qng'.
10669 */
10670 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10671 eep_config.max_dvc_qng = eep_config.max_host_qng;
27c868c2 10672 }
1da177e4 10673
27c868c2 10674 /*
51219358
MW		 10675 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng'
10676 * values based on possibly adjusted EEPROM values.
27c868c2 10677 */
51219358
MW		 10678 asc_dvc->max_host_qng = eep_config.max_host_qng;
10679 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
27c868c2
MW		 10680
10681 /*
51219358
MW		 10682 * If the EEPROM 'termination' field is set to automatic (0), then set
10683 * the ADV_DVC_CFG 'termination' field to automatic also.
10684 *
10685 * If the termination is specified with a non-zero 'termination'
10686 * value check that a legal value is set and set the ADV_DVC_CFG
10687 * 'termination' field appropriately.
27c868c2 10688 */
51219358
MW		 10689 if (eep_config.termination_se == 0) {
10690 termination = 0; /* auto termination for SE */
10691 } else {
10692 /* Enable manual control with low off / high off. */
10693 if (eep_config.termination_se == 1) {
10694 termination = 0;
10695
10696 /* Enable manual control with low off / high on. */
10697 } else if (eep_config.termination_se == 2) {
10698 termination = TERM_SE_HI;
10699
10700 /* Enable manual control with low on / high on. */
10701 } else if (eep_config.termination_se == 3) {
10702 termination = TERM_SE;
10703 } else {
10704 /*
10705 * The EEPROM 'termination_se' field contains a bad value.
10706 * Use automatic termination instead.
10707 */
10708 termination = 0;
10709 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10710 }
27c868c2 10711 }
51219358
MW		 10712
10713 if (eep_config.termination_lvd == 0) {
10714 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10715 } else {
10716 /* Enable manual control with low off / high off. */
10717 if (eep_config.termination_lvd == 1) {
10718 asc_dvc->cfg->termination = termination;
10719
10720 /* Enable manual control with low off / high on. */
10721 } else if (eep_config.termination_lvd == 2) {
10722 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
10723
10724 /* Enable manual control with low on / high on. */
10725 } else if (eep_config.termination_lvd == 3) {
10726 asc_dvc->cfg->termination = termination | TERM_LVD;
10727 } else {
10728 /*
10729 * The EEPROM 'termination_lvd' field contains a bad value.
10730 * Use automatic termination instead.
10731 */
10732 asc_dvc->cfg->termination = termination;
10733 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10734 }
27c868c2 10735 }
1da177e4 10736
51219358 10737 return warn_code;
1da177e4
LT		 10738}
10739
10740/*
51219358
MW		 10741 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and
10742 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while
10743 * all of this is done.
1da177e4 10744 *
51219358 10745 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 10746 *
51219358
MW		 10747 * For a non-fatal error return a warning code. If there are no warnings
10748 * then 0 is returned.
1da177e4 10749 *
51219358 10750 * Note: Chip is stopped on entry.
1da177e4 10751 */
6f039790 10752static int AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc)
1da177e4 10753{
27c868c2 10754 AdvPortAddr iop_base;
51219358
MW		 10755 ushort warn_code;
10756 ADVEEP_38C1600_CONFIG eep_config;
10757 uchar tid, termination;
10758 ushort sdtr_speed = 0;
1da177e4 10759
27c868c2
MW		 10760 iop_base = asc_dvc->iop_base;
10761
51219358 10762 warn_code = 0;
27c868c2 10763
51219358
MW		 10764 /*
10765 * Read the board's EEPROM configuration.
10766 *
10767 * Set default values if a bad checksum is found.
10768 */
10769 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) !=
10770 eep_config.check_sum) {
10771 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc);
10772 warn_code |= ASC_WARN_EEPROM_CHKSUM;
10773
10774 /*
10775 * Set EEPROM default values.
10776 */
10777 memcpy(&eep_config, &Default_38C1600_EEPROM_Config,
10778 sizeof(ADVEEP_38C1600_CONFIG));
10779
10780 if (PCI_FUNC(pdev->devfn) != 0) {
10781 u8 ints;
10782 /*
10783 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60
10784 * and old Mac system booting problem. The Expansion
10785 * ROM must be disabled in Function 1 for these systems
10786 */
10787 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE;
10788 /*
10789 * Clear the INTAB (bit 11) if the GPIO 0 input
10790 * indicates the Function 1 interrupt line is wired
10791 * to INTB.
10792 *
10793 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input:
10794 * 1 - Function 1 interrupt line wired to INT A.
10795 * 0 - Function 1 interrupt line wired to INT B.
10796 *
10797 * Note: Function 0 is always wired to INTA.
10798 * Put all 5 GPIO bits in input mode and then read
10799 * their input values.
10800 */
10801 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0);
10802 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA);
10803 if ((ints & 0x01) == 0)
10804 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB;
10805 }
10806
10807 /*
10808 * Assume the 6 byte board serial number that was read from
10809 * EEPROM is correct even if the EEPROM checksum failed.
10810 */
10811 eep_config.serial_number_word3 =
10812 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1);
10813 eep_config.serial_number_word2 =
10814 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2);
10815 eep_config.serial_number_word1 =
10816 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3);
10817
10818 AdvSet38C1600EEPConfig(iop_base, &eep_config);
27c868c2
MW		 10819 }
10820
10821 /*
51219358
MW		 10822 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the
10823 * EEPROM configuration that was read.
10824 *
10825 * This is the mapping of EEPROM fields to Adv Library fields.
27c868c2 10826 */
51219358
MW		 10827 asc_dvc->wdtr_able = eep_config.wdtr_able;
10828 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1;
10829 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2;
10830 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3;
10831 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4;
10832 asc_dvc->ppr_able = 0;
10833 asc_dvc->tagqng_able = eep_config.tagqng_able;
10834 asc_dvc->cfg->disc_enable = eep_config.disc_enable;
10835 asc_dvc->max_host_qng = eep_config.max_host_qng;
10836 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10837 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID);
10838 asc_dvc->start_motor = eep_config.start_motor;
10839 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay;
10840 asc_dvc->bios_ctrl = eep_config.bios_ctrl;
10841 asc_dvc->no_scam = eep_config.scam_tolerant;
27c868c2 10842
51219358
MW		 10843 /*
10844 * For every Target ID if any of its 'sdtr_speed[1234]' bits
10845 * are set, then set an 'sdtr_able' bit for it.
10846 */
10847 asc_dvc->sdtr_able = 0;
10848 for (tid = 0; tid <= ASC_MAX_TID; tid++) {
10849 if (tid == 0) {
10850 sdtr_speed = asc_dvc->sdtr_speed1;
10851 } else if (tid == 4) {
10852 sdtr_speed = asc_dvc->sdtr_speed2;
10853 } else if (tid == 8) {
10854 sdtr_speed = asc_dvc->sdtr_speed3;
10855 } else if (tid == 12) {
10856 sdtr_speed = asc_dvc->sdtr_speed4;
10857 }
10858 if (sdtr_speed & ASC_MAX_TID) {
10859 asc_dvc->sdtr_able |= (1 << tid);
10860 }
10861 sdtr_speed >>= 4;
10862 }
27c868c2 10863
51219358
MW		 10864 /*
10865 * Set the host maximum queuing (max. 253, min. 16) and the per device
10866 * maximum queuing (max. 63, min. 4).
10867 */
10868 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) {
10869 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10870 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) {
10871 /* If the value is zero, assume it is uninitialized. */
10872 if (eep_config.max_host_qng == 0) {
10873 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG;
10874 } else {
10875 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG;
27c868c2 10876 }
51219358 10877 }
27c868c2 10878
51219358
MW		 10879 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) {
10880 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10881 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) {
10882 /* If the value is zero, assume it is uninitialized. */
10883 if (eep_config.max_dvc_qng == 0) {
10884 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG;
10885 } else {
10886 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG;
10887 }
10888 }
10889
10890 /*
10891 * If 'max_dvc_qng' is greater than 'max_host_qng', then
10892 * set 'max_dvc_qng' to 'max_host_qng'.
10893 */
10894 if (eep_config.max_dvc_qng > eep_config.max_host_qng) {
10895 eep_config.max_dvc_qng = eep_config.max_host_qng;
27c868c2
MW		 10896 }
10897
10898 /*
51219358
MW		 10899 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng'
10900 * values based on possibly adjusted EEPROM values.
10901 */
10902 asc_dvc->max_host_qng = eep_config.max_host_qng;
10903 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng;
10904
10905 /*
10906 * If the EEPROM 'termination' field is set to automatic (0), then set
10907 * the ASC_DVC_CFG 'termination' field to automatic also.
10908 *
10909 * If the termination is specified with a non-zero 'termination'
10910 * value check that a legal value is set and set the ASC_DVC_CFG
10911 * 'termination' field appropriately.
27c868c2 10912 */
51219358
MW		 10913 if (eep_config.termination_se == 0) {
10914 termination = 0; /* auto termination for SE */
10915 } else {
10916 /* Enable manual control with low off / high off. */
10917 if (eep_config.termination_se == 1) {
10918 termination = 0;
27c868c2 10919
51219358
MW		 10920 /* Enable manual control with low off / high on. */
10921 } else if (eep_config.termination_se == 2) {
10922 termination = TERM_SE_HI;
27c868c2 10923
51219358
MW		 10924 /* Enable manual control with low on / high on. */
10925 } else if (eep_config.termination_se == 3) {
10926 termination = TERM_SE;
10927 } else {
10928 /*
10929 * The EEPROM 'termination_se' field contains a bad value.
10930 * Use automatic termination instead.
10931 */
10932 termination = 0;
10933 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10934 }
10935 }
27c868c2 10936
51219358
MW		 10937 if (eep_config.termination_lvd == 0) {
10938 asc_dvc->cfg->termination = termination; /* auto termination for LVD */
10939 } else {
10940 /* Enable manual control with low off / high off. */
10941 if (eep_config.termination_lvd == 1) {
10942 asc_dvc->cfg->termination = termination;
27c868c2 10943
51219358
MW		 10944 /* Enable manual control with low off / high on. */
10945 } else if (eep_config.termination_lvd == 2) {
10946 asc_dvc->cfg->termination = termination | TERM_LVD_HI;
27c868c2 10947
51219358
MW		 10948 /* Enable manual control with low on / high on. */
10949 } else if (eep_config.termination_lvd == 3) {
10950 asc_dvc->cfg->termination = termination | TERM_LVD;
10951 } else {
10952 /*
10953 * The EEPROM 'termination_lvd' field contains a bad value.
10954 * Use automatic termination instead.
10955 */
10956 asc_dvc->cfg->termination = termination;
10957 warn_code |= ASC_WARN_EEPROM_TERMINATION;
10958 }
27c868c2 10959 }
51219358
MW		 10960
10961 return warn_code;
1da177e4
LT		 10962}
10963
10964/*
51219358 10965 * Initialize the ADV_DVC_VAR structure.
1da177e4 10966 *
51219358 10967 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
1da177e4 10968 *
51219358
MW		 10969 * For a non-fatal error return a warning code. If there are no warnings
10970 * then 0 is returned.
1da177e4 10971 */
6f039790 10972static int AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost)
1da177e4 10973{
9d0e96eb
MW		 10974 struct asc_board *board = shost_priv(shost);
10975 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var;
51219358
MW		 10976 unsigned short warn_code = 0;
10977 AdvPortAddr iop_base = asc_dvc->iop_base;
10978 u16 cmd;
10979 int status;
27c868c2 10980
51219358 10981 asc_dvc->err_code = 0;
27c868c2
MW		 10982
10983 /*
51219358
MW		 10984 * Save the state of the PCI Configuration Command Register
10985 * "Parity Error Response Control" Bit. If the bit is clear (0),
10986 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore
10987 * DMA parity errors.
27c868c2 10988 */
51219358
MW		 10989 asc_dvc->cfg->control_flag = 0;
10990 pci_read_config_word(pdev, PCI_COMMAND, &cmd);
10991 if ((cmd & PCI_COMMAND_PARITY) == 0)
10992 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR;
27c868c2 10993
51219358
MW		 10994 asc_dvc->cfg->chip_version =
10995 AdvGetChipVersion(iop_base, asc_dvc->bus_type);
10996
b352f923 10997 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n",
51219358
MW		 10998 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1),
10999 (ushort)ADV_CHIP_ID_BYTE);
11000
b352f923 11001 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n",
51219358
MW		 11002 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0),
11003 (ushort)ADV_CHIP_ID_WORD);
27c868c2
MW		 11004
11005 /*
51219358 11006 * Reset the chip to start and allow register writes.
27c868c2 11007 */
51219358
MW		 11008 if (AdvFindSignature(iop_base) == 0) {
11009 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
11010 return ADV_ERROR;
11011 } else {
27c868c2 11012 /*
51219358 11013 * The caller must set 'chip_type' to a valid setting.
27c868c2 11014 */
51219358
MW		 11015 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 &&
11016 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 &&
11017 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) {
11018 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE;
11019 return ADV_ERROR;
11020 }
1da177e4 11021
51219358
MW		 11022 /*
11023 * Reset Chip.
11024 */
11025 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11026 ADV_CTRL_REG_CMD_RESET);
11027 mdelay(100);
11028 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG,
11029 ADV_CTRL_REG_CMD_WR_IO_REG);
11030
11031 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) {
11032 status = AdvInitFrom38C1600EEP(asc_dvc);
11033 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) {
11034 status = AdvInitFrom38C0800EEP(asc_dvc);
11035 } else {
11036 status = AdvInitFrom3550EEP(asc_dvc);
27c868c2 11037 }
51219358 11038 warn_code |= status;
27c868c2 11039 }
1da177e4 11040
9d0e96eb
MW		 11041 if (warn_code != 0)
11042 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code);
51219358 11043
9d0e96eb
MW		 11044 if (asc_dvc->err_code)
11045 shost_printk(KERN_ERR, shost, "error code 0x%x\n",
11046 asc_dvc->err_code);
51219358
MW		 11047
11048 return asc_dvc->err_code;
1da177e4 11049}
51219358
MW		 11050#endif
11051
11052static struct scsi_host_template advansys_template = {
11053 .proc_name = DRV_NAME,
11054#ifdef CONFIG_PROC_FS
b59fb6fd 11055 .show_info = advansys_show_info,
51219358
MW		 11056#endif
11057 .name = DRV_NAME,
11058 .info = advansys_info,
11059 .queuecommand = advansys_queuecommand,
eac0b0c7 11060 .eh_host_reset_handler = advansys_reset,
51219358
MW		 11061 .bios_param = advansys_biosparam,
11062 .slave_configure = advansys_slave_configure,
11063 /*
11064 * Because the driver may control an ISA adapter 'unchecked_isa_dma'
11065 * must be set. The flag will be cleared in advansys_board_found
11066 * for non-ISA adapters.
11067 */
ae26759e 11068 .unchecked_isa_dma = true,
51219358
MW		 11069 /*
11070 * All adapters controlled by this driver are capable of large
11071 * scatter-gather lists. According to the mid-level SCSI documentation
11072 * this obviates any performance gain provided by setting
11073 * 'use_clustering'. But empirically while CPU utilization is increased
11074 * by enabling clustering, I/O throughput increases as well.
11075 */
11076 .use_clustering = ENABLE_CLUSTERING,
9c17c62a 11077 .use_blk_tags = 1,
51219358 11078};
1da177e4 11079
6f039790 11080static int advansys_wide_init_chip(struct Scsi_Host *shost)
b2c16f58 11081{
9d0e96eb
MW		 11082 struct asc_board *board = shost_priv(shost);
11083 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
0ce53822 11084 size_t sgblk_pool_size;
b2c16f58
MW		 11085 int warn_code, err_code;
11086
11087 /*
11088 * Allocate buffer carrier structures. The total size
98b96a7d 11089 * is about 8 KB, so allocate all at once.
b2c16f58 11090 */
98b96a7d
HR		 11091 adv_dvc->carrier = dma_alloc_coherent(board->dev,
11092 ADV_CARRIER_BUFSIZE, &adv_dvc->carrier_addr, GFP_KERNEL);
11093 ASC_DBG(1, "carrier 0x%p\n", adv_dvc->carrier);
b2c16f58 11094
98b96a7d 11095 if (!adv_dvc->carrier)
b2c16f58
MW		 11096 goto kmalloc_failed;
11097
11098 /*
11099 * Allocate up to 'max_host_qng' request structures for the Wide
11100 * board. The total size is about 16 KB, so allocate all at once.
11101 * If the allocation fails decrement and try again.
11102 */
4b47e464
HR		 11103 board->adv_reqp_size = adv_dvc->max_host_qng * sizeof(adv_req_t);
11104 if (board->adv_reqp_size & 0x1f) {
11105 ASC_DBG(1, "unaligned reqp %lu bytes\n", sizeof(adv_req_t));
11106 board->adv_reqp_size = ADV_32BALIGN(board->adv_reqp_size);
b2c16f58 11107 }
4b47e464
HR		 11108 board->adv_reqp = dma_alloc_coherent(board->dev, board->adv_reqp_size,
11109 &board->adv_reqp_addr, GFP_KERNEL);
b2c16f58 11110
4b47e464 11111 if (!board->adv_reqp)
b2c16f58
MW		 11112 goto kmalloc_failed;
11113
4b47e464
HR		 11114 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", board->adv_reqp,
11115 adv_dvc->max_host_qng, board->adv_reqp_size);
b2c16f58
MW		 11116
11117 /*
11118 * Allocate up to ADV_TOT_SG_BLOCK request structures for
11119 * the Wide board. Each structure is about 136 bytes.
11120 */
0ce53822
HR		 11121 sgblk_pool_size = sizeof(adv_sgblk_t) * ADV_TOT_SG_BLOCK;
11122 board->adv_sgblk_pool = dma_pool_create("adv_sgblk", board->dev,
11123 sgblk_pool_size, 32, 0);
b2c16f58 11124
0ce53822
HR		 11125 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", ADV_TOT_SG_BLOCK,
11126 sizeof(adv_sgblk_t), sgblk_pool_size);
b2c16f58 11127
0ce53822 11128 if (!board->adv_sgblk_pool)
b2c16f58
MW		 11129 goto kmalloc_failed;
11130
9d0e96eb 11131 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) {
b352f923 11132 ASC_DBG(2, "AdvInitAsc3550Driver()\n");
9d0e96eb
MW		 11133 warn_code = AdvInitAsc3550Driver(adv_dvc);
11134 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) {
b352f923 11135 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n");
9d0e96eb 11136 warn_code = AdvInitAsc38C0800Driver(adv_dvc);
b2c16f58 11137 } else {
b352f923 11138 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n");
9d0e96eb 11139 warn_code = AdvInitAsc38C1600Driver(adv_dvc);
b2c16f58 11140 }
9d0e96eb 11141 err_code = adv_dvc->err_code;
b2c16f58
MW		 11142
11143 if (warn_code || err_code) {
9d0e96eb
MW		 11144 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error "
11145 "0x%x\n", warn_code, err_code);
b2c16f58
MW		 11146 }
11147
11148 goto exit;
11149
11150 kmalloc_failed:
9d0e96eb 11151 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n");
b2c16f58
MW		 11152 err_code = ADV_ERROR;
11153 exit:
11154 return err_code;
11155}
11156
98d41c29 11157static void advansys_wide_free_mem(struct asc_board *board)
b2c16f58 11158{
98d41c29 11159 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var;
98b96a7d
HR		 11160
11161 if (adv_dvc->carrier) {
11162 dma_free_coherent(board->dev, ADV_CARRIER_BUFSIZE,
11163 adv_dvc->carrier, adv_dvc->carrier_addr);
11164 adv_dvc->carrier = NULL;
11165 }
4b47e464
HR		 11166 if (board->adv_reqp) {
11167 dma_free_coherent(board->dev, board->adv_reqp_size,
11168 board->adv_reqp, board->adv_reqp_addr);
11169 board->adv_reqp = NULL;
11170 }
0ce53822
HR		 11171 if (board->adv_sgblk_pool) {
11172 dma_pool_destroy(board->adv_sgblk_pool);
11173 board->adv_sgblk_pool = NULL;
b2c16f58
MW		 11174 }
11175}
11176
6f039790
GKH		 11177static int advansys_board_found(struct Scsi_Host *shost, unsigned int iop,
11178 int bus_type)
27c868c2 11179{
d361db48 11180 struct pci_dev *pdev;
d2411495 11181 struct asc_board *boardp = shost_priv(shost);
27c868c2
MW		 11182 ASC_DVC_VAR *asc_dvc_varp = NULL;
11183 ADV_DVC_VAR *adv_dvc_varp = NULL;
d361db48 11184 int share_irq, warn_code, ret;
27c868c2 11185
d361db48 11186 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL;
27c868c2
MW		 11187
11188 if (ASC_NARROW_BOARD(boardp)) {
b352f923 11189 ASC_DBG(1, "narrow board\n");
27c868c2
MW		 11190 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
11191 asc_dvc_varp->bus_type = bus_type;
11192 asc_dvc_varp->drv_ptr = boardp;
11193 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg;
27c868c2 11194 asc_dvc_varp->iop_base = iop;
27c868c2 11195 } else {
57ba5fe9 11196#ifdef CONFIG_PCI
27c868c2
MW		 11197 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
11198 adv_dvc_varp->drv_ptr = boardp;
11199 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg;
27c868c2 11200 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) {
b352f923 11201 ASC_DBG(1, "wide board ASC-3550\n");
27c868c2
MW		 11202 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550;
11203 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) {
b352f923 11204 ASC_DBG(1, "wide board ASC-38C0800\n");
27c868c2
MW		 11205 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800;
11206 } else {
b352f923 11207 ASC_DBG(1, "wide board ASC-38C1600\n");
27c868c2
MW		 11208 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600;
11209 }
27c868c2 11210
57ba5fe9 11211 boardp->asc_n_io_port = pci_resource_len(pdev, 1);
25729a7f 11212 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1);
57ba5fe9 11213 if (!boardp->ioremap_addr) {
9d511a4b 11214 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) "
9d0e96eb 11215 "returned NULL\n",
9d511a4b 11216 (long)pci_resource_start(pdev, 1),
9d0e96eb 11217 boardp->asc_n_io_port);
d361db48 11218 ret = -ENODEV;
b2c16f58 11219 goto err_shost;
27c868c2 11220 }
b352f923
MW		 11221 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr;
11222 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base);
27c868c2
MW		 11223
11224 /*
11225 * Even though it isn't used to access wide boards, other
11226 * than for the debug line below, save I/O Port address so
11227 * that it can be reported.
11228 */
11229 boardp->ioport = iop;
11230
b352f923
MW		 11231 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n",
11232 (ushort)inp(iop + 1), (ushort)inpw(iop));
57ba5fe9 11233#endif /* CONFIG_PCI */
27c868c2
MW		 11234 }
11235
27c868c2 11236 if (ASC_NARROW_BOARD(boardp)) {
27c868c2
MW		 11237 /*
11238 * Set the board bus type and PCI IRQ before
11239 * calling AscInitGetConfig().
11240 */
11241 switch (asc_dvc_varp->bus_type) {
11242#ifdef CONFIG_ISA
11243 case ASC_IS_ISA:
ae26759e 11244 shost->unchecked_isa_dma = true;
074c8fe4 11245 share_irq = 0;
27c868c2
MW		 11246 break;
11247 case ASC_IS_VL:
ae26759e 11248 shost->unchecked_isa_dma = false;
074c8fe4 11249 share_irq = 0;
27c868c2
MW		 11250 break;
11251 case ASC_IS_EISA:
ae26759e 11252 shost->unchecked_isa_dma = false;
074c8fe4 11253 share_irq = IRQF_SHARED;
27c868c2
MW		 11254 break;
11255#endif /* CONFIG_ISA */
11256#ifdef CONFIG_PCI
11257 case ASC_IS_PCI:
ae26759e 11258 shost->unchecked_isa_dma = false;
074c8fe4 11259 share_irq = IRQF_SHARED;
27c868c2
MW		 11260 break;
11261#endif /* CONFIG_PCI */
11262 default:
9d0e96eb
MW		 11263 shost_printk(KERN_ERR, shost, "unknown adapter type: "
11264 "%d\n", asc_dvc_varp->bus_type);
ae26759e 11265 shost->unchecked_isa_dma = false;
074c8fe4 11266 share_irq = 0;
27c868c2
MW		 11267 break;
11268 }
27c868c2 11269
27c868c2
MW		 11270 /*
11271 * NOTE: AscInitGetConfig() may change the board's
11272 * bus_type value. The bus_type value should no
11273 * longer be used. If the bus_type field must be
11274 * referenced only use the bit-wise AND operator "&".
11275 */
b352f923 11276 ASC_DBG(2, "AscInitGetConfig()\n");
9d0e96eb 11277 ret = AscInitGetConfig(shost) ? -ENODEV : 0;
27c868c2 11278 } else {
c2dce2fa
MW		 11279#ifdef CONFIG_PCI
11280 /*
11281 * For Wide boards set PCI information before calling
11282 * AdvInitGetConfig().
11283 */
ae26759e 11284 shost->unchecked_isa_dma = false;
c2dce2fa 11285 share_irq = IRQF_SHARED;
b352f923 11286 ASC_DBG(2, "AdvInitGetConfig()\n");
394dbf3f 11287
9d0e96eb 11288 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0;
c2dce2fa 11289#endif /* CONFIG_PCI */
27c868c2
MW		 11290 }
11291
d361db48 11292 if (ret)
b59fb6fd 11293 goto err_unmap;
27c868c2
MW		 11294
11295 /*
11296 * Save the EEPROM configuration so that it can be displayed
11297 * from /proc/scsi/advansys/[0...].
11298 */
11299 if (ASC_NARROW_BOARD(boardp)) {
11300
11301 ASCEEP_CONFIG *ep;
11302
11303 /*
11304 * Set the adapter's target id bit in the 'init_tidmask' field.
11305 */
11306 boardp->init_tidmask |=
11307 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id);
11308
11309 /*
11310 * Save EEPROM settings for the board.
11311 */
11312 ep = &boardp->eep_config.asc_eep;
11313
11314 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable;
11315 ep->disc_enable = asc_dvc_varp->cfg->disc_enable;
11316 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled;
11317 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed);
11318 ep->start_motor = asc_dvc_varp->start_motor;
11319 ep->cntl = asc_dvc_varp->dvc_cntl;
11320 ep->no_scam = asc_dvc_varp->no_scam;
11321 ep->max_total_qng = asc_dvc_varp->max_total_qng;
11322 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id);
11323 /* 'max_tag_qng' is set to the same value for every device. */
11324 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0];
11325 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0];
11326 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1];
11327 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2];
11328 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3];
11329 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4];
11330 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5];
11331
11332 /*
11333 * Modify board configuration.
11334 */
b352f923 11335 ASC_DBG(2, "AscInitSetConfig()\n");
9d0e96eb 11336 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0;
d361db48 11337 if (ret)
b59fb6fd 11338 goto err_unmap;
27c868c2
MW		 11339 } else {
11340 ADVEEP_3550_CONFIG *ep_3550;
11341 ADVEEP_38C0800_CONFIG *ep_38C0800;
11342 ADVEEP_38C1600_CONFIG *ep_38C1600;
11343
11344 /*
11345 * Save Wide EEP Configuration Information.
11346 */
11347 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
11348 ep_3550 = &boardp->eep_config.adv_3550_eep;
11349
11350 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id;
11351 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng;
11352 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11353 ep_3550->termination = adv_dvc_varp->cfg->termination;
11354 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable;
11355 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl;
11356 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able;
11357 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able;
11358 ep_3550->ultra_able = adv_dvc_varp->ultra_able;
11359 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able;
11360 ep_3550->start_motor = adv_dvc_varp->start_motor;
11361 ep_3550->scsi_reset_delay =
11362 adv_dvc_varp->scsi_reset_wait;
11363 ep_3550->serial_number_word1 =
11364 adv_dvc_varp->cfg->serial1;
11365 ep_3550->serial_number_word2 =
11366 adv_dvc_varp->cfg->serial2;
11367 ep_3550->serial_number_word3 =
11368 adv_dvc_varp->cfg->serial3;
11369 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
11370 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
11371
11372 ep_38C0800->adapter_scsi_id =
11373 adv_dvc_varp->chip_scsi_id;
11374 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng;
11375 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11376 ep_38C0800->termination_lvd =
11377 adv_dvc_varp->cfg->termination;
11378 ep_38C0800->disc_enable =
11379 adv_dvc_varp->cfg->disc_enable;
11380 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl;
11381 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able;
11382 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11383 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11384 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11385 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11386 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11387 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able;
11388 ep_38C0800->start_motor = adv_dvc_varp->start_motor;
11389 ep_38C0800->scsi_reset_delay =
11390 adv_dvc_varp->scsi_reset_wait;
11391 ep_38C0800->serial_number_word1 =
11392 adv_dvc_varp->cfg->serial1;
11393 ep_38C0800->serial_number_word2 =
11394 adv_dvc_varp->cfg->serial2;
11395 ep_38C0800->serial_number_word3 =
11396 adv_dvc_varp->cfg->serial3;
11397 } else {
11398 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
11399
11400 ep_38C1600->adapter_scsi_id =
11401 adv_dvc_varp->chip_scsi_id;
11402 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng;
11403 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng;
11404 ep_38C1600->termination_lvd =
11405 adv_dvc_varp->cfg->termination;
11406 ep_38C1600->disc_enable =
11407 adv_dvc_varp->cfg->disc_enable;
11408 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl;
11409 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able;
11410 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11411 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1;
11412 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2;
11413 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3;
11414 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4;
11415 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able;
11416 ep_38C1600->start_motor = adv_dvc_varp->start_motor;
11417 ep_38C1600->scsi_reset_delay =
11418 adv_dvc_varp->scsi_reset_wait;
11419 ep_38C1600->serial_number_word1 =
11420 adv_dvc_varp->cfg->serial1;
11421 ep_38C1600->serial_number_word2 =
11422 adv_dvc_varp->cfg->serial2;
11423 ep_38C1600->serial_number_word3 =
11424 adv_dvc_varp->cfg->serial3;
11425 }
11426
11427 /*
11428 * Set the adapter's target id bit in the 'init_tidmask' field.
11429 */
11430 boardp->init_tidmask |=
11431 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id);
27c868c2
MW		 11432 }
11433
11434 /*
11435 * Channels are numbered beginning with 0. For AdvanSys one host
11436 * structure supports one channel. Multi-channel boards have a
11437 * separate host structure for each channel.
11438 */
11439 shost->max_channel = 0;
11440 if (ASC_NARROW_BOARD(boardp)) {
11441 shost->max_id = ASC_MAX_TID + 1;
11442 shost->max_lun = ASC_MAX_LUN + 1;
f05ec594 11443 shost->max_cmd_len = ASC_MAX_CDB_LEN;
27c868c2
MW		 11444
11445 shost->io_port = asc_dvc_varp->iop_base;
11446 boardp->asc_n_io_port = ASC_IOADR_GAP;
11447 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id;
11448
11449 /* Set maximum number of queues the adapter can handle. */
11450 shost->can_queue = asc_dvc_varp->max_total_qng;
11451 } else {
11452 shost->max_id = ADV_MAX_TID + 1;
11453 shost->max_lun = ADV_MAX_LUN + 1;
f05ec594 11454 shost->max_cmd_len = ADV_MAX_CDB_LEN;
27c868c2
MW		 11455
11456 /*
11457 * Save the I/O Port address and length even though
11458 * I/O ports are not used to access Wide boards.
11459 * Instead the Wide boards are accessed with
11460 * PCI Memory Mapped I/O.
11461 */
11462 shost->io_port = iop;
27c868c2
MW		 11463
11464 shost->this_id = adv_dvc_varp->chip_scsi_id;
11465
11466 /* Set maximum number of queues the adapter can handle. */
11467 shost->can_queue = adv_dvc_varp->max_host_qng;
11468 }
9c17c62a
HR		 11469 ret = scsi_init_shared_tag_map(shost, shost->can_queue);
11470 if (ret) {
11471 shost_printk(KERN_ERR, shost, "init tag map failed\n");
11472 goto err_free_dma;
11473 }
27c868c2 11474
27c868c2
MW		 11475 /*
11476 * Following v1.3.89, 'cmd_per_lun' is no longer needed
11477 * and should be set to zero.
11478 *
11479 * But because of a bug introduced in v1.3.89 if the driver is
11480 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level
11481 * SCSI function 'allocate_device' will panic. To allow the driver
11482 * to work as a module in these kernels set 'cmd_per_lun' to 1.
11483 *
11484 * Note: This is wrong. cmd_per_lun should be set to the depth
11485 * you want on untagged devices always.
11486 #ifdef MODULE
11487 */
11488 shost->cmd_per_lun = 1;
11489/* #else
11490 shost->cmd_per_lun = 0;
11491#endif */
11492
11493 /*
11494 * Set the maximum number of scatter-gather elements the
11495 * adapter can handle.
11496 */
11497 if (ASC_NARROW_BOARD(boardp)) {
11498 /*
11499 * Allow two commands with 'sg_tablesize' scatter-gather
11500 * elements to be executed simultaneously. This value is
11501 * the theoretical hardware limit. It may be decreased
11502 * below.
11503 */
11504 shost->sg_tablesize =
11505 (((asc_dvc_varp->max_total_qng - 2) / 2) *
11506 ASC_SG_LIST_PER_Q) + 1;
11507 } else {
11508 shost->sg_tablesize = ADV_MAX_SG_LIST;
11509 }
11510
11511 /*
11512 * The value of 'sg_tablesize' can not exceed the SCSI
11513 * mid-level driver definition of SG_ALL. SG_ALL also
11514 * must not be exceeded, because it is used to define the
11515 * size of the scatter-gather table in 'struct asc_sg_head'.
11516 */
11517 if (shost->sg_tablesize > SG_ALL) {
11518 shost->sg_tablesize = SG_ALL;
11519 }
11520
b352f923 11521 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize);
27c868c2
MW		 11522
11523 /* BIOS start address. */
11524 if (ASC_NARROW_BOARD(boardp)) {
b2c16f58
MW		 11525 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base,
11526 asc_dvc_varp->bus_type);
27c868c2
MW		 11527 } else {
11528 /*
11529 * Fill-in BIOS board variables. The Wide BIOS saves
11530 * information in LRAM that is used by the driver.
11531 */
11532 AdvReadWordLram(adv_dvc_varp->iop_base,
11533 BIOS_SIGNATURE, boardp->bios_signature);
11534 AdvReadWordLram(adv_dvc_varp->iop_base,
11535 BIOS_VERSION, boardp->bios_version);
11536 AdvReadWordLram(adv_dvc_varp->iop_base,
11537 BIOS_CODESEG, boardp->bios_codeseg);
11538 AdvReadWordLram(adv_dvc_varp->iop_base,
11539 BIOS_CODELEN, boardp->bios_codelen);
11540
b352f923 11541 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n",
27c868c2
MW		 11542 boardp->bios_signature, boardp->bios_version);
11543
b352f923 11544 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n",
27c868c2
MW		 11545 boardp->bios_codeseg, boardp->bios_codelen);
11546
11547 /*
11548 * If the BIOS saved a valid signature, then fill in
11549 * the BIOS code segment base address.
11550 */
11551 if (boardp->bios_signature == 0x55AA) {
11552 /*
11553 * Convert x86 realmode code segment to a linear
11554 * address by shifting left 4.
11555 */
11556 shost->base = ((ulong)boardp->bios_codeseg << 4);
11557 } else {
11558 shost->base = 0;
11559 }
11560 }
11561
11562 /*
11563 * Register Board Resources - I/O Port, DMA, IRQ
11564 */
11565
27c868c2
MW		 11566 /* Register DMA Channel for Narrow boards. */
11567 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */
11568#ifdef CONFIG_ISA
11569 if (ASC_NARROW_BOARD(boardp)) {
11570 /* Register DMA channel for ISA bus. */
11571 if (asc_dvc_varp->bus_type & ASC_IS_ISA) {
11572 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel;
01fbfe0b 11573 ret = request_dma(shost->dma_channel, DRV_NAME);
b2c16f58 11574 if (ret) {
9d0e96eb
MW		 11575 shost_printk(KERN_ERR, shost, "request_dma() "
11576 "%d failed %d\n",
11577 shost->dma_channel, ret);
b59fb6fd 11578 goto err_unmap;
27c868c2
MW		 11579 }
11580 AscEnableIsaDma(shost->dma_channel);
11581 }
11582 }
11583#endif /* CONFIG_ISA */
11584
11585 /* Register IRQ Number. */
b352f923 11586 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost);
074c8fe4 11587
d361db48 11588 ret = request_irq(boardp->irq, advansys_interrupt, share_irq,
01fbfe0b 11589 DRV_NAME, shost);
074c8fe4
MW		 11590
11591 if (ret) {
27c868c2 11592 if (ret == -EBUSY) {
9d0e96eb
MW		 11593 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11594 "already in use\n", boardp->irq);
27c868c2 11595 } else if (ret == -EINVAL) {
9d0e96eb
MW		 11596 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11597 "not valid\n", boardp->irq);
27c868c2 11598 } else {
9d0e96eb
MW		 11599 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x "
11600 "failed with %d\n", boardp->irq, ret);
27c868c2 11601 }
b2c16f58 11602 goto err_free_dma;
27c868c2
MW		 11603 }
11604
11605 /*
11606 * Initialize board RISC chip and enable interrupts.
11607 */
11608 if (ASC_NARROW_BOARD(boardp)) {
b352f923 11609 ASC_DBG(2, "AscInitAsc1000Driver()\n");
7d5d408c
FT		 11610
11611 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL);
11612 if (!asc_dvc_varp->overrun_buf) {
11613 ret = -ENOMEM;
9a908c1a 11614 goto err_free_irq;
7d5d408c 11615 }
27c868c2 11616 warn_code = AscInitAsc1000Driver(asc_dvc_varp);
27c868c2 11617
d361db48 11618 if (warn_code || asc_dvc_varp->err_code) {
9d0e96eb
MW		 11619 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, "
11620 "warn 0x%x, error 0x%x\n",
11621 asc_dvc_varp->init_state, warn_code,
11622 asc_dvc_varp->err_code);
9a908c1a 11623 if (!asc_dvc_varp->overrun_dma) {
d361db48 11624 ret = -ENODEV;
9a908c1a 11625 goto err_free_mem;
7d5d408c 11626 }
27c868c2
MW		 11627 }
11628 } else {
9a908c1a 11629 if (advansys_wide_init_chip(shost)) {
d361db48 11630 ret = -ENODEV;
9a908c1a
HRK		 11631 goto err_free_mem;
11632 }
27c868c2
MW		 11633 }
11634
27c868c2
MW		 11635 ASC_DBG_PRT_SCSI_HOST(2, shost);
11636
d361db48 11637 ret = scsi_add_host(shost, boardp->dev);
8dfb5379 11638 if (ret)
9a908c1a 11639 goto err_free_mem;
8dfb5379
MW		 11640
11641 scsi_scan_host(shost);
d361db48 11642 return 0;
b2c16f58 11643
9a908c1a
HRK		 11644 err_free_mem:
11645 if (ASC_NARROW_BOARD(boardp)) {
11646 if (asc_dvc_varp->overrun_dma)
11647 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma,
11648 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
11649 kfree(asc_dvc_varp->overrun_buf);
11650 } else
11651 advansys_wide_free_mem(boardp);
11652 err_free_irq:
d361db48 11653 free_irq(boardp->irq, shost);
b2c16f58 11654 err_free_dma:
30037818 11655#ifdef CONFIG_ISA
b2c16f58
MW		 11656 if (shost->dma_channel != NO_ISA_DMA)
11657 free_dma(shost->dma_channel);
30037818 11658#endif
b2c16f58
MW		 11659 err_unmap:
11660 if (boardp->ioremap_addr)
11661 iounmap(boardp->ioremap_addr);
11662 err_shost:
d361db48 11663 return ret;
27c868c2
MW		 11664}
11665
27c868c2
MW		 11666/*
11667 * advansys_release()
11668 *
11669 * Release resources allocated for a single AdvanSys adapter.
11670 */
11671static int advansys_release(struct Scsi_Host *shost)
11672{
d10fb2c7 11673 struct asc_board *board = shost_priv(shost);
b352f923 11674 ASC_DBG(1, "begin\n");
8dfb5379 11675 scsi_remove_host(shost);
d10fb2c7 11676 free_irq(board->irq, shost);
30037818 11677#ifdef CONFIG_ISA
27c868c2 11678 if (shost->dma_channel != NO_ISA_DMA) {
b352f923 11679 ASC_DBG(1, "free_dma()\n");
27c868c2
MW		 11680 free_dma(shost->dma_channel);
11681 }
30037818 11682#endif
d10fb2c7
MW		 11683 if (ASC_NARROW_BOARD(board)) {
11684 dma_unmap_single(board->dev,
11685 board->dvc_var.asc_dvc_var.overrun_dma,
11686 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
7d5d408c 11687 kfree(board->dvc_var.asc_dvc_var.overrun_buf);
d10fb2c7
MW		 11688 } else {
11689 iounmap(board->ioremap_addr);
11690 advansys_wide_free_mem(board);
27c868c2 11691 }
8dfb5379 11692 scsi_host_put(shost);
b352f923 11693 ASC_DBG(1, "end\n");
27c868c2
MW		 11694 return 0;
11695}
11696
95c9f162
MW		 11697#define ASC_IOADR_TABLE_MAX_IX 11
11698
747d016e 11699static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = {
c304ec94
MW		 11700 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190,
11701 0x0210, 0x0230, 0x0250, 0x0330
11702};
11703
d361db48
MW		 11704/*
11705 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as:
11706 * 00: 10
11707 * 01: 11
11708 * 10: 12
11709 * 11: 15
11710 */
6f039790 11711static unsigned int advansys_isa_irq_no(PortAddr iop_base)
d361db48
MW		 11712{
11713 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11714 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10;
11715 if (chip_irq == 13)
11716 chip_irq = 15;
11717 return chip_irq;
11718}
11719
6f039790 11720static int advansys_isa_probe(struct device *dev, unsigned int id)
c304ec94 11721{
d361db48 11722 int err = -ENODEV;
c304ec94
MW		 11723 PortAddr iop_base = _asc_def_iop_base[id];
11724 struct Scsi_Host *shost;
d361db48 11725 struct asc_board *board;
c304ec94 11726
01fbfe0b 11727 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
b352f923 11728 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
c304ec94
MW		 11729 return -ENODEV;
11730 }
b352f923 11731 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
c304ec94 11732 if (!AscFindSignature(iop_base))
d361db48 11733 goto release_region;
c304ec94 11734 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT))
d361db48 11735 goto release_region;
c304ec94 11736
d361db48
MW		 11737 err = -ENOMEM;
11738 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
c304ec94 11739 if (!shost)
d361db48
MW		 11740 goto release_region;
11741
d2411495 11742 board = shost_priv(shost);
d361db48
MW		 11743 board->irq = advansys_isa_irq_no(iop_base);
11744 board->dev = dev;
9c17c62a 11745 board->shost = shost;
d361db48
MW		 11746
11747 err = advansys_board_found(shost, iop_base, ASC_IS_ISA);
11748 if (err)
11749 goto free_host;
c304ec94
MW		 11750
11751 dev_set_drvdata(dev, shost);
11752 return 0;
11753
d361db48
MW		 11754 free_host:
11755 scsi_host_put(shost);
11756 release_region:
71f36115 11757 release_region(iop_base, ASC_IOADR_GAP);
d361db48 11758 return err;
c304ec94
MW		 11759}
11760
6f039790 11761static int advansys_isa_remove(struct device *dev, unsigned int id)
c304ec94 11762{
71f36115 11763 int ioport = _asc_def_iop_base[id];
c304ec94 11764 advansys_release(dev_get_drvdata(dev));
71f36115 11765 release_region(ioport, ASC_IOADR_GAP);
c304ec94
MW		 11766 return 0;
11767}
11768
11769static struct isa_driver advansys_isa_driver = {
11770 .probe = advansys_isa_probe,
6f039790 11771 .remove = advansys_isa_remove,
c304ec94
MW		 11772 .driver = {
11773 .owner = THIS_MODULE,
01fbfe0b 11774 .name = DRV_NAME,
c304ec94
MW		 11775 },
11776};
11777
d361db48
MW		 11778/*
11779 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as:
11780 * 000: invalid
11781 * 001: 10
11782 * 010: 11
11783 * 011: 12
11784 * 100: invalid
11785 * 101: 14
11786 * 110: 15
11787 * 111: invalid
11788 */
6f039790 11789static unsigned int advansys_vlb_irq_no(PortAddr iop_base)
d361db48
MW		 11790{
11791 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base);
11792 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9;
11793 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15))
11794 return 0;
11795 return chip_irq;
11796}
11797
6f039790 11798static int advansys_vlb_probe(struct device *dev, unsigned int id)
c304ec94 11799{
d361db48 11800 int err = -ENODEV;
c304ec94
MW		 11801 PortAddr iop_base = _asc_def_iop_base[id];
11802 struct Scsi_Host *shost;
d361db48 11803 struct asc_board *board;
c304ec94 11804
01fbfe0b 11805 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) {
b352f923 11806 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base);
c304ec94
MW		 11807 return -ENODEV;
11808 }
b352f923 11809 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base);
c304ec94 11810 if (!AscFindSignature(iop_base))
d361db48 11811 goto release_region;
c304ec94
MW		 11812 /*
11813 * I don't think this condition can actually happen, but the old
11814 * driver did it, and the chances of finding a VLB setup in 2007
11815 * to do testing with is slight to none.
11816 */
11817 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL)
d361db48 11818 goto release_region;
c304ec94 11819
d361db48
MW		 11820 err = -ENOMEM;
11821 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
c304ec94 11822 if (!shost)
d361db48
MW		 11823 goto release_region;
11824
d2411495 11825 board = shost_priv(shost);
d361db48
MW		 11826 board->irq = advansys_vlb_irq_no(iop_base);
11827 board->dev = dev;
9c17c62a 11828 board->shost = shost;
d361db48
MW		 11829
11830 err = advansys_board_found(shost, iop_base, ASC_IS_VL);
11831 if (err)
11832 goto free_host;
c304ec94
MW		 11833
11834 dev_set_drvdata(dev, shost);
11835 return 0;
11836
d361db48
MW		 11837 free_host:
11838 scsi_host_put(shost);
11839 release_region:
71f36115 11840 release_region(iop_base, ASC_IOADR_GAP);
c304ec94
MW		 11841 return -ENODEV;
11842}
11843
11844static struct isa_driver advansys_vlb_driver = {
11845 .probe = advansys_vlb_probe,
6f039790 11846 .remove = advansys_isa_remove,
c304ec94
MW		 11847 .driver = {
11848 .owner = THIS_MODULE,
b8e5152b 11849 .name = "advansys_vlb",
c304ec94
MW		 11850 },
11851};
11852
6f039790 11853static struct eisa_device_id advansys_eisa_table[] = {
b09e05a7
MW		 11854 { "ABP7401" },
11855 { "ABP7501" },
11856 { "" }
11857};
11858
11859MODULE_DEVICE_TABLE(eisa, advansys_eisa_table);
11860
11861/*
11862 * EISA is a little more tricky than PCI; each EISA device may have two
11863 * channels, and this driver is written to make each channel its own Scsi_Host
11864 */
11865struct eisa_scsi_data {
11866 struct Scsi_Host *host[2];
11867};
11868
d361db48
MW		 11869/*
11870 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as:
11871 * 000: 10
11872 * 001: 11
11873 * 010: 12
11874 * 011: invalid
11875 * 100: 14
11876 * 101: 15
11877 * 110: invalid
11878 * 111: invalid
11879 */
6f039790 11880static unsigned int advansys_eisa_irq_no(struct eisa_device *edev)
d361db48
MW		 11881{
11882 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86);
11883 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10;
11884 if ((chip_irq == 13) || (chip_irq > 15))
11885 return 0;
11886 return chip_irq;
11887}
11888
6f039790 11889static int advansys_eisa_probe(struct device *dev)
b09e05a7 11890{
d361db48 11891 int i, ioport, irq = 0;
b09e05a7
MW		 11892 int err;
11893 struct eisa_device *edev = to_eisa_device(dev);
11894 struct eisa_scsi_data *data;
11895
11896 err = -ENOMEM;
11897 data = kzalloc(sizeof(*data), GFP_KERNEL);
11898 if (!data)
11899 goto fail;
11900 ioport = edev->base_addr + 0xc30;
11901
11902 err = -ENODEV;
11903 for (i = 0; i < 2; i++, ioport += 0x20) {
d361db48
MW		 11904 struct asc_board *board;
11905 struct Scsi_Host *shost;
01fbfe0b 11906 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) {
71f36115
MW		 11907 printk(KERN_WARNING "Region %x-%x busy\n", ioport,
11908 ioport + ASC_IOADR_GAP - 1);
11909 continue;
11910 }
11911 if (!AscFindSignature(ioport)) {
11912 release_region(ioport, ASC_IOADR_GAP);
b09e05a7 11913 continue;
71f36115
MW		 11914 }
11915
b09e05a7
MW		 11916 /*
11917 * I don't know why we need to do this for EISA chips, but
11918 * not for any others. It looks to be equivalent to
11919 * AscGetChipCfgMsw, but I may have overlooked something,
11920 * so I'm not converting it until I get an EISA board to
11921 * test with.
11922 */
11923 inw(ioport + 4);
d361db48
MW		 11924
11925 if (!irq)
11926 irq = advansys_eisa_irq_no(edev);
11927
11928 err = -ENOMEM;
11929 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
11930 if (!shost)
11931 goto release_region;
11932
d2411495 11933 board = shost_priv(shost);
d361db48
MW		 11934 board->irq = irq;
11935 board->dev = dev;
9c17c62a 11936 board->shost = shost;
d361db48
MW		 11937
11938 err = advansys_board_found(shost, ioport, ASC_IS_EISA);
11939 if (!err) {
11940 data->host[i] = shost;
11941 continue;
71f36115 11942 }
b09e05a7 11943
d361db48
MW		 11944 scsi_host_put(shost);
11945 release_region:
11946 release_region(ioport, ASC_IOADR_GAP);
11947 break;
b09e05a7
MW		 11948 }
11949
d361db48
MW		 11950 if (err)
11951 goto free_data;
11952 dev_set_drvdata(dev, data);
11953 return 0;
11954
11955 free_data:
11956 kfree(data->host[0]);
11957 kfree(data->host[1]);
11958 kfree(data);
b09e05a7
MW		 11959 fail:
11960 return err;
11961}
11962
6f039790 11963static int advansys_eisa_remove(struct device *dev)
b09e05a7
MW		 11964{
11965 int i;
11966 struct eisa_scsi_data *data = dev_get_drvdata(dev);
11967
11968 for (i = 0; i < 2; i++) {
71f36115 11969 int ioport;
b09e05a7
MW		 11970 struct Scsi_Host *shost = data->host[i];
11971 if (!shost)
11972 continue;
71f36115 11973 ioport = shost->io_port;
b09e05a7 11974 advansys_release(shost);
71f36115 11975 release_region(ioport, ASC_IOADR_GAP);
b09e05a7
MW		 11976 }
11977
11978 kfree(data);
11979 return 0;
11980}
11981
11982static struct eisa_driver advansys_eisa_driver = {
11983 .id_table = advansys_eisa_table,
11984 .driver = {
01fbfe0b 11985 .name = DRV_NAME,
b09e05a7 11986 .probe = advansys_eisa_probe,
6f039790 11987 .remove = advansys_eisa_remove,
b09e05a7
MW		 11988 }
11989};
11990
2672ea86 11991/* PCI Devices supported by this driver */
6f039790 11992static struct pci_device_id advansys_pci_tbl[] = {
27c868c2
MW		 11993 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A,
11994 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11995 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940,
11996 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11997 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U,
11998 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
11999 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW,
12000 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12001 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1,
12002 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12003 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1,
12004 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
12005 {}
2672ea86 12006};
27c868c2 12007
2672ea86 12008MODULE_DEVICE_TABLE(pci, advansys_pci_tbl);
78e77d8b 12009
6f039790 12010static void advansys_set_latency(struct pci_dev *pdev)
9649af39
MW		 12011{
12012 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) ||
12013 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) {
12014 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0);
12015 } else {
12016 u8 latency;
12017 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency);
12018 if (latency < 0x20)
12019 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20);
12020 }
12021}
12022
6f039790
GKH		 12023static int advansys_pci_probe(struct pci_dev *pdev,
12024 const struct pci_device_id *ent)
78e77d8b
MW		 12025{
12026 int err, ioport;
12027 struct Scsi_Host *shost;
d361db48 12028 struct asc_board *board;
78e77d8b
MW		 12029
12030 err = pci_enable_device(pdev);
12031 if (err)
12032 goto fail;
01fbfe0b 12033 err = pci_request_regions(pdev, DRV_NAME);
71f36115
MW		 12034 if (err)
12035 goto disable_device;
9649af39
MW		 12036 pci_set_master(pdev);
12037 advansys_set_latency(pdev);
78e77d8b 12038
d361db48 12039 err = -ENODEV;
78e77d8b 12040 if (pci_resource_len(pdev, 0) == 0)
d361db48 12041 goto release_region;
78e77d8b
MW		 12042
12043 ioport = pci_resource_start(pdev, 0);
78e77d8b 12044
d361db48
MW		 12045 err = -ENOMEM;
12046 shost = scsi_host_alloc(&advansys_template, sizeof(*board));
78e77d8b 12047 if (!shost)
d361db48
MW		 12048 goto release_region;
12049
d2411495 12050 board = shost_priv(shost);
d361db48
MW		 12051 board->irq = pdev->irq;
12052 board->dev = &pdev->dev;
9c17c62a 12053 board->shost = shost;
d361db48
MW		 12054
12055 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW ||
12056 pdev->device == PCI_DEVICE_ID_38C0800_REV1 ||
12057 pdev->device == PCI_DEVICE_ID_38C1600_REV1) {
12058 board->flags |= ASC_IS_WIDE_BOARD;
12059 }
12060
12061 err = advansys_board_found(shost, ioport, ASC_IS_PCI);
12062 if (err)
12063 goto free_host;
78e77d8b
MW		 12064
12065 pci_set_drvdata(pdev, shost);
12066 return 0;
12067
d361db48
MW		 12068 free_host:
12069 scsi_host_put(shost);
12070 release_region:
71f36115
MW		 12071 pci_release_regions(pdev);
12072 disable_device:
78e77d8b
MW		 12073 pci_disable_device(pdev);
12074 fail:
12075 return err;
12076}
12077
6f039790 12078static void advansys_pci_remove(struct pci_dev *pdev)
78e77d8b
MW		 12079{
12080 advansys_release(pci_get_drvdata(pdev));
71f36115 12081 pci_release_regions(pdev);
78e77d8b
MW		 12082 pci_disable_device(pdev);
12083}
12084
12085static struct pci_driver advansys_pci_driver = {
01fbfe0b 12086 .name = DRV_NAME,
78e77d8b
MW		 12087 .id_table = advansys_pci_tbl,
12088 .probe = advansys_pci_probe,
6f039790 12089 .remove = advansys_pci_remove,
78e77d8b 12090};
8c6af9e1 12091
8dfb5379
MW		 12092static int __init advansys_init(void)
12093{
c304ec94 12094 int error;
b09e05a7 12095
c304ec94
MW		 12096 error = isa_register_driver(&advansys_isa_driver,
12097 ASC_IOADR_TABLE_MAX_IX);
78e77d8b
MW		 12098 if (error)
12099 goto fail;
8dfb5379 12100
c304ec94
MW		 12101 error = isa_register_driver(&advansys_vlb_driver,
12102 ASC_IOADR_TABLE_MAX_IX);
12103 if (error)
12104 goto unregister_isa;
12105
12106 error = eisa_driver_register(&advansys_eisa_driver);
12107 if (error)
12108 goto unregister_vlb;
12109
b09e05a7
MW		 12110 error = pci_register_driver(&advansys_pci_driver);
12111 if (error)
12112 goto unregister_eisa;
12113
8dfb5379 12114 return 0;
78e77d8b 12115
b09e05a7
MW		 12116 unregister_eisa:
12117 eisa_driver_unregister(&advansys_eisa_driver);
c304ec94
MW		 12118 unregister_vlb:
12119 isa_unregister_driver(&advansys_vlb_driver);
12120 unregister_isa:
12121 isa_unregister_driver(&advansys_isa_driver);
78e77d8b 12122 fail:
78e77d8b 12123 return error;
8dfb5379
MW		 12124}
12125
12126static void __exit advansys_exit(void)
12127{
78e77d8b 12128 pci_unregister_driver(&advansys_pci_driver);
b09e05a7 12129 eisa_driver_unregister(&advansys_eisa_driver);
c304ec94
MW		 12130 isa_unregister_driver(&advansys_vlb_driver);
12131 isa_unregister_driver(&advansys_isa_driver);
8dfb5379
MW		 12132}
12133
12134module_init(advansys_init);
12135module_exit(advansys_exit);
12136
8c6af9e1 12137MODULE_LICENSE("GPL");
989bb5f5
JSR		 12138MODULE_FIRMWARE("advansys/mcode.bin");
12139MODULE_FIRMWARE("advansys/3550.bin");
12140MODULE_FIRMWARE("advansys/38C0800.bin");
12141MODULE_FIRMWARE("advansys/38C1600.bin");
Linux 6.x block layer and io_uring tree(s)