Commit | Line | Data |
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e8b12f0f MR |
1 | /* |
2 | * Adaptec AAC series RAID controller driver | |
3 | * (c) Copyright 2001 Red Hat Inc. | |
4 | * | |
5 | * based on the old aacraid driver that is.. | |
6 | * Adaptec aacraid device driver for Linux. | |
7 | * | |
8 | * Copyright (c) 2000-2010 Adaptec, Inc. | |
9 | * 2010 PMC-Sierra, Inc. (aacraid@pmc-sierra.com) | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * Module Name: | |
26 | * src.c | |
27 | * | |
28 | * Abstract: Hardware Device Interface for PMC SRC based controllers | |
29 | * | |
30 | */ | |
31 | ||
32 | #include <linux/kernel.h> | |
33 | #include <linux/init.h> | |
34 | #include <linux/types.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/spinlock.h> | |
37 | #include <linux/slab.h> | |
38 | #include <linux/blkdev.h> | |
39 | #include <linux/delay.h> | |
e8b12f0f MR |
40 | #include <linux/completion.h> |
41 | #include <linux/time.h> | |
42 | #include <linux/interrupt.h> | |
43 | #include <scsi/scsi_host.h> | |
44 | ||
45 | #include "aacraid.h" | |
46 | ||
495c0217 MR |
47 | static int aac_src_get_sync_status(struct aac_dev *dev); |
48 | ||
305974fe | 49 | static irqreturn_t aac_src_intr_message(int irq, void *dev_id) |
e8b12f0f | 50 | { |
495c0217 MR |
51 | struct aac_msix_ctx *ctx; |
52 | struct aac_dev *dev; | |
e8b12f0f | 53 | unsigned long bellbits, bellbits_shifted; |
495c0217 MR |
54 | int vector_no; |
55 | int isFastResponse, mode; | |
e8b12f0f MR |
56 | u32 index, handle; |
57 | ||
495c0217 MR |
58 | ctx = (struct aac_msix_ctx *)dev_id; |
59 | dev = ctx->dev; | |
60 | vector_no = ctx->vector_no; | |
61 | ||
62 | if (dev->msi_enabled) { | |
63 | mode = AAC_INT_MODE_MSI; | |
64 | if (vector_no == 0) { | |
65 | bellbits = src_readl(dev, MUnit.ODR_MSI); | |
66 | if (bellbits & 0x40000) | |
67 | mode |= AAC_INT_MODE_AIF; | |
68 | if (bellbits & 0x1000) | |
69 | mode |= AAC_INT_MODE_SYNC; | |
e8b12f0f MR |
70 | } |
71 | } else { | |
495c0217 MR |
72 | mode = AAC_INT_MODE_INTX; |
73 | bellbits = src_readl(dev, MUnit.ODR_R); | |
74 | if (bellbits & PmDoorBellResponseSent) { | |
75 | bellbits = PmDoorBellResponseSent; | |
76 | src_writel(dev, MUnit.ODR_C, bellbits); | |
77 | src_readl(dev, MUnit.ODR_C); | |
78 | } else { | |
79 | bellbits_shifted = (bellbits >> SRC_ODR_SHIFT); | |
85d22bbf MR |
80 | src_writel(dev, MUnit.ODR_C, bellbits); |
81 | src_readl(dev, MUnit.ODR_C); | |
85d22bbf | 82 | |
495c0217 MR |
83 | if (bellbits_shifted & DoorBellAifPending) |
84 | mode |= AAC_INT_MODE_AIF; | |
85 | else if (bellbits_shifted & OUTBOUNDDOORBELL_0) | |
86 | mode |= AAC_INT_MODE_SYNC; | |
87 | } | |
88 | } | |
89 | ||
90 | if (mode & AAC_INT_MODE_SYNC) { | |
91 | unsigned long sflags; | |
92 | struct list_head *entry; | |
93 | int send_it = 0; | |
94 | extern int aac_sync_mode; | |
95 | ||
96 | if (!aac_sync_mode && !dev->msi_enabled) { | |
c5bebd82 MR |
97 | src_writel(dev, MUnit.ODR_C, bellbits); |
98 | src_readl(dev, MUnit.ODR_C); | |
495c0217 | 99 | } |
c5bebd82 | 100 | |
495c0217 MR |
101 | if (dev->sync_fib) { |
102 | if (dev->sync_fib->callback) | |
103 | dev->sync_fib->callback(dev->sync_fib->callback_data, | |
104 | dev->sync_fib); | |
105 | spin_lock_irqsave(&dev->sync_fib->event_lock, sflags); | |
106 | if (dev->sync_fib->flags & FIB_CONTEXT_FLAG_WAIT) { | |
107 | dev->management_fib_count--; | |
108 | up(&dev->sync_fib->event_wait); | |
85d22bbf | 109 | } |
495c0217 MR |
110 | spin_unlock_irqrestore(&dev->sync_fib->event_lock, |
111 | sflags); | |
112 | spin_lock_irqsave(&dev->sync_lock, sflags); | |
113 | if (!list_empty(&dev->sync_fib_list)) { | |
114 | entry = dev->sync_fib_list.next; | |
115 | dev->sync_fib = list_entry(entry, | |
116 | struct fib, | |
117 | fiblink); | |
118 | list_del(entry); | |
119 | send_it = 1; | |
120 | } else { | |
121 | dev->sync_fib = NULL; | |
122 | } | |
123 | spin_unlock_irqrestore(&dev->sync_lock, sflags); | |
124 | if (send_it) { | |
125 | aac_adapter_sync_cmd(dev, SEND_SYNCHRONOUS_FIB, | |
126 | (u32)dev->sync_fib->hw_fib_pa, | |
127 | 0, 0, 0, 0, 0, | |
128 | NULL, NULL, NULL, NULL, NULL); | |
11604612 | 129 | } |
e8b12f0f | 130 | } |
495c0217 MR |
131 | if (!dev->msi_enabled) |
132 | mode = 0; | |
133 | ||
e8b12f0f MR |
134 | } |
135 | ||
495c0217 MR |
136 | if (mode & AAC_INT_MODE_AIF) { |
137 | /* handle AIF */ | |
3ffd6c5a RAR |
138 | if (dev->sa_firmware) { |
139 | u32 events = src_readl(dev, MUnit.SCR0); | |
140 | ||
141 | aac_intr_normal(dev, events, 1, 0, NULL); | |
142 | writel(events, &dev->IndexRegs->Mailbox[0]); | |
143 | src_writel(dev, MUnit.IDR, 1 << 23); | |
144 | } else { | |
145 | if (dev->aif_thread && dev->fsa_dev) | |
146 | aac_intr_normal(dev, 0, 2, 0, NULL); | |
147 | } | |
495c0217 MR |
148 | if (dev->msi_enabled) |
149 | aac_src_access_devreg(dev, AAC_CLEAR_AIF_BIT); | |
150 | mode = 0; | |
e8b12f0f | 151 | } |
495c0217 MR |
152 | |
153 | if (mode) { | |
154 | index = dev->host_rrq_idx[vector_no]; | |
155 | ||
156 | for (;;) { | |
157 | isFastResponse = 0; | |
158 | /* remove toggle bit (31) */ | |
3ffd6c5a RAR |
159 | handle = le32_to_cpu((dev->host_rrq[index]) |
160 | & 0x7fffffff); | |
161 | /* check fast response bits (30, 1) */ | |
495c0217 MR |
162 | if (handle & 0x40000000) |
163 | isFastResponse = 1; | |
164 | handle &= 0x0000ffff; | |
165 | if (handle == 0) | |
166 | break; | |
3ffd6c5a | 167 | handle >>= 2; |
495c0217 MR |
168 | if (dev->msi_enabled && dev->max_msix > 1) |
169 | atomic_dec(&dev->rrq_outstanding[vector_no]); | |
3ffd6c5a | 170 | aac_intr_normal(dev, handle, 0, isFastResponse, NULL); |
495c0217 MR |
171 | dev->host_rrq[index++] = 0; |
172 | if (index == (vector_no + 1) * dev->vector_cap) | |
173 | index = vector_no * dev->vector_cap; | |
174 | dev->host_rrq_idx[vector_no] = index; | |
175 | } | |
176 | mode = 0; | |
177 | } | |
178 | ||
179 | return IRQ_HANDLED; | |
e8b12f0f MR |
180 | } |
181 | ||
182 | /** | |
183 | * aac_src_disable_interrupt - Disable interrupts | |
184 | * @dev: Adapter | |
185 | */ | |
186 | ||
187 | static void aac_src_disable_interrupt(struct aac_dev *dev) | |
188 | { | |
189 | src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff); | |
190 | } | |
191 | ||
192 | /** | |
193 | * aac_src_enable_interrupt_message - Enable interrupts | |
194 | * @dev: Adapter | |
195 | */ | |
196 | ||
197 | static void aac_src_enable_interrupt_message(struct aac_dev *dev) | |
198 | { | |
495c0217 | 199 | aac_src_access_devreg(dev, AAC_ENABLE_INTERRUPT); |
e8b12f0f MR |
200 | } |
201 | ||
202 | /** | |
203 | * src_sync_cmd - send a command and wait | |
204 | * @dev: Adapter | |
205 | * @command: Command to execute | |
206 | * @p1: first parameter | |
207 | * @ret: adapter status | |
208 | * | |
209 | * This routine will send a synchronous command to the adapter and wait | |
210 | * for its completion. | |
211 | */ | |
212 | ||
213 | static int src_sync_cmd(struct aac_dev *dev, u32 command, | |
214 | u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, | |
215 | u32 *status, u32 * r1, u32 * r2, u32 * r3, u32 * r4) | |
216 | { | |
217 | unsigned long start; | |
dafde947 | 218 | unsigned long delay; |
e8b12f0f MR |
219 | int ok; |
220 | ||
221 | /* | |
222 | * Write the command into Mailbox 0 | |
223 | */ | |
224 | writel(command, &dev->IndexRegs->Mailbox[0]); | |
225 | /* | |
226 | * Write the parameters into Mailboxes 1 - 6 | |
227 | */ | |
228 | writel(p1, &dev->IndexRegs->Mailbox[1]); | |
229 | writel(p2, &dev->IndexRegs->Mailbox[2]); | |
230 | writel(p3, &dev->IndexRegs->Mailbox[3]); | |
231 | writel(p4, &dev->IndexRegs->Mailbox[4]); | |
232 | ||
233 | /* | |
234 | * Clear the synch command doorbell to start on a clean slate. | |
235 | */ | |
495c0217 MR |
236 | if (!dev->msi_enabled) |
237 | src_writel(dev, | |
238 | MUnit.ODR_C, | |
239 | OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT); | |
e8b12f0f MR |
240 | |
241 | /* | |
242 | * Disable doorbell interrupts | |
243 | */ | |
244 | src_writel(dev, MUnit.OIMR, dev->OIMR = 0xffffffff); | |
245 | ||
246 | /* | |
247 | * Force the completion of the mask register write before issuing | |
248 | * the interrupt. | |
249 | */ | |
250 | src_readl(dev, MUnit.OIMR); | |
251 | ||
252 | /* | |
253 | * Signal that there is a new synch command | |
254 | */ | |
255 | src_writel(dev, MUnit.IDR, INBOUNDDOORBELL_0 << SRC_IDR_SHIFT); | |
256 | ||
11604612 MR |
257 | if (!dev->sync_mode || command != SEND_SYNCHRONOUS_FIB) { |
258 | ok = 0; | |
259 | start = jiffies; | |
e8b12f0f | 260 | |
dafde947 MR |
261 | if (command == IOP_RESET_ALWAYS) { |
262 | /* Wait up to 10 sec */ | |
263 | delay = 10*HZ; | |
264 | } else { | |
265 | /* Wait up to 5 minutes */ | |
266 | delay = 300*HZ; | |
267 | } | |
268 | while (time_before(jiffies, start+delay)) { | |
11604612 MR |
269 | udelay(5); /* Delay 5 microseconds to let Mon960 get info. */ |
270 | /* | |
271 | * Mon960 will set doorbell0 bit when it has completed the command. | |
272 | */ | |
495c0217 | 273 | if (aac_src_get_sync_status(dev) & OUTBOUNDDOORBELL_0) { |
11604612 MR |
274 | /* |
275 | * Clear the doorbell. | |
276 | */ | |
495c0217 MR |
277 | if (dev->msi_enabled) |
278 | aac_src_access_devreg(dev, | |
279 | AAC_CLEAR_SYNC_BIT); | |
280 | else | |
281 | src_writel(dev, | |
282 | MUnit.ODR_C, | |
283 | OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT); | |
11604612 MR |
284 | ok = 1; |
285 | break; | |
286 | } | |
287 | /* | |
288 | * Yield the processor in case we are slow | |
289 | */ | |
290 | msleep(1); | |
e8b12f0f | 291 | } |
11604612 MR |
292 | if (unlikely(ok != 1)) { |
293 | /* | |
294 | * Restore interrupt mask even though we timed out | |
295 | */ | |
296 | aac_adapter_enable_int(dev); | |
297 | return -ETIMEDOUT; | |
298 | } | |
299 | /* | |
300 | * Pull the synch status from Mailbox 0. | |
301 | */ | |
302 | if (status) | |
303 | *status = readl(&dev->IndexRegs->Mailbox[0]); | |
304 | if (r1) | |
305 | *r1 = readl(&dev->IndexRegs->Mailbox[1]); | |
306 | if (r2) | |
307 | *r2 = readl(&dev->IndexRegs->Mailbox[2]); | |
308 | if (r3) | |
309 | *r3 = readl(&dev->IndexRegs->Mailbox[3]); | |
310 | if (r4) | |
311 | *r4 = readl(&dev->IndexRegs->Mailbox[4]); | |
495c0217 MR |
312 | if (command == GET_COMM_PREFERRED_SETTINGS) |
313 | dev->max_msix = | |
314 | readl(&dev->IndexRegs->Mailbox[5]) & 0xFFFF; | |
11604612 MR |
315 | /* |
316 | * Clear the synch command doorbell. | |
317 | */ | |
495c0217 MR |
318 | if (!dev->msi_enabled) |
319 | src_writel(dev, | |
320 | MUnit.ODR_C, | |
321 | OUTBOUNDDOORBELL_0 << SRC_ODR_SHIFT); | |
e8b12f0f MR |
322 | } |
323 | ||
11604612 MR |
324 | /* |
325 | * Restore interrupt mask | |
326 | */ | |
e8b12f0f MR |
327 | aac_adapter_enable_int(dev); |
328 | return 0; | |
e8b12f0f MR |
329 | } |
330 | ||
331 | /** | |
332 | * aac_src_interrupt_adapter - interrupt adapter | |
333 | * @dev: Adapter | |
334 | * | |
335 | * Send an interrupt to the i960 and breakpoint it. | |
336 | */ | |
337 | ||
338 | static void aac_src_interrupt_adapter(struct aac_dev *dev) | |
339 | { | |
340 | src_sync_cmd(dev, BREAKPOINT_REQUEST, | |
341 | 0, 0, 0, 0, 0, 0, | |
342 | NULL, NULL, NULL, NULL, NULL); | |
343 | } | |
344 | ||
345 | /** | |
346 | * aac_src_notify_adapter - send an event to the adapter | |
347 | * @dev: Adapter | |
348 | * @event: Event to send | |
349 | * | |
350 | * Notify the i960 that something it probably cares about has | |
351 | * happened. | |
352 | */ | |
353 | ||
354 | static void aac_src_notify_adapter(struct aac_dev *dev, u32 event) | |
355 | { | |
356 | switch (event) { | |
357 | ||
358 | case AdapNormCmdQue: | |
359 | src_writel(dev, MUnit.ODR_C, | |
360 | INBOUNDDOORBELL_1 << SRC_ODR_SHIFT); | |
361 | break; | |
362 | case HostNormRespNotFull: | |
363 | src_writel(dev, MUnit.ODR_C, | |
364 | INBOUNDDOORBELL_4 << SRC_ODR_SHIFT); | |
365 | break; | |
366 | case AdapNormRespQue: | |
367 | src_writel(dev, MUnit.ODR_C, | |
368 | INBOUNDDOORBELL_2 << SRC_ODR_SHIFT); | |
369 | break; | |
370 | case HostNormCmdNotFull: | |
371 | src_writel(dev, MUnit.ODR_C, | |
372 | INBOUNDDOORBELL_3 << SRC_ODR_SHIFT); | |
373 | break; | |
374 | case FastIo: | |
375 | src_writel(dev, MUnit.ODR_C, | |
376 | INBOUNDDOORBELL_6 << SRC_ODR_SHIFT); | |
377 | break; | |
378 | case AdapPrintfDone: | |
379 | src_writel(dev, MUnit.ODR_C, | |
380 | INBOUNDDOORBELL_5 << SRC_ODR_SHIFT); | |
381 | break; | |
382 | default: | |
383 | BUG(); | |
384 | break; | |
385 | } | |
386 | } | |
387 | ||
388 | /** | |
389 | * aac_src_start_adapter - activate adapter | |
390 | * @dev: Adapter | |
391 | * | |
392 | * Start up processing on an i960 based AAC adapter | |
393 | */ | |
394 | ||
395 | static void aac_src_start_adapter(struct aac_dev *dev) | |
396 | { | |
d1ef4da8 | 397 | union aac_init *init; |
495c0217 | 398 | int i; |
e8b12f0f | 399 | |
85d22bbf | 400 | /* reset host_rrq_idx first */ |
495c0217 MR |
401 | for (i = 0; i < dev->max_msix; i++) { |
402 | dev->host_rrq_idx[i] = i * dev->vector_cap; | |
403 | atomic_set(&dev->rrq_outstanding[i], 0); | |
404 | } | |
3ffd6c5a | 405 | atomic_set(&dev->msix_counter, 0); |
495c0217 | 406 | dev->fibs_pushed_no = 0; |
85d22bbf | 407 | |
e8b12f0f | 408 | init = dev->init; |
d1ef4da8 RAR |
409 | if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE3) { |
410 | init->r8.host_elapsed_seconds = cpu_to_le32(get_seconds()); | |
411 | src_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS, | |
412 | (u32)(ulong)dev->init_pa, | |
413 | (u32)((ulong)dev->init_pa>>32), | |
414 | sizeof(struct _r8) + | |
415 | (AAC_MAX_HRRQ - 1) * sizeof(struct _rrq), | |
416 | 0, 0, 0, NULL, NULL, NULL, NULL, NULL); | |
417 | } else { | |
418 | init->r7.host_elapsed_seconds = cpu_to_le32(get_seconds()); | |
419 | // We can only use a 32 bit address here | |
420 | src_sync_cmd(dev, INIT_STRUCT_BASE_ADDRESS, | |
421 | (u32)(ulong)dev->init_pa, 0, 0, 0, 0, 0, | |
422 | NULL, NULL, NULL, NULL, NULL); | |
423 | } | |
e8b12f0f | 424 | |
e8b12f0f MR |
425 | } |
426 | ||
427 | /** | |
428 | * aac_src_check_health | |
429 | * @dev: device to check if healthy | |
430 | * | |
431 | * Will attempt to determine if the specified adapter is alive and | |
432 | * capable of handling requests, returning 0 if alive. | |
433 | */ | |
434 | static int aac_src_check_health(struct aac_dev *dev) | |
435 | { | |
436 | u32 status = src_readl(dev, MUnit.OMR); | |
437 | ||
438 | /* | |
439 | * Check to see if the board failed any self tests. | |
440 | */ | |
441 | if (unlikely(status & SELF_TEST_FAILED)) | |
442 | return -1; | |
443 | ||
444 | /* | |
445 | * Check to see if the board panic'd. | |
446 | */ | |
447 | if (unlikely(status & KERNEL_PANIC)) | |
448 | return (status >> 16) & 0xFF; | |
449 | /* | |
450 | * Wait for the adapter to be up and running. | |
451 | */ | |
452 | if (unlikely(!(status & KERNEL_UP_AND_RUNNING))) | |
453 | return -3; | |
454 | /* | |
455 | * Everything is OK | |
456 | */ | |
457 | return 0; | |
458 | } | |
459 | ||
423400e6 RAR |
460 | static inline u32 aac_get_vector(struct aac_dev *dev) |
461 | { | |
462 | return atomic_inc_return(&dev->msix_counter)%dev->max_msix; | |
463 | } | |
464 | ||
e8b12f0f MR |
465 | /** |
466 | * aac_src_deliver_message | |
467 | * @fib: fib to issue | |
468 | * | |
469 | * Will send a fib, returning 0 if successful. | |
470 | */ | |
471 | static int aac_src_deliver_message(struct fib *fib) | |
472 | { | |
473 | struct aac_dev *dev = fib->dev; | |
474 | struct aac_queue *q = &dev->queues->queue[AdapNormCmdQueue]; | |
e8b12f0f | 475 | u32 fibsize; |
b5f1758f | 476 | dma_addr_t address; |
e8b12f0f | 477 | struct aac_fib_xporthdr *pFibX; |
423400e6 | 478 | int native_hba; |
c6992781 MR |
479 | #if !defined(writeq) |
480 | unsigned long flags; | |
481 | #endif | |
482 | ||
3f4ce057 | 483 | u16 vector_no; |
e8b12f0f | 484 | |
ef616233 | 485 | atomic_inc(&q->numpending); |
e8b12f0f | 486 | |
423400e6 RAR |
487 | native_hba = (fib->flags & FIB_CONTEXT_FLAG_NATIVE_HBA) ? 1 : 0; |
488 | ||
489 | ||
490 | if (dev->msi_enabled && dev->max_msix > 1 && | |
491 | (native_hba || fib->hw_fib_va->header.Command != AifRequest)) { | |
492 | ||
493 | if ((dev->comm_interface == AAC_COMM_MESSAGE_TYPE3) | |
494 | && dev->sa_firmware) | |
495 | vector_no = aac_get_vector(dev); | |
496 | else | |
497 | vector_no = fib->vector_no; | |
498 | ||
499 | if (native_hba) { | |
500 | ((struct aac_hba_cmd_req *)fib->hw_fib_va)->reply_qid | |
501 | = vector_no; | |
502 | ((struct aac_hba_cmd_req *)fib->hw_fib_va)->request_id | |
503 | += (vector_no << 16); | |
504 | } else { | |
505 | fib->hw_fib_va->header.Handle += (vector_no << 16); | |
506 | } | |
3f4ce057 RAR |
507 | } else { |
508 | vector_no = 0; | |
495c0217 MR |
509 | } |
510 | ||
3f4ce057 RAR |
511 | atomic_inc(&dev->rrq_outstanding[vector_no]); |
512 | ||
423400e6 | 513 | if (native_hba) { |
85d22bbf | 514 | address = fib->hw_fib_pa; |
423400e6 RAR |
515 | fibsize = (fib->hbacmd_size + 127) / 128 - 1; |
516 | if (fibsize > 31) | |
517 | fibsize = 31; | |
85d22bbf | 518 | address |= fibsize; |
423400e6 RAR |
519 | #if defined(writeq) |
520 | src_writeq(dev, MUnit.IQN_L, (u64)address); | |
521 | #else | |
522 | spin_lock_irqsave(&fib->dev->iq_lock, flags); | |
523 | src_writel(dev, MUnit.IQN_H, | |
524 | upper_32_bits(address) & 0xffffffff); | |
525 | src_writel(dev, MUnit.IQN_L, address & 0xffffffff); | |
526 | spin_unlock_irqrestore(&fib->dev->iq_lock, flags); | |
527 | #endif | |
85d22bbf | 528 | } else { |
423400e6 RAR |
529 | if (dev->comm_interface == AAC_COMM_MESSAGE_TYPE2 || |
530 | dev->comm_interface == AAC_COMM_MESSAGE_TYPE3) { | |
531 | /* Calculate the amount to the fibsize bits */ | |
532 | fibsize = (le16_to_cpu(fib->hw_fib_va->header.Size) | |
533 | + 127) / 128 - 1; | |
534 | /* New FIB header, 32-bit */ | |
535 | address = fib->hw_fib_pa; | |
536 | fib->hw_fib_va->header.StructType = FIB_MAGIC2; | |
537 | fib->hw_fib_va->header.SenderFibAddress = | |
538 | cpu_to_le32((u32)address); | |
539 | fib->hw_fib_va->header.u.TimeStamp = 0; | |
540 | WARN_ON(((u32)(((address) >> 16) >> 16)) != 0L); | |
541 | } else { | |
542 | /* Calculate the amount to the fibsize bits */ | |
543 | fibsize = (sizeof(struct aac_fib_xporthdr) + | |
544 | le16_to_cpu(fib->hw_fib_va->header.Size) | |
545 | + 127) / 128 - 1; | |
546 | /* Fill XPORT header */ | |
547 | pFibX = (struct aac_fib_xporthdr *) | |
548 | ((unsigned char *)fib->hw_fib_va - | |
549 | sizeof(struct aac_fib_xporthdr)); | |
550 | pFibX->Handle = fib->hw_fib_va->header.Handle; | |
551 | pFibX->HostAddress = | |
552 | cpu_to_le64((u64)fib->hw_fib_pa); | |
553 | pFibX->Size = cpu_to_le32( | |
554 | le16_to_cpu(fib->hw_fib_va->header.Size)); | |
555 | address = fib->hw_fib_pa - | |
556 | (u64)sizeof(struct aac_fib_xporthdr); | |
557 | } | |
558 | if (fibsize > 31) | |
559 | fibsize = 31; | |
85d22bbf | 560 | address |= fibsize; |
423400e6 | 561 | |
c6992781 | 562 | #if defined(writeq) |
423400e6 | 563 | src_writeq(dev, MUnit.IQ_L, (u64)address); |
c6992781 | 564 | #else |
423400e6 RAR |
565 | spin_lock_irqsave(&fib->dev->iq_lock, flags); |
566 | src_writel(dev, MUnit.IQ_H, | |
567 | upper_32_bits(address) & 0xffffffff); | |
568 | src_writel(dev, MUnit.IQ_L, address & 0xffffffff); | |
569 | spin_unlock_irqrestore(&fib->dev->iq_lock, flags); | |
c6992781 | 570 | #endif |
423400e6 | 571 | } |
e8b12f0f MR |
572 | return 0; |
573 | } | |
574 | ||
575 | /** | |
576 | * aac_src_ioremap | |
577 | * @size: mapping resize request | |
578 | * | |
579 | */ | |
580 | static int aac_src_ioremap(struct aac_dev *dev, u32 size) | |
581 | { | |
582 | if (!size) { | |
71552505 TH |
583 | iounmap(dev->regs.src.bar1); |
584 | dev->regs.src.bar1 = NULL; | |
e8b12f0f | 585 | iounmap(dev->regs.src.bar0); |
11604612 | 586 | dev->base = dev->regs.src.bar0 = NULL; |
e8b12f0f MR |
587 | return 0; |
588 | } | |
589 | dev->regs.src.bar1 = ioremap(pci_resource_start(dev->pdev, 2), | |
590 | AAC_MIN_SRC_BAR1_SIZE); | |
591 | dev->base = NULL; | |
592 | if (dev->regs.src.bar1 == NULL) | |
593 | return -1; | |
ff08784b | 594 | dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size); |
e8b12f0f MR |
595 | if (dev->base == NULL) { |
596 | iounmap(dev->regs.src.bar1); | |
597 | dev->regs.src.bar1 = NULL; | |
598 | return -1; | |
599 | } | |
600 | dev->IndexRegs = &((struct src_registers __iomem *) | |
11604612 MR |
601 | dev->base)->u.tupelo.IndexRegs; |
602 | return 0; | |
603 | } | |
604 | ||
605 | /** | |
606 | * aac_srcv_ioremap | |
607 | * @size: mapping resize request | |
608 | * | |
609 | */ | |
610 | static int aac_srcv_ioremap(struct aac_dev *dev, u32 size) | |
611 | { | |
612 | if (!size) { | |
613 | iounmap(dev->regs.src.bar0); | |
614 | dev->base = dev->regs.src.bar0 = NULL; | |
615 | return 0; | |
616 | } | |
3ffd6c5a RAR |
617 | |
618 | dev->regs.src.bar1 = | |
619 | ioremap(pci_resource_start(dev->pdev, 2), AAC_MIN_SRCV_BAR1_SIZE); | |
620 | dev->base = NULL; | |
621 | if (dev->regs.src.bar1 == NULL) | |
622 | return -1; | |
ff08784b | 623 | dev->base = dev->regs.src.bar0 = ioremap(dev->base_start, size); |
3ffd6c5a RAR |
624 | if (dev->base == NULL) { |
625 | iounmap(dev->regs.src.bar1); | |
626 | dev->regs.src.bar1 = NULL; | |
11604612 | 627 | return -1; |
3ffd6c5a | 628 | } |
11604612 MR |
629 | dev->IndexRegs = &((struct src_registers __iomem *) |
630 | dev->base)->u.denali.IndexRegs; | |
e8b12f0f MR |
631 | return 0; |
632 | } | |
633 | ||
634 | static int aac_src_restart_adapter(struct aac_dev *dev, int bled) | |
635 | { | |
636 | u32 var, reset_mask; | |
637 | ||
638 | if (bled >= 0) { | |
639 | if (bled) | |
640 | printk(KERN_ERR "%s%d: adapter kernel panic'd %x.\n", | |
641 | dev->name, dev->id, bled); | |
dafde947 | 642 | dev->a_ops.adapter_enable_int = aac_src_disable_interrupt; |
e8b12f0f MR |
643 | bled = aac_adapter_sync_cmd(dev, IOP_RESET_ALWAYS, |
644 | 0, 0, 0, 0, 0, 0, &var, &reset_mask, NULL, NULL, NULL); | |
dafde947 MR |
645 | if ((bled || (var != 0x00000001)) && |
646 | !dev->doorbell_mask) | |
647 | return -EINVAL; | |
648 | else if (dev->doorbell_mask) { | |
649 | reset_mask = dev->doorbell_mask; | |
650 | bled = 0; | |
651 | var = 0x00000001; | |
652 | } | |
495c0217 MR |
653 | |
654 | if ((dev->pdev->device == PMC_DEVICE_S7 || | |
655 | dev->pdev->device == PMC_DEVICE_S8 || | |
656 | dev->pdev->device == PMC_DEVICE_S9) && dev->msi_enabled) { | |
657 | aac_src_access_devreg(dev, AAC_ENABLE_INTX); | |
658 | dev->msi_enabled = 0; | |
659 | msleep(5000); /* Delay 5 seconds */ | |
660 | } | |
661 | ||
dafde947 MR |
662 | if (!bled && (dev->supplement_adapter_info.SupportedOptions2 & |
663 | AAC_OPTION_DOORBELL_RESET)) { | |
e8b12f0f | 664 | src_writel(dev, MUnit.IDR, reset_mask); |
495c0217 | 665 | ssleep(45); |
dafde947 MR |
666 | } else { |
667 | src_writel(dev, MUnit.IDR, 0x100); | |
668 | ssleep(45); | |
e8b12f0f MR |
669 | } |
670 | } | |
671 | ||
672 | if (src_readl(dev, MUnit.OMR) & KERNEL_PANIC) | |
673 | return -ENODEV; | |
674 | ||
675 | if (startup_timeout < 300) | |
676 | startup_timeout = 300; | |
677 | ||
678 | return 0; | |
679 | } | |
680 | ||
681 | /** | |
682 | * aac_src_select_comm - Select communications method | |
683 | * @dev: Adapter | |
684 | * @comm: communications method | |
685 | */ | |
a44199ee | 686 | static int aac_src_select_comm(struct aac_dev *dev, int comm) |
e8b12f0f MR |
687 | { |
688 | switch (comm) { | |
689 | case AAC_COMM_MESSAGE: | |
e8b12f0f MR |
690 | dev->a_ops.adapter_intr = aac_src_intr_message; |
691 | dev->a_ops.adapter_deliver = aac_src_deliver_message; | |
692 | break; | |
693 | default: | |
694 | return 1; | |
695 | } | |
696 | return 0; | |
697 | } | |
698 | ||
699 | /** | |
700 | * aac_src_init - initialize an Cardinal Frey Bar card | |
701 | * @dev: device to configure | |
702 | * | |
703 | */ | |
704 | ||
705 | int aac_src_init(struct aac_dev *dev) | |
706 | { | |
707 | unsigned long start; | |
708 | unsigned long status; | |
709 | int restart = 0; | |
710 | int instance = dev->id; | |
711 | const char *name = dev->name; | |
712 | ||
713 | dev->a_ops.adapter_ioremap = aac_src_ioremap; | |
714 | dev->a_ops.adapter_comm = aac_src_select_comm; | |
715 | ||
716 | dev->base_size = AAC_MIN_SRC_BAR0_SIZE; | |
717 | if (aac_adapter_ioremap(dev, dev->base_size)) { | |
718 | printk(KERN_WARNING "%s: unable to map adapter.\n", name); | |
719 | goto error_iounmap; | |
720 | } | |
721 | ||
722 | /* Failure to reset here is an option ... */ | |
723 | dev->a_ops.adapter_sync_cmd = src_sync_cmd; | |
724 | dev->a_ops.adapter_enable_int = aac_src_disable_interrupt; | |
725 | if ((aac_reset_devices || reset_devices) && | |
726 | !aac_src_restart_adapter(dev, 0)) | |
727 | ++restart; | |
728 | /* | |
729 | * Check to see if the board panic'd while booting. | |
730 | */ | |
731 | status = src_readl(dev, MUnit.OMR); | |
732 | if (status & KERNEL_PANIC) { | |
733 | if (aac_src_restart_adapter(dev, aac_src_check_health(dev))) | |
734 | goto error_iounmap; | |
735 | ++restart; | |
736 | } | |
737 | /* | |
738 | * Check to see if the board failed any self tests. | |
739 | */ | |
740 | status = src_readl(dev, MUnit.OMR); | |
741 | if (status & SELF_TEST_FAILED) { | |
742 | printk(KERN_ERR "%s%d: adapter self-test failed.\n", | |
743 | dev->name, instance); | |
744 | goto error_iounmap; | |
745 | } | |
746 | /* | |
747 | * Check to see if the monitor panic'd while booting. | |
748 | */ | |
749 | if (status & MONITOR_PANIC) { | |
750 | printk(KERN_ERR "%s%d: adapter monitor panic.\n", | |
751 | dev->name, instance); | |
752 | goto error_iounmap; | |
753 | } | |
754 | start = jiffies; | |
755 | /* | |
756 | * Wait for the adapter to be up and running. Wait up to 3 minutes | |
757 | */ | |
758 | while (!((status = src_readl(dev, MUnit.OMR)) & | |
759 | KERNEL_UP_AND_RUNNING)) { | |
760 | if ((restart && | |
761 | (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) || | |
762 | time_after(jiffies, start+HZ*startup_timeout)) { | |
763 | printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n", | |
764 | dev->name, instance, status); | |
765 | goto error_iounmap; | |
766 | } | |
767 | if (!restart && | |
768 | ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) || | |
769 | time_after(jiffies, start + HZ * | |
770 | ((startup_timeout > 60) | |
771 | ? (startup_timeout - 60) | |
772 | : (startup_timeout / 2))))) { | |
773 | if (likely(!aac_src_restart_adapter(dev, | |
774 | aac_src_check_health(dev)))) | |
775 | start = jiffies; | |
776 | ++restart; | |
777 | } | |
778 | msleep(1); | |
779 | } | |
780 | if (restart && aac_commit) | |
781 | aac_commit = 1; | |
782 | /* | |
783 | * Fill in the common function dispatch table. | |
784 | */ | |
785 | dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter; | |
786 | dev->a_ops.adapter_disable_int = aac_src_disable_interrupt; | |
dafde947 | 787 | dev->a_ops.adapter_enable_int = aac_src_disable_interrupt; |
e8b12f0f MR |
788 | dev->a_ops.adapter_notify = aac_src_notify_adapter; |
789 | dev->a_ops.adapter_sync_cmd = src_sync_cmd; | |
790 | dev->a_ops.adapter_check_health = aac_src_check_health; | |
791 | dev->a_ops.adapter_restart = aac_src_restart_adapter; | |
de665f28 | 792 | dev->a_ops.adapter_start = aac_src_start_adapter; |
e8b12f0f MR |
793 | |
794 | /* | |
795 | * First clear out all interrupts. Then enable the one's that we | |
796 | * can handle. | |
797 | */ | |
798 | aac_adapter_comm(dev, AAC_COMM_MESSAGE); | |
799 | aac_adapter_disable_int(dev); | |
800 | src_writel(dev, MUnit.ODR_C, 0xffffffff); | |
801 | aac_adapter_enable_int(dev); | |
802 | ||
803 | if (aac_init_adapter(dev) == NULL) | |
804 | goto error_iounmap; | |
805 | if (dev->comm_interface != AAC_COMM_MESSAGE_TYPE1) | |
806 | goto error_iounmap; | |
807 | ||
9022d375 | 808 | dev->msi = !pci_enable_msi(dev->pdev); |
e8b12f0f | 809 | |
495c0217 MR |
810 | dev->aac_msix[0].vector_no = 0; |
811 | dev->aac_msix[0].dev = dev; | |
812 | ||
e8b12f0f | 813 | if (request_irq(dev->pdev->irq, dev->a_ops.adapter_intr, |
495c0217 | 814 | IRQF_SHARED, "aacraid", &(dev->aac_msix[0])) < 0) { |
e8b12f0f MR |
815 | |
816 | if (dev->msi) | |
817 | pci_disable_msi(dev->pdev); | |
818 | ||
819 | printk(KERN_ERR "%s%d: Interrupt unavailable.\n", | |
820 | name, instance); | |
821 | goto error_iounmap; | |
822 | } | |
823 | dev->dbg_base = pci_resource_start(dev->pdev, 2); | |
824 | dev->dbg_base_mapped = dev->regs.src.bar1; | |
825 | dev->dbg_size = AAC_MIN_SRC_BAR1_SIZE; | |
dafde947 | 826 | dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message; |
e8b12f0f MR |
827 | |
828 | aac_adapter_enable_int(dev); | |
11604612 MR |
829 | |
830 | if (!dev->sync_mode) { | |
831 | /* | |
832 | * Tell the adapter that all is configured, and it can | |
833 | * start accepting requests | |
834 | */ | |
835 | aac_src_start_adapter(dev); | |
836 | } | |
837 | return 0; | |
838 | ||
839 | error_iounmap: | |
840 | ||
841 | return -1; | |
842 | } | |
843 | ||
844 | /** | |
845 | * aac_srcv_init - initialize an SRCv card | |
846 | * @dev: device to configure | |
847 | * | |
848 | */ | |
849 | ||
850 | int aac_srcv_init(struct aac_dev *dev) | |
851 | { | |
852 | unsigned long start; | |
853 | unsigned long status; | |
854 | int restart = 0; | |
855 | int instance = dev->id; | |
856 | const char *name = dev->name; | |
857 | ||
858 | dev->a_ops.adapter_ioremap = aac_srcv_ioremap; | |
859 | dev->a_ops.adapter_comm = aac_src_select_comm; | |
860 | ||
861 | dev->base_size = AAC_MIN_SRCV_BAR0_SIZE; | |
862 | if (aac_adapter_ioremap(dev, dev->base_size)) { | |
863 | printk(KERN_WARNING "%s: unable to map adapter.\n", name); | |
864 | goto error_iounmap; | |
865 | } | |
866 | ||
867 | /* Failure to reset here is an option ... */ | |
868 | dev->a_ops.adapter_sync_cmd = src_sync_cmd; | |
869 | dev->a_ops.adapter_enable_int = aac_src_disable_interrupt; | |
870 | if ((aac_reset_devices || reset_devices) && | |
871 | !aac_src_restart_adapter(dev, 0)) | |
872 | ++restart; | |
2c10cd43 MR |
873 | /* |
874 | * Check to see if flash update is running. | |
875 | * Wait for the adapter to be up and running. Wait up to 5 minutes | |
876 | */ | |
877 | status = src_readl(dev, MUnit.OMR); | |
878 | if (status & FLASH_UPD_PENDING) { | |
879 | start = jiffies; | |
880 | do { | |
881 | status = src_readl(dev, MUnit.OMR); | |
882 | if (time_after(jiffies, start+HZ*FWUPD_TIMEOUT)) { | |
883 | printk(KERN_ERR "%s%d: adapter flash update failed.\n", | |
884 | dev->name, instance); | |
885 | goto error_iounmap; | |
886 | } | |
887 | } while (!(status & FLASH_UPD_SUCCESS) && | |
888 | !(status & FLASH_UPD_FAILED)); | |
889 | /* Delay 10 seconds. | |
890 | * Because right now FW is doing a soft reset, | |
891 | * do not read scratch pad register at this time | |
892 | */ | |
893 | ssleep(10); | |
894 | } | |
e8b12f0f | 895 | /* |
11604612 | 896 | * Check to see if the board panic'd while booting. |
e8b12f0f | 897 | */ |
11604612 MR |
898 | status = src_readl(dev, MUnit.OMR); |
899 | if (status & KERNEL_PANIC) { | |
900 | if (aac_src_restart_adapter(dev, aac_src_check_health(dev))) | |
901 | goto error_iounmap; | |
902 | ++restart; | |
903 | } | |
904 | /* | |
905 | * Check to see if the board failed any self tests. | |
906 | */ | |
907 | status = src_readl(dev, MUnit.OMR); | |
908 | if (status & SELF_TEST_FAILED) { | |
909 | printk(KERN_ERR "%s%d: adapter self-test failed.\n", dev->name, instance); | |
910 | goto error_iounmap; | |
911 | } | |
912 | /* | |
913 | * Check to see if the monitor panic'd while booting. | |
914 | */ | |
915 | if (status & MONITOR_PANIC) { | |
916 | printk(KERN_ERR "%s%d: adapter monitor panic.\n", dev->name, instance); | |
917 | goto error_iounmap; | |
918 | } | |
919 | start = jiffies; | |
920 | /* | |
921 | * Wait for the adapter to be up and running. Wait up to 3 minutes | |
922 | */ | |
2c10cd43 MR |
923 | while (!((status = src_readl(dev, MUnit.OMR)) & |
924 | KERNEL_UP_AND_RUNNING) || | |
925 | status == 0xffffffff) { | |
11604612 MR |
926 | if ((restart && |
927 | (status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC))) || | |
928 | time_after(jiffies, start+HZ*startup_timeout)) { | |
929 | printk(KERN_ERR "%s%d: adapter kernel failed to start, init status = %lx.\n", | |
930 | dev->name, instance, status); | |
931 | goto error_iounmap; | |
932 | } | |
933 | if (!restart && | |
934 | ((status & (KERNEL_PANIC|SELF_TEST_FAILED|MONITOR_PANIC)) || | |
935 | time_after(jiffies, start + HZ * | |
936 | ((startup_timeout > 60) | |
937 | ? (startup_timeout - 60) | |
938 | : (startup_timeout / 2))))) { | |
939 | if (likely(!aac_src_restart_adapter(dev, aac_src_check_health(dev)))) | |
940 | start = jiffies; | |
941 | ++restart; | |
942 | } | |
943 | msleep(1); | |
944 | } | |
945 | if (restart && aac_commit) | |
946 | aac_commit = 1; | |
947 | /* | |
948 | * Fill in the common function dispatch table. | |
949 | */ | |
950 | dev->a_ops.adapter_interrupt = aac_src_interrupt_adapter; | |
951 | dev->a_ops.adapter_disable_int = aac_src_disable_interrupt; | |
dafde947 | 952 | dev->a_ops.adapter_enable_int = aac_src_disable_interrupt; |
11604612 MR |
953 | dev->a_ops.adapter_notify = aac_src_notify_adapter; |
954 | dev->a_ops.adapter_sync_cmd = src_sync_cmd; | |
955 | dev->a_ops.adapter_check_health = aac_src_check_health; | |
956 | dev->a_ops.adapter_restart = aac_src_restart_adapter; | |
de665f28 | 957 | dev->a_ops.adapter_start = aac_src_start_adapter; |
11604612 MR |
958 | |
959 | /* | |
960 | * First clear out all interrupts. Then enable the one's that we | |
961 | * can handle. | |
962 | */ | |
963 | aac_adapter_comm(dev, AAC_COMM_MESSAGE); | |
964 | aac_adapter_disable_int(dev); | |
965 | src_writel(dev, MUnit.ODR_C, 0xffffffff); | |
966 | aac_adapter_enable_int(dev); | |
e8b12f0f | 967 | |
11604612 MR |
968 | if (aac_init_adapter(dev) == NULL) |
969 | goto error_iounmap; | |
d1ef4da8 RAR |
970 | if ((dev->comm_interface != AAC_COMM_MESSAGE_TYPE2) && |
971 | (dev->comm_interface != AAC_COMM_MESSAGE_TYPE3)) | |
11604612 | 972 | goto error_iounmap; |
495c0217 MR |
973 | if (dev->msi_enabled) |
974 | aac_src_access_devreg(dev, AAC_ENABLE_MSIX); | |
8b1462e0 MR |
975 | |
976 | if (aac_acquire_irq(dev)) | |
977 | goto error_iounmap; | |
978 | ||
3ffd6c5a RAR |
979 | dev->dbg_base = pci_resource_start(dev->pdev, 2); |
980 | dev->dbg_base_mapped = dev->regs.src.bar1; | |
981 | dev->dbg_size = AAC_MIN_SRCV_BAR1_SIZE; | |
dafde947 | 982 | dev->a_ops.adapter_enable_int = aac_src_enable_interrupt_message; |
11604612 MR |
983 | |
984 | aac_adapter_enable_int(dev); | |
985 | ||
986 | if (!dev->sync_mode) { | |
987 | /* | |
988 | * Tell the adapter that all is configured, and it can | |
989 | * start accepting requests | |
990 | */ | |
991 | aac_src_start_adapter(dev); | |
992 | } | |
e8b12f0f MR |
993 | return 0; |
994 | ||
995 | error_iounmap: | |
996 | ||
997 | return -1; | |
998 | } | |
11604612 | 999 | |
495c0217 MR |
1000 | void aac_src_access_devreg(struct aac_dev *dev, int mode) |
1001 | { | |
1002 | u_int32_t val; | |
1003 | ||
1004 | switch (mode) { | |
1005 | case AAC_ENABLE_INTERRUPT: | |
1006 | src_writel(dev, | |
1007 | MUnit.OIMR, | |
1008 | dev->OIMR = (dev->msi_enabled ? | |
1009 | AAC_INT_ENABLE_TYPE1_MSIX : | |
1010 | AAC_INT_ENABLE_TYPE1_INTX)); | |
1011 | break; | |
1012 | ||
1013 | case AAC_DISABLE_INTERRUPT: | |
1014 | src_writel(dev, | |
1015 | MUnit.OIMR, | |
1016 | dev->OIMR = AAC_INT_DISABLE_ALL); | |
1017 | break; | |
1018 | ||
1019 | case AAC_ENABLE_MSIX: | |
1020 | /* set bit 6 */ | |
1021 | val = src_readl(dev, MUnit.IDR); | |
1022 | val |= 0x40; | |
1023 | src_writel(dev, MUnit.IDR, val); | |
1024 | src_readl(dev, MUnit.IDR); | |
1025 | /* unmask int. */ | |
1026 | val = PMC_ALL_INTERRUPT_BITS; | |
1027 | src_writel(dev, MUnit.IOAR, val); | |
1028 | val = src_readl(dev, MUnit.OIMR); | |
1029 | src_writel(dev, | |
1030 | MUnit.OIMR, | |
1031 | val & (~(PMC_GLOBAL_INT_BIT2 | PMC_GLOBAL_INT_BIT0))); | |
1032 | break; | |
1033 | ||
1034 | case AAC_DISABLE_MSIX: | |
1035 | /* reset bit 6 */ | |
1036 | val = src_readl(dev, MUnit.IDR); | |
1037 | val &= ~0x40; | |
1038 | src_writel(dev, MUnit.IDR, val); | |
1039 | src_readl(dev, MUnit.IDR); | |
1040 | break; | |
1041 | ||
1042 | case AAC_CLEAR_AIF_BIT: | |
1043 | /* set bit 5 */ | |
1044 | val = src_readl(dev, MUnit.IDR); | |
1045 | val |= 0x20; | |
1046 | src_writel(dev, MUnit.IDR, val); | |
1047 | src_readl(dev, MUnit.IDR); | |
1048 | break; | |
1049 | ||
1050 | case AAC_CLEAR_SYNC_BIT: | |
1051 | /* set bit 4 */ | |
1052 | val = src_readl(dev, MUnit.IDR); | |
1053 | val |= 0x10; | |
1054 | src_writel(dev, MUnit.IDR, val); | |
1055 | src_readl(dev, MUnit.IDR); | |
1056 | break; | |
1057 | ||
1058 | case AAC_ENABLE_INTX: | |
1059 | /* set bit 7 */ | |
1060 | val = src_readl(dev, MUnit.IDR); | |
1061 | val |= 0x80; | |
1062 | src_writel(dev, MUnit.IDR, val); | |
1063 | src_readl(dev, MUnit.IDR); | |
1064 | /* unmask int. */ | |
1065 | val = PMC_ALL_INTERRUPT_BITS; | |
1066 | src_writel(dev, MUnit.IOAR, val); | |
1067 | src_readl(dev, MUnit.IOAR); | |
1068 | val = src_readl(dev, MUnit.OIMR); | |
1069 | src_writel(dev, MUnit.OIMR, | |
1070 | val & (~(PMC_GLOBAL_INT_BIT2))); | |
1071 | break; | |
1072 | ||
1073 | default: | |
1074 | break; | |
1075 | } | |
1076 | } | |
1077 | ||
1078 | static int aac_src_get_sync_status(struct aac_dev *dev) | |
1079 | { | |
1080 | ||
1081 | int val; | |
1082 | ||
1083 | if (dev->msi_enabled) | |
1084 | val = src_readl(dev, MUnit.ODR_MSI) & 0x1000 ? 1 : 0; | |
1085 | else | |
1086 | val = src_readl(dev, MUnit.ODR_R) >> SRC_ODR_SHIFT; | |
1087 | ||
1088 | return val; | |
1089 | } |