Commit | Line | Data |
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24b043cb RAR |
1 | #ifndef _AACRAID_H_ |
2 | #define _AACRAID_H_ | |
8ce3eca4 | 3 | #ifndef dprintk |
1da177e4 LT |
4 | # define dprintk(x) |
5 | #endif | |
7a8cf29d MH |
6 | /* eg: if (nblank(dprintk(x))) */ |
7 | #define _nblank(x) #x | |
8 | #define nblank(x) _nblank(x)[0] | |
9 | ||
28713324 | 10 | #include <linux/interrupt.h> |
495c0217 | 11 | #include <linux/pci.h> |
1da177e4 LT |
12 | |
13 | /*------------------------------------------------------------------------------ | |
14 | * D E F I N E S | |
15 | *----------------------------------------------------------------------------*/ | |
16 | ||
84859c92 | 17 | #define AAC_MAX_MSIX 32 /* vectors */ |
495c0217 MR |
18 | #define AAC_PCI_MSI_ENABLE 0x8000 |
19 | ||
20 | enum { | |
21 | AAC_ENABLE_INTERRUPT = 0x0, | |
22 | AAC_DISABLE_INTERRUPT, | |
23 | AAC_ENABLE_MSIX, | |
24 | AAC_DISABLE_MSIX, | |
25 | AAC_CLEAR_AIF_BIT, | |
26 | AAC_CLEAR_SYNC_BIT, | |
27 | AAC_ENABLE_INTX | |
28 | }; | |
29 | ||
30 | #define AAC_INT_MODE_INTX (1<<0) | |
31 | #define AAC_INT_MODE_MSI (1<<1) | |
32 | #define AAC_INT_MODE_AIF (1<<2) | |
33 | #define AAC_INT_MODE_SYNC (1<<3) | |
78cbccd3 | 34 | #define AAC_INT_MODE_MSIX (1<<16) |
495c0217 MR |
35 | |
36 | #define AAC_INT_ENABLE_TYPE1_INTX 0xfffffffb | |
37 | #define AAC_INT_ENABLE_TYPE1_MSIX 0xfffffffa | |
38 | #define AAC_INT_DISABLE_ALL 0xffffffff | |
39 | ||
40 | /* Bit definitions in IOA->Host Interrupt Register */ | |
41 | #define PMC_TRANSITION_TO_OPERATIONAL (1<<31) | |
42 | #define PMC_IOARCB_TRANSFER_FAILED (1<<28) | |
43 | #define PMC_IOA_UNIT_CHECK (1<<27) | |
44 | #define PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE (1<<26) | |
45 | #define PMC_CRITICAL_IOA_OP_IN_PROGRESS (1<<25) | |
46 | #define PMC_IOARRIN_LOST (1<<4) | |
47 | #define PMC_SYSTEM_BUS_MMIO_ERROR (1<<3) | |
48 | #define PMC_IOA_PROCESSOR_IN_ERROR_STATE (1<<2) | |
49 | #define PMC_HOST_RRQ_VALID (1<<1) | |
50 | #define PMC_OPERATIONAL_STATUS (1<<31) | |
51 | #define PMC_ALLOW_MSIX_VECTOR0 (1<<0) | |
52 | ||
53 | #define PMC_IOA_ERROR_INTERRUPTS (PMC_IOARCB_TRANSFER_FAILED | \ | |
54 | PMC_IOA_UNIT_CHECK | \ | |
55 | PMC_NO_HOST_RRQ_FOR_CMD_RESPONSE | \ | |
56 | PMC_IOARRIN_LOST | \ | |
57 | PMC_SYSTEM_BUS_MMIO_ERROR | \ | |
58 | PMC_IOA_PROCESSOR_IN_ERROR_STATE) | |
59 | ||
60 | #define PMC_ALL_INTERRUPT_BITS (PMC_IOA_ERROR_INTERRUPTS | \ | |
61 | PMC_HOST_RRQ_VALID | \ | |
62 | PMC_TRANSITION_TO_OPERATIONAL | \ | |
63 | PMC_ALLOW_MSIX_VECTOR0) | |
64 | #define PMC_GLOBAL_INT_BIT2 0x00000004 | |
65 | #define PMC_GLOBAL_INT_BIT0 0x00000001 | |
66 | ||
9a72f976 | 67 | #ifndef AAC_DRIVER_BUILD |
139112fb | 68 | # define AAC_DRIVER_BUILD 41066 |
29c97684 | 69 | # define AAC_DRIVER_BRANCH "-ms" |
9a72f976 | 70 | #endif |
1da177e4 LT |
71 | #define MAXIMUM_NUM_CONTAINERS 32 |
72 | ||
7c00ffa3 | 73 | #define AAC_NUM_MGT_FIB 8 |
2b4df6ea | 74 | #define AAC_NUM_IO_FIB (1024 - AAC_NUM_MGT_FIB) |
7c00ffa3 | 75 | #define AAC_NUM_FIB (AAC_NUM_IO_FIB + AAC_NUM_MGT_FIB) |
1da177e4 LT |
76 | |
77 | #define AAC_MAX_LUN (8) | |
78 | ||
79 | #define AAC_MAX_HOSTPHYSMEMPAGES (0xfffff) | |
7a9366e4 | 80 | #define AAC_MAX_32BIT_SGBCOUNT ((unsigned short)256) |
1da177e4 | 81 | |
9cccde93 RM |
82 | #define AAC_DEBUG_INSTRUMENT_AIF_DELETE |
83 | ||
c83b11e3 RAR |
84 | #define AAC_MAX_NATIVE_TARGETS 1024 |
85 | /* Thor: 5 phys. buses: #0: empty, 1-4: 256 targets each */ | |
86 | #define AAC_MAX_BUSES 5 | |
87 | #define AAC_MAX_TARGETS 256 | |
88 | #define AAC_MAX_NATIVE_SIZE 2048 | |
89 | ||
90 | #define CISS_REPORT_PHYSICAL_LUNS 0xc3 | |
91 | ||
92 | struct aac_ciss_phys_luns_resp { | |
93 | u8 list_length[4]; /* LUN list length (N-7, big endian) */ | |
94 | u8 resp_flag; /* extended response_flag */ | |
95 | u8 reserved[3]; | |
96 | struct _ciss_lun { | |
97 | u8 tid[3]; /* Target ID */ | |
98 | u8 bus; /* Bus, flag (bits 6,7) */ | |
99 | u8 level3[2]; | |
100 | u8 level2[2]; | |
101 | u8 node_ident[16]; /* phys. node identifier */ | |
102 | } lun[1]; /* List of phys. devices */ | |
103 | }; | |
104 | ||
d1ef4da8 RAR |
105 | /* |
106 | * Interrupts | |
107 | */ | |
108 | #define AAC_MAX_HRRQ 64 | |
109 | ||
1da177e4 LT |
110 | /* |
111 | * These macros convert from physical channels to virtual channels | |
112 | */ | |
113 | #define CONTAINER_CHANNEL (0) | |
1da177e4 LT |
114 | #define CONTAINER_TO_CHANNEL(cont) (CONTAINER_CHANNEL) |
115 | #define CONTAINER_TO_ID(cont) (cont) | |
116 | #define CONTAINER_TO_LUN(cont) (0) | |
117 | ||
495c0217 | 118 | #define PMC_DEVICE_S6 0x28b |
2b4df6ea MR |
119 | #define PMC_DEVICE_S7 0x28c |
120 | #define PMC_DEVICE_S8 0x28d | |
121 | #define PMC_DEVICE_S9 0x28f | |
122 | ||
e2efe7aa MS |
123 | #define aac_phys_to_logical(x) ((x)+1) |
124 | #define aac_logical_to_phys(x) ((x)?(x)-1:0) | |
1da177e4 | 125 | |
b9fb54b4 RAR |
126 | /* |
127 | * These macros are for keeping track of | |
128 | * character device state. | |
129 | */ | |
130 | #define AAC_CHARDEV_UNREGISTERED (-1) | |
131 | #define AAC_CHARDEV_NEEDS_REINIT (-2) | |
132 | ||
1da177e4 LT |
133 | /* #define AAC_DETAILED_STATUS_INFO */ |
134 | ||
135 | struct diskparm | |
136 | { | |
137 | int heads; | |
138 | int sectors; | |
139 | int cylinders; | |
140 | }; | |
141 | ||
142 | ||
143 | /* | |
74ee9d52 | 144 | * Firmware constants |
1da177e4 | 145 | */ |
8ce3eca4 | 146 | |
1da177e4 | 147 | #define CT_NONE 0 |
8ce3eca4 | 148 | #define CT_OK 218 |
1da177e4 LT |
149 | #define FT_FILESYS 8 /* ADAPTEC's "FSA"(tm) filesystem */ |
150 | #define FT_DRIVE 9 /* physical disk - addressable in scsi by bus/id/lun */ | |
1da177e4 LT |
151 | |
152 | /* | |
153 | * Host side memory scatter gather list | |
154 | * Used by the adapter for read, write, and readdirplus operations | |
155 | * We have separate 32 and 64 bit version because even | |
156 | * on 64 bit systems not all cards support the 64 bit version | |
157 | */ | |
158 | struct sgentry { | |
56b58712 MH |
159 | __le32 addr; /* 32-bit address. */ |
160 | __le32 count; /* Length. */ | |
161 | }; | |
162 | ||
163 | struct user_sgentry { | |
1da177e4 LT |
164 | u32 addr; /* 32-bit address. */ |
165 | u32 count; /* Length. */ | |
166 | }; | |
167 | ||
168 | struct sgentry64 { | |
56b58712 MH |
169 | __le32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */ |
170 | __le32 count; /* Length. */ | |
171 | }; | |
172 | ||
173 | struct user_sgentry64 { | |
1da177e4 LT |
174 | u32 addr[2]; /* 64-bit addr. 2 pieces for data alignment */ |
175 | u32 count; /* Length. */ | |
176 | }; | |
177 | ||
0e68c003 MH |
178 | struct sgentryraw { |
179 | __le32 next; /* reserved for F/W use */ | |
180 | __le32 prev; /* reserved for F/W use */ | |
181 | __le32 addr[2]; | |
182 | __le32 count; | |
183 | __le32 flags; /* reserved for F/W use */ | |
184 | }; | |
185 | ||
186 | struct user_sgentryraw { | |
187 | u32 next; /* reserved for F/W use */ | |
188 | u32 prev; /* reserved for F/W use */ | |
189 | u32 addr[2]; | |
190 | u32 count; | |
191 | u32 flags; /* reserved for F/W use */ | |
192 | }; | |
193 | ||
85d22bbf MR |
194 | struct sge_ieee1212 { |
195 | u32 addrLow; | |
196 | u32 addrHigh; | |
197 | u32 length; | |
198 | u32 flags; | |
199 | }; | |
200 | ||
1da177e4 LT |
201 | /* |
202 | * SGMAP | |
203 | * | |
204 | * This is the SGMAP structure for all commands that use | |
205 | * 32-bit addressing. | |
206 | */ | |
207 | ||
208 | struct sgmap { | |
56b58712 | 209 | __le32 count; |
8ce3eca4 | 210 | struct sgentry sg[1]; |
1da177e4 LT |
211 | }; |
212 | ||
56b58712 | 213 | struct user_sgmap { |
1da177e4 | 214 | u32 count; |
8ce3eca4 | 215 | struct user_sgentry sg[1]; |
56b58712 MH |
216 | }; |
217 | ||
218 | struct sgmap64 { | |
219 | __le32 count; | |
1da177e4 LT |
220 | struct sgentry64 sg[1]; |
221 | }; | |
222 | ||
56b58712 MH |
223 | struct user_sgmap64 { |
224 | u32 count; | |
225 | struct user_sgentry64 sg[1]; | |
226 | }; | |
227 | ||
0e68c003 MH |
228 | struct sgmapraw { |
229 | __le32 count; | |
230 | struct sgentryraw sg[1]; | |
231 | }; | |
232 | ||
233 | struct user_sgmapraw { | |
234 | u32 count; | |
235 | struct user_sgentryraw sg[1]; | |
236 | }; | |
237 | ||
1da177e4 LT |
238 | struct creation_info |
239 | { | |
8ce3eca4 SM |
240 | u8 buildnum; /* e.g., 588 */ |
241 | u8 usec; /* e.g., 588 */ | |
242 | u8 via; /* e.g., 1 = FSU, | |
243 | * 2 = API | |
1da177e4 | 244 | */ |
8ce3eca4 | 245 | u8 year; /* e.g., 1997 = 97 */ |
56b58712 | 246 | __le32 date; /* |
8ce3eca4 SM |
247 | * unsigned Month :4; // 1 - 12 |
248 | * unsigned Day :6; // 1 - 32 | |
249 | * unsigned Hour :6; // 0 - 23 | |
250 | * unsigned Minute :6; // 0 - 60 | |
251 | * unsigned Second :6; // 0 - 60 | |
1da177e4 | 252 | */ |
56b58712 | 253 | __le32 serial[2]; /* e.g., 0x1DEADB0BFAFAF001 */ |
1da177e4 LT |
254 | }; |
255 | ||
256 | ||
257 | /* | |
258 | * Define all the constants needed for the communication interface | |
259 | */ | |
260 | ||
261 | /* | |
262 | * Define how many queue entries each queue will have and the total | |
263 | * number of entries for the entire communication interface. Also define | |
264 | * how many queues we support. | |
265 | * | |
266 | * This has to match the controller | |
267 | */ | |
268 | ||
269 | #define NUMBER_OF_COMM_QUEUES 8 // 4 command; 4 response | |
270 | #define HOST_HIGH_CMD_ENTRIES 4 | |
271 | #define HOST_NORM_CMD_ENTRIES 8 | |
272 | #define ADAP_HIGH_CMD_ENTRIES 4 | |
273 | #define ADAP_NORM_CMD_ENTRIES 512 | |
274 | #define HOST_HIGH_RESP_ENTRIES 4 | |
275 | #define HOST_NORM_RESP_ENTRIES 512 | |
276 | #define ADAP_HIGH_RESP_ENTRIES 4 | |
277 | #define ADAP_NORM_RESP_ENTRIES 8 | |
278 | ||
279 | #define TOTAL_QUEUE_ENTRIES \ | |
280 | (HOST_NORM_CMD_ENTRIES + HOST_HIGH_CMD_ENTRIES + ADAP_NORM_CMD_ENTRIES + ADAP_HIGH_CMD_ENTRIES + \ | |
281 | HOST_NORM_RESP_ENTRIES + HOST_HIGH_RESP_ENTRIES + ADAP_NORM_RESP_ENTRIES + ADAP_HIGH_RESP_ENTRIES) | |
282 | ||
283 | ||
284 | /* | |
285 | * Set the queues on a 16 byte alignment | |
286 | */ | |
8ce3eca4 | 287 | |
1da177e4 LT |
288 | #define QUEUE_ALIGNMENT 16 |
289 | ||
290 | /* | |
291 | * The queue headers define the Communication Region queues. These | |
292 | * are physically contiguous and accessible by both the adapter and the | |
293 | * host. Even though all queue headers are in the same contiguous block | |
294 | * they will be represented as individual units in the data structures. | |
295 | */ | |
296 | ||
297 | struct aac_entry { | |
56b58712 MH |
298 | __le32 size; /* Size in bytes of Fib which this QE points to */ |
299 | __le32 addr; /* Receiver address of the FIB */ | |
1da177e4 LT |
300 | }; |
301 | ||
302 | /* | |
303 | * The adapter assumes the ProducerIndex and ConsumerIndex are grouped | |
304 | * adjacently and in that order. | |
305 | */ | |
8ce3eca4 | 306 | |
1da177e4 | 307 | struct aac_qhdr { |
8ce3eca4 | 308 | __le64 header_addr;/* Address to hand the adapter to access |
56b58712 MH |
309 | to this queue head */ |
310 | __le32 *producer; /* The producer index for this queue (host address) */ | |
311 | __le32 *consumer; /* The consumer index for this queue (host address) */ | |
1da177e4 LT |
312 | }; |
313 | ||
314 | /* | |
315 | * Define all the events which the adapter would like to notify | |
316 | * the host of. | |
317 | */ | |
8ce3eca4 | 318 | |
1da177e4 LT |
319 | #define HostNormCmdQue 1 /* Change in host normal priority command queue */ |
320 | #define HostHighCmdQue 2 /* Change in host high priority command queue */ | |
321 | #define HostNormRespQue 3 /* Change in host normal priority response queue */ | |
322 | #define HostHighRespQue 4 /* Change in host high priority response queue */ | |
323 | #define AdapNormRespNotFull 5 | |
324 | #define AdapHighRespNotFull 6 | |
325 | #define AdapNormCmdNotFull 7 | |
326 | #define AdapHighCmdNotFull 8 | |
327 | #define SynchCommandComplete 9 | |
328 | #define AdapInternalError 0xfe /* The adapter detected an internal error shutting down */ | |
329 | ||
330 | /* | |
331 | * Define all the events the host wishes to notify the | |
332 | * adapter of. The first four values much match the Qid the | |
333 | * corresponding queue. | |
334 | */ | |
335 | ||
336 | #define AdapNormCmdQue 2 | |
337 | #define AdapHighCmdQue 3 | |
338 | #define AdapNormRespQue 6 | |
339 | #define AdapHighRespQue 7 | |
340 | #define HostShutdown 8 | |
341 | #define HostPowerFail 9 | |
342 | #define FatalCommError 10 | |
343 | #define HostNormRespNotFull 11 | |
344 | #define HostHighRespNotFull 12 | |
345 | #define HostNormCmdNotFull 13 | |
346 | #define HostHighCmdNotFull 14 | |
347 | #define FastIo 15 | |
348 | #define AdapPrintfDone 16 | |
349 | ||
350 | /* | |
351 | * Define all the queues that the adapter and host use to communicate | |
352 | * Number them to match the physical queue layout. | |
353 | */ | |
354 | ||
355 | enum aac_queue_types { | |
356 | HostNormCmdQueue = 0, /* Adapter to host normal priority command traffic */ | |
357 | HostHighCmdQueue, /* Adapter to host high priority command traffic */ | |
358 | AdapNormCmdQueue, /* Host to adapter normal priority command traffic */ | |
359 | AdapHighCmdQueue, /* Host to adapter high priority command traffic */ | |
360 | HostNormRespQueue, /* Adapter to host normal priority response traffic */ | |
361 | HostHighRespQueue, /* Adapter to host high priority response traffic */ | |
362 | AdapNormRespQueue, /* Host to adapter normal priority response traffic */ | |
363 | AdapHighRespQueue /* Host to adapter high priority response traffic */ | |
364 | }; | |
365 | ||
366 | /* | |
367 | * Assign type values to the FSA communication data structures | |
368 | */ | |
369 | ||
370 | #define FIB_MAGIC 0x0001 | |
85d22bbf MR |
371 | #define FIB_MAGIC2 0x0004 |
372 | #define FIB_MAGIC2_64 0x0005 | |
1da177e4 LT |
373 | |
374 | /* | |
375 | * Define the priority levels the FSA communication routines support. | |
376 | */ | |
377 | ||
378 | #define FsaNormal 1 | |
1da177e4 | 379 | |
e8b12f0f MR |
380 | /* transport FIB header (PMC) */ |
381 | struct aac_fib_xporthdr { | |
382 | u64 HostAddress; /* FIB host address w/o xport header */ | |
383 | u32 Size; /* FIB size excluding xport header */ | |
384 | u32 Handle; /* driver handle to reference the FIB */ | |
385 | u64 Reserved[2]; | |
386 | }; | |
387 | ||
388 | #define ALIGN32 32 | |
389 | ||
1da177e4 LT |
390 | /* |
391 | * Define the FIB. The FIB is the where all the requested data and | |
392 | * command information are put to the application on the FSA adapter. | |
393 | */ | |
394 | ||
395 | struct aac_fibhdr { | |
56b58712 MH |
396 | __le32 XferState; /* Current transfer state for this CCB */ |
397 | __le16 Command; /* Routing information for the destination */ | |
398 | u8 StructType; /* Type FIB */ | |
85d22bbf | 399 | u8 Unused; /* Unused */ |
56b58712 | 400 | __le16 Size; /* Size of this FIB in bytes */ |
8ce3eca4 | 401 | __le16 SenderSize; /* Size of the FIB in the sender |
56b58712 MH |
402 | (for response sizing) */ |
403 | __le32 SenderFibAddress; /* Host defined data in the FIB */ | |
1da177e4 | 404 | union { |
85d22bbf MR |
405 | __le32 ReceiverFibAddress;/* Logical address of this FIB for |
406 | the adapter (old) */ | |
407 | __le32 SenderFibAddressHigh;/* upper 32bit of phys. FIB address */ | |
408 | __le32 TimeStamp; /* otherwise timestamp for FW internal use */ | |
409 | } u; | |
3ffd6c5a | 410 | __le32 Handle; /* FIB handle used for MSGU commnunication */ |
85d22bbf MR |
411 | u32 Previous; /* FW internal use */ |
412 | u32 Next; /* FW internal use */ | |
1da177e4 LT |
413 | }; |
414 | ||
1da177e4 LT |
415 | struct hw_fib { |
416 | struct aac_fibhdr header; | |
7c00ffa3 | 417 | u8 data[512-sizeof(struct aac_fibhdr)]; // Command specific data |
1da177e4 LT |
418 | }; |
419 | ||
420 | /* | |
421 | * FIB commands | |
422 | */ | |
423 | ||
8ce3eca4 | 424 | #define TestCommandResponse 1 |
1da177e4 LT |
425 | #define TestAdapterCommand 2 |
426 | /* | |
427 | * Lowlevel and comm commands | |
428 | */ | |
429 | #define LastTestCommand 100 | |
430 | #define ReinitHostNormCommandQueue 101 | |
431 | #define ReinitHostHighCommandQueue 102 | |
432 | #define ReinitHostHighRespQueue 103 | |
433 | #define ReinitHostNormRespQueue 104 | |
434 | #define ReinitAdapNormCommandQueue 105 | |
435 | #define ReinitAdapHighCommandQueue 107 | |
436 | #define ReinitAdapHighRespQueue 108 | |
437 | #define ReinitAdapNormRespQueue 109 | |
438 | #define InterfaceShutdown 110 | |
439 | #define DmaCommandFib 120 | |
440 | #define StartProfile 121 | |
441 | #define TermProfile 122 | |
442 | #define SpeedTest 123 | |
443 | #define TakeABreakPt 124 | |
444 | #define RequestPerfData 125 | |
445 | #define SetInterruptDefTimer 126 | |
446 | #define SetInterruptDefCount 127 | |
447 | #define GetInterruptDefStatus 128 | |
448 | #define LastCommCommand 129 | |
449 | /* | |
450 | * Filesystem commands | |
451 | */ | |
452 | #define NuFileSystem 300 | |
453 | #define UFS 301 | |
454 | #define HostFileSystem 302 | |
455 | #define LastFileSystemCommand 303 | |
456 | /* | |
457 | * Container Commands | |
458 | */ | |
459 | #define ContainerCommand 500 | |
460 | #define ContainerCommand64 501 | |
0e68c003 | 461 | #define ContainerRawIo 502 |
85d22bbf | 462 | #define ContainerRawIo2 503 |
1da177e4 LT |
463 | /* |
464 | * Scsi Port commands (scsi passthrough) | |
465 | */ | |
466 | #define ScsiPortCommand 600 | |
467 | #define ScsiPortCommand64 601 | |
468 | /* | |
469 | * Misc house keeping and generic adapter initiated commands | |
470 | */ | |
471 | #define AifRequest 700 | |
472 | #define CheckRevision 701 | |
473 | #define FsaHostShutdown 702 | |
474 | #define RequestAdapterInfo 703 | |
475 | #define IsAdapterPaused 704 | |
476 | #define SendHostTime 705 | |
7c00ffa3 MH |
477 | #define RequestSupplementAdapterInfo 706 |
478 | #define LastMiscCommand 707 | |
1da177e4 | 479 | |
7c00ffa3 MH |
480 | /* |
481 | * Commands that will target the failover level on the FSA adapter | |
482 | */ | |
1da177e4 LT |
483 | |
484 | enum fib_xfer_state { | |
8ce3eca4 SM |
485 | HostOwned = (1<<0), |
486 | AdapterOwned = (1<<1), | |
487 | FibInitialized = (1<<2), | |
488 | FibEmpty = (1<<3), | |
489 | AllocatedFromPool = (1<<4), | |
490 | SentFromHost = (1<<5), | |
491 | SentFromAdapter = (1<<6), | |
492 | ResponseExpected = (1<<7), | |
493 | NoResponseExpected = (1<<8), | |
494 | AdapterProcessed = (1<<9), | |
495 | HostProcessed = (1<<10), | |
496 | HighPriority = (1<<11), | |
497 | NormalPriority = (1<<12), | |
1da177e4 LT |
498 | Async = (1<<13), |
499 | AsyncIo = (1<<13), // rpbfix: remove with new regime | |
500 | PageFileIo = (1<<14), // rpbfix: remove with new regime | |
501 | ShutdownRequest = (1<<15), | |
502 | LazyWrite = (1<<16), // rpbfix: remove with new regime | |
503 | AdapterMicroFib = (1<<17), | |
504 | BIOSFibPath = (1<<18), | |
505 | FastResponseCapable = (1<<19), | |
e8b12f0f MR |
506 | ApiFib = (1<<20), /* Its an API Fib */ |
507 | /* PMC NEW COMM: There is no more AIF data pending */ | |
508 | NoMoreAifDataAvailable = (1<<21) | |
1da177e4 LT |
509 | }; |
510 | ||
511 | /* | |
512 | * The following defines needs to be updated any time there is an | |
513 | * incompatible change made to the aac_init structure. | |
514 | */ | |
515 | ||
516 | #define ADAPTER_INIT_STRUCT_REVISION 3 | |
7c00ffa3 | 517 | #define ADAPTER_INIT_STRUCT_REVISION_4 4 // rocket science |
e8b12f0f | 518 | #define ADAPTER_INIT_STRUCT_REVISION_6 6 /* PMC src */ |
85d22bbf | 519 | #define ADAPTER_INIT_STRUCT_REVISION_7 7 /* Denali */ |
d1ef4da8 | 520 | #define ADAPTER_INIT_STRUCT_REVISION_8 8 // Thor |
1da177e4 | 521 | |
d1ef4da8 | 522 | union aac_init |
1da177e4 | 523 | { |
d1ef4da8 RAR |
524 | struct _r7 { |
525 | __le32 init_struct_revision; | |
526 | __le32 no_of_msix_vectors; | |
527 | __le32 fsrev; | |
528 | __le32 comm_header_address; | |
529 | __le32 fast_io_comm_area_address; | |
530 | __le32 adapter_fibs_physical_address; | |
531 | __le32 adapter_fibs_virtual_address; | |
532 | __le32 adapter_fibs_size; | |
533 | __le32 adapter_fib_align; | |
534 | __le32 printfbuf; | |
535 | __le32 printfbufsiz; | |
536 | /* number of 4k pages of host phys. mem. */ | |
537 | __le32 host_phys_mem_pages; | |
538 | /* number of seconds since 1970. */ | |
539 | __le32 host_elapsed_seconds; | |
540 | /* ADAPTER_INIT_STRUCT_REVISION_4 begins here */ | |
541 | __le32 init_flags; /* flags for supported features */ | |
7c00ffa3 | 542 | #define INITFLAGS_NEW_COMM_SUPPORTED 0x00000001 |
655d722c MS |
543 | #define INITFLAGS_DRIVER_USES_UTC_TIME 0x00000010 |
544 | #define INITFLAGS_DRIVER_SUPPORTS_PM 0x00000020 | |
85d22bbf MR |
545 | #define INITFLAGS_NEW_COMM_TYPE1_SUPPORTED 0x00000040 |
546 | #define INITFLAGS_FAST_JBOD_SUPPORTED 0x00000080 | |
547 | #define INITFLAGS_NEW_COMM_TYPE2_SUPPORTED 0x00000100 | |
d1ef4da8 RAR |
548 | #define INITFLAGS_DRIVER_SUPPORTS_HBA_MODE 0x00000400 |
549 | __le32 max_io_commands; /* max outstanding commands */ | |
550 | __le32 max_io_size; /* largest I/O command */ | |
551 | __le32 max_fib_size; /* largest FIB to adapter */ | |
552 | /* ADAPTER_INIT_STRUCT_REVISION_5 begins here */ | |
553 | __le32 max_num_aif; /* max number of aif */ | |
554 | /* ADAPTER_INIT_STRUCT_REVISION_6 begins here */ | |
555 | /* Host RRQ (response queue) for SRC */ | |
556 | __le32 host_rrq_addr_low; | |
557 | __le32 host_rrq_addr_high; | |
558 | } r7; | |
559 | struct _r8 { | |
560 | /* ADAPTER_INIT_STRUCT_REVISION_8 */ | |
561 | __le32 init_struct_revision; | |
562 | __le32 rr_queue_count; | |
563 | __le32 host_elapsed_seconds; /* number of secs since 1970. */ | |
564 | __le32 init_flags; | |
565 | __le32 max_io_size; /* largest I/O command */ | |
566 | __le32 max_num_aif; /* max number of aif */ | |
567 | __le32 reserved1; | |
568 | __le32 reserved2; | |
569 | struct _rrq { | |
570 | __le32 host_addr_low; | |
571 | __le32 host_addr_high; | |
572 | __le16 msix_id; | |
573 | __le16 element_count; | |
574 | __le16 comp_thresh; | |
575 | __le16 unused; | |
576 | } rrq[1]; /* up to 64 RRQ addresses */ | |
577 | } r8; | |
1da177e4 LT |
578 | }; |
579 | ||
580 | enum aac_log_level { | |
581 | LOG_AAC_INIT = 10, | |
582 | LOG_AAC_INFORMATIONAL = 20, | |
583 | LOG_AAC_WARNING = 30, | |
584 | LOG_AAC_LOW_ERROR = 40, | |
585 | LOG_AAC_MEDIUM_ERROR = 50, | |
586 | LOG_AAC_HIGH_ERROR = 60, | |
587 | LOG_AAC_PANIC = 70, | |
588 | LOG_AAC_DEBUG = 80, | |
589 | LOG_AAC_WINDBG_PRINT = 90 | |
590 | }; | |
591 | ||
592 | #define FSAFS_NTC_GET_ADAPTER_FIB_CONTEXT 0x030b | |
593 | #define FSAFS_NTC_FIB_CONTEXT 0x030c | |
594 | ||
595 | struct aac_dev; | |
8e0c5ebd | 596 | struct fib; |
e8f32de5 | 597 | struct scsi_cmnd; |
1da177e4 LT |
598 | |
599 | struct adapter_ops | |
600 | { | |
28713324 | 601 | /* Low level operations */ |
1da177e4 LT |
602 | void (*adapter_interrupt)(struct aac_dev *dev); |
603 | void (*adapter_notify)(struct aac_dev *dev, u32 event); | |
bd1aac80 | 604 | void (*adapter_disable_int)(struct aac_dev *dev); |
28713324 | 605 | void (*adapter_enable_int)(struct aac_dev *dev); |
7c00ffa3 | 606 | int (*adapter_sync_cmd)(struct aac_dev *dev, u32 command, u32 p1, u32 p2, u32 p3, u32 p4, u32 p5, u32 p6, u32 *status, u32 *r1, u32 *r2, u32 *r3, u32 *r4); |
1da177e4 | 607 | int (*adapter_check_health)(struct aac_dev *dev); |
8418852d | 608 | int (*adapter_restart)(struct aac_dev *dev, int bled); |
de665f28 | 609 | void (*adapter_start)(struct aac_dev *dev); |
28713324 | 610 | /* Transport operations */ |
76a7f8fd | 611 | int (*adapter_ioremap)(struct aac_dev * dev, u32 size); |
476834c2 | 612 | irq_handler_t adapter_intr; |
28713324 MH |
613 | /* Packet operations */ |
614 | int (*adapter_deliver)(struct fib * fib); | |
e8f32de5 MH |
615 | int (*adapter_bounds)(struct aac_dev * dev, struct scsi_cmnd * cmd, u64 lba); |
616 | int (*adapter_read)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count); | |
9d399cc7 | 617 | int (*adapter_write)(struct fib * fib, struct scsi_cmnd * cmd, u64 lba, u32 count, int fua); |
e8f32de5 | 618 | int (*adapter_scsi)(struct fib * fib, struct scsi_cmnd * cmd); |
28713324 MH |
619 | /* Administrative operations */ |
620 | int (*adapter_comm)(struct aac_dev * dev, int comm); | |
1da177e4 LT |
621 | }; |
622 | ||
623 | /* | |
624 | * Define which interrupt handler needs to be installed | |
625 | */ | |
626 | ||
627 | struct aac_driver_ident | |
628 | { | |
8ce3eca4 | 629 | int (*init)(struct aac_dev *dev); |
1da177e4 LT |
630 | char * name; |
631 | char * vname; | |
632 | char * model; | |
633 | u16 channels; | |
634 | int quirks; | |
635 | }; | |
636 | /* | |
8ce3eca4 | 637 | * Some adapter firmware needs communication memory |
1da177e4 LT |
638 | * below 2gig. This tells the init function to set the |
639 | * dma mask such that fib memory will be allocated where the | |
640 | * adapter firmware can get to it. | |
641 | */ | |
642 | #define AAC_QUIRK_31BIT 0x0001 | |
643 | ||
644 | /* | |
645 | * Some adapter firmware, when the raid card's cache is turned off, can not | |
646 | * split up scatter gathers in order to deal with the limits of the | |
647 | * underlying CHIM. This limit is 34 scatter gather elements. | |
648 | */ | |
649 | #define AAC_QUIRK_34SG 0x0002 | |
650 | ||
651 | /* | |
652 | * This adapter is a slave (no Firmware) | |
653 | */ | |
654 | #define AAC_QUIRK_SLAVE 0x0004 | |
655 | ||
656 | /* | |
657 | * This adapter is a master. | |
658 | */ | |
659 | #define AAC_QUIRK_MASTER 0x0008 | |
660 | ||
db39363c MH |
661 | /* |
662 | * Some adapter firmware perform poorly when it must split up scatter gathers | |
663 | * in order to deal with the limits of the underlying CHIM. This limit in this | |
664 | * class of adapters is 17 scatter gather elements. | |
665 | */ | |
666 | #define AAC_QUIRK_17SG 0x0010 | |
667 | ||
94cf6ba1 SM |
668 | /* |
669 | * Some adapter firmware does not support 64 bit scsi passthrough | |
670 | * commands. | |
671 | */ | |
672 | #define AAC_QUIRK_SCSI_32 0x0020 | |
673 | ||
787ab6e9 HR |
674 | /* |
675 | * SRC based adapters support the AifReqEvent functions | |
676 | */ | |
677 | #define AAC_QUIRK_SRC 0x0040 | |
678 | ||
1da177e4 LT |
679 | /* |
680 | * The adapter interface specs all queues to be located in the same | |
af901ca1 | 681 | * physically contiguous block. The host structure that defines the |
1da177e4 | 682 | * commuication queues will assume they are each a separate physically |
af901ca1 AGR |
683 | * contiguous memory region that will support them all being one big |
684 | * contiguous block. | |
1da177e4 LT |
685 | * There is a command and response queue for each level and direction of |
686 | * commuication. These regions are accessed by both the host and adapter. | |
687 | */ | |
8ce3eca4 | 688 | |
1da177e4 | 689 | struct aac_queue { |
8ce3eca4 | 690 | u64 logical; /*address we give the adapter */ |
1da177e4 | 691 | struct aac_entry *base; /*system virtual address */ |
8ce3eca4 SM |
692 | struct aac_qhdr headers; /*producer,consumer q headers*/ |
693 | u32 entries; /*Number of queue entries */ | |
1da177e4 LT |
694 | wait_queue_head_t qfull; /*Event to wait on if q full */ |
695 | wait_queue_head_t cmdready; /*Cmd ready from the adapter */ | |
8ce3eca4 SM |
696 | /* This is only valid for adapter to host command queues. */ |
697 | spinlock_t *lock; /* Spinlock for this queue must take this lock before accessing the lock */ | |
1da177e4 | 698 | spinlock_t lockdata; /* Actual lock (used only on one side of the lock) */ |
8ce3eca4 SM |
699 | struct list_head cmdq; /* A queue of FIBs which need to be prcessed by the FS thread. This is */ |
700 | /* only valid for command queues which receive entries from the adapter. */ | |
ef616233 MR |
701 | /* Number of entries on outstanding queue. */ |
702 | atomic_t numpending; | |
1da177e4 LT |
703 | struct aac_dev * dev; /* Back pointer to adapter structure */ |
704 | }; | |
705 | ||
706 | /* | |
8ce3eca4 | 707 | * Message queues. The order here is important, see also the |
1da177e4 LT |
708 | * queue type ordering |
709 | */ | |
710 | ||
711 | struct aac_queue_block | |
712 | { | |
713 | struct aac_queue queue[8]; | |
714 | }; | |
715 | ||
716 | /* | |
717 | * SaP1 Message Unit Registers | |
718 | */ | |
8ce3eca4 | 719 | |
1da177e4 | 720 | struct sa_drawbridge_CSR { |
8ce3eca4 | 721 | /* Offset | Name */ |
1da177e4 LT |
722 | __le32 reserved[10]; /* 00h-27h | Reserved */ |
723 | u8 LUT_Offset; /* 28h | Lookup Table Offset */ | |
8ce3eca4 | 724 | u8 reserved1[3]; /* 29h-2bh | Reserved */ |
1da177e4 LT |
725 | __le32 LUT_Data; /* 2ch | Looup Table Data */ |
726 | __le32 reserved2[26]; /* 30h-97h | Reserved */ | |
727 | __le16 PRICLEARIRQ; /* 98h | Primary Clear Irq */ | |
728 | __le16 SECCLEARIRQ; /* 9ah | Secondary Clear Irq */ | |
729 | __le16 PRISETIRQ; /* 9ch | Primary Set Irq */ | |
730 | __le16 SECSETIRQ; /* 9eh | Secondary Set Irq */ | |
731 | __le16 PRICLEARIRQMASK;/* a0h | Primary Clear Irq Mask */ | |
732 | __le16 SECCLEARIRQMASK;/* a2h | Secondary Clear Irq Mask */ | |
733 | __le16 PRISETIRQMASK; /* a4h | Primary Set Irq Mask */ | |
734 | __le16 SECSETIRQMASK; /* a6h | Secondary Set Irq Mask */ | |
735 | __le32 MAILBOX0; /* a8h | Scratchpad 0 */ | |
736 | __le32 MAILBOX1; /* ach | Scratchpad 1 */ | |
737 | __le32 MAILBOX2; /* b0h | Scratchpad 2 */ | |
738 | __le32 MAILBOX3; /* b4h | Scratchpad 3 */ | |
739 | __le32 MAILBOX4; /* b8h | Scratchpad 4 */ | |
740 | __le32 MAILBOX5; /* bch | Scratchpad 5 */ | |
741 | __le32 MAILBOX6; /* c0h | Scratchpad 6 */ | |
742 | __le32 MAILBOX7; /* c4h | Scratchpad 7 */ | |
8ce3eca4 SM |
743 | __le32 ROM_Setup_Data; /* c8h | Rom Setup and Data */ |
744 | __le32 ROM_Control_Addr;/* cch | Rom Control and Address */ | |
1da177e4 LT |
745 | __le32 reserved3[12]; /* d0h-ffh | reserved */ |
746 | __le32 LUT[64]; /* 100h-1ffh | Lookup Table Entries */ | |
747 | }; | |
748 | ||
749 | #define Mailbox0 SaDbCSR.MAILBOX0 | |
750 | #define Mailbox1 SaDbCSR.MAILBOX1 | |
751 | #define Mailbox2 SaDbCSR.MAILBOX2 | |
752 | #define Mailbox3 SaDbCSR.MAILBOX3 | |
753 | #define Mailbox4 SaDbCSR.MAILBOX4 | |
754 | #define Mailbox5 SaDbCSR.MAILBOX5 | |
7c00ffa3 | 755 | #define Mailbox6 SaDbCSR.MAILBOX6 |
1da177e4 | 756 | #define Mailbox7 SaDbCSR.MAILBOX7 |
8ce3eca4 | 757 | |
1da177e4 LT |
758 | #define DoorbellReg_p SaDbCSR.PRISETIRQ |
759 | #define DoorbellReg_s SaDbCSR.SECSETIRQ | |
760 | #define DoorbellClrReg_p SaDbCSR.PRICLEARIRQ | |
761 | ||
762 | ||
763 | #define DOORBELL_0 0x0001 | |
764 | #define DOORBELL_1 0x0002 | |
765 | #define DOORBELL_2 0x0004 | |
766 | #define DOORBELL_3 0x0008 | |
767 | #define DOORBELL_4 0x0010 | |
768 | #define DOORBELL_5 0x0020 | |
769 | #define DOORBELL_6 0x0040 | |
770 | ||
8ce3eca4 | 771 | |
1da177e4 LT |
772 | #define PrintfReady DOORBELL_5 |
773 | #define PrintfDone DOORBELL_5 | |
8ce3eca4 | 774 | |
1da177e4 LT |
775 | struct sa_registers { |
776 | struct sa_drawbridge_CSR SaDbCSR; /* 98h - c4h */ | |
777 | }; | |
8ce3eca4 | 778 | |
1da177e4 | 779 | |
a6cd4549 | 780 | #define SA_INIT_NUM_MSIXVECTORS 1 |
d1ef4da8 | 781 | #define SA_MINIPORT_REVISION SA_INIT_NUM_MSIXVECTORS |
1da177e4 LT |
782 | |
783 | #define sa_readw(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) | |
8ce3eca4 | 784 | #define sa_readl(AEP, CSR) readl(&((AEP)->regs.sa->CSR)) |
1da177e4 LT |
785 | #define sa_writew(AEP, CSR, value) writew(value, &((AEP)->regs.sa->CSR)) |
786 | #define sa_writel(AEP, CSR, value) writel(value, &((AEP)->regs.sa->CSR)) | |
787 | ||
788 | /* | |
789 | * Rx Message Unit Registers | |
790 | */ | |
791 | ||
792 | struct rx_mu_registers { | |
793 | /* Local | PCI*| Name */ | |
794 | __le32 ARSR; /* 1300h | 00h | APIC Register Select Register */ | |
795 | __le32 reserved0; /* 1304h | 04h | Reserved */ | |
796 | __le32 AWR; /* 1308h | 08h | APIC Window Register */ | |
797 | __le32 reserved1; /* 130Ch | 0Ch | Reserved */ | |
798 | __le32 IMRx[2]; /* 1310h | 10h | Inbound Message Registers */ | |
799 | __le32 OMRx[2]; /* 1318h | 18h | Outbound Message Registers */ | |
800 | __le32 IDR; /* 1320h | 20h | Inbound Doorbell Register */ | |
8ce3eca4 | 801 | __le32 IISR; /* 1324h | 24h | Inbound Interrupt |
1da177e4 | 802 | Status Register */ |
8ce3eca4 SM |
803 | __le32 IIMR; /* 1328h | 28h | Inbound Interrupt |
804 | Mask Register */ | |
1da177e4 | 805 | __le32 ODR; /* 132Ch | 2Ch | Outbound Doorbell Register */ |
8ce3eca4 | 806 | __le32 OISR; /* 1330h | 30h | Outbound Interrupt |
1da177e4 | 807 | Status Register */ |
8ce3eca4 | 808 | __le32 OIMR; /* 1334h | 34h | Outbound Interrupt |
1da177e4 | 809 | Mask Register */ |
8e0c5ebd MH |
810 | __le32 reserved2; /* 1338h | 38h | Reserved */ |
811 | __le32 reserved3; /* 133Ch | 3Ch | Reserved */ | |
812 | __le32 InboundQueue;/* 1340h | 40h | Inbound Queue Port relative to firmware */ | |
813 | __le32 OutboundQueue;/*1344h | 44h | Outbound Queue Port relative to firmware */ | |
8ce3eca4 SM |
814 | /* * Must access through ATU Inbound |
815 | Translation Window */ | |
1da177e4 LT |
816 | }; |
817 | ||
818 | struct rx_inbound { | |
819 | __le32 Mailbox[8]; | |
820 | }; | |
821 | ||
1da177e4 LT |
822 | #define INBOUNDDOORBELL_0 0x00000001 |
823 | #define INBOUNDDOORBELL_1 0x00000002 | |
824 | #define INBOUNDDOORBELL_2 0x00000004 | |
825 | #define INBOUNDDOORBELL_3 0x00000008 | |
826 | #define INBOUNDDOORBELL_4 0x00000010 | |
827 | #define INBOUNDDOORBELL_5 0x00000020 | |
828 | #define INBOUNDDOORBELL_6 0x00000040 | |
829 | ||
830 | #define OUTBOUNDDOORBELL_0 0x00000001 | |
831 | #define OUTBOUNDDOORBELL_1 0x00000002 | |
832 | #define OUTBOUNDDOORBELL_2 0x00000004 | |
833 | #define OUTBOUNDDOORBELL_3 0x00000008 | |
834 | #define OUTBOUNDDOORBELL_4 0x00000010 | |
835 | ||
836 | #define InboundDoorbellReg MUnit.IDR | |
837 | #define OutboundDoorbellReg MUnit.ODR | |
838 | ||
839 | struct rx_registers { | |
e8b12f0f | 840 | struct rx_mu_registers MUnit; /* 1300h - 1347h */ |
8e0c5ebd | 841 | __le32 reserved1[2]; /* 1348h - 134ch */ |
1da177e4 LT |
842 | struct rx_inbound IndexRegs; |
843 | }; | |
844 | ||
845 | #define rx_readb(AEP, CSR) readb(&((AEP)->regs.rx->CSR)) | |
846 | #define rx_readl(AEP, CSR) readl(&((AEP)->regs.rx->CSR)) | |
847 | #define rx_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rx->CSR)) | |
848 | #define rx_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rx->CSR)) | |
849 | ||
850 | /* | |
851 | * Rkt Message Unit Registers (same as Rx, except a larger reserve region) | |
852 | */ | |
853 | ||
854 | #define rkt_mu_registers rx_mu_registers | |
855 | #define rkt_inbound rx_inbound | |
856 | ||
857 | struct rkt_registers { | |
e8b12f0f | 858 | struct rkt_mu_registers MUnit; /* 1300h - 1347h */ |
8e0c5ebd | 859 | __le32 reserved1[1006]; /* 1348h - 22fch */ |
1da177e4 LT |
860 | struct rkt_inbound IndexRegs; /* 2300h - */ |
861 | }; | |
862 | ||
863 | #define rkt_readb(AEP, CSR) readb(&((AEP)->regs.rkt->CSR)) | |
864 | #define rkt_readl(AEP, CSR) readl(&((AEP)->regs.rkt->CSR)) | |
865 | #define rkt_writeb(AEP, CSR, value) writeb(value, &((AEP)->regs.rkt->CSR)) | |
866 | #define rkt_writel(AEP, CSR, value) writel(value, &((AEP)->regs.rkt->CSR)) | |
867 | ||
e8b12f0f MR |
868 | /* |
869 | * PMC SRC message unit registers | |
870 | */ | |
871 | ||
872 | #define src_inbound rx_inbound | |
873 | ||
874 | struct src_mu_registers { | |
3ffd6c5a RAR |
875 | /* PCI*| Name */ |
876 | __le32 reserved0[6]; /* 00h | Reserved */ | |
877 | __le32 IOAR[2]; /* 18h | IOA->host interrupt register */ | |
878 | __le32 IDR; /* 20h | Inbound Doorbell Register */ | |
879 | __le32 IISR; /* 24h | Inbound Int. Status Register */ | |
880 | __le32 reserved1[3]; /* 28h | Reserved */ | |
881 | __le32 OIMR; /* 34h | Outbound Int. Mask Register */ | |
882 | __le32 reserved2[25]; /* 38h | Reserved */ | |
883 | __le32 ODR_R; /* 9ch | Outbound Doorbell Read */ | |
884 | __le32 ODR_C; /* a0h | Outbound Doorbell Clear */ | |
885 | __le32 reserved3[3]; /* a4h | Reserved */ | |
886 | __le32 SCR0; /* b0h | Scratchpad 0 */ | |
887 | __le32 reserved4[2]; /* b4h | Reserved */ | |
888 | __le32 OMR; /* bch | Outbound Message Register */ | |
e8b12f0f MR |
889 | __le32 IQ_L; /* c0h | Inbound Queue (Low address) */ |
890 | __le32 IQ_H; /* c4h | Inbound Queue (High address) */ | |
495c0217 | 891 | __le32 ODR_MSI; /* c8h | MSI register for sync./AIF */ |
e8b12f0f MR |
892 | }; |
893 | ||
894 | struct src_registers { | |
495c0217 | 895 | struct src_mu_registers MUnit; /* 00h - cbh */ |
11604612 MR |
896 | union { |
897 | struct { | |
495c0217 | 898 | __le32 reserved1[130789]; /* cch - 7fc5fh */ |
11604612 MR |
899 | struct src_inbound IndexRegs; /* 7fc60h */ |
900 | } tupelo; | |
901 | struct { | |
495c0217 | 902 | __le32 reserved1[973]; /* cch - fffh */ |
11604612 MR |
903 | struct src_inbound IndexRegs; /* 1000h */ |
904 | } denali; | |
905 | } u; | |
e8b12f0f MR |
906 | }; |
907 | ||
908 | #define src_readb(AEP, CSR) readb(&((AEP)->regs.src.bar0->CSR)) | |
909 | #define src_readl(AEP, CSR) readl(&((AEP)->regs.src.bar0->CSR)) | |
910 | #define src_writeb(AEP, CSR, value) writeb(value, \ | |
911 | &((AEP)->regs.src.bar0->CSR)) | |
912 | #define src_writel(AEP, CSR, value) writel(value, \ | |
913 | &((AEP)->regs.src.bar0->CSR)) | |
c6992781 MR |
914 | #if defined(writeq) |
915 | #define src_writeq(AEP, CSR, value) writeq(value, \ | |
916 | &((AEP)->regs.src.bar0->CSR)) | |
917 | #endif | |
e8b12f0f MR |
918 | |
919 | #define SRC_ODR_SHIFT 12 | |
920 | #define SRC_IDR_SHIFT 9 | |
921 | ||
1da177e4 LT |
922 | typedef void (*fib_callback)(void *ctxt, struct fib *fibctx); |
923 | ||
924 | struct aac_fib_context { | |
8ce3eca4 SM |
925 | s16 type; // used for verification of structure |
926 | s16 size; | |
1da177e4 LT |
927 | u32 unique; // unique value representing this context |
928 | ulong jiffies; // used for cleanup - dmb changed to ulong | |
929 | struct list_head next; // used to link context's into a linked list | |
8ce3eca4 | 930 | struct semaphore wait_sem; // this is used to wait for the next fib to arrive. |
1da177e4 LT |
931 | int wait; // Set to true when thread is in WaitForSingleObject |
932 | unsigned long count; // total number of FIBs on FibList | |
933 | struct list_head fib_list; // this holds fibs and their attachd hw_fibs | |
934 | }; | |
935 | ||
936 | struct sense_data { | |
937 | u8 error_code; /* 70h (current errors), 71h(deferred errors) */ | |
938 | u8 valid:1; /* A valid bit of one indicates that the information */ | |
939 | /* field contains valid information as defined in the | |
940 | * SCSI-2 Standard. | |
941 | */ | |
942 | u8 segment_number; /* Only used for COPY, COMPARE, or COPY AND VERIFY Commands */ | |
943 | u8 sense_key:4; /* Sense Key */ | |
944 | u8 reserved:1; | |
945 | u8 ILI:1; /* Incorrect Length Indicator */ | |
946 | u8 EOM:1; /* End Of Medium - reserved for random access devices */ | |
947 | u8 filemark:1; /* Filemark - reserved for random access devices */ | |
948 | ||
8ce3eca4 SM |
949 | u8 information[4]; /* for direct-access devices, contains the unsigned |
950 | * logical block address or residue associated with | |
951 | * the sense key | |
1da177e4 LT |
952 | */ |
953 | u8 add_sense_len; /* number of additional sense bytes to follow this field */ | |
954 | u8 cmnd_info[4]; /* not used */ | |
955 | u8 ASC; /* Additional Sense Code */ | |
956 | u8 ASCQ; /* Additional Sense Code Qualifier */ | |
957 | u8 FRUC; /* Field Replaceable Unit Code - not used */ | |
958 | u8 bit_ptr:3; /* indicates which byte of the CDB or parameter data | |
959 | * was in error | |
960 | */ | |
8ce3eca4 | 961 | u8 BPV:1; /* bit pointer valid (BPV): 1- indicates that |
1da177e4 LT |
962 | * the bit_ptr field has valid value |
963 | */ | |
964 | u8 reserved2:2; | |
965 | u8 CD:1; /* command data bit: 1- illegal parameter in CDB. | |
966 | * 0- illegal parameter in data. | |
967 | */ | |
968 | u8 SKSV:1; | |
969 | u8 field_ptr[2]; /* byte of the CDB or parameter data in error */ | |
970 | }; | |
971 | ||
972 | struct fsa_dev_info { | |
973 | u64 last; | |
974 | u64 size; | |
975 | u32 type; | |
131256cf | 976 | u32 config_waiting_on; |
31876f32 | 977 | unsigned long config_waiting_stamp; |
1da177e4 | 978 | u16 queue_depth; |
131256cf | 979 | u8 config_needed; |
1da177e4 LT |
980 | u8 valid; |
981 | u8 ro; | |
982 | u8 locked; | |
983 | u8 deleted; | |
984 | char devname[8]; | |
985 | struct sense_data sense_data; | |
b836439f | 986 | u32 block_size; |
3ffd6c5a | 987 | u8 identifier[16]; |
1da177e4 LT |
988 | }; |
989 | ||
990 | struct fib { | |
991 | void *next; /* this is used by the allocator */ | |
992 | s16 type; | |
993 | s16 size; | |
994 | /* | |
995 | * The Adapter that this I/O is destined for. | |
996 | */ | |
8ce3eca4 | 997 | struct aac_dev *dev; |
1da177e4 LT |
998 | /* |
999 | * This is the event the sendfib routine will wait on if the | |
1000 | * caller did not pass one and this is synch io. | |
1001 | */ | |
8ce3eca4 | 1002 | struct semaphore event_wait; |
1da177e4 LT |
1003 | spinlock_t event_lock; |
1004 | ||
1005 | u32 done; /* gets set to 1 when fib is complete */ | |
8ce3eca4 SM |
1006 | fib_callback callback; |
1007 | void *callback_data; | |
1da177e4 | 1008 | u32 flags; // u32 dmb was ulong |
1da177e4 LT |
1009 | /* |
1010 | * And for the internal issue/reply queues (we may be able | |
1011 | * to merge these two) | |
1012 | */ | |
1013 | struct list_head fiblink; | |
8ce3eca4 | 1014 | void *data; |
3f4ce057 | 1015 | u32 vector_no; |
a8166a52 | 1016 | struct hw_fib *hw_fib_va; /* Actual shared object */ |
1da177e4 | 1017 | dma_addr_t hw_fib_pa; /* physical address of hw_fib*/ |
3ffd6c5a | 1018 | u32 hbacmd_size; /* cmd size for native */ |
1da177e4 LT |
1019 | }; |
1020 | ||
c83b11e3 RAR |
1021 | #define AAC_DEVTYPE_RAID_MEMBER 1 |
1022 | #define AAC_DEVTYPE_ARC_RAW 2 | |
1023 | #define AAC_DEVTYPE_NATIVE_RAW 3 | |
1024 | #define AAC_EXPOSE_DISK 0 | |
1025 | #define AAC_HIDE_DISK 3 | |
1026 | ||
1027 | struct aac_hba_map_info { | |
1028 | __le32 rmw_nexus; /* nexus for native HBA devices */ | |
1029 | u8 devtype; /* device type */ | |
1030 | u8 reset_state; /* 0 - no reset, 1..x - */ | |
1031 | /* after xth TM LUN reset */ | |
1032 | u8 expose; /*checks if to expose or not*/ | |
1033 | }; | |
1034 | ||
1da177e4 LT |
1035 | /* |
1036 | * Adapter Information Block | |
1037 | * | |
1038 | * This is returned by the RequestAdapterInfo block | |
1039 | */ | |
8ce3eca4 | 1040 | |
1da177e4 LT |
1041 | struct aac_adapter_info |
1042 | { | |
56b58712 MH |
1043 | __le32 platform; |
1044 | __le32 cpu; | |
1045 | __le32 subcpu; | |
1046 | __le32 clock; | |
1047 | __le32 execmem; | |
1048 | __le32 buffermem; | |
1049 | __le32 totalmem; | |
1050 | __le32 kernelrev; | |
1051 | __le32 kernelbuild; | |
1052 | __le32 monitorrev; | |
1053 | __le32 monitorbuild; | |
1054 | __le32 hwrev; | |
1055 | __le32 hwbuild; | |
1056 | __le32 biosrev; | |
1057 | __le32 biosbuild; | |
1058 | __le32 cluster; | |
8ce3eca4 | 1059 | __le32 clusterchannelmask; |
56b58712 MH |
1060 | __le32 serial[2]; |
1061 | __le32 battery; | |
1062 | __le32 options; | |
1063 | __le32 OEM; | |
1da177e4 LT |
1064 | }; |
1065 | ||
7c00ffa3 MH |
1066 | struct aac_supplement_adapter_info |
1067 | { | |
1068 | u8 AdapterTypeText[17+1]; | |
1069 | u8 Pad[2]; | |
1070 | __le32 FlashMemoryByteSize; | |
1071 | __le32 FlashImageId; | |
1072 | __le32 MaxNumberPorts; | |
1073 | __le32 Version; | |
1074 | __le32 FeatureBits; | |
1075 | u8 SlotNumber; | |
a45c863f | 1076 | u8 ReservedPad0[3]; |
7c00ffa3 MH |
1077 | u8 BuildDate[12]; |
1078 | __le32 CurrentNumberPorts; | |
a45c863f SM |
1079 | struct { |
1080 | u8 AssemblyPn[8]; | |
1081 | u8 FruPn[8]; | |
1082 | u8 BatteryFruPn[8]; | |
1083 | u8 EcVersionString[8]; | |
1084 | u8 Tsid[12]; | |
1085 | } VpdInfo; | |
1086 | __le32 FlashFirmwareRevision; | |
1087 | __le32 FlashFirmwareBuild; | |
1088 | __le32 RaidTypeMorphOptions; | |
1089 | __le32 FlashFirmwareBootRevision; | |
1090 | __le32 FlashFirmwareBootBuild; | |
1091 | u8 MfgPcbaSerialNo[12]; | |
1092 | u8 MfgWWNName[8]; | |
29c97684 | 1093 | __le32 SupportedOptions2; |
d8e96507 LA |
1094 | __le32 StructExpansion; |
1095 | /* StructExpansion == 1 */ | |
1096 | __le32 FeatureBits3; | |
1097 | __le32 SupportedPerformanceModes; | |
c83b11e3 RAR |
1098 | u8 HostBusType; /* uses HOST_BUS_TYPE_xxx defines */ |
1099 | u8 HostBusWidth; /* actual width in bits or links */ | |
1100 | u16 HostBusSpeed; /* actual bus speed/link rate in MHz */ | |
1101 | u8 MaxRRCDrives; /* max. number of ITP-RRC drives/pool */ | |
1102 | u8 MaxDiskXtasks; /* max. possible num of DiskX Tasks */ | |
1103 | ||
1104 | u8 CpldVerLoaded; | |
1105 | u8 CpldVerInFlash; | |
1106 | ||
1107 | __le64 MaxRRCCapacity; | |
1108 | __le32 CompiledMaxHistLogLevel; | |
1109 | u8 CustomBoardName[12]; | |
1110 | u16 SupportedCntlrMode; /* identify supported controller mode */ | |
1111 | u16 ReservedForFuture16; | |
1112 | __le32 SupportedOptions3; /* reserved for future options */ | |
1113 | ||
1114 | __le16 VirtDeviceBus; /* virt. SCSI device for Thor */ | |
1115 | __le16 VirtDeviceTarget; | |
1116 | __le16 VirtDeviceLUN; | |
1117 | __le16 Unused; | |
1118 | __le32 ReservedForFutureGrowth[68]; | |
1119 | ||
7c00ffa3 | 1120 | }; |
a3940da5 | 1121 | #define AAC_FEATURE_FALCON cpu_to_le32(0x00000010) |
cb1042f2 | 1122 | #define AAC_FEATURE_JBOD cpu_to_le32(0x08000000) |
655d722c MS |
1123 | /* SupportedOptions2 */ |
1124 | #define AAC_OPTION_MU_RESET cpu_to_le32(0x00000001) | |
1125 | #define AAC_OPTION_IGNORE_RESET cpu_to_le32(0x00000002) | |
1126 | #define AAC_OPTION_POWER_MANAGEMENT cpu_to_le32(0x00000004) | |
e8b12f0f | 1127 | #define AAC_OPTION_DOORBELL_RESET cpu_to_le32(0x00004000) |
b836439f MR |
1128 | /* 4KB sector size */ |
1129 | #define AAC_OPTION_VARIABLE_BLOCK_SIZE cpu_to_le32(0x00040000) | |
a7129a54 MR |
1130 | /* 240 simple volume support */ |
1131 | #define AAC_OPTION_SUPPORTED_240_VOLUMES cpu_to_le32(0x10000000) | |
7c00ffa3 MH |
1132 | #define AAC_SIS_VERSION_V3 3 |
1133 | #define AAC_SIS_SLOT_UNKNOWN 0xFF | |
1134 | ||
84971738 MH |
1135 | #define GetBusInfo 0x00000009 |
1136 | struct aac_bus_info { | |
1137 | __le32 Command; /* VM_Ioctl */ | |
1138 | __le32 ObjType; /* FT_DRIVE */ | |
1139 | __le32 MethodId; /* 1 = SCSI Layer */ | |
1140 | __le32 ObjectId; /* Handle */ | |
1141 | __le32 CtlCmd; /* GetBusInfo */ | |
1142 | }; | |
1143 | ||
1144 | struct aac_bus_info_response { | |
1145 | __le32 Status; /* ST_OK */ | |
1146 | __le32 ObjType; | |
1147 | __le32 MethodId; /* unused */ | |
1148 | __le32 ObjectId; /* unused */ | |
1149 | __le32 CtlCmd; /* unused */ | |
1150 | __le32 ProbeComplete; | |
1151 | __le32 BusCount; | |
1152 | __le32 TargetsPerBus; | |
1153 | u8 InitiatorBusId[10]; | |
1154 | u8 BusValid[10]; | |
1155 | }; | |
1156 | ||
1da177e4 LT |
1157 | /* |
1158 | * Battery platforms | |
1159 | */ | |
1160 | #define AAC_BAT_REQ_PRESENT (1) | |
1161 | #define AAC_BAT_REQ_NOTPRESENT (2) | |
1162 | #define AAC_BAT_OPT_PRESENT (3) | |
1163 | #define AAC_BAT_OPT_NOTPRESENT (4) | |
1164 | #define AAC_BAT_NOT_SUPPORTED (5) | |
1165 | /* | |
1166 | * cpu types | |
1167 | */ | |
1168 | #define AAC_CPU_SIMULATOR (1) | |
1169 | #define AAC_CPU_I960 (2) | |
1170 | #define AAC_CPU_STRONGARM (3) | |
1171 | ||
1172 | /* | |
1173 | * Supported Options | |
1174 | */ | |
1175 | #define AAC_OPT_SNAPSHOT cpu_to_le32(1) | |
1176 | #define AAC_OPT_CLUSTERS cpu_to_le32(1<<1) | |
1177 | #define AAC_OPT_WRITE_CACHE cpu_to_le32(1<<2) | |
1178 | #define AAC_OPT_64BIT_DATA cpu_to_le32(1<<3) | |
1179 | #define AAC_OPT_HOST_TIME_FIB cpu_to_le32(1<<4) | |
1180 | #define AAC_OPT_RAID50 cpu_to_le32(1<<5) | |
1181 | #define AAC_OPT_4GB_WINDOW cpu_to_le32(1<<6) | |
8ce3eca4 | 1182 | #define AAC_OPT_SCSI_UPGRADEABLE cpu_to_le32(1<<7) |
1da177e4 | 1183 | #define AAC_OPT_SOFT_ERR_REPORT cpu_to_le32(1<<8) |
8ce3eca4 | 1184 | #define AAC_OPT_SUPPORTED_RECONDITION cpu_to_le32(1<<9) |
1da177e4 LT |
1185 | #define AAC_OPT_SGMAP_HOST64 cpu_to_le32(1<<10) |
1186 | #define AAC_OPT_ALARM cpu_to_le32(1<<11) | |
1187 | #define AAC_OPT_NONDASD cpu_to_le32(1<<12) | |
8ce3eca4 | 1188 | #define AAC_OPT_SCSI_MANAGED cpu_to_le32(1<<13) |
1da177e4 LT |
1189 | #define AAC_OPT_RAID_SCSI_MODE cpu_to_le32(1<<14) |
1190 | #define AAC_OPT_SUPPLEMENT_ADAPTER_INFO cpu_to_le32(1<<16) | |
1191 | #define AAC_OPT_NEW_COMM cpu_to_le32(1<<17) | |
1192 | #define AAC_OPT_NEW_COMM_64 cpu_to_le32(1<<18) | |
d503e2fd | 1193 | #define AAC_OPT_EXTENDED cpu_to_le32(1<<23) |
e8b12f0f | 1194 | #define AAC_OPT_NEW_COMM_TYPE1 cpu_to_le32(1<<28) |
11604612 MR |
1195 | #define AAC_OPT_NEW_COMM_TYPE2 cpu_to_le32(1<<29) |
1196 | #define AAC_OPT_NEW_COMM_TYPE3 cpu_to_le32(1<<30) | |
1197 | #define AAC_OPT_NEW_COMM_TYPE4 cpu_to_le32(1<<31) | |
1198 | ||
d1ef4da8 RAR |
1199 | #define AAC_COMM_PRODUCER 0 |
1200 | #define AAC_COMM_MESSAGE 1 | |
1201 | #define AAC_COMM_MESSAGE_TYPE1 3 | |
1202 | #define AAC_COMM_MESSAGE_TYPE2 4 | |
1203 | #define AAC_COMM_MESSAGE_TYPE3 5 | |
1204 | ||
d503e2fd RAR |
1205 | #define AAC_EXTOPT_SA_FIRMWARE cpu_to_le32(1<<1) |
1206 | ||
495c0217 MR |
1207 | /* MSIX context */ |
1208 | struct aac_msix_ctx { | |
1209 | int vector_no; | |
1210 | struct aac_dev *dev; | |
1211 | }; | |
1da177e4 LT |
1212 | |
1213 | struct aac_dev | |
1214 | { | |
1215 | struct list_head entry; | |
1216 | const char *name; | |
1217 | int id; | |
1218 | ||
7c00ffa3 MH |
1219 | /* |
1220 | * negotiated FIB settings | |
1221 | */ | |
3ffd6c5a RAR |
1222 | unsigned int max_fib_size; |
1223 | unsigned int sg_tablesize; | |
1224 | unsigned int max_num_aif; | |
1225 | ||
1226 | unsigned int max_cmd_size; /* max_fib_size or MAX_NATIVE */ | |
7c00ffa3 | 1227 | |
1da177e4 LT |
1228 | /* |
1229 | * Map for 128 fib objects (64k) | |
8ce3eca4 | 1230 | */ |
1da177e4 LT |
1231 | dma_addr_t hw_fib_pa; |
1232 | struct hw_fib *hw_fib_va; | |
1233 | struct hw_fib *aif_base_va; | |
1234 | /* | |
1235 | * Fib Headers | |
1236 | */ | |
1237 | struct fib *fibs; | |
1238 | ||
1239 | struct fib *free_fib; | |
1da177e4 | 1240 | spinlock_t fib_lock; |
8ce3eca4 | 1241 | |
222a9fb3 | 1242 | struct mutex ioctl_mutex; |
1da177e4 LT |
1243 | struct aac_queue_block *queues; |
1244 | /* | |
1245 | * The user API will use an IOCTL to register itself to receive | |
1246 | * FIBs from the adapter. The following list is used to keep | |
1247 | * track of all the threads that have requested these FIBs. The | |
8ce3eca4 | 1248 | * mutex is used to synchronize access to all data associated |
1da177e4 LT |
1249 | * with the adapter fibs. |
1250 | */ | |
1251 | struct list_head fib_list; | |
1252 | ||
1253 | struct adapter_ops a_ops; | |
1254 | unsigned long fsrev; /* Main driver's revision number */ | |
8ce3eca4 | 1255 | |
ff08784b BC |
1256 | resource_size_t base_start; /* main IO base */ |
1257 | resource_size_t dbg_base; /* address of UART | |
e8b12f0f MR |
1258 | * debug buffer */ |
1259 | ||
ff08784b | 1260 | resource_size_t base_size, dbg_size; /* Size of |
e8b12f0f | 1261 | * mapped in region */ |
d1ef4da8 RAR |
1262 | /* |
1263 | * Holds initialization info | |
1264 | * to communicate with adapter | |
1265 | */ | |
1266 | union aac_init *init; | |
8ce3eca4 | 1267 | dma_addr_t init_pa; /* Holds physical address of the init struct */ |
3ffd6c5a RAR |
1268 | /* response queue (if AAC_COMM_MESSAGE_TYPE1) */ |
1269 | __le32 *host_rrq; | |
e8b12f0f | 1270 | dma_addr_t host_rrq_pa; /* phys. address */ |
495c0217 MR |
1271 | /* index into rrq buffer */ |
1272 | u32 host_rrq_idx[AAC_MAX_MSIX]; | |
1273 | atomic_t rrq_outstanding[AAC_MAX_MSIX]; | |
1274 | u32 fibs_pushed_no; | |
1da177e4 | 1275 | struct pci_dev *pdev; /* Our PCI interface */ |
3ffd6c5a RAR |
1276 | /* pointer to buffer used for printf's from the adapter */ |
1277 | void *printfbuf; | |
1278 | void *comm_addr; /* Base address of Comm area */ | |
1da177e4 LT |
1279 | dma_addr_t comm_phys; /* Physical Address of Comm area */ |
1280 | size_t comm_size; | |
1281 | ||
1282 | struct Scsi_Host *scsi_host_ptr; | |
1283 | int maximum_num_containers; | |
84971738 MH |
1284 | int maximum_num_physicals; |
1285 | int maximum_num_channels; | |
1da177e4 | 1286 | struct fsa_dev_info *fsa_dev; |
fe27381d | 1287 | struct task_struct *thread; |
1da177e4 | 1288 | int cardtype; |
c6992781 MR |
1289 | /* |
1290 | *This lock will protect the two 32-bit | |
1291 | *writes to the Inbound Queue | |
1292 | */ | |
1293 | spinlock_t iq_lock; | |
8ce3eca4 | 1294 | |
1da177e4 LT |
1295 | /* |
1296 | * The following is the device specific extension. | |
1297 | */ | |
8ce3eca4 | 1298 | #ifndef AAC_MIN_FOOTPRINT_SIZE |
8e0c5ebd | 1299 | # define AAC_MIN_FOOTPRINT_SIZE 8192 |
e8b12f0f MR |
1300 | # define AAC_MIN_SRC_BAR0_SIZE 0x400000 |
1301 | # define AAC_MIN_SRC_BAR1_SIZE 0x800 | |
11604612 MR |
1302 | # define AAC_MIN_SRCV_BAR0_SIZE 0x100000 |
1303 | # define AAC_MIN_SRCV_BAR1_SIZE 0x400 | |
8e0c5ebd | 1304 | #endif |
1da177e4 LT |
1305 | union |
1306 | { | |
1307 | struct sa_registers __iomem *sa; | |
1308 | struct rx_registers __iomem *rx; | |
1309 | struct rkt_registers __iomem *rkt; | |
e8b12f0f MR |
1310 | struct { |
1311 | struct src_registers __iomem *bar0; | |
1312 | char __iomem *bar1; | |
1313 | } src; | |
1da177e4 | 1314 | } regs; |
e8b12f0f | 1315 | volatile void __iomem *base, *dbg_base_mapped; |
76a7f8fd | 1316 | volatile struct rx_inbound __iomem *IndexRegs; |
1da177e4 LT |
1317 | u32 OIMR; /* Mask Register Cache */ |
1318 | /* | |
1319 | * AIF thread states | |
1320 | */ | |
1321 | u32 aif_thread; | |
1da177e4 | 1322 | struct aac_adapter_info adapter_info; |
7c00ffa3 | 1323 | struct aac_supplement_adapter_info supplement_adapter_info; |
1da177e4 LT |
1324 | /* These are in adapter info but they are in the io flow so |
1325 | * lets break them out so we don't have to do an AND to check them | |
1326 | */ | |
8ce3eca4 | 1327 | u8 nondasd_support; |
cb1042f2 | 1328 | u8 jbod; |
95e852e1 | 1329 | u8 cache_protected; |
1da177e4 | 1330 | u8 dac_support; |
d8e96507 | 1331 | u8 needs_dac; |
1da177e4 | 1332 | u8 raid_scsi_mode; |
28713324 | 1333 | u8 comm_interface; |
e8b12f0f | 1334 | u8 raw_io_interface; |
7a8cf29d | 1335 | u8 raw_io_64; |
7c00ffa3 | 1336 | u8 printf_enabled; |
8c867b25 | 1337 | u8 in_reset; |
8ef22247 | 1338 | u8 msi; |
d503e2fd | 1339 | u8 sa_firmware; |
cacb6dc3 PNRCEH |
1340 | int management_fib_count; |
1341 | spinlock_t manage_lock; | |
11604612 MR |
1342 | spinlock_t sync_lock; |
1343 | int sync_mode; | |
1344 | struct fib *sync_fib; | |
1345 | struct list_head sync_fib_list; | |
dafde947 | 1346 | u32 doorbell_mask; |
495c0217 MR |
1347 | u32 max_msix; /* max. MSI-X vectors */ |
1348 | u32 vector_cap; /* MSI-X vector capab.*/ | |
1349 | int msi_enabled; /* MSI/MSI-X enabled */ | |
3ffd6c5a RAR |
1350 | atomic_t msix_counter; |
1351 | struct msix_entry msixentry[AAC_MAX_MSIX]; | |
495c0217 | 1352 | struct aac_msix_ctx aac_msix[AAC_MAX_MSIX]; /* context */ |
c83b11e3 | 1353 | struct aac_hba_map_info hba_map[AAC_MAX_BUSES][AAC_MAX_TARGETS]; |
f9c42596 | 1354 | u8 adapter_shutdown; |
5c63f7f7 | 1355 | u32 handle_pci_error; |
1da177e4 LT |
1356 | }; |
1357 | ||
1358 | #define aac_adapter_interrupt(dev) \ | |
1359 | (dev)->a_ops.adapter_interrupt(dev) | |
1360 | ||
1361 | #define aac_adapter_notify(dev, event) \ | |
1362 | (dev)->a_ops.adapter_notify(dev, event) | |
1363 | ||
bd1aac80 MH |
1364 | #define aac_adapter_disable_int(dev) \ |
1365 | (dev)->a_ops.adapter_disable_int(dev) | |
1366 | ||
28713324 MH |
1367 | #define aac_adapter_enable_int(dev) \ |
1368 | (dev)->a_ops.adapter_enable_int(dev) | |
1369 | ||
7c00ffa3 MH |
1370 | #define aac_adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) \ |
1371 | (dev)->a_ops.adapter_sync_cmd(dev, command, p1, p2, p3, p4, p5, p6, status, r1, r2, r3, r4) | |
1da177e4 LT |
1372 | |
1373 | #define aac_adapter_check_health(dev) \ | |
1374 | (dev)->a_ops.adapter_check_health(dev) | |
1375 | ||
8418852d MH |
1376 | #define aac_adapter_restart(dev,bled) \ |
1377 | (dev)->a_ops.adapter_restart(dev,bled) | |
1378 | ||
de665f28 MR |
1379 | #define aac_adapter_start(dev) \ |
1380 | ((dev)->a_ops.adapter_start(dev)) | |
1381 | ||
76a7f8fd MH |
1382 | #define aac_adapter_ioremap(dev, size) \ |
1383 | (dev)->a_ops.adapter_ioremap(dev, size) | |
1384 | ||
28713324 MH |
1385 | #define aac_adapter_deliver(fib) \ |
1386 | ((fib)->dev)->a_ops.adapter_deliver(fib) | |
1387 | ||
e8f32de5 MH |
1388 | #define aac_adapter_bounds(dev,cmd,lba) \ |
1389 | dev->a_ops.adapter_bounds(dev,cmd,lba) | |
1390 | ||
1391 | #define aac_adapter_read(fib,cmd,lba,count) \ | |
1392 | ((fib)->dev)->a_ops.adapter_read(fib,cmd,lba,count) | |
1393 | ||
9d399cc7 SM |
1394 | #define aac_adapter_write(fib,cmd,lba,count,fua) \ |
1395 | ((fib)->dev)->a_ops.adapter_write(fib,cmd,lba,count,fua) | |
e8f32de5 MH |
1396 | |
1397 | #define aac_adapter_scsi(fib,cmd) \ | |
1398 | ((fib)->dev)->a_ops.adapter_scsi(fib,cmd) | |
1399 | ||
28713324 MH |
1400 | #define aac_adapter_comm(dev,comm) \ |
1401 | (dev)->a_ops.adapter_comm(dev, comm) | |
1402 | ||
1da177e4 | 1403 | #define FIB_CONTEXT_FLAG_TIMED_OUT (0x00000001) |
b6ef70f3 | 1404 | #define FIB_CONTEXT_FLAG (0x00000002) |
11604612 | 1405 | #define FIB_CONTEXT_FLAG_WAIT (0x00000004) |
85d22bbf | 1406 | #define FIB_CONTEXT_FLAG_FASTRESP (0x00000008) |
1da177e4 LT |
1407 | |
1408 | /* | |
1409 | * Define the command values | |
1410 | */ | |
8ce3eca4 | 1411 | |
1da177e4 | 1412 | #define Null 0 |
8ce3eca4 SM |
1413 | #define GetAttributes 1 |
1414 | #define SetAttributes 2 | |
1415 | #define Lookup 3 | |
1416 | #define ReadLink 4 | |
1417 | #define Read 5 | |
1418 | #define Write 6 | |
1da177e4 LT |
1419 | #define Create 7 |
1420 | #define MakeDirectory 8 | |
1421 | #define SymbolicLink 9 | |
1422 | #define MakeNode 10 | |
1423 | #define Removex 11 | |
1424 | #define RemoveDirectoryx 12 | |
1425 | #define Rename 13 | |
1426 | #define Link 14 | |
1427 | #define ReadDirectory 15 | |
1428 | #define ReadDirectoryPlus 16 | |
1429 | #define FileSystemStatus 17 | |
1430 | #define FileSystemInfo 18 | |
1431 | #define PathConfigure 19 | |
1432 | #define Commit 20 | |
1433 | #define Mount 21 | |
1434 | #define UnMount 22 | |
1435 | #define Newfs 23 | |
1436 | #define FsCheck 24 | |
1437 | #define FsSync 25 | |
1438 | #define SimReadWrite 26 | |
1439 | #define SetFileSystemStatus 27 | |
1440 | #define BlockRead 28 | |
1441 | #define BlockWrite 29 | |
1442 | #define NvramIoctl 30 | |
1443 | #define FsSyncWait 31 | |
1444 | #define ClearArchiveBit 32 | |
1445 | #define SetAcl 33 | |
1446 | #define GetAcl 34 | |
1447 | #define AssignAcl 35 | |
1448 | #define FaultInsertion 36 /* Fault Insertion Command */ | |
1449 | #define CrazyCache 37 /* Crazycache */ | |
1450 | ||
1451 | #define MAX_FSACOMMAND_NUM 38 | |
1452 | ||
1453 | ||
1454 | /* | |
1455 | * Define the status returns. These are very unixlike although | |
1456 | * most are not in fact used | |
1457 | */ | |
1458 | ||
1459 | #define ST_OK 0 | |
1460 | #define ST_PERM 1 | |
1461 | #define ST_NOENT 2 | |
1462 | #define ST_IO 5 | |
1463 | #define ST_NXIO 6 | |
1464 | #define ST_E2BIG 7 | |
f956a669 | 1465 | #define ST_MEDERR 8 |
1da177e4 LT |
1466 | #define ST_ACCES 13 |
1467 | #define ST_EXIST 17 | |
1468 | #define ST_XDEV 18 | |
1469 | #define ST_NODEV 19 | |
1470 | #define ST_NOTDIR 20 | |
1471 | #define ST_ISDIR 21 | |
1472 | #define ST_INVAL 22 | |
1473 | #define ST_FBIG 27 | |
1474 | #define ST_NOSPC 28 | |
1475 | #define ST_ROFS 30 | |
1476 | #define ST_MLINK 31 | |
1477 | #define ST_WOULDBLOCK 35 | |
1478 | #define ST_NAMETOOLONG 63 | |
1479 | #define ST_NOTEMPTY 66 | |
1480 | #define ST_DQUOT 69 | |
1481 | #define ST_STALE 70 | |
1482 | #define ST_REMOTE 71 | |
655d722c | 1483 | #define ST_NOT_READY 72 |
1da177e4 LT |
1484 | #define ST_BADHANDLE 10001 |
1485 | #define ST_NOT_SYNC 10002 | |
1486 | #define ST_BAD_COOKIE 10003 | |
1487 | #define ST_NOTSUPP 10004 | |
1488 | #define ST_TOOSMALL 10005 | |
1489 | #define ST_SERVERFAULT 10006 | |
1490 | #define ST_BADTYPE 10007 | |
1491 | #define ST_JUKEBOX 10008 | |
1492 | #define ST_NOTMOUNTED 10009 | |
1493 | #define ST_MAINTMODE 10010 | |
1494 | #define ST_STALEACL 10011 | |
1495 | ||
1496 | /* | |
1497 | * On writes how does the client want the data written. | |
1498 | */ | |
1499 | ||
1500 | #define CACHE_CSTABLE 1 | |
1501 | #define CACHE_UNSTABLE 2 | |
1502 | ||
1503 | /* | |
25985edc | 1504 | * Lets the client know at which level the data was committed on |
1da177e4 LT |
1505 | * a write request |
1506 | */ | |
1507 | ||
1508 | #define CMFILE_SYNCH_NVRAM 1 | |
1509 | #define CMDATA_SYNCH_NVRAM 2 | |
1510 | #define CMFILE_SYNCH 3 | |
1511 | #define CMDATA_SYNCH 4 | |
1512 | #define CMUNSTABLE 5 | |
1513 | ||
85d22bbf MR |
1514 | #define RIO_TYPE_WRITE 0x0000 |
1515 | #define RIO_TYPE_READ 0x0001 | |
1516 | #define RIO_SUREWRITE 0x0008 | |
1517 | ||
1518 | #define RIO2_IO_TYPE 0x0003 | |
1519 | #define RIO2_IO_TYPE_WRITE 0x0000 | |
1520 | #define RIO2_IO_TYPE_READ 0x0001 | |
1521 | #define RIO2_IO_TYPE_VERIFY 0x0002 | |
1522 | #define RIO2_IO_ERROR 0x0004 | |
1523 | #define RIO2_IO_SUREWRITE 0x0008 | |
1524 | #define RIO2_SGL_CONFORMANT 0x0010 | |
1525 | #define RIO2_SG_FORMAT 0xF000 | |
1526 | #define RIO2_SG_FORMAT_ARC 0x0000 | |
1527 | #define RIO2_SG_FORMAT_SRL 0x1000 | |
1528 | #define RIO2_SG_FORMAT_IEEE1212 0x2000 | |
1529 | ||
1da177e4 LT |
1530 | struct aac_read |
1531 | { | |
8ce3eca4 SM |
1532 | __le32 command; |
1533 | __le32 cid; | |
1534 | __le32 block; | |
1535 | __le32 count; | |
1da177e4 LT |
1536 | struct sgmap sg; // Must be last in struct because it is variable |
1537 | }; | |
1538 | ||
1539 | struct aac_read64 | |
1540 | { | |
8ce3eca4 SM |
1541 | __le32 command; |
1542 | __le16 cid; | |
1543 | __le16 sector_count; | |
1544 | __le32 block; | |
56b58712 MH |
1545 | __le16 pad; |
1546 | __le16 flags; | |
1da177e4 LT |
1547 | struct sgmap64 sg; // Must be last in struct because it is variable |
1548 | }; | |
1549 | ||
1550 | struct aac_read_reply | |
1551 | { | |
8ce3eca4 SM |
1552 | __le32 status; |
1553 | __le32 count; | |
1da177e4 LT |
1554 | }; |
1555 | ||
1556 | struct aac_write | |
1557 | { | |
56b58712 | 1558 | __le32 command; |
8ce3eca4 SM |
1559 | __le32 cid; |
1560 | __le32 block; | |
1561 | __le32 count; | |
1562 | __le32 stable; // Not used | |
1da177e4 LT |
1563 | struct sgmap sg; // Must be last in struct because it is variable |
1564 | }; | |
1565 | ||
1566 | struct aac_write64 | |
1567 | { | |
8ce3eca4 SM |
1568 | __le32 command; |
1569 | __le16 cid; | |
1570 | __le16 sector_count; | |
1571 | __le32 block; | |
56b58712 MH |
1572 | __le16 pad; |
1573 | __le16 flags; | |
1da177e4 LT |
1574 | struct sgmap64 sg; // Must be last in struct because it is variable |
1575 | }; | |
1576 | struct aac_write_reply | |
1577 | { | |
56b58712 | 1578 | __le32 status; |
8ce3eca4 | 1579 | __le32 count; |
56b58712 | 1580 | __le32 committed; |
1da177e4 LT |
1581 | }; |
1582 | ||
0e68c003 MH |
1583 | struct aac_raw_io |
1584 | { | |
1585 | __le32 block[2]; | |
1586 | __le32 count; | |
1587 | __le16 cid; | |
1588 | __le16 flags; /* 00 W, 01 R */ | |
1589 | __le16 bpTotal; /* reserved for F/W use */ | |
1590 | __le16 bpComplete; /* reserved for F/W use */ | |
1591 | struct sgmapraw sg; | |
1592 | }; | |
1593 | ||
85d22bbf MR |
1594 | struct aac_raw_io2 { |
1595 | __le32 blockLow; | |
1596 | __le32 blockHigh; | |
1597 | __le32 byteCount; | |
1598 | __le16 cid; | |
1599 | __le16 flags; /* RIO2 flags */ | |
1600 | __le32 sgeFirstSize; /* size of first sge el. */ | |
1601 | __le32 sgeNominalSize; /* size of 2nd sge el. (if conformant) */ | |
1602 | u8 sgeCnt; /* only 8 bits required */ | |
1603 | u8 bpTotal; /* reserved for F/W use */ | |
1604 | u8 bpComplete; /* reserved for F/W use */ | |
1605 | u8 sgeFirstIndex; /* reserved for F/W use */ | |
1606 | u8 unused[4]; | |
1607 | struct sge_ieee1212 sge[1]; | |
1608 | }; | |
1609 | ||
1da177e4 LT |
1610 | #define CT_FLUSH_CACHE 129 |
1611 | struct aac_synchronize { | |
56b58712 MH |
1612 | __le32 command; /* VM_ContainerConfig */ |
1613 | __le32 type; /* CT_FLUSH_CACHE */ | |
1614 | __le32 cid; | |
1615 | __le32 parm1; | |
1616 | __le32 parm2; | |
1617 | __le32 parm3; | |
1618 | __le32 parm4; | |
1619 | __le32 count; /* sizeof(((struct aac_synchronize_reply *)NULL)->data) */ | |
1da177e4 LT |
1620 | }; |
1621 | ||
1622 | struct aac_synchronize_reply { | |
56b58712 MH |
1623 | __le32 dummy0; |
1624 | __le32 dummy1; | |
1625 | __le32 status; /* CT_OK */ | |
1626 | __le32 parm1; | |
1627 | __le32 parm2; | |
1628 | __le32 parm3; | |
1629 | __le32 parm4; | |
1630 | __le32 parm5; | |
1da177e4 LT |
1631 | u8 data[16]; |
1632 | }; | |
1633 | ||
655d722c MS |
1634 | #define CT_POWER_MANAGEMENT 245 |
1635 | #define CT_PM_START_UNIT 2 | |
1636 | #define CT_PM_STOP_UNIT 3 | |
1637 | #define CT_PM_UNIT_IMMEDIATE 1 | |
1638 | struct aac_power_management { | |
1639 | __le32 command; /* VM_ContainerConfig */ | |
1640 | __le32 type; /* CT_POWER_MANAGEMENT */ | |
1641 | __le32 sub; /* CT_PM_* */ | |
1642 | __le32 cid; | |
1643 | __le32 parm; /* CT_PM_sub_* */ | |
1644 | }; | |
1645 | ||
29c97684 SM |
1646 | #define CT_PAUSE_IO 65 |
1647 | #define CT_RELEASE_IO 66 | |
1648 | struct aac_pause { | |
1649 | __le32 command; /* VM_ContainerConfig */ | |
1650 | __le32 type; /* CT_PAUSE_IO */ | |
1651 | __le32 timeout; /* 10ms ticks */ | |
1652 | __le32 min; | |
1653 | __le32 noRescan; | |
1654 | __le32 parm3; | |
1655 | __le32 parm4; | |
1656 | __le32 count; /* sizeof(((struct aac_pause_reply *)NULL)->data) */ | |
1657 | }; | |
1658 | ||
1da177e4 | 1659 | struct aac_srb |
56b58712 MH |
1660 | { |
1661 | __le32 function; | |
1662 | __le32 channel; | |
1663 | __le32 id; | |
1664 | __le32 lun; | |
1665 | __le32 timeout; | |
1666 | __le32 flags; | |
1667 | __le32 count; // Data xfer size | |
1668 | __le32 retry_limit; | |
1669 | __le32 cdb_size; | |
1670 | u8 cdb[16]; | |
1671 | struct sgmap sg; | |
1672 | }; | |
1673 | ||
1674 | /* | |
0e68c003 | 1675 | * This and associated data structs are used by the |
56b58712 MH |
1676 | * ioctl caller and are in cpu order. |
1677 | */ | |
1678 | struct user_aac_srb | |
1da177e4 LT |
1679 | { |
1680 | u32 function; | |
1681 | u32 channel; | |
1682 | u32 id; | |
1683 | u32 lun; | |
1684 | u32 timeout; | |
1685 | u32 flags; | |
1686 | u32 count; // Data xfer size | |
1687 | u32 retry_limit; | |
1688 | u32 cdb_size; | |
1689 | u8 cdb[16]; | |
56b58712 | 1690 | struct user_sgmap sg; |
1da177e4 LT |
1691 | }; |
1692 | ||
1da177e4 LT |
1693 | #define AAC_SENSE_BUFFERSIZE 30 |
1694 | ||
1695 | struct aac_srb_reply | |
1696 | { | |
56b58712 MH |
1697 | __le32 status; |
1698 | __le32 srb_status; | |
1699 | __le32 scsi_status; | |
1700 | __le32 data_xfer_length; | |
1701 | __le32 sense_data_size; | |
1da177e4 LT |
1702 | u8 sense_data[AAC_SENSE_BUFFERSIZE]; // Can this be SCSI_SENSE_BUFFERSIZE |
1703 | }; | |
1704 | /* | |
1705 | * SRB Flags | |
1706 | */ | |
1707 | #define SRB_NoDataXfer 0x0000 | |
1708 | #define SRB_DisableDisconnect 0x0004 | |
1709 | #define SRB_DisableSynchTransfer 0x0008 | |
8ce3eca4 | 1710 | #define SRB_BypassFrozenQueue 0x0010 |
1da177e4 LT |
1711 | #define SRB_DisableAutosense 0x0020 |
1712 | #define SRB_DataIn 0x0040 | |
8ce3eca4 | 1713 | #define SRB_DataOut 0x0080 |
1da177e4 LT |
1714 | |
1715 | /* | |
1716 | * SRB Functions - set in aac_srb->function | |
1717 | */ | |
1718 | #define SRBF_ExecuteScsi 0x0000 | |
1719 | #define SRBF_ClaimDevice 0x0001 | |
1720 | #define SRBF_IO_Control 0x0002 | |
1721 | #define SRBF_ReceiveEvent 0x0003 | |
1722 | #define SRBF_ReleaseQueue 0x0004 | |
1723 | #define SRBF_AttachDevice 0x0005 | |
1724 | #define SRBF_ReleaseDevice 0x0006 | |
1725 | #define SRBF_Shutdown 0x0007 | |
1726 | #define SRBF_Flush 0x0008 | |
1727 | #define SRBF_AbortCommand 0x0010 | |
1728 | #define SRBF_ReleaseRecovery 0x0011 | |
1729 | #define SRBF_ResetBus 0x0012 | |
1730 | #define SRBF_ResetDevice 0x0013 | |
1731 | #define SRBF_TerminateIO 0x0014 | |
1732 | #define SRBF_FlushQueue 0x0015 | |
1733 | #define SRBF_RemoveDevice 0x0016 | |
1734 | #define SRBF_DomainValidation 0x0017 | |
1735 | ||
8ce3eca4 | 1736 | /* |
1da177e4 LT |
1737 | * SRB SCSI Status - set in aac_srb->scsi_status |
1738 | */ | |
1739 | #define SRB_STATUS_PENDING 0x00 | |
1740 | #define SRB_STATUS_SUCCESS 0x01 | |
1741 | #define SRB_STATUS_ABORTED 0x02 | |
1742 | #define SRB_STATUS_ABORT_FAILED 0x03 | |
1743 | #define SRB_STATUS_ERROR 0x04 | |
1744 | #define SRB_STATUS_BUSY 0x05 | |
1745 | #define SRB_STATUS_INVALID_REQUEST 0x06 | |
1746 | #define SRB_STATUS_INVALID_PATH_ID 0x07 | |
1747 | #define SRB_STATUS_NO_DEVICE 0x08 | |
1748 | #define SRB_STATUS_TIMEOUT 0x09 | |
1749 | #define SRB_STATUS_SELECTION_TIMEOUT 0x0A | |
1750 | #define SRB_STATUS_COMMAND_TIMEOUT 0x0B | |
1751 | #define SRB_STATUS_MESSAGE_REJECTED 0x0D | |
1752 | #define SRB_STATUS_BUS_RESET 0x0E | |
1753 | #define SRB_STATUS_PARITY_ERROR 0x0F | |
1754 | #define SRB_STATUS_REQUEST_SENSE_FAILED 0x10 | |
1755 | #define SRB_STATUS_NO_HBA 0x11 | |
1756 | #define SRB_STATUS_DATA_OVERRUN 0x12 | |
1757 | #define SRB_STATUS_UNEXPECTED_BUS_FREE 0x13 | |
1758 | #define SRB_STATUS_PHASE_SEQUENCE_FAILURE 0x14 | |
1759 | #define SRB_STATUS_BAD_SRB_BLOCK_LENGTH 0x15 | |
1760 | #define SRB_STATUS_REQUEST_FLUSHED 0x16 | |
1761 | #define SRB_STATUS_DELAYED_RETRY 0x17 | |
1762 | #define SRB_STATUS_INVALID_LUN 0x20 | |
1763 | #define SRB_STATUS_INVALID_TARGET_ID 0x21 | |
1764 | #define SRB_STATUS_BAD_FUNCTION 0x22 | |
1765 | #define SRB_STATUS_ERROR_RECOVERY 0x23 | |
1766 | #define SRB_STATUS_NOT_STARTED 0x24 | |
1767 | #define SRB_STATUS_NOT_IN_USE 0x30 | |
1768 | #define SRB_STATUS_FORCE_ABORT 0x31 | |
1769 | #define SRB_STATUS_DOMAIN_VALIDATION_FAIL 0x32 | |
1770 | ||
1771 | /* | |
1772 | * Object-Server / Volume-Manager Dispatch Classes | |
1773 | */ | |
1774 | ||
1775 | #define VM_Null 0 | |
1776 | #define VM_NameServe 1 | |
1777 | #define VM_ContainerConfig 2 | |
1778 | #define VM_Ioctl 3 | |
1779 | #define VM_FilesystemIoctl 4 | |
1780 | #define VM_CloseAll 5 | |
1781 | #define VM_CtBlockRead 6 | |
1782 | #define VM_CtBlockWrite 7 | |
1783 | #define VM_SliceBlockRead 8 /* raw access to configured "storage objects" */ | |
1784 | #define VM_SliceBlockWrite 9 | |
1785 | #define VM_DriveBlockRead 10 /* raw access to physical devices */ | |
1786 | #define VM_DriveBlockWrite 11 | |
1787 | #define VM_EnclosureMgt 12 /* enclosure management */ | |
1788 | #define VM_Unused 13 /* used to be diskset management */ | |
1789 | #define VM_CtBlockVerify 14 | |
1790 | #define VM_CtPerf 15 /* performance test */ | |
1791 | #define VM_CtBlockRead64 16 | |
1792 | #define VM_CtBlockWrite64 17 | |
1793 | #define VM_CtBlockVerify64 18 | |
1794 | #define VM_CtHostRead64 19 | |
1795 | #define VM_CtHostWrite64 20 | |
7a8cf29d MH |
1796 | #define VM_DrvErrTblLog 21 |
1797 | #define VM_NameServe64 22 | |
b836439f | 1798 | #define VM_NameServeAllBlk 30 |
1da177e4 | 1799 | |
7a8cf29d | 1800 | #define MAX_VMCOMMAND_NUM 23 /* used for sizing stats array - leave last */ |
1da177e4 LT |
1801 | |
1802 | /* | |
1803 | * Descriptive information (eg, vital stats) | |
1804 | * that a content manager might report. The | |
1805 | * FileArray filesystem component is one example | |
1806 | * of a content manager. Raw mode might be | |
1807 | * another. | |
1808 | */ | |
1809 | ||
1810 | struct aac_fsinfo { | |
56b58712 MH |
1811 | __le32 fsTotalSize; /* Consumed by fs, incl. metadata */ |
1812 | __le32 fsBlockSize; | |
1813 | __le32 fsFragSize; | |
1814 | __le32 fsMaxExtendSize; | |
1815 | __le32 fsSpaceUnits; | |
1816 | __le32 fsMaxNumFiles; | |
1817 | __le32 fsNumFreeFiles; | |
1818 | __le32 fsInodeDensity; | |
1da177e4 LT |
1819 | }; /* valid iff ObjType == FT_FILESYS && !(ContentState & FSCS_NOTCLEAN) */ |
1820 | ||
b836439f MR |
1821 | struct aac_blockdevinfo { |
1822 | __le32 block_size; | |
1823 | }; | |
1824 | ||
1da177e4 | 1825 | union aac_contentinfo { |
b836439f MR |
1826 | struct aac_fsinfo filesys; |
1827 | struct aac_blockdevinfo bdevinfo; | |
1da177e4 LT |
1828 | }; |
1829 | ||
1830 | /* | |
1831 | * Query for Container Configuration Status | |
1832 | */ | |
1833 | ||
1834 | #define CT_GET_CONFIG_STATUS 147 | |
1835 | struct aac_get_config_status { | |
56b58712 MH |
1836 | __le32 command; /* VM_ContainerConfig */ |
1837 | __le32 type; /* CT_GET_CONFIG_STATUS */ | |
1838 | __le32 parm1; | |
1839 | __le32 parm2; | |
1840 | __le32 parm3; | |
1841 | __le32 parm4; | |
1842 | __le32 parm5; | |
1843 | __le32 count; /* sizeof(((struct aac_get_config_status_resp *)NULL)->data) */ | |
1da177e4 LT |
1844 | }; |
1845 | ||
1846 | #define CFACT_CONTINUE 0 | |
1847 | #define CFACT_PAUSE 1 | |
1848 | #define CFACT_ABORT 2 | |
1849 | struct aac_get_config_status_resp { | |
56b58712 MH |
1850 | __le32 response; /* ST_OK */ |
1851 | __le32 dummy0; | |
1852 | __le32 status; /* CT_OK */ | |
1853 | __le32 parm1; | |
1854 | __le32 parm2; | |
1855 | __le32 parm3; | |
1856 | __le32 parm4; | |
1857 | __le32 parm5; | |
1da177e4 | 1858 | struct { |
56b58712 MH |
1859 | __le32 action; /* CFACT_CONTINUE, CFACT_PAUSE or CFACT_ABORT */ |
1860 | __le16 flags; | |
1861 | __le16 count; | |
1da177e4 LT |
1862 | } data; |
1863 | }; | |
1864 | ||
1865 | /* | |
1866 | * Accept the configuration as-is | |
1867 | */ | |
1868 | ||
1869 | #define CT_COMMIT_CONFIG 152 | |
1870 | ||
1871 | struct aac_commit_config { | |
56b58712 MH |
1872 | __le32 command; /* VM_ContainerConfig */ |
1873 | __le32 type; /* CT_COMMIT_CONFIG */ | |
1da177e4 LT |
1874 | }; |
1875 | ||
1876 | /* | |
7c00ffa3 | 1877 | * Query for Container Configuration Status |
1da177e4 LT |
1878 | */ |
1879 | ||
1880 | #define CT_GET_CONTAINER_COUNT 4 | |
1881 | struct aac_get_container_count { | |
56b58712 MH |
1882 | __le32 command; /* VM_ContainerConfig */ |
1883 | __le32 type; /* CT_GET_CONTAINER_COUNT */ | |
1da177e4 LT |
1884 | }; |
1885 | ||
1886 | struct aac_get_container_count_resp { | |
56b58712 MH |
1887 | __le32 response; /* ST_OK */ |
1888 | __le32 dummy0; | |
1889 | __le32 MaxContainers; | |
1890 | __le32 ContainerSwitchEntries; | |
1891 | __le32 MaxPartitions; | |
a7129a54 | 1892 | __le32 MaxSimpleVolumes; |
1da177e4 LT |
1893 | }; |
1894 | ||
1895 | ||
1896 | /* | |
1897 | * Query for "mountable" objects, ie, objects that are typically | |
1898 | * associated with a drive letter on the client (host) side. | |
1899 | */ | |
1900 | ||
1901 | struct aac_mntent { | |
8ce3eca4 | 1902 | __le32 oid; |
56b58712 MH |
1903 | u8 name[16]; /* if applicable */ |
1904 | struct creation_info create_info; /* if applicable */ | |
1905 | __le32 capacity; | |
8ce3eca4 SM |
1906 | __le32 vol; /* substrate structure */ |
1907 | __le32 obj; /* FT_FILESYS, etc. */ | |
1908 | __le32 state; /* unready for mounting, | |
56b58712 | 1909 | readonly, etc. */ |
8ce3eca4 | 1910 | union aac_contentinfo fileinfo; /* Info specific to content |
56b58712 | 1911 | manager (eg, filesystem) */ |
8ce3eca4 | 1912 | __le32 altoid; /* != oid <==> snapshot or |
56b58712 | 1913 | broken mirror exists */ |
7a8cf29d | 1914 | __le32 capacityhigh; |
1da177e4 LT |
1915 | }; |
1916 | ||
3a4fa0a2 | 1917 | #define FSCS_NOTCLEAN 0x0001 /* fsck is necessary before mounting */ |
1da177e4 LT |
1918 | #define FSCS_READONLY 0x0002 /* possible result of broken mirror */ |
1919 | #define FSCS_HIDDEN 0x0004 /* should be ignored - set during a clear */ | |
655d722c | 1920 | #define FSCS_NOT_READY 0x0008 /* Array spinning up to fulfil request */ |
1da177e4 LT |
1921 | |
1922 | struct aac_query_mount { | |
56b58712 MH |
1923 | __le32 command; |
1924 | __le32 type; | |
1925 | __le32 count; | |
1da177e4 LT |
1926 | }; |
1927 | ||
1928 | struct aac_mount { | |
56b58712 | 1929 | __le32 status; |
8ce3eca4 | 1930 | __le32 type; /* should be same as that requested */ |
56b58712 | 1931 | __le32 count; |
1da177e4 LT |
1932 | struct aac_mntent mnt[1]; |
1933 | }; | |
1934 | ||
1935 | #define CT_READ_NAME 130 | |
1936 | struct aac_get_name { | |
56b58712 MH |
1937 | __le32 command; /* VM_ContainerConfig */ |
1938 | __le32 type; /* CT_READ_NAME */ | |
1939 | __le32 cid; | |
1940 | __le32 parm1; | |
1941 | __le32 parm2; | |
1942 | __le32 parm3; | |
1943 | __le32 parm4; | |
1944 | __le32 count; /* sizeof(((struct aac_get_name_resp *)NULL)->data) */ | |
1da177e4 LT |
1945 | }; |
1946 | ||
1da177e4 | 1947 | struct aac_get_name_resp { |
56b58712 MH |
1948 | __le32 dummy0; |
1949 | __le32 dummy1; | |
1950 | __le32 status; /* CT_OK */ | |
1951 | __le32 parm1; | |
1952 | __le32 parm2; | |
1953 | __le32 parm3; | |
1954 | __le32 parm4; | |
1955 | __le32 parm5; | |
1da177e4 LT |
1956 | u8 data[16]; |
1957 | }; | |
1958 | ||
88e2f98e SM |
1959 | #define CT_CID_TO_32BITS_UID 165 |
1960 | struct aac_get_serial { | |
1961 | __le32 command; /* VM_ContainerConfig */ | |
1962 | __le32 type; /* CT_CID_TO_32BITS_UID */ | |
1963 | __le32 cid; | |
1964 | }; | |
1965 | ||
1966 | struct aac_get_serial_resp { | |
1967 | __le32 dummy0; | |
1968 | __le32 dummy1; | |
1969 | __le32 status; /* CT_OK */ | |
1970 | __le32 uid; | |
1971 | }; | |
1972 | ||
1da177e4 LT |
1973 | /* |
1974 | * The following command is sent to shut down each container. | |
1975 | */ | |
1976 | ||
1977 | struct aac_close { | |
56b58712 MH |
1978 | __le32 command; |
1979 | __le32 cid; | |
1da177e4 LT |
1980 | }; |
1981 | ||
1982 | struct aac_query_disk | |
1983 | { | |
1984 | s32 cnum; | |
1985 | s32 bus; | |
1986 | s32 id; | |
1987 | s32 lun; | |
1988 | u32 valid; | |
1989 | u32 locked; | |
1990 | u32 deleted; | |
1991 | s32 instance; | |
1992 | s8 name[10]; | |
1993 | u32 unmapped; | |
1994 | }; | |
1995 | ||
1996 | struct aac_delete_disk { | |
1997 | u32 disknum; | |
1998 | u32 cnum; | |
1999 | }; | |
8ce3eca4 | 2000 | |
1da177e4 LT |
2001 | struct fib_ioctl |
2002 | { | |
2003 | u32 fibctx; | |
2004 | s32 wait; | |
2005 | char __user *fib; | |
2006 | }; | |
2007 | ||
2008 | struct revision | |
2009 | { | |
9f30a323 | 2010 | u32 compat; |
c7f47602 MH |
2011 | __le32 version; |
2012 | __le32 build; | |
1da177e4 | 2013 | }; |
8ce3eca4 | 2014 | |
c7f47602 | 2015 | |
1da177e4 | 2016 | /* |
8ce3eca4 | 2017 | * Ugly - non Linux like ioctl coding for back compat. |
1da177e4 LT |
2018 | */ |
2019 | ||
2020 | #define CTL_CODE(function, method) ( \ | |
2021 | (4<< 16) | ((function) << 2) | (method) \ | |
2022 | ) | |
2023 | ||
2024 | /* | |
8ce3eca4 | 2025 | * Define the method codes for how buffers are passed for I/O and FS |
1da177e4 LT |
2026 | * controls |
2027 | */ | |
2028 | ||
2029 | #define METHOD_BUFFERED 0 | |
2030 | #define METHOD_NEITHER 3 | |
2031 | ||
2032 | /* | |
2033 | * Filesystem ioctls | |
2034 | */ | |
2035 | ||
8ce3eca4 SM |
2036 | #define FSACTL_SENDFIB CTL_CODE(2050, METHOD_BUFFERED) |
2037 | #define FSACTL_SEND_RAW_SRB CTL_CODE(2067, METHOD_BUFFERED) | |
1da177e4 LT |
2038 | #define FSACTL_DELETE_DISK 0x163 |
2039 | #define FSACTL_QUERY_DISK 0x173 | |
2040 | #define FSACTL_OPEN_GET_ADAPTER_FIB CTL_CODE(2100, METHOD_BUFFERED) | |
2041 | #define FSACTL_GET_NEXT_ADAPTER_FIB CTL_CODE(2101, METHOD_BUFFERED) | |
2042 | #define FSACTL_CLOSE_GET_ADAPTER_FIB CTL_CODE(2102, METHOD_BUFFERED) | |
2043 | #define FSACTL_MINIPORT_REV_CHECK CTL_CODE(2107, METHOD_BUFFERED) | |
8ce3eca4 | 2044 | #define FSACTL_GET_PCI_INFO CTL_CODE(2119, METHOD_BUFFERED) |
1da177e4 LT |
2045 | #define FSACTL_FORCE_DELETE_DISK CTL_CODE(2120, METHOD_NEITHER) |
2046 | #define FSACTL_GET_CONTAINERS 2131 | |
7c00ffa3 | 2047 | #define FSACTL_SEND_LARGE_FIB CTL_CODE(2138, METHOD_BUFFERED) |
1da177e4 LT |
2048 | |
2049 | ||
2050 | struct aac_common | |
2051 | { | |
2052 | /* | |
8ce3eca4 | 2053 | * If this value is set to 1 then interrupt moderation will occur |
1da177e4 LT |
2054 | * in the base commuication support. |
2055 | */ | |
2056 | u32 irq_mod; | |
2057 | u32 peak_fibs; | |
2058 | u32 zero_fibs; | |
2059 | u32 fib_timeouts; | |
2060 | /* | |
2061 | * Statistical counters in debug mode | |
2062 | */ | |
2063 | #ifdef DBG | |
2064 | u32 FibsSent; | |
2065 | u32 FibRecved; | |
2066 | u32 NoResponseSent; | |
2067 | u32 NoResponseRecved; | |
2068 | u32 AsyncSent; | |
2069 | u32 AsyncRecved; | |
2070 | u32 NormalSent; | |
2071 | u32 NormalRecved; | |
2072 | #endif | |
2073 | }; | |
2074 | ||
2075 | extern struct aac_common aac_config; | |
2076 | ||
2077 | ||
2078 | /* | |
2079 | * The following macro is used when sending and receiving FIBs. It is | |
2080 | * only used for debugging. | |
2081 | */ | |
8ce3eca4 | 2082 | |
1da177e4 LT |
2083 | #ifdef DBG |
2084 | #define FIB_COUNTER_INCREMENT(counter) (counter)++ | |
2085 | #else | |
8ce3eca4 | 2086 | #define FIB_COUNTER_INCREMENT(counter) |
1da177e4 LT |
2087 | #endif |
2088 | ||
2089 | /* | |
2090 | * Adapter direct commands | |
2091 | * Monitor/Kernel API | |
2092 | */ | |
2093 | ||
2094 | #define BREAKPOINT_REQUEST 0x00000004 | |
2095 | #define INIT_STRUCT_BASE_ADDRESS 0x00000005 | |
2096 | #define READ_PERMANENT_PARAMETERS 0x0000000a | |
2097 | #define WRITE_PERMANENT_PARAMETERS 0x0000000b | |
2098 | #define HOST_CRASHING 0x0000000d | |
2099 | #define SEND_SYNCHRONOUS_FIB 0x0000000c | |
2100 | #define COMMAND_POST_RESULTS 0x00000014 | |
2101 | #define GET_ADAPTER_PROPERTIES 0x00000019 | |
2102 | #define GET_DRIVER_BUFFER_PROPERTIES 0x00000023 | |
2103 | #define RCV_TEMP_READINGS 0x00000025 | |
2104 | #define GET_COMM_PREFERRED_SETTINGS 0x00000026 | |
2105 | #define IOP_RESET 0x00001000 | |
8c23cd74 | 2106 | #define IOP_RESET_ALWAYS 0x00001001 |
1da177e4 LT |
2107 | #define RE_INIT_ADAPTER 0x000000ee |
2108 | ||
2109 | /* | |
2110 | * Adapter Status Register | |
2111 | * | |
2112 | * Phase Staus mailbox is 32bits: | |
2113 | * <31:16> = Phase Status | |
2114 | * <15:0> = Phase | |
2115 | * | |
2116 | * The adapter reports is present state through the phase. Only | |
2117 | * a single phase should be ever be set. Each phase can have multiple | |
8ce3eca4 SM |
2118 | * phase status bits to provide more detailed information about the |
2119 | * state of the board. Care should be taken to ensure that any phase | |
1da177e4 LT |
2120 | * status bits that are set when changing the phase are also valid |
2121 | * for the new phase or be cleared out. Adapter software (monitor, | |
8ce3eca4 | 2122 | * iflash, kernel) is responsible for properly maintining the phase |
1da177e4 | 2123 | * status mailbox when it is running. |
1da177e4 | 2124 | * |
8ce3eca4 SM |
2125 | * MONKER_API Phases |
2126 | * | |
2127 | * Phases are bit oriented. It is NOT valid to have multiple bits set | |
2128 | */ | |
1da177e4 LT |
2129 | |
2130 | #define SELF_TEST_FAILED 0x00000004 | |
2131 | #define MONITOR_PANIC 0x00000020 | |
2132 | #define KERNEL_UP_AND_RUNNING 0x00000080 | |
2133 | #define KERNEL_PANIC 0x00000100 | |
2c10cd43 MR |
2134 | #define FLASH_UPD_PENDING 0x00002000 |
2135 | #define FLASH_UPD_SUCCESS 0x00004000 | |
2136 | #define FLASH_UPD_FAILED 0x00008000 | |
2137 | #define FWUPD_TIMEOUT (5 * 60) | |
1da177e4 LT |
2138 | |
2139 | /* | |
2140 | * Doorbell bit defines | |
2141 | */ | |
2142 | ||
2143 | #define DoorBellSyncCmdAvailable (1<<0) /* Host -> Adapter */ | |
2144 | #define DoorBellPrintfDone (1<<5) /* Host -> Adapter */ | |
2145 | #define DoorBellAdapterNormCmdReady (1<<1) /* Adapter -> Host */ | |
2146 | #define DoorBellAdapterNormRespReady (1<<2) /* Adapter -> Host */ | |
2147 | #define DoorBellAdapterNormCmdNotFull (1<<3) /* Adapter -> Host */ | |
2148 | #define DoorBellAdapterNormRespNotFull (1<<4) /* Adapter -> Host */ | |
2149 | #define DoorBellPrintfReady (1<<5) /* Adapter -> Host */ | |
e8b12f0f MR |
2150 | #define DoorBellAifPending (1<<6) /* Adapter -> Host */ |
2151 | ||
2152 | /* PMC specific outbound doorbell bits */ | |
2153 | #define PmDoorBellResponseSent (1<<1) /* Adapter -> Host */ | |
1da177e4 LT |
2154 | |
2155 | /* | |
2156 | * For FIB communication, we need all of the following things | |
2157 | * to send back to the user. | |
2158 | */ | |
8ce3eca4 SM |
2159 | |
2160 | #define AifCmdEventNotify 1 /* Notify of event */ | |
1da177e4 LT |
2161 | #define AifEnConfigChange 3 /* Adapter configuration change */ |
2162 | #define AifEnContainerChange 4 /* Container configuration change */ | |
2163 | #define AifEnDeviceFailure 5 /* SCSI device failed */ | |
0995ad38 SM |
2164 | #define AifEnEnclosureManagement 13 /* EM_DRIVE_* */ |
2165 | #define EM_DRIVE_INSERTION 31 | |
2166 | #define EM_DRIVE_REMOVAL 32 | |
46154a02 MR |
2167 | #define EM_SES_DRIVE_INSERTION 33 |
2168 | #define EM_SES_DRIVE_REMOVAL 26 | |
95e852e1 | 2169 | #define AifEnBatteryEvent 14 /* Change in Battery State */ |
1da177e4 LT |
2170 | #define AifEnAddContainer 15 /* A new array was created */ |
2171 | #define AifEnDeleteContainer 16 /* A container was deleted */ | |
2172 | #define AifEnExpEvent 23 /* Firmware Event Log */ | |
2173 | #define AifExeFirmwarePanic 3 /* Firmware Event Panic */ | |
2174 | #define AifHighPriority 3 /* Highest Priority Event */ | |
cb1042f2 SM |
2175 | #define AifEnAddJBOD 30 /* JBOD created */ |
2176 | #define AifEnDeleteJBOD 31 /* JBOD deleted */ | |
1da177e4 | 2177 | |
9cb62fa2 RAR |
2178 | #define AifBuManagerEvent 42 /* Bu management*/ |
2179 | #define AifBuCacheDataLoss 10 | |
2180 | #define AifBuCacheDataRecover 11 | |
2181 | ||
1da177e4 LT |
2182 | #define AifCmdJobProgress 2 /* Progress report */ |
2183 | #define AifJobCtrZero 101 /* Array Zero progress */ | |
2184 | #define AifJobStsSuccess 1 /* Job completes */ | |
131256cf | 2185 | #define AifJobStsRunning 102 /* Job running */ |
1da177e4 LT |
2186 | #define AifCmdAPIReport 3 /* Report from other user of API */ |
2187 | #define AifCmdDriverNotify 4 /* Notify host driver of event */ | |
2188 | #define AifDenMorphComplete 200 /* A morph operation completed */ | |
2189 | #define AifDenVolumeExtendComplete 201 /* A volume extend completed */ | |
2190 | #define AifReqJobList 100 /* Gets back complete job list */ | |
2191 | #define AifReqJobsForCtr 101 /* Gets back jobs for specific container */ | |
8ce3eca4 SM |
2192 | #define AifReqJobsForScsi 102 /* Gets back jobs for specific SCSI device */ |
2193 | #define AifReqJobReport 103 /* Gets back a specific job report or list of them */ | |
1da177e4 LT |
2194 | #define AifReqTerminateJob 104 /* Terminates job */ |
2195 | #define AifReqSuspendJob 105 /* Suspends a job */ | |
8ce3eca4 | 2196 | #define AifReqResumeJob 106 /* Resumes a job */ |
1da177e4 LT |
2197 | #define AifReqSendAPIReport 107 /* API generic report requests */ |
2198 | #define AifReqAPIJobStart 108 /* Start a job from the API */ | |
2199 | #define AifReqAPIJobUpdate 109 /* Update a job report from the API */ | |
2200 | #define AifReqAPIJobFinish 110 /* Finish a job from the API */ | |
2201 | ||
e8b12f0f MR |
2202 | /* PMC NEW COMM: Request the event data */ |
2203 | #define AifReqEvent 200 | |
2204 | ||
dab04b01 MR |
2205 | /* RAW device deleted */ |
2206 | #define AifRawDeviceRemove 203 | |
2207 | ||
1da177e4 LT |
2208 | /* |
2209 | * Adapter Initiated FIB command structures. Start with the adapter | |
2210 | * initiated FIBs that really come from the adapter, and get responded | |
2211 | * to by the host. | |
2212 | */ | |
2213 | ||
2214 | struct aac_aifcmd { | |
56b58712 MH |
2215 | __le32 command; /* Tell host what type of notify this is */ |
2216 | __le32 seqnum; /* To allow ordering of reports (if necessary) */ | |
1da177e4 LT |
2217 | u8 data[1]; /* Undefined length (from kernel viewpoint) */ |
2218 | }; | |
2219 | ||
2220 | /** | |
8ce3eca4 SM |
2221 | * Convert capacity to cylinders |
2222 | * accounting for the fact capacity could be a 64 bit value | |
1da177e4 LT |
2223 | * |
2224 | */ | |
c835e372 | 2225 | static inline unsigned int cap_to_cyls(sector_t capacity, unsigned divisor) |
1da177e4 LT |
2226 | { |
2227 | sector_div(capacity, divisor); | |
c835e372 | 2228 | return capacity; |
1da177e4 LT |
2229 | } |
2230 | ||
77d644d4 MH |
2231 | /* SCp.phase values */ |
2232 | #define AAC_OWNER_MIDLEVEL 0x101 | |
2233 | #define AAC_OWNER_LOWLEVEL 0x102 | |
2234 | #define AAC_OWNER_ERROR_HANDLER 0x103 | |
2235 | #define AAC_OWNER_FIRMWARE 0x106 | |
1da177e4 | 2236 | |
8b1462e0 MR |
2237 | int aac_acquire_irq(struct aac_dev *dev); |
2238 | void aac_free_irq(struct aac_dev *dev); | |
c83b11e3 | 2239 | int aac_report_phys_luns(struct aac_dev *dev, struct fib *fibptr); |
1da177e4 | 2240 | const char *aac_driverinfo(struct Scsi_Host *); |
3f4ce057 | 2241 | void aac_fib_vector_assign(struct aac_dev *dev); |
bfb35aa8 | 2242 | struct fib *aac_fib_alloc(struct aac_dev *dev); |
6bf3b630 | 2243 | struct fib *aac_fib_alloc_tag(struct aac_dev *dev, struct scsi_cmnd *scmd); |
bfb35aa8 MH |
2244 | int aac_fib_setup(struct aac_dev *dev); |
2245 | void aac_fib_map_free(struct aac_dev *dev); | |
2246 | void aac_fib_free(struct fib * context); | |
2247 | void aac_fib_init(struct fib * context); | |
1da177e4 | 2248 | void aac_printf(struct aac_dev *dev, u32 val); |
bfb35aa8 | 2249 | int aac_fib_send(u16 command, struct fib * context, unsigned long size, int priority, int wait, int reply, fib_callback callback, void *ctxt); |
1da177e4 LT |
2250 | int aac_consumer_get(struct aac_dev * dev, struct aac_queue * q, struct aac_entry **entry); |
2251 | void aac_consumer_free(struct aac_dev * dev, struct aac_queue * q, u32 qnum); | |
bfb35aa8 | 2252 | int aac_fib_complete(struct fib * context); |
a8166a52 | 2253 | #define fib_data(fibctx) ((void *)(fibctx)->hw_fib_va->data) |
1da177e4 | 2254 | struct aac_dev *aac_init_adapter(struct aac_dev *dev); |
495c0217 | 2255 | void aac_src_access_devreg(struct aac_dev *dev, int mode); |
8c867b25 | 2256 | int aac_get_config_status(struct aac_dev *dev, int commit_flag); |
1da177e4 LT |
2257 | int aac_get_containers(struct aac_dev *dev); |
2258 | int aac_scsi_cmd(struct scsi_cmnd *cmd); | |
2259 | int aac_dev_ioctl(struct aac_dev *dev, int cmd, void __user *arg); | |
24f02e1d | 2260 | #ifndef shost_to_class |
ee959b00 | 2261 | #define shost_to_class(shost) &shost->shost_dev |
24f02e1d | 2262 | #endif |
ee959b00 | 2263 | ssize_t aac_get_serial_number(struct device *dev, char *buf); |
1da177e4 LT |
2264 | int aac_do_ioctl(struct aac_dev * dev, int cmd, void __user *arg); |
2265 | int aac_rx_init(struct aac_dev *dev); | |
2266 | int aac_rkt_init(struct aac_dev *dev); | |
239eab19 | 2267 | int aac_nark_init(struct aac_dev *dev); |
1da177e4 | 2268 | int aac_sa_init(struct aac_dev *dev); |
e8b12f0f | 2269 | int aac_src_init(struct aac_dev *dev); |
11604612 | 2270 | int aac_srcv_init(struct aac_dev *dev); |
28713324 | 2271 | int aac_queue_get(struct aac_dev * dev, u32 * index, u32 qid, struct hw_fib * hw_fib, int wait, struct fib * fibptr, unsigned long *nonotify); |
de665f28 | 2272 | void aac_define_int_mode(struct aac_dev *dev); |
1da177e4 LT |
2273 | unsigned int aac_response_normal(struct aac_queue * q); |
2274 | unsigned int aac_command_normal(struct aac_queue * q); | |
e8b12f0f MR |
2275 | unsigned int aac_intr_normal(struct aac_dev *dev, u32 Index, |
2276 | int isAif, int isFastResponse, | |
2277 | struct hw_fib *aif_fib); | |
29c97684 | 2278 | int aac_reset_adapter(struct aac_dev * dev, int forced); |
8c867b25 | 2279 | int aac_check_health(struct aac_dev * dev); |
fe27381d | 2280 | int aac_command_thread(void *data); |
1da177e4 | 2281 | int aac_close_fib_context(struct aac_dev * dev, struct aac_fib_context *fibctx); |
bfb35aa8 | 2282 | int aac_fib_adapter_complete(struct fib * fibptr, unsigned short size); |
1da177e4 LT |
2283 | struct aac_driver_ident* aac_get_driver_ident(int devtype); |
2284 | int aac_get_adapter_info(struct aac_dev* dev); | |
2285 | int aac_send_shutdown(struct aac_dev *dev); | |
bfb35aa8 | 2286 | int aac_probe_container(struct aac_dev *dev, int cid); |
9695a25d AB |
2287 | int _aac_rx_init(struct aac_dev *dev); |
2288 | int aac_rx_select_comm(struct aac_dev *dev, int comm); | |
2ab01efd | 2289 | int aac_rx_deliver_producer(struct fib * fib); |
17eaacee | 2290 | char * get_container_type(unsigned type); |
7c00ffa3 | 2291 | extern int numacb; |
c7f47602 | 2292 | extern char aac_driver_version[]; |
404d9a90 MH |
2293 | extern int startup_timeout; |
2294 | extern int aif_timeout; | |
9695a25d | 2295 | extern int expose_physicals; |
1208bab5 | 2296 | extern int aac_reset_devices; |
8ef22247 | 2297 | extern int aac_msi; |
1208bab5 | 2298 | extern int aac_commit; |
29c97684 SM |
2299 | extern int update_interval; |
2300 | extern int check_interval; | |
87f3bda3 | 2301 | extern int aac_check_reset; |
24b043cb | 2302 | #endif |