Commit | Line | Data |
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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
4a71df50 | 2 | /* |
4a71df50 FB |
3 | * Copyright IBM Corp. 2007 |
4 | * Author(s): Utz Bacher <utz.bacher@de.ibm.com>, | |
5 | * Frank Pavlic <fpavlic@de.ibm.com>, | |
6 | * Thomas Spatzier <tspat@de.ibm.com>, | |
7 | * Frank Blaschka <frank.blaschka@de.ibm.com> | |
8 | */ | |
9 | ||
10 | #ifndef __QETH_CORE_H__ | |
11 | #define __QETH_CORE_H__ | |
12 | ||
782e4a79 | 13 | #include <linux/completion.h> |
fb8d2580 | 14 | #include <linux/debugfs.h> |
4a71df50 FB |
15 | #include <linux/if.h> |
16 | #include <linux/if_arp.h> | |
4a71df50 FB |
17 | #include <linux/etherdevice.h> |
18 | #include <linux/if_vlan.h> | |
19 | #include <linux/ctype.h> | |
20 | #include <linux/in6.h> | |
21 | #include <linux/bitops.h> | |
22 | #include <linux/seq_file.h> | |
fe5c8028 | 23 | #include <linux/hashtable.h> |
41aeed58 | 24 | #include <linux/ip.h> |
0d49c06b | 25 | #include <linux/rcupdate.h> |
ae695927 | 26 | #include <linux/refcount.h> |
e53edf74 | 27 | #include <linux/timer.h> |
0d49c06b | 28 | #include <linux/types.h> |
782e4a79 | 29 | #include <linux/wait.h> |
c2780c1a | 30 | #include <linux/workqueue.h> |
4a71df50 | 31 | |
980f4568 JW |
32 | #include <net/dst.h> |
33 | #include <net/ip6_fib.h> | |
4a71df50 FB |
34 | #include <net/ipv6.h> |
35 | #include <net/if_inet6.h> | |
36 | #include <net/addrconf.h> | |
1d38c2e4 | 37 | #include <net/route.h> |
eeac0e20 | 38 | #include <net/sch_generic.h> |
e517b649 | 39 | #include <net/tcp.h> |
4a71df50 FB |
40 | |
41 | #include <asm/debug.h> | |
42 | #include <asm/qdio.h> | |
43 | #include <asm/ccwdev.h> | |
44 | #include <asm/ccwgroup.h> | |
6bcac508 | 45 | #include <asm/sysinfo.h> |
4a71df50 | 46 | |
b0abc4f5 JW |
47 | #include <uapi/linux/if_link.h> |
48 | ||
4a71df50 FB |
49 | #include "qeth_core_mpc.h" |
50 | ||
51 | /** | |
52 | * Debug Facility stuff | |
53 | */ | |
d11ba0c4 PT |
54 | enum qeth_dbf_names { |
55 | QETH_DBF_SETUP, | |
d11ba0c4 | 56 | QETH_DBF_MSG, |
d11ba0c4 PT |
57 | QETH_DBF_CTRL, |
58 | QETH_DBF_INFOS /* must be last element */ | |
59 | }; | |
60 | ||
61 | struct qeth_dbf_info { | |
62 | char name[DEBUG_MAX_NAME_LEN]; | |
63 | int pages; | |
64 | int areas; | |
65 | int len; | |
66 | int level; | |
67 | struct debug_view *view; | |
68 | debug_info_t *id; | |
69 | }; | |
70 | ||
c3b2218d | 71 | #define QETH_DBF_CTRL_LEN 256U |
4a71df50 FB |
72 | |
73 | #define QETH_DBF_TEXT(name, level, text) \ | |
d11ba0c4 | 74 | debug_text_event(qeth_dbf[QETH_DBF_##name].id, level, text) |
4a71df50 FB |
75 | |
76 | #define QETH_DBF_HEX(name, level, addr, len) \ | |
d11ba0c4 PT |
77 | debug_event(qeth_dbf[QETH_DBF_##name].id, level, (void *)(addr), len) |
78 | ||
79 | #define QETH_DBF_MESSAGE(level, text...) \ | |
80 | debug_sprintf_event(qeth_dbf[QETH_DBF_MSG].id, level, text) | |
81 | ||
82 | #define QETH_DBF_TEXT_(name, level, text...) \ | |
8e96c51c | 83 | qeth_dbf_longtext(qeth_dbf[QETH_DBF_##name].id, level, text) |
4a71df50 | 84 | |
af039068 CO |
85 | #define QETH_CARD_TEXT(card, level, text) \ |
86 | debug_text_event(card->debug, level, text) | |
87 | ||
88 | #define QETH_CARD_HEX(card, level, addr, len) \ | |
89 | debug_event(card->debug, level, (void *)(addr), len) | |
90 | ||
91 | #define QETH_CARD_MESSAGE(card, text...) \ | |
92 | debug_sprintf_event(card->debug, level, text) | |
93 | ||
94 | #define QETH_CARD_TEXT_(card, level, text...) \ | |
95 | qeth_dbf_longtext(card->debug, level, text) | |
96 | ||
4a71df50 FB |
97 | #define SENSE_COMMAND_REJECT_BYTE 0 |
98 | #define SENSE_COMMAND_REJECT_FLAG 0x80 | |
99 | #define SENSE_RESETTING_EVENT_BYTE 1 | |
100 | #define SENSE_RESETTING_EVENT_FLAG 0x80 | |
101 | ||
e19e5be8 JW |
102 | static inline u32 qeth_get_device_id(struct ccw_device *cdev) |
103 | { | |
104 | struct ccw_dev_id dev_id; | |
105 | u32 id; | |
106 | ||
107 | ccw_device_get_id(cdev, &dev_id); | |
108 | id = dev_id.devno; | |
109 | id |= (u32) (dev_id.ssid << 16); | |
110 | ||
111 | return id; | |
112 | } | |
113 | ||
4a71df50 FB |
114 | /* |
115 | * Common IO related definitions | |
116 | */ | |
117 | #define CARD_RDEV(card) card->read.ccwdev | |
118 | #define CARD_WDEV(card) card->write.ccwdev | |
119 | #define CARD_DDEV(card) card->data.ccwdev | |
2a0217d5 KS |
120 | #define CARD_BUS_ID(card) dev_name(&card->gdev->dev) |
121 | #define CARD_RDEV_ID(card) dev_name(&card->read.ccwdev->dev) | |
122 | #define CARD_WDEV_ID(card) dev_name(&card->write.ccwdev->dev) | |
123 | #define CARD_DDEV_ID(card) dev_name(&card->data.ccwdev->dev) | |
e19e5be8 JW |
124 | #define CCW_DEVID(cdev) (qeth_get_device_id(cdev)) |
125 | #define CARD_DEVID(card) (CCW_DEVID(CARD_RDEV(card))) | |
4a71df50 | 126 | |
4a71df50 FB |
127 | /* Routing stuff */ |
128 | struct qeth_routing_info { | |
129 | enum qeth_routing_types type; | |
130 | }; | |
131 | ||
b4d72c08 EC |
132 | /* SETBRIDGEPORT stuff */ |
133 | enum qeth_sbp_roles { | |
134 | QETH_SBP_ROLE_NONE = 0, | |
135 | QETH_SBP_ROLE_PRIMARY = 1, | |
136 | QETH_SBP_ROLE_SECONDARY = 2, | |
137 | }; | |
138 | ||
139 | enum qeth_sbp_states { | |
140 | QETH_SBP_STATE_INACTIVE = 0, | |
141 | QETH_SBP_STATE_STANDBY = 1, | |
142 | QETH_SBP_STATE_ACTIVE = 2, | |
143 | }; | |
144 | ||
9f48b9db EC |
145 | #define QETH_SBP_HOST_NOTIFICATION 1 |
146 | ||
b4d72c08 EC |
147 | struct qeth_sbp_info { |
148 | __u32 supported_funcs; | |
149 | enum qeth_sbp_roles role; | |
9f48b9db | 150 | __u32 hostnotification:1; |
0db587b0 EC |
151 | __u32 reflect_promisc:1; |
152 | __u32 reflect_promisc_primary:1; | |
b4d72c08 EC |
153 | }; |
154 | ||
a45b3faf HW |
155 | struct qeth_vnicc_info { |
156 | /* supported/currently configured VNICCs; updated in IPA exchanges */ | |
157 | u32 sup_chars; | |
158 | u32 cur_chars; | |
caa1f0b1 HW |
159 | /* supported commands: bitmasks which VNICCs support respective cmd */ |
160 | u32 set_char_sup; | |
349d13d5 HW |
161 | u32 getset_timeout_sup; |
162 | /* timeout value for the learning characteristic */ | |
163 | u32 learning_timeout; | |
caa1f0b1 HW |
164 | /* characteristics wanted/configured by user */ |
165 | u32 wanted_chars; | |
166 | /* has user explicitly enabled rx_bcast while online? */ | |
167 | bool rx_bcast_enabled; | |
a45b3faf HW |
168 | }; |
169 | ||
5113fec0 | 170 | #define QETH_IDX_FUNC_LEVEL_OSD 0x0101 |
6298263a | 171 | #define QETH_IDX_FUNC_LEVEL_IQD 0x4108 |
4a71df50 | 172 | |
4a71df50 | 173 | #define QETH_BUFSIZE 4096 |
45ca2fd6 JW |
174 | #define CCW_CMD_WRITE 0x01 |
175 | #define CCW_CMD_READ 0x02 | |
4a71df50 FB |
176 | |
177 | /** | |
178 | * some more defs | |
179 | */ | |
378ac80d JW |
180 | #define QETH_TX_TIMEOUT (100 * HZ) |
181 | #define QETH_RCD_TIMEOUT (60 * HZ) | |
b3332930 | 182 | #define QETH_RECLAIM_WORK_TIME HZ |
4a71df50 FB |
183 | #define QETH_MAX_PORTNO 15 |
184 | ||
4a71df50 FB |
185 | /*****************************************************************************/ |
186 | /* QDIO queue and buffer handling */ | |
187 | /*****************************************************************************/ | |
d8564e19 | 188 | #define QETH_MAX_OUT_QUEUES 4 |
3a18d754 JW |
189 | #define QETH_IQD_MIN_TXQ 2 /* One for ucast, one for mcast. */ |
190 | #define QETH_IQD_MCAST_TXQ 0 | |
191 | #define QETH_IQD_MIN_UCAST_TXQ 1 | |
562cf773 | 192 | |
d8564e19 | 193 | #define QETH_MAX_IN_QUEUES 2 |
562cf773 | 194 | #define QETH_RX_COPYBREAK (PAGE_SIZE >> 1) |
4a71df50 | 195 | #define QETH_IN_BUF_SIZE_DEFAULT 65536 |
dcf4ae2d FB |
196 | #define QETH_IN_BUF_COUNT_DEFAULT 64 |
197 | #define QETH_IN_BUF_COUNT_HSDEFAULT 128 | |
ab29c480 JW |
198 | #define QETH_IN_BUF_COUNT_MIN 8U |
199 | #define QETH_IN_BUF_COUNT_MAX 128U | |
4a71df50 FB |
200 | #define QETH_MAX_BUFFER_ELEMENTS(card) ((card)->qdio.in_buf_size >> 12) |
201 | #define QETH_IN_BUF_REQUEUE_THRESHOLD(card) \ | |
0284a0fd | 202 | ((card)->qdio.in_buf_pool.buf_count / 2) |
4a71df50 FB |
203 | |
204 | /* buffers we have to be behind before we get a PCI */ | |
205 | #define QETH_PCI_THRESHOLD_A(card) ((card)->qdio.in_buf_pool.buf_count+1) | |
206 | /*enqueued free buffers left before we get a PCI*/ | |
207 | #define QETH_PCI_THRESHOLD_B(card) 0 | |
208 | /*not used unless the microcode gets patched*/ | |
209 | #define QETH_PCI_TIMER_VALUE(card) 3 | |
210 | ||
4a71df50 FB |
211 | /* priority queing */ |
212 | #define QETH_PRIOQ_DEFAULT QETH_NO_PRIO_QUEUEING | |
213 | #define QETH_DEFAULT_QUEUE 2 | |
214 | #define QETH_NO_PRIO_QUEUEING 0 | |
215 | #define QETH_PRIO_Q_ING_PREC 1 | |
216 | #define QETH_PRIO_Q_ING_TOS 2 | |
d66cb37e SR |
217 | #define QETH_PRIO_Q_ING_SKB 3 |
218 | #define QETH_PRIO_Q_ING_VLAN 4 | |
c91a1fb7 | 219 | #define QETH_PRIO_Q_ING_FIXED 5 |
4a71df50 FB |
220 | |
221 | /* Packing */ | |
222 | #define QETH_LOW_WATERMARK_PACK 2 | |
223 | #define QETH_HIGH_WATERMARK_PACK 5 | |
224 | #define QETH_WATERMARK_PACK_FUZZ 1 | |
225 | ||
4a71df50 FB |
226 | struct qeth_hdr_layer3 { |
227 | __u8 id; | |
228 | __u8 flags; | |
229 | __u16 inbound_checksum; /*TSO:__u16 seqno */ | |
230 | __u32 token; /*TSO: __u32 reserved */ | |
231 | __u16 length; | |
232 | __u8 vlan_prio; | |
233 | __u8 ext_flags; | |
234 | __u16 vlan_id; | |
235 | __u16 frame_offset; | |
a843383a JW |
236 | union { |
237 | /* TX: */ | |
1d38c2e4 | 238 | struct in6_addr addr; |
a843383a JW |
239 | /* RX: */ |
240 | struct rx { | |
241 | u8 res1[2]; | |
242 | u8 src_mac[6]; | |
243 | u8 res2[4]; | |
244 | u16 vlan_id; | |
245 | u8 res3[2]; | |
246 | } rx; | |
247 | } next_hop; | |
248 | }; | |
4a71df50 FB |
249 | |
250 | struct qeth_hdr_layer2 { | |
251 | __u8 id; | |
252 | __u8 flags[3]; | |
253 | __u8 port_no; | |
254 | __u8 hdr_length; | |
255 | __u16 pkt_length; | |
256 | __u16 seq_no; | |
257 | __u16 vlan_id; | |
258 | __u32 reserved; | |
259 | __u8 reserved2[16]; | |
260 | } __attribute__ ((packed)); | |
261 | ||
4a71df50 FB |
262 | struct qeth_hdr { |
263 | union { | |
264 | struct qeth_hdr_layer2 l2; | |
265 | struct qeth_hdr_layer3 l3; | |
4a71df50 FB |
266 | } hdr; |
267 | } __attribute__ ((packed)); | |
268 | ||
949bbf4d JW |
269 | #define QETH_QIB_PQUE_ORDER_RR 0 |
270 | #define QETH_QIB_PQUE_UNITS_SBAL 2 | |
271 | #define QETH_QIB_PQUE_PRIO_DEFAULT 4 | |
272 | ||
72d5e850 JW |
273 | struct qeth_qib_parms { |
274 | char pcit_magic[4]; | |
275 | u32 pcit_a; | |
276 | u32 pcit_b; | |
277 | u32 pcit_c; | |
278 | char blkt_magic[4]; | |
279 | u32 blkt_total; | |
280 | u32 blkt_inter_packet; | |
281 | u32 blkt_inter_packet_jumbo; | |
949bbf4d JW |
282 | char pque_magic[4]; |
283 | u8 pque_order; | |
284 | u8 pque_units; | |
285 | u16 reserved; | |
286 | u32 pque_priority[4]; | |
72d5e850 JW |
287 | }; |
288 | ||
4a71df50 FB |
289 | /*TCP Segmentation Offload header*/ |
290 | struct qeth_hdr_ext_tso { | |
291 | __u16 hdr_tot_len; | |
292 | __u8 imb_hdr_no; | |
293 | __u8 reserved; | |
294 | __u8 hdr_type; | |
295 | __u8 hdr_version; | |
296 | __u16 hdr_len; | |
297 | __u32 payload_len; | |
298 | __u16 mss; | |
299 | __u16 dg_hdr_len; | |
300 | __u8 padding[16]; | |
301 | } __attribute__ ((packed)); | |
302 | ||
303 | struct qeth_hdr_tso { | |
304 | struct qeth_hdr hdr; /*hdr->hdr.l3.xxx*/ | |
305 | struct qeth_hdr_ext_tso ext; | |
306 | } __attribute__ ((packed)); | |
307 | ||
308 | ||
309 | /* flags for qeth_hdr.flags */ | |
310 | #define QETH_HDR_PASSTHRU 0x10 | |
311 | #define QETH_HDR_IPV6 0x80 | |
312 | #define QETH_HDR_CAST_MASK 0x07 | |
313 | enum qeth_cast_flags { | |
314 | QETH_CAST_UNICAST = 0x06, | |
315 | QETH_CAST_MULTICAST = 0x04, | |
316 | QETH_CAST_BROADCAST = 0x05, | |
317 | QETH_CAST_ANYCAST = 0x07, | |
318 | QETH_CAST_NOCAST = 0x00, | |
319 | }; | |
320 | ||
321 | enum qeth_layer2_frame_flags { | |
322 | QETH_LAYER2_FLAG_MULTICAST = 0x01, | |
323 | QETH_LAYER2_FLAG_BROADCAST = 0x02, | |
324 | QETH_LAYER2_FLAG_UNICAST = 0x04, | |
325 | QETH_LAYER2_FLAG_VLAN = 0x10, | |
326 | }; | |
327 | ||
328 | enum qeth_header_ids { | |
329 | QETH_HEADER_TYPE_LAYER3 = 0x01, | |
330 | QETH_HEADER_TYPE_LAYER2 = 0x02, | |
0aef8392 | 331 | QETH_HEADER_TYPE_L3_TSO = 0x03, |
0aef8392 | 332 | QETH_HEADER_TYPE_L2_TSO = 0x06, |
5fd3fcbb | 333 | QETH_HEADER_MASK_INVAL = 0x80, |
4a71df50 FB |
334 | }; |
335 | /* flags for qeth_hdr.ext_flags */ | |
336 | #define QETH_HDR_EXT_VLAN_FRAME 0x01 | |
337 | #define QETH_HDR_EXT_TOKEN_ID 0x02 | |
338 | #define QETH_HDR_EXT_INCLUDE_VLAN_TAG 0x04 | |
339 | #define QETH_HDR_EXT_SRC_MAC_ADDR 0x08 | |
340 | #define QETH_HDR_EXT_CSUM_HDR_REQ 0x10 | |
341 | #define QETH_HDR_EXT_CSUM_TRANSP_REQ 0x20 | |
f6b85b6c | 342 | #define QETH_HDR_EXT_UDP 0x40 /*bit off for TCP*/ |
4a71df50 | 343 | |
9549d70a JW |
344 | static inline bool qeth_l2_same_vlan(struct qeth_hdr_layer2 *h1, |
345 | struct qeth_hdr_layer2 *h2) | |
346 | { | |
347 | return !((h1->flags[2] ^ h2->flags[2]) & QETH_LAYER2_FLAG_VLAN) && | |
348 | h1->vlan_id == h2->vlan_id; | |
349 | } | |
350 | ||
351 | static inline bool qeth_l3_iqd_same_vlan(struct qeth_hdr_layer3 *h1, | |
352 | struct qeth_hdr_layer3 *h2) | |
353 | { | |
354 | return !((h1->ext_flags ^ h2->ext_flags) & QETH_HDR_EXT_VLAN_FRAME) && | |
355 | h1->vlan_id == h2->vlan_id; | |
356 | } | |
357 | ||
358 | static inline bool qeth_l3_same_next_hop(struct qeth_hdr_layer3 *h1, | |
359 | struct qeth_hdr_layer3 *h2) | |
360 | { | |
361 | return !((h1->flags ^ h2->flags) & QETH_HDR_IPV6) && | |
1d38c2e4 | 362 | ipv6_addr_equal(&h1->next_hop.addr, &h2->next_hop.addr); |
9549d70a JW |
363 | } |
364 | ||
0d49c06b JW |
365 | struct qeth_local_addr { |
366 | struct hlist_node hnode; | |
367 | struct rcu_head rcu; | |
368 | struct in6_addr addr; | |
369 | }; | |
370 | ||
4a71df50 FB |
371 | enum qeth_qdio_info_states { |
372 | QETH_QDIO_UNINITIALIZED, | |
373 | QETH_QDIO_ALLOCATED, | |
374 | QETH_QDIO_ESTABLISHED, | |
375 | QETH_QDIO_CLEANING | |
376 | }; | |
377 | ||
378 | struct qeth_buffer_pool_entry { | |
379 | struct list_head list; | |
380 | struct list_head init_list; | |
f81649df | 381 | struct page *elements[QDIO_MAX_ELEMENTS_PER_BUFFER]; |
4a71df50 FB |
382 | }; |
383 | ||
384 | struct qeth_qdio_buffer_pool { | |
385 | struct list_head entry_list; | |
386 | int buf_count; | |
387 | }; | |
388 | ||
389 | struct qeth_qdio_buffer { | |
390 | struct qdio_buffer *buffer; | |
391 | /* the buffer pool entry currently associated to this buffer */ | |
392 | struct qeth_buffer_pool_entry *pool_entry; | |
b3332930 | 393 | struct sk_buff *rx_skb; |
4a71df50 FB |
394 | }; |
395 | ||
396 | struct qeth_qdio_q { | |
6d284bde | 397 | struct qdio_buffer *qdio_bufs[QDIO_MAX_BUFFERS_PER_Q]; |
4a71df50 FB |
398 | struct qeth_qdio_buffer bufs[QDIO_MAX_BUFFERS_PER_Q]; |
399 | int next_buf_to_init; | |
6d284bde | 400 | }; |
4a71df50 | 401 | |
5c0bfba7 JW |
402 | enum qeth_qdio_out_buffer_state { |
403 | /* Owned by driver, in order to be filled. */ | |
404 | QETH_QDIO_BUF_EMPTY, | |
405 | /* Filled by driver; owned by hardware in order to be sent. */ | |
406 | QETH_QDIO_BUF_PRIMED, | |
838e4cc8 JW |
407 | }; |
408 | ||
409 | enum qeth_qaob_state { | |
410 | QETH_QAOB_ISSUED, | |
411 | QETH_QAOB_PENDING, | |
412 | QETH_QAOB_DONE, | |
413 | }; | |
414 | ||
415 | struct qeth_qaob_priv1 { | |
416 | unsigned int state; | |
417 | u8 queue_no; | |
5c0bfba7 JW |
418 | }; |
419 | ||
4a71df50 FB |
420 | struct qeth_qdio_out_buffer { |
421 | struct qdio_buffer *buffer; | |
422 | atomic_t state; | |
423 | int next_element_to_fill; | |
1ab2f8c6 | 424 | unsigned int frames; |
96bd6c94 | 425 | unsigned int bytes; |
4a71df50 | 426 | struct sk_buff_head skb_list; |
bb7032dd | 427 | DECLARE_BITMAP(from_kmem_cache, QDIO_MAX_ELEMENTS_PER_BUFFER); |
0da9581d | 428 | |
c20383ad | 429 | struct list_head list_entry; |
396c1004 | 430 | struct qaob *aob; |
4a71df50 FB |
431 | }; |
432 | ||
433 | struct qeth_card; | |
434 | ||
b0abc4f5 JW |
435 | #define QETH_CARD_STAT_ADD(_c, _stat, _val) ((_c)->stats._stat += (_val)) |
436 | #define QETH_CARD_STAT_INC(_c, _stat) QETH_CARD_STAT_ADD(_c, _stat, 1) | |
437 | ||
438 | #define QETH_TXQ_STAT_ADD(_q, _stat, _val) ((_q)->stats._stat += (_val)) | |
439 | #define QETH_TXQ_STAT_INC(_q, _stat) QETH_TXQ_STAT_ADD(_q, _stat, 1) | |
440 | ||
441 | struct qeth_card_stats { | |
442 | u64 rx_bufs; | |
443 | u64 rx_skb_csum; | |
444 | u64 rx_sg_skbs; | |
445 | u64 rx_sg_frags; | |
446 | u64 rx_sg_alloc_page; | |
447 | ||
845ef904 JW |
448 | u64 rx_dropped_nomem; |
449 | u64 rx_dropped_notsupp; | |
5b55633f | 450 | u64 rx_dropped_runt; |
845ef904 | 451 | |
b0abc4f5 JW |
452 | /* rtnl_link_stats64 */ |
453 | u64 rx_packets; | |
454 | u64 rx_bytes; | |
b0abc4f5 | 455 | u64 rx_multicast; |
845ef904 | 456 | u64 rx_length_errors; |
5fd3fcbb | 457 | u64 rx_frame_errors; |
845ef904 | 458 | u64 rx_fifo_errors; |
b0abc4f5 JW |
459 | }; |
460 | ||
461 | struct qeth_out_q_stats { | |
462 | u64 bufs; | |
463 | u64 bufs_pack; | |
464 | u64 buf_elements; | |
465 | u64 skbs_pack; | |
466 | u64 skbs_sg; | |
467 | u64 skbs_csum; | |
468 | u64 skbs_tso; | |
469 | u64 skbs_linearized; | |
470 | u64 skbs_linearized_fail; | |
471 | u64 tso_bytes; | |
472 | u64 packing_mode_switch; | |
54a50941 | 473 | u64 stopped; |
1ab2f8c6 | 474 | u64 doorbell; |
ee1e52d1 | 475 | u64 coal_frames; |
e872d0c1 | 476 | u64 completion_irq; |
e53edf74 JW |
477 | u64 completion_yield; |
478 | u64 completion_timer; | |
b0abc4f5 JW |
479 | |
480 | /* rtnl_link_stats64 */ | |
481 | u64 tx_packets; | |
482 | u64 tx_bytes; | |
483 | u64 tx_errors; | |
484 | u64 tx_dropped; | |
b0abc4f5 JW |
485 | }; |
486 | ||
ee1e52d1 JW |
487 | #define QETH_TX_MAX_COALESCED_FRAMES 1 |
488 | #define QETH_TX_COALESCE_USECS 25 | |
e53edf74 JW |
489 | #define QETH_TX_TIMER_USECS 500 |
490 | ||
4a71df50 | 491 | struct qeth_qdio_out_q { |
d445a4e2 | 492 | struct qdio_buffer *qdio_bufs[QDIO_MAX_BUFFERS_PER_Q]; |
0da9581d | 493 | struct qeth_qdio_out_buffer *bufs[QDIO_MAX_BUFFERS_PER_Q]; |
c20383ad | 494 | struct list_head pending_bufs; |
b0abc4f5 | 495 | struct qeth_out_q_stats stats; |
a1668474 | 496 | spinlock_t lock; |
949bbf4d | 497 | unsigned int priority; |
4e26c5fe JW |
498 | u8 next_buf_to_fill; |
499 | u8 max_elements; | |
500 | u8 queue_no; | |
501 | u8 do_pack; | |
4a71df50 | 502 | struct qeth_card *card; |
4a71df50 FB |
503 | /* |
504 | * number of buffers that are currently filled (PRIMED) | |
505 | * -> these buffers are hardware-owned | |
506 | */ | |
507 | atomic_t used_buffers; | |
508 | /* indicates whether PCI flag must be set (or if one is outstanding) */ | |
509 | atomic_t set_pci_flags_count; | |
e53edf74 JW |
510 | struct napi_struct napi; |
511 | struct timer_list timer; | |
9549d70a | 512 | struct qeth_hdr *prev_hdr; |
ee1e52d1 | 513 | unsigned int coalesced_frames; |
9549d70a | 514 | u8 bulk_start; |
8b664cd1 JW |
515 | u8 bulk_count; |
516 | u8 bulk_max; | |
ee1e52d1 JW |
517 | |
518 | unsigned int coalesce_usecs; | |
519 | unsigned int max_coalesced_frames; | |
7a4b92e8 | 520 | unsigned int rescan_usecs; |
d445a4e2 | 521 | }; |
4a71df50 | 522 | |
e53edf74 JW |
523 | #define qeth_for_each_output_queue(card, q, i) \ |
524 | for (i = 0; i < card->qdio.no_out_queues && \ | |
525 | (q = card->qdio.out_qs[i]); i++) | |
526 | ||
527 | #define qeth_napi_to_out_queue(n) container_of(n, struct qeth_qdio_out_q, napi) | |
528 | ||
ee1e52d1 JW |
529 | static inline void qeth_tx_arm_timer(struct qeth_qdio_out_q *queue, |
530 | unsigned long usecs) | |
e53edf74 | 531 | { |
ee1e52d1 | 532 | timer_reduce(&queue->timer, usecs_to_jiffies(usecs) + jiffies); |
e53edf74 JW |
533 | } |
534 | ||
54a50941 JW |
535 | static inline bool qeth_out_queue_is_full(struct qeth_qdio_out_q *queue) |
536 | { | |
537 | return atomic_read(&queue->used_buffers) >= QDIO_MAX_BUFFERS_PER_Q; | |
538 | } | |
539 | ||
e53edf74 JW |
540 | static inline bool qeth_out_queue_is_empty(struct qeth_qdio_out_q *queue) |
541 | { | |
542 | return atomic_read(&queue->used_buffers) == 0; | |
543 | } | |
544 | ||
4a71df50 FB |
545 | struct qeth_qdio_info { |
546 | atomic_t state; | |
547 | /* input */ | |
548 | struct qeth_qdio_q *in_q; | |
0da9581d | 549 | struct qeth_qdio_q *c_q; |
4a71df50 FB |
550 | struct qeth_qdio_buffer_pool in_buf_pool; |
551 | struct qeth_qdio_buffer_pool init_pool; | |
552 | int in_buf_size; | |
553 | ||
554 | /* output */ | |
bb5ab541 | 555 | unsigned int no_out_queues; |
d8564e19 | 556 | struct qeth_qdio_out_q *out_qs[QETH_MAX_OUT_QUEUES]; |
4a71df50 FB |
557 | |
558 | /* priority queueing */ | |
559 | int do_prio_queueing; | |
560 | int default_out_queue; | |
561 | }; | |
562 | ||
4a71df50 FB |
563 | /** |
564 | * channel state machine | |
565 | */ | |
566 | enum qeth_channel_states { | |
567 | CH_STATE_UP, | |
568 | CH_STATE_DOWN, | |
4a71df50 FB |
569 | CH_STATE_HALTED, |
570 | CH_STATE_STOPPED, | |
4a71df50 FB |
571 | }; |
572 | /** | |
573 | * card state machine | |
574 | */ | |
575 | enum qeth_card_states { | |
576 | CARD_STATE_DOWN, | |
4a71df50 | 577 | CARD_STATE_SOFTSETUP, |
4a71df50 FB |
578 | }; |
579 | ||
580 | /** | |
581 | * Protocol versions | |
582 | */ | |
583 | enum qeth_prot_versions { | |
a59d121d | 584 | QETH_PROT_NONE = 0x0000, |
4a71df50 FB |
585 | QETH_PROT_IPV4 = 0x0004, |
586 | QETH_PROT_IPV6 = 0x0006, | |
587 | }; | |
588 | ||
0da9581d EL |
589 | enum qeth_cq { |
590 | QETH_CQ_DISABLED = 0, | |
591 | QETH_CQ_ENABLED = 1, | |
592 | QETH_CQ_NOTAVAILABLE = 2, | |
593 | }; | |
594 | ||
4a71df50 | 595 | struct qeth_ipato { |
7fbd9493 | 596 | bool enabled; |
02f510f3 JW |
597 | bool invert4; |
598 | bool invert6; | |
4a71df50 FB |
599 | struct list_head entries; |
600 | }; | |
601 | ||
c3b2218d JW |
602 | struct qeth_channel { |
603 | struct ccw_device *ccwdev; | |
f9e50b02 | 604 | struct qeth_cmd_buffer *active_cmd; |
c3b2218d | 605 | enum qeth_channel_states state; |
c3b2218d | 606 | }; |
4a71df50 | 607 | |
308946b0 JW |
608 | struct qeth_reply { |
609 | int (*callback)(struct qeth_card *card, struct qeth_reply *reply, | |
610 | unsigned long data); | |
611 | void *param; | |
612 | }; | |
613 | ||
4a71df50 | 614 | struct qeth_cmd_buffer { |
04ea30c8 | 615 | struct list_head list_entry; |
308946b0 JW |
616 | struct completion done; |
617 | spinlock_t lock; | |
40554895 | 618 | unsigned int length; |
d9b9f40b | 619 | refcount_t ref_count; |
4a71df50 | 620 | struct qeth_channel *channel; |
308946b0 | 621 | struct qeth_reply reply; |
782e4a79 | 622 | long timeout; |
4a71df50 | 623 | unsigned char *data; |
c3b2218d | 624 | void (*finalize)(struct qeth_card *card, struct qeth_cmd_buffer *iob); |
7f92316c JW |
625 | bool (*match)(struct qeth_cmd_buffer *iob, |
626 | struct qeth_cmd_buffer *reply); | |
12fc286f JW |
627 | void (*callback)(struct qeth_card *card, struct qeth_cmd_buffer *iob, |
628 | unsigned int data_length); | |
308946b0 | 629 | int rc; |
4a71df50 FB |
630 | }; |
631 | ||
d9b9f40b JW |
632 | static inline void qeth_get_cmd(struct qeth_cmd_buffer *iob) |
633 | { | |
634 | refcount_inc(&iob->ref_count); | |
635 | } | |
636 | ||
7f92316c JW |
637 | static inline struct qeth_ipa_cmd *__ipa_reply(struct qeth_cmd_buffer *iob) |
638 | { | |
639 | if (!IS_IPA(iob->data)) | |
640 | return NULL; | |
641 | ||
642 | return (struct qeth_ipa_cmd *) PDU_ENCAPSULATION(iob->data); | |
643 | } | |
644 | ||
1c5b2216 JW |
645 | static inline struct qeth_ipa_cmd *__ipa_cmd(struct qeth_cmd_buffer *iob) |
646 | { | |
647 | return (struct qeth_ipa_cmd *)(iob->data + IPA_PDU_HEADER_SIZE); | |
648 | } | |
649 | ||
40554895 JW |
650 | static inline struct ccw1 *__ccw_from_cmd(struct qeth_cmd_buffer *iob) |
651 | { | |
40554895 JW |
652 | return (struct ccw1 *)(iob->data + ALIGN(iob->length, 8)); |
653 | } | |
654 | ||
4a71df50 FB |
655 | /** |
656 | * OSA card related definitions | |
657 | */ | |
658 | struct qeth_token { | |
659 | __u32 issuer_rm_w; | |
660 | __u32 issuer_rm_r; | |
661 | __u32 cm_filter_w; | |
662 | __u32 cm_filter_r; | |
663 | __u32 cm_connection_w; | |
664 | __u32 cm_connection_r; | |
665 | __u32 ulp_filter_w; | |
666 | __u32 ulp_filter_r; | |
667 | __u32 ulp_connection_w; | |
668 | __u32 ulp_connection_r; | |
669 | }; | |
670 | ||
671 | struct qeth_seqno { | |
672 | __u32 trans_hdr; | |
673 | __u32 pdu_hdr; | |
674 | __u32 pdu_hdr_ack; | |
675 | __u16 ipa; | |
4a71df50 FB |
676 | }; |
677 | ||
4a71df50 FB |
678 | struct qeth_card_blkt { |
679 | int time_total; | |
680 | int inter_packet; | |
681 | int inter_packet_jumbo; | |
682 | }; | |
683 | ||
9d6a569a JW |
684 | enum qeth_pnso_mode { |
685 | QETH_PNSO_NONE, | |
686 | QETH_PNSO_BRIDGEPORT, | |
10a6cfc0 | 687 | QETH_PNSO_ADDR_INFO, |
9d6a569a JW |
688 | }; |
689 | ||
235db527 JW |
690 | enum qeth_link_mode { |
691 | QETH_LINK_MODE_UNKNOWN, | |
692 | QETH_LINK_MODE_FIBRE_SHORT, | |
693 | QETH_LINK_MODE_FIBRE_LONG, | |
694 | }; | |
695 | ||
4139b2b1 JW |
696 | struct qeth_link_info { |
697 | u32 speed; | |
698 | u8 duplex; | |
699 | u8 port; | |
235db527 | 700 | enum qeth_link_mode link_mode; |
4139b2b1 JW |
701 | }; |
702 | ||
4a71df50 FB |
703 | #define QETH_BROADCAST_WITH_ECHO 0x01 |
704 | #define QETH_BROADCAST_WITHOUT_ECHO 0x02 | |
4a71df50 FB |
705 | struct qeth_card_info { |
706 | unsigned short unit_addr2; | |
707 | unsigned short cula; | |
4a71df50 FB |
708 | __u16 func_level; |
709 | char mcl_level[QETH_MCL_LENGTH + 1]; | |
fa115adf AW |
710 | /* doubleword below corresponds to net_if_token */ |
711 | u16 ddev_devno; | |
712 | u8 cssid; | |
713 | u8 iid; | |
714 | u8 ssid; | |
715 | u8 chpid; | |
716 | u16 chid; | |
717 | u8 ids_valid:1; /* cssid,iid,chid */ | |
9de15117 | 718 | u8 dev_addr_is_registered:1; |
59b757a9 | 719 | u8 promisc_mode:1; |
09ac887f | 720 | u8 use_v1_blkt:1; |
379ac99e | 721 | u8 is_vm_nic:1; |
3be83016 JW |
722 | /* no bitfield, we take a pointer on these two: */ |
723 | u8 has_lp2lp_cso_v6; | |
724 | u8 has_lp2lp_cso_v4; | |
9d6a569a | 725 | enum qeth_pnso_mode pnso_mode; |
4a71df50 FB |
726 | enum qeth_card_types type; |
727 | enum qeth_link_types link_type; | |
4a71df50 | 728 | int broadcast_capable; |
c70eb09d | 729 | bool layer_enforced; |
4a71df50 | 730 | struct qeth_card_blkt blkt; |
1da74b1c FB |
731 | __u32 diagass_support; |
732 | __u32 hwtrap; | |
baf7998d | 733 | struct qeth_link_info link_info; |
4a71df50 FB |
734 | }; |
735 | ||
4fda3354 JW |
736 | enum qeth_discipline_id { |
737 | QETH_DISCIPLINE_UNDETERMINED = -1, | |
738 | QETH_DISCIPLINE_LAYER3 = 0, | |
739 | QETH_DISCIPLINE_LAYER2 = 1, | |
740 | }; | |
741 | ||
4a71df50 | 742 | struct qeth_card_options { |
52f82bf1 JW |
743 | struct qeth_ipa_caps ipa4; |
744 | struct qeth_ipa_caps ipa6; | |
4a71df50 | 745 | struct qeth_routing_info route4; |
4a71df50 | 746 | struct qeth_routing_info route6; |
52f82bf1 | 747 | struct qeth_ipa_caps adp; /* Adapter parameters */ |
b4d72c08 | 748 | struct qeth_sbp_info sbp; /* SETBRIDGEPORT options */ |
a45b3faf | 749 | struct qeth_vnicc_info vnicc; /* VNICC options */ |
4fda3354 | 750 | enum qeth_discipline_id layer; |
d64ecc22 | 751 | enum qeth_ipa_isolation_modes isolation; |
76b11f8e | 752 | int sniffer; |
0da9581d | 753 | enum qeth_cq cq; |
b3332930 | 754 | char hsuid[9]; |
4a71df50 FB |
755 | }; |
756 | ||
4fda3354 JW |
757 | #define IS_LAYER2(card) ((card)->options.layer == QETH_DISCIPLINE_LAYER2) |
758 | #define IS_LAYER3(card) ((card)->options.layer == QETH_DISCIPLINE_LAYER3) | |
759 | ||
4a71df50 FB |
760 | /* |
761 | * thread bits for qeth_card thread masks | |
762 | */ | |
763 | enum qeth_threads { | |
764 | QETH_RECOVER_THREAD = 1, | |
765 | }; | |
766 | ||
4a71df50 | 767 | struct qeth_discipline { |
c041f2d4 SO |
768 | int (*setup) (struct ccwgroup_device *); |
769 | void (*remove) (struct ccwgroup_device *); | |
b7ea041b | 770 | int (*set_online)(struct qeth_card *card, bool carrier_ok); |
91003f35 | 771 | void (*set_offline)(struct qeth_card *card); |
c044dc21 EC |
772 | int (*control_event_handler)(struct qeth_card *card, |
773 | struct qeth_ipa_cmd *cmd); | |
4a71df50 FB |
774 | }; |
775 | ||
5f78e29c LD |
776 | enum qeth_addr_disposition { |
777 | QETH_DISP_ADDR_DELETE = 0, | |
778 | QETH_DISP_ADDR_DO_NOTHING = 1, | |
779 | QETH_DISP_ADDR_ADD = 2, | |
4a71df50 FB |
780 | }; |
781 | ||
a1c3ed4c FB |
782 | struct qeth_rx { |
783 | int b_count; | |
784 | int b_index; | |
ed13615d | 785 | u8 buf_element; |
a1c3ed4c FB |
786 | int e_offset; |
787 | int qdio_err; | |
7c94a882 | 788 | u8 bufs_refill; |
a1c3ed4c FB |
789 | }; |
790 | ||
45cbb2e4 SR |
791 | struct qeth_switch_info { |
792 | __u32 capabilities; | |
793 | __u32 settings; | |
794 | }; | |
795 | ||
562cf773 JW |
796 | struct qeth_priv { |
797 | unsigned int rx_copybreak; | |
bb5ab541 | 798 | unsigned int tx_wanted_queues; |
fa115adf | 799 | u32 brport_hw_features; |
817741a8 | 800 | u32 brport_features; |
562cf773 JW |
801 | }; |
802 | ||
4a71df50 | 803 | struct qeth_card { |
4a71df50 | 804 | enum qeth_card_states state; |
4a71df50 FB |
805 | spinlock_t lock; |
806 | struct ccwgroup_device *gdev; | |
d9b9f40b | 807 | struct qeth_cmd_buffer *read_cmd; |
4a71df50 FB |
808 | struct qeth_channel read; |
809 | struct qeth_channel write; | |
810 | struct qeth_channel data; | |
811 | ||
812 | struct net_device *dev; | |
fb8d2580 | 813 | struct dentry *debugfs; |
b0abc4f5 | 814 | struct qeth_card_stats stats; |
4a71df50 FB |
815 | struct qeth_card_info info; |
816 | struct qeth_token token; | |
817 | struct qeth_seqno seqno; | |
818 | struct qeth_card_options options; | |
819 | ||
c0a2e4d1 | 820 | struct workqueue_struct *event_wq; |
7686e4b6 | 821 | struct workqueue_struct *cmd_wq; |
4a71df50 | 822 | wait_queue_head_t wait_q; |
d6e6426f JW |
823 | |
824 | struct mutex ip_lock; | |
825 | /* protected by ip_lock: */ | |
5f78e29c | 826 | DECLARE_HASHTABLE(ip_htable, 4); |
d6e6426f JW |
827 | struct qeth_ipato ipato; |
828 | ||
0d49c06b JW |
829 | DECLARE_HASHTABLE(local_addrs4, 4); |
830 | DECLARE_HASHTABLE(local_addrs6, 4); | |
831 | spinlock_t local_addrs4_lock; | |
832 | spinlock_t local_addrs6_lock; | |
0973292f | 833 | DECLARE_HASHTABLE(rx_mode_addrs, 4); |
d0c74825 | 834 | struct work_struct rx_mode_work; |
4a71df50 FB |
835 | struct work_struct kernel_thread_starter; |
836 | spinlock_t thread_mask_lock; | |
837 | unsigned long thread_start_mask; | |
838 | unsigned long thread_allowed_mask; | |
839 | unsigned long thread_running_mask; | |
4a71df50 FB |
840 | struct list_head cmd_waiter_list; |
841 | /* QDIO buffer handling */ | |
842 | struct qeth_qdio_info qdio; | |
908abbb5 | 843 | int read_or_write_problem; |
50144f67 | 844 | const struct qeth_discipline *discipline; |
4a71df50 | 845 | atomic_t force_alloc_skb; |
6bcac508 | 846 | struct service_level qeth_service_level; |
76b11f8e | 847 | struct qdio_ssqd_desc ssqd; |
af039068 | 848 | debug_info_t *debug; |
c8183f54 | 849 | struct mutex sbp_lock; |
c4949f07 | 850 | struct mutex conf_mutex; |
9dc48ccc | 851 | struct mutex discipline_mutex; |
a1c3ed4c FB |
852 | struct napi_struct napi; |
853 | struct qeth_rx rx; | |
b3332930 | 854 | struct delayed_work buffer_reclaim_work; |
4a71df50 FB |
855 | }; |
856 | ||
0f7aedbd JW |
857 | static inline bool qeth_card_hw_is_reachable(struct qeth_card *card) |
858 | { | |
859 | return card->state == CARD_STATE_SOFTSETUP; | |
860 | } | |
861 | ||
7a4b92e8 JW |
862 | static inline bool qeth_use_tx_irqs(struct qeth_card *card) |
863 | { | |
864 | return !IS_IQD(card); | |
865 | } | |
866 | ||
7359393f JW |
867 | static inline void qeth_unlock_channel(struct qeth_card *card, |
868 | struct qeth_channel *channel) | |
869 | { | |
3518ae76 | 870 | xchg(&channel->active_cmd, NULL); |
7359393f JW |
871 | wake_up(&card->wait_q); |
872 | } | |
873 | ||
3518ae76 JW |
874 | static inline bool qeth_trylock_channel(struct qeth_channel *channel, |
875 | struct qeth_cmd_buffer *cmd) | |
876 | { | |
877 | return cmpxchg(&channel->active_cmd, NULL, cmd) == NULL; | |
878 | } | |
879 | ||
1da74b1c FB |
880 | struct qeth_trap_id { |
881 | __u16 lparnr; | |
882 | char vmname[8]; | |
883 | __u8 chpid; | |
884 | __u8 ssid; | |
885 | __u16 devno; | |
886 | } __packed; | |
887 | ||
949bbf4d JW |
888 | static inline bool qeth_uses_tx_prio_queueing(struct qeth_card *card) |
889 | { | |
890 | return card->qdio.do_prio_queueing != QETH_NO_PRIO_QUEUEING; | |
891 | } | |
892 | ||
bb5ab541 JW |
893 | static inline unsigned int qeth_tx_actual_queues(struct qeth_card *card) |
894 | { | |
895 | struct qeth_priv *priv = netdev_priv(card->dev); | |
896 | ||
949bbf4d JW |
897 | if (qeth_uses_tx_prio_queueing(card)) |
898 | return min(card->dev->num_tx_queues, card->qdio.no_out_queues); | |
899 | ||
bb5ab541 JW |
900 | return min(priv->tx_wanted_queues, card->qdio.no_out_queues); |
901 | } | |
902 | ||
3a18d754 JW |
903 | static inline u16 qeth_iqd_translate_txq(struct net_device *dev, u16 txq) |
904 | { | |
905 | if (txq == QETH_IQD_MCAST_TXQ) | |
906 | return dev->num_tx_queues - 1; | |
907 | if (txq == dev->num_tx_queues - 1) | |
908 | return QETH_IQD_MCAST_TXQ; | |
909 | return txq; | |
910 | } | |
911 | ||
8b664cd1 JW |
912 | static inline bool qeth_iqd_is_mcast_queue(struct qeth_card *card, |
913 | struct qeth_qdio_out_q *queue) | |
914 | { | |
915 | return qeth_iqd_translate_txq(card->dev, queue->queue_no) == | |
916 | QETH_IQD_MCAST_TXQ; | |
917 | } | |
918 | ||
ce28867f JW |
919 | static inline void qeth_scrub_qdio_buffer(struct qdio_buffer *buf, |
920 | unsigned int elements) | |
921 | { | |
922 | unsigned int i; | |
923 | ||
924 | for (i = 0; i < elements; i++) | |
925 | memset(&buf->element[i], 0, sizeof(struct qdio_buffer_element)); | |
926 | buf->element[14].sflags = 0; | |
927 | buf->element[15].sflags = 0; | |
928 | } | |
929 | ||
2863c613 EC |
930 | /** |
931 | * qeth_get_elements_for_range() - find number of SBALEs to cover range. | |
932 | * @start: Start of the address range. | |
933 | * @end: Address after the end of the range. | |
934 | * | |
935 | * Returns the number of pages, and thus QDIO buffer elements, needed to cover | |
936 | * the specified address range. | |
937 | */ | |
938 | static inline int qeth_get_elements_for_range(addr_t start, addr_t end) | |
939 | { | |
89271c65 | 940 | return PFN_UP(end) - PFN_DOWN(start); |
2863c613 EC |
941 | } |
942 | ||
58aa2491 JW |
943 | static inline int qeth_get_ether_cast_type(struct sk_buff *skb) |
944 | { | |
945 | u8 *addr = eth_hdr(skb)->h_dest; | |
946 | ||
947 | if (is_multicast_ether_addr(addr)) | |
948 | return is_broadcast_ether_addr(addr) ? RTN_BROADCAST : | |
949 | RTN_MULTICAST; | |
950 | return RTN_UNICAST; | |
951 | } | |
952 | ||
17f3a8b5 JW |
953 | static inline struct dst_entry *qeth_dst_check_rcu(struct sk_buff *skb, |
954 | __be16 proto) | |
980f4568 JW |
955 | { |
956 | struct dst_entry *dst = skb_dst(skb); | |
957 | struct rt6_info *rt; | |
958 | ||
e8dfd42c | 959 | rt = dst_rt6_info(dst); |
17f3a8b5 JW |
960 | if (dst) { |
961 | if (proto == htons(ETH_P_IPV6)) | |
962 | dst = dst_check(dst, rt6_get_cookie(rt)); | |
963 | else | |
964 | dst = dst_check(dst, 0); | |
965 | } | |
966 | ||
980f4568 JW |
967 | return dst; |
968 | } | |
969 | ||
1d38c2e4 JW |
970 | static inline __be32 qeth_next_hop_v4_rcu(struct sk_buff *skb, |
971 | struct dst_entry *dst) | |
972 | { | |
05d6d492 ED |
973 | return (dst) ? rt_nexthop(dst_rtable(dst), ip_hdr(skb)->daddr) : |
974 | ip_hdr(skb)->daddr; | |
1d38c2e4 JW |
975 | } |
976 | ||
977 | static inline struct in6_addr *qeth_next_hop_v6_rcu(struct sk_buff *skb, | |
978 | struct dst_entry *dst) | |
979 | { | |
e8dfd42c | 980 | struct rt6_info *rt = dst_rt6_info(dst); |
1d38c2e4 JW |
981 | |
982 | if (rt && !ipv6_addr_any(&rt->rt6i_gateway)) | |
983 | return &rt->rt6i_gateway; | |
984 | else | |
985 | return &ipv6_hdr(skb)->daddr; | |
986 | } | |
987 | ||
17f3a8b5 | 988 | static inline void qeth_tx_csum(struct sk_buff *skb, u8 *flags, __be16 proto) |
6195b936 JW |
989 | { |
990 | *flags |= QETH_HDR_EXT_CSUM_TRANSP_REQ; | |
17f3a8b5 JW |
991 | if ((proto == htons(ETH_P_IP) && ip_hdr(skb)->protocol == IPPROTO_UDP) || |
992 | (proto == htons(ETH_P_IPV6) && ipv6_hdr(skb)->nexthdr == IPPROTO_UDP)) | |
6195b936 | 993 | *flags |= QETH_HDR_EXT_UDP; |
6195b936 JW |
994 | } |
995 | ||
f90b744e FB |
996 | static inline void qeth_put_buffer_pool_entry(struct qeth_card *card, |
997 | struct qeth_buffer_pool_entry *entry) | |
998 | { | |
999 | list_add_tail(&entry->list, &card->qdio.in_buf_pool.entry_list); | |
1000 | } | |
1001 | ||
1da74b1c FB |
1002 | static inline int qeth_is_diagass_supported(struct qeth_card *card, |
1003 | enum qeth_diags_cmds cmd) | |
1004 | { | |
1005 | return card->info.diagass_support & (__u32)cmd; | |
1006 | } | |
1007 | ||
a8155b00 KM |
1008 | int qeth_send_simple_setassparms_prot(struct qeth_card *card, |
1009 | enum qeth_ipa_funcs ipa_func, | |
1c696c89 | 1010 | u16 cmd_code, u32 *data, |
a8155b00 KM |
1011 | enum qeth_prot_versions prot); |
1012 | /* IPv4 variant */ | |
1013 | static inline int qeth_send_simple_setassparms(struct qeth_card *card, | |
1014 | enum qeth_ipa_funcs ipa_func, | |
1c696c89 | 1015 | u16 cmd_code, u32 *data) |
a8155b00 KM |
1016 | { |
1017 | return qeth_send_simple_setassparms_prot(card, ipa_func, cmd_code, | |
1018 | data, QETH_PROT_IPV4); | |
1019 | } | |
1020 | ||
1021 | static inline int qeth_send_simple_setassparms_v6(struct qeth_card *card, | |
1022 | enum qeth_ipa_funcs ipa_func, | |
1c696c89 | 1023 | u16 cmd_code, u32 *data) |
a8155b00 KM |
1024 | { |
1025 | return qeth_send_simple_setassparms_prot(card, ipa_func, cmd_code, | |
1026 | data, QETH_PROT_IPV6); | |
1027 | } | |
1028 | ||
50144f67 JW |
1029 | extern const struct qeth_discipline qeth_l2_discipline; |
1030 | extern const struct qeth_discipline qeth_l3_discipline; | |
d896ac62 | 1031 | extern const struct ethtool_ops qeth_ethtool_ops; |
0b8da811 | 1032 | extern const struct attribute_group *qeth_dev_groups[]; |
b7169c51 | 1033 | |
4a71df50 | 1034 | const char *qeth_get_cardname_short(struct qeth_card *); |
5d4f7856 | 1035 | int qeth_resize_buffer_pool(struct qeth_card *card, unsigned int count); |
ea12f1b3 JW |
1036 | int qeth_setup_discipline(struct qeth_card *card, enum qeth_discipline_id disc); |
1037 | void qeth_remove_discipline(struct qeth_card *card); | |
4a71df50 FB |
1038 | |
1039 | /* exports for qeth discipline device drivers */ | |
d11ba0c4 | 1040 | extern struct qeth_dbf_info qeth_dbf[QETH_DBF_INFOS]; |
4a71df50 | 1041 | |
d3d1b205 | 1042 | struct net_device *qeth_clone_netdev(struct net_device *orig); |
378ac80d JW |
1043 | void qeth_set_allowed_threads(struct qeth_card *card, unsigned long threads, |
1044 | int clear_start_mask); | |
4a71df50 | 1045 | int qeth_threads_running(struct qeth_card *, unsigned long); |
0b9902c1 JW |
1046 | int qeth_set_offline(struct qeth_card *card, const struct qeth_discipline *disc, |
1047 | bool resetting); | |
f9e50b02 | 1048 | |
4a71df50 FB |
1049 | int qeth_send_ipa_cmd(struct qeth_card *, struct qeth_cmd_buffer *, |
1050 | int (*reply_cb) | |
1051 | (struct qeth_card *, struct qeth_reply *, unsigned long), | |
1052 | void *); | |
a59d121d JW |
1053 | struct qeth_cmd_buffer *qeth_ipa_alloc_cmd(struct qeth_card *card, |
1054 | enum qeth_ipa_cmds cmd_code, | |
1055 | enum qeth_prot_versions prot, | |
1056 | unsigned int data_length); | |
b9150461 JW |
1057 | struct qeth_cmd_buffer *qeth_get_setassparms_cmd(struct qeth_card *card, |
1058 | enum qeth_ipa_funcs ipa_func, | |
1059 | u16 cmd_code, | |
1060 | unsigned int data_length, | |
1061 | enum qeth_prot_versions prot); | |
5cfbe10a JW |
1062 | struct qeth_cmd_buffer *qeth_get_diag_cmd(struct qeth_card *card, |
1063 | enum qeth_diags_cmds sub_cmd, | |
1064 | unsigned int data_length); | |
a59d121d | 1065 | |
7005b754 | 1066 | int qeth_schedule_recovery(struct qeth_card *card); |
d73ef324 | 1067 | int qeth_poll(struct napi_struct *napi, int budget); |
59b757a9 | 1068 | void qeth_setadp_promisc_mode(struct qeth_card *card, bool enable); |
4a71df50 | 1069 | int qeth_setadpparms_change_macaddr(struct qeth_card *); |
0290bd29 | 1070 | void qeth_tx_timeout(struct net_device *, unsigned int txqueue); |
45cbb2e4 SR |
1071 | int qeth_query_switch_attributes(struct qeth_card *card, |
1072 | struct qeth_switch_info *sw_info); | |
d896ac62 | 1073 | int qeth_query_card_info(struct qeth_card *card, |
4139b2b1 | 1074 | struct qeth_link_info *link_info); |
65878fd9 JW |
1075 | int qeth_setadpparms_set_access_ctrl(struct qeth_card *card, |
1076 | enum qeth_ipa_isolation_modes mode); | |
1077 | ||
942d6984 | 1078 | int qeth_do_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); |
18787eee AB |
1079 | int qeth_siocdevprivate(struct net_device *dev, struct ifreq *rq, |
1080 | void __user *data, int cmd); | |
79140e22 | 1081 | __printf(3, 4) |
8e96c51c | 1082 | void qeth_dbf_longtext(debug_info_t *id, int level, char *text, ...); |
0da9581d | 1083 | int qeth_configure_cq(struct qeth_card *, enum qeth_cq); |
1da74b1c | 1084 | int qeth_hw_trap(struct qeth_card *, enum qeth_diags_trap_action); |
8f43fb00 | 1085 | int qeth_setassparms_cb(struct qeth_card *, struct qeth_reply *, unsigned long); |
8f43fb00 | 1086 | int qeth_set_features(struct net_device *, netdev_features_t); |
d025da9e | 1087 | void qeth_enable_hw_features(struct net_device *dev); |
8f43fb00 | 1088 | netdev_features_t qeth_fix_features(struct net_device *, netdev_features_t); |
6d69b1f1 JW |
1089 | netdev_features_t qeth_features_check(struct sk_buff *skb, |
1090 | struct net_device *dev, | |
1091 | netdev_features_t features); | |
b0abc4f5 | 1092 | void qeth_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats); |
5d8ce41c | 1093 | int qeth_set_real_num_tx_queues(struct qeth_card *card, unsigned int count); |
3a18d754 JW |
1094 | u16 qeth_iqd_select_queue(struct net_device *dev, struct sk_buff *skb, |
1095 | u8 cast_type, struct net_device *sb_dev); | |
1b9e410f JW |
1096 | u16 qeth_osa_select_queue(struct net_device *dev, struct sk_buff *skb, |
1097 | struct net_device *sb_dev); | |
e22355ea JW |
1098 | int qeth_open(struct net_device *dev); |
1099 | int qeth_stop(struct net_device *dev); | |
1100 | ||
ec61bd2f | 1101 | int qeth_vm_request_mac(struct qeth_card *card); |
fc69660b | 1102 | int qeth_xmit(struct qeth_card *card, struct sk_buff *skb, |
17f3a8b5 | 1103 | struct qeth_qdio_out_q *queue, __be16 proto, |
b0abc4f5 JW |
1104 | void (*fill_header)(struct qeth_qdio_out_q *queue, |
1105 | struct qeth_hdr *hdr, struct sk_buff *skb, | |
17f3a8b5 | 1106 | __be16 proto, unsigned int data_len)); |
4a71df50 | 1107 | |
4a71df50 | 1108 | #endif /* __QETH_CORE_H__ */ |