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b2441318 | 1 | /* SPDX-License-Identifier: GPL-2.0 */ |
779e6e1c | 2 | /* |
a53c8fab | 3 | * Copyright IBM Corp. 2000, 2009 |
779e6e1c JG |
4 | * Author(s): Utz Bacher <utz.bacher@de.ibm.com> |
5 | * Jan Glauber <jang@linux.vnet.ibm.com> | |
6 | */ | |
1da177e4 LT |
7 | #ifndef _CIO_QDIO_H |
8 | #define _CIO_QDIO_H | |
9 | ||
0b642ede | 10 | #include <asm/page.h> |
9d92a7e1 | 11 | #include <asm/schid.h> |
22f99347 | 12 | #include <asm/debug.h> |
779e6e1c | 13 | #include "chsc.h" |
a8237fc4 | 14 | |
3a601bfe | 15 | #define QDIO_BUSY_BIT_PATIENCE (100 << 12) /* 100 microseconds */ |
be8d97a5 JG |
16 | #define QDIO_BUSY_BIT_RETRY_DELAY 10 /* 10 milliseconds */ |
17 | #define QDIO_BUSY_BIT_RETRIES 1000 /* = 10s retry time */ | |
3a601bfe | 18 | #define QDIO_INPUT_THRESHOLD (500 << 12) /* 500 microseconds */ |
1da177e4 LT |
19 | |
20 | enum qdio_irq_states { | |
21 | QDIO_IRQ_STATE_INACTIVE, | |
22 | QDIO_IRQ_STATE_ESTABLISHED, | |
23 | QDIO_IRQ_STATE_ACTIVE, | |
24 | QDIO_IRQ_STATE_STOPPED, | |
25 | QDIO_IRQ_STATE_CLEANUP, | |
26 | QDIO_IRQ_STATE_ERR, | |
27 | NR_QDIO_IRQ_STATES, | |
28 | }; | |
29 | ||
779e6e1c JG |
30 | /* used as intparm in do_IO */ |
31 | #define QDIO_DOING_ESTABLISH 1 | |
32 | #define QDIO_DOING_ACTIVATE 2 | |
33 | #define QDIO_DOING_CLEANUP 3 | |
34 | ||
35 | #define SLSB_STATE_NOT_INIT 0x0 | |
36 | #define SLSB_STATE_EMPTY 0x1 | |
37 | #define SLSB_STATE_PRIMED 0x2 | |
104ea556 | 38 | #define SLSB_STATE_PENDING 0x3 |
779e6e1c JG |
39 | #define SLSB_STATE_HALTED 0xe |
40 | #define SLSB_STATE_ERROR 0xf | |
41 | #define SLSB_TYPE_INPUT 0x0 | |
42 | #define SLSB_TYPE_OUTPUT 0x20 | |
43 | #define SLSB_OWNER_PROG 0x80 | |
44 | #define SLSB_OWNER_CU 0x40 | |
45 | ||
46 | #define SLSB_P_INPUT_NOT_INIT \ | |
47 | (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_NOT_INIT) /* 0x80 */ | |
48 | #define SLSB_P_INPUT_ACK \ | |
49 | (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY) /* 0x81 */ | |
50 | #define SLSB_CU_INPUT_EMPTY \ | |
51 | (SLSB_OWNER_CU | SLSB_TYPE_INPUT | SLSB_STATE_EMPTY) /* 0x41 */ | |
52 | #define SLSB_P_INPUT_PRIMED \ | |
53 | (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_PRIMED) /* 0x82 */ | |
54 | #define SLSB_P_INPUT_HALTED \ | |
55 | (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_HALTED) /* 0x8e */ | |
56 | #define SLSB_P_INPUT_ERROR \ | |
57 | (SLSB_OWNER_PROG | SLSB_TYPE_INPUT | SLSB_STATE_ERROR) /* 0x8f */ | |
58 | #define SLSB_P_OUTPUT_NOT_INIT \ | |
59 | (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_NOT_INIT) /* 0xa0 */ | |
60 | #define SLSB_P_OUTPUT_EMPTY \ | |
61 | (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_EMPTY) /* 0xa1 */ | |
104ea556 | 62 | #define SLSB_P_OUTPUT_PENDING \ |
63 | (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_PENDING) /* 0xa3 */ | |
779e6e1c JG |
64 | #define SLSB_CU_OUTPUT_PRIMED \ |
65 | (SLSB_OWNER_CU | SLSB_TYPE_OUTPUT | SLSB_STATE_PRIMED) /* 0x62 */ | |
66 | #define SLSB_P_OUTPUT_HALTED \ | |
67 | (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_HALTED) /* 0xae */ | |
68 | #define SLSB_P_OUTPUT_ERROR \ | |
69 | (SLSB_OWNER_PROG | SLSB_TYPE_OUTPUT | SLSB_STATE_ERROR) /* 0xaf */ | |
70 | ||
71 | #define SLSB_ERROR_DURING_LOOKUP 0xff | |
72 | ||
73 | /* additional CIWs returned by extended Sense-ID */ | |
74 | #define CIW_TYPE_EQUEUE 0x3 /* establish QDIO queues */ | |
75 | #define CIW_TYPE_AQUEUE 0x4 /* activate QDIO queues */ | |
1da177e4 | 76 | |
779e6e1c JG |
77 | /* flags for st qdio sch data */ |
78 | #define CHSC_FLAG_QDIO_CAPABILITY 0x80 | |
79 | #define CHSC_FLAG_VALIDITY 0x40 | |
80 | ||
958c0ba4 JG |
81 | /* SIGA flags */ |
82 | #define QDIO_SIGA_WRITE 0x00 | |
83 | #define QDIO_SIGA_READ 0x01 | |
84 | #define QDIO_SIGA_SYNC 0x02 | |
104ea556 | 85 | #define QDIO_SIGA_WRITEQ 0x04 |
958c0ba4 JG |
86 | #define QDIO_SIGA_QEBSM_FLAG 0x80 |
87 | ||
779e6e1c JG |
88 | static inline int do_sqbs(u64 token, unsigned char state, int queue, |
89 | int *start, int *count) | |
90 | { | |
91 | register unsigned long _ccq asm ("0") = *count; | |
92 | register unsigned long _token asm ("1") = token; | |
93 | unsigned long _queuestart = ((unsigned long)queue << 32) | *start; | |
1da177e4 | 94 | |
779e6e1c JG |
95 | asm volatile( |
96 | " .insn rsy,0xeb000000008A,%1,0,0(%2)" | |
97 | : "+d" (_ccq), "+d" (_queuestart) | |
98 | : "d" ((unsigned long)state), "d" (_token) | |
99 | : "memory", "cc"); | |
100 | *count = _ccq & 0xff; | |
101 | *start = _queuestart & 0xff; | |
8129ee16 | 102 | |
779e6e1c | 103 | return (_ccq >> 32) & 0xff; |
8129ee16 FP |
104 | } |
105 | ||
779e6e1c | 106 | static inline int do_eqbs(u64 token, unsigned char *state, int queue, |
50f769df | 107 | int *start, int *count, int ack) |
8129ee16 | 108 | { |
8129ee16 | 109 | register unsigned long _ccq asm ("0") = *count; |
779e6e1c | 110 | register unsigned long _token asm ("1") = token; |
8129ee16 | 111 | unsigned long _queuestart = ((unsigned long)queue << 32) | *start; |
50f769df | 112 | unsigned long _state = (unsigned long)ack << 63; |
8129ee16 | 113 | |
94c12cc7 MS |
114 | asm volatile( |
115 | " .insn rrf,0xB99c0000,%1,%2,0,0" | |
116 | : "+d" (_ccq), "+d" (_queuestart), "+d" (_state) | |
779e6e1c JG |
117 | : "d" (_token) |
118 | : "memory", "cc"); | |
8129ee16 FP |
119 | *count = _ccq & 0xff; |
120 | *start = _queuestart & 0xff; | |
121 | *state = _state & 0xff; | |
122 | ||
123 | return (_ccq >> 32) & 0xff; | |
1da177e4 | 124 | } |
1da177e4 | 125 | |
779e6e1c | 126 | struct qdio_irq; |
1da177e4 | 127 | |
779e6e1c JG |
128 | struct siga_flag { |
129 | u8 input:1; | |
130 | u8 output:1; | |
131 | u8 sync:1; | |
90adac58 JG |
132 | u8 sync_after_ai:1; |
133 | u8 sync_out_after_pci:1; | |
134 | u8:3; | |
779e6e1c | 135 | } __attribute__ ((packed)); |
1da177e4 | 136 | |
6486cda6 JG |
137 | struct qdio_dev_perf_stat { |
138 | unsigned int adapter_int; | |
139 | unsigned int qdio_int; | |
140 | unsigned int pci_request_int; | |
141 | ||
142 | unsigned int tasklet_inbound; | |
143 | unsigned int tasklet_inbound_resched; | |
144 | unsigned int tasklet_inbound_resched2; | |
145 | unsigned int tasklet_outbound; | |
146 | ||
147 | unsigned int siga_read; | |
148 | unsigned int siga_write; | |
149 | unsigned int siga_sync; | |
150 | ||
151 | unsigned int inbound_call; | |
152 | unsigned int inbound_handler; | |
153 | unsigned int stop_polling; | |
154 | unsigned int inbound_queue_full; | |
155 | unsigned int outbound_call; | |
156 | unsigned int outbound_handler; | |
0195843b | 157 | unsigned int outbound_queue_full; |
6486cda6 JG |
158 | unsigned int fast_requeue; |
159 | unsigned int target_full; | |
160 | unsigned int eqbs; | |
161 | unsigned int eqbs_partial; | |
162 | unsigned int sqbs; | |
163 | unsigned int sqbs_partial; | |
d36deae7 | 164 | unsigned int int_discarded; |
432ac5e0 | 165 | } ____cacheline_aligned; |
6486cda6 | 166 | |
d307297f JG |
167 | struct qdio_queue_perf_stat { |
168 | /* | |
169 | * Sorted into order-2 buckets: 1, 2-3, 4-7, ... 64-127, 128. | |
170 | * Since max. 127 SBALs are scanned reuse entry for 128 as queue full | |
171 | * aka 127 SBALs found. | |
172 | */ | |
173 | unsigned int nr_sbals[8]; | |
174 | unsigned int nr_sbal_error; | |
175 | unsigned int nr_sbal_nop; | |
176 | unsigned int nr_sbal_total; | |
177 | }; | |
178 | ||
d36deae7 JG |
179 | enum qdio_queue_irq_states { |
180 | QDIO_QUEUE_IRQS_DISABLED, | |
181 | }; | |
182 | ||
779e6e1c JG |
183 | struct qdio_input_q { |
184 | /* input buffer acknowledgement flag */ | |
185 | int polling; | |
e85dea0e JG |
186 | /* first ACK'ed buffer */ |
187 | int ack_start; | |
50f769df JG |
188 | /* how much sbals are acknowledged with qebsm */ |
189 | int ack_count; | |
779e6e1c JG |
190 | /* last time of noticing incoming data */ |
191 | u64 timestamp; | |
d36deae7 JG |
192 | /* upper-layer polling flag */ |
193 | unsigned long queue_irq_state; | |
194 | /* callback to start upper-layer polling */ | |
195 | void (*queue_start_poll) (struct ccw_device *, int, unsigned long); | |
1da177e4 | 196 | }; |
1da177e4 | 197 | |
779e6e1c | 198 | struct qdio_output_q { |
779e6e1c JG |
199 | /* PCIs are enabled for the queue */ |
200 | int pci_out_enabled; | |
104ea556 | 201 | /* cq: use asynchronous output buffers */ |
202 | int use_cq; | |
203 | /* cq: aobs used for particual SBAL */ | |
204 | struct qaob **aobs; | |
205 | /* cq: sbal state related to asynchronous operation */ | |
206 | struct qdio_outbuf_state *sbal_state; | |
779e6e1c JG |
207 | /* timer to check for more outbound work */ |
208 | struct timer_list timer; | |
3d6c76ff JG |
209 | /* used SBALs before tasklet schedule */ |
210 | int scan_threshold; | |
779e6e1c | 211 | }; |
1da177e4 | 212 | |
d307297f JG |
213 | /* |
214 | * Note on cache alignment: grouped slsb and write mostly data at the beginning | |
215 | * sbal[] is read-only and starts on a new cacheline followed by read mostly. | |
216 | */ | |
1da177e4 | 217 | struct qdio_q { |
779e6e1c | 218 | struct slsb slsb; |
d307297f | 219 | |
779e6e1c JG |
220 | union { |
221 | struct qdio_input_q in; | |
222 | struct qdio_output_q out; | |
223 | } u; | |
1da177e4 | 224 | |
779e6e1c JG |
225 | /* |
226 | * inbound: next buffer the program should check for | |
d307297f | 227 | * outbound: next buffer to check if adapter processed it |
779e6e1c JG |
228 | */ |
229 | int first_to_check; | |
1da177e4 | 230 | |
779e6e1c | 231 | /* first_to_check of the last time */ |
e85dea0e | 232 | int last_move; |
1da177e4 | 233 | |
779e6e1c JG |
234 | /* beginning position for calling the program */ |
235 | int first_to_kick; | |
1da177e4 | 236 | |
779e6e1c JG |
237 | /* number of buffers in use by the adapter */ |
238 | atomic_t nr_buf_used; | |
1da177e4 | 239 | |
779e6e1c | 240 | /* error condition during a data transfer */ |
1da177e4 | 241 | unsigned int qdio_error; |
1da177e4 | 242 | |
a2b86019 JG |
243 | /* last scan of the queue */ |
244 | u64 timestamp; | |
245 | ||
d307297f JG |
246 | struct tasklet_struct tasklet; |
247 | struct qdio_queue_perf_stat q_stats; | |
248 | ||
249 | struct qdio_buffer *sbal[QDIO_MAX_BUFFERS_PER_Q] ____cacheline_aligned; | |
250 | ||
251 | /* queue number */ | |
252 | int nr; | |
253 | ||
254 | /* bitmask of queue number */ | |
255 | int mask; | |
256 | ||
257 | /* input or output queue */ | |
258 | int is_input_q; | |
259 | ||
260 | /* list of thinint input queues */ | |
261 | struct list_head entry; | |
262 | ||
263 | /* upper-layer program handler */ | |
264 | qdio_handler_t (*handler); | |
779e6e1c | 265 | |
d307297f JG |
266 | struct dentry *debugfs_q; |
267 | struct qdio_irq *irq_ptr; | |
268 | struct sl *sl; | |
779e6e1c | 269 | /* |
5382fe11 JG |
270 | * A page is allocated under this pointer and used for slib and sl. |
271 | * slib is 2048 bytes big and sl points to offset PAGE_SIZE / 2. | |
779e6e1c JG |
272 | */ |
273 | struct slib *slib; | |
1da177e4 LT |
274 | } __attribute__ ((aligned(256))); |
275 | ||
276 | struct qdio_irq { | |
779e6e1c JG |
277 | struct qib qib; |
278 | u32 *dsci; /* address of device state change indicator */ | |
279 | struct ccw_device *cdev; | |
3f09bb89 | 280 | struct dentry *debugfs_dev; |
6486cda6 | 281 | struct dentry *debugfs_perf; |
1da177e4 LT |
282 | |
283 | unsigned long int_parm; | |
a8237fc4 | 284 | struct subchannel_id schid; |
779e6e1c | 285 | unsigned long sch_token; /* QEBSM facility */ |
8129ee16 | 286 | |
1da177e4 LT |
287 | enum qdio_irq_states state; |
288 | ||
779e6e1c | 289 | struct siga_flag siga_flag; /* siga sync information from qdioac */ |
1da177e4 | 290 | |
779e6e1c JG |
291 | int nr_input_qs; |
292 | int nr_output_qs; | |
1da177e4 LT |
293 | |
294 | struct ccw1 ccw; | |
1da177e4 LT |
295 | struct ciw equeue; |
296 | struct ciw aqueue; | |
297 | ||
779e6e1c | 298 | struct qdio_ssqd_desc ssqd_desc; |
779e6e1c | 299 | void (*orig_handler) (struct ccw_device *, unsigned long, struct irb *); |
1da177e4 | 300 | |
6486cda6 | 301 | int perf_stat_enabled; |
432ac5e0 | 302 | |
1da177e4 | 303 | struct qdr *qdr; |
779e6e1c JG |
304 | unsigned long chsc_page; |
305 | ||
1da177e4 LT |
306 | struct qdio_q *input_qs[QDIO_MAX_QUEUES_PER_IRQ]; |
307 | struct qdio_q *output_qs[QDIO_MAX_QUEUES_PER_IRQ]; | |
779e6e1c | 308 | |
22f99347 | 309 | debug_info_t *debug_area; |
779e6e1c | 310 | struct mutex setup_mutex; |
432ac5e0 | 311 | struct qdio_dev_perf_stat perf_stat; |
1da177e4 | 312 | }; |
779e6e1c JG |
313 | |
314 | /* helper functions */ | |
315 | #define queue_type(q) q->irq_ptr->qib.qfmt | |
22f99347 | 316 | #define SCH_NO(q) (q->irq_ptr->schid.sch_no) |
779e6e1c JG |
317 | |
318 | #define is_thinint_irq(irq) \ | |
319 | (irq->qib.qfmt == QDIO_IQDIO_QFMT || \ | |
320 | css_general_characteristics.aif_osa) | |
321 | ||
d307297f JG |
322 | #define qperf(__qdev, __attr) ((__qdev)->perf_stat.(__attr)) |
323 | ||
324 | #define qperf_inc(__q, __attr) \ | |
325 | ({ \ | |
326 | struct qdio_irq *qdev = (__q)->irq_ptr; \ | |
327 | if (qdev->perf_stat_enabled) \ | |
328 | (qdev->perf_stat.__attr)++; \ | |
329 | }) | |
330 | ||
331 | static inline void account_sbals_error(struct qdio_q *q, int count) | |
332 | { | |
333 | q->q_stats.nr_sbal_error += count; | |
334 | q->q_stats.nr_sbal_total += count; | |
335 | } | |
6486cda6 | 336 | |
779e6e1c JG |
337 | /* the highest iqdio queue is used for multicast */ |
338 | static inline int multicast_outbound(struct qdio_q *q) | |
339 | { | |
340 | return (q->irq_ptr->nr_output_qs > 1) && | |
341 | (q->nr == q->irq_ptr->nr_output_qs - 1); | |
342 | } | |
343 | ||
779e6e1c JG |
344 | #define pci_out_supported(q) \ |
345 | (q->irq_ptr->qib.ac & QIB_AC_OUTBOUND_PCI_SUPPORTED) | |
346 | #define is_qebsm(q) (q->irq_ptr->sch_token != 0) | |
347 | ||
779e6e1c JG |
348 | #define need_siga_in(q) (q->irq_ptr->siga_flag.input) |
349 | #define need_siga_out(q) (q->irq_ptr->siga_flag.output) | |
90adac58 JG |
350 | #define need_siga_sync(q) (unlikely(q->irq_ptr->siga_flag.sync)) |
351 | #define need_siga_sync_after_ai(q) \ | |
352 | (unlikely(q->irq_ptr->siga_flag.sync_after_ai)) | |
353 | #define need_siga_sync_out_after_pci(q) \ | |
354 | (unlikely(q->irq_ptr->siga_flag.sync_out_after_pci)) | |
779e6e1c | 355 | |
dbb0dd02 JA |
356 | #define for_each_input_queue(irq_ptr, q, i) \ |
357 | for (i = 0; i < irq_ptr->nr_input_qs && \ | |
358 | ({ q = irq_ptr->input_qs[i]; 1; }); i++) | |
359 | #define for_each_output_queue(irq_ptr, q, i) \ | |
360 | for (i = 0; i < irq_ptr->nr_output_qs && \ | |
361 | ({ q = irq_ptr->output_qs[i]; 1; }); i++) | |
779e6e1c JG |
362 | |
363 | #define prev_buf(bufnr) \ | |
364 | ((bufnr + QDIO_MAX_BUFFERS_MASK) & QDIO_MAX_BUFFERS_MASK) | |
365 | #define next_buf(bufnr) \ | |
366 | ((bufnr + 1) & QDIO_MAX_BUFFERS_MASK) | |
367 | #define add_buf(bufnr, inc) \ | |
368 | ((bufnr + inc) & QDIO_MAX_BUFFERS_MASK) | |
50f769df JG |
369 | #define sub_buf(bufnr, dec) \ |
370 | ((bufnr - dec) & QDIO_MAX_BUFFERS_MASK) | |
779e6e1c | 371 | |
d36deae7 JG |
372 | #define queue_irqs_enabled(q) \ |
373 | (test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) == 0) | |
374 | #define queue_irqs_disabled(q) \ | |
375 | (test_bit(QDIO_QUEUE_IRQS_DISABLED, &q->u.in.queue_irq_state) != 0) | |
376 | ||
a2b86019 JG |
377 | extern u64 last_ai_time; |
378 | ||
779e6e1c | 379 | /* prototypes for thin interrupt */ |
779e6e1c JG |
380 | void qdio_setup_thinint(struct qdio_irq *irq_ptr); |
381 | int qdio_establish_thinint(struct qdio_irq *irq_ptr); | |
382 | void qdio_shutdown_thinint(struct qdio_irq *irq_ptr); | |
383 | void tiqdio_add_input_queues(struct qdio_irq *irq_ptr); | |
384 | void tiqdio_remove_input_queues(struct qdio_irq *irq_ptr); | |
385 | void tiqdio_inbound_processing(unsigned long q); | |
386 | int tiqdio_allocate_memory(void); | |
387 | void tiqdio_free_memory(void); | |
388 | int tiqdio_register_thinints(void); | |
389 | void tiqdio_unregister_thinints(void); | |
5f4026f8 JG |
390 | void clear_nonshared_ind(struct qdio_irq *); |
391 | int test_nonshared_ind(struct qdio_irq *); | |
104ea556 | 392 | |
779e6e1c JG |
393 | /* prototypes for setup */ |
394 | void qdio_inbound_processing(unsigned long data); | |
395 | void qdio_outbound_processing(unsigned long data); | |
cb9f780a | 396 | void qdio_outbound_timer(struct timer_list *t); |
779e6e1c JG |
397 | void qdio_int_handler(struct ccw_device *cdev, unsigned long intparm, |
398 | struct irb *irb); | |
399 | int qdio_allocate_qs(struct qdio_irq *irq_ptr, int nr_input_qs, | |
400 | int nr_output_qs); | |
401 | void qdio_setup_ssqd_info(struct qdio_irq *irq_ptr); | |
bbd50e17 JG |
402 | int qdio_setup_get_ssqd(struct qdio_irq *irq_ptr, |
403 | struct subchannel_id *schid, | |
404 | struct qdio_ssqd_desc *data); | |
779e6e1c JG |
405 | int qdio_setup_irq(struct qdio_initialize *init_data); |
406 | void qdio_print_subchannel_info(struct qdio_irq *irq_ptr, | |
407 | struct ccw_device *cdev); | |
408 | void qdio_release_memory(struct qdio_irq *irq_ptr); | |
50f769df JG |
409 | int qdio_setup_create_sysfs(struct ccw_device *cdev); |
410 | void qdio_setup_destroy_sysfs(struct ccw_device *cdev); | |
779e6e1c JG |
411 | int qdio_setup_init(void); |
412 | void qdio_setup_exit(void); | |
104ea556 | 413 | int qdio_enable_async_operation(struct qdio_output_q *q); |
414 | void qdio_disable_async_operation(struct qdio_output_q *q); | |
415 | struct qaob *qdio_allocate_aob(void); | |
779e6e1c | 416 | |
60b5df2f JG |
417 | int debug_get_buf_state(struct qdio_q *q, unsigned int bufnr, |
418 | unsigned char *state); | |
779e6e1c | 419 | #endif /* _CIO_QDIO_H */ |