[linux-2.6-block.git] / drivers / rtc / rtc-zynqmp.c

/*
 * Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
 *
 * Copyright (C) 2015 Xilinx, Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program. If not, see <http://www.gnu.org/licenses/>.
 *
 */

#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>

/* RTC Registers */
#define RTC_SET_TM_WR		0x00
#define RTC_SET_TM_RD		0x04
#define RTC_CALIB_WR		0x08
#define RTC_CALIB_RD		0x0C
#define RTC_CUR_TM		0x10
#define RTC_CUR_TICK		0x14
#define RTC_ALRM		0x18
#define RTC_INT_STS		0x20
#define RTC_INT_MASK		0x24
#define RTC_INT_EN		0x28
#define RTC_INT_DIS		0x2C
#define RTC_CTRL		0x40

#define RTC_FR_EN		BIT(20)
#define RTC_FR_DATSHIFT		16
#define RTC_TICK_MASK		0xFFFF
#define RTC_INT_SEC		BIT(0)
#define RTC_INT_ALRM		BIT(1)
#define RTC_OSC_EN		BIT(24)
#define RTC_BATT_EN		BIT(31)

#define RTC_CALIB_DEF		0x198233
#define RTC_CALIB_MASK		0x1FFFFF
#define RTC_SEC_MAX_VAL		0xFFFFFFFF

struct xlnx_rtc_dev {
	struct rtc_device	*rtc;
	void __iomem		*reg_base;
	int			alarm_irq;
	int			sec_irq;
	int			calibval;
};

static int xlnx_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
	unsigned long new_time;

	new_time = rtc_tm_to_time64(tm);

	if (new_time > RTC_SEC_MAX_VAL)
		return -EINVAL;

	/*
	 * Writing into calibration register will clear the Tick Counter and
	 * force the next second to be signaled exactly in 1 second period
	 */
	xrtcdev->calibval &= RTC_CALIB_MASK;
	writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));

	writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);

	return 0;
}

static int xlnx_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);

	rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm);

	return rtc_valid_tm(tm);
}

static int xlnx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);

	rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
	alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;

	return 0;
}

static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
{
	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);

	if (enabled)
		writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
	else
		writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);

	return 0;
}

static int xlnx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
	unsigned long alarm_time;

	alarm_time = rtc_tm_to_time64(&alrm->time);

	if (alarm_time > RTC_SEC_MAX_VAL)
		return -EINVAL;

	writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));

	xlnx_rtc_alarm_irq_enable(dev, alrm->enabled);

	return 0;
}

static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
{
	u32 rtc_ctrl;

	/* Enable RTC switch to battery when VCC_PSAUX is not available */
	rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
	rtc_ctrl |= RTC_BATT_EN;
	writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);

	/*
	 * Based on crystal freq of 33.330 KHz
	 * set the seconds counter and enable, set fractions counter
	 * to default value suggested as per design spec
	 * to correct RTC delay in frequency over period of time.
	 */
	xrtcdev->calibval &= RTC_CALIB_MASK;
	writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
}

static const struct rtc_class_ops xlnx_rtc_ops = {
	.set_time	  = xlnx_rtc_set_time,
	.read_time	  = xlnx_rtc_read_time,
	.read_alarm	  = xlnx_rtc_read_alarm,
	.set_alarm	  = xlnx_rtc_set_alarm,
	.alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
};

static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
{
	struct xlnx_rtc_dev *xrtcdev = (struct xlnx_rtc_dev *)id;
	unsigned int status;

	status = readl(xrtcdev->reg_base + RTC_INT_STS);
	/* Check if interrupt asserted */
	if (!(status & (RTC_INT_SEC | RTC_INT_ALRM)))
		return IRQ_NONE;

	/* Clear interrupt */
	writel(status, xrtcdev->reg_base + RTC_INT_STS);

	if (status & RTC_INT_SEC)
		rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_UF);
	if (status & RTC_INT_ALRM)
		rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF | RTC_AF);

	return IRQ_HANDLED;
}

static int xlnx_rtc_probe(struct platform_device *pdev)
{
	struct xlnx_rtc_dev *xrtcdev;
	struct resource *res;
	int ret;

	xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
	if (!xrtcdev)
		return -ENOMEM;

	platform_set_drvdata(pdev, xrtcdev);

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);

	xrtcdev->reg_base = devm_ioremap_resource(&pdev->dev, res);
	if (IS_ERR(xrtcdev->reg_base))
		return PTR_ERR(xrtcdev->reg_base);

	xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
	if (xrtcdev->alarm_irq < 0) {
		dev_err(&pdev->dev, "no irq resource\n");
		return xrtcdev->alarm_irq;
	}
	ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
			       xlnx_rtc_interrupt, 0,
			       dev_name(&pdev->dev), xrtcdev);
	if (ret) {
		dev_err(&pdev->dev, "request irq failed\n");
		return ret;
	}

	xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
	if (xrtcdev->sec_irq < 0) {
		dev_err(&pdev->dev, "no irq resource\n");
		return xrtcdev->sec_irq;
	}
	ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
			       xlnx_rtc_interrupt, 0,
			       dev_name(&pdev->dev), xrtcdev);
	if (ret) {
		dev_err(&pdev->dev, "request irq failed\n");
		return ret;
	}

	ret = of_property_read_u32(pdev->dev.of_node, "calibration",
				   &xrtcdev->calibval);
	if (ret)
		xrtcdev->calibval = RTC_CALIB_DEF;

	xlnx_init_rtc(xrtcdev);

	device_init_wakeup(&pdev->dev, 1);

	xrtcdev->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
					 &xlnx_rtc_ops, THIS_MODULE);
	return PTR_ERR_OR_ZERO(xrtcdev->rtc);
}

static int xlnx_rtc_remove(struct platform_device *pdev)
{
	xlnx_rtc_alarm_irq_enable(&pdev->dev, 0);
	device_init_wakeup(&pdev->dev, 0);

	return 0;
}

static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct xlnx_rtc_dev *xrtcdev = platform_get_drvdata(pdev);

	if (device_may_wakeup(&pdev->dev))
		enable_irq_wake(xrtcdev->alarm_irq);
	else
		xlnx_rtc_alarm_irq_enable(dev, 0);

	return 0;
}

static int __maybe_unused xlnx_rtc_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct xlnx_rtc_dev *xrtcdev = platform_get_drvdata(pdev);

	if (device_may_wakeup(&pdev->dev))
		disable_irq_wake(xrtcdev->alarm_irq);
	else
		xlnx_rtc_alarm_irq_enable(dev, 1);

	return 0;
}

static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume);

static const struct of_device_id xlnx_rtc_of_match[] = {
	{.compatible = "xlnx,zynqmp-rtc" },
	{ }
};
MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match);

static struct platform_driver xlnx_rtc_driver = {
	.probe		= xlnx_rtc_probe,
	.remove		= xlnx_rtc_remove,
	.driver		= {
		.name	= KBUILD_MODNAME,
		.pm	= &xlnx_rtc_pm_ops,
		.of_match_table	= xlnx_rtc_of_match,
	},
};

module_platform_driver(xlnx_rtc_driver);

MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
MODULE_AUTHOR("Xilinx Inc.");
MODULE_LICENSE("GPL v2");
Commit	Line	Data
11143c19 SG	1	/*
	2	* Xilinx Zynq Ultrascale+ MPSoC Real Time Clock Driver
	3	*
	4	* Copyright (C) 2015 Xilinx, Inc.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License along with
	16	* this program. If not, see <http://www.gnu.org/licenses/>.
	17	*
	18	*/
	19
	20	#include <linux/delay.h>
	21	#include <linux/init.h>
	22	#include <linux/io.h>
	23	#include <linux/module.h>
	24	#include <linux/of.h>
	25	#include <linux/platform_device.h>
	26	#include <linux/rtc.h>
	27
	28	/* RTC Registers */
	29	#define RTC_SET_TM_WR 0x00
	30	#define RTC_SET_TM_RD 0x04
	31	#define RTC_CALIB_WR 0x08
	32	#define RTC_CALIB_RD 0x0C
	33	#define RTC_CUR_TM 0x10
	34	#define RTC_CUR_TICK 0x14
	35	#define RTC_ALRM 0x18
	36	#define RTC_INT_STS 0x20
	37	#define RTC_INT_MASK 0x24
	38	#define RTC_INT_EN 0x28
	39	#define RTC_INT_DIS 0x2C
	40	#define RTC_CTRL 0x40
	41
	42	#define RTC_FR_EN BIT(20)
	43	#define RTC_FR_DATSHIFT 16
	44	#define RTC_TICK_MASK 0xFFFF
	45	#define RTC_INT_SEC BIT(0)
	46	#define RTC_INT_ALRM BIT(1)
	47	#define RTC_OSC_EN BIT(24)
9092984f	48	#define RTC_BATT_EN BIT(31)
11143c19 SG	49
	50	#define RTC_CALIB_DEF 0x198233
	51	#define RTC_CALIB_MASK 0x1FFFFF
	52	#define RTC_SEC_MAX_VAL 0xFFFFFFFF
	53
	54	struct xlnx_rtc_dev {
	55	struct rtc_device *rtc;
	56	void __iomem *reg_base;
	57	int alarm_irq;
	58	int sec_irq;
58c4ed3b	59	int calibval;
11143c19 SG	60	};
	61
	62	static int xlnx_rtc_set_time(struct device dev, struct rtc_time tm)
	63	{
	64	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
	65	unsigned long new_time;
	66
	67	new_time = rtc_tm_to_time64(tm);
	68
	69	if (new_time > RTC_SEC_MAX_VAL)
	70	return -EINVAL;
	71
58c4ed3b AKV	72	/*
	73	* Writing into calibration register will clear the Tick Counter and
	74	* force the next second to be signaled exactly in 1 second period
	75	*/
	76	xrtcdev->calibval &= RTC_CALIB_MASK;
	77	writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
	78
11143c19 SG	79	writel(new_time, xrtcdev->reg_base + RTC_SET_TM_WR);
	80
	81	return 0;
	82	}
	83
	84	static int xlnx_rtc_read_time(struct device dev, struct rtc_time tm)
	85	{
	86	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
	87
	88	rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_CUR_TM), tm);
	89
	90	return rtc_valid_tm(tm);
	91	}
	92
	93	static int xlnx_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	94	{
	95	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
	96
	97	rtc_time64_to_tm(readl(xrtcdev->reg_base + RTC_ALRM), &alrm->time);
	98	alrm->enabled = readl(xrtcdev->reg_base + RTC_INT_MASK) & RTC_INT_ALRM;
	99
	100	return 0;
	101	}
	102
	103	static int xlnx_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
	104	{
	105	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
	106
	107	if (enabled)
	108	writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_EN);
	109	else
	110	writel(RTC_INT_ALRM, xrtcdev->reg_base + RTC_INT_DIS);
	111
	112	return 0;
	113	}
	114
	115	static int xlnx_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	116	{
	117	struct xlnx_rtc_dev *xrtcdev = dev_get_drvdata(dev);
	118	unsigned long alarm_time;
	119
	120	alarm_time = rtc_tm_to_time64(&alrm->time);
	121
	122	if (alarm_time > RTC_SEC_MAX_VAL)
	123	return -EINVAL;
	124
	125	writel((u32)alarm_time, (xrtcdev->reg_base + RTC_ALRM));
	126
	127	xlnx_rtc_alarm_irq_enable(dev, alrm->enabled);
	128
	129	return 0;
	130	}
	131
58c4ed3b	132	static void xlnx_init_rtc(struct xlnx_rtc_dev *xrtcdev)
11143c19	133	{
9092984f AKV	134	u32 rtc_ctrl;
	135
	136	/* Enable RTC switch to battery when VCC_PSAUX is not available */
	137	rtc_ctrl = readl(xrtcdev->reg_base + RTC_CTRL);
	138	rtc_ctrl \|= RTC_BATT_EN;
	139	writel(rtc_ctrl, xrtcdev->reg_base + RTC_CTRL);
	140
11143c19 SG	141	/*
	142	* Based on crystal freq of 33.330 KHz
	143	* set the seconds counter and enable, set fractions counter
	144	* to default value suggested as per design spec
	145	* to correct RTC delay in frequency over period of time.
	146	*/
58c4ed3b AKV	147	xrtcdev->calibval &= RTC_CALIB_MASK;
58c4ed3b AKV	148	writel(xrtcdev->calibval, (xrtcdev->reg_base + RTC_CALIB_WR));
11143c19 SG	149	}
	150
	151	static const struct rtc_class_ops xlnx_rtc_ops = {
	152	.set_time = xlnx_rtc_set_time,
	153	.read_time = xlnx_rtc_read_time,
	154	.read_alarm = xlnx_rtc_read_alarm,
	155	.set_alarm = xlnx_rtc_set_alarm,
	156	.alarm_irq_enable = xlnx_rtc_alarm_irq_enable,
	157	};
	158
	159	static irqreturn_t xlnx_rtc_interrupt(int irq, void *id)
	160	{
	161	struct xlnx_rtc_dev xrtcdev = (struct xlnx_rtc_dev )id;
	162	unsigned int status;
	163
	164	status = readl(xrtcdev->reg_base + RTC_INT_STS);
	165	/* Check if interrupt asserted */
	166	if (!(status & (RTC_INT_SEC \| RTC_INT_ALRM)))
	167	return IRQ_NONE;
	168
	169	/* Clear interrupt */
	170	writel(status, xrtcdev->reg_base + RTC_INT_STS);
	171
	172	if (status & RTC_INT_SEC)
	173	rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF \| RTC_UF);
	174	if (status & RTC_INT_ALRM)
	175	rtc_update_irq(xrtcdev->rtc, 1, RTC_IRQF \| RTC_AF);
	176
	177	return IRQ_HANDLED;
	178	}
	179
	180	static int xlnx_rtc_probe(struct platform_device *pdev)
	181	{
	182	struct xlnx_rtc_dev *xrtcdev;
	183	struct resource *res;
	184	int ret;
11143c19 SG	185
	186	xrtcdev = devm_kzalloc(&pdev->dev, sizeof(*xrtcdev), GFP_KERNEL);
	187	if (!xrtcdev)
	188	return -ENOMEM;
	189
	190	platform_set_drvdata(pdev, xrtcdev);
	191
	192	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	193
	194	xrtcdev->reg_base = devm_ioremap_resource(&pdev->dev, res);
	195	if (IS_ERR(xrtcdev->reg_base))
	196	return PTR_ERR(xrtcdev->reg_base);
	197
	198	xrtcdev->alarm_irq = platform_get_irq_byname(pdev, "alarm");
	199	if (xrtcdev->alarm_irq < 0) {
	200	dev_err(&pdev->dev, "no irq resource\n");
	201	return xrtcdev->alarm_irq;
	202	}
	203	ret = devm_request_irq(&pdev->dev, xrtcdev->alarm_irq,
	204	xlnx_rtc_interrupt, 0,
	205	dev_name(&pdev->dev), xrtcdev);
	206	if (ret) {
	207	dev_err(&pdev->dev, "request irq failed\n");
	208	return ret;
	209	}
	210
	211	xrtcdev->sec_irq = platform_get_irq_byname(pdev, "sec");
	212	if (xrtcdev->sec_irq < 0) {
	213	dev_err(&pdev->dev, "no irq resource\n");
	214	return xrtcdev->sec_irq;
	215	}
	216	ret = devm_request_irq(&pdev->dev, xrtcdev->sec_irq,
	217	xlnx_rtc_interrupt, 0,
	218	dev_name(&pdev->dev), xrtcdev);
	219	if (ret) {
	220	dev_err(&pdev->dev, "request irq failed\n");
	221	return ret;
	222	}
	223
	224	ret = of_property_read_u32(pdev->dev.of_node, "calibration",
58c4ed3b	225	&xrtcdev->calibval);
11143c19	226	if (ret)
58c4ed3b	227	xrtcdev->calibval = RTC_CALIB_DEF;
11143c19	228
58c4ed3b	229	xlnx_init_rtc(xrtcdev);
11143c19 SG	230
	231	device_init_wakeup(&pdev->dev, 1);
	232
	233	xrtcdev->rtc = devm_rtc_device_register(&pdev->dev, pdev->name,
	234	&xlnx_rtc_ops, THIS_MODULE);
	235	return PTR_ERR_OR_ZERO(xrtcdev->rtc);
	236	}
	237
	238	static int xlnx_rtc_remove(struct platform_device *pdev)
	239	{
	240	xlnx_rtc_alarm_irq_enable(&pdev->dev, 0);
	241	device_init_wakeup(&pdev->dev, 0);
	242
	243	return 0;
	244	}
	245
	246	static int __maybe_unused xlnx_rtc_suspend(struct device *dev)
	247	{
	248	struct platform_device *pdev = to_platform_device(dev);
	249	struct xlnx_rtc_dev *xrtcdev = platform_get_drvdata(pdev);
	250
	251	if (device_may_wakeup(&pdev->dev))
	252	enable_irq_wake(xrtcdev->alarm_irq);
	253	else
	254	xlnx_rtc_alarm_irq_enable(dev, 0);
	255
	256	return 0;
	257	}
	258
	259	static int __maybe_unused xlnx_rtc_resume(struct device *dev)
	260	{
	261	struct platform_device *pdev = to_platform_device(dev);
	262	struct xlnx_rtc_dev *xrtcdev = platform_get_drvdata(pdev);
	263
	264	if (device_may_wakeup(&pdev->dev))
	265	disable_irq_wake(xrtcdev->alarm_irq);
	266	else
	267	xlnx_rtc_alarm_irq_enable(dev, 1);
	268
	269	return 0;
	270	}
	271
	272	static SIMPLE_DEV_PM_OPS(xlnx_rtc_pm_ops, xlnx_rtc_suspend, xlnx_rtc_resume);
	273
	274	static const struct of_device_id xlnx_rtc_of_match[] = {
	275	{.compatible = "xlnx,zynqmp-rtc" },
	276	{ }
	277	};
	278	MODULE_DEVICE_TABLE(of, xlnx_rtc_of_match);
	279
	280	static struct platform_driver xlnx_rtc_driver = {
	281	.probe = xlnx_rtc_probe,
	282	.remove = xlnx_rtc_remove,
	283	.driver = {
	284	.name = KBUILD_MODNAME,
	285	.pm = &xlnx_rtc_pm_ops,
	286	.of_match_table = xlnx_rtc_of_match,
	287	},
	288	};
	289
	290	module_platform_driver(xlnx_rtc_driver);
	291
	292	MODULE_DESCRIPTION("Xilinx Zynq MPSoC RTC driver");
	293	MODULE_AUTHOR("Xilinx Inc.");
294	MODULE_LICENSE("GPL v2");