[linux-block.git] / drivers / rtc / rtc-xgene.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * APM X-Gene SoC Real Time Clock Driver
 *
 * Copyright (c) 2014, Applied Micro Circuits Corporation
 * Author: Rameshwar Prasad Sahu <rsahu@apm.com>
 *         Loc Ho <lho@apm.com>
 */

#include <linux/clk.h>
#include <linux/delay.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/slab.h>

/* RTC CSR Registers */
#define RTC_CCVR		0x00
#define RTC_CMR			0x04
#define RTC_CLR			0x08
#define RTC_CCR			0x0C
#define  RTC_CCR_IE		BIT(0)
#define  RTC_CCR_MASK		BIT(1)
#define  RTC_CCR_EN		BIT(2)
#define  RTC_CCR_WEN		BIT(3)
#define RTC_STAT		0x10
#define  RTC_STAT_BIT		BIT(0)
#define RTC_RSTAT		0x14
#define RTC_EOI			0x18
#define RTC_VER			0x1C

struct xgene_rtc_dev {
	struct rtc_device *rtc;
	void __iomem *csr_base;
	struct clk *clk;
	unsigned int irq_wake;
	unsigned int irq_enabled;
};

static int xgene_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);

	rtc_time64_to_tm(readl(pdata->csr_base + RTC_CCVR), tm);
	return 0;
}

static int xgene_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);

	/*
	 * NOTE: After the following write, the RTC_CCVR is only reflected
	 *       after the update cycle of 1 seconds.
	 */
	writel((u32)rtc_tm_to_time64(tm), pdata->csr_base + RTC_CLR);
	readl(pdata->csr_base + RTC_CLR); /* Force a barrier */

	return 0;
}

static int xgene_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);

	/* If possible, CMR should be read here */
	rtc_time64_to_tm(0, &alrm->time);
	alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE;

	return 0;
}

static int xgene_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
{
	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
	u32 ccr;

	ccr = readl(pdata->csr_base + RTC_CCR);
	if (enabled) {
		ccr &= ~RTC_CCR_MASK;
		ccr |= RTC_CCR_IE;
	} else {
		ccr &= ~RTC_CCR_IE;
		ccr |= RTC_CCR_MASK;
	}
	writel(ccr, pdata->csr_base + RTC_CCR);

	return 0;
}

static int xgene_rtc_alarm_irq_enabled(struct device *dev)
{
	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);

	return readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE ? 1 : 0;
}

static int xgene_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);

	writel((u32)rtc_tm_to_time64(&alrm->time), pdata->csr_base + RTC_CMR);

	xgene_rtc_alarm_irq_enable(dev, alrm->enabled);

	return 0;
}

static const struct rtc_class_ops xgene_rtc_ops = {
	.read_time	= xgene_rtc_read_time,
	.set_time	= xgene_rtc_set_time,
	.read_alarm	= xgene_rtc_read_alarm,
	.set_alarm	= xgene_rtc_set_alarm,
	.alarm_irq_enable = xgene_rtc_alarm_irq_enable,
};

static irqreturn_t xgene_rtc_interrupt(int irq, void *id)
{
	struct xgene_rtc_dev *pdata = id;

	/* Check if interrupt asserted */
	if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT))
		return IRQ_NONE;

	/* Clear interrupt */
	readl(pdata->csr_base + RTC_EOI);

	rtc_update_irq(pdata->rtc, 1, RTC_IRQF | RTC_AF);

	return IRQ_HANDLED;
}

static int xgene_rtc_probe(struct platform_device *pdev)
{
	struct xgene_rtc_dev *pdata;
	int ret;
	int irq;

	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata)
		return -ENOMEM;
	platform_set_drvdata(pdev, pdata);

	pdata->csr_base = devm_platform_ioremap_resource(pdev, 0);
	if (IS_ERR(pdata->csr_base))
		return PTR_ERR(pdata->csr_base);

	pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(pdata->rtc))
		return PTR_ERR(pdata->rtc);

	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;
	ret = devm_request_irq(&pdev->dev, irq, xgene_rtc_interrupt, 0,
			       dev_name(&pdev->dev), pdata);
	if (ret) {
		dev_err(&pdev->dev, "Could not request IRQ\n");
		return ret;
	}

	pdata->clk = devm_clk_get(&pdev->dev, NULL);
	if (IS_ERR(pdata->clk)) {
		dev_err(&pdev->dev, "Couldn't get the clock for RTC\n");
		return -ENODEV;
	}
	ret = clk_prepare_enable(pdata->clk);
	if (ret)
		return ret;

	/* Turn on the clock and the crystal */
	writel(RTC_CCR_EN, pdata->csr_base + RTC_CCR);

	ret = device_init_wakeup(&pdev->dev, 1);
	if (ret) {
		clk_disable_unprepare(pdata->clk);
		return ret;
	}

	pdata->rtc->ops = &xgene_rtc_ops;
	pdata->rtc->range_max = U32_MAX;

	ret = devm_rtc_register_device(pdata->rtc);
	if (ret) {
		clk_disable_unprepare(pdata->clk);
		return ret;
	}

	return 0;
}

static int xgene_rtc_remove(struct platform_device *pdev)
{
	struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);

	xgene_rtc_alarm_irq_enable(&pdev->dev, 0);
	device_init_wakeup(&pdev->dev, 0);
	clk_disable_unprepare(pdata->clk);
	return 0;
}

static int __maybe_unused xgene_rtc_suspend(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
	int irq;

	irq = platform_get_irq(pdev, 0);

	/*
	 * If this RTC alarm will be used for waking the system up,
	 * don't disable it of course. Else we just disable the alarm
	 * and await suspension.
	 */
	if (device_may_wakeup(&pdev->dev)) {
		if (!enable_irq_wake(irq))
			pdata->irq_wake = 1;
	} else {
		pdata->irq_enabled = xgene_rtc_alarm_irq_enabled(dev);
		xgene_rtc_alarm_irq_enable(dev, 0);
		clk_disable_unprepare(pdata->clk);
	}
	return 0;
}

static int __maybe_unused xgene_rtc_resume(struct device *dev)
{
	struct platform_device *pdev = to_platform_device(dev);
	struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
	int irq;
	int rc;

	irq = platform_get_irq(pdev, 0);

	if (device_may_wakeup(&pdev->dev)) {
		if (pdata->irq_wake) {
			disable_irq_wake(irq);
			pdata->irq_wake = 0;
		}
	} else {
		rc = clk_prepare_enable(pdata->clk);
		if (rc) {
			dev_err(dev, "Unable to enable clock error %d\n", rc);
			return rc;
		}
		xgene_rtc_alarm_irq_enable(dev, pdata->irq_enabled);
	}

	return 0;
}

static SIMPLE_DEV_PM_OPS(xgene_rtc_pm_ops, xgene_rtc_suspend, xgene_rtc_resume);

#ifdef CONFIG_OF
static const struct of_device_id xgene_rtc_of_match[] = {
	{.compatible = "apm,xgene-rtc" },
	{ }
};
MODULE_DEVICE_TABLE(of, xgene_rtc_of_match);
#endif

static struct platform_driver xgene_rtc_driver = {
	.probe		= xgene_rtc_probe,
	.remove		= xgene_rtc_remove,
	.driver		= {
		.name	= "xgene-rtc",
		.pm = &xgene_rtc_pm_ops,
		.of_match_table	= of_match_ptr(xgene_rtc_of_match),
	},
};

module_platform_driver(xgene_rtc_driver);

MODULE_DESCRIPTION("APM X-Gene SoC RTC driver");
MODULE_AUTHOR("Rameshwar Sahu <rsahu@apm.com>");
MODULE_LICENSE("GPL");
Commit	Line	Data
3a205b9d	1	// SPDX-License-Identifier: GPL-2.0+
f12d8695 LH	2	/*
	3	* APM X-Gene SoC Real Time Clock Driver
	4	*
	5	* Copyright (c) 2014, Applied Micro Circuits Corporation
	6	* Author: Rameshwar Prasad Sahu <rsahu@apm.com>
	7	* Loc Ho <lho@apm.com>
f12d8695 LH	8	*/
f12d8695 LH	9
db785341 AB	10	#include <linux/clk.h>
db785341 AB	11	#include <linux/delay.h>
f12d8695	12	#include <linux/init.h>
db785341	13	#include <linux/io.h>
f12d8695 LH	14	#include <linux/module.h>
	15	#include <linux/of.h>
	16	#include <linux/platform_device.h>
f12d8695	17	#include <linux/rtc.h>
db785341	18	#include <linux/slab.h>
f12d8695 LH	19
	20	/* RTC CSR Registers */
	21	#define RTC_CCVR 0x00
	22	#define RTC_CMR 0x04
	23	#define RTC_CLR 0x08
	24	#define RTC_CCR 0x0C
	25	#define RTC_CCR_IE BIT(0)
	26	#define RTC_CCR_MASK BIT(1)
	27	#define RTC_CCR_EN BIT(2)
	28	#define RTC_CCR_WEN BIT(3)
	29	#define RTC_STAT 0x10
	30	#define RTC_STAT_BIT BIT(0)
	31	#define RTC_RSTAT 0x14
	32	#define RTC_EOI 0x18
	33	#define RTC_VER 0x1C
	34
	35	struct xgene_rtc_dev {
	36	struct rtc_device *rtc;
f12d8695 LH	37	void __iomem *csr_base;
	38	struct clk *clk;
	39	unsigned int irq_wake;
d0bcd82b	40	unsigned int irq_enabled;
f12d8695 LH	41	};
	42
	43	static int xgene_rtc_read_time(struct device dev, struct rtc_time tm)
	44	{
	45	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
	46
43f327fa	47	rtc_time64_to_tm(readl(pdata->csr_base + RTC_CCVR), tm);
ab62670e	48	return 0;
f12d8695 LH	49	}
f12d8695 LH	50
58f88915	51	static int xgene_rtc_set_time(struct device dev, struct rtc_time tm)
f12d8695 LH	52	{
	53	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
	54
	55	/*
	56	* NOTE: After the following write, the RTC_CCVR is only reflected
	57	* after the update cycle of 1 seconds.
	58	*/
58f88915	59	writel((u32)rtc_tm_to_time64(tm), pdata->csr_base + RTC_CLR);
f12d8695 LH	60	readl(pdata->csr_base + RTC_CLR); /* Force a barrier */
	61
	62	return 0;
	63	}
	64
	65	static int xgene_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	66	{
	67	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
	68
9a842a7e	69	/* If possible, CMR should be read here */
43f327fa	70	rtc_time64_to_tm(0, &alrm->time);
f12d8695 LH	71	alrm->enabled = readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE;
	72
	73	return 0;
	74	}
	75
	76	static int xgene_rtc_alarm_irq_enable(struct device *dev, u32 enabled)
	77	{
	78	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
	79	u32 ccr;
	80
	81	ccr = readl(pdata->csr_base + RTC_CCR);
	82	if (enabled) {
	83	ccr &= ~RTC_CCR_MASK;
	84	ccr \|= RTC_CCR_IE;
	85	} else {
	86	ccr &= ~RTC_CCR_IE;
	87	ccr \|= RTC_CCR_MASK;
	88	}
	89	writel(ccr, pdata->csr_base + RTC_CCR);
	90
	91	return 0;
	92	}
	93
d0bcd82b LH	94	static int xgene_rtc_alarm_irq_enabled(struct device *dev)
	95	{
	96	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
	97
	98	return readl(pdata->csr_base + RTC_CCR) & RTC_CCR_IE ? 1 : 0;
	99	}
	100
f12d8695 LH	101	static int xgene_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	102	{
	103	struct xgene_rtc_dev *pdata = dev_get_drvdata(dev);
f12d8695	104
43f327fa	105	writel((u32)rtc_tm_to_time64(&alrm->time), pdata->csr_base + RTC_CMR);
f12d8695 LH	106
	107	xgene_rtc_alarm_irq_enable(dev, alrm->enabled);
	108
	109	return 0;
	110	}
	111
	112	static const struct rtc_class_ops xgene_rtc_ops = {
	113	.read_time = xgene_rtc_read_time,
58f88915	114	.set_time = xgene_rtc_set_time,
f12d8695 LH	115	.read_alarm = xgene_rtc_read_alarm,
	116	.set_alarm = xgene_rtc_set_alarm,
	117	.alarm_irq_enable = xgene_rtc_alarm_irq_enable,
	118	};
	119
	120	static irqreturn_t xgene_rtc_interrupt(int irq, void *id)
	121	{
db785341	122	struct xgene_rtc_dev *pdata = id;
f12d8695 LH	123
	124	/* Check if interrupt asserted */
	125	if (!(readl(pdata->csr_base + RTC_STAT) & RTC_STAT_BIT))
	126	return IRQ_NONE;
	127
	128	/* Clear interrupt */
	129	readl(pdata->csr_base + RTC_EOI);
	130
	131	rtc_update_irq(pdata->rtc, 1, RTC_IRQF \| RTC_AF);
	132
	133	return IRQ_HANDLED;
	134	}
	135
	136	static int xgene_rtc_probe(struct platform_device *pdev)
	137	{
	138	struct xgene_rtc_dev *pdata;
f12d8695 LH	139	int ret;
	140	int irq;
	141
	142	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
	143	if (!pdata)
	144	return -ENOMEM;
	145	platform_set_drvdata(pdev, pdata);
f12d8695	146
09ef18bc	147	pdata->csr_base = devm_platform_ioremap_resource(pdev, 0);
f12d8695 LH	148	if (IS_ERR(pdata->csr_base))
	149	return PTR_ERR(pdata->csr_base);
	150
a652e00e AB	151	pdata->rtc = devm_rtc_allocate_device(&pdev->dev);
	152	if (IS_ERR(pdata->rtc))
	153	return PTR_ERR(pdata->rtc);
	154
f12d8695	155	irq = platform_get_irq(pdev, 0);
faac9102	156	if (irq < 0)
f12d8695	157	return irq;
f12d8695 LH	158	ret = devm_request_irq(&pdev->dev, irq, xgene_rtc_interrupt, 0,
	159	dev_name(&pdev->dev), pdata);
	160	if (ret) {
	161	dev_err(&pdev->dev, "Could not request IRQ\n");
	162	return ret;
	163	}
	164
	165	pdata->clk = devm_clk_get(&pdev->dev, NULL);
	166	if (IS_ERR(pdata->clk)) {
	167	dev_err(&pdev->dev, "Couldn't get the clock for RTC\n");
	168	return -ENODEV;
	169	}
d0bcd82b LH	170	ret = clk_prepare_enable(pdata->clk);
	171	if (ret)
	172	return ret;
f12d8695 LH	173
	174	/* Turn on the clock and the crystal */
	175	writel(RTC_CCR_EN, pdata->csr_base + RTC_CCR);
	176
d0bcd82b LH	177	ret = device_init_wakeup(&pdev->dev, 1);
	178	if (ret) {
	179	clk_disable_unprepare(pdata->clk);
	180	return ret;
	181	}
f12d8695	182
a652e00e	183	pdata->rtc->ops = &xgene_rtc_ops;
490595ab	184	pdata->rtc->range_max = U32_MAX;
a652e00e	185
fdcfd854	186	ret = devm_rtc_register_device(pdata->rtc);
a652e00e AB	187	if (ret) {
	188	clk_disable_unprepare(pdata->clk);
	189	return ret;
	190	}
f12d8695 LH	191
	192	return 0;
	193	}
	194
	195	static int xgene_rtc_remove(struct platform_device *pdev)
	196	{
	197	struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
	198
	199	xgene_rtc_alarm_irq_enable(&pdev->dev, 0);
	200	device_init_wakeup(&pdev->dev, 0);
	201	clk_disable_unprepare(pdata->clk);
	202	return 0;
	203	}
	204
573e2bf0	205	static int __maybe_unused xgene_rtc_suspend(struct device *dev)
f12d8695 LH	206	{
	207	struct platform_device *pdev = to_platform_device(dev);
	208	struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
	209	int irq;
	210
	211	irq = platform_get_irq(pdev, 0);
d0bcd82b LH	212
	213	/*
	214	* If this RTC alarm will be used for waking the system up,
	215	* don't disable it of course. Else we just disable the alarm
	216	* and await suspension.
	217	*/
f12d8695 LH	218	if (device_may_wakeup(&pdev->dev)) {
	219	if (!enable_irq_wake(irq))
	220	pdata->irq_wake = 1;
	221	} else {
d0bcd82b	222	pdata->irq_enabled = xgene_rtc_alarm_irq_enabled(dev);
f12d8695	223	xgene_rtc_alarm_irq_enable(dev, 0);
d0bcd82b	224	clk_disable_unprepare(pdata->clk);
f12d8695	225	}
f12d8695 LH	226	return 0;
	227	}
	228
573e2bf0	229	static int __maybe_unused xgene_rtc_resume(struct device *dev)
f12d8695 LH	230	{
	231	struct platform_device *pdev = to_platform_device(dev);
	232	struct xgene_rtc_dev *pdata = platform_get_drvdata(pdev);
	233	int irq;
d0bcd82b	234	int rc;
f12d8695 LH	235
f12d8695 LH	236	irq = platform_get_irq(pdev, 0);
d0bcd82b	237
f12d8695 LH	238	if (device_may_wakeup(&pdev->dev)) {
	239	if (pdata->irq_wake) {
	240	disable_irq_wake(irq);
	241	pdata->irq_wake = 0;
	242	}
	243	} else {
d0bcd82b LH	244	rc = clk_prepare_enable(pdata->clk);
	245	if (rc) {
	246	dev_err(dev, "Unable to enable clock error %d\n", rc);
	247	return rc;
	248	}
	249	xgene_rtc_alarm_irq_enable(dev, pdata->irq_enabled);
f12d8695 LH	250	}
	251
	252	return 0;
	253	}
f12d8695 LH	254
	255	static SIMPLE_DEV_PM_OPS(xgene_rtc_pm_ops, xgene_rtc_suspend, xgene_rtc_resume);
	256
	257	#ifdef CONFIG_OF
	258	static const struct of_device_id xgene_rtc_of_match[] = {
	259	{.compatible = "apm,xgene-rtc" },
	260	{ }
	261	};
	262	MODULE_DEVICE_TABLE(of, xgene_rtc_of_match);
	263	#endif
	264
	265	static struct platform_driver xgene_rtc_driver = {
	266	.probe = xgene_rtc_probe,
	267	.remove = xgene_rtc_remove,
	268	.driver = {
f12d8695 LH	269	.name = "xgene-rtc",
	270	.pm = &xgene_rtc_pm_ops,
	271	.of_match_table = of_match_ptr(xgene_rtc_of_match),
	272	},
	273	};
	274
	275	module_platform_driver(xgene_rtc_driver);
	276
	277	MODULE_DESCRIPTION("APM X-Gene SoC RTC driver");
	278	MODULE_AUTHOR("Rameshwar Sahu <rsahu@apm.com>");
	279	MODULE_LICENSE("GPL");