[linux-2.6-block.git] / drivers / rtc / rtc-x1205.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * An i2c driver for the Xicor/Intersil X1205 RTC
 * Copyright 2004 Karen Spearel
 * Copyright 2005 Alessandro Zummo
 *
 * please send all reports to:
 *	Karen Spearel <kas111 at gmail dot com>
 *	Alessandro Zummo <a.zummo@towertech.it>
 *
 * based on a lot of other RTC drivers.
 *
 * Information and datasheet:
 * http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
 */

#include <linux/i2c.h>
#include <linux/bcd.h>
#include <linux/rtc.h>
#include <linux/delay.h>
#include <linux/module.h>
#include <linux/bitops.h>

/* offsets into CCR area */

#define CCR_SEC			0
#define CCR_MIN			1
#define CCR_HOUR		2
#define CCR_MDAY		3
#define CCR_MONTH		4
#define CCR_YEAR		5
#define CCR_WDAY		6
#define CCR_Y2K			7

#define X1205_REG_SR		0x3F	/* status register */
#define X1205_REG_Y2K		0x37
#define X1205_REG_DW		0x36
#define X1205_REG_YR		0x35
#define X1205_REG_MO		0x34
#define X1205_REG_DT		0x33
#define X1205_REG_HR		0x32
#define X1205_REG_MN		0x31
#define X1205_REG_SC		0x30
#define X1205_REG_DTR		0x13
#define X1205_REG_ATR		0x12
#define X1205_REG_INT		0x11
#define X1205_REG_0		0x10
#define X1205_REG_Y2K1		0x0F
#define X1205_REG_DWA1		0x0E
#define X1205_REG_YRA1		0x0D
#define X1205_REG_MOA1		0x0C
#define X1205_REG_DTA1		0x0B
#define X1205_REG_HRA1		0x0A
#define X1205_REG_MNA1		0x09
#define X1205_REG_SCA1		0x08
#define X1205_REG_Y2K0		0x07
#define X1205_REG_DWA0		0x06
#define X1205_REG_YRA0		0x05
#define X1205_REG_MOA0		0x04
#define X1205_REG_DTA0		0x03
#define X1205_REG_HRA0		0x02
#define X1205_REG_MNA0		0x01
#define X1205_REG_SCA0		0x00

#define X1205_CCR_BASE		0x30	/* Base address of CCR */
#define X1205_ALM0_BASE		0x00	/* Base address of ALARM0 */

#define X1205_SR_RTCF		0x01	/* Clock failure */
#define X1205_SR_WEL		0x02	/* Write Enable Latch */
#define X1205_SR_RWEL		0x04	/* Register Write Enable */
#define X1205_SR_AL0		0x20	/* Alarm 0 match */

#define X1205_DTR_DTR0		0x01
#define X1205_DTR_DTR1		0x02
#define X1205_DTR_DTR2		0x04

#define X1205_HR_MIL		0x80	/* Set in ccr.hour for 24 hr mode */

#define X1205_INT_AL0E		0x20	/* Alarm 0 enable */

static struct i2c_driver x1205_driver;

/*
 * In the routines that deal directly with the x1205 hardware, we use
 * rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
 * Epoch is initialized as 2000. Time is set to UTC.
 */
static int x1205_get_datetime(struct i2c_client *client, struct rtc_time *tm,
				unsigned char reg_base)
{
	unsigned char dt_addr[2] = { 0, reg_base };
	unsigned char buf[8];
	int i;

	struct i2c_msg msgs[] = {
		{/* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = dt_addr
		},
		{/* read date */
			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 8,
			.buf = buf
		},
	};

	/* read date registers */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev,
		"%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
		"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
		__func__,
		buf[0], buf[1], buf[2], buf[3],
		buf[4], buf[5], buf[6], buf[7]);

	/* Mask out the enable bits if these are alarm registers */
	if (reg_base < X1205_CCR_BASE)
		for (i = 0; i <= 4; i++)
			buf[i] &= 0x7F;

	tm->tm_sec = bcd2bin(buf[CCR_SEC]);
	tm->tm_min = bcd2bin(buf[CCR_MIN]);
	tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
	tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
	tm->tm_mon = bcd2bin(buf[CCR_MONTH]) - 1; /* mon is 0-11 */
	tm->tm_year = bcd2bin(buf[CCR_YEAR])
			+ (bcd2bin(buf[CCR_Y2K]) * 100) - 1900;
	tm->tm_wday = buf[CCR_WDAY];

	dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
		"mday=%d, mon=%d, year=%d, wday=%d\n",
		__func__,
		tm->tm_sec, tm->tm_min, tm->tm_hour,
		tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);

	return 0;
}

static int x1205_get_status(struct i2c_client *client, unsigned char *sr)
{
	static unsigned char sr_addr[2] = { 0, X1205_REG_SR };

	struct i2c_msg msgs[] = {
		{     /* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = sr_addr
		},
		{    /* read status */
			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 1,
			.buf = sr
		},
	};

	/* read status register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	return 0;
}

static int x1205_set_datetime(struct i2c_client *client, struct rtc_time *tm,
			u8 reg_base, unsigned char alm_enable)
{
	int i, xfer;
	unsigned char rdata[10] = { 0, reg_base };
	unsigned char *buf = rdata + 2;

	static const unsigned char wel[3] = { 0, X1205_REG_SR,
						X1205_SR_WEL };

	static const unsigned char rwel[3] = { 0, X1205_REG_SR,
						X1205_SR_WEL | X1205_SR_RWEL };

	static const unsigned char diswe[3] = { 0, X1205_REG_SR, 0 };

	dev_dbg(&client->dev,
		"%s: sec=%d min=%d hour=%d mday=%d mon=%d year=%d wday=%d\n",
		__func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday,
		tm->tm_mon, tm->tm_year, tm->tm_wday);

	buf[CCR_SEC] = bin2bcd(tm->tm_sec);
	buf[CCR_MIN] = bin2bcd(tm->tm_min);

	/* set hour and 24hr bit */
	buf[CCR_HOUR] = bin2bcd(tm->tm_hour) | X1205_HR_MIL;

	buf[CCR_MDAY] = bin2bcd(tm->tm_mday);

	/* month, 1 - 12 */
	buf[CCR_MONTH] = bin2bcd(tm->tm_mon + 1);

	/* year, since the rtc epoch*/
	buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
	buf[CCR_WDAY] = tm->tm_wday & 0x07;
	buf[CCR_Y2K] = bin2bcd((tm->tm_year + 1900) / 100);

	/* If writing alarm registers, set compare bits on registers 0-4 */
	if (reg_base < X1205_CCR_BASE)
		for (i = 0; i <= 4; i++)
			buf[i] |= 0x80;

	/* this sequence is required to unlock the chip */
	xfer = i2c_master_send(client, wel, 3);
	if (xfer != 3) {
		dev_err(&client->dev, "%s: wel - %d\n", __func__, xfer);
		return -EIO;
	}

	xfer = i2c_master_send(client, rwel, 3);
	if (xfer != 3) {
		dev_err(&client->dev, "%s: rwel - %d\n", __func__, xfer);
		return -EIO;
	}

	xfer = i2c_master_send(client, rdata, sizeof(rdata));
	if (xfer != sizeof(rdata)) {
		dev_err(&client->dev,
			"%s: result=%d addr=%02x, data=%02x\n",
			__func__,
			 xfer, rdata[1], rdata[2]);
		return -EIO;
	}

	/* If we wrote to the nonvolatile region, wait 10msec for write cycle*/
	if (reg_base < X1205_CCR_BASE) {
		unsigned char al0e[3] = { 0, X1205_REG_INT, 0 };

		msleep(10);

		/* ...and set or clear the AL0E bit in the INT register */

		/* Need to set RWEL again as the write has cleared it */
		xfer = i2c_master_send(client, rwel, 3);
		if (xfer != 3) {
			dev_err(&client->dev,
				"%s: aloe rwel - %d\n",
				__func__,
				xfer);
			return -EIO;
		}

		if (alm_enable)
			al0e[2] = X1205_INT_AL0E;

		xfer = i2c_master_send(client, al0e, 3);
		if (xfer != 3) {
			dev_err(&client->dev,
				"%s: al0e - %d\n",
				__func__,
				xfer);
			return -EIO;
		}

		/* and wait 10msec again for this write to complete */
		msleep(10);
	}

	/* disable further writes */
	xfer = i2c_master_send(client, diswe, 3);
	if (xfer != 3) {
		dev_err(&client->dev, "%s: diswe - %d\n", __func__, xfer);
		return -EIO;
	}

	return 0;
}

static int x1205_fix_osc(struct i2c_client *client)
{
	int err;
	struct rtc_time tm;

	memset(&tm, 0, sizeof(tm));

	err = x1205_set_datetime(client, &tm, X1205_CCR_BASE, 0);
	if (err < 0)
		dev_err(&client->dev, "unable to restart the oscillator\n");

	return err;
}

static int x1205_get_dtrim(struct i2c_client *client, int *trim)
{
	unsigned char dtr;
	static unsigned char dtr_addr[2] = { 0, X1205_REG_DTR };

	struct i2c_msg msgs[] = {
		{	/* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = dtr_addr
		},
		{      /* read dtr */
			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 1,
			.buf = &dtr
		},
	};

	/* read dtr register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr);

	*trim = 0;

	if (dtr & X1205_DTR_DTR0)
		*trim += 20;

	if (dtr & X1205_DTR_DTR1)
		*trim += 10;

	if (dtr & X1205_DTR_DTR2)
		*trim = -*trim;

	return 0;
}

static int x1205_get_atrim(struct i2c_client *client, int *trim)
{
	s8 atr;
	static unsigned char atr_addr[2] = { 0, X1205_REG_ATR };

	struct i2c_msg msgs[] = {
		{/* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = atr_addr
		},
		{/* read atr */
			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 1,
			.buf = &atr
		},
	};

	/* read atr register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}

	dev_dbg(&client->dev, "%s: raw atr=%x\n", __func__, atr);

	/* atr is a two's complement value on 6 bits,
	 * perform sign extension. The formula is
	 * Catr = (atr * 0.25pF) + 11.00pF.
	 */
	atr = sign_extend32(atr, 5);

	dev_dbg(&client->dev, "%s: raw atr=%x (%d)\n", __func__, atr, atr);

	*trim = (atr * 250) + 11000;

	dev_dbg(&client->dev, "%s: real=%d\n", __func__, *trim);

	return 0;
}

struct x1205_limit {
	unsigned char reg, mask, min, max;
};

static int x1205_validate_client(struct i2c_client *client)
{
	int i, xfer;

	/* Probe array. We will read the register at the specified
	 * address and check if the given bits are zero.
	 */
	static const unsigned char probe_zero_pattern[] = {
		/* register, mask */
		X1205_REG_SR,	0x18,
		X1205_REG_DTR,	0xF8,
		X1205_REG_ATR,	0xC0,
		X1205_REG_INT,	0x18,
		X1205_REG_0,	0xFF,
	};

	static const struct x1205_limit probe_limits_pattern[] = {
		/* register, mask, min, max */
		{ X1205_REG_Y2K,	0xFF,	19,	20	},
		{ X1205_REG_DW,		0xFF,	0,	6	},
		{ X1205_REG_YR,		0xFF,	0,	99	},
		{ X1205_REG_MO,		0xFF,	0,	12	},
		{ X1205_REG_DT,		0xFF,	0,	31	},
		{ X1205_REG_HR,		0x7F,	0,	23	},
		{ X1205_REG_MN,		0xFF,	0,	59	},
		{ X1205_REG_SC,		0xFF,	0,	59	},
		{ X1205_REG_Y2K1,	0xFF,	19,	20	},
		{ X1205_REG_Y2K0,	0xFF,	19,	20	},
	};

	/* check that registers have bits a 0 where expected */
	for (i = 0; i < ARRAY_SIZE(probe_zero_pattern); i += 2) {
		unsigned char buf;

		unsigned char addr[2] = { 0, probe_zero_pattern[i] };

		struct i2c_msg msgs[2] = {
			{
				.addr = client->addr,
				.len = 2,
				.buf = addr
			},
			{
				.addr = client->addr,
				.flags = I2C_M_RD,
				.len = 1,
				.buf = &buf
			},
		};

		xfer = i2c_transfer(client->adapter, msgs, 2);
		if (xfer != 2) {
			dev_err(&client->dev,
				"%s: could not read register %x\n",
				__func__, probe_zero_pattern[i]);

			return -EIO;
		}

		if ((buf & probe_zero_pattern[i+1]) != 0) {
			dev_err(&client->dev,
				"%s: register=%02x, zero pattern=%d, value=%x\n",
				__func__, probe_zero_pattern[i], i, buf);

			return -ENODEV;
		}
	}

	/* check limits (only registers with bcd values) */
	for (i = 0; i < ARRAY_SIZE(probe_limits_pattern); i++) {
		unsigned char reg, value;

		unsigned char addr[2] = { 0, probe_limits_pattern[i].reg };

		struct i2c_msg msgs[2] = {
			{
				.addr = client->addr,
				.len = 2,
				.buf = addr
			},
			{
				.addr = client->addr,
				.flags = I2C_M_RD,
				.len = 1,
				.buf = &reg
			},
		};

		xfer = i2c_transfer(client->adapter, msgs, 2);
		if (xfer != 2) {
			dev_err(&client->dev,
				"%s: could not read register %x\n",
				__func__, probe_limits_pattern[i].reg);

			return -EIO;
		}

		value = bcd2bin(reg & probe_limits_pattern[i].mask);

		if (value > probe_limits_pattern[i].max ||
			value < probe_limits_pattern[i].min) {
			dev_dbg(&client->dev,
				"%s: register=%x, lim pattern=%d, value=%d\n",
				__func__, probe_limits_pattern[i].reg,
				i, value);

			return -ENODEV;
		}
	}

	return 0;
}

static int x1205_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	int err;
	unsigned char intreg, status;
	static unsigned char int_addr[2] = { 0, X1205_REG_INT };
	struct i2c_client *client = to_i2c_client(dev);
	struct i2c_msg msgs[] = {
		{ /* setup read ptr */
			.addr = client->addr,
			.len = 2,
			.buf = int_addr
		},
		{/* read INT register */

			.addr = client->addr,
			.flags = I2C_M_RD,
			.len = 1,
			.buf = &intreg
		},
	};

	/* read interrupt register and status register */
	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
		dev_err(&client->dev, "%s: read error\n", __func__);
		return -EIO;
	}
	err = x1205_get_status(client, &status);
	if (err == 0) {
		alrm->pending = (status & X1205_SR_AL0) ? 1 : 0;
		alrm->enabled = (intreg & X1205_INT_AL0E) ? 1 : 0;
		err = x1205_get_datetime(client, &alrm->time, X1205_ALM0_BASE);
	}
	return err;
}

static int x1205_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
{
	return x1205_set_datetime(to_i2c_client(dev),
		&alrm->time, X1205_ALM0_BASE, alrm->enabled);
}

static int x1205_rtc_read_time(struct device *dev, struct rtc_time *tm)
{
	return x1205_get_datetime(to_i2c_client(dev),
		tm, X1205_CCR_BASE);
}

static int x1205_rtc_set_time(struct device *dev, struct rtc_time *tm)
{
	return x1205_set_datetime(to_i2c_client(dev),
		tm, X1205_CCR_BASE, 0);
}

static int x1205_rtc_proc(struct device *dev, struct seq_file *seq)
{
	int err, dtrim, atrim;

	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
	if (!err)
		seq_printf(seq, "digital_trim\t: %d ppm\n", dtrim);

	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
	if (!err)
		seq_printf(seq, "analog_trim\t: %d.%02d pF\n",
			atrim / 1000, atrim % 1000);
	return 0;
}

static const struct rtc_class_ops x1205_rtc_ops = {
	.proc		= x1205_rtc_proc,
	.read_time	= x1205_rtc_read_time,
	.set_time	= x1205_rtc_set_time,
	.read_alarm	= x1205_rtc_read_alarm,
	.set_alarm	= x1205_rtc_set_alarm,
};

static ssize_t x1205_sysfs_show_atrim(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	int err, atrim;

	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
	if (err)
		return err;

	return sprintf(buf, "%d.%02d pF\n", atrim / 1000, atrim % 1000);
}
static DEVICE_ATTR(atrim, S_IRUGO, x1205_sysfs_show_atrim, NULL);

static ssize_t x1205_sysfs_show_dtrim(struct device *dev,
				struct device_attribute *attr, char *buf)
{
	int err, dtrim;

	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
	if (err)
		return err;

	return sprintf(buf, "%d ppm\n", dtrim);
}
static DEVICE_ATTR(dtrim, S_IRUGO, x1205_sysfs_show_dtrim, NULL);

static int x1205_sysfs_register(struct device *dev)
{
	int err;

	err = device_create_file(dev, &dev_attr_atrim);
	if (err)
		return err;

	err = device_create_file(dev, &dev_attr_dtrim);
	if (err)
		device_remove_file(dev, &dev_attr_atrim);

	return err;
}

static void x1205_sysfs_unregister(struct device *dev)
{
	device_remove_file(dev, &dev_attr_atrim);
	device_remove_file(dev, &dev_attr_dtrim);
}


static int x1205_probe(struct i2c_client *client,
			const struct i2c_device_id *id)
{
	int err = 0;
	unsigned char sr;
	struct rtc_device *rtc;

	dev_dbg(&client->dev, "%s\n", __func__);

	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
		return -ENODEV;

	if (x1205_validate_client(client) < 0)
		return -ENODEV;

	rtc = devm_rtc_device_register(&client->dev, x1205_driver.driver.name,
					&x1205_rtc_ops, THIS_MODULE);

	if (IS_ERR(rtc))
		return PTR_ERR(rtc);

	i2c_set_clientdata(client, rtc);

	/* Check for power failures and eventually enable the osc */
	err = x1205_get_status(client, &sr);
	if (!err) {
		if (sr & X1205_SR_RTCF) {
			dev_err(&client->dev,
				"power failure detected, "
				"please set the clock\n");
			udelay(50);
			x1205_fix_osc(client);
		}
	} else {
		dev_err(&client->dev, "couldn't read status\n");
	}

	err = x1205_sysfs_register(&client->dev);
	if (err)
		dev_err(&client->dev, "Unable to create sysfs entries\n");

	return 0;
}

static int x1205_remove(struct i2c_client *client)
{
	x1205_sysfs_unregister(&client->dev);
	return 0;
}

static const struct i2c_device_id x1205_id[] = {
	{ "x1205", 0 },
	{ }
};
MODULE_DEVICE_TABLE(i2c, x1205_id);

static const struct of_device_id x1205_dt_ids[] = {
	{ .compatible = "xircom,x1205", },
	{},
};
MODULE_DEVICE_TABLE(of, x1205_dt_ids);

static struct i2c_driver x1205_driver = {
	.driver		= {
		.name	= "rtc-x1205",
		.of_match_table = x1205_dt_ids,
	},
	.probe		= x1205_probe,
	.remove		= x1205_remove,
	.id_table	= x1205_id,
};

module_i2c_driver(x1205_driver);

MODULE_AUTHOR(
	"Karen Spearel <kas111 at gmail dot com>, "
	"Alessandro Zummo <a.zummo@towertech.it>");
MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver");
MODULE_LICENSE("GPL");
Commit	Line	Data
d2912cb1	1	// SPDX-License-Identifier: GPL-2.0-only
1fec7c66 AZ	2	/*
	3	* An i2c driver for the Xicor/Intersil X1205 RTC
	4	* Copyright 2004 Karen Spearel
	5	* Copyright 2005 Alessandro Zummo
	6	*
	7	* please send all reports to:
66e3f10c	8	* Karen Spearel <kas111 at gmail dot com>
1fec7c66 AZ	9	* Alessandro Zummo <a.zummo@towertech.it>
	10	*
	11	* based on a lot of other RTC drivers.
	12	*
890e0375 JD	13	* Information and datasheet:
890e0375 JD	14	* http://www.intersil.com/cda/deviceinfo/0,1477,X1205,00.html
1fec7c66 AZ	15	*/
	16
	17	#include <linux/i2c.h>
	18	#include <linux/bcd.h>
	19	#include <linux/rtc.h>
	20	#include <linux/delay.h>
2113852b	21	#include <linux/module.h>
86e66604	22	#include <linux/bitops.h>
1fec7c66	23
1fec7c66 AZ	24	/* offsets into CCR area */
	25
	26	#define CCR_SEC 0
	27	#define CCR_MIN 1
	28	#define CCR_HOUR 2
	29	#define CCR_MDAY 3
	30	#define CCR_MONTH 4
	31	#define CCR_YEAR 5
	32	#define CCR_WDAY 6
	33	#define CCR_Y2K 7
	34
	35	#define X1205_REG_SR 0x3F /* status register */
	36	#define X1205_REG_Y2K 0x37
	37	#define X1205_REG_DW 0x36
	38	#define X1205_REG_YR 0x35
	39	#define X1205_REG_MO 0x34
	40	#define X1205_REG_DT 0x33
	41	#define X1205_REG_HR 0x32
	42	#define X1205_REG_MN 0x31
	43	#define X1205_REG_SC 0x30
	44	#define X1205_REG_DTR 0x13
	45	#define X1205_REG_ATR 0x12
	46	#define X1205_REG_INT 0x11
	47	#define X1205_REG_0 0x10
	48	#define X1205_REG_Y2K1 0x0F
	49	#define X1205_REG_DWA1 0x0E
	50	#define X1205_REG_YRA1 0x0D
	51	#define X1205_REG_MOA1 0x0C
	52	#define X1205_REG_DTA1 0x0B
	53	#define X1205_REG_HRA1 0x0A
	54	#define X1205_REG_MNA1 0x09
	55	#define X1205_REG_SCA1 0x08
	56	#define X1205_REG_Y2K0 0x07
	57	#define X1205_REG_DWA0 0x06
	58	#define X1205_REG_YRA0 0x05
	59	#define X1205_REG_MOA0 0x04
	60	#define X1205_REG_DTA0 0x03
	61	#define X1205_REG_HRA0 0x02
	62	#define X1205_REG_MNA0 0x01
	63	#define X1205_REG_SCA0 0x00
	64
	65	#define X1205_CCR_BASE 0x30 /* Base address of CCR */
	66	#define X1205_ALM0_BASE 0x00 /* Base address of ALARM0 */
	67
	68	#define X1205_SR_RTCF 0x01 /* Clock failure */
	69	#define X1205_SR_WEL 0x02 /* Write Enable Latch */
	70	#define X1205_SR_RWEL 0x04 /* Register Write Enable */
471d47e3	71	#define X1205_SR_AL0 0x20 /* Alarm 0 match */
1fec7c66 AZ	72
	73	#define X1205_DTR_DTR0 0x01
	74	#define X1205_DTR_DTR1 0x02
	75	#define X1205_DTR_DTR2 0x04
	76
	77	#define X1205_HR_MIL 0x80 /* Set in ccr.hour for 24 hr mode */
	78
471d47e3 MH	79	#define X1205_INT_AL0E 0x20 /* Alarm 0 enable */
471d47e3 MH	80
4edac2b4	81	static struct i2c_driver x1205_driver;
1fec7c66 AZ	82
	83	/*
	84	* In the routines that deal directly with the x1205 hardware, we use
	85	* rtc_time -- month 0-11, hour 0-23, yr = calendar year-epoch
	86	* Epoch is initialized as 2000. Time is set to UTC.
	87	*/
	88	static int x1205_get_datetime(struct i2c_client client, struct rtc_time tm,
	89	unsigned char reg_base)
	90	{
	91	unsigned char dt_addr[2] = { 0, reg_base };
1fec7c66	92	unsigned char buf[8];
471d47e3	93	int i;
1fec7c66 AZ	94
1fec7c66 AZ	95	struct i2c_msg msgs[] = {
c3fe92b7 S	96	{/* setup read ptr */
	97	.addr = client->addr,
	98	.len = 2,
	99	.buf = dt_addr
	100	},
	101	{/* read date */
	102	.addr = client->addr,
	103	.flags = I2C_M_RD,
	104	.len = 8,
	105	.buf = buf
	106	},
1fec7c66 AZ	107	};
	108
	109	/* read date registers */
471d47e3	110	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	111	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	112	return -EIO;
	113	}
	114
	115	dev_dbg(&client->dev,
	116	"%s: raw read data - sec=%02x, min=%02x, hr=%02x, "
	117	"mday=%02x, mon=%02x, year=%02x, wday=%02x, y2k=%02x\n",
2a4e2b87	118	__func__,
1fec7c66 AZ	119	buf[0], buf[1], buf[2], buf[3],
	120	buf[4], buf[5], buf[6], buf[7]);
	121
471d47e3 MH	122	/* Mask out the enable bits if these are alarm registers */
	123	if (reg_base < X1205_CCR_BASE)
	124	for (i = 0; i <= 4; i++)
	125	buf[i] &= 0x7F;
	126
fe20ba70 AB	127	tm->tm_sec = bcd2bin(buf[CCR_SEC]);
	128	tm->tm_min = bcd2bin(buf[CCR_MIN]);
	129	tm->tm_hour = bcd2bin(buf[CCR_HOUR] & 0x3F); /* hr is 0-23 */
	130	tm->tm_mday = bcd2bin(buf[CCR_MDAY]);
	131	tm->tm_mon = bcd2bin(buf[CCR_MONTH]) - 1; /* mon is 0-11 */
	132	tm->tm_year = bcd2bin(buf[CCR_YEAR])
	133	+ (bcd2bin(buf[CCR_Y2K]) * 100) - 1900;
1fec7c66 AZ	134	tm->tm_wday = buf[CCR_WDAY];
	135
	136	dev_dbg(&client->dev, "%s: tm is secs=%d, mins=%d, hours=%d, "
	137	"mday=%d, mon=%d, year=%d, wday=%d\n",
2a4e2b87	138	__func__,
1fec7c66 AZ	139	tm->tm_sec, tm->tm_min, tm->tm_hour,
	140	tm->tm_mday, tm->tm_mon, tm->tm_year, tm->tm_wday);
	141
	142	return 0;
	143	}
	144
	145	static int x1205_get_status(struct i2c_client client, unsigned char sr)
	146	{
	147	static unsigned char sr_addr[2] = { 0, X1205_REG_SR };
	148
	149	struct i2c_msg msgs[] = {
c3fe92b7 S	150	{ /* setup read ptr */
	151	.addr = client->addr,
	152	.len = 2,
	153	.buf = sr_addr
	154	},
	155	{ /* read status */
	156	.addr = client->addr,
	157	.flags = I2C_M_RD,
	158	.len = 1,
	159	.buf = sr
	160	},
1fec7c66 AZ	161	};
	162
	163	/* read status register */
471d47e3	164	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	165	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	166	return -EIO;
	167	}
	168
	169	return 0;
	170	}
	171
	172	static int x1205_set_datetime(struct i2c_client client, struct rtc_time tm,
d973b632	173	u8 reg_base, unsigned char alm_enable)
1fec7c66	174	{
d973b632	175	int i, xfer;
471d47e3	176	unsigned char rdata[10] = { 0, reg_base };
d973b632	177	unsigned char *buf = rdata + 2;
1fec7c66 AZ	178
	179	static const unsigned char wel[3] = { 0, X1205_REG_SR,
	180	X1205_SR_WEL };
	181
	182	static const unsigned char rwel[3] = { 0, X1205_REG_SR,
	183	X1205_SR_WEL \| X1205_SR_RWEL };
	184
	185	static const unsigned char diswe[3] = { 0, X1205_REG_SR, 0 };
	186
	187	dev_dbg(&client->dev,
d973b632 JW	188	"%s: sec=%d min=%d hour=%d mday=%d mon=%d year=%d wday=%d\n",
	189	__func__, tm->tm_sec, tm->tm_min, tm->tm_hour, tm->tm_mday,
	190	tm->tm_mon, tm->tm_year, tm->tm_wday);
1fec7c66	191
fe20ba70 AB	192	buf[CCR_SEC] = bin2bcd(tm->tm_sec);
fe20ba70 AB	193	buf[CCR_MIN] = bin2bcd(tm->tm_min);
1fec7c66 AZ	194
1fec7c66 AZ	195	/* set hour and 24hr bit */
fe20ba70	196	buf[CCR_HOUR] = bin2bcd(tm->tm_hour) \| X1205_HR_MIL;
1fec7c66	197
d973b632	198	buf[CCR_MDAY] = bin2bcd(tm->tm_mday);
1fec7c66	199
d973b632 JW	200	/* month, 1 - 12 */
d973b632 JW	201	buf[CCR_MONTH] = bin2bcd(tm->tm_mon + 1);
1fec7c66	202
d973b632 JW	203	/* year, since the rtc epoch*/
	204	buf[CCR_YEAR] = bin2bcd(tm->tm_year % 100);
	205	buf[CCR_WDAY] = tm->tm_wday & 0x07;
	206	buf[CCR_Y2K] = bin2bcd((tm->tm_year + 1900) / 100);
1fec7c66	207
471d47e3 MH	208	/* If writing alarm registers, set compare bits on registers 0-4 */
	209	if (reg_base < X1205_CCR_BASE)
	210	for (i = 0; i <= 4; i++)
	211	buf[i] \|= 0x80;
	212
1fec7c66	213	/* this sequence is required to unlock the chip */
66e3f10c SK	214	xfer = i2c_master_send(client, wel, 3);
66e3f10c SK	215	if (xfer != 3) {
2a4e2b87	216	dev_err(&client->dev, "%s: wel - %d\n", __func__, xfer);
1fec7c66 AZ	217	return -EIO;
	218	}
	219
66e3f10c SK	220	xfer = i2c_master_send(client, rwel, 3);
66e3f10c SK	221	if (xfer != 3) {
2a4e2b87	222	dev_err(&client->dev, "%s: rwel - %d\n", __func__, xfer);
1fec7c66 AZ	223	return -EIO;
	224	}
	225
d973b632 JW	226	xfer = i2c_master_send(client, rdata, sizeof(rdata));
d973b632 JW	227	if (xfer != sizeof(rdata)) {
471d47e3 MH	228	dev_err(&client->dev,
	229	"%s: result=%d addr=%02x, data=%02x\n",
	230	__func__,
	231	xfer, rdata[1], rdata[2]);
	232	return -EIO;
	233	}
	234
	235	/* If we wrote to the nonvolatile region, wait 10msec for write cycle*/
	236	if (reg_base < X1205_CCR_BASE) {
	237	unsigned char al0e[3] = { 0, X1205_REG_INT, 0 };
	238
	239	msleep(10);
	240
	241	/* ...and set or clear the AL0E bit in the INT register */
1fec7c66	242
471d47e3 MH	243	/* Need to set RWEL again as the write has cleared it */
471d47e3 MH	244	xfer = i2c_master_send(client, rwel, 3);
1fec7c66 AZ	245	if (xfer != 3) {
1fec7c66 AZ	246	dev_err(&client->dev,
471d47e3	247	"%s: aloe rwel - %d\n",
2a4e2b87	248	__func__,
471d47e3 MH	249	xfer);
	250	return -EIO;
	251	}
	252
	253	if (alm_enable)
	254	al0e[2] = X1205_INT_AL0E;
	255
	256	xfer = i2c_master_send(client, al0e, 3);
	257	if (xfer != 3) {
	258	dev_err(&client->dev,
	259	"%s: al0e - %d\n",
	260	__func__,
	261	xfer);
1fec7c66 AZ	262	return -EIO;
1fec7c66 AZ	263	}
471d47e3 MH	264
	265	/* and wait 10msec again for this write to complete */
	266	msleep(10);
	267	}
1fec7c66 AZ	268
1fec7c66 AZ	269	/* disable further writes */
66e3f10c SK	270	xfer = i2c_master_send(client, diswe, 3);
66e3f10c SK	271	if (xfer != 3) {
2a4e2b87	272	dev_err(&client->dev, "%s: diswe - %d\n", __func__, xfer);
1fec7c66 AZ	273	return -EIO;
	274	}
	275
	276	return 0;
	277	}
	278
	279	static int x1205_fix_osc(struct i2c_client *client)
	280	{
	281	int err;
	282	struct rtc_time tm;
	283
cb8799ee	284	memset(&tm, 0, sizeof(tm));
1fec7c66	285
d973b632	286	err = x1205_set_datetime(client, &tm, X1205_CCR_BASE, 0);
471d47e3 MH	287	if (err < 0)
471d47e3 MH	288	dev_err(&client->dev, "unable to restart the oscillator\n");
1fec7c66 AZ	289
	290	return err;
	291	}
	292
	293	static int x1205_get_dtrim(struct i2c_client client, int trim)
	294	{
	295	unsigned char dtr;
	296	static unsigned char dtr_addr[2] = { 0, X1205_REG_DTR };
	297
	298	struct i2c_msg msgs[] = {
c3fe92b7 S	299	{ /* setup read ptr */
	300	.addr = client->addr,
	301	.len = 2,
	302	.buf = dtr_addr
	303	},
	304	{ /* read dtr */
	305	.addr = client->addr,
	306	.flags = I2C_M_RD,
	307	.len = 1,
	308	.buf = &dtr
	309	},
1fec7c66 AZ	310	};
	311
	312	/* read dtr register */
471d47e3	313	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	314	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	315	return -EIO;
	316	}
	317
2a4e2b87	318	dev_dbg(&client->dev, "%s: raw dtr=%x\n", __func__, dtr);
1fec7c66 AZ	319
	320	*trim = 0;
	321
	322	if (dtr & X1205_DTR_DTR0)
	323	*trim += 20;
	324
	325	if (dtr & X1205_DTR_DTR1)
	326	*trim += 10;
	327
	328	if (dtr & X1205_DTR_DTR2)
	329	trim = -trim;
	330
	331	return 0;
	332	}
	333
	334	static int x1205_get_atrim(struct i2c_client client, int trim)
	335	{
	336	s8 atr;
	337	static unsigned char atr_addr[2] = { 0, X1205_REG_ATR };
	338
	339	struct i2c_msg msgs[] = {
c3fe92b7 S	340	{/* setup read ptr */
	341	.addr = client->addr,
	342	.len = 2,
	343	.buf = atr_addr
	344	},
	345	{/* read atr */
	346	.addr = client->addr,
	347	.flags = I2C_M_RD,
	348	.len = 1,
	349	.buf = &atr
	350	},
1fec7c66 AZ	351	};
	352
	353	/* read atr register */
471d47e3	354	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
2a4e2b87	355	dev_err(&client->dev, "%s: read error\n", __func__);
1fec7c66 AZ	356	return -EIO;
	357	}
	358
2a4e2b87	359	dev_dbg(&client->dev, "%s: raw atr=%x\n", __func__, atr);
1fec7c66 AZ	360
	361	/* atr is a two's complement value on 6 bits,
	362	* perform sign extension. The formula is
	363	* Catr = (atr * 0.25pF) + 11.00pF.
	364	*/
86e66604	365	atr = sign_extend32(atr, 5);
1fec7c66	366
2a4e2b87	367	dev_dbg(&client->dev, "%s: raw atr=%x (%d)\n", __func__, atr, atr);
1fec7c66 AZ	368
	369	trim = (atr 250) + 11000;
	370
2a4e2b87	371	dev_dbg(&client->dev, "%s: real=%d\n", __func__, *trim);
1fec7c66 AZ	372
	373	return 0;
	374	}
	375
66e3f10c	376	struct x1205_limit {
1fec7c66 AZ	377	unsigned char reg, mask, min, max;
	378	};
	379
	380	static int x1205_validate_client(struct i2c_client *client)
	381	{
	382	int i, xfer;
	383
	384	/* Probe array. We will read the register at the specified
	385	* address and check if the given bits are zero.
	386	*/
	387	static const unsigned char probe_zero_pattern[] = {
	388	/* register, mask */
	389	X1205_REG_SR, 0x18,
	390	X1205_REG_DTR, 0xF8,
	391	X1205_REG_ATR, 0xC0,
	392	X1205_REG_INT, 0x18,
	393	X1205_REG_0, 0xFF,
	394	};
	395
	396	static const struct x1205_limit probe_limits_pattern[] = {
	397	/* register, mask, min, max */
	398	{ X1205_REG_Y2K, 0xFF, 19, 20 },
	399	{ X1205_REG_DW, 0xFF, 0, 6 },
	400	{ X1205_REG_YR, 0xFF, 0, 99 },
	401	{ X1205_REG_MO, 0xFF, 0, 12 },
	402	{ X1205_REG_DT, 0xFF, 0, 31 },
	403	{ X1205_REG_HR, 0x7F, 0, 23 },
	404	{ X1205_REG_MN, 0xFF, 0, 59 },
	405	{ X1205_REG_SC, 0xFF, 0, 59 },
	406	{ X1205_REG_Y2K1, 0xFF, 19, 20 },
	407	{ X1205_REG_Y2K0, 0xFF, 19, 20 },
	408	};
	409
	410	/* check that registers have bits a 0 where expected */
	411	for (i = 0; i < ARRAY_SIZE(probe_zero_pattern); i += 2) {
	412	unsigned char buf;
	413
	414	unsigned char addr[2] = { 0, probe_zero_pattern[i] };
	415
	416	struct i2c_msg msgs[2] = {
c3fe92b7 S	417	{
	418	.addr = client->addr,
	419	.len = 2,
	420	.buf = addr
	421	},
	422	{
	423	.addr = client->addr,
	424	.flags = I2C_M_RD,
	425	.len = 1,
	426	.buf = &buf
	427	},
1fec7c66 AZ	428	};
1fec7c66 AZ	429
66e3f10c SK	430	xfer = i2c_transfer(client->adapter, msgs, 2);
66e3f10c SK	431	if (xfer != 2) {
a14e1893	432	dev_err(&client->dev,
1fec7c66	433	"%s: could not read register %x\n",
2a4e2b87	434	__func__, probe_zero_pattern[i]);
1fec7c66 AZ	435
	436	return -EIO;
	437	}
	438
	439	if ((buf & probe_zero_pattern[i+1]) != 0) {
a14e1893	440	dev_err(&client->dev,
1fec7c66	441	"%s: register=%02x, zero pattern=%d, value=%x\n",
2a4e2b87	442	__func__, probe_zero_pattern[i], i, buf);
1fec7c66 AZ	443
	444	return -ENODEV;
	445	}
	446	}
	447
	448	/* check limits (only registers with bcd values) */
	449	for (i = 0; i < ARRAY_SIZE(probe_limits_pattern); i++) {
	450	unsigned char reg, value;
	451
	452	unsigned char addr[2] = { 0, probe_limits_pattern[i].reg };
	453
	454	struct i2c_msg msgs[2] = {
c3fe92b7 S	455	{
	456	.addr = client->addr,
	457	.len = 2,
	458	.buf = addr
	459	},
	460	{
	461	.addr = client->addr,
	462	.flags = I2C_M_RD,
	463	.len = 1,
	464	.buf = &reg
	465	},
1fec7c66 AZ	466	};
1fec7c66 AZ	467
66e3f10c SK	468	xfer = i2c_transfer(client->adapter, msgs, 2);
66e3f10c SK	469	if (xfer != 2) {
a14e1893	470	dev_err(&client->dev,
1fec7c66	471	"%s: could not read register %x\n",
2a4e2b87	472	__func__, probe_limits_pattern[i].reg);
1fec7c66 AZ	473
	474	return -EIO;
	475	}
	476
fe20ba70	477	value = bcd2bin(reg & probe_limits_pattern[i].mask);
1fec7c66 AZ	478
	479	if (value > probe_limits_pattern[i].max \|\|
	480	value < probe_limits_pattern[i].min) {
a14e1893	481	dev_dbg(&client->dev,
1fec7c66	482	"%s: register=%x, lim pattern=%d, value=%d\n",
2a4e2b87	483	__func__, probe_limits_pattern[i].reg,
1fec7c66 AZ	484	i, value);
	485
	486	return -ENODEV;
	487	}
	488	}
	489
	490	return 0;
	491	}
	492
	493	static int x1205_rtc_read_alarm(struct device dev, struct rtc_wkalrm alrm)
	494	{
471d47e3 MH	495	int err;
	496	unsigned char intreg, status;
	497	static unsigned char int_addr[2] = { 0, X1205_REG_INT };
	498	struct i2c_client *client = to_i2c_client(dev);
	499	struct i2c_msg msgs[] = {
c3fe92b7 S	500	{ /* setup read ptr */
	501	.addr = client->addr,
	502	.len = 2,
	503	.buf = int_addr
	504	},
	505	{/* read INT register */
	506
	507	.addr = client->addr,
	508	.flags = I2C_M_RD,
	509	.len = 1,
	510	.buf = &intreg
	511	},
471d47e3 MH	512	};
	513
	514	/* read interrupt register and status register */
	515	if (i2c_transfer(client->adapter, &msgs[0], 2) != 2) {
	516	dev_err(&client->dev, "%s: read error\n", __func__);
	517	return -EIO;
	518	}
	519	err = x1205_get_status(client, &status);
	520	if (err == 0) {
	521	alrm->pending = (status & X1205_SR_AL0) ? 1 : 0;
	522	alrm->enabled = (intreg & X1205_INT_AL0E) ? 1 : 0;
	523	err = x1205_get_datetime(client, &alrm->time, X1205_ALM0_BASE);
	524	}
	525	return err;
1fec7c66 AZ	526	}
	527
	528	static int x1205_rtc_set_alarm(struct device dev, struct rtc_wkalrm alrm)
	529	{
	530	return x1205_set_datetime(to_i2c_client(dev),
d973b632	531	&alrm->time, X1205_ALM0_BASE, alrm->enabled);
1fec7c66 AZ	532	}
	533
	534	static int x1205_rtc_read_time(struct device dev, struct rtc_time tm)
	535	{
	536	return x1205_get_datetime(to_i2c_client(dev),
	537	tm, X1205_CCR_BASE);
	538	}
	539
	540	static int x1205_rtc_set_time(struct device dev, struct rtc_time tm)
	541	{
	542	return x1205_set_datetime(to_i2c_client(dev),
d973b632	543	tm, X1205_CCR_BASE, 0);
1fec7c66 AZ	544	}
	545
	546	static int x1205_rtc_proc(struct device dev, struct seq_file seq)
	547	{
	548	int err, dtrim, atrim;
	549
66e3f10c SK	550	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
66e3f10c SK	551	if (!err)
1fec7c66 AZ	552	seq_printf(seq, "digital_trim\t: %d ppm\n", dtrim);
1fec7c66 AZ	553
66e3f10c SK	554	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
66e3f10c SK	555	if (!err)
1fec7c66 AZ	556	seq_printf(seq, "analog_trim\t: %d.%02d pF\n",
	557	atrim / 1000, atrim % 1000);
	558	return 0;
	559	}
	560
ff8371ac	561	static const struct rtc_class_ops x1205_rtc_ops = {
1fec7c66 AZ	562	.proc = x1205_rtc_proc,
	563	.read_time = x1205_rtc_read_time,
	564	.set_time = x1205_rtc_set_time,
	565	.read_alarm = x1205_rtc_read_alarm,
	566	.set_alarm = x1205_rtc_set_alarm,
	567	};
	568
	569	static ssize_t x1205_sysfs_show_atrim(struct device *dev,
	570	struct device_attribute attr, char buf)
	571	{
015aefbb	572	int err, atrim;
1fec7c66	573
015aefbb AZ	574	err = x1205_get_atrim(to_i2c_client(dev), &atrim);
	575	if (err)
	576	return err;
	577
	578	return sprintf(buf, "%d.%02d pF\n", atrim / 1000, atrim % 1000);
1fec7c66 AZ	579	}
	580	static DEVICE_ATTR(atrim, S_IRUGO, x1205_sysfs_show_atrim, NULL);
	581
	582	static ssize_t x1205_sysfs_show_dtrim(struct device *dev,
	583	struct device_attribute attr, char buf)
	584	{
015aefbb	585	int err, dtrim;
1fec7c66	586
015aefbb AZ	587	err = x1205_get_dtrim(to_i2c_client(dev), &dtrim);
	588	if (err)
	589	return err;
1fec7c66	590
015aefbb	591	return sprintf(buf, "%d ppm\n", dtrim);
1fec7c66 AZ	592	}
	593	static DEVICE_ATTR(dtrim, S_IRUGO, x1205_sysfs_show_dtrim, NULL);
	594
4edac2b4 AZ	595	static int x1205_sysfs_register(struct device *dev)
	596	{
	597	int err;
	598
	599	err = device_create_file(dev, &dev_attr_atrim);
	600	if (err)
	601	return err;
	602
	603	err = device_create_file(dev, &dev_attr_dtrim);
	604	if (err)
	605	device_remove_file(dev, &dev_attr_atrim);
	606
	607	return err;
	608	}
	609
	610	static void x1205_sysfs_unregister(struct device *dev)
1fec7c66	611	{
4edac2b4 AZ	612	device_remove_file(dev, &dev_attr_atrim);
4edac2b4 AZ	613	device_remove_file(dev, &dev_attr_dtrim);
1fec7c66 AZ	614	}
1fec7c66 AZ	615
4edac2b4	616
d2653e92 JD	617	static int x1205_probe(struct i2c_client *client,
d2653e92 JD	618	const struct i2c_device_id *id)
1fec7c66 AZ	619	{
	620	int err = 0;
	621	unsigned char sr;
1fec7c66 AZ	622	struct rtc_device *rtc;
1fec7c66 AZ	623
4edac2b4	624	dev_dbg(&client->dev, "%s\n", __func__);
1fec7c66	625
4edac2b4 AZ	626	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
4edac2b4 AZ	627	return -ENODEV;
1fec7c66	628
4edac2b4 AZ	629	if (x1205_validate_client(client) < 0)
4edac2b4 AZ	630	return -ENODEV;
1fec7c66	631
17581718 JH	632	rtc = devm_rtc_device_register(&client->dev, x1205_driver.driver.name,
17581718 JH	633	&x1205_rtc_ops, THIS_MODULE);
1fec7c66	634
4edac2b4 AZ	635	if (IS_ERR(rtc))
4edac2b4 AZ	636	return PTR_ERR(rtc);
1fec7c66 AZ	637
	638	i2c_set_clientdata(client, rtc);
	639
25985edc	640	/* Check for power failures and eventually enable the osc */
66e3f10c SK	641	err = x1205_get_status(client, &sr);
66e3f10c SK	642	if (!err) {
1fec7c66 AZ	643	if (sr & X1205_SR_RTCF) {
	644	dev_err(&client->dev,
	645	"power failure detected, "
	646	"please set the clock\n");
	647	udelay(50);
	648	x1205_fix_osc(client);
	649	}
66e3f10c	650	} else {
1fec7c66	651	dev_err(&client->dev, "couldn't read status\n");
66e3f10c	652	}
1fec7c66	653
4edac2b4 AZ	654	err = x1205_sysfs_register(&client->dev);
4edac2b4 AZ	655	if (err)
4071ea25	656	dev_err(&client->dev, "Unable to create sysfs entries\n");
1fec7c66 AZ	657
1fec7c66 AZ	658	return 0;
1fec7c66 AZ	659	}
1fec7c66 AZ	660
4edac2b4	661	static int x1205_remove(struct i2c_client *client)
1fec7c66	662	{
4edac2b4	663	x1205_sysfs_unregister(&client->dev);
1fec7c66 AZ	664	return 0;
	665	}
	666
3760f736 JD	667	static const struct i2c_device_id x1205_id[] = {
	668	{ "x1205", 0 },
	669	{ }
	670	};
	671	MODULE_DEVICE_TABLE(i2c, x1205_id);
	672
6875404f LW	673	static const struct of_device_id x1205_dt_ids[] = {
	674	{ .compatible = "xircom,x1205", },
	675	{},
	676	};
	677	MODULE_DEVICE_TABLE(of, x1205_dt_ids);
	678
4edac2b4 AZ	679	static struct i2c_driver x1205_driver = {
	680	.driver = {
	681	.name = "rtc-x1205",
6875404f	682	.of_match_table = x1205_dt_ids,
4edac2b4 AZ	683	},
	684	.probe = x1205_probe,
	685	.remove = x1205_remove,
3760f736	686	.id_table = x1205_id,
4edac2b4 AZ	687	};
4edac2b4 AZ	688
0abc9201	689	module_i2c_driver(x1205_driver);
1fec7c66 AZ	690
	691	MODULE_AUTHOR(
	692	"Karen Spearel <kas111 at gmail dot com>, "
	693	"Alessandro Zummo <a.zummo@towertech.it>");
	694	MODULE_DESCRIPTION("Xicor/Intersil X1205 RTC driver");
	695	MODULE_LICENSE("GPL");