[linux-2.6-block.git] / drivers / rtc / rtc-vr41xx.c

/*
 *  Driver for NEC VR4100 series Real Time Clock unit.
 *
 *  Copyright (C) 2003-2008  Yoichi Yuasa <yuasa@linux-mips.org>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2 of the License, or
 *  (at your option) any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; if not, write to the Free Software
 *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */
#include <linux/err.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/uaccess.h>
#include <linux/log2.h>

#include <asm/div64.h>

MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
MODULE_LICENSE("GPL v2");

/* RTC 1 registers */
#define ETIMELREG		0x00
#define ETIMEMREG		0x02
#define ETIMEHREG		0x04
/* RFU */
#define ECMPLREG		0x08
#define ECMPMREG		0x0a
#define ECMPHREG		0x0c
/* RFU */
#define RTCL1LREG		0x10
#define RTCL1HREG		0x12
#define RTCL1CNTLREG		0x14
#define RTCL1CNTHREG		0x16
#define RTCL2LREG		0x18
#define RTCL2HREG		0x1a
#define RTCL2CNTLREG		0x1c
#define RTCL2CNTHREG		0x1e

/* RTC 2 registers */
#define TCLKLREG		0x00
#define TCLKHREG		0x02
#define TCLKCNTLREG		0x04
#define TCLKCNTHREG		0x06
/* RFU */
#define RTCINTREG		0x1e
 #define TCLOCK_INT		0x08
 #define RTCLONG2_INT		0x04
 #define RTCLONG1_INT		0x02
 #define ELAPSEDTIME_INT	0x01

#define RTC_FREQUENCY		32768
#define MAX_PERIODIC_RATE	6553

static void __iomem *rtc1_base;
static void __iomem *rtc2_base;

#define rtc1_read(offset)		readw(rtc1_base + (offset))
#define rtc1_write(offset, value)	writew((value), rtc1_base + (offset))

#define rtc2_read(offset)		readw(rtc2_base + (offset))
#define rtc2_write(offset, value)	writew((value), rtc2_base + (offset))

static unsigned long epoch = 1970;	/* Jan 1 1970 00:00:00 */

static DEFINE_SPINLOCK(rtc_lock);
static char rtc_name[] = "RTC";
static unsigned long periodic_count;
static unsigned int alarm_enabled;
static int aie_irq;
static int pie_irq;

static inline time64_t read_elapsed_second(void)
{

	unsigned long first_low, first_mid, first_high;

	unsigned long second_low, second_mid, second_high;

	do {
		first_low = rtc1_read(ETIMELREG);
		first_mid = rtc1_read(ETIMEMREG);
		first_high = rtc1_read(ETIMEHREG);
		second_low = rtc1_read(ETIMELREG);
		second_mid = rtc1_read(ETIMEMREG);
		second_high = rtc1_read(ETIMEHREG);
	} while (first_low != second_low || first_mid != second_mid ||
		 first_high != second_high);

	return ((u64)first_high << 17) | (first_mid << 1) | (first_low >> 15);
}

static inline void write_elapsed_second(time64_t sec)
{
	spin_lock_irq(&rtc_lock);

	rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
	rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
	rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));

	spin_unlock_irq(&rtc_lock);
}

static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
{
	time64_t epoch_sec, elapsed_sec;

	epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
	elapsed_sec = read_elapsed_second();

	rtc_time64_to_tm(epoch_sec + elapsed_sec, time);

	return 0;
}

static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
{
	time64_t epoch_sec, current_sec;

	epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
	current_sec = rtc_tm_to_time64(time);

	write_elapsed_second(current_sec - epoch_sec);

	return 0;
}

static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
	unsigned long low, mid, high;
	struct rtc_time *time = &wkalrm->time;

	spin_lock_irq(&rtc_lock);

	low = rtc1_read(ECMPLREG);
	mid = rtc1_read(ECMPMREG);
	high = rtc1_read(ECMPHREG);
	wkalrm->enabled = alarm_enabled;

	spin_unlock_irq(&rtc_lock);

	rtc_time64_to_tm((high << 17) | (mid << 1) | (low >> 15), time);

	return 0;
}

static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
	time64_t alarm_sec;

	alarm_sec = rtc_tm_to_time64(&wkalrm->time);

	spin_lock_irq(&rtc_lock);

	if (alarm_enabled)
		disable_irq(aie_irq);

	rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
	rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
	rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));

	if (wkalrm->enabled)
		enable_irq(aie_irq);

	alarm_enabled = wkalrm->enabled;

	spin_unlock_irq(&rtc_lock);

	return 0;
}

static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
	switch (cmd) {
	case RTC_EPOCH_READ:
		return put_user(epoch, (unsigned long __user *)arg);
	case RTC_EPOCH_SET:
		/* Doesn't support before 1900 */
		if (arg < 1900)
			return -EINVAL;
		epoch = arg;
		break;
	default:
		return -ENOIOCTLCMD;
	}

	return 0;
}

static int vr41xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	spin_lock_irq(&rtc_lock);
	if (enabled) {
		if (!alarm_enabled) {
			enable_irq(aie_irq);
			alarm_enabled = 1;
		}
	} else {
		if (alarm_enabled) {
			disable_irq(aie_irq);
			alarm_enabled = 0;
		}
	}
	spin_unlock_irq(&rtc_lock);
	return 0;
}

static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = (struct platform_device *)dev_id;
	struct rtc_device *rtc = platform_get_drvdata(pdev);

	rtc2_write(RTCINTREG, ELAPSEDTIME_INT);

	rtc_update_irq(rtc, 1, RTC_AF);

	return IRQ_HANDLED;
}

static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = (struct platform_device *)dev_id;
	struct rtc_device *rtc = platform_get_drvdata(pdev);
	unsigned long count = periodic_count;

	rtc2_write(RTCINTREG, RTCLONG1_INT);

	rtc1_write(RTCL1LREG, count);
	rtc1_write(RTCL1HREG, count >> 16);

	rtc_update_irq(rtc, 1, RTC_PF);

	return IRQ_HANDLED;
}

static const struct rtc_class_ops vr41xx_rtc_ops = {
	.ioctl			= vr41xx_rtc_ioctl,
	.read_time		= vr41xx_rtc_read_time,
	.set_time		= vr41xx_rtc_set_time,
	.read_alarm		= vr41xx_rtc_read_alarm,
	.set_alarm		= vr41xx_rtc_set_alarm,
	.alarm_irq_enable	= vr41xx_rtc_alarm_irq_enable,
};

static int rtc_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct rtc_device *rtc;
	int retval;

	if (pdev->num_resources != 4)
		return -EBUSY;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -EBUSY;

	rtc1_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
	if (!rtc1_base)
		return -EBUSY;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		retval = -EBUSY;
		goto err_rtc1_iounmap;
	}

	rtc2_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
	if (!rtc2_base) {
		retval = -EBUSY;
		goto err_rtc1_iounmap;
	}

	rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(rtc)) {
		retval = PTR_ERR(rtc);
		goto err_iounmap_all;
	}

	rtc->ops = &vr41xx_rtc_ops;

	/* 48-bit counter at 32.768 kHz */
	rtc->range_max = (1ULL << 33) - 1;
	rtc->max_user_freq = MAX_PERIODIC_RATE;

	spin_lock_irq(&rtc_lock);

	rtc1_write(ECMPLREG, 0);
	rtc1_write(ECMPMREG, 0);
	rtc1_write(ECMPHREG, 0);
	rtc1_write(RTCL1LREG, 0);
	rtc1_write(RTCL1HREG, 0);

	spin_unlock_irq(&rtc_lock);

	aie_irq = platform_get_irq(pdev, 0);
	if (aie_irq <= 0) {
		retval = -EBUSY;
		goto err_iounmap_all;
	}

	retval = devm_request_irq(&pdev->dev, aie_irq, elapsedtime_interrupt, 0,
				"elapsed_time", pdev);
	if (retval < 0)
		goto err_iounmap_all;

	pie_irq = platform_get_irq(pdev, 1);
	if (pie_irq <= 0) {
		retval = -EBUSY;
		goto err_iounmap_all;
	}

	retval = devm_request_irq(&pdev->dev, pie_irq, rtclong1_interrupt, 0,
				"rtclong1", pdev);
	if (retval < 0)
		goto err_iounmap_all;

	platform_set_drvdata(pdev, rtc);

	disable_irq(aie_irq);
	disable_irq(pie_irq);

	dev_info(&pdev->dev, "Real Time Clock of NEC VR4100 series\n");

	retval = rtc_register_device(rtc);
	if (retval)
		goto err_iounmap_all;

	return 0;

err_iounmap_all:
	rtc2_base = NULL;

err_rtc1_iounmap:
	rtc1_base = NULL;

	return retval;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:RTC");

static struct platform_driver rtc_platform_driver = {
	.probe		= rtc_probe,
	.driver		= {
		.name	= rtc_name,
	},
};

module_platform_driver(rtc_platform_driver);
Commit	Line	Data
1da177e4	1	/*
8417eb7a	2	* Driver for NEC VR4100 series Real Time Clock unit.
1da177e4	3	*
ada8e951	4	* Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
1da177e4 LT	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2 of the License, or
	9	* (at your option) any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
bd076509	20	#include <linux/err.h>
1da177e4 LT	21	#include <linux/fs.h>
1da177e4 LT	22	#include <linux/init.h>
4271e7ff	23	#include <linux/io.h>
1da177e4	24	#include <linux/ioport.h>
bd076509	25	#include <linux/interrupt.h>
1da177e4	26	#include <linux/module.h>
8417eb7a	27	#include <linux/platform_device.h>
1da177e4 LT	28	#include <linux/rtc.h>
	29	#include <linux/spinlock.h>
	30	#include <linux/types.h>
4271e7ff	31	#include <linux/uaccess.h>
5d2a5037	32	#include <linux/log2.h>
1da177e4 LT	33
1da177e4 LT	34	#include <asm/div64.h>
1da177e4	35
ada8e951	36	MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
1da177e4	37	MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
4cad4431	38	MODULE_LICENSE("GPL v2");
1da177e4	39
1da177e4 LT	40	/* RTC 1 registers */
	41	#define ETIMELREG 0x00
	42	#define ETIMEMREG 0x02
	43	#define ETIMEHREG 0x04
	44	/* RFU */
	45	#define ECMPLREG 0x08
	46	#define ECMPMREG 0x0a
	47	#define ECMPHREG 0x0c
	48	/* RFU */
	49	#define RTCL1LREG 0x10
	50	#define RTCL1HREG 0x12
	51	#define RTCL1CNTLREG 0x14
	52	#define RTCL1CNTHREG 0x16
	53	#define RTCL2LREG 0x18
	54	#define RTCL2HREG 0x1a
	55	#define RTCL2CNTLREG 0x1c
	56	#define RTCL2CNTHREG 0x1e
	57
	58	/* RTC 2 registers */
	59	#define TCLKLREG 0x00
	60	#define TCLKHREG 0x02
	61	#define TCLKCNTLREG 0x04
	62	#define TCLKCNTHREG 0x06
	63	/* RFU */
	64	#define RTCINTREG 0x1e
	65	#define TCLOCK_INT 0x08
	66	#define RTCLONG2_INT 0x04
	67	#define RTCLONG1_INT 0x02
	68	#define ELAPSEDTIME_INT 0x01
	69
	70	#define RTC_FREQUENCY 32768
	71	#define MAX_PERIODIC_RATE 6553
1da177e4 LT	72
	73	static void __iomem *rtc1_base;
	74	static void __iomem *rtc2_base;
	75
	76	#define rtc1_read(offset) readw(rtc1_base + (offset))
	77	#define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
	78
	79	#define rtc2_read(offset) readw(rtc2_base + (offset))
	80	#define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
	81
	82	static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
	83
34af946a	84	static DEFINE_SPINLOCK(rtc_lock);
1da177e4	85	static char rtc_name[] = "RTC";
1da177e4	86	static unsigned long periodic_count;
9b5ef64a	87	static unsigned int alarm_enabled;
2fac6674 AV	88	static int aie_irq;
2fac6674 AV	89	static int pie_irq;
1da177e4	90
0d1c6553	91	static inline time64_t read_elapsed_second(void)
1da177e4	92	{
8417eb7a	93
1da177e4	94	unsigned long first_low, first_mid, first_high;
8417eb7a	95
1da177e4 LT	96	unsigned long second_low, second_mid, second_high;
	97
	98	do {
	99	first_low = rtc1_read(ETIMELREG);
	100	first_mid = rtc1_read(ETIMEMREG);
	101	first_high = rtc1_read(ETIMEHREG);
	102	second_low = rtc1_read(ETIMELREG);
	103	second_mid = rtc1_read(ETIMEMREG);
	104	second_high = rtc1_read(ETIMEHREG);
	105	} while (first_low != second_low \|\| first_mid != second_mid \|\|
0218bcf6	106	first_high != second_high);
1da177e4	107
0d1c6553	108	return ((u64)first_high << 17) \| (first_mid << 1) \| (first_low >> 15);
1da177e4 LT	109	}
1da177e4 LT	110
0d1c6553	111	static inline void write_elapsed_second(time64_t sec)
1da177e4 LT	112	{
	113	spin_lock_irq(&rtc_lock);
	114
	115	rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
	116	rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
	117	rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
	118
	119	spin_unlock_irq(&rtc_lock);
	120	}
	121
8417eb7a	122	static int vr41xx_rtc_read_time(struct device dev, struct rtc_time time)
1da177e4	123	{
0d1c6553	124	time64_t epoch_sec, elapsed_sec;
1da177e4	125
0d1c6553	126	epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
1da177e4 LT	127	elapsed_sec = read_elapsed_second();
1da177e4 LT	128
0d1c6553	129	rtc_time64_to_tm(epoch_sec + elapsed_sec, time);
8417eb7a YY	130
8417eb7a YY	131	return 0;
1da177e4 LT	132	}
1da177e4 LT	133
8417eb7a	134	static int vr41xx_rtc_set_time(struct device dev, struct rtc_time time)
1da177e4	135	{
0d1c6553	136	time64_t epoch_sec, current_sec;
1da177e4	137
0d1c6553	138	epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
89e27ce4	139	current_sec = rtc_tm_to_time64(time);
1da177e4 LT	140
1da177e4 LT	141	write_elapsed_second(current_sec - epoch_sec);
8417eb7a YY	142
8417eb7a YY	143	return 0;
1da177e4 LT	144	}
1da177e4 LT	145
8417eb7a	146	static int vr41xx_rtc_read_alarm(struct device dev, struct rtc_wkalrm wkalrm)
1da177e4	147	{
8417eb7a YY	148	unsigned long low, mid, high;
8417eb7a YY	149	struct rtc_time *time = &wkalrm->time;
1da177e4	150
8417eb7a	151	spin_lock_irq(&rtc_lock);
1da177e4	152
8417eb7a YY	153	low = rtc1_read(ECMPLREG);
	154	mid = rtc1_read(ECMPMREG);
	155	high = rtc1_read(ECMPHREG);
9b5ef64a	156	wkalrm->enabled = alarm_enabled;
1da177e4	157
8417eb7a	158	spin_unlock_irq(&rtc_lock);
1da177e4	159
89e27ce4	160	rtc_time64_to_tm((high << 17) \| (mid << 1) \| (low >> 15), time);
1da177e4	161
8417eb7a YY	162	return 0;
8417eb7a YY	163	}
1da177e4	164
8417eb7a YY	165	static int vr41xx_rtc_set_alarm(struct device dev, struct rtc_wkalrm wkalrm)
8417eb7a YY	166	{
0d1c6553	167	time64_t alarm_sec;
1da177e4	168
89e27ce4	169	alarm_sec = rtc_tm_to_time64(&wkalrm->time);
1da177e4	170
8417eb7a	171	spin_lock_irq(&rtc_lock);
1da177e4	172
9b5ef64a	173	if (alarm_enabled)
bd076509	174	disable_irq(aie_irq);
9b5ef64a	175
8417eb7a YY	176	rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
	177	rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
	178	rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
1da177e4	179
9b5ef64a	180	if (wkalrm->enabled)
bd076509	181	enable_irq(aie_irq);
9b5ef64a YY	182
	183	alarm_enabled = wkalrm->enabled;
	184
8417eb7a	185	spin_unlock_irq(&rtc_lock);
1da177e4 LT	186
	187	return 0;
	188	}
	189
4cad4431 YY	190	static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
4cad4431 YY	191	{
1da177e4	192	switch (cmd) {
1da177e4 LT	193	case RTC_EPOCH_READ:
	194	return put_user(epoch, (unsigned long __user *)arg);
	195	case RTC_EPOCH_SET:
	196	/* Doesn't support before 1900 */
	197	if (arg < 1900)
	198	return -EINVAL;
1da177e4 LT	199	epoch = arg;
	200	break;
	201	default:
b3969e58	202	return -ENOIOCTLCMD;
1da177e4 LT	203	}
	204
	205	return 0;
	206	}
	207
16380c15 JS	208	static int vr41xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	209	{
	210	spin_lock_irq(&rtc_lock);
	211	if (enabled) {
	212	if (!alarm_enabled) {
	213	enable_irq(aie_irq);
	214	alarm_enabled = 1;
	215	}
	216	} else {
	217	if (alarm_enabled) {
	218	disable_irq(aie_irq);
	219	alarm_enabled = 0;
	220	}
	221	}
	222	spin_unlock_irq(&rtc_lock);
	223	return 0;
	224	}
	225
7d12e780	226	static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
1da177e4	227	{
8417eb7a YY	228	struct platform_device pdev = (struct platform_device )dev_id;
8417eb7a YY	229	struct rtc_device *rtc = platform_get_drvdata(pdev);
1da177e4	230
8417eb7a	231	rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
1da177e4	232
ab6a2d70	233	rtc_update_irq(rtc, 1, RTC_AF);
1da177e4 LT	234
	235	return IRQ_HANDLED;
	236	}
	237
7d12e780	238	static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
1da177e4	239	{
8417eb7a YY	240	struct platform_device pdev = (struct platform_device )dev_id;
8417eb7a YY	241	struct rtc_device *rtc = platform_get_drvdata(pdev);
1da177e4 LT	242	unsigned long count = periodic_count;
1da177e4 LT	243
1da177e4 LT	244	rtc2_write(RTCINTREG, RTCLONG1_INT);
	245
	246	rtc1_write(RTCL1LREG, count);
	247	rtc1_write(RTCL1HREG, count >> 16);
	248
ab6a2d70	249	rtc_update_irq(rtc, 1, RTC_PF);
1da177e4 LT	250
	251	return IRQ_HANDLED;
	252	}
	253
ff8371ac	254	static const struct rtc_class_ops vr41xx_rtc_ops = {
a25f4a95 GU	255	.ioctl = vr41xx_rtc_ioctl,
	256	.read_time = vr41xx_rtc_read_time,
	257	.set_time = vr41xx_rtc_set_time,
	258	.read_alarm = vr41xx_rtc_read_alarm,
	259	.set_alarm = vr41xx_rtc_set_alarm,
	260	.alarm_irq_enable = vr41xx_rtc_alarm_irq_enable,
1da177e4 LT	261	};
1da177e4 LT	262
5a167f45	263	static int rtc_probe(struct platform_device *pdev)
1da177e4	264	{
bd076509	265	struct resource *res;
8417eb7a	266	struct rtc_device *rtc;
1da177e4 LT	267	int retval;
1da177e4 LT	268
bd076509	269	if (pdev->num_resources != 4)
1da177e4 LT	270	return -EBUSY;
1da177e4 LT	271
bd076509 YY	272	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
bd076509 YY	273	if (!res)
1da177e4 LT	274	return -EBUSY;
1da177e4 LT	275
bf6ce1a1	276	rtc1_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
bd076509	277	if (!rtc1_base)
1da177e4	278	return -EBUSY;
bd076509 YY	279
	280	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	281	if (!res) {
	282	retval = -EBUSY;
	283	goto err_rtc1_iounmap;
	284	}
	285
bf6ce1a1	286	rtc2_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
bd076509 YY	287	if (!rtc2_base) {
	288	retval = -EBUSY;
	289	goto err_rtc1_iounmap;
1da177e4 LT	290	}
1da177e4 LT	291
9a99247c	292	rtc = devm_rtc_allocate_device(&pdev->dev);
8417eb7a	293	if (IS_ERR(rtc)) {
bd076509 YY	294	retval = PTR_ERR(rtc);
bd076509 YY	295	goto err_iounmap_all;
1da177e4 LT	296	}
1da177e4 LT	297
9a99247c AB	298	rtc->ops = &vr41xx_rtc_ops;
9a99247c AB	299
30d7891a AB	300	/* 48-bit counter at 32.768 kHz */
30d7891a AB	301	rtc->range_max = (1ULL << 33) - 1;
4cad4431 YY	302	rtc->max_user_freq = MAX_PERIODIC_RATE;
4cad4431 YY	303
1da177e4 LT	304	spin_lock_irq(&rtc_lock);
	305
	306	rtc1_write(ECMPLREG, 0);
	307	rtc1_write(ECMPMREG, 0);
	308	rtc1_write(ECMPHREG, 0);
	309	rtc1_write(RTCL1LREG, 0);
	310	rtc1_write(RTCL1HREG, 0);
	311
1da177e4 LT	312	spin_unlock_irq(&rtc_lock);
1da177e4 LT	313
bd076509	314	aie_irq = platform_get_irq(pdev, 0);
2fac6674	315	if (aie_irq <= 0) {
bd076509	316	retval = -EBUSY;
bf6ce1a1	317	goto err_iounmap_all;
1da177e4 LT	318	}
1da177e4 LT	319
bf6ce1a1 JH	320	retval = devm_request_irq(&pdev->dev, aie_irq, elapsedtime_interrupt, 0,
bf6ce1a1 JH	321	"elapsed_time", pdev);
bd076509	322	if (retval < 0)
bf6ce1a1	323	goto err_iounmap_all;
bd076509 YY	324
bd076509 YY	325	pie_irq = platform_get_irq(pdev, 1);
812f1478 WY	326	if (pie_irq <= 0) {
812f1478 WY	327	retval = -EBUSY;
bf6ce1a1	328	goto err_iounmap_all;
812f1478	329	}
bd076509	330
bf6ce1a1 JH	331	retval = devm_request_irq(&pdev->dev, pie_irq, rtclong1_interrupt, 0,
bf6ce1a1 JH	332	"rtclong1", pdev);
bd076509	333	if (retval < 0)
bf6ce1a1	334	goto err_iounmap_all;
1da177e4	335
8417eb7a YY	336	platform_set_drvdata(pdev, rtc);
8417eb7a YY	337
bd076509 YY	338	disable_irq(aie_irq);
bd076509 YY	339	disable_irq(pie_irq);
1da177e4	340
d75dcd33	341	dev_info(&pdev->dev, "Real Time Clock of NEC VR4100 series\n");
1da177e4	342
9a99247c AB	343	retval = rtc_register_device(rtc);
	344	if (retval)
	345	goto err_iounmap_all;
	346
1da177e4	347	return 0;
bd076509	348
bd076509	349	err_iounmap_all:
bd076509 YY	350	rtc2_base = NULL;
	351
	352	err_rtc1_iounmap:
bd076509 YY	353	rtc1_base = NULL;
	354
	355	return retval;
1da177e4 LT	356	}
1da177e4 LT	357
ad28a07b KS	358	/* work with hotplug and coldplug */
	359	MODULE_ALIAS("platform:RTC");
	360
8417eb7a	361	static struct platform_driver rtc_platform_driver = {
1da177e4	362	.probe = rtc_probe,
3ae5eaec RK	363	.driver = {
	364	.name = rtc_name,
	365	},
1da177e4 LT	366	};
1da177e4 LT	367
0c4eae66	368	module_platform_driver(rtc_platform_driver);