[linux-2.6-block.git] / drivers / rtc / rtc-vr41xx.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  Driver for NEC VR4100 series Real Time Clock unit.
 *
 *  Copyright (C) 2003-2008  Yoichi Yuasa <yuasa@linux-mips.org>
 */
#include <linux/err.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/uaccess.h>
#include <linux/log2.h>

#include <asm/div64.h>

MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
MODULE_LICENSE("GPL v2");

/* RTC 1 registers */
#define ETIMELREG		0x00
#define ETIMEMREG		0x02
#define ETIMEHREG		0x04
/* RFU */
#define ECMPLREG		0x08
#define ECMPMREG		0x0a
#define ECMPHREG		0x0c
/* RFU */
#define RTCL1LREG		0x10
#define RTCL1HREG		0x12
#define RTCL1CNTLREG		0x14
#define RTCL1CNTHREG		0x16
#define RTCL2LREG		0x18
#define RTCL2HREG		0x1a
#define RTCL2CNTLREG		0x1c
#define RTCL2CNTHREG		0x1e

/* RTC 2 registers */
#define TCLKLREG		0x00
#define TCLKHREG		0x02
#define TCLKCNTLREG		0x04
#define TCLKCNTHREG		0x06
/* RFU */
#define RTCINTREG		0x1e
 #define TCLOCK_INT		0x08
 #define RTCLONG2_INT		0x04
 #define RTCLONG1_INT		0x02
 #define ELAPSEDTIME_INT	0x01

#define RTC_FREQUENCY		32768
#define MAX_PERIODIC_RATE	6553

static void __iomem *rtc1_base;
static void __iomem *rtc2_base;

#define rtc1_read(offset)		readw(rtc1_base + (offset))
#define rtc1_write(offset, value)	writew((value), rtc1_base + (offset))

#define rtc2_read(offset)		readw(rtc2_base + (offset))
#define rtc2_write(offset, value)	writew((value), rtc2_base + (offset))

static unsigned long epoch = 1970;	/* Jan 1 1970 00:00:00 */

static DEFINE_SPINLOCK(rtc_lock);
static char rtc_name[] = "RTC";
static unsigned long periodic_count;
static unsigned int alarm_enabled;
static int aie_irq;
static int pie_irq;

static inline time64_t read_elapsed_second(void)
{

	unsigned long first_low, first_mid, first_high;

	unsigned long second_low, second_mid, second_high;

	do {
		first_low = rtc1_read(ETIMELREG);
		first_mid = rtc1_read(ETIMEMREG);
		first_high = rtc1_read(ETIMEHREG);
		second_low = rtc1_read(ETIMELREG);
		second_mid = rtc1_read(ETIMEMREG);
		second_high = rtc1_read(ETIMEHREG);
	} while (first_low != second_low || first_mid != second_mid ||
		 first_high != second_high);

	return ((u64)first_high << 17) | (first_mid << 1) | (first_low >> 15);
}

static inline void write_elapsed_second(time64_t sec)
{
	spin_lock_irq(&rtc_lock);

	rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
	rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
	rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));

	spin_unlock_irq(&rtc_lock);
}

static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
{
	time64_t epoch_sec, elapsed_sec;

	epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
	elapsed_sec = read_elapsed_second();

	rtc_time64_to_tm(epoch_sec + elapsed_sec, time);

	return 0;
}

static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
{
	time64_t epoch_sec, current_sec;

	epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
	current_sec = rtc_tm_to_time64(time);

	write_elapsed_second(current_sec - epoch_sec);

	return 0;
}

static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
	unsigned long low, mid, high;
	struct rtc_time *time = &wkalrm->time;

	spin_lock_irq(&rtc_lock);

	low = rtc1_read(ECMPLREG);
	mid = rtc1_read(ECMPMREG);
	high = rtc1_read(ECMPHREG);
	wkalrm->enabled = alarm_enabled;

	spin_unlock_irq(&rtc_lock);

	rtc_time64_to_tm((high << 17) | (mid << 1) | (low >> 15), time);

	return 0;
}

static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
	time64_t alarm_sec;

	alarm_sec = rtc_tm_to_time64(&wkalrm->time);

	spin_lock_irq(&rtc_lock);

	if (alarm_enabled)
		disable_irq(aie_irq);

	rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
	rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
	rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));

	if (wkalrm->enabled)
		enable_irq(aie_irq);

	alarm_enabled = wkalrm->enabled;

	spin_unlock_irq(&rtc_lock);

	return 0;
}

static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
	switch (cmd) {
	case RTC_EPOCH_READ:
		return put_user(epoch, (unsigned long __user *)arg);
	case RTC_EPOCH_SET:
		/* Doesn't support before 1900 */
		if (arg < 1900)
			return -EINVAL;
		epoch = arg;
		break;
	default:
		return -ENOIOCTLCMD;
	}

	return 0;
}

static int vr41xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	spin_lock_irq(&rtc_lock);
	if (enabled) {
		if (!alarm_enabled) {
			enable_irq(aie_irq);
			alarm_enabled = 1;
		}
	} else {
		if (alarm_enabled) {
			disable_irq(aie_irq);
			alarm_enabled = 0;
		}
	}
	spin_unlock_irq(&rtc_lock);
	return 0;
}

static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = (struct platform_device *)dev_id;
	struct rtc_device *rtc = platform_get_drvdata(pdev);

	rtc2_write(RTCINTREG, ELAPSEDTIME_INT);

	rtc_update_irq(rtc, 1, RTC_AF);

	return IRQ_HANDLED;
}

static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = (struct platform_device *)dev_id;
	struct rtc_device *rtc = platform_get_drvdata(pdev);
	unsigned long count = periodic_count;

	rtc2_write(RTCINTREG, RTCLONG1_INT);

	rtc1_write(RTCL1LREG, count);
	rtc1_write(RTCL1HREG, count >> 16);

	rtc_update_irq(rtc, 1, RTC_PF);

	return IRQ_HANDLED;
}

static const struct rtc_class_ops vr41xx_rtc_ops = {
	.ioctl			= vr41xx_rtc_ioctl,
	.read_time		= vr41xx_rtc_read_time,
	.set_time		= vr41xx_rtc_set_time,
	.read_alarm		= vr41xx_rtc_read_alarm,
	.set_alarm		= vr41xx_rtc_set_alarm,
	.alarm_irq_enable	= vr41xx_rtc_alarm_irq_enable,
};

static int rtc_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct rtc_device *rtc;
	int retval;

	if (pdev->num_resources != 4)
		return -EBUSY;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -EBUSY;

	rtc1_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
	if (!rtc1_base)
		return -EBUSY;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		retval = -EBUSY;
		goto err_rtc1_iounmap;
	}

	rtc2_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
	if (!rtc2_base) {
		retval = -EBUSY;
		goto err_rtc1_iounmap;
	}

	rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(rtc)) {
		retval = PTR_ERR(rtc);
		goto err_iounmap_all;
	}

	rtc->ops = &vr41xx_rtc_ops;

	/* 48-bit counter at 32.768 kHz */
	rtc->range_max = (1ULL << 33) - 1;
	rtc->max_user_freq = MAX_PERIODIC_RATE;

	spin_lock_irq(&rtc_lock);

	rtc1_write(ECMPLREG, 0);
	rtc1_write(ECMPMREG, 0);
	rtc1_write(ECMPHREG, 0);
	rtc1_write(RTCL1LREG, 0);
	rtc1_write(RTCL1HREG, 0);

	spin_unlock_irq(&rtc_lock);

	aie_irq = platform_get_irq(pdev, 0);
	if (aie_irq <= 0) {
		retval = -EBUSY;
		goto err_iounmap_all;
	}

	retval = devm_request_irq(&pdev->dev, aie_irq, elapsedtime_interrupt, 0,
				"elapsed_time", pdev);
	if (retval < 0)
		goto err_iounmap_all;

	pie_irq = platform_get_irq(pdev, 1);
	if (pie_irq <= 0) {
		retval = -EBUSY;
		goto err_iounmap_all;
	}

	retval = devm_request_irq(&pdev->dev, pie_irq, rtclong1_interrupt, 0,
				"rtclong1", pdev);
	if (retval < 0)
		goto err_iounmap_all;

	platform_set_drvdata(pdev, rtc);

	disable_irq(aie_irq);
	disable_irq(pie_irq);

	dev_info(&pdev->dev, "Real Time Clock of NEC VR4100 series\n");

	retval = rtc_register_device(rtc);
	if (retval)
		goto err_iounmap_all;

	return 0;

err_iounmap_all:
	rtc2_base = NULL;

err_rtc1_iounmap:
	rtc1_base = NULL;

	return retval;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:RTC");

static struct platform_driver rtc_platform_driver = {
	.probe		= rtc_probe,
	.driver		= {
		.name	= rtc_name,
	},
};

module_platform_driver(rtc_platform_driver);
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4	2	/*
8417eb7a	3	* Driver for NEC VR4100 series Real Time Clock unit.
1da177e4	4	*
ada8e951	5	* Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
1da177e4	6	*/
bd076509	7	#include <linux/err.h>
1da177e4 LT	8	#include <linux/fs.h>
1da177e4 LT	9	#include <linux/init.h>
4271e7ff	10	#include <linux/io.h>
1da177e4	11	#include <linux/ioport.h>
bd076509	12	#include <linux/interrupt.h>
1da177e4	13	#include <linux/module.h>
8417eb7a	14	#include <linux/platform_device.h>
1da177e4 LT	15	#include <linux/rtc.h>
	16	#include <linux/spinlock.h>
	17	#include <linux/types.h>
4271e7ff	18	#include <linux/uaccess.h>
5d2a5037	19	#include <linux/log2.h>
1da177e4 LT	20
1da177e4 LT	21	#include <asm/div64.h>
1da177e4	22
ada8e951	23	MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
1da177e4	24	MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
4cad4431	25	MODULE_LICENSE("GPL v2");
1da177e4	26
1da177e4 LT	27	/* RTC 1 registers */
	28	#define ETIMELREG 0x00
	29	#define ETIMEMREG 0x02
	30	#define ETIMEHREG 0x04
	31	/* RFU */
	32	#define ECMPLREG 0x08
	33	#define ECMPMREG 0x0a
	34	#define ECMPHREG 0x0c
	35	/* RFU */
	36	#define RTCL1LREG 0x10
	37	#define RTCL1HREG 0x12
	38	#define RTCL1CNTLREG 0x14
	39	#define RTCL1CNTHREG 0x16
	40	#define RTCL2LREG 0x18
	41	#define RTCL2HREG 0x1a
	42	#define RTCL2CNTLREG 0x1c
	43	#define RTCL2CNTHREG 0x1e
	44
	45	/* RTC 2 registers */
	46	#define TCLKLREG 0x00
	47	#define TCLKHREG 0x02
	48	#define TCLKCNTLREG 0x04
	49	#define TCLKCNTHREG 0x06
	50	/* RFU */
	51	#define RTCINTREG 0x1e
	52	#define TCLOCK_INT 0x08
	53	#define RTCLONG2_INT 0x04
	54	#define RTCLONG1_INT 0x02
	55	#define ELAPSEDTIME_INT 0x01
	56
	57	#define RTC_FREQUENCY 32768
	58	#define MAX_PERIODIC_RATE 6553
1da177e4 LT	59
	60	static void __iomem *rtc1_base;
	61	static void __iomem *rtc2_base;
	62
	63	#define rtc1_read(offset) readw(rtc1_base + (offset))
	64	#define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
	65
	66	#define rtc2_read(offset) readw(rtc2_base + (offset))
	67	#define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
	68
	69	static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
	70
34af946a	71	static DEFINE_SPINLOCK(rtc_lock);
1da177e4	72	static char rtc_name[] = "RTC";
1da177e4	73	static unsigned long periodic_count;
9b5ef64a	74	static unsigned int alarm_enabled;
2fac6674 AV	75	static int aie_irq;
2fac6674 AV	76	static int pie_irq;
1da177e4	77
0d1c6553	78	static inline time64_t read_elapsed_second(void)
1da177e4	79	{
8417eb7a	80
1da177e4	81	unsigned long first_low, first_mid, first_high;
8417eb7a	82
1da177e4 LT	83	unsigned long second_low, second_mid, second_high;
	84
	85	do {
	86	first_low = rtc1_read(ETIMELREG);
	87	first_mid = rtc1_read(ETIMEMREG);
	88	first_high = rtc1_read(ETIMEHREG);
	89	second_low = rtc1_read(ETIMELREG);
	90	second_mid = rtc1_read(ETIMEMREG);
	91	second_high = rtc1_read(ETIMEHREG);
	92	} while (first_low != second_low \|\| first_mid != second_mid \|\|
0218bcf6	93	first_high != second_high);
1da177e4	94
0d1c6553	95	return ((u64)first_high << 17) \| (first_mid << 1) \| (first_low >> 15);
1da177e4 LT	96	}
1da177e4 LT	97
0d1c6553	98	static inline void write_elapsed_second(time64_t sec)
1da177e4 LT	99	{
	100	spin_lock_irq(&rtc_lock);
	101
	102	rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
	103	rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
	104	rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
	105
	106	spin_unlock_irq(&rtc_lock);
	107	}
	108
8417eb7a	109	static int vr41xx_rtc_read_time(struct device dev, struct rtc_time time)
1da177e4	110	{
0d1c6553	111	time64_t epoch_sec, elapsed_sec;
1da177e4	112
0d1c6553	113	epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
1da177e4 LT	114	elapsed_sec = read_elapsed_second();
1da177e4 LT	115
0d1c6553	116	rtc_time64_to_tm(epoch_sec + elapsed_sec, time);
8417eb7a YY	117
8417eb7a YY	118	return 0;
1da177e4 LT	119	}
1da177e4 LT	120
8417eb7a	121	static int vr41xx_rtc_set_time(struct device dev, struct rtc_time time)
1da177e4	122	{
0d1c6553	123	time64_t epoch_sec, current_sec;
1da177e4	124
0d1c6553	125	epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
89e27ce4	126	current_sec = rtc_tm_to_time64(time);
1da177e4 LT	127
1da177e4 LT	128	write_elapsed_second(current_sec - epoch_sec);
8417eb7a YY	129
8417eb7a YY	130	return 0;
1da177e4 LT	131	}
1da177e4 LT	132
8417eb7a	133	static int vr41xx_rtc_read_alarm(struct device dev, struct rtc_wkalrm wkalrm)
1da177e4	134	{
8417eb7a YY	135	unsigned long low, mid, high;
8417eb7a YY	136	struct rtc_time *time = &wkalrm->time;
1da177e4	137
8417eb7a	138	spin_lock_irq(&rtc_lock);
1da177e4	139
8417eb7a YY	140	low = rtc1_read(ECMPLREG);
	141	mid = rtc1_read(ECMPMREG);
	142	high = rtc1_read(ECMPHREG);
9b5ef64a	143	wkalrm->enabled = alarm_enabled;
1da177e4	144
8417eb7a	145	spin_unlock_irq(&rtc_lock);
1da177e4	146
89e27ce4	147	rtc_time64_to_tm((high << 17) \| (mid << 1) \| (low >> 15), time);
1da177e4	148
8417eb7a YY	149	return 0;
8417eb7a YY	150	}
1da177e4	151
8417eb7a YY	152	static int vr41xx_rtc_set_alarm(struct device dev, struct rtc_wkalrm wkalrm)
8417eb7a YY	153	{
0d1c6553	154	time64_t alarm_sec;
1da177e4	155
89e27ce4	156	alarm_sec = rtc_tm_to_time64(&wkalrm->time);
1da177e4	157
8417eb7a	158	spin_lock_irq(&rtc_lock);
1da177e4	159
9b5ef64a	160	if (alarm_enabled)
bd076509	161	disable_irq(aie_irq);
9b5ef64a	162
8417eb7a YY	163	rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
	164	rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
	165	rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
1da177e4	166
9b5ef64a	167	if (wkalrm->enabled)
bd076509	168	enable_irq(aie_irq);
9b5ef64a YY	169
	170	alarm_enabled = wkalrm->enabled;
	171
8417eb7a	172	spin_unlock_irq(&rtc_lock);
1da177e4 LT	173
	174	return 0;
	175	}
	176
4cad4431 YY	177	static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
4cad4431 YY	178	{
1da177e4	179	switch (cmd) {
1da177e4 LT	180	case RTC_EPOCH_READ:
	181	return put_user(epoch, (unsigned long __user *)arg);
	182	case RTC_EPOCH_SET:
	183	/* Doesn't support before 1900 */
	184	if (arg < 1900)
	185	return -EINVAL;
1da177e4 LT	186	epoch = arg;
	187	break;
	188	default:
b3969e58	189	return -ENOIOCTLCMD;
1da177e4 LT	190	}
	191
	192	return 0;
	193	}
	194
16380c15 JS	195	static int vr41xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	196	{
	197	spin_lock_irq(&rtc_lock);
	198	if (enabled) {
	199	if (!alarm_enabled) {
	200	enable_irq(aie_irq);
	201	alarm_enabled = 1;
	202	}
	203	} else {
	204	if (alarm_enabled) {
	205	disable_irq(aie_irq);
	206	alarm_enabled = 0;
	207	}
	208	}
	209	spin_unlock_irq(&rtc_lock);
	210	return 0;
	211	}
	212
7d12e780	213	static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
1da177e4	214	{
8417eb7a YY	215	struct platform_device pdev = (struct platform_device )dev_id;
8417eb7a YY	216	struct rtc_device *rtc = platform_get_drvdata(pdev);
1da177e4	217
8417eb7a	218	rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
1da177e4	219
ab6a2d70	220	rtc_update_irq(rtc, 1, RTC_AF);
1da177e4 LT	221
	222	return IRQ_HANDLED;
	223	}
	224
7d12e780	225	static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
1da177e4	226	{
8417eb7a YY	227	struct platform_device pdev = (struct platform_device )dev_id;
8417eb7a YY	228	struct rtc_device *rtc = platform_get_drvdata(pdev);
1da177e4 LT	229	unsigned long count = periodic_count;
1da177e4 LT	230
1da177e4 LT	231	rtc2_write(RTCINTREG, RTCLONG1_INT);
	232
	233	rtc1_write(RTCL1LREG, count);
	234	rtc1_write(RTCL1HREG, count >> 16);
	235
ab6a2d70	236	rtc_update_irq(rtc, 1, RTC_PF);
1da177e4 LT	237
	238	return IRQ_HANDLED;
	239	}
	240
ff8371ac	241	static const struct rtc_class_ops vr41xx_rtc_ops = {
a25f4a95 GU	242	.ioctl = vr41xx_rtc_ioctl,
	243	.read_time = vr41xx_rtc_read_time,
	244	.set_time = vr41xx_rtc_set_time,
	245	.read_alarm = vr41xx_rtc_read_alarm,
	246	.set_alarm = vr41xx_rtc_set_alarm,
	247	.alarm_irq_enable = vr41xx_rtc_alarm_irq_enable,
1da177e4 LT	248	};
1da177e4 LT	249
5a167f45	250	static int rtc_probe(struct platform_device *pdev)
1da177e4	251	{
bd076509	252	struct resource *res;
8417eb7a	253	struct rtc_device *rtc;
1da177e4 LT	254	int retval;
1da177e4 LT	255
bd076509	256	if (pdev->num_resources != 4)
1da177e4 LT	257	return -EBUSY;
1da177e4 LT	258
bd076509 YY	259	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
bd076509 YY	260	if (!res)
1da177e4 LT	261	return -EBUSY;
1da177e4 LT	262
bf6ce1a1	263	rtc1_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
bd076509	264	if (!rtc1_base)
1da177e4	265	return -EBUSY;
bd076509 YY	266
	267	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	268	if (!res) {
	269	retval = -EBUSY;
	270	goto err_rtc1_iounmap;
	271	}
	272
bf6ce1a1	273	rtc2_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
bd076509 YY	274	if (!rtc2_base) {
	275	retval = -EBUSY;
	276	goto err_rtc1_iounmap;
1da177e4 LT	277	}
1da177e4 LT	278
9a99247c	279	rtc = devm_rtc_allocate_device(&pdev->dev);
8417eb7a	280	if (IS_ERR(rtc)) {
bd076509 YY	281	retval = PTR_ERR(rtc);
bd076509 YY	282	goto err_iounmap_all;
1da177e4 LT	283	}
1da177e4 LT	284
9a99247c AB	285	rtc->ops = &vr41xx_rtc_ops;
9a99247c AB	286
30d7891a AB	287	/* 48-bit counter at 32.768 kHz */
30d7891a AB	288	rtc->range_max = (1ULL << 33) - 1;
4cad4431 YY	289	rtc->max_user_freq = MAX_PERIODIC_RATE;
4cad4431 YY	290
1da177e4 LT	291	spin_lock_irq(&rtc_lock);
	292
	293	rtc1_write(ECMPLREG, 0);
	294	rtc1_write(ECMPMREG, 0);
	295	rtc1_write(ECMPHREG, 0);
	296	rtc1_write(RTCL1LREG, 0);
	297	rtc1_write(RTCL1HREG, 0);
	298
1da177e4 LT	299	spin_unlock_irq(&rtc_lock);
1da177e4 LT	300
bd076509	301	aie_irq = platform_get_irq(pdev, 0);
2fac6674	302	if (aie_irq <= 0) {
bd076509	303	retval = -EBUSY;
bf6ce1a1	304	goto err_iounmap_all;
1da177e4 LT	305	}
1da177e4 LT	306
bf6ce1a1 JH	307	retval = devm_request_irq(&pdev->dev, aie_irq, elapsedtime_interrupt, 0,
bf6ce1a1 JH	308	"elapsed_time", pdev);
bd076509	309	if (retval < 0)
bf6ce1a1	310	goto err_iounmap_all;
bd076509 YY	311
bd076509 YY	312	pie_irq = platform_get_irq(pdev, 1);
812f1478 WY	313	if (pie_irq <= 0) {
812f1478 WY	314	retval = -EBUSY;
bf6ce1a1	315	goto err_iounmap_all;
812f1478	316	}
bd076509	317
bf6ce1a1 JH	318	retval = devm_request_irq(&pdev->dev, pie_irq, rtclong1_interrupt, 0,
bf6ce1a1 JH	319	"rtclong1", pdev);
bd076509	320	if (retval < 0)
bf6ce1a1	321	goto err_iounmap_all;
1da177e4	322
8417eb7a YY	323	platform_set_drvdata(pdev, rtc);
8417eb7a YY	324
bd076509 YY	325	disable_irq(aie_irq);
bd076509 YY	326	disable_irq(pie_irq);
1da177e4	327
d75dcd33	328	dev_info(&pdev->dev, "Real Time Clock of NEC VR4100 series\n");
1da177e4	329
9a99247c AB	330	retval = rtc_register_device(rtc);
	331	if (retval)
	332	goto err_iounmap_all;
	333
1da177e4	334	return 0;
bd076509	335
bd076509	336	err_iounmap_all:
bd076509 YY	337	rtc2_base = NULL;
	338
	339	err_rtc1_iounmap:
bd076509 YY	340	rtc1_base = NULL;
	341
	342	return retval;
1da177e4 LT	343	}
1da177e4 LT	344
ad28a07b KS	345	/* work with hotplug and coldplug */
	346	MODULE_ALIAS("platform:RTC");
	347
8417eb7a	348	static struct platform_driver rtc_platform_driver = {
1da177e4	349	.probe = rtc_probe,
3ae5eaec RK	350	.driver = {
	351	.name = rtc_name,
	352	},
1da177e4 LT	353	};
1da177e4 LT	354
0c4eae66	355	module_platform_driver(rtc_platform_driver);