[linux-block.git] / drivers / rtc / rtc-vr41xx.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  Driver for NEC VR4100 series Real Time Clock unit.
 *
 *  Copyright (C) 2003-2008  Yoichi Yuasa <yuasa@linux-mips.org>
 */
#include <linux/compat.h>
#include <linux/err.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/platform_device.h>
#include <linux/rtc.h>
#include <linux/spinlock.h>
#include <linux/types.h>
#include <linux/uaccess.h>
#include <linux/log2.h>

#include <asm/div64.h>

MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
MODULE_LICENSE("GPL v2");

/* RTC 1 registers */
#define ETIMELREG		0x00
#define ETIMEMREG		0x02
#define ETIMEHREG		0x04
/* RFU */
#define ECMPLREG		0x08
#define ECMPMREG		0x0a
#define ECMPHREG		0x0c
/* RFU */
#define RTCL1LREG		0x10
#define RTCL1HREG		0x12
#define RTCL1CNTLREG		0x14
#define RTCL1CNTHREG		0x16
#define RTCL2LREG		0x18
#define RTCL2HREG		0x1a
#define RTCL2CNTLREG		0x1c
#define RTCL2CNTHREG		0x1e

/* RTC 2 registers */
#define TCLKLREG		0x00
#define TCLKHREG		0x02
#define TCLKCNTLREG		0x04
#define TCLKCNTHREG		0x06
/* RFU */
#define RTCINTREG		0x1e
 #define TCLOCK_INT		0x08
 #define RTCLONG2_INT		0x04
 #define RTCLONG1_INT		0x02
 #define ELAPSEDTIME_INT	0x01

#define RTC_FREQUENCY		32768
#define MAX_PERIODIC_RATE	6553

static void __iomem *rtc1_base;
static void __iomem *rtc2_base;

#define rtc1_read(offset)		readw(rtc1_base + (offset))
#define rtc1_write(offset, value)	writew((value), rtc1_base + (offset))

#define rtc2_read(offset)		readw(rtc2_base + (offset))
#define rtc2_write(offset, value)	writew((value), rtc2_base + (offset))

/* 32-bit compat for ioctls that nobody else uses */
#define RTC_EPOCH_READ32	_IOR('p', 0x0d, __u32)

static unsigned long epoch = 1970;	/* Jan 1 1970 00:00:00 */

static DEFINE_SPINLOCK(rtc_lock);
static char rtc_name[] = "RTC";
static unsigned long periodic_count;
static unsigned int alarm_enabled;
static int aie_irq;
static int pie_irq;

static inline time64_t read_elapsed_second(void)
{

	unsigned long first_low, first_mid, first_high;

	unsigned long second_low, second_mid, second_high;

	do {
		first_low = rtc1_read(ETIMELREG);
		first_mid = rtc1_read(ETIMEMREG);
		first_high = rtc1_read(ETIMEHREG);
		second_low = rtc1_read(ETIMELREG);
		second_mid = rtc1_read(ETIMEMREG);
		second_high = rtc1_read(ETIMEHREG);
	} while (first_low != second_low || first_mid != second_mid ||
		 first_high != second_high);

	return ((u64)first_high << 17) | (first_mid << 1) | (first_low >> 15);
}

static inline void write_elapsed_second(time64_t sec)
{
	spin_lock_irq(&rtc_lock);

	rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
	rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
	rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));

	spin_unlock_irq(&rtc_lock);
}

static int vr41xx_rtc_read_time(struct device *dev, struct rtc_time *time)
{
	time64_t epoch_sec, elapsed_sec;

	epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
	elapsed_sec = read_elapsed_second();

	rtc_time64_to_tm(epoch_sec + elapsed_sec, time);

	return 0;
}

static int vr41xx_rtc_set_time(struct device *dev, struct rtc_time *time)
{
	time64_t epoch_sec, current_sec;

	epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
	current_sec = rtc_tm_to_time64(time);

	write_elapsed_second(current_sec - epoch_sec);

	return 0;
}

static int vr41xx_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
	unsigned long low, mid, high;
	struct rtc_time *time = &wkalrm->time;

	spin_lock_irq(&rtc_lock);

	low = rtc1_read(ECMPLREG);
	mid = rtc1_read(ECMPMREG);
	high = rtc1_read(ECMPHREG);
	wkalrm->enabled = alarm_enabled;

	spin_unlock_irq(&rtc_lock);

	rtc_time64_to_tm((high << 17) | (mid << 1) | (low >> 15), time);

	return 0;
}

static int vr41xx_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *wkalrm)
{
	time64_t alarm_sec;

	alarm_sec = rtc_tm_to_time64(&wkalrm->time);

	spin_lock_irq(&rtc_lock);

	if (alarm_enabled)
		disable_irq(aie_irq);

	rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
	rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
	rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));

	if (wkalrm->enabled)
		enable_irq(aie_irq);

	alarm_enabled = wkalrm->enabled;

	spin_unlock_irq(&rtc_lock);

	return 0;
}

static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
{
	switch (cmd) {
	case RTC_EPOCH_READ:
		return put_user(epoch, (unsigned long __user *)arg);
#ifdef CONFIG_64BIT
	case RTC_EPOCH_READ32:
		return put_user(epoch, (unsigned int __user *)arg);
#endif
	case RTC_EPOCH_SET:
		/* Doesn't support before 1900 */
		if (arg < 1900)
			return -EINVAL;
		epoch = arg;
		break;
	default:
		return -ENOIOCTLCMD;
	}

	return 0;
}

static int vr41xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
{
	spin_lock_irq(&rtc_lock);
	if (enabled) {
		if (!alarm_enabled) {
			enable_irq(aie_irq);
			alarm_enabled = 1;
		}
	} else {
		if (alarm_enabled) {
			disable_irq(aie_irq);
			alarm_enabled = 0;
		}
	}
	spin_unlock_irq(&rtc_lock);
	return 0;
}

static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = (struct platform_device *)dev_id;
	struct rtc_device *rtc = platform_get_drvdata(pdev);

	rtc2_write(RTCINTREG, ELAPSEDTIME_INT);

	rtc_update_irq(rtc, 1, RTC_AF);

	return IRQ_HANDLED;
}

static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
{
	struct platform_device *pdev = (struct platform_device *)dev_id;
	struct rtc_device *rtc = platform_get_drvdata(pdev);
	unsigned long count = periodic_count;

	rtc2_write(RTCINTREG, RTCLONG1_INT);

	rtc1_write(RTCL1LREG, count);
	rtc1_write(RTCL1HREG, count >> 16);

	rtc_update_irq(rtc, 1, RTC_PF);

	return IRQ_HANDLED;
}

static const struct rtc_class_ops vr41xx_rtc_ops = {
	.ioctl			= vr41xx_rtc_ioctl,
	.read_time		= vr41xx_rtc_read_time,
	.set_time		= vr41xx_rtc_set_time,
	.read_alarm		= vr41xx_rtc_read_alarm,
	.set_alarm		= vr41xx_rtc_set_alarm,
	.alarm_irq_enable	= vr41xx_rtc_alarm_irq_enable,
};

static int rtc_probe(struct platform_device *pdev)
{
	struct resource *res;
	struct rtc_device *rtc;
	int retval;

	if (pdev->num_resources != 4)
		return -EBUSY;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!res)
		return -EBUSY;

	rtc1_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
	if (!rtc1_base)
		return -EBUSY;

	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (!res) {
		retval = -EBUSY;
		goto err_rtc1_iounmap;
	}

	rtc2_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
	if (!rtc2_base) {
		retval = -EBUSY;
		goto err_rtc1_iounmap;
	}

	rtc = devm_rtc_allocate_device(&pdev->dev);
	if (IS_ERR(rtc)) {
		retval = PTR_ERR(rtc);
		goto err_iounmap_all;
	}

	rtc->ops = &vr41xx_rtc_ops;

	/* 48-bit counter at 32.768 kHz */
	rtc->range_max = (1ULL << 33) - 1;
	rtc->max_user_freq = MAX_PERIODIC_RATE;

	spin_lock_irq(&rtc_lock);

	rtc1_write(ECMPLREG, 0);
	rtc1_write(ECMPMREG, 0);
	rtc1_write(ECMPHREG, 0);
	rtc1_write(RTCL1LREG, 0);
	rtc1_write(RTCL1HREG, 0);

	spin_unlock_irq(&rtc_lock);

	aie_irq = platform_get_irq(pdev, 0);
	if (aie_irq <= 0) {
		retval = -EBUSY;
		goto err_iounmap_all;
	}

	retval = devm_request_irq(&pdev->dev, aie_irq, elapsedtime_interrupt, 0,
				"elapsed_time", pdev);
	if (retval < 0)
		goto err_iounmap_all;

	pie_irq = platform_get_irq(pdev, 1);
	if (pie_irq <= 0) {
		retval = -EBUSY;
		goto err_iounmap_all;
	}

	retval = devm_request_irq(&pdev->dev, pie_irq, rtclong1_interrupt, 0,
				"rtclong1", pdev);
	if (retval < 0)
		goto err_iounmap_all;

	platform_set_drvdata(pdev, rtc);

	disable_irq(aie_irq);
	disable_irq(pie_irq);

	dev_info(&pdev->dev, "Real Time Clock of NEC VR4100 series\n");

	retval = devm_rtc_register_device(rtc);
	if (retval)
		goto err_iounmap_all;

	return 0;

err_iounmap_all:
	rtc2_base = NULL;

err_rtc1_iounmap:
	rtc1_base = NULL;

	return retval;
}

/* work with hotplug and coldplug */
MODULE_ALIAS("platform:RTC");

static struct platform_driver rtc_platform_driver = {
	.probe		= rtc_probe,
	.driver		= {
		.name	= rtc_name,
	},
};

module_platform_driver(rtc_platform_driver);
Commit	Line	Data
1a59d1b8	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4	2	/*
8417eb7a	3	* Driver for NEC VR4100 series Real Time Clock unit.
1da177e4	4	*
ada8e951	5	* Copyright (C) 2003-2008 Yoichi Yuasa <yuasa@linux-mips.org>
1da177e4	6	*/
076ff658	7	#include <linux/compat.h>
bd076509	8	#include <linux/err.h>
1da177e4 LT	9	#include <linux/fs.h>
1da177e4 LT	10	#include <linux/init.h>
4271e7ff	11	#include <linux/io.h>
1da177e4	12	#include <linux/ioport.h>
bd076509	13	#include <linux/interrupt.h>
1da177e4	14	#include <linux/module.h>
8417eb7a	15	#include <linux/platform_device.h>
1da177e4 LT	16	#include <linux/rtc.h>
	17	#include <linux/spinlock.h>
	18	#include <linux/types.h>
4271e7ff	19	#include <linux/uaccess.h>
5d2a5037	20	#include <linux/log2.h>
1da177e4 LT	21
1da177e4 LT	22	#include <asm/div64.h>
1da177e4	23
ada8e951	24	MODULE_AUTHOR("Yoichi Yuasa <yuasa@linux-mips.org>");
1da177e4	25	MODULE_DESCRIPTION("NEC VR4100 series RTC driver");
4cad4431	26	MODULE_LICENSE("GPL v2");
1da177e4	27
1da177e4 LT	28	/* RTC 1 registers */
	29	#define ETIMELREG 0x00
	30	#define ETIMEMREG 0x02
	31	#define ETIMEHREG 0x04
	32	/* RFU */
	33	#define ECMPLREG 0x08
	34	#define ECMPMREG 0x0a
	35	#define ECMPHREG 0x0c
	36	/* RFU */
	37	#define RTCL1LREG 0x10
	38	#define RTCL1HREG 0x12
	39	#define RTCL1CNTLREG 0x14
	40	#define RTCL1CNTHREG 0x16
	41	#define RTCL2LREG 0x18
	42	#define RTCL2HREG 0x1a
	43	#define RTCL2CNTLREG 0x1c
	44	#define RTCL2CNTHREG 0x1e
	45
	46	/* RTC 2 registers */
	47	#define TCLKLREG 0x00
	48	#define TCLKHREG 0x02
	49	#define TCLKCNTLREG 0x04
	50	#define TCLKCNTHREG 0x06
	51	/* RFU */
	52	#define RTCINTREG 0x1e
	53	#define TCLOCK_INT 0x08
	54	#define RTCLONG2_INT 0x04
	55	#define RTCLONG1_INT 0x02
	56	#define ELAPSEDTIME_INT 0x01
	57
	58	#define RTC_FREQUENCY 32768
	59	#define MAX_PERIODIC_RATE 6553
1da177e4 LT	60
	61	static void __iomem *rtc1_base;
	62	static void __iomem *rtc2_base;
	63
	64	#define rtc1_read(offset) readw(rtc1_base + (offset))
	65	#define rtc1_write(offset, value) writew((value), rtc1_base + (offset))
	66
	67	#define rtc2_read(offset) readw(rtc2_base + (offset))
	68	#define rtc2_write(offset, value) writew((value), rtc2_base + (offset))
	69
076ff658 AB	70	/* 32-bit compat for ioctls that nobody else uses */
	71	#define RTC_EPOCH_READ32 _IOR('p', 0x0d, __u32)
	72
1da177e4 LT	73	static unsigned long epoch = 1970; /* Jan 1 1970 00:00:00 */
1da177e4 LT	74
34af946a	75	static DEFINE_SPINLOCK(rtc_lock);
1da177e4	76	static char rtc_name[] = "RTC";
1da177e4	77	static unsigned long periodic_count;
9b5ef64a	78	static unsigned int alarm_enabled;
2fac6674 AV	79	static int aie_irq;
2fac6674 AV	80	static int pie_irq;
1da177e4	81
0d1c6553	82	static inline time64_t read_elapsed_second(void)
1da177e4	83	{
8417eb7a	84
1da177e4	85	unsigned long first_low, first_mid, first_high;
8417eb7a	86
1da177e4 LT	87	unsigned long second_low, second_mid, second_high;
	88
	89	do {
	90	first_low = rtc1_read(ETIMELREG);
	91	first_mid = rtc1_read(ETIMEMREG);
	92	first_high = rtc1_read(ETIMEHREG);
	93	second_low = rtc1_read(ETIMELREG);
	94	second_mid = rtc1_read(ETIMEMREG);
	95	second_high = rtc1_read(ETIMEHREG);
	96	} while (first_low != second_low \|\| first_mid != second_mid \|\|
0218bcf6	97	first_high != second_high);
1da177e4	98
0d1c6553	99	return ((u64)first_high << 17) \| (first_mid << 1) \| (first_low >> 15);
1da177e4 LT	100	}
1da177e4 LT	101
0d1c6553	102	static inline void write_elapsed_second(time64_t sec)
1da177e4 LT	103	{
	104	spin_lock_irq(&rtc_lock);
	105
	106	rtc1_write(ETIMELREG, (uint16_t)(sec << 15));
	107	rtc1_write(ETIMEMREG, (uint16_t)(sec >> 1));
	108	rtc1_write(ETIMEHREG, (uint16_t)(sec >> 17));
	109
	110	spin_unlock_irq(&rtc_lock);
	111	}
	112
8417eb7a	113	static int vr41xx_rtc_read_time(struct device dev, struct rtc_time time)
1da177e4	114	{
0d1c6553	115	time64_t epoch_sec, elapsed_sec;
1da177e4	116
0d1c6553	117	epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
1da177e4 LT	118	elapsed_sec = read_elapsed_second();
1da177e4 LT	119
0d1c6553	120	rtc_time64_to_tm(epoch_sec + elapsed_sec, time);
8417eb7a YY	121
8417eb7a YY	122	return 0;
1da177e4 LT	123	}
1da177e4 LT	124
8417eb7a	125	static int vr41xx_rtc_set_time(struct device dev, struct rtc_time time)
1da177e4	126	{
0d1c6553	127	time64_t epoch_sec, current_sec;
1da177e4	128
0d1c6553	129	epoch_sec = mktime64(epoch, 1, 1, 0, 0, 0);
89e27ce4	130	current_sec = rtc_tm_to_time64(time);
1da177e4 LT	131
1da177e4 LT	132	write_elapsed_second(current_sec - epoch_sec);
8417eb7a YY	133
8417eb7a YY	134	return 0;
1da177e4 LT	135	}
1da177e4 LT	136
8417eb7a	137	static int vr41xx_rtc_read_alarm(struct device dev, struct rtc_wkalrm wkalrm)
1da177e4	138	{
8417eb7a YY	139	unsigned long low, mid, high;
8417eb7a YY	140	struct rtc_time *time = &wkalrm->time;
1da177e4	141
8417eb7a	142	spin_lock_irq(&rtc_lock);
1da177e4	143
8417eb7a YY	144	low = rtc1_read(ECMPLREG);
	145	mid = rtc1_read(ECMPMREG);
	146	high = rtc1_read(ECMPHREG);
9b5ef64a	147	wkalrm->enabled = alarm_enabled;
1da177e4	148
8417eb7a	149	spin_unlock_irq(&rtc_lock);
1da177e4	150
89e27ce4	151	rtc_time64_to_tm((high << 17) \| (mid << 1) \| (low >> 15), time);
1da177e4	152
8417eb7a YY	153	return 0;
8417eb7a YY	154	}
1da177e4	155
8417eb7a YY	156	static int vr41xx_rtc_set_alarm(struct device dev, struct rtc_wkalrm wkalrm)
8417eb7a YY	157	{
0d1c6553	158	time64_t alarm_sec;
1da177e4	159
89e27ce4	160	alarm_sec = rtc_tm_to_time64(&wkalrm->time);
1da177e4	161
8417eb7a	162	spin_lock_irq(&rtc_lock);
1da177e4	163
9b5ef64a	164	if (alarm_enabled)
bd076509	165	disable_irq(aie_irq);
9b5ef64a	166
8417eb7a YY	167	rtc1_write(ECMPLREG, (uint16_t)(alarm_sec << 15));
	168	rtc1_write(ECMPMREG, (uint16_t)(alarm_sec >> 1));
	169	rtc1_write(ECMPHREG, (uint16_t)(alarm_sec >> 17));
1da177e4	170
9b5ef64a	171	if (wkalrm->enabled)
bd076509	172	enable_irq(aie_irq);
9b5ef64a YY	173
	174	alarm_enabled = wkalrm->enabled;
	175
8417eb7a	176	spin_unlock_irq(&rtc_lock);
1da177e4 LT	177
	178	return 0;
	179	}
	180
4cad4431 YY	181	static int vr41xx_rtc_ioctl(struct device *dev, unsigned int cmd, unsigned long arg)
4cad4431 YY	182	{
1da177e4	183	switch (cmd) {
1da177e4 LT	184	case RTC_EPOCH_READ:
1da177e4 LT	185	return put_user(epoch, (unsigned long __user *)arg);
076ff658 AB	186	#ifdef CONFIG_64BIT
	187	case RTC_EPOCH_READ32:
	188	return put_user(epoch, (unsigned int __user *)arg);
	189	#endif
1da177e4 LT	190	case RTC_EPOCH_SET:
	191	/* Doesn't support before 1900 */
	192	if (arg < 1900)
	193	return -EINVAL;
1da177e4 LT	194	epoch = arg;
	195	break;
	196	default:
b3969e58	197	return -ENOIOCTLCMD;
1da177e4 LT	198	}
	199
	200	return 0;
	201	}
	202
16380c15 JS	203	static int vr41xx_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
	204	{
	205	spin_lock_irq(&rtc_lock);
	206	if (enabled) {
	207	if (!alarm_enabled) {
	208	enable_irq(aie_irq);
	209	alarm_enabled = 1;
	210	}
	211	} else {
	212	if (alarm_enabled) {
	213	disable_irq(aie_irq);
	214	alarm_enabled = 0;
	215	}
	216	}
	217	spin_unlock_irq(&rtc_lock);
	218	return 0;
	219	}
	220
7d12e780	221	static irqreturn_t elapsedtime_interrupt(int irq, void *dev_id)
1da177e4	222	{
8417eb7a YY	223	struct platform_device pdev = (struct platform_device )dev_id;
8417eb7a YY	224	struct rtc_device *rtc = platform_get_drvdata(pdev);
1da177e4	225
8417eb7a	226	rtc2_write(RTCINTREG, ELAPSEDTIME_INT);
1da177e4	227
ab6a2d70	228	rtc_update_irq(rtc, 1, RTC_AF);
1da177e4 LT	229
	230	return IRQ_HANDLED;
	231	}
	232
7d12e780	233	static irqreturn_t rtclong1_interrupt(int irq, void *dev_id)
1da177e4	234	{
8417eb7a YY	235	struct platform_device pdev = (struct platform_device )dev_id;
8417eb7a YY	236	struct rtc_device *rtc = platform_get_drvdata(pdev);
1da177e4 LT	237	unsigned long count = periodic_count;
1da177e4 LT	238
1da177e4 LT	239	rtc2_write(RTCINTREG, RTCLONG1_INT);
	240
	241	rtc1_write(RTCL1LREG, count);
	242	rtc1_write(RTCL1HREG, count >> 16);
	243
ab6a2d70	244	rtc_update_irq(rtc, 1, RTC_PF);
1da177e4 LT	245
	246	return IRQ_HANDLED;
	247	}
	248
ff8371ac	249	static const struct rtc_class_ops vr41xx_rtc_ops = {
a25f4a95 GU	250	.ioctl = vr41xx_rtc_ioctl,
	251	.read_time = vr41xx_rtc_read_time,
	252	.set_time = vr41xx_rtc_set_time,
	253	.read_alarm = vr41xx_rtc_read_alarm,
	254	.set_alarm = vr41xx_rtc_set_alarm,
	255	.alarm_irq_enable = vr41xx_rtc_alarm_irq_enable,
1da177e4 LT	256	};
1da177e4 LT	257
5a167f45	258	static int rtc_probe(struct platform_device *pdev)
1da177e4	259	{
bd076509	260	struct resource *res;
8417eb7a	261	struct rtc_device *rtc;
1da177e4 LT	262	int retval;
1da177e4 LT	263
bd076509	264	if (pdev->num_resources != 4)
1da177e4 LT	265	return -EBUSY;
1da177e4 LT	266
bd076509 YY	267	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
bd076509 YY	268	if (!res)
1da177e4 LT	269	return -EBUSY;
1da177e4 LT	270
bf6ce1a1	271	rtc1_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
bd076509	272	if (!rtc1_base)
1da177e4	273	return -EBUSY;
bd076509 YY	274
	275	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	276	if (!res) {
	277	retval = -EBUSY;
	278	goto err_rtc1_iounmap;
	279	}
	280
bf6ce1a1	281	rtc2_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
bd076509 YY	282	if (!rtc2_base) {
	283	retval = -EBUSY;
	284	goto err_rtc1_iounmap;
1da177e4 LT	285	}
1da177e4 LT	286
9a99247c	287	rtc = devm_rtc_allocate_device(&pdev->dev);
8417eb7a	288	if (IS_ERR(rtc)) {
bd076509 YY	289	retval = PTR_ERR(rtc);
bd076509 YY	290	goto err_iounmap_all;
1da177e4 LT	291	}
1da177e4 LT	292
9a99247c AB	293	rtc->ops = &vr41xx_rtc_ops;
9a99247c AB	294
30d7891a AB	295	/* 48-bit counter at 32.768 kHz */
30d7891a AB	296	rtc->range_max = (1ULL << 33) - 1;
4cad4431 YY	297	rtc->max_user_freq = MAX_PERIODIC_RATE;
4cad4431 YY	298
1da177e4 LT	299	spin_lock_irq(&rtc_lock);
	300
	301	rtc1_write(ECMPLREG, 0);
	302	rtc1_write(ECMPMREG, 0);
	303	rtc1_write(ECMPHREG, 0);
	304	rtc1_write(RTCL1LREG, 0);
	305	rtc1_write(RTCL1HREG, 0);
	306
1da177e4 LT	307	spin_unlock_irq(&rtc_lock);
1da177e4 LT	308
bd076509	309	aie_irq = platform_get_irq(pdev, 0);
2fac6674	310	if (aie_irq <= 0) {
bd076509	311	retval = -EBUSY;
bf6ce1a1	312	goto err_iounmap_all;
1da177e4 LT	313	}
1da177e4 LT	314
bf6ce1a1 JH	315	retval = devm_request_irq(&pdev->dev, aie_irq, elapsedtime_interrupt, 0,
bf6ce1a1 JH	316	"elapsed_time", pdev);
bd076509	317	if (retval < 0)
bf6ce1a1	318	goto err_iounmap_all;
bd076509 YY	319
bd076509 YY	320	pie_irq = platform_get_irq(pdev, 1);
812f1478 WY	321	if (pie_irq <= 0) {
812f1478 WY	322	retval = -EBUSY;
bf6ce1a1	323	goto err_iounmap_all;
812f1478	324	}
bd076509	325
bf6ce1a1 JH	326	retval = devm_request_irq(&pdev->dev, pie_irq, rtclong1_interrupt, 0,
bf6ce1a1 JH	327	"rtclong1", pdev);
bd076509	328	if (retval < 0)
bf6ce1a1	329	goto err_iounmap_all;
1da177e4	330
8417eb7a YY	331	platform_set_drvdata(pdev, rtc);
8417eb7a YY	332
bd076509 YY	333	disable_irq(aie_irq);
bd076509 YY	334	disable_irq(pie_irq);
1da177e4	335
d75dcd33	336	dev_info(&pdev->dev, "Real Time Clock of NEC VR4100 series\n");
1da177e4	337
fdcfd854	338	retval = devm_rtc_register_device(rtc);
9a99247c AB	339	if (retval)
	340	goto err_iounmap_all;
	341
1da177e4	342	return 0;
bd076509	343
bd076509	344	err_iounmap_all:
bd076509 YY	345	rtc2_base = NULL;
	346
	347	err_rtc1_iounmap:
bd076509 YY	348	rtc1_base = NULL;
	349
	350	return retval;
1da177e4 LT	351	}
1da177e4 LT	352
ad28a07b KS	353	/* work with hotplug and coldplug */
	354	MODULE_ALIAS("platform:RTC");
	355
8417eb7a	356	static struct platform_driver rtc_platform_driver = {
1da177e4	357	.probe = rtc_probe,
3ae5eaec RK	358	.driver = {
	359	.name = rtc_name,
	360	},
1da177e4 LT	361	};
1da177e4 LT	362
0c4eae66	363	module_platform_driver(rtc_platform_driver);